diff --git a/.cproject b/.cproject new file mode 100644 index 0000000..da7e7b8 --- /dev/null +++ b/.cproject @@ -0,0 +1,233 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.mxproject b/.mxproject new file mode 100644 index 0000000..9965b9f --- /dev/null +++ b/.mxproject @@ -0,0 +1,34 @@ +[PreviousLibFiles] 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+HeaderPath=Middlewares\Third_Party\LwIP\src\include;Middlewares\Third_Party\LwIP\system;Middlewares\Third_Party\LwIP\src\include;Middlewares\Third_Party\LwIP\system;Drivers\STM32H7xx_HAL_Driver\Inc;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;Drivers\BSP\Components\lan8742;Middlewares\Third_Party\LwIP\src\include\netif\ppp;Drivers\CMSIS\Device\ST\STM32H7xx\Include;Middlewares\Third_Party\LwIP\src\include\lwip;Middlewares\Third_Party\LwIP\src\include\lwip\apps;Middlewares\Third_Party\LwIP\src\include\lwip\priv;Middlewares\Third_Party\LwIP\src\include\lwip\prot;Middlewares\Third_Party\LwIP\src\include\netif;Middlewares\Third_Party\LwIP\src\include\compat\posix;Middlewares\Third_Party\LwIP\src\include\compat\posix\arpa;Middlewares\Third_Party\LwIP\src\include\compat\posix\net;Middlewares\Third_Party\LwIP\src\include\compat\posix\sys;Middlewares\Third_Party\LwIP\src\include\compat\stdc;Middlewares\Third_Party\LwIP\system\arch;Drivers\CMSIS\Include;LWIP\App;LWIP\Target;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32H723xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=6 +HeaderFiles#0=..\LWIP\App\lwip.h +HeaderFiles#1=..\LWIP\Target\lwipopts.h +HeaderFiles#2=..\LWIP\Target\ethernetif.h +HeaderFiles#3=..\Core\Inc\stm32h7xx_it.h +HeaderFiles#4=..\Core\Inc\stm32h7xx_hal_conf.h +HeaderFiles#5=..\Core\Inc\main.h +HeaderFolderListSize=3 +HeaderPath#0=..\LWIP\App +HeaderPath#1=..\LWIP\Target +HeaderPath#2=..\Core\Inc +HeaderFiles=; +SourceFileListSize=5 +SourceFiles#0=..\LWIP\App\lwip.c +SourceFiles#1=..\LWIP\Target\ethernetif.c +SourceFiles#2=..\Core\Src\stm32h7xx_it.c +SourceFiles#3=..\Core\Src\stm32h7xx_hal_msp.c +SourceFiles#4=..\Core\Src\main.c +SourceFolderListSize=3 +SourcePath#0=..\LWIP\App +SourcePath#1=..\LWIP\Target +SourcePath#2=..\Core\Src +SourceFiles=; + diff --git a/.project b/.project new file mode 100644 index 0000000..ec118c4 --- /dev/null +++ b/.project @@ -0,0 +1,32 @@ + + + lwip_test + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + org.eclipse.cdt.core.cnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs b/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs new file mode 100644 index 0000000..98a69fc --- /dev/null +++ b/.settings/com.st.stm32cube.ide.mcu.sfrview.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +sfrviewstate={"fFavorites"\:{"fLists"\:{}},"fProperties"\:{"fNodeProperties"\:{}}} diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml new file mode 100644 index 0000000..68d9653 --- /dev/null +++ b/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.settings/org.eclipse.core.resources.prefs b/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..99f26c0 --- /dev/null +++ b/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs new file mode 100644 index 0000000..50c300f --- /dev/null +++ b/.settings/stm32cubeide.project.prefs @@ -0,0 +1,6 @@ +2F62501ED4689FB349E356AB974DBE57=0F380600D8D2B0DDEC8E00D7C844FF4C +635E684B79701B039C64EA45C3F84D30=591ABC0D4CC77D36A04CE6FE702D2AB0 +66BE74F758C12D739921AEA421D593D3=4 +8DF89ED150041C4CBC7CB9A9CAA90856=0F380600D8D2B0DDEC8E00D7C844FF4C +DC22A860405A8BF2F2C095E5B6529F12=3689951419DD9ED3A6AC68932BCB3771 +eclipse.preferences.version=1 diff --git a/Core/Inc/main.h b/Core/Inc/main.h new file mode 100644 index 0000000..4345c9f --- /dev/null +++ b/Core/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Core/Inc/stm32h7xx_hal_conf.h b/Core/Inc/stm32h7xx_hal_conf.h new file mode 100644 index 0000000..0b964f5 --- /dev/null +++ b/Core/Inc/stm32h7xx_hal_conf.h @@ -0,0 +1,515 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CONF_H +#define STM32H7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_FMAC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_OTFDEC_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HRTIM_MODULE_ENABLED */ +/* #define HAL_HSEM_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SWPMI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal oscillator (CSI) default value. + * This value is the default CSI value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ +#define USE_SPI_CRC 0U /*!< use CRC in SPI */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################### Ethernet Configuration ######################### */ +#define ETH_TX_DESC_CNT 4U /* number of Ethernet Tx DMA descriptors */ +#define ETH_RX_DESC_CNT 4U /* number of Ethernet Rx DMA descriptors */ + +#define ETH_MAC_ADDR0 (0x02UL) +#define ETH_MAC_ADDR1 (0x00UL) +#define ETH_MAC_ADDR2 (0x00UL) +#define ETH_MAC_ADDR3 (0x00UL) +#define ETH_MAC_ADDR4 (0x00UL) +#define ETH_MAC_ADDR5 (0x00UL) + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_MDMA_MODULE_ENABLED + #include "stm32h7xx_hal_mdma.h" +#endif /* HAL_MDMA_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32h7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32h7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32h7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32h7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32h7xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32h7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED + #include "stm32h7xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED + #include "stm32h7xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32h7xx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32h7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32h7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32h7xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32h7xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h7xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32h7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7xx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32h7xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CONF_H */ diff --git a/Core/Inc/stm32h7xx_it.h b/Core/Inc/stm32h7xx_it.h new file mode 100644 index 0000000..d0a29c7 --- /dev/null +++ b/Core/Inc/stm32h7xx_it.h @@ -0,0 +1,67 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_IT_H +#define __STM32H7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void ETH_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_IT_H */ diff --git a/Core/Src/main.c b/Core/Src/main.c new file mode 100644 index 0000000..c750c3b --- /dev/null +++ b/Core/Src/main.c @@ -0,0 +1,404 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include <_lwftp.h> +#include "main.h" +#include "lwip.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include +#include +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MPU_Config(void); +static void MX_GPIO_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +#define min(x, y) (x) < (y) ? (x) : (y) +#define max(x, y) (x) > (y) ? (x) : (y) + +int _write(int32_t file, uint8_t *ptr, int32_t len) { + for (int32_t i = 0; i < len; ++i) + ITM_SendChar(*ptr++); + return len; +} + +extern void LOG_TRACE(const char *message) { + printf("TRACE: %s \r\n", message); +} + +/* ============ LWFTP Code ============*/ +static void ftp_retr_callback(void *arg, int result) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (result != LWFTP_RESULT_OK) { + LOG_ERROR("retr failed (%d)", result); + return lwftp_close(s); + } + // Test is done + lwftp_close(s); +} + +static uint data_sink(void *arg, const char *ptr, uint len) { + static const uint mylen = 12345; + static char *const myconfig = (char*) 0x20000000; + static uint offset = 0; + + if (ptr) { + len = min(len, mylen - offset); + memcpy(myconfig + offset, ptr, len); + offset += len; + } + return len; +} + +static void ftp_stor_callback(void *arg, int result) { + lwftp_session_t *s = (lwftp_session_t*) arg; + err_t error; + + if (result != LWFTP_RESULT_OK) { + LOG_ERROR("stor failed (%d)", result); + return lwftp_close(s); + } + // Continue with RETR request + s->data_sink = data_sink; + s->done_fn = ftp_retr_callback; + s->remote_path = "configfile"; + error = lwftp_retrieve(s); + if (error != LWFTP_RESULT_INPROGRESS) { + LOG_ERROR("lwftp_retrieve failed (%d)", error); + } + // FTP session will continue with RETR and sink callbacks +} + +static uint data_source(void *arg, const char **pptr, uint maxlen) { + static const uint mylen = 12345; + static const char *const mydata = (char*) 0x20000000; + static uint offset = 0; + uint len = 0; + + // Check for data request or data sent notice + if (pptr) { + len = mylen - offset; + if (len > maxlen) + len = maxlen; + *pptr = mydata + offset; + } else { + offset += maxlen; + if (offset > mylen) + offset = mylen; + } + return len; +} + +static void ftp_connect_callback(void *arg, int result) { + lwftp_session_t *s = (lwftp_session_t*) arg; + err_t error; + if (result == LWFTP_RESULT_LOGGED) { + LOG_TRACE("login success !!!!! \r\n"); + } else { + LOG_TRACE("login failed !!!!! \r\n"); + } +// LOG_TRACE("> lwftp connect callback \r\n"); +// if (result != LWFTP_RESULT_LOGGED) { +// LOG_ERROR("login failed (%d)", result); +// return lwftp_close(s); +// } + + return + // Continue with STOR request + s->data_source = data_source; + s->done_fn = ftp_stor_callback; + s->remote_path = "logfile"; + error = lwftp_store(s); + if (error != LWFTP_RESULT_INPROGRESS) { + LOG_ERROR("lwftp_store failed (%d)", error); + } + // FTP session will continue with STOR and source callbacks +} + +static void ftp_test(void) { + static lwftp_session_t s; // static content for the whole FTP session + err_t error; + + // Initialize session data + memset(&s, 0, sizeof(s)); + + IP4_ADDR(&s.server_ip, 192, 168, 0, 100); + s.server_port = 21; + s.done_fn = ftp_connect_callback; + s.user = "anonymous"; // Anonymous client + s.pass = "space2lim@naver.com"; + // We have no extra user data, simply use the session structure + s.handle = &s; + + // Start the connection state machine + error = lwftp_connect(&s); + if (error != LWFTP_RESULT_INPROGRESS) { + LOG_ERROR("lwftp_connect failed (%d)", error); + } + // FTP session will continue with the connection callback +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) { + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MPU Configuration--------------------------------------------------------*/ + MPU_Config(); + /* Enable the CPU Cache */ + + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); + + /* Enable D-Cache---------------------------------------------------------*/ + SCB_EnableDCache(); + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_LWIP_Init(); + /* USER CODE BEGIN 2 */ + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + + /* ============ LWFTP Code ============*/ + ftp_test(); +// ftp_connect(); + + while (1) { + MX_LWIP_Process(); + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) { + } + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + RCC_OscInitStruct.PLL.PLLN = 96; + RCC_OscInitStruct.PLL.PLLP = 1; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 + | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) { + /* USER CODE BEGIN MX_GPIO_Init_1 */ + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + /* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/* MPU Configuration */ + +void MPU_Config(void) { + MPU_Region_InitTypeDef MPU_InitStruct = { 0 }; + + /* Disables the MPU */ + HAL_MPU_Disable(); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.BaseAddress = 0x0; + MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; + MPU_InitStruct.SubRegionDisable = 0x87; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER1; + MPU_InitStruct.BaseAddress = 0x30000000; + MPU_InitStruct.Size = MPU_REGION_SIZE_32KB; + MPU_InitStruct.SubRegionDisable = 0x0; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER2; + MPU_InitStruct.Size = MPU_REGION_SIZE_512B; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + /* Enables the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) { + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/Core/Src/stm32h7xx_hal_msp.c b/Core/Src/stm32h7xx_hal_msp.c new file mode 100644 index 0000000..d0a0d91 --- /dev/null +++ b/Core/Src/stm32h7xx_hal_msp.c @@ -0,0 +1,81 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/stm32h7xx_it.c b/Core/Src/stm32h7xx_it.c new file mode 100644 index 0000000..8cd685b --- /dev/null +++ b/Core/Src/stm32h7xx_it.c @@ -0,0 +1,217 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern ETH_HandleTypeDef heth; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles Ethernet global interrupt. + */ +void ETH_IRQHandler(void) +{ + /* USER CODE BEGIN ETH_IRQn 0 */ + + /* USER CODE END ETH_IRQn 0 */ + HAL_ETH_IRQHandler(&heth); + /* USER CODE BEGIN ETH_IRQn 1 */ + + /* USER CODE END ETH_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Core/Src/syscalls.c b/Core/Src/syscalls.c new file mode 100644 index 0000000..d190edf --- /dev/null +++ b/Core/Src/syscalls.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeIDE + * @brief STM32CubeIDE Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} diff --git a/Core/Src/sysmem.c b/Core/Src/sysmem.c new file mode 100644 index 0000000..921ecef --- /dev/null +++ b/Core/Src/sysmem.c @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeIDE + * @brief STM32CubeIDE System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the newlib libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} diff --git a/Core/Src/system_stm32h7xx.c b/Core/Src/system_stm32h7xx.c new file mode 100644 index 0000000..86e6784 --- /dev/null +++ b/Core/Src/system_stm32h7xx.c @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ +/* #define DATA_IN_D2_SRAM */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +#if defined(DUAL_CORE) && defined(CORE_CM4) +/*!< Uncomment the following line if you need to relocate your vector Table + in D2 AXI SRAM else user remap will be done in FLASH BANK2. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif /* VECT_TAB_SRAM */ +#else +/*!< Uncomment the following line if you need to relocate your vector Table + in D1 AXI SRAM else user remap will be done in FLASH BANK1. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif /* VECT_TAB_SRAM */ +#endif /* DUAL_CORE && CORE_CM4 */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined (DATA_IN_D2_SRAM) + __IO uint32_t tmpreg; +#endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + +#if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x02020200; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x01FF0000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } +#endif /* STM32H7_DEV_ID */ + +#if defined(DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + (void) tmpreg; +#endif /* DATA_IN_D2_SRAM */ + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#else + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#endif /*DUAL_CORE && CORE_CM4*/ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/Core/Startup/startup_stm32h723vghx.s b/Core/Startup/startup_stm32h723vghx.s new file mode 100644 index 0000000..73d8bd2 --- /dev/null +++ b/Core/Startup/startup_stm32h723vghx.s @@ -0,0 +1,756 @@ +/** + ****************************************************************************** + * @file startup_stm32h723xx.s + * @author MCD Application Team + * @brief STM32H723xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word 0 /* Reserved */ + .word OCTOSPI1_IRQHandler /* OCTOSPI1 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word 0 /* Reserved */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word 0 /* Reserved */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word DTS_IRQHandler /* Digital Temperature Sensor interrupt */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .word OCTOSPI2_IRQHandler /* OCTOSPI2 Interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMAC_IRQHandler /* FMAC Interrupt */ + .word CORDIC_IRQHandler /* CORDIC Interrupt */ + .word UART9_IRQHandler /* UART9 Interrupt */ + .word USART10_IRQHandler /* UART10 Interrupt */ + .word I2C5_EV_IRQHandler /* I2C5 Event Interrupt */ + .word I2C5_ER_IRQHandler /* I2C5 Error Interrupt */ + .word FDCAN3_IT0_IRQHandler /* FDCAN3 interrupt line 0 */ + .word FDCAN3_IT1_IRQHandler /* FDCAN3 interrupt line 1 */ + .word TIM23_IRQHandler /* TIM23 global interrupt */ + .word TIM24_IRQHandler /* TIM24 global interrupt */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak FMAC_IRQHandler + .thumb_set FMAC_IRQHandler,Default_Handler + + .weak CORDIC_IRQHandler + .thumb_set CORDIC_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak I2C5_EV_IRQHandler + .thumb_set I2C5_EV_IRQHandler,Default_Handler + + .weak I2C5_ER_IRQHandler + .thumb_set I2C5_ER_IRQHandler,Default_Handler + + .weak FDCAN3_IT0_IRQHandler + .thumb_set FDCAN3_IT0_IRQHandler,Default_Handler + + .weak FDCAN3_IT1_IRQHandler + .thumb_set FDCAN3_IT1_IRQHandler,Default_Handler + + .weak TIM23_IRQHandler + .thumb_set TIM23_IRQHandler,Default_Handler + + .weak TIM24_IRQHandler + .thumb_set TIM24_IRQHandler,Default_Handler + + diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo new file mode 100644 index 0000000..738202f --- /dev/null +++ b/Debug/Core/Src/main.cyclo @@ -0,0 +1,14 @@ +../Drivers/CMSIS/Include/core_cm7.h:2660:26:ITM_SendChar 4 +../Core/Src/main.c:64:5:_write 2 +../Core/Src/main.c:78:13:LOG_TRACE 1 +../Core/Src/main.c:83:13:ftp_retr_callback 2 +../Core/Src/main.c:94:13:data_sink 2 +../Core/Src/main.c:107:13:ftp_stor_callback 3 +../Core/Src/main.c:126:13:data_source 4 +../Core/Src/main.c:146:13:ftp_connect_callback 2 +../Core/Src/main.c:172:13:ftp_test 2 +../Core/Src/main.c:201:5:main 5 +../Core/Src/main.c:259:6:SystemClock_Config 4 +../Core/Src/main.c:316:13:MX_GPIO_Init 1 +../Core/Src/main.c:336:6:MPU_Config 1 +../Core/Src/main.c:388:6:Error_Handler 1 diff --git a/Debug/Core/Src/main.d b/Debug/Core/Src/main.d new file mode 100644 index 0000000..71a8c41 --- /dev/null +++ b/Debug/Core/Src/main.d @@ -0,0 +1,133 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../LWIP/App/lwip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../LWIP/Target/ethernetif.h C:/_NoSleep/STM32/lwip_test/LWFTP/lwftp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../LWIP/App/lwip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../LWIP/Target/ethernetif.h: +C:/_NoSleep/STM32/lwip_test/LWFTP/lwftp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o new file mode 100644 index 0000000..72c67e2 Binary files /dev/null and b/Debug/Core/Src/main.o differ diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su new file mode 100644 index 0000000..4774449 --- /dev/null +++ b/Debug/Core/Src/main.su @@ -0,0 +1,14 @@ +../Drivers/CMSIS/Include/core_cm7.h:2660:26:ITM_SendChar 16 static,ignoring_inline_asm +../Core/Src/main.c:64:5:_write 32 static +../Core/Src/main.c:78:13:LOG_TRACE 16 static +../Core/Src/main.c:83:13:ftp_retr_callback 24 static +../Core/Src/main.c:94:13:data_sink 24 static +../Core/Src/main.c:107:13:ftp_stor_callback 24 static +../Core/Src/main.c:126:13:data_source 32 static +../Core/Src/main.c:146:13:ftp_connect_callback 24 static +../Core/Src/main.c:172:13:ftp_test 16 static +../Core/Src/main.c:201:5:main 24 static,ignoring_inline_asm +../Core/Src/main.c:259:6:SystemClock_Config 120 static +../Core/Src/main.c:316:13:MX_GPIO_Init 24 static +../Core/Src/main.c:336:6:MPU_Config 24 static +../Core/Src/main.c:388:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.cyclo b/Debug/Core/Src/stm32h7xx_hal_msp.cyclo new file mode 100644 index 0000000..5590235 --- /dev/null +++ b/Debug/Core/Src/stm32h7xx_hal_msp.cyclo @@ -0,0 +1 @@ +../Core/Src/stm32h7xx_hal_msp.c:64:6:HAL_MspInit 1 diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.d b/Debug/Core/Src/stm32h7xx_hal_msp.d new file mode 100644 index 0000000..1f1339d --- /dev/null +++ b/Debug/Core/Src/stm32h7xx_hal_msp.d @@ -0,0 +1,62 @@ +Core/Src/stm32h7xx_hal_msp.o: ../Core/Src/stm32h7xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.o b/Debug/Core/Src/stm32h7xx_hal_msp.o new file mode 100644 index 0000000..2282ea6 Binary files /dev/null and b/Debug/Core/Src/stm32h7xx_hal_msp.o differ diff --git a/Debug/Core/Src/stm32h7xx_hal_msp.su b/Debug/Core/Src/stm32h7xx_hal_msp.su new file mode 100644 index 0000000..8061c9c --- /dev/null +++ b/Debug/Core/Src/stm32h7xx_hal_msp.su @@ -0,0 +1 @@ +../Core/Src/stm32h7xx_hal_msp.c:64:6:HAL_MspInit 16 static diff --git a/Debug/Core/Src/stm32h7xx_it.cyclo b/Debug/Core/Src/stm32h7xx_it.cyclo new file mode 100644 index 0000000..9b41ae6 --- /dev/null +++ b/Debug/Core/Src/stm32h7xx_it.cyclo @@ -0,0 +1,10 @@ +../Core/Src/stm32h7xx_it.c:69:6:NMI_Handler 1 +../Core/Src/stm32h7xx_it.c:84:6:HardFault_Handler 1 +../Core/Src/stm32h7xx_it.c:99:6:MemManage_Handler 1 +../Core/Src/stm32h7xx_it.c:114:6:BusFault_Handler 1 +../Core/Src/stm32h7xx_it.c:129:6:UsageFault_Handler 1 +../Core/Src/stm32h7xx_it.c:144:6:SVC_Handler 1 +../Core/Src/stm32h7xx_it.c:157:6:DebugMon_Handler 1 +../Core/Src/stm32h7xx_it.c:170:6:PendSV_Handler 1 +../Core/Src/stm32h7xx_it.c:183:6:SysTick_Handler 1 +../Core/Src/stm32h7xx_it.c:204:6:ETH_IRQHandler 1 diff --git a/Debug/Core/Src/stm32h7xx_it.d b/Debug/Core/Src/stm32h7xx_it.d new file mode 100644 index 0000000..14d76bd --- /dev/null +++ b/Debug/Core/Src/stm32h7xx_it.d @@ -0,0 +1,64 @@ +Core/Src/stm32h7xx_it.o: ../Core/Src/stm32h7xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Core/Inc/stm32h7xx_it.h +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Core/Inc/stm32h7xx_it.h: diff --git a/Debug/Core/Src/stm32h7xx_it.o b/Debug/Core/Src/stm32h7xx_it.o new file mode 100644 index 0000000..ca8405d Binary files /dev/null and b/Debug/Core/Src/stm32h7xx_it.o differ diff --git a/Debug/Core/Src/stm32h7xx_it.su b/Debug/Core/Src/stm32h7xx_it.su new file mode 100644 index 0000000..bda5435 --- /dev/null +++ b/Debug/Core/Src/stm32h7xx_it.su @@ -0,0 +1,10 @@ +../Core/Src/stm32h7xx_it.c:69:6:NMI_Handler 4 static +../Core/Src/stm32h7xx_it.c:84:6:HardFault_Handler 4 static +../Core/Src/stm32h7xx_it.c:99:6:MemManage_Handler 4 static +../Core/Src/stm32h7xx_it.c:114:6:BusFault_Handler 4 static +../Core/Src/stm32h7xx_it.c:129:6:UsageFault_Handler 4 static +../Core/Src/stm32h7xx_it.c:144:6:SVC_Handler 4 static +../Core/Src/stm32h7xx_it.c:157:6:DebugMon_Handler 4 static +../Core/Src/stm32h7xx_it.c:170:6:PendSV_Handler 4 static +../Core/Src/stm32h7xx_it.c:183:6:SysTick_Handler 8 static +../Core/Src/stm32h7xx_it.c:204:6:ETH_IRQHandler 8 static diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..342b87a --- /dev/null +++ b/Debug/Core/Src/subdir.mk @@ -0,0 +1,42 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/main.c \ +../Core/Src/stm32h7xx_hal_msp.c \ +../Core/Src/stm32h7xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32h7xx.c + +OBJS += \ +./Core/Src/main.o \ +./Core/Src/stm32h7xx_hal_msp.o \ +./Core/Src/stm32h7xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32h7xx.o + +C_DEPS += \ +./Core/Src/main.d \ +./Core/Src/stm32h7xx_hal_msp.d \ +./Core/Src/stm32h7xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32h7xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/stm32h7xx_hal_msp.cyclo ./Core/Src/stm32h7xx_hal_msp.d ./Core/Src/stm32h7xx_hal_msp.o ./Core/Src/stm32h7xx_hal_msp.su ./Core/Src/stm32h7xx_it.cyclo ./Core/Src/stm32h7xx_it.d ./Core/Src/stm32h7xx_it.o ./Core/Src/stm32h7xx_it.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32h7xx.cyclo ./Core/Src/system_stm32h7xx.d ./Core/Src/system_stm32h7xx.o ./Core/Src/system_stm32h7xx.su + +.PHONY: clean-Core-2f-Src + diff --git a/Debug/Core/Src/syscalls.cyclo b/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 0000000..6cbfdd0 --- /dev/null +++ b/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 +../Core/Src/syscalls.c:163:5:_fork 1 +../Core/Src/syscalls.c:169:5:_execve 1 diff --git a/Debug/Core/Src/syscalls.d b/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..01862e2 --- /dev/null +++ b/Debug/Core/Src/syscalls.d @@ -0,0 +1,76 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..caa4ce2 Binary files /dev/null and b/Debug/Core/Src/syscalls.o differ diff --git a/Debug/Core/Src/syscalls.su b/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..e06feaf --- /dev/null +++ b/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static +../Core/Src/syscalls.c:48:5:_getpid 4 static +../Core/Src/syscalls.c:53:5:_kill 16 static +../Core/Src/syscalls.c:61:6:_exit 16 static +../Core/Src/syscalls.c:67:27:_read 32 static +../Core/Src/syscalls.c:80:27:_write 32 static +../Core/Src/syscalls.c:92:5:_close 16 static +../Core/Src/syscalls.c:99:5:_fstat 16 static +../Core/Src/syscalls.c:106:5:_isatty 16 static +../Core/Src/syscalls.c:112:5:_lseek 24 static +../Core/Src/syscalls.c:120:5:_open 12 static +../Core/Src/syscalls.c:128:5:_wait 16 static +../Core/Src/syscalls.c:135:5:_unlink 16 static +../Core/Src/syscalls.c:142:5:_times 16 static +../Core/Src/syscalls.c:148:5:_stat 16 static +../Core/Src/syscalls.c:155:5:_link 16 static +../Core/Src/syscalls.c:163:5:_fork 4 static +../Core/Src/syscalls.c:169:5:_execve 24 static diff --git a/Debug/Core/Src/sysmem.cyclo b/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 0000000..0090c10 --- /dev/null +++ b/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 3 diff --git a/Debug/Core/Src/sysmem.d b/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..b7ac370 --- /dev/null +++ b/Debug/Core/Src/sysmem.d @@ -0,0 +1,76 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..6371db9 Binary files /dev/null and b/Debug/Core/Src/sysmem.o differ diff --git a/Debug/Core/Src/sysmem.su b/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..12d5f17 --- /dev/null +++ b/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/Debug/Core/Src/system_stm32h7xx.cyclo b/Debug/Core/Src/system_stm32h7xx.cyclo new file mode 100644 index 0000000..89c4fc2 --- /dev/null +++ b/Debug/Core/Src/system_stm32h7xx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32h7xx.c:175:6:SystemInit 3 +../Core/Src/system_stm32h7xx.c:340:6:SystemCoreClockUpdate 10 diff --git a/Debug/Core/Src/system_stm32h7xx.d b/Debug/Core/Src/system_stm32h7xx.d new file mode 100644 index 0000000..72b7c75 --- /dev/null +++ b/Debug/Core/Src/system_stm32h7xx.d @@ -0,0 +1,61 @@ +Core/Src/system_stm32h7xx.o: ../Core/Src/system_stm32h7xx.c \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Core/Src/system_stm32h7xx.o b/Debug/Core/Src/system_stm32h7xx.o new file mode 100644 index 0000000..33d8a56 Binary files /dev/null and b/Debug/Core/Src/system_stm32h7xx.o differ diff --git a/Debug/Core/Src/system_stm32h7xx.su b/Debug/Core/Src/system_stm32h7xx.su new file mode 100644 index 0000000..ceeaf63 --- /dev/null +++ b/Debug/Core/Src/system_stm32h7xx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32h7xx.c:175:6:SystemInit 16 static +../Core/Src/system_stm32h7xx.c:340:6:SystemCoreClockUpdate 48 static diff --git a/Debug/Core/Startup/startup_stm32h723vghx.d b/Debug/Core/Startup/startup_stm32h723vghx.d new file mode 100644 index 0000000..67df352 --- /dev/null +++ b/Debug/Core/Startup/startup_stm32h723vghx.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32h723vghx.o: \ + ../Core/Startup/startup_stm32h723vghx.s diff --git a/Debug/Core/Startup/startup_stm32h723vghx.o b/Debug/Core/Startup/startup_stm32h723vghx.o new file mode 100644 index 0000000..54f55d8 Binary files /dev/null and b/Debug/Core/Startup/startup_stm32h723vghx.o differ diff --git a/Debug/Core/Startup/subdir.mk b/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..bc68ae8 --- /dev/null +++ b/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32h723vghx.s + +OBJS += \ +./Core/Startup/startup_stm32h723vghx.o + +S_DEPS += \ +./Core/Startup/startup_stm32h723vghx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m7 -g3 -DDEBUG -c -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32h723vghx.d ./Core/Startup/startup_stm32h723vghx.o + +.PHONY: clean-Core-2f-Startup + diff --git a/Debug/Drivers/BSP/Components/lan8742/lan8742.cyclo b/Debug/Drivers/BSP/Components/lan8742/lan8742.cyclo new file mode 100644 index 0000000..f20159c --- /dev/null +++ b/Debug/Drivers/BSP/Components/lan8742/lan8742.cyclo @@ -0,0 +1,14 @@ +../Drivers/BSP/Components/lan8742/lan8742.c:63:10:LAN8742_RegisterBusIO 5 +../Drivers/BSP/Components/lan8742/lan8742.c:88:10:LAN8742_Init 15 +../Drivers/BSP/Components/lan8742/lan8742.c:188:9:LAN8742_DeInit 4 +../Drivers/BSP/Components/lan8742/lan8742.c:213:9:LAN8742_DisablePowerDownMode 3 +../Drivers/BSP/Components/lan8742/lan8742.c:243:9:LAN8742_EnablePowerDownMode 3 +../Drivers/BSP/Components/lan8742/lan8742.c:273:9:LAN8742_StartAutoNego 3 +../Drivers/BSP/Components/lan8742/lan8742.c:309:9:LAN8742_GetLinkState 15 +../Drivers/BSP/Components/lan8742/lan8742.c:401:9:LAN8742_SetLinkState 7 +../Drivers/BSP/Components/lan8742/lan8742.c:453:9:LAN8742_EnableLoopbackMode 3 +../Drivers/BSP/Components/lan8742/lan8742.c:483:9:LAN8742_DisableLoopbackMode 3 +../Drivers/BSP/Components/lan8742/lan8742.c:523:9:LAN8742_EnableIT 3 +../Drivers/BSP/Components/lan8742/lan8742.c:563:9:LAN8742_DisableIT 3 +../Drivers/BSP/Components/lan8742/lan8742.c:602:10:LAN8742_ClearIT 2 +../Drivers/BSP/Components/lan8742/lan8742.c:632:9:LAN8742_GetITStatus 2 diff --git a/Debug/Drivers/BSP/Components/lan8742/lan8742.d b/Debug/Drivers/BSP/Components/lan8742/lan8742.d new file mode 100644 index 0000000..47f281d --- /dev/null +++ b/Debug/Drivers/BSP/Components/lan8742/lan8742.d @@ -0,0 +1,4 @@ +Drivers/BSP/Components/lan8742/lan8742.o: \ + ../Drivers/BSP/Components/lan8742/lan8742.c \ + ../Drivers/BSP/Components/lan8742/lan8742.h +../Drivers/BSP/Components/lan8742/lan8742.h: diff --git a/Debug/Drivers/BSP/Components/lan8742/lan8742.o b/Debug/Drivers/BSP/Components/lan8742/lan8742.o new file mode 100644 index 0000000..cbaa2dc Binary files /dev/null and b/Debug/Drivers/BSP/Components/lan8742/lan8742.o differ diff --git a/Debug/Drivers/BSP/Components/lan8742/lan8742.su b/Debug/Drivers/BSP/Components/lan8742/lan8742.su new file mode 100644 index 0000000..c75843a --- /dev/null +++ b/Debug/Drivers/BSP/Components/lan8742/lan8742.su @@ -0,0 +1,14 @@ +../Drivers/BSP/Components/lan8742/lan8742.c:63:10:LAN8742_RegisterBusIO 16 static +../Drivers/BSP/Components/lan8742/lan8742.c:88:10:LAN8742_Init 32 static +../Drivers/BSP/Components/lan8742/lan8742.c:188:9:LAN8742_DeInit 16 static +../Drivers/BSP/Components/lan8742/lan8742.c:213:9:LAN8742_DisablePowerDownMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:243:9:LAN8742_EnablePowerDownMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:273:9:LAN8742_StartAutoNego 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:309:9:LAN8742_GetLinkState 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:401:9:LAN8742_SetLinkState 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:453:9:LAN8742_EnableLoopbackMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:483:9:LAN8742_DisableLoopbackMode 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:523:9:LAN8742_EnableIT 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:563:9:LAN8742_DisableIT 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:602:10:LAN8742_ClearIT 24 static +../Drivers/BSP/Components/lan8742/lan8742.c:632:9:LAN8742_GetITStatus 24 static diff --git a/Debug/Drivers/BSP/Components/lan8742/subdir.mk b/Debug/Drivers/BSP/Components/lan8742/subdir.mk new file mode 100644 index 0000000..ab4a471 --- /dev/null +++ b/Debug/Drivers/BSP/Components/lan8742/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/BSP/Components/lan8742/lan8742.c + +OBJS += \ +./Drivers/BSP/Components/lan8742/lan8742.o + +C_DEPS += \ +./Drivers/BSP/Components/lan8742/lan8742.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/BSP/Components/lan8742/%.o Drivers/BSP/Components/lan8742/%.su Drivers/BSP/Components/lan8742/%.cyclo: ../Drivers/BSP/Components/lan8742/%.c Drivers/BSP/Components/lan8742/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-BSP-2f-Components-2f-lan8742 + +clean-Drivers-2f-BSP-2f-Components-2f-lan8742: + -$(RM) ./Drivers/BSP/Components/lan8742/lan8742.cyclo ./Drivers/BSP/Components/lan8742/lan8742.d ./Drivers/BSP/Components/lan8742/lan8742.o ./Drivers/BSP/Components/lan8742/lan8742.su + +.PHONY: clean-Drivers-2f-BSP-2f-Components-2f-lan8742 + diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo new file mode 100644 index 0000000..949f040 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo @@ -0,0 +1,54 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:134:19:HAL_Init 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:187:19:HAL_DeInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:228:13:HAL_MspInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:239:13:HAL_MspDeInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:262:26:HAL_InitTick 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:327:13:HAL_IncTick 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:338:17:HAL_GetTick 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:347:10:HAL_GetTickPrio 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:356:19:HAL_SetTickFreq 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:388:21:HAL_GetTickFreq 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:404:13:HAL_Delay 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:430:13:HAL_SuspendTick 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:446:13:HAL_ResumeTick 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:456:10:HAL_GetHalVersion 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:465:10:HAL_GetREVID 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:474:10:HAL_GetDEVID 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:483:10:HAL_GetUIDw0 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:492:10:HAL_GetUIDw1 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:501:10:HAL_GetUIDw2 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:520:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:536:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:548:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:560:19:HAL_SYSCFG_EnableVREFBUF 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:586:6:HAL_SYSCFG_DisableVREFBUF 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:600:6:HAL_SYSCFG_ETHInterfaceSelect 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:630:6:HAL_SYSCFG_AnalogSwitchConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:648:6:HAL_SYSCFG_EnableBOOST 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:660:6:HAL_SYSCFG_DisableBOOST 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:676:6:HAL_SYSCFG_CM7BootAddConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:775:6:HAL_EnableCompensationCell 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:786:6:HAL_DisableCompensationCell 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:799:6:HAL_SYSCFG_EnableIOSpeedOptimize 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:815:6:HAL_SYSCFG_DisableIOSpeedOptimize 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:832:6:HAL_SYSCFG_CompensationCodeSelect 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:849:6:HAL_SYSCFG_CompensationCodeConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:883:6:HAL_SYSCFG_ADC2ALT_Rout0Config 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:898:6:HAL_SYSCFG_ADC2ALT_Rout1Config 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:911:6:HAL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:920:6:HAL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:930:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:939:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:948:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:957:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1023:6:HAL_EnableDomain3DBGStopMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1032:6:HAL_DisableDomain3DBGStopMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1043:6:HAL_EnableDomain3DBGStandbyMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1052:6:HAL_DisableDomain3DBGStandbyMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1064:6:HAL_SetFMCMemorySwappingConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1076:10:HAL_GetFMCMemorySwappingConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1093:6:HAL_EXTI_EdgeConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1119:6:HAL_EXTI_GenerateSWInterrupt 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1134:6:HAL_EXTI_D1_ClearFlag 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1169:6:HAL_EXTI_D1_EventInputConfig 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1263:6:HAL_EXTI_D3_EventInputConfig 3 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d new file mode 100644 index 0000000..f14b3b3 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o new file mode 100644 index 0000000..794ff8b Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su new file mode 100644 index 0000000..30153a4 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su @@ -0,0 +1,54 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:134:19:HAL_Init 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:187:19:HAL_DeInit 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:228:13:HAL_MspInit 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:239:13:HAL_MspDeInit 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:262:26:HAL_InitTick 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:327:13:HAL_IncTick 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:338:17:HAL_GetTick 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:347:10:HAL_GetTickPrio 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:356:19:HAL_SetTickFreq 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:388:21:HAL_GetTickFreq 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:404:13:HAL_Delay 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:430:13:HAL_SuspendTick 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:446:13:HAL_ResumeTick 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:456:10:HAL_GetHalVersion 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:465:10:HAL_GetREVID 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:474:10:HAL_GetDEVID 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:483:10:HAL_GetUIDw0 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:492:10:HAL_GetUIDw1 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:501:10:HAL_GetUIDw2 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:520:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:536:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:548:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:560:19:HAL_SYSCFG_EnableVREFBUF 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:586:6:HAL_SYSCFG_DisableVREFBUF 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:600:6:HAL_SYSCFG_ETHInterfaceSelect 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:630:6:HAL_SYSCFG_AnalogSwitchConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:648:6:HAL_SYSCFG_EnableBOOST 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:660:6:HAL_SYSCFG_DisableBOOST 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:676:6:HAL_SYSCFG_CM7BootAddConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:775:6:HAL_EnableCompensationCell 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:786:6:HAL_DisableCompensationCell 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:799:6:HAL_SYSCFG_EnableIOSpeedOptimize 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:815:6:HAL_SYSCFG_DisableIOSpeedOptimize 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:832:6:HAL_SYSCFG_CompensationCodeSelect 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:849:6:HAL_SYSCFG_CompensationCodeConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:883:6:HAL_SYSCFG_ADC2ALT_Rout0Config 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:898:6:HAL_SYSCFG_ADC2ALT_Rout1Config 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:911:6:HAL_DBGMCU_EnableDBGSleepMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:920:6:HAL_DBGMCU_DisableDBGSleepMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:930:6:HAL_DBGMCU_EnableDBGStopMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:939:6:HAL_DBGMCU_DisableDBGStopMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:948:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:957:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1023:6:HAL_EnableDomain3DBGStopMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1032:6:HAL_DisableDomain3DBGStopMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1043:6:HAL_EnableDomain3DBGStandbyMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1052:6:HAL_DisableDomain3DBGStandbyMode 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1064:6:HAL_SetFMCMemorySwappingConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1076:10:HAL_GetFMCMemorySwappingConfig 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1093:6:HAL_EXTI_EdgeConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1119:6:HAL_EXTI_GenerateSWInterrupt 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1134:6:HAL_EXTI_D1_ClearFlag 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1169:6:HAL_EXTI_D1_EventInputConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c:1263:6:HAL_EXTI_D3_EventInputConfig 32 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo new file mode 100644 index 0000000..7f39479 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo @@ -0,0 +1,33 @@ +../Drivers/CMSIS/Include/core_cm7.h:1871:22:__NVIC_SetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm7.h:1890:26:__NVIC_GetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm7.h:1902:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm7.h:1940:22:__NVIC_DisableIRQ 2 +../Drivers/CMSIS/Include/core_cm7.h:1959:26:__NVIC_GetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm7.h:1978:22:__NVIC_SetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm7.h:1993:22:__NVIC_ClearPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm7.h:2010:26:__NVIC_GetActive 2 +../Drivers/CMSIS/Include/core_cm7.h:2032:22:__NVIC_SetPriority 2 +../Drivers/CMSIS/Include/core_cm7.h:2054:26:__NVIC_GetPriority 2 +../Drivers/CMSIS/Include/core_cm7.h:2079:26:NVIC_EncodePriority 2 +../Drivers/CMSIS/Include/core_cm7.h:2106:22:NVIC_DecodePriority 2 +../Drivers/CMSIS/Include/core_cm7.h:2156:34:__NVIC_SystemReset 1 +../Drivers/CMSIS/Include/core_cm7.h:2618:26:SysTick_Config 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:142:6:HAL_NVIC_SetPriorityGrouping 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:164:6:HAL_NVIC_SetPriority 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:186:6:HAL_NVIC_EnableIRQ 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:202:6:HAL_NVIC_DisableIRQ 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:215:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:228:10:HAL_SYSTICK_Config 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:256:6:HAL_MPU_Disable 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:279:6:HAL_MPU_Enable 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:297:6:HAL_MPU_ConfigRegion 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:341:10:HAL_NVIC_GetPriorityGrouping 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:368:6:HAL_NVIC_GetPriority 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:383:6:HAL_NVIC_SetPendingIRQ 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:401:10:HAL_NVIC_GetPendingIRQ 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:417:6:HAL_NVIC_ClearPendingIRQ 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:434:10:HAL_NVIC_GetActive 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:451:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:469:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:478:13:HAL_SYSTICK_Callback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:509:10:HAL_GetCurrentCPUID 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d new file mode 100644 index 0000000..e15a315 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o new file mode 100644 index 0000000..36540cf Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su new file mode 100644 index 0000000..767d15f --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su @@ -0,0 +1,33 @@ +../Drivers/CMSIS/Include/core_cm7.h:1871:22:__NVIC_SetPriorityGrouping 24 static +../Drivers/CMSIS/Include/core_cm7.h:1890:26:__NVIC_GetPriorityGrouping 4 static +../Drivers/CMSIS/Include/core_cm7.h:1902:22:__NVIC_EnableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm7.h:1940:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm7.h:1959:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm7.h:1978:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm7.h:1993:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm7.h:2010:26:__NVIC_GetActive 16 static +../Drivers/CMSIS/Include/core_cm7.h:2032:22:__NVIC_SetPriority 16 static +../Drivers/CMSIS/Include/core_cm7.h:2054:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm7.h:2079:26:NVIC_EncodePriority 40 static +../Drivers/CMSIS/Include/core_cm7.h:2106:22:NVIC_DecodePriority 40 static +../Drivers/CMSIS/Include/core_cm7.h:2156:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm7.h:2618:26:SysTick_Config 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:142:6:HAL_NVIC_SetPriorityGrouping 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:164:6:HAL_NVIC_SetPriority 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:186:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:202:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:215:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:228:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:256:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:279:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:297:6:HAL_MPU_ConfigRegion 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:341:10:HAL_NVIC_GetPriorityGrouping 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:368:6:HAL_NVIC_GetPriority 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:383:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:401:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:417:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:434:10:HAL_NVIC_GetActive 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:451:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:469:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:478:13:HAL_SYSTICK_Callback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c:509:10:HAL_GetCurrentCPUID 4 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo new file mode 100644 index 0000000..34496ad --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:216:19:HAL_DMA_Init 98 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:468:19:HAL_DMA_DeInit 47 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:625:19:HAL_DMA_Start 36 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:681:19:HAL_DMA_Start_IT 82 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:781:19:HAL_DMA_Abort 106 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:897:19:HAL_DMA_Abort_IT 79 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:981:19:HAL_DMA_PollForTransfer 112 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1208:6:HAL_DMA_IRQHandler 222 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1578:19:HAL_DMA_RegisterCallback 10 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1645:19:HAL_DMA_UnRegisterCallback 11 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1736:22:HAL_DMA_GetState 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1747:10:HAL_DMA_GetError 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1773:13:DMA_SetConfig 55 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1860:17:DMA_CalcBaseAndBitshift 19 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1896:26:DMA_CheckFifoParam 15 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1990:13:DMA_CalcDMAMUXChannelBaseAndMask 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:2025:13:DMA_CalcDMAMUXRequestGenBaseAndMask 12 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d new file mode 100644 index 0000000..331cd08 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o new file mode 100644 index 0000000..13a12eb Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su new file mode 100644 index 0000000..8daecf5 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su @@ -0,0 +1,17 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:216:19:HAL_DMA_Init 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:468:19:HAL_DMA_DeInit 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:625:19:HAL_DMA_Start 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:681:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:781:19:HAL_DMA_Abort 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:897:19:HAL_DMA_Abort_IT 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:981:19:HAL_DMA_PollForTransfer 48 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1208:6:HAL_DMA_IRQHandler 48 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1578:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1645:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1736:22:HAL_DMA_GetState 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1747:10:HAL_DMA_GetError 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1773:13:DMA_SetConfig 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1860:17:DMA_CalcBaseAndBitshift 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1896:26:DMA_CheckFifoParam 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:1990:13:DMA_CalcDMAMUXChannelBaseAndMask 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c:2025:13:DMA_CalcDMAMUXRequestGenBaseAndMask 24 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo new file mode 100644 index 0000000..4ddefe6 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:120:19:HAL_DMAEx_MultiBufferStart 63 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:217:19:HAL_DMAEx_MultiBufferStart_IT 111 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:357:19:HAL_DMAEx_ChangeMemory 20 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:396:19:HAL_DMAEx_ConfigMuxSync 19 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:464:19:HAL_DMAEx_ConfigMuxRequestGenerator 20 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:530:19:HAL_DMAEx_EnableMuxRequestGenerator 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:556:19:HAL_DMAEx_DisableMuxRequestGenerator 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:582:6:HAL_DMAEx_MUX_IRQHandler 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:648:13:DMA_MultiBufferSetConfig 20 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d new file mode 100644 index 0000000..f170cbd --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o new file mode 100644 index 0000000..7ded811 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su new file mode 100644 index 0000000..b27c6e9 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su @@ -0,0 +1,9 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:120:19:HAL_DMAEx_MultiBufferStart 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:217:19:HAL_DMAEx_MultiBufferStart_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:357:19:HAL_DMAEx_ChangeMemory 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:396:19:HAL_DMAEx_ConfigMuxSync 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:464:19:HAL_DMAEx_ConfigMuxRequestGenerator 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:530:19:HAL_DMAEx_EnableMuxRequestGenerator 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:556:19:HAL_DMAEx_DisableMuxRequestGenerator 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:582:6:HAL_DMAEx_MUX_IRQHandler 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c:648:13:DMA_MultiBufferSetConfig 24 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo new file mode 100644 index 0000000..5b8d31e --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo @@ -0,0 +1,56 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:307:19:HAL_ETH_Init 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:425:19:HAL_ETH_DeInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:458:13:HAL_ETH_MspInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:473:13:HAL_ETH_MspDeInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:709:19:HAL_ETH_Start 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:755:19:HAL_ETH_Start_IT 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:818:19:HAL_ETH_Stop 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:856:19:HAL_ETH_Stop_IT 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:916:19:HAL_ETH_Transmit 10 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:991:19:HAL_ETH_Transmit_IT 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1037:19:HAL_ETH_ReadData 14 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1150:13:ETH_UpdateDescriptor 9 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1225:19:HAL_ETH_RegisterRxAllocateCallback 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1246:19:HAL_ETH_UnRegisterRxAllocateCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1259:13:HAL_ETH_RxAllocateCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1276:13:HAL_ETH_RxLinkCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1295:19:HAL_ETH_RegisterRxLinkCallback 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1315:19:HAL_ETH_UnRegisterRxLinkCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1330:19:HAL_ETH_GetRxDataErrorCode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1345:19:HAL_ETH_RegisterTxFreeCallback 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1365:19:HAL_ETH_UnRegisterTxFreeCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1378:13:HAL_ETH_TxFreeCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1393:19:HAL_ETH_ReleaseTxPacket 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1832:6:HAL_ETH_IRQHandler 13 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2025:13:HAL_ETH_TxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2040:13:HAL_ETH_RxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2055:13:HAL_ETH_ErrorCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2070:13:HAL_ETH_PMTCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2085:13:HAL_ETH_EEECallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2100:13:HAL_ETH_WakeUpCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2118:19:HAL_ETH_ReadPHYRegister 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2174:19:HAL_ETH_WritePHYRegister 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2247:19:HAL_ETH_GetMACConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2322:19:HAL_ETH_GetDMAConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2355:19:HAL_ETH_SetMACConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2382:19:HAL_ETH_SetDMAConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2407:6:HAL_ETH_SetMDIOClockRange 9 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2460:19:HAL_ETH_SetMACFilterConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2494:19:HAL_ETH_GetMACFilterConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2531:19:HAL_ETH_SetSourceMACAddrMatch 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2566:19:HAL_ETH_SetHashTable 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2588:6:HAL_ETH_SetRxVLANIdentifier 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2610:6:HAL_ETH_EnterPowerDownMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2632:6:HAL_ETH_ExitPowerDownMode 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2656:19:HAL_ETH_SetWakeUpFilter 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2705:22:HAL_ETH_GetState 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2716:10:HAL_ETH_GetError 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2727:10:HAL_ETH_GetDMAError 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2738:10:HAL_ETH_GetMACError 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2749:10:HAL_ETH_GetMACWakeUpSource 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2767:13:ETH_SetMACConfig 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2844:13:ETH_SetDMAConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2886:13:ETH_MACDMAConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2960:13:ETH_DMATxDescListInit 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2998:13:ETH_DMARxDescListInit 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:3045:17:ETH_Prepare_Tx_Descriptors 26 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d new file mode 100644 index 0000000..c4c3f78 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o new file mode 100644 index 0000000..b5bf092 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su new file mode 100644 index 0000000..0950563 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su @@ -0,0 +1,56 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:307:19:HAL_ETH_Init 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:425:19:HAL_ETH_DeInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:458:13:HAL_ETH_MspInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:473:13:HAL_ETH_MspDeInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:709:19:HAL_ETH_Start 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:755:19:HAL_ETH_Start_IT 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:818:19:HAL_ETH_Stop 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:856:19:HAL_ETH_Stop_IT 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:916:19:HAL_ETH_Transmit 32 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:991:19:HAL_ETH_Transmit_IT 16 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1037:19:HAL_ETH_ReadData 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1150:13:ETH_UpdateDescriptor 40 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1225:19:HAL_ETH_RegisterRxAllocateCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1246:19:HAL_ETH_UnRegisterRxAllocateCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1259:13:HAL_ETH_RxAllocateCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1276:13:HAL_ETH_RxLinkCallback 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1295:19:HAL_ETH_RegisterRxLinkCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1315:19:HAL_ETH_UnRegisterRxLinkCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1330:19:HAL_ETH_GetRxDataErrorCode 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1345:19:HAL_ETH_RegisterTxFreeCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1365:19:HAL_ETH_UnRegisterTxFreeCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1378:13:HAL_ETH_TxFreeCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1393:19:HAL_ETH_ReleaseTxPacket 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:1832:6:HAL_ETH_IRQHandler 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2025:13:HAL_ETH_TxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2040:13:HAL_ETH_RxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2055:13:HAL_ETH_ErrorCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2070:13:HAL_ETH_PMTCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2085:13:HAL_ETH_EEECallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2100:13:HAL_ETH_WakeUpCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2118:19:HAL_ETH_ReadPHYRegister 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2174:19:HAL_ETH_WritePHYRegister 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2247:19:HAL_ETH_GetMACConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2322:19:HAL_ETH_GetDMAConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2355:19:HAL_ETH_SetMACConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2382:19:HAL_ETH_SetDMAConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2407:6:HAL_ETH_SetMDIOClockRange 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2460:19:HAL_ETH_SetMACFilterConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2494:19:HAL_ETH_GetMACFilterConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2531:19:HAL_ETH_SetSourceMACAddrMatch 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2566:19:HAL_ETH_SetHashTable 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2588:6:HAL_ETH_SetRxVLANIdentifier 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2610:6:HAL_ETH_EnterPowerDownMode 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2632:6:HAL_ETH_ExitPowerDownMode 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2656:19:HAL_ETH_SetWakeUpFilter 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2705:22:HAL_ETH_GetState 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2716:10:HAL_ETH_GetError 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2727:10:HAL_ETH_GetDMAError 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2738:10:HAL_ETH_GetMACError 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2749:10:HAL_ETH_GetMACWakeUpSource 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2767:13:ETH_SetMACConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2844:13:ETH_SetDMAConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2886:13:ETH_MACDMAConfig 152 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2960:13:ETH_DMATxDescListInit 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:2998:13:ETH_DMARxDescListInit 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c:3045:17:ETH_Prepare_Tx_Descriptors 56 static,ignoring_inline_asm diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo new file mode 100644 index 0000000..3c65666 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo @@ -0,0 +1,20 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:94:6:HAL_ETHEx_EnableARPOffload 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:105:6:HAL_ETHEx_DisableARPOffload 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:117:6:HAL_ETHEx_SetARPAddressMatch 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:135:19:HAL_ETHEx_SetL4FilterConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:175:19:HAL_ETHEx_GetL4FilterConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:212:19:HAL_ETHEx_SetL3FilterConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:266:19:HAL_ETHEx_GetL3FilterConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:307:6:HAL_ETHEx_EnableL3L4Filtering 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:319:6:HAL_ETHEx_DisableL3L4Filtering 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:333:19:HAL_ETHEx_GetRxVLANConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:366:19:HAL_ETHEx_SetRxVLANConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:394:6:HAL_ETHEx_SetVLANHashTable 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:410:19:HAL_ETHEx_GetTxVLANConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:445:19:HAL_ETHEx_SetTxVLANConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:476:6:HAL_ETHEx_SetTxVLANIdentifier 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:494:6:HAL_ETHEx_EnableVLANProcessing 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:506:6:HAL_ETHEx_DisableVLANProcessing 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:520:6:HAL_ETHEx_EnterLPIMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:538:6:HAL_ETHEx_ExitLPIMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:554:10:HAL_ETHEx_GetMACLPIEvent 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d new file mode 100644 index 0000000..4afa1c7 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o new file mode 100644 index 0000000..2ebd769 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su new file mode 100644 index 0000000..5253700 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su @@ -0,0 +1,20 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:94:6:HAL_ETHEx_EnableARPOffload 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:105:6:HAL_ETHEx_DisableARPOffload 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:117:6:HAL_ETHEx_SetARPAddressMatch 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:135:19:HAL_ETHEx_SetL4FilterConfig 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:175:19:HAL_ETHEx_GetL4FilterConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:212:19:HAL_ETHEx_SetL3FilterConfig 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:266:19:HAL_ETHEx_GetL3FilterConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:307:6:HAL_ETHEx_EnableL3L4Filtering 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:319:6:HAL_ETHEx_DisableL3L4Filtering 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:333:19:HAL_ETHEx_GetRxVLANConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:366:19:HAL_ETHEx_SetRxVLANConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:394:6:HAL_ETHEx_SetVLANHashTable 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:410:19:HAL_ETHEx_GetTxVLANConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:445:19:HAL_ETHEx_SetTxVLANConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:476:6:HAL_ETHEx_SetTxVLANIdentifier 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:494:6:HAL_ETHEx_EnableVLANProcessing 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:506:6:HAL_ETHEx_DisableVLANProcessing 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:520:6:HAL_ETHEx_EnterLPIMode 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:538:6:HAL_ETHEx_ExitLPIMode 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c:554:10:HAL_ETHEx_GetMACLPIEvent 16 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo new file mode 100644 index 0000000..d54adf1 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:170:19:HAL_EXTI_SetConfigLine 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:374:19:HAL_EXTI_GetConfigLine 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:512:19:HAL_EXTI_ClearConfigLine 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:612:19:HAL_EXTI_RegisterCallback 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:644:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:685:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:737:10:HAL_EXTI_GetPending 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:785:6:HAL_EXTI_ClearPending 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:824:6:HAL_EXTI_GenerateSWI 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d new file mode 100644 index 0000000..cecfc6d --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o new file mode 100644 index 0000000..b0926fa Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su new file mode 100644 index 0000000..89fdcbd --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:170:19:HAL_EXTI_SetConfigLine 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:374:19:HAL_EXTI_GetConfigLine 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:512:19:HAL_EXTI_ClearConfigLine 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:612:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:644:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:685:6:HAL_EXTI_IRQHandler 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:737:10:HAL_EXTI_GetPending 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:785:6:HAL_EXTI_ClearPending 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c:824:6:HAL_EXTI_GenerateSWI 32 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo new file mode 100644 index 0000000..52ee4a9 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:154:19:HAL_FLASH_Program 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:317:19:HAL_FLASH_Program_IT 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:471:6:HAL_FLASH_IRQHandler 15 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:741:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:759:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:792:19:HAL_FLASH_Unlock 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:829:19:HAL_FLASH_Lock 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:858:19:HAL_FLASH_OB_Unlock 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:880:19:HAL_FLASH_OB_Lock 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:898:19:HAL_FLASH_OB_Launch 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:976:10:HAL_FLASH_GetError 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1001:19:FLASH_WaitForLastOperation 9 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1085:19:FLASH_OB_WaitForLastOperation 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1124:19:FLASH_CRC_WaitForLastOperation 8 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d new file mode 100644 index 0000000..423eb1e --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o new file mode 100644 index 0000000..e3b5ccc Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su new file mode 100644 index 0000000..f666ec8 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su @@ -0,0 +1,14 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:154:19:HAL_FLASH_Program 48 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:317:19:HAL_FLASH_Program_IT 48 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:471:6:HAL_FLASH_IRQHandler 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:741:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:759:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:792:19:HAL_FLASH_Unlock 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:829:19:HAL_FLASH_Lock 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:858:19:HAL_FLASH_OB_Unlock 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:880:19:HAL_FLASH_OB_Lock 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:898:19:HAL_FLASH_OB_Launch 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:976:10:HAL_FLASH_GetError 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1001:19:FLASH_WaitForLastOperation 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1085:19:FLASH_OB_WaitForLastOperation 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c:1124:19:FLASH_CRC_WaitForLastOperation 24 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo new file mode 100644 index 0000000..1565cf4 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo @@ -0,0 +1,30 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:176:19:HAL_FLASHEx_Erase 11 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:293:19:HAL_FLASHEx_Erase_IT 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:414:19:HAL_FLASHEx_OBProgram 14 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:557:6:HAL_FLASHEx_OBGetConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:625:19:HAL_FLASHEx_Unlock_Bank1 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:647:19:HAL_FLASHEx_Lock_Bank1 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:700:19:HAL_FLASHEx_ComputeCRC 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:848:13:FLASH_MassErase 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:925:6:FLASH_Erase_Sector 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:982:13:FLASH_OB_EnableWRP 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1017:13:FLASH_OB_DisableWRP 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1056:13:FLASH_OB_GetWRP 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1102:13:FLASH_OB_RDPConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1119:17:FLASH_OB_GetRDP 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1175:13:FLASH_OB_UserConfig 11 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1363:17:FLASH_OB_GetUser 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1397:13:FLASH_OB_PCROPConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1446:13:FLASH_OB_GetPCROP 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1482:13:FLASH_OB_BOR_LevelConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1499:17:FLASH_OB_GetBOR 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1514:13:FLASH_OB_BootAddConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1552:13:FLASH_OB_GetBootAdd 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1636:13:FLASH_OB_SecureAreaConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1678:13:FLASH_OB_GetSecureArea 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1711:13:FLASH_CRC_AddSector 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1743:13:FLASH_CRC_SelectAddress 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1804:13:FLASH_OB_SharedRAM_Config 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1818:17:FLASH_OB_SharedRAM_GetConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1831:13:FLASH_OB_CPUFreq_BoostConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1845:17:FLASH_OB_CPUFreq_GetBoost 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d new file mode 100644 index 0000000..111791a --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o new file mode 100644 index 0000000..9faf5a5 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su new file mode 100644 index 0000000..655976d --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su @@ -0,0 +1,30 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:176:19:HAL_FLASHEx_Erase 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:293:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:414:19:HAL_FLASHEx_OBProgram 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:557:6:HAL_FLASHEx_OBGetConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:625:19:HAL_FLASHEx_Unlock_Bank1 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:647:19:HAL_FLASHEx_Lock_Bank1 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:700:19:HAL_FLASHEx_ComputeCRC 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:848:13:FLASH_MassErase 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:925:6:FLASH_Erase_Sector 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:982:13:FLASH_OB_EnableWRP 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1017:13:FLASH_OB_DisableWRP 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1056:13:FLASH_OB_GetWRP 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1102:13:FLASH_OB_RDPConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1119:17:FLASH_OB_GetRDP 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1175:13:FLASH_OB_UserConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1363:17:FLASH_OB_GetUser 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1397:13:FLASH_OB_PCROPConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1446:13:FLASH_OB_GetPCROP 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1482:13:FLASH_OB_BOR_LevelConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1499:17:FLASH_OB_GetBOR 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1514:13:FLASH_OB_BootAddConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1552:13:FLASH_OB_GetBootAdd 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1636:13:FLASH_OB_SecureAreaConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1678:13:FLASH_OB_GetSecureArea 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1711:13:FLASH_CRC_AddSector 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1743:13:FLASH_CRC_SelectAddress 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1804:13:FLASH_OB_SharedRAM_Config 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1818:17:FLASH_OB_SharedRAM_GetConfig 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1831:13:FLASH_OB_CPUFreq_BoostConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c:1845:17:FLASH_OB_CPUFreq_GetBoost 4 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo new file mode 100644 index 0000000..7f18224 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:165:6:HAL_GPIO_Init 21 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:302:6:HAL_GPIO_DeInit 13 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:389:15:HAL_GPIO_ReadPin 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:423:6:HAL_GPIO_WritePin 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:445:6:HAL_GPIO_TogglePin 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:470:19:HAL_GPIO_LockPin 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:505:6:HAL_GPIO_EXTI_IRQHandler 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:528:13:HAL_GPIO_EXTI_Callback 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d new file mode 100644 index 0000000..01b516e --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o new file mode 100644 index 0000000..373152e Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su new file mode 100644 index 0000000..db18f74 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su @@ -0,0 +1,8 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:165:6:HAL_GPIO_Init 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:302:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:389:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:423:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:445:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:470:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:505:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c:528:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo new file mode 100644 index 0000000..5be35c7 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo @@ -0,0 +1,11 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:159:20:HAL_HSEM_Take 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:196:19:HAL_HSEM_FastTake 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:225:10:HAL_HSEM_IsSemTaken 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:237:7:HAL_HSEM_Release 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:258:6:HAL_HSEM_ReleaseAll 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:290:7:HAL_HSEM_SetClearKey 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:302:10:HAL_HSEM_GetClearKey 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:329:6:HAL_HSEM_ActivateNotification 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:353:6:HAL_HSEM_DeactivateNotification 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:376:6:HAL_HSEM_IRQHandler 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:422:13:HAL_HSEM_FreeCallback 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d new file mode 100644 index 0000000..b83bf39 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o new file mode 100644 index 0000000..25dae27 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su new file mode 100644 index 0000000..654cf48 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su @@ -0,0 +1,11 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:159:20:HAL_HSEM_Take 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:196:19:HAL_HSEM_FastTake 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:225:10:HAL_HSEM_IsSemTaken 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:237:7:HAL_HSEM_Release 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:258:6:HAL_HSEM_ReleaseAll 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:290:7:HAL_HSEM_SetClearKey 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:302:10:HAL_HSEM_GetClearKey 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:329:6:HAL_HSEM_ActivateNotification 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:353:6:HAL_HSEM_DeactivateNotification 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:376:6:HAL_HSEM_IRQHandler 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c:422:13:HAL_HSEM_FreeCallback 16 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo new file mode 100644 index 0000000..b220e84 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo @@ -0,0 +1,81 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:528:19:HAL_I2C_Init 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:638:19:HAL_I2C_DeInit 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:684:13:HAL_I2C_MspInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:700:13:HAL_I2C_MspDeInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1107:19:HAL_I2C_Master_Transmit 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1226:19:HAL_I2C_Master_Receive 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1344:19:HAL_I2C_Slave_Transmit 15 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1500:19:HAL_I2C_Slave_Receive 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1630:19:HAL_I2C_Master_Transmit_IT 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1701:19:HAL_I2C_Master_Receive_IT 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1770:19:HAL_I2C_Slave_Transmit_IT 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1834:19:HAL_I2C_Slave_Receive_IT 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1886:19:HAL_I2C_Master_Transmit_DMA 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2033:19:HAL_I2C_Master_Receive_DMA 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2178:19:HAL_I2C_Slave_Transmit_DMA 9 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2314:19:HAL_I2C_Slave_Receive_DMA 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2422:19:HAL_I2C_Mem_Write 15 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2559:19:HAL_I2C_Mem_Read 15 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2696:19:HAL_I2C_Mem_Write_IT 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2783:19:HAL_I2C_Mem_Read_IT 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2869:19:HAL_I2C_Mem_Write_DMA 10 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3015:19:HAL_I2C_Mem_Read_DMA 10 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3160:19:HAL_I2C_IsDeviceReady 16 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3302:19:HAL_I2C_Master_Seq_Transmit_IT 9 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3393:19:HAL_I2C_Master_Seq_Transmit_DMA 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3561:19:HAL_I2C_Master_Seq_Receive_IT 9 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3648:19:HAL_I2C_Master_Seq_Receive_DMA 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3814:19:HAL_I2C_Slave_Seq_Transmit_IT 11 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3914:19:HAL_I2C_Slave_Seq_Transmit_DMA 17 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4098:19:HAL_I2C_Slave_Seq_Receive_IT 11 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4198:19:HAL_I2C_Slave_Seq_Receive_DMA 17 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4378:19:HAL_I2C_EnableListen_IT 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4402:19:HAL_I2C_DisableListen_IT 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4435:19:HAL_I2C_Master_Abort_IT 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4497:6:HAL_I2C_EV_IRQHandler 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4516:6:HAL_I2C_ER_IRQHandler 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4568:13:HAL_I2C_MasterTxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4584:13:HAL_I2C_MasterRxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4599:13:HAL_I2C_SlaveTxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4615:13:HAL_I2C_SlaveRxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4633:13:HAL_I2C_AddrCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4651:13:HAL_I2C_ListenCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4667:13:HAL_I2C_MemTxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4683:13:HAL_I2C_MemRxCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4699:13:HAL_I2C_ErrorCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4715:13:HAL_I2C_AbortCpltCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4750:22:HAL_I2C_GetState 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4762:21:HAL_I2C_GetMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4773:10:HAL_I2C_GetError 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4798:26:I2C_Master_ISR_IT 22 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4944:26:I2C_Mem_ISR_IT 20 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5081:26:I2C_Slave_ISR_IT 25 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5222:26:I2C_Master_ISR_DMA 18 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5362:26:I2C_Mem_ISR_DMA 18 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5501:26:I2C_Slave_ISR_DMA 59 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5646:26:I2C_RequestMemoryWrite 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5701:26:I2C_RequestMemoryRead 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5750:13:I2C_ITAddrCplt 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5845:13:I2C_ITMasterSeqCplt 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5898:13:I2C_ITSlaveSeqCplt 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5972:13:I2C_ITMasterCplt 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6115:13:I2C_ITSlaveCplt 48 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6274:13:I2C_ITListenCplt 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6325:13:I2C_ITError 19 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6454:13:I2C_TreatErrorCallback 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6492:13:I2C_Flush_TXDR 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6513:13:I2C_DMAMasterTransmitCplt 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6563:13:I2C_DMASlaveTransmitCplt 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6591:13:I2C_DMAMasterReceiveCplt 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6641:13:I2C_DMASlaveReceiveCplt 19 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6669:13:I2C_DMAError 39 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6708:13:I2C_DMAAbort 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6737:26:I2C_WaitOnFlagUntilTimeout 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6771:26:I2C_WaitOnTXISFlagUntilTimeout 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6812:26:I2C_WaitOnSTOPFlagUntilTimeout 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6850:26:I2C_WaitOnRXNEFlagUntilTimeout 10 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6926:26:I2C_IsErrorOccurred 17 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7067:13:I2C_TransferConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7094:13:I2C_Enable_IRQ 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7171:13:I2C_Disable_IRQ 9 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7234:13:I2C_ConvertOtherXferOptions 3 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d new file mode 100644 index 0000000..58e8fe3 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o new file mode 100644 index 0000000..cc04e29 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su new file mode 100644 index 0000000..3010100 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su @@ -0,0 +1,81 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:528:19:HAL_I2C_Init 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:638:19:HAL_I2C_DeInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:684:13:HAL_I2C_MspInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:700:13:HAL_I2C_MspDeInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1107:19:HAL_I2C_Master_Transmit 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1226:19:HAL_I2C_Master_Receive 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1344:19:HAL_I2C_Slave_Transmit 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1500:19:HAL_I2C_Slave_Receive 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1630:19:HAL_I2C_Master_Transmit_IT 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1701:19:HAL_I2C_Master_Receive_IT 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1770:19:HAL_I2C_Slave_Transmit_IT 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1834:19:HAL_I2C_Slave_Receive_IT 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:1886:19:HAL_I2C_Master_Transmit_DMA 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2033:19:HAL_I2C_Master_Receive_DMA 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2178:19:HAL_I2C_Slave_Transmit_DMA 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2314:19:HAL_I2C_Slave_Receive_DMA 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2422:19:HAL_I2C_Mem_Write 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2559:19:HAL_I2C_Mem_Read 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2696:19:HAL_I2C_Mem_Write_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2783:19:HAL_I2C_Mem_Read_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:2869:19:HAL_I2C_Mem_Write_DMA 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3015:19:HAL_I2C_Mem_Read_DMA 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3160:19:HAL_I2C_IsDeviceReady 48 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3302:19:HAL_I2C_Master_Seq_Transmit_IT 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3393:19:HAL_I2C_Master_Seq_Transmit_DMA 48 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3561:19:HAL_I2C_Master_Seq_Receive_IT 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3648:19:HAL_I2C_Master_Seq_Receive_DMA 48 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3814:19:HAL_I2C_Slave_Seq_Transmit_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:3914:19:HAL_I2C_Slave_Seq_Transmit_DMA 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4098:19:HAL_I2C_Slave_Seq_Receive_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4198:19:HAL_I2C_Slave_Seq_Receive_DMA 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4378:19:HAL_I2C_EnableListen_IT 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4402:19:HAL_I2C_DisableListen_IT 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4435:19:HAL_I2C_Master_Abort_IT 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4497:6:HAL_I2C_EV_IRQHandler 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4516:6:HAL_I2C_ER_IRQHandler 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4568:13:HAL_I2C_MasterTxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4584:13:HAL_I2C_MasterRxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4599:13:HAL_I2C_SlaveTxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4615:13:HAL_I2C_SlaveRxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4633:13:HAL_I2C_AddrCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4651:13:HAL_I2C_ListenCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4667:13:HAL_I2C_MemTxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4683:13:HAL_I2C_MemRxCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4699:13:HAL_I2C_ErrorCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4715:13:HAL_I2C_AbortCpltCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4750:22:HAL_I2C_GetState 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4762:21:HAL_I2C_GetMode 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4773:10:HAL_I2C_GetError 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4798:26:I2C_Master_ISR_IT 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:4944:26:I2C_Mem_ISR_IT 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5081:26:I2C_Slave_ISR_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5222:26:I2C_Master_ISR_DMA 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5362:26:I2C_Mem_ISR_DMA 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5501:26:I2C_Slave_ISR_DMA 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5646:26:I2C_RequestMemoryWrite 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5701:26:I2C_RequestMemoryRead 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5750:13:I2C_ITAddrCplt 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5845:13:I2C_ITMasterSeqCplt 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5898:13:I2C_ITSlaveSeqCplt 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:5972:13:I2C_ITMasterCplt 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6115:13:I2C_ITSlaveCplt 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6274:13:I2C_ITListenCplt 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6325:13:I2C_ITError 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6454:13:I2C_TreatErrorCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6492:13:I2C_Flush_TXDR 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6513:13:I2C_DMAMasterTransmitCplt 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6563:13:I2C_DMASlaveTransmitCplt 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6591:13:I2C_DMAMasterReceiveCplt 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6641:13:I2C_DMASlaveReceiveCplt 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6669:13:I2C_DMAError 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6708:13:I2C_DMAAbort 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6737:26:I2C_WaitOnFlagUntilTimeout 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6771:26:I2C_WaitOnTXISFlagUntilTimeout 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6812:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6850:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:6926:26:I2C_IsErrorOccurred 48 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7067:13:I2C_TransferConfig 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7094:13:I2C_Enable_IRQ 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7171:13:I2C_Disable_IRQ 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c:7234:13:I2C_ConvertOtherXferOptions 16 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo new file mode 100644 index 0000000..a259241 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:316:6:HAL_I2CEx_EnableFastModePlus 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:347:6:HAL_I2CEx_DisableFastModePlus 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d new file mode 100644 index 0000000..ed8c368 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o new file mode 100644 index 0000000..cce033a Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su new file mode 100644 index 0000000..f5125f3 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su @@ -0,0 +1,6 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:96:19:HAL_I2CEx_ConfigAnalogFilter 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:140:19:HAL_I2CEx_ConfigDigitalFilter 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:208:19:HAL_I2CEx_EnableWakeUp 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:247:19:HAL_I2CEx_DisableWakeUp 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:316:6:HAL_I2CEx_EnableFastModePlus 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c:347:6:HAL_I2CEx_DisableFastModePlus 24 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo new file mode 100644 index 0000000..1af2ba1 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo @@ -0,0 +1,21 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:218:19:HAL_MDMA_Init 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:294:19:HAL_MDMA_DeInit 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:347:19:HAL_MDMA_ConfigPostRequestMask 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:409:19:HAL_MDMA_RegisterCallback 10 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:474:19:HAL_MDMA_UnRegisterCallback 11 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:568:19:HAL_MDMA_LinkedList_CreateNode 13 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:711:19:HAL_MDMA_LinkedList_AddNode 18 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:844:19:HAL_MDMA_LinkedList_RemoveNode 16 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:957:19:HAL_MDMA_LinkedList_EnableCircularMode 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1001:19:HAL_MDMA_LinkedList_DisableCircularMode 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1072:19:HAL_MDMA_Start 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1132:19:HAL_MDMA_Start_IT 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1215:19:HAL_MDMA_Abort 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1280:19:HAL_MDMA_Abort_IT 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1315:19:HAL_MDMA_PollForTransfer 20 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1462:19:HAL_MDMA_GenerateSWRequest 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1504:6:HAL_MDMA_IRQHandler 28 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1722:23:HAL_MDMA_GetState 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1733:10:HAL_MDMA_GetError 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1760:13:MDMA_SetConfig 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1814:13:MDMA_Init 5 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d new file mode 100644 index 0000000..011d337 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o new file mode 100644 index 0000000..7832633 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su new file mode 100644 index 0000000..5e80aff --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su @@ -0,0 +1,21 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:218:19:HAL_MDMA_Init 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:294:19:HAL_MDMA_DeInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:347:19:HAL_MDMA_ConfigPostRequestMask 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:409:19:HAL_MDMA_RegisterCallback 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:474:19:HAL_MDMA_UnRegisterCallback 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:568:19:HAL_MDMA_LinkedList_CreateNode 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:711:19:HAL_MDMA_LinkedList_AddNode 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:844:19:HAL_MDMA_LinkedList_RemoveNode 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:957:19:HAL_MDMA_LinkedList_EnableCircularMode 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1001:19:HAL_MDMA_LinkedList_DisableCircularMode 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1072:19:HAL_MDMA_Start 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1132:19:HAL_MDMA_Start_IT 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1215:19:HAL_MDMA_Abort 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1280:19:HAL_MDMA_Abort_IT 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1315:19:HAL_MDMA_PollForTransfer 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1462:19:HAL_MDMA_GenerateSWRequest 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1504:6:HAL_MDMA_IRQHandler 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1722:23:HAL_MDMA_GetState 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1733:10:HAL_MDMA_GetError 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1760:13:MDMA_SetConfig 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c:1814:13:MDMA_Init 24 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo new file mode 100644 index 0000000..7254bb6 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:225:6:HAL_PWR_DeInit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:236:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:249:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:415:6:HAL_PWR_ConfigPVD 6 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:470:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:480:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:507:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:536:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:564:6:HAL_PWR_EnterSLEEPMode 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:615:6:HAL_PWR_EnterSTOPMode 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:686:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:738:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:751:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:764:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:776:6:HAL_PWR_DisableSEVOnPend 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:805:6:HAL_PWR_PVD_IRQHandler 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:850:13:HAL_PWR_PVDCallback 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d new file mode 100644 index 0000000..8596620 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o new file mode 100644 index 0000000..2abeb77 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su new file mode 100644 index 0000000..3e10d44 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su @@ -0,0 +1,17 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:225:6:HAL_PWR_DeInit 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:236:6:HAL_PWR_EnableBkUpAccess 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:249:6:HAL_PWR_DisableBkUpAccess 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:415:6:HAL_PWR_ConfigPVD 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:470:6:HAL_PWR_EnablePVD 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:480:6:HAL_PWR_DisablePVD 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:507:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:536:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:564:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:615:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:686:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:738:6:HAL_PWR_EnableSleepOnExit 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:751:6:HAL_PWR_DisableSleepOnExit 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:764:6:HAL_PWR_EnableSEVOnPend 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:776:6:HAL_PWR_DisableSEVOnPend 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:805:6:HAL_PWR_PVD_IRQHandler 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c:850:13:HAL_PWR_PVDCallback 4 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo new file mode 100644 index 0000000..ff427ab --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo @@ -0,0 +1,38 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:313:19:HAL_PWREx_ConfigSupply 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:385:10:HAL_PWREx_GetSupplyConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:413:19:HAL_PWREx_ControlVoltageScaling 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:512:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:538:19:HAL_PWREx_ControlStopModeVoltageScaling 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:553:10:HAL_PWREx_GetStopModeVoltageRange 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:816:6:HAL_PWREx_EnterSTOPMode 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:939:6:HAL_PWREx_ClearPendingEvent 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:986:6:HAL_PWREx_EnterSTANDBYMode 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1081:6:HAL_PWREx_ConfigD3Domain 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1212:6:HAL_PWREx_EnableFlashPowerDown 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1226:6:HAL_PWREx_DisableFlashPowerDown 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1302:6:HAL_PWREx_EnableWakeUpPin 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1344:6:HAL_PWREx_DisableWakeUpPin 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1369:10:HAL_PWREx_GetWakeupFlag 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1394:19:HAL_PWREx_ClearWakeupFlag 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1416:6:HAL_PWREx_WAKEUP_PIN_IRQHandler 4 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1477:13:HAL_PWREx_WKUP1_Callback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1488:13:HAL_PWREx_WKUP2_Callback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1512:13:HAL_PWREx_WKUP4_Callback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1536:13:HAL_PWREx_WKUP6_Callback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1625:19:HAL_PWREx_EnableBkUpReg 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1651:19:HAL_PWREx_DisableBkUpReg 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1677:19:HAL_PWREx_EnableUSBReg 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1703:19:HAL_PWREx_DisableUSBReg 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1729:6:HAL_PWREx_EnableUSBVoltageDetector 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1739:6:HAL_PWREx_DisableUSBVoltageDetector 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1755:6:HAL_PWREx_EnableBatteryCharging 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1771:6:HAL_PWREx_DisableBatteryCharging 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1861:6:HAL_PWREx_EnableMonitoring 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1871:6:HAL_PWREx_DisableMonitoring 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1882:10:HAL_PWREx_GetTemperatureLevel 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1913:10:HAL_PWREx_GetVBATLevel 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1976:6:HAL_PWREx_ConfigAVD 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2025:6:HAL_PWREx_EnableAVD 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2035:6:HAL_PWREx_DisableAVD 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2046:6:HAL_PWREx_PVD_AVD_IRQHandler 5 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2119:13:HAL_PWREx_AVDCallback 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d new file mode 100644 index 0000000..fc4af42 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o new file mode 100644 index 0000000..2ae5146 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su new file mode 100644 index 0000000..c138574 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su @@ -0,0 +1,38 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:313:19:HAL_PWREx_ConfigSupply 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:385:10:HAL_PWREx_GetSupplyConfig 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:413:19:HAL_PWREx_ControlVoltageScaling 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:512:10:HAL_PWREx_GetVoltageRange 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:538:19:HAL_PWREx_ControlStopModeVoltageScaling 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:553:10:HAL_PWREx_GetStopModeVoltageRange 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:816:6:HAL_PWREx_EnterSTOPMode 24 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:939:6:HAL_PWREx_ClearPendingEvent 4 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:986:6:HAL_PWREx_EnterSTANDBYMode 16 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1081:6:HAL_PWREx_ConfigD3Domain 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1212:6:HAL_PWREx_EnableFlashPowerDown 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1226:6:HAL_PWREx_DisableFlashPowerDown 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1302:6:HAL_PWREx_EnableWakeUpPin 80 static,ignoring_inline_asm +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1344:6:HAL_PWREx_DisableWakeUpPin 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1369:10:HAL_PWREx_GetWakeupFlag 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1394:19:HAL_PWREx_ClearWakeupFlag 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1416:6:HAL_PWREx_WAKEUP_PIN_IRQHandler 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1477:13:HAL_PWREx_WKUP1_Callback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1488:13:HAL_PWREx_WKUP2_Callback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1512:13:HAL_PWREx_WKUP4_Callback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1536:13:HAL_PWREx_WKUP6_Callback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1625:19:HAL_PWREx_EnableBkUpReg 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1651:19:HAL_PWREx_DisableBkUpReg 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1677:19:HAL_PWREx_EnableUSBReg 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1703:19:HAL_PWREx_DisableUSBReg 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1729:6:HAL_PWREx_EnableUSBVoltageDetector 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1739:6:HAL_PWREx_DisableUSBVoltageDetector 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1755:6:HAL_PWREx_EnableBatteryCharging 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1771:6:HAL_PWREx_DisableBatteryCharging 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1861:6:HAL_PWREx_EnableMonitoring 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1871:6:HAL_PWREx_DisableMonitoring 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1882:10:HAL_PWREx_GetTemperatureLevel 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1913:10:HAL_PWREx_GetVBATLevel 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:1976:6:HAL_PWREx_ConfigAVD 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2025:6:HAL_PWREx_EnableAVD 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2035:6:HAL_PWREx_DisableAVD 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2046:6:HAL_PWREx_PVD_AVD_IRQHandler 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c:2119:13:HAL_PWREx_AVDCallback 4 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo new file mode 100644 index 0000000..97101d2 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:188:19:HAL_RCC_DeInit 18 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:405:26:HAL_RCC_OscConfig 81 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:922:19:HAL_RCC_ClockConfig 36 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1286:6:HAL_RCC_MCOConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1340:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1349:6:HAL_RCC_DisableCSS 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1388:10:HAL_RCC_GetSysClockFreq 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1485:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1517:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1535:10:HAL_RCC_GetPCLK2Freq 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1552:6:HAL_RCC_GetOscConfig 10 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1718:6:HAL_RCC_GetClockConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1774:6:HAL_RCC_NMI_IRQHandler 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1791:13:HAL_RCC_CSSCallback 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d new file mode 100644 index 0000000..bba4b19 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o new file mode 100644 index 0000000..f4ac506 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su new file mode 100644 index 0000000..97ae8e5 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su @@ -0,0 +1,14 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:188:19:HAL_RCC_DeInit 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:405:26:HAL_RCC_OscConfig 56 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:922:19:HAL_RCC_ClockConfig 32 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1286:6:HAL_RCC_MCOConfig 56 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1340:6:HAL_RCC_EnableCSS 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1349:6:HAL_RCC_DisableCSS 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1388:10:HAL_RCC_GetSysClockFreq 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1485:10:HAL_RCC_GetHCLKFreq 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1517:10:HAL_RCC_GetPCLK1Freq 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1535:10:HAL_RCC_GetPCLK2Freq 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1552:6:HAL_RCC_GetOscConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1718:6:HAL_RCC_GetClockConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1774:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c:1791:13:HAL_RCC_CSSCallback 4 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo new file mode 100644 index 0000000..ea09280 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo @@ -0,0 +1,28 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig 203 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1692:6:HAL_RCCEx_GetPeriphCLKConfig 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1881:10:HAL_RCCEx_GetPeriphCLKFreq 128 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2904:10:HAL_RCCEx_GetD1PCLK1Freq 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2921:10:HAL_RCCEx_GetD3PCLK1Freq 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2945:6:HAL_RCCEx_GetPLL2ClockFreq 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3014:6:HAL_RCCEx_GetPLL3ClockFreq 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3082:6:HAL_RCCEx_GetPLL1ClockFreq 7 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3143:10:HAL_RCCEx_GetD1SysClockFreq 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3183:6:HAL_RCCEx_EnableLSECSS 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3193:6:HAL_RCCEx_DisableLSECSS 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3205:6:HAL_RCCEx_EnableLSECSS_IT 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3232:6:HAL_RCCEx_WakeUpStopCLKConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3247:6:HAL_RCCEx_KerWakeUpStopCLKConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3301:6:HAL_RCCEx_WWDGxSysResetConfig 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3382:6:HAL_RCCEx_CRSConfig 3 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3432:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3442:6:HAL_RCCEx_CRSGetSynchronizationInfo 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3475:10:HAL_RCCEx_CRSWaitSynchronization 11 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3559:6:HAL_RCCEx_CRS_IRQHandler 12 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3624:13:HAL_RCCEx_CRS_SyncOkCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3635:13:HAL_RCCEx_CRS_SyncWarnCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3646:13:HAL_RCCEx_CRS_ExpectedSyncCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3662:13:HAL_RCCEx_CRS_ErrorCallback 1 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3693:26:RCCEx_PLL2_Config 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3798:26:RCCEx_PLL3_Config 8 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3895:6:HAL_RCCEx_LSECSS_IRQHandler 2 +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3914:13:HAL_RCCEx_LSECSS_Callback 1 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d new file mode 100644 index 0000000..962adae --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o new file mode 100644 index 0000000..7fc1c12 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su new file mode 100644 index 0000000..9f19b9b --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su @@ -0,0 +1,28 @@ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:105:19:HAL_RCCEx_PeriphCLKConfig 312 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1692:6:HAL_RCCEx_GetPeriphCLKConfig 48 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:1881:10:HAL_RCCEx_GetPeriphCLKFreq 72 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2904:10:HAL_RCCEx_GetD1PCLK1Freq 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2921:10:HAL_RCCEx_GetD3PCLK1Freq 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:2945:6:HAL_RCCEx_GetPLL2ClockFreq 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3014:6:HAL_RCCEx_GetPLL3ClockFreq 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3082:6:HAL_RCCEx_GetPLL1ClockFreq 40 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3143:10:HAL_RCCEx_GetD1SysClockFreq 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3183:6:HAL_RCCEx_EnableLSECSS 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3193:6:HAL_RCCEx_DisableLSECSS 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3205:6:HAL_RCCEx_EnableLSECSS_IT 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3232:6:HAL_RCCEx_WakeUpStopCLKConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3247:6:HAL_RCCEx_KerWakeUpStopCLKConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3301:6:HAL_RCCEx_WWDGxSysResetConfig 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3382:6:HAL_RCCEx_CRSConfig 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3432:6:HAL_RCCEx_CRSSoftwareSynchronizationGenerate 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3442:6:HAL_RCCEx_CRSGetSynchronizationInfo 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3475:10:HAL_RCCEx_CRSWaitSynchronization 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3559:6:HAL_RCCEx_CRS_IRQHandler 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3624:13:HAL_RCCEx_CRS_SyncOkCallback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3635:13:HAL_RCCEx_CRS_SyncWarnCallback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3646:13:HAL_RCCEx_CRS_ExpectedSyncCallback 4 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3662:13:HAL_RCCEx_CRS_ErrorCallback 16 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3693:26:RCCEx_PLL2_Config 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3798:26:RCCEx_PLL3_Config 24 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3895:6:HAL_RCCEx_LSECSS_IRQHandler 8 static +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c:3914:13:HAL_RCCEx_LSECSS_Callback 4 static diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d new file mode 100644 index 0000000..353ea59 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o new file mode 100644 index 0000000..b93754c Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d new file mode 100644 index 0000000..6521462 --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d @@ -0,0 +1,62 @@ +Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o: \ + ../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o new file mode 100644 index 0000000..e17b3d1 Binary files /dev/null and b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o differ diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..2e7edff --- /dev/null +++ b/Debug/Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,84 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \ +../Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c + +OBJS += \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o + +C_DEPS += \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d \ +./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32H7xx_HAL_Driver/Src/%.o Drivers/STM32H7xx_HAL_Driver/Src/%.su Drivers/STM32H7xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32H7xx_HAL_Driver/Src/%.c Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.su ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.cyclo ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.d ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.su + +.PHONY: clean-Drivers-2f-STM32H7xx_HAL_Driver-2f-Src + diff --git a/Debug/LWFTP/lwftp.cyclo b/Debug/LWFTP/lwftp.cyclo new file mode 100644 index 0000000..39e66f6 --- /dev/null +++ b/Debug/LWFTP/lwftp.cyclo @@ -0,0 +1,22 @@ +../LWFTP/lwftp.c:57:14:lwftp_pcb_close 2 +../LWFTP/lwftp.c:75:14:lwftp_send_next_data 5 +../LWFTP/lwftp.c:103:14:lwftp_data_recv 5 +../LWFTP/lwftp.c:133:14:lwftp_data_sent 2 +../LWFTP/lwftp.c:146:13:lwftp_data_err 3 +../LWFTP/lwftp.c:164:14:lwftp_data_connected 2 +../LWFTP/lwftp.c:180:14:lwftp_data_open 3 +../LWFTP/lwftp.c:216:14:lwftp_send_msg 2 +../LWFTP/lwftp.c:231:13:lwftp_data_close 3 +../LWFTP/lwftp.c:245:13:lwftp_control_close 5 +../LWFTP/lwftp.c:265:13:lwftp_control_process 39 +../LWFTP/lwftp.c:429:13:lwftp_start_RETR 3 +../LWFTP/lwftp.c:446:13:lwftp_start_STOR 3 +../LWFTP/lwftp.c:463:13:lwftp_send_QUIT 2 +../LWFTP/lwftp.c:479:14:lwftp_control_recv 3 +../LWFTP/lwftp.c:503:14:lwftp_control_sent 1 +../LWFTP/lwftp.c:512:13:lwftp_control_err 3 +../LWFTP/lwftp.c:534:14:lwftp_control_connected 3 +../LWFTP/lwftp.c:551:7:lwftp_connect 9 +../LWFTP/lwftp.c:593:7:lwftp_retrieve 7 +../LWFTP/lwftp.c:627:7:lwftp_store 7 +../LWFTP/lwftp.c:677:6:lwftp_close 4 diff --git a/Debug/LWFTP/lwftp.d b/Debug/LWFTP/lwftp.d new file mode 100644 index 0000000..8e91576 --- /dev/null +++ b/Debug/LWFTP/lwftp.d @@ -0,0 +1,123 @@ +LWFTP/lwftp.o: ../LWFTP/lwftp.c ../LWFTP/lwftp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h +../LWFTP/lwftp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h: diff --git a/Debug/LWFTP/lwftp.o b/Debug/LWFTP/lwftp.o new file mode 100644 index 0000000..acdab9b Binary files /dev/null and b/Debug/LWFTP/lwftp.o differ diff --git a/Debug/LWFTP/lwftp.su b/Debug/LWFTP/lwftp.su new file mode 100644 index 0000000..c1c0f2d --- /dev/null +++ b/Debug/LWFTP/lwftp.su @@ -0,0 +1,22 @@ +../LWFTP/lwftp.c:57:14:lwftp_pcb_close 24 static +../LWFTP/lwftp.c:75:14:lwftp_send_next_data 32 static +../LWFTP/lwftp.c:103:14:lwftp_data_recv 32 static +../LWFTP/lwftp.c:133:14:lwftp_data_sent 32 static +../LWFTP/lwftp.c:146:13:lwftp_data_err 24 static +../LWFTP/lwftp.c:164:14:lwftp_data_connected 32 static +../LWFTP/lwftp.c:180:14:lwftp_data_open 48 static +../LWFTP/lwftp.c:216:14:lwftp_send_msg 32 static +../LWFTP/lwftp.c:231:13:lwftp_data_close 16 static +../LWFTP/lwftp.c:245:13:lwftp_control_close 16 static +../LWFTP/lwftp.c:265:13:lwftp_control_process 40 static +../LWFTP/lwftp.c:429:13:lwftp_start_RETR 24 static +../LWFTP/lwftp.c:446:13:lwftp_start_STOR 24 static +../LWFTP/lwftp.c:463:13:lwftp_send_QUIT 24 static +../LWFTP/lwftp.c:479:14:lwftp_control_recv 32 static +../LWFTP/lwftp.c:503:14:lwftp_control_sent 24 static +../LWFTP/lwftp.c:512:13:lwftp_control_err 24 static +../LWFTP/lwftp.c:534:14:lwftp_control_connected 32 static +../LWFTP/lwftp.c:551:7:lwftp_connect 24 static +../LWFTP/lwftp.c:593:7:lwftp_retrieve 24 static +../LWFTP/lwftp.c:627:7:lwftp_store 24 static +../LWFTP/lwftp.c:677:6:lwftp_close 16 static diff --git a/Debug/LWFTP/lwftp_mod.cyclo b/Debug/LWFTP/lwftp_mod.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/LWFTP/lwftp_mod.d b/Debug/LWFTP/lwftp_mod.d new file mode 100644 index 0000000..64751d2 --- /dev/null +++ b/Debug/LWFTP/lwftp_mod.d @@ -0,0 +1 @@ +LWFTP/lwftp_mod.o: ../LWFTP/lwftp_mod.c diff --git a/Debug/LWFTP/lwftp_mod.o b/Debug/LWFTP/lwftp_mod.o new file mode 100644 index 0000000..8b80a07 Binary files /dev/null and b/Debug/LWFTP/lwftp_mod.o differ diff --git a/Debug/LWFTP/lwftp_mod.su b/Debug/LWFTP/lwftp_mod.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/LWFTP/subdir.mk b/Debug/LWFTP/subdir.mk new file mode 100644 index 0000000..b18219d --- /dev/null +++ b/Debug/LWFTP/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../LWFTP/lwftp.c \ +../LWFTP/lwftp_mod.c + +OBJS += \ +./LWFTP/lwftp.o \ +./LWFTP/lwftp_mod.o + +C_DEPS += \ +./LWFTP/lwftp.d \ +./LWFTP/lwftp_mod.d + + +# Each subdirectory must supply rules for building sources it contributes +LWFTP/%.o LWFTP/%.su LWFTP/%.cyclo: ../LWFTP/%.c LWFTP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-LWFTP + +clean-LWFTP: + -$(RM) ./LWFTP/lwftp.cyclo ./LWFTP/lwftp.d ./LWFTP/lwftp.o ./LWFTP/lwftp.su ./LWFTP/lwftp_mod.cyclo ./LWFTP/lwftp_mod.d ./LWFTP/lwftp_mod.o ./LWFTP/lwftp_mod.su + +.PHONY: clean-LWFTP + diff --git a/Debug/LWIP/App/lwip.cyclo b/Debug/LWIP/App/lwip.cyclo new file mode 100644 index 0000000..dada6f4 --- /dev/null +++ b/Debug/LWIP/App/lwip.cyclo @@ -0,0 +1,4 @@ +../LWIP/App/lwip.c:60:6:MX_LWIP_Init 1 +../LWIP/App/lwip.c:118:13:Ethernet_Link_Periodic_Handle 2 +../LWIP/App/lwip.c:144:6:MX_LWIP_Process 1 +../LWIP/App/lwip.c:166:13:ethernet_link_status_updated 1 diff --git a/Debug/LWIP/App/lwip.d b/Debug/LWIP/App/lwip.d new file mode 100644 index 0000000..aec034a --- /dev/null +++ b/Debug/LWIP/App/lwip.d @@ -0,0 +1,127 @@ +LWIP/App/lwip.o: ../LWIP/App/lwip.c ../LWIP/App/lwip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../LWIP/Target/ethernetif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h +../LWIP/App/lwip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../LWIP/Target/ethernetif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/init.h: diff --git a/Debug/LWIP/App/lwip.o b/Debug/LWIP/App/lwip.o new file mode 100644 index 0000000..37c07e4 Binary files /dev/null and b/Debug/LWIP/App/lwip.o differ diff --git a/Debug/LWIP/App/lwip.su b/Debug/LWIP/App/lwip.su new file mode 100644 index 0000000..5f55939 --- /dev/null +++ b/Debug/LWIP/App/lwip.su @@ -0,0 +1,4 @@ +../LWIP/App/lwip.c:60:6:MX_LWIP_Init 24 static +../LWIP/App/lwip.c:118:13:Ethernet_Link_Periodic_Handle 16 static +../LWIP/App/lwip.c:144:6:MX_LWIP_Process 8 static +../LWIP/App/lwip.c:166:13:ethernet_link_status_updated 16 static diff --git a/Debug/LWIP/App/subdir.mk b/Debug/LWIP/App/subdir.mk new file mode 100644 index 0000000..6df08e7 --- /dev/null +++ b/Debug/LWIP/App/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../LWIP/App/lwip.c + +OBJS += \ +./LWIP/App/lwip.o + +C_DEPS += \ +./LWIP/App/lwip.d + + +# Each subdirectory must supply rules for building sources it contributes +LWIP/App/%.o LWIP/App/%.su LWIP/App/%.cyclo: ../LWIP/App/%.c LWIP/App/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-LWIP-2f-App + +clean-LWIP-2f-App: + -$(RM) ./LWIP/App/lwip.cyclo ./LWIP/App/lwip.d ./LWIP/App/lwip.o ./LWIP/App/lwip.su + +.PHONY: clean-LWIP-2f-App + diff --git a/Debug/LWIP/Target/ethernetif.cyclo b/Debug/LWIP/Target/ethernetif.cyclo new file mode 100644 index 0000000..ff08edf --- /dev/null +++ b/Debug/LWIP/Target/ethernetif.cyclo @@ -0,0 +1,18 @@ +../LWIP/Target/ethernetif.c:159:13:low_level_init 2 +../LWIP/Target/ethernetif.c:259:14:low_level_output 5 +../LWIP/Target/ethernetif.c:306:22:low_level_input 2 +../LWIP/Target/ethernetif.c:327:6:ethernetif_input 4 +../LWIP/Target/ethernetif.c:377:7:ethernetif_init 2 +../LWIP/Target/ethernetif.c:428:6:pbuf_free_custom 2 +../LWIP/Target/ethernetif.c:450:7:sys_now 1 +../LWIP/Target/ethernetif.c:463:6:HAL_ETH_MspInit 2 +../LWIP/Target/ethernetif.c:520:6:HAL_ETH_MspDeInit 2 +../LWIP/Target/ethernetif.c:566:9:ETH_PHY_IO_Init 1 +../LWIP/Target/ethernetif.c:583:9:ETH_PHY_IO_DeInit 1 +../LWIP/Target/ethernetif.c:595:9:ETH_PHY_IO_ReadReg 2 +../LWIP/Target/ethernetif.c:612:9:ETH_PHY_IO_WriteReg 2 +../LWIP/Target/ethernetif.c:626:9:ETH_PHY_IO_GetTick 1 +../LWIP/Target/ethernetif.c:635:6:ethernet_link_check_state 10 +../LWIP/Target/ethernetif.c:692:6:HAL_ETH_RxAllocateCallback 2 +../LWIP/Target/ethernetif.c:714:6:HAL_ETH_RxLinkCallback 5 +../LWIP/Target/ethernetif.c:754:6:HAL_ETH_TxFreeCallback 1 diff --git a/Debug/LWIP/Target/ethernetif.d b/Debug/LWIP/Target/ethernetif.d new file mode 100644 index 0000000..113b115 --- /dev/null +++ b/Debug/LWIP/Target/ethernetif.d @@ -0,0 +1,125 @@ +LWIP/Target/ethernetif.o: ../LWIP/Target/ethernetif.c ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h \ + ../LWIP/Target/ethernetif.h ../Drivers/BSP/Components/lan8742/lan8742.h +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/netif/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h: +../LWIP/Target/ethernetif.h: +../Drivers/BSP/Components/lan8742/lan8742.h: diff --git a/Debug/LWIP/Target/ethernetif.o b/Debug/LWIP/Target/ethernetif.o new file mode 100644 index 0000000..1e91acf Binary files /dev/null and b/Debug/LWIP/Target/ethernetif.o differ diff --git a/Debug/LWIP/Target/ethernetif.su b/Debug/LWIP/Target/ethernetif.su new file mode 100644 index 0000000..9df8f41 --- /dev/null +++ b/Debug/LWIP/Target/ethernetif.su @@ -0,0 +1,18 @@ +../LWIP/Target/ethernetif.c:159:13:low_level_init 24 static +../LWIP/Target/ethernetif.c:259:14:low_level_output 80 static +../LWIP/Target/ethernetif.c:306:22:low_level_input 24 static +../LWIP/Target/ethernetif.c:327:6:ethernetif_input 24 static +../LWIP/Target/ethernetif.c:377:7:ethernetif_init 16 static +../LWIP/Target/ethernetif.c:428:6:pbuf_free_custom 24 static +../LWIP/Target/ethernetif.c:450:7:sys_now 8 static +../LWIP/Target/ethernetif.c:463:6:HAL_ETH_MspInit 64 static +../LWIP/Target/ethernetif.c:520:6:HAL_ETH_MspDeInit 16 static +../LWIP/Target/ethernetif.c:566:9:ETH_PHY_IO_Init 8 static +../LWIP/Target/ethernetif.c:583:9:ETH_PHY_IO_DeInit 4 static +../LWIP/Target/ethernetif.c:595:9:ETH_PHY_IO_ReadReg 24 static +../LWIP/Target/ethernetif.c:612:9:ETH_PHY_IO_WriteReg 24 static +../LWIP/Target/ethernetif.c:626:9:ETH_PHY_IO_GetTick 8 static +../LWIP/Target/ethernetif.c:635:6:ethernet_link_check_state 136 static +../LWIP/Target/ethernetif.c:692:6:HAL_ETH_RxAllocateCallback 32 static +../LWIP/Target/ethernetif.c:714:6:HAL_ETH_RxLinkCallback 56 static,ignoring_inline_asm +../LWIP/Target/ethernetif.c:754:6:HAL_ETH_TxFreeCallback 16 static diff --git a/Debug/LWIP/Target/subdir.mk b/Debug/LWIP/Target/subdir.mk new file mode 100644 index 0000000..778e9f6 --- /dev/null +++ b/Debug/LWIP/Target/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../LWIP/Target/ethernetif.c + +OBJS += \ +./LWIP/Target/ethernetif.o + +C_DEPS += \ +./LWIP/Target/ethernetif.d + + +# Each subdirectory must supply rules for building sources it contributes +LWIP/Target/%.o LWIP/Target/%.su LWIP/Target/%.cyclo: ../LWIP/Target/%.c LWIP/Target/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-LWIP-2f-Target + +clean-LWIP-2f-Target: + -$(RM) ./LWIP/Target/ethernetif.cyclo ./LWIP/Target/ethernetif.d ./LWIP/Target/ethernetif.o ./LWIP/Target/ethernetif.su + +.PHONY: clean-LWIP-2f-Target + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d new file mode 100644 index 0000000..2cd56d6 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/api/api_lib.o: \ + ../Middlewares/Third_Party/LwIP/src/api/api_lib.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o new file mode 100644 index 0000000..bee5e94 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su b/Debug/Middlewares/Third_Party/LwIP/src/api/api_lib.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d new file mode 100644 index 0000000..decb0a2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/api/api_msg.o: \ + ../Middlewares/Third_Party/LwIP/src/api/api_msg.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o new file mode 100644 index 0000000..6e28aec Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su b/Debug/Middlewares/Third_Party/LwIP/src/api/api_msg.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo new file mode 100644 index 0000000..101b8a9 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/err.cyclo @@ -0,0 +1 @@ +../Middlewares/Third_Party/LwIP/src/api/err.c:107:1:lwip_strerr 3 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.d b/Debug/Middlewares/Third_Party/LwIP/src/api/err.d new file mode 100644 index 0000000..e0db62c --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/err.d @@ -0,0 +1,83 @@ +Middlewares/Third_Party/LwIP/src/api/err.o: \ + ../Middlewares/Third_Party/LwIP/src/api/err.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/errno.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.o b/Debug/Middlewares/Third_Party/LwIP/src/api/err.o new file mode 100644 index 0000000..bd9999e Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/err.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/err.su b/Debug/Middlewares/Third_Party/LwIP/src/api/err.su new file mode 100644 index 0000000..2da5ed9 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/err.su @@ -0,0 +1 @@ +../Middlewares/Third_Party/LwIP/src/api/err.c:107:1:lwip_strerr 16 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d new file mode 100644 index 0000000..19f70c5 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/api/if_api.o: \ + ../Middlewares/Third_Party/LwIP/src/api/if_api.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o new file mode 100644 index 0000000..ef2530e Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su b/Debug/Middlewares/Third_Party/LwIP/src/api/if_api.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d new file mode 100644 index 0000000..5befdb1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/api/netbuf.o: \ + ../Middlewares/Third_Party/LwIP/src/api/netbuf.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o new file mode 100644 index 0000000..a0fd983 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su b/Debug/Middlewares/Third_Party/LwIP/src/api/netbuf.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d new file mode 100644 index 0000000..e5f5695 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/api/netdb.o: \ + ../Middlewares/Third_Party/LwIP/src/api/netdb.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o new file mode 100644 index 0000000..66609f9 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.su b/Debug/Middlewares/Third_Party/LwIP/src/api/netdb.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d new file mode 100644 index 0000000..0d5dba5 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/api/netifapi.o: \ + ../Middlewares/Third_Party/LwIP/src/api/netifapi.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o new file mode 100644 index 0000000..bab5811 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.su b/Debug/Middlewares/Third_Party/LwIP/src/api/netifapi.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d new file mode 100644 index 0000000..a7bcb90 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/api/sockets.o: \ + ../Middlewares/Third_Party/LwIP/src/api/sockets.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o new file mode 100644 index 0000000..8d6e872 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su b/Debug/Middlewares/Third_Party/LwIP/src/api/sockets.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk new file mode 100644 index 0000000..2035083 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/api/api_lib.c \ +../Middlewares/Third_Party/LwIP/src/api/api_msg.c \ +../Middlewares/Third_Party/LwIP/src/api/err.c \ +../Middlewares/Third_Party/LwIP/src/api/if_api.c \ +../Middlewares/Third_Party/LwIP/src/api/netbuf.c \ +../Middlewares/Third_Party/LwIP/src/api/netdb.c \ +../Middlewares/Third_Party/LwIP/src/api/netifapi.c \ +../Middlewares/Third_Party/LwIP/src/api/sockets.c \ +../Middlewares/Third_Party/LwIP/src/api/tcpip.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/api/api_lib.o \ +./Middlewares/Third_Party/LwIP/src/api/api_msg.o \ +./Middlewares/Third_Party/LwIP/src/api/err.o \ +./Middlewares/Third_Party/LwIP/src/api/if_api.o \ +./Middlewares/Third_Party/LwIP/src/api/netbuf.o \ +./Middlewares/Third_Party/LwIP/src/api/netdb.o \ +./Middlewares/Third_Party/LwIP/src/api/netifapi.o \ +./Middlewares/Third_Party/LwIP/src/api/sockets.o \ +./Middlewares/Third_Party/LwIP/src/api/tcpip.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/api/api_lib.d \ +./Middlewares/Third_Party/LwIP/src/api/api_msg.d \ +./Middlewares/Third_Party/LwIP/src/api/err.d \ +./Middlewares/Third_Party/LwIP/src/api/if_api.d \ +./Middlewares/Third_Party/LwIP/src/api/netbuf.d \ +./Middlewares/Third_Party/LwIP/src/api/netdb.d \ +./Middlewares/Third_Party/LwIP/src/api/netifapi.d \ +./Middlewares/Third_Party/LwIP/src/api/sockets.d \ +./Middlewares/Third_Party/LwIP/src/api/tcpip.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/api/%.o Middlewares/Third_Party/LwIP/src/api/%.su Middlewares/Third_Party/LwIP/src/api/%.cyclo: ../Middlewares/Third_Party/LwIP/src/api/%.c Middlewares/Third_Party/LwIP/src/api/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-api + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-api: + -$(RM) ./Middlewares/Third_Party/LwIP/src/api/api_lib.cyclo ./Middlewares/Third_Party/LwIP/src/api/api_lib.d ./Middlewares/Third_Party/LwIP/src/api/api_lib.o ./Middlewares/Third_Party/LwIP/src/api/api_lib.su ./Middlewares/Third_Party/LwIP/src/api/api_msg.cyclo ./Middlewares/Third_Party/LwIP/src/api/api_msg.d ./Middlewares/Third_Party/LwIP/src/api/api_msg.o ./Middlewares/Third_Party/LwIP/src/api/api_msg.su ./Middlewares/Third_Party/LwIP/src/api/err.cyclo ./Middlewares/Third_Party/LwIP/src/api/err.d ./Middlewares/Third_Party/LwIP/src/api/err.o ./Middlewares/Third_Party/LwIP/src/api/err.su ./Middlewares/Third_Party/LwIP/src/api/if_api.cyclo ./Middlewares/Third_Party/LwIP/src/api/if_api.d ./Middlewares/Third_Party/LwIP/src/api/if_api.o ./Middlewares/Third_Party/LwIP/src/api/if_api.su ./Middlewares/Third_Party/LwIP/src/api/netbuf.cyclo ./Middlewares/Third_Party/LwIP/src/api/netbuf.d ./Middlewares/Third_Party/LwIP/src/api/netbuf.o ./Middlewares/Third_Party/LwIP/src/api/netbuf.su ./Middlewares/Third_Party/LwIP/src/api/netdb.cyclo ./Middlewares/Third_Party/LwIP/src/api/netdb.d ./Middlewares/Third_Party/LwIP/src/api/netdb.o ./Middlewares/Third_Party/LwIP/src/api/netdb.su ./Middlewares/Third_Party/LwIP/src/api/netifapi.cyclo ./Middlewares/Third_Party/LwIP/src/api/netifapi.d ./Middlewares/Third_Party/LwIP/src/api/netifapi.o ./Middlewares/Third_Party/LwIP/src/api/netifapi.su ./Middlewares/Third_Party/LwIP/src/api/sockets.cyclo ./Middlewares/Third_Party/LwIP/src/api/sockets.d ./Middlewares/Third_Party/LwIP/src/api/sockets.o ./Middlewares/Third_Party/LwIP/src/api/sockets.su ./Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo ./Middlewares/Third_Party/LwIP/src/api/tcpip.d ./Middlewares/Third_Party/LwIP/src/api/tcpip.o ./Middlewares/Third_Party/LwIP/src/api/tcpip.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-api + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d new file mode 100644 index 0000000..39fd54e --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/api/tcpip.o: \ + ../Middlewares/Third_Party/LwIP/src/api/tcpip.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o new file mode 100644 index 0000000..fb6f89b Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su b/Debug/Middlewares/Third_Party/LwIP/src/api/tcpip.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo new file mode 100644 index 0000000..f56fde8 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo @@ -0,0 +1,39 @@ +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:153:1:mqtt_msg_type_to_str 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:170:1:msg_generate_packet_id 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:184:1:mqtt_ringbuf_put 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:195:1:mqtt_ringbuf_get_ptr 1 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:201:1:mqtt_ringbuf_advance_get_idx 3 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:213:1:mqtt_ringbuf_len 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:234:1:mqtt_output_send 13 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:287:1:mqtt_create_request 4 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:313:1:mqtt_append_request 5 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:342:1:mqtt_delete_request 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:356:1:mqtt_take_request 7 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:391:1:mqtt_request_time_elapsed 6 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:420:1:mqtt_clear_requests 3 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:436:1:mqtt_init_requests 3 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:451:1:mqtt_output_append_u8 1 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:457:6:mqtt_output_append_u16 1 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:464:1:mqtt_output_append_buf 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:473:1:mqtt_output_append_string 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:494:1:mqtt_output_append_fixed_header 3 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:514:1:mqtt_output_check_space 3 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:537:1:mqtt_close 6 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:576:1:mqtt_cyclic_timer 10 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:635:1:pub_ack_rec_rel_response 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:656:1:mqtt_incomming_suback 3 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:672:1:mqtt_message_received 38 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:839:1:mqtt_parse_incoming 14 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:932:1:mqtt_tcp_recv_cb 7 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:976:1:mqtt_tcp_sent_cb 4 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1009:1:mqtt_tcp_err_cb 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1027:1:mqtt_tcp_poll_cb 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1044:1:mqtt_tcp_connect_cb 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1097:1:mqtt_publish 12 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1173:1:mqtt_sub_unsub 11 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1238:1:mqtt_set_inpub_callback 2 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1254:1:mqtt_client_new 1 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1266:1:mqtt_client_free 1 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1283:1:mqtt_client_connect 30 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1437:1:mqtt_disconnect 3 +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1456:1:mqtt_client_is_connected 2 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d new file mode 100644 index 0000000..3fc744a --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d @@ -0,0 +1,137 @@ +Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o: \ + ../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h +../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o new file mode 100644 index 0000000..1f0dd59 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su new file mode 100644 index 0000000..837ac47 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su @@ -0,0 +1,39 @@ +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:153:1:mqtt_msg_type_to_str 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:170:1:msg_generate_packet_id 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:184:1:mqtt_ringbuf_put 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:195:1:mqtt_ringbuf_get_ptr 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:201:1:mqtt_ringbuf_advance_get_idx 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:213:1:mqtt_ringbuf_len 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:234:1:mqtt_output_send 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:287:1:mqtt_create_request 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:313:1:mqtt_append_request 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:342:1:mqtt_delete_request 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:356:1:mqtt_take_request 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:391:1:mqtt_request_time_elapsed 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:420:1:mqtt_clear_requests 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:436:1:mqtt_init_requests 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:451:1:mqtt_output_append_u8 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:457:6:mqtt_output_append_u16 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:464:1:mqtt_output_append_buf 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:473:1:mqtt_output_append_string 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:494:1:mqtt_output_append_fixed_header 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:514:1:mqtt_output_check_space 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:537:1:mqtt_close 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:576:1:mqtt_cyclic_timer 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:635:1:pub_ack_rec_rel_response 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:656:1:mqtt_incomming_suback 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:672:1:mqtt_message_received 72 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:839:1:mqtt_parse_incoming 40 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:932:1:mqtt_tcp_recv_cb 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:976:1:mqtt_tcp_sent_cb 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1009:1:mqtt_tcp_err_cb 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1027:1:mqtt_tcp_poll_cb 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1044:1:mqtt_tcp_connect_cb 32 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1097:1:mqtt_publish 56 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1173:1:mqtt_sub_unsub 56 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1238:1:mqtt_set_inpub_callback 24 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1254:1:mqtt_client_new 8 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1266:1:mqtt_client_free 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1283:1:mqtt_client_connect 56 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1437:1:mqtt_disconnect 16 static +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c:1456:1:mqtt_client_is_connected 16 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk new file mode 100644 index 0000000..1fef600 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/apps/mqtt/%.o Middlewares/Third_Party/LwIP/src/apps/mqtt/%.su Middlewares/Third_Party/LwIP/src/apps/mqtt/%.cyclo: ../Middlewares/Third_Party/LwIP/src/apps/mqtt/%.c Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-apps-2f-mqtt + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-apps-2f-mqtt: + -$(RM) ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.cyclo ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.d ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-apps-2f-mqtt + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d new file mode 100644 index 0000000..a7f8a88 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/altcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/altcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o new file mode 100644 index 0000000..d0e77ef Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d new file mode 100644 index 0000000..976d0a7 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o: \ + ../Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o new file mode 100644 index 0000000..f97882e Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.su b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d new file mode 100644 index 0000000..86bddf2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o new file mode 100644 index 0000000..af2ba03 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/def.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/def.cyclo new file mode 100644 index 0000000..850ccb0 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/def.cyclo @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/def.c:76:1:lwip_htons 1 +../Middlewares/Third_Party/LwIP/src/core/def.c:90:1:lwip_htonl 1 +../Middlewares/Third_Party/LwIP/src/core/def.c:105:1:lwip_strnstr 6 +../Middlewares/Third_Party/LwIP/src/core/def.c:128:1:lwip_stricmp 6 +../Middlewares/Third_Party/LwIP/src/core/def.c:163:1:lwip_strnicmp 7 +../Middlewares/Third_Party/LwIP/src/core/def.c:199:1:lwip_itoa 8 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/def.d b/Debug/Middlewares/Third_Party/LwIP/src/core/def.d new file mode 100644 index 0000000..781810e --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/def.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/core/def.o: \ + ../Middlewares/Third_Party/LwIP/src/core/def.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/def.o b/Debug/Middlewares/Third_Party/LwIP/src/core/def.o new file mode 100644 index 0000000..495996c Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/def.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/def.su b/Debug/Middlewares/Third_Party/LwIP/src/core/def.su new file mode 100644 index 0000000..ddb6a0a --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/def.su @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/def.c:76:1:lwip_htons 16 static +../Middlewares/Third_Party/LwIP/src/core/def.c:90:1:lwip_htonl 16 static +../Middlewares/Third_Party/LwIP/src/core/def.c:105:1:lwip_strnstr 32 static +../Middlewares/Third_Party/LwIP/src/core/def.c:128:1:lwip_stricmp 24 static +../Middlewares/Third_Party/LwIP/src/core/def.c:163:1:lwip_strnicmp 32 static +../Middlewares/Third_Party/LwIP/src/core/def.c:199:1:lwip_itoa 40 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d new file mode 100644 index 0000000..59461ca --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/dns.o: \ + ../Middlewares/Third_Party/LwIP/src/core/dns.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o new file mode 100644 index 0000000..c5e0368 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/dns.su b/Debug/Middlewares/Third_Party/LwIP/src/core/dns.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo new file mode 100644 index 0000000..f1af66f --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo @@ -0,0 +1,9 @@ +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:133:1:lwip_standard_chksum 6 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:260:1:inet_cksum_pseudo_base 4 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:310:1:inet_chksum_pseudo 1 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:379:1:ip_chksum_pseudo 1 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:399:1:inet_cksum_pseudo_partial_base 7 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:456:1:inet_chksum_pseudo_partial 1 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:526:1:ip_chksum_pseudo_partial 1 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:555:1:inet_chksum 1 +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:568:1:inet_chksum_pbuf 4 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d new file mode 100644 index 0000000..9f4b81c --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/core/inet_chksum.o: \ + ../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o new file mode 100644 index 0000000..2d6b31a Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.su b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.su new file mode 100644 index 0000000..f49ae34 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/inet_chksum.su @@ -0,0 +1,9 @@ +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:133:1:lwip_standard_chksum 40 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:260:1:inet_cksum_pseudo_base 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:310:1:inet_chksum_pseudo 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:379:1:ip_chksum_pseudo 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:399:1:inet_cksum_pseudo_partial_base 40 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:456:1:inet_chksum_pseudo_partial 40 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:526:1:ip_chksum_pseudo_partial 32 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:555:1:inet_chksum 16 static +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c:568:1:inet_chksum_pbuf 32 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/init.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/init.cyclo new file mode 100644 index 0000000..ab7904d --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/init.cyclo @@ -0,0 +1 @@ +../Middlewares/Third_Party/LwIP/src/core/init.c:332:1:lwip_init 1 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/init.d b/Debug/Middlewares/Third_Party/LwIP/src/core/init.d new file mode 100644 index 0000000..52876f1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/init.d @@ -0,0 +1,161 @@ +Middlewares/Third_Party/LwIP/src/core/init.o: \ + ../Middlewares/Third_Party/LwIP/src/core/init.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/init.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/init.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/init.o b/Debug/Middlewares/Third_Party/LwIP/src/core/init.o new file mode 100644 index 0000000..539d3c4 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/init.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/init.su b/Debug/Middlewares/Third_Party/LwIP/src/core/init.su new file mode 100644 index 0000000..2da7773 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/init.su @@ -0,0 +1 @@ +../Middlewares/Third_Party/LwIP/src/core/init.c:332:1:lwip_init 16 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d new file mode 100644 index 0000000..c716f08 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.d @@ -0,0 +1,113 @@ +Middlewares/Third_Party/LwIP/src/core/ip.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ip.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o new file mode 100644 index 0000000..e74c7ba Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ip.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ip.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d new file mode 100644 index 0000000..5b1256f --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o new file mode 100644 index 0000000..b789018 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d new file mode 100644 index 0000000..045290c --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o new file mode 100644 index 0000000..0d7a151 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo new file mode 100644 index 0000000..785b548 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo @@ -0,0 +1,14 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:168:1:etharp_free_entry 2 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:197:1:etharp_tmr 9 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:256:1:etharp_find_entry 29 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:422:1:etharp_update_arp_entry 8 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:559:1:etharp_cleanup_netif 4 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:583:1:etharp_find_addr 5 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:612:1:etharp_get_entry 6 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:641:1:etharp_input 11 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:748:1:etharp_output_to_arp_index 7 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:791:1:etharp_output 16 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:933:1:etharp_query 23 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1101:1:etharp_raw 5 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1181:1:etharp_request_dst 1 +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1198:1:etharp_request 1 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d new file mode 100644 index 0000000..97047f2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d @@ -0,0 +1,125 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o new file mode 100644 index 0000000..e7dd609 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su new file mode 100644 index 0000000..1528cfc --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su @@ -0,0 +1,14 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:168:1:etharp_free_entry 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:197:1:etharp_tmr 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:256:1:etharp_find_entry 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:422:1:etharp_update_arp_entry 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:559:1:etharp_cleanup_netif 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:583:1:etharp_find_addr 32 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:612:1:etharp_get_entry 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:641:1:etharp_input 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:748:1:etharp_output_to_arp_index 32 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:791:1:etharp_output 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:933:1:etharp_query 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1101:1:etharp_raw 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1181:1:etharp_request_dst 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c:1198:1:etharp_request 16 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo new file mode 100644 index 0000000..4b9308c --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo @@ -0,0 +1,4 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:80:1:icmp_input 19 +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:308:1:icmp_dest_unreach 1 +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:323:1:icmp_time_exceeded 1 +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:340:1:icmp_send_response 4 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d new file mode 100644 index 0000000..c4579a9 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d @@ -0,0 +1,119 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o new file mode 100644 index 0000000..c846bb4 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su new file mode 100644 index 0000000..ff5baf3 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su @@ -0,0 +1,4 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:80:1:icmp_input 64 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:308:1:icmp_dest_unreach 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:323:1:icmp_time_exceeded 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c:340:1:icmp_send_response 56 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d new file mode 100644 index 0000000..2711320 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o new file mode 100644 index 0000000..4ee6e6a Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo new file mode 100644 index 0000000..b989d17 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:152:1:ip4_route 13 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:374:1:ip4_input_accept 5 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:426:1:ip4_input 25 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:787:1:ip4_output_if 4 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:827:1:ip4_output_if_src 9 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:1028:1:ip4_output 3 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d new file mode 100644 index 0000000..6cd3580 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d @@ -0,0 +1,141 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o new file mode 100644 index 0000000..79a8149 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su new file mode 100644 index 0000000..1b750df --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:152:1:ip4_route 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:374:1:ip4_input_accept 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:426:1:ip4_input 32 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:787:1:ip4_output_if 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:827:1:ip4_output_if_src 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c:1028:1:ip4_output 48 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo new file mode 100644 index 0000000..58c5231 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:58:1:ip4_addr_isbroadcast_u32 7 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:93:1:ip4_addr_netmask_valid 5 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:123:1:ipaddr_addr 2 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:145:1:ip4addr_aton 28 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:267:1:ip4addr_ntoa 1 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:283:1:ip4addr_ntoa_r 6 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d new file mode 100644 index 0000000..ebf7acd --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d @@ -0,0 +1,103 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o new file mode 100644 index 0000000..ea7e853 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su new file mode 100644 index 0000000..c8832bb --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:58:1:ip4_addr_isbroadcast_u32 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:93:1:ip4_addr_netmask_valid 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:123:1:ipaddr_addr 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:145:1:ip4addr_aton 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:267:1:ip4addr_ntoa 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c:283:1:ip4addr_ntoa_r 56 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo new file mode 100644 index 0000000..b6d3020 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:128:1:ip_reass_tmr 3 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:164:1:ip_reass_free_complete_datagram 9 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:227:1:ip_reass_remove_oldest_datagram 11 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:278:1:ip_reass_enqueue_new_datagram 4 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:317:1:ip_reass_dequeue_datagram 3 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:344:1:ip_reass_chain_frag_into_datagram_and_validate 30 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:503:1:ip4_reass 28 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:699:1:ip_frag_alloc_pbuf_custom_ref 1 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:706:1:ip_frag_free_pbuf_custom_ref 2 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:715:1:ipfrag_free_pbuf_custom 4 +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:740:1:ip4_frag 15 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d new file mode 100644 index 0000000..1b5ee90 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d @@ -0,0 +1,121 @@ +Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o new file mode 100644 index 0000000..77e1af3 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su new file mode 100644 index 0000000..e7ecbae --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:128:1:ip_reass_tmr 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:164:1:ip_reass_free_complete_datagram 40 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:227:1:ip_reass_remove_oldest_datagram 48 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:278:1:ip_reass_enqueue_new_datagram 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:317:1:ip_reass_dequeue_datagram 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:344:1:ip_reass_chain_frag_into_datagram_and_validate 56 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:503:1:ip4_reass 64 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:699:1:ip_frag_alloc_pbuf_custom_ref 8 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:706:1:ip_frag_free_pbuf_custom_ref 16 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:715:1:ipfrag_free_pbuf_custom 24 static +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c:740:1:ip4_frag 88 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk new file mode 100644 index 0000000..89cd3dc --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/core/ipv4/%.o Middlewares/Third_Party/LwIP/src/core/ipv4/%.su Middlewares/Third_Party/LwIP/src/core/ipv4/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/ipv4/%.c Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv4 + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv4: + -$(RM) ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.su ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.d ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o ./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv4 + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d new file mode 100644 index 0000000..1df6c13 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o new file mode 100644 index 0000000..a31bb80 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d new file mode 100644 index 0000000..1795d63 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o new file mode 100644 index 0000000..ab0e3c1 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d new file mode 100644 index 0000000..cc3d9e6 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o new file mode 100644 index 0000000..e648dd0 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d new file mode 100644 index 0000000..b3446db --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o new file mode 100644 index 0000000..0279f10 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d new file mode 100644 index 0000000..8bf53c7 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o new file mode 100644 index 0000000..89b3c1a Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d new file mode 100644 index 0000000..8347601 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o new file mode 100644 index 0000000..f316741 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d new file mode 100644 index 0000000..2c1e0c6 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d @@ -0,0 +1,121 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o new file mode 100644 index 0000000..2881bcc Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d new file mode 100644 index 0000000..90ecb24 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o new file mode 100644 index 0000000..4938a51 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d new file mode 100644 index 0000000..54e2af6 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o: \ + ../Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o new file mode 100644 index 0000000..054ddb2 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.su b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk new file mode 100644 index 0000000..60ec069 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c \ +../Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d \ +./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/core/ipv6/%.o Middlewares/Third_Party/LwIP/src/core/ipv6/%.su Middlewares/Third_Party/LwIP/src/core/ipv6/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/ipv6/%.c Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv6 + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv6: + -$(RM) ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.su ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.cyclo ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.d ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o ./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core-2f-ipv6 + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo new file mode 100644 index 0000000..63b0381 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.cyclo @@ -0,0 +1,9 @@ +../Middlewares/Third_Party/LwIP/src/core/mem.c:451:1:ptr_to_mem 1 +../Middlewares/Third_Party/LwIP/src/core/mem.c:457:1:mem_to_ptr 1 +../Middlewares/Third_Party/LwIP/src/core/mem.c:474:1:plug_holes 14 +../Middlewares/Third_Party/LwIP/src/core/mem.c:516:1:mem_init 1 +../Middlewares/Third_Party/LwIP/src/core/mem.c:551:1:mem_link_valid 7 +../Middlewares/Third_Party/LwIP/src/core/mem.c:617:1:mem_free 8 +../Middlewares/Third_Party/LwIP/src/core/mem.c:699:1:mem_trim 19 +../Middlewares/Third_Party/LwIP/src/core/mem.c:831:1:mem_malloc 19 +../Middlewares/Third_Party/LwIP/src/core/mem.c:999:1:mem_calloc 3 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d new file mode 100644 index 0000000..8a23b73 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.d @@ -0,0 +1,93 @@ +Middlewares/Third_Party/LwIP/src/core/mem.o: \ + ../Middlewares/Third_Party/LwIP/src/core/mem.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o new file mode 100644 index 0000000..7eb6767 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su new file mode 100644 index 0000000..67591ad --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/mem.su @@ -0,0 +1,9 @@ +../Middlewares/Third_Party/LwIP/src/core/mem.c:451:1:ptr_to_mem 16 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:457:1:mem_to_ptr 16 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:474:1:plug_holes 32 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:516:1:mem_init 16 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:551:1:mem_link_valid 32 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:617:1:mem_free 24 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:699:1:mem_trim 40 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:831:1:mem_malloc 40 static +../Middlewares/Third_Party/LwIP/src/core/mem.c:999:1:mem_calloc 24 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.cyclo new file mode 100644 index 0000000..cc5be74 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.cyclo @@ -0,0 +1,8 @@ +../Middlewares/Third_Party/LwIP/src/core/memp.c:175:1:memp_init_pool 2 +../Middlewares/Third_Party/LwIP/src/core/memp.c:224:1:memp_init 2 +../Middlewares/Third_Party/LwIP/src/core/memp.c:245:1:do_memp_malloc_pool 3 +../Middlewares/Third_Party/LwIP/src/core/memp.c:311:1:memp_malloc_pool 3 +../Middlewares/Third_Party/LwIP/src/core/memp.c:337:1:memp_malloc 2 +../Middlewares/Third_Party/LwIP/src/core/memp.c:359:1:do_memp_free_pool 2 +../Middlewares/Third_Party/LwIP/src/core/memp.c:403:1:memp_free_pool 4 +../Middlewares/Third_Party/LwIP/src/core/memp.c:420:1:memp_free 3 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d new file mode 100644 index 0000000..331fecd --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.d @@ -0,0 +1,171 @@ +Middlewares/Third_Party/LwIP/src/core/memp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/memp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/api.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/raw.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/api.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o new file mode 100644 index 0000000..4d887b6 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/memp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.su new file mode 100644 index 0000000..822791f --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/memp.su @@ -0,0 +1,8 @@ +../Middlewares/Third_Party/LwIP/src/core/memp.c:175:1:memp_init_pool 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:224:1:memp_init 16 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:245:1:do_memp_malloc_pool 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:311:1:memp_malloc_pool 16 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:337:1:memp_malloc 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:359:1:do_memp_free_pool 24 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:403:1:memp_free_pool 16 static +../Middlewares/Third_Party/LwIP/src/core/memp.c:420:1:memp_free 16 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.cyclo new file mode 100644 index 0000000..6ad03fd --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.cyclo @@ -0,0 +1,25 @@ +../Middlewares/Third_Party/LwIP/src/core/netif.c:177:1:netif_init 1 +../Middlewares/Third_Party/LwIP/src/core/netif.c:217:1:netif_input 4 +../Middlewares/Third_Party/LwIP/src/core/netif.c:239:1:netif_add_noaddr 1 +../Middlewares/Third_Party/LwIP/src/core/netif.c:276:1:netif_add 26 +../Middlewares/Third_Party/LwIP/src/core/netif.c:442:1:netif_do_ip_addr_changed 1 +../Middlewares/Third_Party/LwIP/src/core/netif.c:457:1:netif_do_set_ipaddr 5 +../Middlewares/Third_Party/LwIP/src/core/netif.c:500:1:netif_set_ipaddr 3 +../Middlewares/Third_Party/LwIP/src/core/netif.c:523:1:netif_do_set_netmask 3 +../Middlewares/Third_Party/LwIP/src/core/netif.c:560:1:netif_set_netmask 3 +../Middlewares/Third_Party/LwIP/src/core/netif.c:587:1:netif_do_set_gw 3 +../Middlewares/Third_Party/LwIP/src/core/netif.c:621:1:netif_set_gw 3 +../Middlewares/Third_Party/LwIP/src/core/netif.c:658:1:netif_set_addr 8 +../Middlewares/Third_Party/LwIP/src/core/netif.c:737:1:netif_remove 9 +../Middlewares/Third_Party/LwIP/src/core/netif.c:822:1:netif_set_default 3 +../Middlewares/Third_Party/LwIP/src/core/netif.c:844:1:netif_set_up 3 +../Middlewares/Third_Party/LwIP/src/core/netif.c:875:1:netif_issue_reports 7 +../Middlewares/Third_Party/LwIP/src/core/netif.c:919:1:netif_set_down 4 +../Middlewares/Third_Party/LwIP/src/core/netif.c:988:1:netif_set_link_up 4 +../Middlewares/Third_Party/LwIP/src/core/netif.c:1026:1:netif_set_link_down 4 +../Middlewares/Third_Party/LwIP/src/core/netif.c:1051:1:netif_set_link_callback 2 +../Middlewares/Third_Party/LwIP/src/core/netif.c:1619:1:netif_null_output_ip4 1 +../Middlewares/Third_Party/LwIP/src/core/netif.c:1637:1:netif_name_to_index 2 +../Middlewares/Third_Party/LwIP/src/core/netif.c:1656:1:netif_index_to_name 2 +../Middlewares/Third_Party/LwIP/src/core/netif.c:1676:1:netif_get_by_index 4 +../Middlewares/Third_Party/LwIP/src/core/netif.c:1701:1:netif_find 6 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d new file mode 100644 index 0000000..782f977 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.d @@ -0,0 +1,147 @@ +Middlewares/Third_Party/LwIP/src/core/netif.o: \ + ../Middlewares/Third_Party/LwIP/src/core/netif.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + 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+../Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o new file mode 100644 index 0000000..751692a Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/netif.su b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.su new file mode 100644 index 0000000..d9b9c53 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/netif.su @@ -0,0 +1,25 @@ +../Middlewares/Third_Party/LwIP/src/core/netif.c:177:1:netif_init 4 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:217:1:netif_input 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:239:1:netif_add_noaddr 40 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:276:1:netif_add 40 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:442:1:netif_do_ip_addr_changed 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:457:1:netif_do_set_ipaddr 32 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:500:1:netif_set_ipaddr 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:523:1:netif_do_set_netmask 48 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:560:1:netif_set_netmask 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:587:1:netif_do_set_gw 48 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:621:1:netif_set_gw 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:658:1:netif_set_addr 40 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:737:1:netif_remove 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:822:1:netif_set_default 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:844:1:netif_set_up 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:875:1:netif_issue_reports 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:919:1:netif_set_down 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:988:1:netif_set_link_up 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1026:1:netif_set_link_down 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1051:1:netif_set_link_callback 16 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1619:1:netif_null_output_ip4 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1637:1:netif_name_to_index 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1656:1:netif_index_to_name 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1676:1:netif_get_by_index 24 static +../Middlewares/Third_Party/LwIP/src/core/netif.c:1701:1:netif_find 24 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo new file mode 100644 index 0000000..f358553 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo @@ -0,0 +1,36 @@ +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:128:1:pbuf_free_ooseq 3 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:157:1:pbuf_pool_is_empty 1 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:179:1:pbuf_init_alloced_pbuf 1 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:224:1:pbuf_alloc 17 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:327:1:pbuf_alloc_reference 4 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:363:1:pbuf_alloced_custom 3 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+../Middlewares/Third_Party/LwIP/src/core/pbuf.c:895:1:pbuf_chain 1 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:912:1:pbuf_dechain 5 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:961:1:pbuf_copy 18 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1027:1:pbuf_copy_partial 8 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1074:1:pbuf_get_contiguous 7 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1152:1:pbuf_skip_const 4 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1178:1:pbuf_skip 1 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1196:1:pbuf_take 12 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1240:1:pbuf_take_at 6 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1278:1:pbuf_coalesce 3 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1306:1:pbuf_clone 3 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1371:1:pbuf_get_at 2 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1389:1:pbuf_try_get_at 3 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1411:1:pbuf_put_at 3 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1434:1:pbuf_memcmp 6 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1476:1:pbuf_memfind 4 +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1503:1:pbuf_strstr 5 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d new file mode 100644 index 0000000..0d817c8 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.d @@ -0,0 +1,127 @@ +Middlewares/Third_Party/LwIP/src/core/pbuf.o: \ + ../Middlewares/Third_Party/LwIP/src/core/pbuf.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + 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+../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o new file mode 100644 index 0000000..4419ef6 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su new file mode 100644 index 0000000..7ff14ea --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/pbuf.su @@ -0,0 +1,36 @@ +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:128:1:pbuf_free_ooseq 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:157:1:pbuf_pool_is_empty 4 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:179:1:pbuf_init_alloced_pbuf 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:224:1:pbuf_alloc 56 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:327:1:pbuf_alloc_reference 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:363:1:pbuf_alloced_custom 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:402:1:pbuf_realloc 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:473:1:pbuf_add_header_impl 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:551:1:pbuf_add_header 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:561:1:pbuf_add_header_force 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:582:1:pbuf_remove_header 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:616:1:pbuf_header_impl 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:646:1:pbuf_header 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:656:1:pbuf_header_force 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:671:1:pbuf_free_header 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:725:1:pbuf_free 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:809:1:pbuf_clen 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:829:1:pbuf_ref 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:853:1:pbuf_cat 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:895:1:pbuf_chain 16 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:912:1:pbuf_dechain 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:961:1:pbuf_copy 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1027:1:pbuf_copy_partial 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1074:1:pbuf_get_contiguous 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1152:1:pbuf_skip_const 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1178:1:pbuf_skip 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1196:1:pbuf_take 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1240:1:pbuf_take_at 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1278:1:pbuf_coalesce 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1306:1:pbuf_clone 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1371:1:pbuf_get_at 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1389:1:pbuf_try_get_at 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1411:1:pbuf_put_at 24 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1434:1:pbuf_memcmp 40 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1476:1:pbuf_memfind 32 static +../Middlewares/Third_Party/LwIP/src/core/pbuf.c:1503:1:pbuf_strstr 24 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d new file mode 100644 index 0000000..bf86a33 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/raw.o: \ + ../Middlewares/Third_Party/LwIP/src/core/raw.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o new file mode 100644 index 0000000..f9db435 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/raw.su b/Debug/Middlewares/Third_Party/LwIP/src/core/raw.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d new file mode 100644 index 0000000..3326bef --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.d @@ -0,0 +1,75 @@ +Middlewares/Third_Party/LwIP/src/core/stats.o: \ + ../Middlewares/Third_Party/LwIP/src/core/stats.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o new file mode 100644 index 0000000..8d53158 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/stats.su b/Debug/Middlewares/Third_Party/LwIP/src/core/stats.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk new file mode 100644 index 0000000..3d642f1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/subdir.mk @@ -0,0 +1,84 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/core/altcp.c \ +../Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c \ +../Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c \ +../Middlewares/Third_Party/LwIP/src/core/def.c \ +../Middlewares/Third_Party/LwIP/src/core/dns.c \ +../Middlewares/Third_Party/LwIP/src/core/inet_chksum.c \ +../Middlewares/Third_Party/LwIP/src/core/init.c \ +../Middlewares/Third_Party/LwIP/src/core/ip.c \ +../Middlewares/Third_Party/LwIP/src/core/mem.c \ +../Middlewares/Third_Party/LwIP/src/core/memp.c \ +../Middlewares/Third_Party/LwIP/src/core/netif.c \ +../Middlewares/Third_Party/LwIP/src/core/pbuf.c \ +../Middlewares/Third_Party/LwIP/src/core/raw.c \ +../Middlewares/Third_Party/LwIP/src/core/stats.c \ +../Middlewares/Third_Party/LwIP/src/core/sys.c \ +../Middlewares/Third_Party/LwIP/src/core/tcp.c \ +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c \ +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c \ +../Middlewares/Third_Party/LwIP/src/core/timeouts.c \ +../Middlewares/Third_Party/LwIP/src/core/udp.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/core/altcp.o \ +./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o \ +./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o \ +./Middlewares/Third_Party/LwIP/src/core/def.o \ +./Middlewares/Third_Party/LwIP/src/core/dns.o \ +./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o \ +./Middlewares/Third_Party/LwIP/src/core/init.o \ +./Middlewares/Third_Party/LwIP/src/core/ip.o \ +./Middlewares/Third_Party/LwIP/src/core/mem.o \ +./Middlewares/Third_Party/LwIP/src/core/memp.o \ +./Middlewares/Third_Party/LwIP/src/core/netif.o \ +./Middlewares/Third_Party/LwIP/src/core/pbuf.o \ +./Middlewares/Third_Party/LwIP/src/core/raw.o \ +./Middlewares/Third_Party/LwIP/src/core/stats.o \ +./Middlewares/Third_Party/LwIP/src/core/sys.o \ +./Middlewares/Third_Party/LwIP/src/core/tcp.o \ +./Middlewares/Third_Party/LwIP/src/core/tcp_in.o \ +./Middlewares/Third_Party/LwIP/src/core/tcp_out.o \ +./Middlewares/Third_Party/LwIP/src/core/timeouts.o \ +./Middlewares/Third_Party/LwIP/src/core/udp.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/core/altcp.d \ +./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d \ +./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d \ +./Middlewares/Third_Party/LwIP/src/core/def.d \ +./Middlewares/Third_Party/LwIP/src/core/dns.d \ +./Middlewares/Third_Party/LwIP/src/core/inet_chksum.d \ +./Middlewares/Third_Party/LwIP/src/core/init.d \ +./Middlewares/Third_Party/LwIP/src/core/ip.d \ +./Middlewares/Third_Party/LwIP/src/core/mem.d \ +./Middlewares/Third_Party/LwIP/src/core/memp.d \ +./Middlewares/Third_Party/LwIP/src/core/netif.d \ +./Middlewares/Third_Party/LwIP/src/core/pbuf.d \ +./Middlewares/Third_Party/LwIP/src/core/raw.d \ +./Middlewares/Third_Party/LwIP/src/core/stats.d \ +./Middlewares/Third_Party/LwIP/src/core/sys.d \ +./Middlewares/Third_Party/LwIP/src/core/tcp.d \ +./Middlewares/Third_Party/LwIP/src/core/tcp_in.d \ +./Middlewares/Third_Party/LwIP/src/core/tcp_out.d \ +./Middlewares/Third_Party/LwIP/src/core/timeouts.d \ +./Middlewares/Third_Party/LwIP/src/core/udp.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/core/%.o Middlewares/Third_Party/LwIP/src/core/%.su Middlewares/Third_Party/LwIP/src/core/%.cyclo: ../Middlewares/Third_Party/LwIP/src/core/%.c Middlewares/Third_Party/LwIP/src/core/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core: + -$(RM) ./Middlewares/Third_Party/LwIP/src/core/altcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/altcp.d ./Middlewares/Third_Party/LwIP/src/core/altcp.o ./Middlewares/Third_Party/LwIP/src/core/altcp.su ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.cyclo ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.d ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.su ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.d ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.su ./Middlewares/Third_Party/LwIP/src/core/def.cyclo ./Middlewares/Third_Party/LwIP/src/core/def.d ./Middlewares/Third_Party/LwIP/src/core/def.o ./Middlewares/Third_Party/LwIP/src/core/def.su ./Middlewares/Third_Party/LwIP/src/core/dns.cyclo ./Middlewares/Third_Party/LwIP/src/core/dns.d ./Middlewares/Third_Party/LwIP/src/core/dns.o ./Middlewares/Third_Party/LwIP/src/core/dns.su ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.cyclo ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.d ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.su ./Middlewares/Third_Party/LwIP/src/core/init.cyclo ./Middlewares/Third_Party/LwIP/src/core/init.d ./Middlewares/Third_Party/LwIP/src/core/init.o ./Middlewares/Third_Party/LwIP/src/core/init.su ./Middlewares/Third_Party/LwIP/src/core/ip.cyclo ./Middlewares/Third_Party/LwIP/src/core/ip.d ./Middlewares/Third_Party/LwIP/src/core/ip.o ./Middlewares/Third_Party/LwIP/src/core/ip.su ./Middlewares/Third_Party/LwIP/src/core/mem.cyclo ./Middlewares/Third_Party/LwIP/src/core/mem.d ./Middlewares/Third_Party/LwIP/src/core/mem.o ./Middlewares/Third_Party/LwIP/src/core/mem.su ./Middlewares/Third_Party/LwIP/src/core/memp.cyclo ./Middlewares/Third_Party/LwIP/src/core/memp.d ./Middlewares/Third_Party/LwIP/src/core/memp.o ./Middlewares/Third_Party/LwIP/src/core/memp.su ./Middlewares/Third_Party/LwIP/src/core/netif.cyclo ./Middlewares/Third_Party/LwIP/src/core/netif.d ./Middlewares/Third_Party/LwIP/src/core/netif.o ./Middlewares/Third_Party/LwIP/src/core/netif.su ./Middlewares/Third_Party/LwIP/src/core/pbuf.cyclo ./Middlewares/Third_Party/LwIP/src/core/pbuf.d ./Middlewares/Third_Party/LwIP/src/core/pbuf.o ./Middlewares/Third_Party/LwIP/src/core/pbuf.su ./Middlewares/Third_Party/LwIP/src/core/raw.cyclo ./Middlewares/Third_Party/LwIP/src/core/raw.d ./Middlewares/Third_Party/LwIP/src/core/raw.o ./Middlewares/Third_Party/LwIP/src/core/raw.su ./Middlewares/Third_Party/LwIP/src/core/stats.cyclo ./Middlewares/Third_Party/LwIP/src/core/stats.d ./Middlewares/Third_Party/LwIP/src/core/stats.o ./Middlewares/Third_Party/LwIP/src/core/stats.su ./Middlewares/Third_Party/LwIP/src/core/sys.cyclo ./Middlewares/Third_Party/LwIP/src/core/sys.d ./Middlewares/Third_Party/LwIP/src/core/sys.o ./Middlewares/Third_Party/LwIP/src/core/sys.su ./Middlewares/Third_Party/LwIP/src/core/tcp.cyclo ./Middlewares/Third_Party/LwIP/src/core/tcp.d ./Middlewares/Third_Party/LwIP/src/core/tcp.o ./Middlewares/Third_Party/LwIP/src/core/tcp.su ./Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo ./Middlewares/Third_Party/LwIP/src/core/tcp_in.d ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o ./Middlewares/Third_Party/LwIP/src/core/tcp_in.su ./Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo ./Middlewares/Third_Party/LwIP/src/core/tcp_out.d ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o ./Middlewares/Third_Party/LwIP/src/core/tcp_out.su ./Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo ./Middlewares/Third_Party/LwIP/src/core/timeouts.d ./Middlewares/Third_Party/LwIP/src/core/timeouts.o ./Middlewares/Third_Party/LwIP/src/core/timeouts.su ./Middlewares/Third_Party/LwIP/src/core/udp.cyclo ./Middlewares/Third_Party/LwIP/src/core/udp.d ./Middlewares/Third_Party/LwIP/src/core/udp.o ./Middlewares/Third_Party/LwIP/src/core/udp.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-core + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d new file mode 100644 index 0000000..a69a8b2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/core/sys.o: \ + ../Middlewares/Third_Party/LwIP/src/core/sys.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o new file mode 100644 index 0000000..3931e9c Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su b/Debug/Middlewares/Third_Party/LwIP/src/core/sys.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.cyclo new file mode 100644 index 0000000..bd13c6b --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.cyclo @@ -0,0 +1,52 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp.c:201:1:tcp_init 1 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:210:1:tcp_free 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:221:1:tcp_free_listen 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:234:1:tcp_tmr 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:251:1:tcp_remove_listener 4 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:269:1:tcp_listen_closed 4 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:348:1:tcp_close_shutdown 20 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:409:1:tcp_close_shutdown_fin 11 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:484:1:tcp_close 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:515:1:tcp_shutdown 10 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:563:1:tcp_abandon 14 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:638:1:tcp_abort 1 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:661:1:tcp_bind 17 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:763:1:tcp_bind_netif 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:778:1:tcp_accept_null 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:825:1:tcp_listen_with_backlog 1 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:848:1:tcp_listen_with_backlog_and_err 10 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:930:1:tcp_update_rcv_ann_wnd 5 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:968:1:tcp_recved 6 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1011:1:tcp_new_port 6 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1067:1:tcp_connect 18 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1192:1:tcp_slowtmr 63 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1479:1:tcp_fasttmr 7 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1526:1:tcp_txnow 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1539:1:tcp_process_refused_data 9 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1608:1:tcp_segs_free 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1623:1:tcp_seg_free 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1644:1:tcp_setprio 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1662:1:tcp_seg_copy 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1684:1:tcp_recv_null 4 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1706:1:tcp_kill_prio 8 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1752:1:tcp_kill_state 7 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1784:1:tcp_kill_timewait 4 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1811:1:tcp_handle_closepend 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1834:1:tcp_alloc 6 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1945:1:tcp_new 1 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1962:1:tcp_new_ip_type 1 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1988:1:tcp_arg 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2011:1:tcp_recv 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2031:1:tcp_sent 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2057:1:tcp_err 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2076:1:tcp_accept 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2105:1:tcp_poll 3 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2127:1:tcp_pcb_purge 7 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2177:1:tcp_pcb_remove 13 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2215:1:tcp_next_iss 2 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2238:1:tcp_eff_send_mss_netif 5 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2299:1:tcp_netif_ip_addr_changed_pcblist 4 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2331:1:tcp_netif_ip_addr_changed 7 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2354:1:tcp_debug_state_str 1 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2360:1:tcp_tcp_get_tcp_addrinfo 7 +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2386:1:tcp_free_ooseq 2 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d new file mode 100644 index 0000000..08e16b4 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.d @@ -0,0 +1,127 @@ +Middlewares/Third_Party/LwIP/src/core/tcp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/tcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o new file mode 100644 index 0000000..a4aeb91 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.su new file mode 100644 index 0000000..17c1295 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp.su @@ -0,0 +1,52 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp.c:201:1:tcp_init 8 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:210:1:tcp_free 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:221:1:tcp_free_listen 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:234:1:tcp_tmr 8 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:251:1:tcp_remove_listener 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:269:1:tcp_listen_closed 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:348:1:tcp_close_shutdown 48 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:409:1:tcp_close_shutdown_fin 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:484:1:tcp_close 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:515:1:tcp_shutdown 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:563:1:tcp_abandon 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:638:1:tcp_abort 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:661:1:tcp_bind 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:763:1:tcp_bind_netif 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:778:1:tcp_accept_null 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:825:1:tcp_listen_with_backlog 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:848:1:tcp_listen_with_backlog_and_err 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:930:1:tcp_update_rcv_ann_wnd 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:968:1:tcp_recved 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1011:1:tcp_new_port 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1067:1:tcp_connect 48 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1192:1:tcp_slowtmr 80 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1479:1:tcp_fasttmr 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1526:1:tcp_txnow 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1539:1:tcp_process_refused_data 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1608:1:tcp_segs_free 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1623:1:tcp_seg_free 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1644:1:tcp_setprio 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1662:1:tcp_seg_copy 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1684:1:tcp_recv_null 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1706:1:tcp_kill_prio 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1752:1:tcp_kill_state 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1784:1:tcp_kill_timewait 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1811:1:tcp_handle_closepend 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1834:1:tcp_alloc 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1945:1:tcp_new 8 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1962:1:tcp_new_ip_type 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:1988:1:tcp_arg 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2011:1:tcp_recv 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2031:1:tcp_sent 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2057:1:tcp_err 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2076:1:tcp_accept 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2105:1:tcp_poll 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2127:1:tcp_pcb_purge 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2177:1:tcp_pcb_remove 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2215:1:tcp_next_iss 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2238:1:tcp_eff_send_mss_netif 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2299:1:tcp_netif_ip_addr_changed_pcblist 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2331:1:tcp_netif_ip_addr_changed 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2354:1:tcp_debug_state_str 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2360:1:tcp_tcp_get_tcp_addrinfo 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp.c:2386:1:tcp_free_ooseq 16 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo new file mode 100644 index 0000000..f5521f3 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.cyclo @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:118:1:tcp_input 73 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:600:1:tcp_input_delayed_close 5 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:630:1:tcp_listen_input 8 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:739:1:tcp_timewait_input 8 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:788:1:tcp_process 72 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1051:1:tcp_oos_insert_segment 8 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1088:1:tcp_free_acked_segments 8 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1141:1:tcp_receive 109 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1888:1:tcp_get_next_optbyte 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1909:1:tcp_parseopt 13 +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:2029:1:tcp_trigger_input_pcb_close 1 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d new file mode 100644 index 0000000..eff388a --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.d @@ -0,0 +1,129 @@ +Middlewares/Third_Party/LwIP/src/core/tcp_in.o: \ + ../Middlewares/Third_Party/LwIP/src/core/tcp_in.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o new file mode 100644 index 0000000..2ce9238 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.su b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.su new file mode 100644 index 0000000..0578f9e --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_in.su @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:118:1:tcp_input 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:600:1:tcp_input_delayed_close 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:630:1:tcp_listen_input 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:739:1:tcp_timewait_input 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:788:1:tcp_process 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1051:1:tcp_oos_insert_segment 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1088:1:tcp_free_acked_segments 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1141:1:tcp_receive 96 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1888:1:tcp_get_next_optbyte 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:1909:1:tcp_parseopt 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp_in.c:2029:1:tcp_trigger_input_pcb_close 4 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo new file mode 100644 index 0000000..c5aef97 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.cyclo @@ -0,0 +1,24 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:132:1:tcp_route 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:158:1:tcp_create_segment 6 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:225:1:tcp_pbuf_prealloc 11 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:305:1:tcp_write_checks 14 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:390:1:tcp_write 59 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:827:1:tcp_split_unsent_seg 15 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1001:1:tcp_send_fin 5 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1032:1:tcp_enqueue_flags 17 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1237:1:tcp_output 42 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1432:1:tcp_output_segment_busy 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1455:1:tcp_output_segment 10 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1631:1:tcp_rexmit_rto_prepare 8 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1686:1:tcp_rexmit_rto_commit 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1707:1:tcp_rexmit_rto 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1724:1:tcp_rexmit 8 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1783:1:tcp_rexmit_fast 7 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1818:1:tcp_output_alloc_header_common 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1853:1:tcp_output_alloc_header 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1872:1:tcp_output_fill_options 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1921:1:tcp_output_control_segment 4 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1980:1:tcp_rst 4 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2019:1:tcp_send_empty_ack 4 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2078:1:tcp_keepalive 3 +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2116:1:tcp_zero_window_probe 9 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d new file mode 100644 index 0000000..12fe08a --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.d @@ -0,0 +1,127 @@ +Middlewares/Third_Party/LwIP/src/core/tcp_out.o: \ + ../Middlewares/Third_Party/LwIP/src/core/tcp_out.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o new file mode 100644 index 0000000..7bfd9fa Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.su b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.su new file mode 100644 index 0000000..8dabebd --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/tcp_out.su @@ -0,0 +1,24 @@ +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:132:1:tcp_route 24 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:158:1:tcp_create_segment 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:225:1:tcp_pbuf_prealloc 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:305:1:tcp_write_checks 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:390:1:tcp_write 128 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:827:1:tcp_split_unsent_seg 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1001:1:tcp_send_fin 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1032:1:tcp_enqueue_flags 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1237:1:tcp_output 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1432:1:tcp_output_segment_busy 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1455:1:tcp_output_segment 64 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1631:1:tcp_rexmit_rto_prepare 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1686:1:tcp_rexmit_rto_commit 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1707:1:tcp_rexmit_rto 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1724:1:tcp_rexmit 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1783:1:tcp_rexmit_fast 16 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1818:1:tcp_output_alloc_header_common 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1853:1:tcp_output_alloc_header 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1872:1:tcp_output_fill_options 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1921:1:tcp_output_control_segment 48 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:1980:1:tcp_rst 56 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2019:1:tcp_send_empty_ack 40 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2078:1:tcp_keepalive 32 static +../Middlewares/Third_Party/LwIP/src/core/tcp_out.c:2116:1:tcp_zero_window_probe 56 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo new file mode 100644 index 0000000..cd2c8f1 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.cyclo @@ -0,0 +1,10 @@ +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:144:1:tcpip_tcp_timer 3 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:166:1:tcp_timer_needed 4 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:183:1:sys_timeout_abs 8 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:232:1:lwip_cyclic_timer 2 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:264:6:sys_timeouts_init 2 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:290:1:sys_timeout 2 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:317:1:sys_untimeout 6 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:352:1:sys_check_timeouts 5 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:404:1:sys_restart_timeouts 3 +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:426:1:sys_timeouts_sleeptime 4 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d new file mode 100644 index 0000000..a07b561 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.d @@ -0,0 +1,157 @@ +Middlewares/Third_Party/LwIP/src/core/timeouts.o: \ + ../Middlewares/Third_Party/LwIP/src/core/timeouts.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dns.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o new file mode 100644 index 0000000..6d23557 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.su b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.su new file mode 100644 index 0000000..89b582f --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/timeouts.su @@ -0,0 +1,10 @@ +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:144:1:tcpip_tcp_timer 16 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:166:1:tcp_timer_needed 8 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:183:1:sys_timeout_abs 32 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:232:1:lwip_cyclic_timer 32 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:264:6:sys_timeouts_init 16 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:290:1:sys_timeout 32 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:317:1:sys_untimeout 24 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:352:1:sys_check_timeouts 24 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:404:1:sys_restart_timeouts 24 static +../Middlewares/Third_Party/LwIP/src/core/timeouts.c:426:1:sys_timeouts_sleeptime 16 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.cyclo new file mode 100644 index 0000000..3055021 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.cyclo @@ -0,0 +1,17 @@ +../Middlewares/Third_Party/LwIP/src/core/udp.c:87:1:udp_init 1 +../Middlewares/Third_Party/LwIP/src/core/udp.c:100:1:udp_new_port 5 +../Middlewares/Third_Party/LwIP/src/core/udp.c:130:1:udp_input_local_match 13 +../Middlewares/Third_Party/LwIP/src/core/udp.c:194:1:udp_input 25 +../Middlewares/Third_Party/LwIP/src/core/udp.c:467:1:udp_send 3 +../Middlewares/Third_Party/LwIP/src/core/udp.c:520:1:udp_sendto 6 +../Middlewares/Third_Party/LwIP/src/core/udp.c:624:1:udp_sendto_if 9 +../Middlewares/Third_Party/LwIP/src/core/udp.c:699:1:udp_sendto_if_src 14 +../Middlewares/Third_Party/LwIP/src/core/udp.c:932:1:udp_bind 17 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1042:1:udp_bind_netif 2 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1071:1:udp_connect 8 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1126:1:udp_disconnect 2 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1158:1:udp_recv 2 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1179:1:udp_remove 6 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1218:1:udp_new 2 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1255:1:udp_new_ip_type 1 +../Middlewares/Third_Party/LwIP/src/core/udp.c:1278:6:udp_netif_ip_addr_changed 7 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d new file mode 100644 index 0000000..2635cf9 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.d @@ -0,0 +1,131 @@ +Middlewares/Third_Party/LwIP/src/core/udp.o: \ + ../Middlewares/Third_Party/LwIP/src/core/udp.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o new file mode 100644 index 0000000..cf0b9a5 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/core/udp.su b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.su new file mode 100644 index 0000000..3865a30 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/core/udp.su @@ -0,0 +1,17 @@ +../Middlewares/Third_Party/LwIP/src/core/udp.c:87:1:udp_init 8 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:100:1:udp_new_port 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:130:1:udp_input_local_match 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:194:1:udp_input 64 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:467:1:udp_send 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:520:1:udp_sendto 40 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:624:1:udp_sendto_if 40 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:699:1:udp_sendto_if_src 56 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:932:1:udp_bind 32 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1042:1:udp_bind_netif 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1071:1:udp_connect 32 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1126:1:udp_disconnect 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1158:1:udp_recv 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1179:1:udp_remove 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1218:1:udp_new 16 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1255:1:udp_new_ip_type 24 static +../Middlewares/Third_Party/LwIP/src/core/udp.c:1278:6:udp_netif_ip_addr_changed 24 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d new file mode 100644 index 0000000..e7dfb50 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.d @@ -0,0 +1,127 @@ +Middlewares/Third_Party/LwIP/src/netif/bridgeif.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/bridgeif.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h: +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o new file mode 100644 index 0000000..b85f789 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo new file mode 100644 index 0000000..ff1bed7 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo @@ -0,0 +1,5 @@ +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:76:1:bridgeif_fdb_update_src 10 +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:128:1:bridgeif_fdb_get_dst_ports 5 +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:153:1:bridgeif_fdb_age_one_second 7 +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:180:1:bridgeif_age_tmr 2 +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:195:1:bridgeif_fdb_init 3 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d new file mode 100644 index 0000000..6ce57d6 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d @@ -0,0 +1,91 @@ +Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h: +../Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o new file mode 100644 index 0000000..ea703e2 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su new file mode 100644 index 0000000..d4ac644 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su @@ -0,0 +1,5 @@ +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:76:1:bridgeif_fdb_update_src 40 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:128:1:bridgeif_fdb_get_dst_ports 32 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:153:1:bridgeif_fdb_age_one_second 32 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:180:1:bridgeif_age_tmr 24 static +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c:195:1:bridgeif_fdb_init 32 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo new file mode 100644 index 0000000..a1c1deb --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo @@ -0,0 +1,2 @@ +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c:81:1:ethernet_input 14 +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c:270:1:ethernet_output 3 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d new file mode 100644 index 0000000..f61ea79 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.d @@ -0,0 +1,127 @@ +Middlewares/Third_Party/LwIP/src/netif/ethernet.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ethernet.c \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o new file mode 100644 index 0000000..299cba6 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.su new file mode 100644 index 0000000..b04052e --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ethernet.su @@ -0,0 +1,2 @@ +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c:81:1:ethernet_input 32 static +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c:270:1:ethernet_output 32 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d new file mode 100644 index 0000000..472467d --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.d @@ -0,0 +1,79 @@ +Middlewares/Third_Party/LwIP/src/netif/lowpan6.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/lowpan6.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o new file mode 100644 index 0000000..f1311e3 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d new file mode 100644 index 0000000..0f478bb --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d @@ -0,0 +1,79 @@ +Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o new file mode 100644 index 0000000..e4bdfa5 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d new file mode 100644 index 0000000..e12778d --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d @@ -0,0 +1,79 @@ +Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o new file mode 100644 index 0000000..c94e4e4 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d new file mode 100644 index 0000000..e32fad4 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o new file mode 100644 index 0000000..06e76e4 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d new file mode 100644 index 0000000..02960f9 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o new file mode 100644 index 0000000..c11c54c Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d new file mode 100644 index 0000000..a81da72 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o new file mode 100644 index 0000000..99879c9 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d new file mode 100644 index 0000000..95a4d20 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o new file mode 100644 index 0000000..120aa1b Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d new file mode 100644 index 0000000..0d3d45c --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o new file mode 100644 index 0000000..edd3ec6 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d new file mode 100644 index 0000000..7ee83f2 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o new file mode 100644 index 0000000..5336d77 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d new file mode 100644 index 0000000..8d6d5ef --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o new file mode 100644 index 0000000..85193ff Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d new file mode 100644 index 0000000..c253bb7 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o new file mode 100644 index 0000000..df84ae2 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d new file mode 100644 index 0000000..488046f --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o new file mode 100644 index 0000000..e09b4ad Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d new file mode 100644 index 0000000..bb29f84 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o new file mode 100644 index 0000000..ee43ca4 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d new file mode 100644 index 0000000..d0b8724 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o new file mode 100644 index 0000000..9304039 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d new file mode 100644 index 0000000..db2fb9a --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o new file mode 100644 index 0000000..28df5b3 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d new file mode 100644 index 0000000..0017715 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o new file mode 100644 index 0000000..03f053b Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d new file mode 100644 index 0000000..978007a --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o new file mode 100644 index 0000000..62b06ce Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d new file mode 100644 index 0000000..b0bf737 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o new file mode 100644 index 0000000..4586a34 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d new file mode 100644 index 0000000..3fb48bd --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o new file mode 100644 index 0000000..90cc50c Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d new file mode 100644 index 0000000..84bea15 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o new file mode 100644 index 0000000..a35af86 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d new file mode 100644 index 0000000..5fccfff --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o new file mode 100644 index 0000000..cdc3035 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d new file mode 100644 index 0000000..a414880 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o new file mode 100644 index 0000000..7d36e9d Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d new file mode 100644 index 0000000..81054f0 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o new file mode 100644 index 0000000..989b13e Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d new file mode 100644 index 0000000..36cb85c --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o new file mode 100644 index 0000000..031937c Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d new file mode 100644 index 0000000..8d43086 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o new file mode 100644 index 0000000..49a4ef2 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk new file mode 100644 index 0000000..656f895 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk @@ -0,0 +1,99 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c \ +../Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d \ +./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/netif/ppp/%.o Middlewares/Third_Party/LwIP/src/netif/ppp/%.su Middlewares/Third_Party/LwIP/src/netif/ppp/%.cyclo: ../Middlewares/Third_Party/LwIP/src/netif/ppp/%.c Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif-2f-ppp + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif-2f-ppp: + -$(RM) ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.su ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o ./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif-2f-ppp + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d new file mode 100644 index 0000000..36be8e5 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o new file mode 100644 index 0000000..8f1d944 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d new file mode 100644 index 0000000..7bebc10 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o new file mode 100644 index 0000000..51d4c25 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d new file mode 100644 index 0000000..b2073cb --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.d @@ -0,0 +1,77 @@ +Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h +../Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o new file mode 100644 index 0000000..26c9604 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo new file mode 100644 index 0000000..15bb618 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:116:1:slipif_output 8 +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:172:1:slipif_output_v4 1 +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:207:1:slipif_rxbyte 18 +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:310:1:slipif_rxbyte_input 3 +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:360:1:slipif_init 4 +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:426:1:slipif_poll 4 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d new file mode 100644 index 0000000..fe32d0b --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.d @@ -0,0 +1,111 @@ +Middlewares/Third_Party/LwIP/src/netif/slipif.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/slipif.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/slipif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/err.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/def.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/sio.h +../Middlewares/Third_Party/LwIP/src/include/netif/slipif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/netif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/err.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/def.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/stats.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/mem.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/memp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sys.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/sio.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o new file mode 100644 index 0000000..500bfd5 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su new file mode 100644 index 0000000..0915971 --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/slipif.su @@ -0,0 +1,6 @@ +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:116:1:slipif_output 32 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:172:1:slipif_output_v4 24 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:207:1:slipif_rxbyte 24 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:310:1:slipif_rxbyte_input 24 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:360:1:slipif_init 24 static +../Middlewares/Third_Party/LwIP/src/netif/slipif.c:426:1:slipif_poll 24 static diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk b/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk new file mode 100644 index 0000000..0e1999c --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/LwIP/src/netif/bridgeif.c \ +../Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c \ +../Middlewares/Third_Party/LwIP/src/netif/ethernet.c \ +../Middlewares/Third_Party/LwIP/src/netif/lowpan6.c \ +../Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c \ +../Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c \ +../Middlewares/Third_Party/LwIP/src/netif/slipif.c \ +../Middlewares/Third_Party/LwIP/src/netif/zepif.c + +OBJS += \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o \ +./Middlewares/Third_Party/LwIP/src/netif/ethernet.o \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o \ +./Middlewares/Third_Party/LwIP/src/netif/slipif.o \ +./Middlewares/Third_Party/LwIP/src/netif/zepif.o + +C_DEPS += \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif.d \ +./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d \ +./Middlewares/Third_Party/LwIP/src/netif/ethernet.d \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6.d \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d \ +./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d \ +./Middlewares/Third_Party/LwIP/src/netif/slipif.d \ +./Middlewares/Third_Party/LwIP/src/netif/zepif.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/LwIP/src/netif/%.o Middlewares/Third_Party/LwIP/src/netif/%.su Middlewares/Third_Party/LwIP/src/netif/%.cyclo: ../Middlewares/Third_Party/LwIP/src/netif/%.c Middlewares/Third_Party/LwIP/src/netif/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m7 -std=gnu11 -g3 -DDEBUG -DDATA_IN_D2_SRAM -DUSE_HAL_DRIVER -DSTM32H723xx -c -I../Core/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc -I../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32H7xx/Include -I../Drivers/CMSIS/Include -I../LWIP/App -I../LWIP/Target -I../Middlewares/Third_Party/LwIP/src/include -I../Middlewares/Third_Party/LwIP/system -I../Drivers/BSP/Components/lan8742 -I../Middlewares/Third_Party/LwIP/src/include/netif/ppp -I../Middlewares/Third_Party/LwIP/src/include/lwip -I../Middlewares/Third_Party/LwIP/src/include/lwip/apps -I../Middlewares/Third_Party/LwIP/src/include/lwip/priv -I../Middlewares/Third_Party/LwIP/src/include/lwip/prot -I../Middlewares/Third_Party/LwIP/src/include/netif -I../Middlewares/Third_Party/LwIP/src/include/compat/posix -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/net -I../Middlewares/Third_Party/LwIP/src/include/compat/posix/sys -I../Middlewares/Third_Party/LwIP/src/include/compat/stdc -I../Middlewares/Third_Party/LwIP/system/arch -I"C:/_NoSleep/STM32/lwip_test/LWFTP" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif + +clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif: + -$(RM) ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.cyclo ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o ./Middlewares/Third_Party/LwIP/src/netif/bridgeif.su ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.cyclo ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.d ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o ./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.su ./Middlewares/Third_Party/LwIP/src/netif/ethernet.cyclo ./Middlewares/Third_Party/LwIP/src/netif/ethernet.d ./Middlewares/Third_Party/LwIP/src/netif/ethernet.o ./Middlewares/Third_Party/LwIP/src/netif/ethernet.su ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.cyclo ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o ./Middlewares/Third_Party/LwIP/src/netif/lowpan6.su ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.cyclo ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.su ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.cyclo ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.d ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o ./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.su ./Middlewares/Third_Party/LwIP/src/netif/slipif.cyclo ./Middlewares/Third_Party/LwIP/src/netif/slipif.d ./Middlewares/Third_Party/LwIP/src/netif/slipif.o ./Middlewares/Third_Party/LwIP/src/netif/slipif.su ./Middlewares/Third_Party/LwIP/src/netif/zepif.cyclo ./Middlewares/Third_Party/LwIP/src/netif/zepif.d ./Middlewares/Third_Party/LwIP/src/netif/zepif.o ./Middlewares/Third_Party/LwIP/src/netif/zepif.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-LwIP-2f-src-2f-netif + diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.cyclo b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d new file mode 100644 index 0000000..21779fc --- /dev/null +++ b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.d @@ -0,0 +1,81 @@ +Middlewares/Third_Party/LwIP/src/netif/zepif.o: \ + ../Middlewares/Third_Party/LwIP/src/netif/zepif.c \ + ../Middlewares/Third_Party/LwIP/src/include/netif/zepif.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h \ + ../LWIP/Target/lwipopts.h ../Core/Inc/main.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h \ + ../Core/Inc/stm32h7xx_hal_conf.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h \ + ../Drivers/CMSIS/Include/core_cm7.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h \ + ../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h \ + ../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cc.h \ + ../Middlewares/Third_Party/LwIP/system/arch/cpu.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h \ + ../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h +../Middlewares/Third_Party/LwIP/src/include/netif/zepif.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/opt.h: +../LWIP/Target/lwipopts.h: +../Core/Inc/main.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h: +../Core/Inc/stm32h7xx_hal_conf.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h: +../Drivers/CMSIS/Include/core_cm7.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h: +../Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/debug.h: +../Middlewares/Third_Party/LwIP/src/include/lwip/arch.h: +../Middlewares/Third_Party/LwIP/system/arch/cc.h: +../Middlewares/Third_Party/LwIP/system/arch/cpu.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h: +../Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h: diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o new file mode 100644 index 0000000..88597c6 Binary files /dev/null and b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.o differ diff --git a/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.su b/Debug/Middlewares/Third_Party/LwIP/src/netif/zepif.su new file mode 100644 index 0000000..e69de29 diff --git a/Debug/lwip_test.list b/Debug/lwip_test.list new file mode 100644 index 0000000..355ef68 --- /dev/null +++ b/Debug/lwip_test.list @@ -0,0 +1,44508 @@ + +lwip_test.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000002cc 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 000112d4 080002d0 080002d0 000102d0 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 000039e4 080115a4 080115a4 000215a4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .init_array 00000004 08014f88 08014f88 00024f88 2**2 + CONTENTS, ALLOC, LOAD, DATA + 4 .fini_array 00000004 08014f8c 08014f8c 00024f8c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 5 .data 000000d0 24000000 08014f90 00030000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 6 .bss 00007d48 240000d0 08015060 000300d0 2**2 + ALLOC + 7 ._user_heap_stack 00000600 24007e18 08015060 00037e18 2**0 + ALLOC + 8 .lwip_sec 00000160 30000000 30000000 00040000 2**2 + ALLOC + 9 .ARM.attributes 0000002e 00000000 00000000 000300d0 2**0 + CONTENTS, READONLY + 10 .comment 00000043 00000000 00000000 000300fe 2**0 + CONTENTS, READONLY + 11 .debug_info 0001f0ff 00000000 00000000 00030141 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 12 .debug_abbrev 000054e0 00000000 00000000 0004f240 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_aranges 00001508 00000000 00000000 00054720 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_rnglists 00001094 00000000 00000000 00055c28 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_macro 0003e829 00000000 00000000 00056cbc 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_line 00026379 00000000 00000000 000954e5 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_str 00150dcb 00000000 00000000 000bb85e 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_frame 00005dfc 00000000 00000000 0020c62c 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_line_str 0000004a 00000000 00000000 00212428 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080002d0 <__do_global_dtors_aux>: + 80002d0: b510 push {r4, lr} + 80002d2: 4c05 ldr r4, [pc, #20] ; (80002e8 <__do_global_dtors_aux+0x18>) + 80002d4: 7823 ldrb r3, [r4, #0] + 80002d6: b933 cbnz r3, 80002e6 <__do_global_dtors_aux+0x16> + 80002d8: 4b04 ldr r3, [pc, #16] ; (80002ec <__do_global_dtors_aux+0x1c>) + 80002da: b113 cbz r3, 80002e2 <__do_global_dtors_aux+0x12> + 80002dc: 4804 ldr r0, [pc, #16] ; (80002f0 <__do_global_dtors_aux+0x20>) + 80002de: f3af 8000 nop.w + 80002e2: 2301 movs r3, #1 + 80002e4: 7023 strb r3, [r4, #0] + 80002e6: bd10 pop {r4, pc} + 80002e8: 240000d0 .word 0x240000d0 + 80002ec: 00000000 .word 0x00000000 + 80002f0: 0801158c .word 0x0801158c + +080002f4 : + 80002f4: b508 push {r3, lr} + 80002f6: 4b03 ldr r3, [pc, #12] ; (8000304 ) + 80002f8: b11b cbz r3, 8000302 + 80002fa: 4903 ldr r1, [pc, #12] ; (8000308 ) + 80002fc: 4803 ldr r0, [pc, #12] ; (800030c ) + 80002fe: f3af 8000 nop.w + 8000302: bd08 pop {r3, pc} + 8000304: 00000000 .word 0x00000000 + 8000308: 240000d4 .word 0x240000d4 + 800030c: 0801158c .word 0x0801158c + +08000310 : + 8000310: f001 01ff and.w r1, r1, #255 ; 0xff + 8000314: 2a10 cmp r2, #16 + 8000316: db2b blt.n 8000370 + 8000318: f010 0f07 tst.w r0, #7 + 800031c: d008 beq.n 8000330 + 800031e: f810 3b01 ldrb.w r3, [r0], #1 + 8000322: 3a01 subs r2, #1 + 8000324: 428b cmp r3, r1 + 8000326: d02d beq.n 8000384 + 8000328: f010 0f07 tst.w r0, #7 + 800032c: b342 cbz r2, 8000380 + 800032e: d1f6 bne.n 800031e + 8000330: b4f0 push {r4, r5, r6, r7} + 8000332: ea41 2101 orr.w r1, r1, r1, lsl #8 + 8000336: ea41 4101 orr.w r1, r1, r1, lsl #16 + 800033a: f022 0407 bic.w r4, r2, #7 + 800033e: f07f 0700 mvns.w r7, #0 + 8000342: 2300 movs r3, #0 + 8000344: e8f0 5602 ldrd r5, r6, [r0], #8 + 8000348: 3c08 subs r4, #8 + 800034a: ea85 0501 eor.w r5, r5, r1 + 800034e: ea86 0601 eor.w r6, r6, r1 + 8000352: fa85 f547 uadd8 r5, r5, r7 + 8000356: faa3 f587 sel r5, r3, r7 + 800035a: fa86 f647 uadd8 r6, r6, r7 + 800035e: faa5 f687 sel r6, r5, r7 + 8000362: b98e cbnz r6, 8000388 + 8000364: d1ee bne.n 8000344 + 8000366: bcf0 pop {r4, r5, r6, r7} + 8000368: f001 01ff and.w r1, r1, #255 ; 0xff + 800036c: f002 0207 and.w r2, r2, #7 + 8000370: b132 cbz r2, 8000380 + 8000372: f810 3b01 ldrb.w r3, [r0], #1 + 8000376: 3a01 subs r2, #1 + 8000378: ea83 0301 eor.w r3, r3, r1 + 800037c: b113 cbz r3, 8000384 + 800037e: d1f8 bne.n 8000372 + 8000380: 2000 movs r0, #0 + 8000382: 4770 bx lr + 8000384: 3801 subs r0, #1 + 8000386: 4770 bx lr + 8000388: 2d00 cmp r5, #0 + 800038a: bf06 itte eq + 800038c: 4635 moveq r5, r6 + 800038e: 3803 subeq r0, #3 + 8000390: 3807 subne r0, #7 + 8000392: f015 0f01 tst.w r5, #1 + 8000396: d107 bne.n 80003a8 + 8000398: 3001 adds r0, #1 + 800039a: f415 7f80 tst.w r5, #256 ; 0x100 + 800039e: bf02 ittt eq + 80003a0: 3001 addeq r0, #1 + 80003a2: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 + 80003a6: 3001 addeq r0, #1 + 80003a8: bcf0 pop {r4, r5, r6, r7} + 80003aa: 3801 subs r0, #1 + 80003ac: 4770 bx lr + 80003ae: bf00 nop + +080003b0 : + 80003b0: 4603 mov r3, r0 + 80003b2: f813 2b01 ldrb.w r2, [r3], #1 + 80003b6: 2a00 cmp r2, #0 + 80003b8: d1fb bne.n 80003b2 + 80003ba: 1a18 subs r0, r3, r0 + 80003bc: 3801 subs r0, #1 + 80003be: 4770 bx lr + +080003c0 : + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + 80003c0: b480 push {r7} + 80003c2: b083 sub sp, #12 + 80003c4: af00 add r7, sp, #0 + 80003c6: 6078 str r0, [r7, #4] + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + 80003c8: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 + 80003cc: f8d3 3e80 ldr.w r3, [r3, #3712] ; 0xe80 + 80003d0: f003 0301 and.w r3, r3, #1 + 80003d4: 2b00 cmp r3, #0 + 80003d6: d013 beq.n 8000400 + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + 80003d8: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 + 80003dc: f8d3 3e00 ldr.w r3, [r3, #3584] ; 0xe00 + 80003e0: f003 0301 and.w r3, r3, #1 + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + 80003e4: 2b00 cmp r3, #0 + 80003e6: d00b beq.n 8000400 + { + while (ITM->PORT[0U].u32 == 0UL) + 80003e8: e000 b.n 80003ec + { + __NOP(); + 80003ea: bf00 nop + while (ITM->PORT[0U].u32 == 0UL) + 80003ec: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 + 80003f0: 681b ldr r3, [r3, #0] + 80003f2: 2b00 cmp r3, #0 + 80003f4: d0f9 beq.n 80003ea + } + ITM->PORT[0U].u8 = (uint8_t)ch; + 80003f6: f04f 4360 mov.w r3, #3758096384 ; 0xe0000000 + 80003fa: 687a ldr r2, [r7, #4] + 80003fc: b2d2 uxtb r2, r2 + 80003fe: 701a strb r2, [r3, #0] + } + return (ch); + 8000400: 687b ldr r3, [r7, #4] +} + 8000402: 4618 mov r0, r3 + 8000404: 370c adds r7, #12 + 8000406: 46bd mov sp, r7 + 8000408: f85d 7b04 ldr.w r7, [sp], #4 + 800040c: 4770 bx lr + +0800040e <_write>: +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +#define min(x, y) (x) < (y) ? (x) : (y) +#define max(x, y) (x) > (y) ? (x) : (y) + +int _write(int32_t file, uint8_t *ptr, int32_t len) { + 800040e: b580 push {r7, lr} + 8000410: b086 sub sp, #24 + 8000412: af00 add r7, sp, #0 + 8000414: 60f8 str r0, [r7, #12] + 8000416: 60b9 str r1, [r7, #8] + 8000418: 607a str r2, [r7, #4] + for (int32_t i = 0; i < len; ++i) + 800041a: 2300 movs r3, #0 + 800041c: 617b str r3, [r7, #20] + 800041e: e009 b.n 8000434 <_write+0x26> + ITM_SendChar(*ptr++); + 8000420: 68bb ldr r3, [r7, #8] + 8000422: 1c5a adds r2, r3, #1 + 8000424: 60ba str r2, [r7, #8] + 8000426: 781b ldrb r3, [r3, #0] + 8000428: 4618 mov r0, r3 + 800042a: f7ff ffc9 bl 80003c0 + for (int32_t i = 0; i < len; ++i) + 800042e: 697b ldr r3, [r7, #20] + 8000430: 3301 adds r3, #1 + 8000432: 617b str r3, [r7, #20] + 8000434: 697a ldr r2, [r7, #20] + 8000436: 687b ldr r3, [r7, #4] + 8000438: 429a cmp r2, r3 + 800043a: dbf1 blt.n 8000420 <_write+0x12> + return len; + 800043c: 687b ldr r3, [r7, #4] +} + 800043e: 4618 mov r0, r3 + 8000440: 3718 adds r7, #24 + 8000442: 46bd mov sp, r7 + 8000444: bd80 pop {r7, pc} + ... + +08000448 : + +extern void LOG_ERROR(const char *format, ...) { + 8000448: b40f push {r0, r1, r2, r3} + 800044a: b580 push {r7, lr} + 800044c: b082 sub sp, #8 + 800044e: af00 add r7, sp, #0 + va_list args; + va_start(args, format); + 8000450: f107 0314 add.w r3, r7, #20 + 8000454: 607b str r3, [r7, #4] + fprintf(stderr, "ERROR: "); + 8000456: 4b0f ldr r3, [pc, #60] ; (8000494 ) + 8000458: 681b ldr r3, [r3, #0] + 800045a: 68db ldr r3, [r3, #12] + 800045c: 2207 movs r2, #7 + 800045e: 2101 movs r1, #1 + 8000460: 480d ldr r0, [pc, #52] ; (8000498 ) + 8000462: f010 fba3 bl 8010bac + vfprintf(stderr, format, args); + 8000466: 4b0b ldr r3, [pc, #44] ; (8000494 ) + 8000468: 681b ldr r3, [r3, #0] + 800046a: 68db ldr r3, [r3, #12] + 800046c: 687a ldr r2, [r7, #4] + 800046e: 6939 ldr r1, [r7, #16] + 8000470: 4618 mov r0, r3 + 8000472: f010 f8f3 bl 801065c + fprintf(stderr, "\r\n"); + 8000476: 4b07 ldr r3, [pc, #28] ; (8000494 ) + 8000478: 681b ldr r3, [r3, #0] + 800047a: 68db ldr r3, [r3, #12] + 800047c: 2202 movs r2, #2 + 800047e: 2101 movs r1, #1 + 8000480: 4806 ldr r0, [pc, #24] ; (800049c ) + 8000482: f010 fb93 bl 8010bac + va_end(args); +} + 8000486: bf00 nop + 8000488: 3708 adds r7, #8 + 800048a: 46bd mov sp, r7 + 800048c: e8bd 4080 ldmia.w sp!, {r7, lr} + 8000490: b004 add sp, #16 + 8000492: 4770 bx lr + 8000494: 240000cc .word 0x240000cc + 8000498: 080115a4 .word 0x080115a4 + 800049c: 080115ac .word 0x080115ac + +080004a0 : +extern void LOG_TRACE(const char *message) { + 80004a0: b580 push {r7, lr} + 80004a2: b082 sub sp, #8 + 80004a4: af00 add r7, sp, #0 + 80004a6: 6078 str r0, [r7, #4] + printf("TRACE: %s \r\n", message); + 80004a8: 6879 ldr r1, [r7, #4] + 80004aa: 4803 ldr r0, [pc, #12] ; (80004b8 ) + 80004ac: f010 fb8c bl 8010bc8 +} + 80004b0: bf00 nop + 80004b2: 3708 adds r7, #8 + 80004b4: 46bd mov sp, r7 + 80004b6: bd80 pop {r7, pc} + 80004b8: 080115b0 .word 0x080115b0 + +080004bc : + LOG_ERROR("lwftp_retrieve failed (%d)", error); + } + // FTP session will continue with RETR and sink callbacks +} + +static uint data_source(void *arg, const char **pptr, uint maxlen) { + 80004bc: b480 push {r7} + 80004be: b087 sub sp, #28 + 80004c0: af00 add r7, sp, #0 + 80004c2: 60f8 str r0, [r7, #12] + 80004c4: 60b9 str r1, [r7, #8] + 80004c6: 607a str r2, [r7, #4] + static const uint mylen = 12345; + static const char *const mydata = (char*) 0x20000000; + static uint offset = 0; + uint len = 0; + 80004c8: 2300 movs r3, #0 + 80004ca: 617b str r3, [r7, #20] + + // Check for data request or data sent notice + if (pptr) { + 80004cc: 68bb ldr r3, [r7, #8] + 80004ce: 2b00 cmp r3, #0 + 80004d0: d013 beq.n 80004fa + len = mylen - offset; + 80004d2: 4b15 ldr r3, [pc, #84] ; (8000528 ) + 80004d4: 681a ldr r2, [r3, #0] + 80004d6: 4b15 ldr r3, [pc, #84] ; (800052c ) + 80004d8: 681b ldr r3, [r3, #0] + 80004da: 1ad3 subs r3, r2, r3 + 80004dc: 617b str r3, [r7, #20] + if (len > maxlen) + 80004de: 697a ldr r2, [r7, #20] + 80004e0: 687b ldr r3, [r7, #4] + 80004e2: 429a cmp r2, r3 + 80004e4: d901 bls.n 80004ea + len = maxlen; + 80004e6: 687b ldr r3, [r7, #4] + 80004e8: 617b str r3, [r7, #20] + *pptr = mydata + offset; + 80004ea: 4b11 ldr r3, [pc, #68] ; (8000530 ) + 80004ec: 681a ldr r2, [r3, #0] + 80004ee: 4b0f ldr r3, [pc, #60] ; (800052c ) + 80004f0: 681b ldr r3, [r3, #0] + 80004f2: 441a add r2, r3 + 80004f4: 68bb ldr r3, [r7, #8] + 80004f6: 601a str r2, [r3, #0] + 80004f8: e00f b.n 800051a + } else { + offset += maxlen; + 80004fa: 4b0c ldr r3, [pc, #48] ; (800052c ) + 80004fc: 681a ldr r2, [r3, #0] + 80004fe: 687b ldr r3, [r7, #4] + 8000500: 4413 add r3, r2 + 8000502: 4a0a ldr r2, [pc, #40] ; (800052c ) + 8000504: 6013 str r3, [r2, #0] + if (offset > mylen) + 8000506: 4b09 ldr r3, [pc, #36] ; (800052c ) + 8000508: 681a ldr r2, [r3, #0] + 800050a: 4b07 ldr r3, [pc, #28] ; (8000528 ) + 800050c: 681b ldr r3, [r3, #0] + 800050e: 429a cmp r2, r3 + 8000510: d903 bls.n 800051a + offset = mylen; + 8000512: 4b05 ldr r3, [pc, #20] ; (8000528 ) + 8000514: 681b ldr r3, [r3, #0] + 8000516: 4a05 ldr r2, [pc, #20] ; (800052c ) + 8000518: 6013 str r3, [r2, #0] + } + return len; + 800051a: 697b ldr r3, [r7, #20] +} + 800051c: 4618 mov r0, r3 + 800051e: 371c adds r7, #28 + 8000520: 46bd mov sp, r7 + 8000522: f85d 7b04 ldr.w r7, [sp], #4 + 8000526: 4770 bx lr + 8000528: 08014c78 .word 0x08014c78 + 800052c: 240000ec .word 0x240000ec + 8000530: 08014c7c .word 0x08014c7c + +08000534 : + +static void ftp_connect_callback(void *arg, int result) { + 8000534: b580 push {r7, lr} + 8000536: b084 sub sp, #16 + 8000538: af00 add r7, sp, #0 + 800053a: 6078 str r0, [r7, #4] + 800053c: 6039 str r1, [r7, #0] + lwftp_session_t *s = (lwftp_session_t*) arg; + 800053e: 687b ldr r3, [r7, #4] + 8000540: 60fb str r3, [r7, #12] + err_t error; + if (result == LWFTP_RESULT_LOGGED) { + 8000542: 683b ldr r3, [r7, #0] + 8000544: 2b02 cmp r3, #2 + 8000546: d103 bne.n 8000550 + LOG_TRACE("login success !!!!! \r\n"); + 8000548: 4806 ldr r0, [pc, #24] ; (8000564 ) + 800054a: f7ff ffa9 bl 80004a0 + 800054e: e002 b.n 8000556 + } else { + LOG_TRACE("login failed !!!!! \r\n"); + 8000550: 4805 ldr r0, [pc, #20] ; (8000568 ) + 8000552: f7ff ffa5 bl 80004a0 +// return lwftp_close(s); +// } + + return + // Continue with STOR request + s->data_source = data_source; + 8000556: 68fb ldr r3, [r7, #12] + 8000558: 4a04 ldr r2, [pc, #16] ; (800056c ) + 800055a: 619a str r2, [r3, #24] + error = lwftp_store(s); + if (error != LWFTP_RESULT_INPROGRESS) { + LOG_ERROR("lwftp_store failed (%d)", error); + } + // FTP session will continue with STOR and source callbacks +} + 800055c: 3710 adds r7, #16 + 800055e: 46bd mov sp, r7 + 8000560: bd80 pop {r7, pc} + 8000562: bf00 nop + 8000564: 08011610 .word 0x08011610 + 8000568: 08011628 .word 0x08011628 + 800056c: 080004bd .word 0x080004bd + +08000570 : + +static void ftp_test(void) { + 8000570: b580 push {r7, lr} + 8000572: b082 sub sp, #8 + 8000574: af00 add r7, sp, #0 + static lwftp_session_t s; // static content for the whole FTP session + err_t error; + + // Initialize session data + memset(&s, 0, sizeof(s)); + 8000576: 2234 movs r2, #52 ; 0x34 + 8000578: 2100 movs r1, #0 + 800057a: 4814 ldr r0, [pc, #80] ; (80005cc ) + 800057c: f010 fc82 bl 8010e84 + + IP4_ADDR(&s.server_ip, 192, 168, 0, 100); + 8000580: 4b12 ldr r3, [pc, #72] ; (80005cc ) + 8000582: 4a13 ldr r2, [pc, #76] ; (80005d0 ) + 8000584: 601a str r2, [r3, #0] + s.server_port = 21; + 8000586: 4b11 ldr r3, [pc, #68] ; (80005cc ) + 8000588: 2215 movs r2, #21 + 800058a: 809a strh r2, [r3, #4] + s.done_fn = ftp_connect_callback; + 800058c: 4b0f ldr r3, [pc, #60] ; (80005cc ) + 800058e: 4a11 ldr r2, [pc, #68] ; (80005d4 ) + 8000590: 621a str r2, [r3, #32] + s.user = "anonymous"; // Anonymous client + 8000592: 4b0e ldr r3, [pc, #56] ; (80005cc ) + 8000594: 4a10 ldr r2, [pc, #64] ; (80005d8 ) + 8000596: 60da str r2, [r3, #12] + s.pass = "space2lim@naver.com"; + 8000598: 4b0c ldr r3, [pc, #48] ; (80005cc ) + 800059a: 4a10 ldr r2, [pc, #64] ; (80005dc ) + 800059c: 611a str r2, [r3, #16] + // We have no extra user data, simply use the session structure + s.handle = &s; + 800059e: 4b0b ldr r3, [pc, #44] ; (80005cc ) + 80005a0: 4a0a ldr r2, [pc, #40] ; (80005cc ) + 80005a2: 615a str r2, [r3, #20] + + // Start the connection state machine + error = lwftp_connect(&s); + 80005a4: 4809 ldr r0, [pc, #36] ; (80005cc ) + 80005a6: f004 fa09 bl 80049bc + 80005aa: 4603 mov r3, r0 + 80005ac: 71fb strb r3, [r7, #7] + if (error != LWFTP_RESULT_INPROGRESS) { + 80005ae: f997 3007 ldrsb.w r3, [r7, #7] + 80005b2: 2b01 cmp r3, #1 + 80005b4: d005 beq.n 80005c2 + LOG_ERROR("lwftp_connect failed (%d)", error); + 80005b6: f997 3007 ldrsb.w r3, [r7, #7] + 80005ba: 4619 mov r1, r3 + 80005bc: 4808 ldr r0, [pc, #32] ; (80005e0 ) + 80005be: f7ff ff43 bl 8000448 + } + // FTP session will continue with the connection callback +} + 80005c2: bf00 nop + 80005c4: 3708 adds r7, #8 + 80005c6: 46bd mov sp, r7 + 80005c8: bd80 pop {r7, pc} + 80005ca: bf00 nop + 80005cc: 240000f0 .word 0x240000f0 + 80005d0: 6400a8c0 .word 0x6400a8c0 + 80005d4: 08000535 .word 0x08000535 + 80005d8: 08011640 .word 0x08011640 + 80005dc: 0801164c .word 0x0801164c + 80005e0: 08011660 .word 0x08011660 + +080005e4
: + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) { + 80005e4: b580 push {r7, lr} + 80005e6: b084 sub sp, #16 + 80005e8: af00 add r7, sp, #0 + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MPU Configuration--------------------------------------------------------*/ + MPU_Config(); + 80005ea: f000 f929 bl 8000840 + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + 80005ee: 4b38 ldr r3, [pc, #224] ; (80006d0 ) + 80005f0: 695b ldr r3, [r3, #20] + 80005f2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80005f6: 2b00 cmp r3, #0 + 80005f8: d11b bne.n 8000632 + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 80005fa: f3bf 8f4f dsb sy +} + 80005fe: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 8000600: f3bf 8f6f isb sy +} + 8000604: bf00 nop + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + 8000606: 4b32 ldr r3, [pc, #200] ; (80006d0 ) + 8000608: 2200 movs r2, #0 + 800060a: f8c3 2250 str.w r2, [r3, #592] ; 0x250 + __ASM volatile ("dsb 0xF":::"memory"); + 800060e: f3bf 8f4f dsb sy +} + 8000612: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 8000614: f3bf 8f6f isb sy +} + 8000618: bf00 nop + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + 800061a: 4b2d ldr r3, [pc, #180] ; (80006d0 ) + 800061c: 695b ldr r3, [r3, #20] + 800061e: 4a2c ldr r2, [pc, #176] ; (80006d0 ) + 8000620: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8000624: 6153 str r3, [r2, #20] + __ASM volatile ("dsb 0xF":::"memory"); + 8000626: f3bf 8f4f dsb sy +} + 800062a: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 800062c: f3bf 8f6f isb sy +} + 8000630: e000 b.n 8000634 + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + 8000632: bf00 nop + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + 8000634: 4b26 ldr r3, [pc, #152] ; (80006d0 ) + 8000636: 695b ldr r3, [r3, #20] + 8000638: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800063c: 2b00 cmp r3, #0 + 800063e: d138 bne.n 80006b2 + SCB->CSSELR = 0U; /* select Level 1 data cache */ + 8000640: 4b23 ldr r3, [pc, #140] ; (80006d0 ) + 8000642: 2200 movs r2, #0 + 8000644: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + __ASM volatile ("dsb 0xF":::"memory"); + 8000648: f3bf 8f4f dsb sy +} + 800064c: bf00 nop + ccsidr = SCB->CCSIDR; + 800064e: 4b20 ldr r3, [pc, #128] ; (80006d0 ) + 8000650: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8000654: 60fb str r3, [r7, #12] + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + 8000656: 68fb ldr r3, [r7, #12] + 8000658: 0b5b lsrs r3, r3, #13 + 800065a: f3c3 030e ubfx r3, r3, #0, #15 + 800065e: 60bb str r3, [r7, #8] + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + 8000660: 68fb ldr r3, [r7, #12] + 8000662: 08db lsrs r3, r3, #3 + 8000664: f3c3 0309 ubfx r3, r3, #0, #10 + 8000668: 607b str r3, [r7, #4] + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + 800066a: 68bb ldr r3, [r7, #8] + 800066c: 015a lsls r2, r3, #5 + 800066e: f643 73e0 movw r3, #16352 ; 0x3fe0 + 8000672: 4013 ands r3, r2 + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + 8000674: 687a ldr r2, [r7, #4] + 8000676: 0792 lsls r2, r2, #30 + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + 8000678: 4915 ldr r1, [pc, #84] ; (80006d0 ) + 800067a: 4313 orrs r3, r2 + 800067c: f8c1 3260 str.w r3, [r1, #608] ; 0x260 + } while (ways-- != 0U); + 8000680: 687b ldr r3, [r7, #4] + 8000682: 1e5a subs r2, r3, #1 + 8000684: 607a str r2, [r7, #4] + 8000686: 2b00 cmp r3, #0 + 8000688: d1ef bne.n 800066a + } while(sets-- != 0U); + 800068a: 68bb ldr r3, [r7, #8] + 800068c: 1e5a subs r2, r3, #1 + 800068e: 60ba str r2, [r7, #8] + 8000690: 2b00 cmp r3, #0 + 8000692: d1e5 bne.n 8000660 + __ASM volatile ("dsb 0xF":::"memory"); + 8000694: f3bf 8f4f dsb sy +} + 8000698: bf00 nop + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + 800069a: 4b0d ldr r3, [pc, #52] ; (80006d0 ) + 800069c: 695b ldr r3, [r3, #20] + 800069e: 4a0c ldr r2, [pc, #48] ; (80006d0 ) + 80006a0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80006a4: 6153 str r3, [r2, #20] + __ASM volatile ("dsb 0xF":::"memory"); + 80006a6: f3bf 8f4f dsb sy +} + 80006aa: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 80006ac: f3bf 8f6f isb sy +} + 80006b0: e000 b.n 80006b4 + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + 80006b2: bf00 nop + SCB_EnableDCache(); + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 80006b4: f000 fc24 bl 8000f00 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 80006b8: f000 f80c bl 80006d4 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 80006bc: f000 f878 bl 80007b0 + MX_LWIP_Init(); + 80006c0: f004 fa04 bl 8004acc + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + + /* ============ LWFTP Code ============*/ + ftp_test(); + 80006c4: f7ff ff54 bl 8000570 +// ftp_connect(); + + while (1) { + MX_LWIP_Process(); + 80006c8: f004 fb40 bl 8004d4c + 80006cc: e7fc b.n 80006c8 + 80006ce: bf00 nop + 80006d0: e000ed00 .word 0xe000ed00 + +080006d4 : + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) { + 80006d4: b580 push {r7, lr} + 80006d6: b09c sub sp, #112 ; 0x70 + 80006d8: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + 80006da: f107 0324 add.w r3, r7, #36 ; 0x24 + 80006de: 224c movs r2, #76 ; 0x4c + 80006e0: 2100 movs r1, #0 + 80006e2: 4618 mov r0, r3 + 80006e4: f010 fbce bl 8010e84 + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + 80006e8: 1d3b adds r3, r7, #4 + 80006ea: 2220 movs r2, #32 + 80006ec: 2100 movs r1, #0 + 80006ee: 4618 mov r0, r3 + 80006f0: f010 fbc8 bl 8010e84 + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + 80006f4: 2002 movs r0, #2 + 80006f6: f002 fce9 bl 80030cc + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + 80006fa: 2300 movs r3, #0 + 80006fc: 603b str r3, [r7, #0] + 80006fe: 4b2b ldr r3, [pc, #172] ; (80007ac ) + 8000700: 699b ldr r3, [r3, #24] + 8000702: 4a2a ldr r2, [pc, #168] ; (80007ac ) + 8000704: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8000708: 6193 str r3, [r2, #24] + 800070a: 4b28 ldr r3, [pc, #160] ; (80007ac ) + 800070c: 699b ldr r3, [r3, #24] + 800070e: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8000712: 603b str r3, [r7, #0] + 8000714: 683b ldr r3, [r7, #0] + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) { + 8000716: bf00 nop + 8000718: 4b24 ldr r3, [pc, #144] ; (80007ac ) + 800071a: 699b ldr r3, [r3, #24] + 800071c: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8000720: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8000724: d1f8 bne.n 8000718 + } + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 8000726: 2301 movs r3, #1 + 8000728: 627b str r3, [r7, #36] ; 0x24 + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 800072a: f44f 3380 mov.w r3, #65536 ; 0x10000 + 800072e: 62bb str r3, [r7, #40] ; 0x28 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8000730: 2302 movs r3, #2 + 8000732: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + 8000734: 2302 movs r3, #2 + 8000736: 64fb str r3, [r7, #76] ; 0x4c + RCC_OscInitStruct.PLL.PLLM = 5; + 8000738: 2305 movs r3, #5 + 800073a: 653b str r3, [r7, #80] ; 0x50 + RCC_OscInitStruct.PLL.PLLN = 96; + 800073c: 2360 movs r3, #96 ; 0x60 + 800073e: 657b str r3, [r7, #84] ; 0x54 + RCC_OscInitStruct.PLL.PLLP = 1; + 8000740: 2301 movs r3, #1 + 8000742: 65bb str r3, [r7, #88] ; 0x58 + RCC_OscInitStruct.PLL.PLLQ = 2; + 8000744: 2302 movs r3, #2 + 8000746: 65fb str r3, [r7, #92] ; 0x5c + RCC_OscInitStruct.PLL.PLLR = 2; + 8000748: 2302 movs r3, #2 + 800074a: 663b str r3, [r7, #96] ; 0x60 + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + 800074c: 2308 movs r3, #8 + 800074e: 667b str r3, [r7, #100] ; 0x64 + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + 8000750: 2300 movs r3, #0 + 8000752: 66bb str r3, [r7, #104] ; 0x68 + RCC_OscInitStruct.PLL.PLLFRACN = 0; + 8000754: 2300 movs r3, #0 + 8000756: 66fb str r3, [r7, #108] ; 0x6c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + 8000758: f107 0324 add.w r3, r7, #36 ; 0x24 + 800075c: 4618 mov r0, r3 + 800075e: f002 fcef bl 8003140 + 8000762: 4603 mov r3, r0 + 8000764: 2b00 cmp r3, #0 + 8000766: d001 beq.n 800076c + Error_Handler(); + 8000768: f000 f8b7 bl 80008da + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + 800076c: 233f movs r3, #63 ; 0x3f + 800076e: 607b str r3, [r7, #4] + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 + | RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8000770: 2303 movs r3, #3 + 8000772: 60bb str r3, [r7, #8] + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + 8000774: 2300 movs r3, #0 + 8000776: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + 8000778: 2308 movs r3, #8 + 800077a: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + 800077c: 2340 movs r3, #64 ; 0x40 + 800077e: 617b str r3, [r7, #20] + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + 8000780: 2340 movs r3, #64 ; 0x40 + 8000782: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + 8000784: f44f 6380 mov.w r3, #1024 ; 0x400 + 8000788: 61fb str r3, [r7, #28] + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + 800078a: 2340 movs r3, #64 ; 0x40 + 800078c: 623b str r3, [r7, #32] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + 800078e: 1d3b adds r3, r7, #4 + 8000790: 2103 movs r1, #3 + 8000792: 4618 mov r0, r3 + 8000794: f003 f8ae bl 80038f4 + 8000798: 4603 mov r3, r0 + 800079a: 2b00 cmp r3, #0 + 800079c: d001 beq.n 80007a2 + Error_Handler(); + 800079e: f000 f89c bl 80008da + } +} + 80007a2: bf00 nop + 80007a4: 3770 adds r7, #112 ; 0x70 + 80007a6: 46bd mov sp, r7 + 80007a8: bd80 pop {r7, pc} + 80007aa: bf00 nop + 80007ac: 58024800 .word 0x58024800 + +080007b0 : +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) { + 80007b0: b480 push {r7} + 80007b2: b085 sub sp, #20 + 80007b4: af00 add r7, sp, #0 + /* USER CODE BEGIN MX_GPIO_Init_1 */ + /* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 80007b6: 4b21 ldr r3, [pc, #132] ; (800083c ) + 80007b8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 80007bc: 4a1f ldr r2, [pc, #124] ; (800083c ) + 80007be: f043 0302 orr.w r3, r3, #2 + 80007c2: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 + 80007c6: 4b1d ldr r3, [pc, #116] ; (800083c ) + 80007c8: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 80007cc: f003 0302 and.w r3, r3, #2 + 80007d0: 60fb str r3, [r7, #12] + 80007d2: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80007d4: 4b19 ldr r3, [pc, #100] ; (800083c ) + 80007d6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 80007da: 4a18 ldr r2, [pc, #96] ; (800083c ) + 80007dc: f043 0301 orr.w r3, r3, #1 + 80007e0: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 + 80007e4: 4b15 ldr r3, [pc, #84] ; (800083c ) + 80007e6: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 80007ea: f003 0301 and.w r3, r3, #1 + 80007ee: 60bb str r3, [r7, #8] + 80007f0: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 80007f2: 4b12 ldr r3, [pc, #72] ; (800083c ) + 80007f4: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 80007f8: 4a10 ldr r2, [pc, #64] ; (800083c ) + 80007fa: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80007fe: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 + 8000802: 4b0e ldr r3, [pc, #56] ; (800083c ) + 8000804: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8000808: f003 0380 and.w r3, r3, #128 ; 0x80 + 800080c: 607b str r3, [r7, #4] + 800080e: 687b ldr r3, [r7, #4] + __HAL_RCC_GPIOC_CLK_ENABLE(); + 8000810: 4b0a ldr r3, [pc, #40] ; (800083c ) + 8000812: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8000816: 4a09 ldr r2, [pc, #36] ; (800083c ) + 8000818: f043 0304 orr.w r3, r3, #4 + 800081c: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 + 8000820: 4b06 ldr r3, [pc, #24] ; (800083c ) + 8000822: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8000826: f003 0304 and.w r3, r3, #4 + 800082a: 603b str r3, [r7, #0] + 800082c: 683b ldr r3, [r7, #0] + + /* USER CODE BEGIN MX_GPIO_Init_2 */ + /* USER CODE END MX_GPIO_Init_2 */ +} + 800082e: bf00 nop + 8000830: 3714 adds r7, #20 + 8000832: 46bd mov sp, r7 + 8000834: f85d 7b04 ldr.w r7, [sp], #4 + 8000838: 4770 bx lr + 800083a: bf00 nop + 800083c: 58024400 .word 0x58024400 + +08000840 : + +/* USER CODE END 4 */ + +/* MPU Configuration */ + +void MPU_Config(void) { + 8000840: b580 push {r7, lr} + 8000842: b084 sub sp, #16 + 8000844: af00 add r7, sp, #0 + MPU_Region_InitTypeDef MPU_InitStruct = { 0 }; + 8000846: 463b mov r3, r7 + 8000848: 2200 movs r2, #0 + 800084a: 601a str r2, [r3, #0] + 800084c: 605a str r2, [r3, #4] + 800084e: 609a str r2, [r3, #8] + 8000850: 60da str r2, [r3, #12] + + /* Disables the MPU */ + HAL_MPU_Disable(); + 8000852: f000 fd0b bl 800126c + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + 8000856: 2301 movs r3, #1 + 8000858: 703b strb r3, [r7, #0] + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + 800085a: 2300 movs r3, #0 + 800085c: 707b strb r3, [r7, #1] + MPU_InitStruct.BaseAddress = 0x0; + 800085e: 2300 movs r3, #0 + 8000860: 607b str r3, [r7, #4] + MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; + 8000862: 231f movs r3, #31 + 8000864: 723b strb r3, [r7, #8] + MPU_InitStruct.SubRegionDisable = 0x87; + 8000866: 2387 movs r3, #135 ; 0x87 + 8000868: 727b strb r3, [r7, #9] + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + 800086a: 2300 movs r3, #0 + 800086c: 72bb strb r3, [r7, #10] + MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; + 800086e: 2300 movs r3, #0 + 8000870: 72fb strb r3, [r7, #11] + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + 8000872: 2301 movs r3, #1 + 8000874: 733b strb r3, [r7, #12] + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + 8000876: 2301 movs r3, #1 + 8000878: 737b strb r3, [r7, #13] + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + 800087a: 2300 movs r3, #0 + 800087c: 73bb strb r3, [r7, #14] + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + 800087e: 2300 movs r3, #0 + 8000880: 73fb strb r3, [r7, #15] + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + 8000882: 463b mov r3, r7 + 8000884: 4618 mov r0, r3 + 8000886: f000 fd29 bl 80012dc + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER1; + 800088a: 2301 movs r3, #1 + 800088c: 707b strb r3, [r7, #1] + MPU_InitStruct.BaseAddress = 0x30000000; + 800088e: f04f 5340 mov.w r3, #805306368 ; 0x30000000 + 8000892: 607b str r3, [r7, #4] + MPU_InitStruct.Size = MPU_REGION_SIZE_32KB; + 8000894: 230e movs r3, #14 + 8000896: 723b strb r3, [r7, #8] + MPU_InitStruct.SubRegionDisable = 0x0; + 8000898: 2300 movs r3, #0 + 800089a: 727b strb r3, [r7, #9] + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; + 800089c: 2301 movs r3, #1 + 800089e: 72bb strb r3, [r7, #10] + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + 80008a0: 2303 movs r3, #3 + 80008a2: 72fb strb r3, [r7, #11] + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + 80008a4: 2300 movs r3, #0 + 80008a6: 737b strb r3, [r7, #13] + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + 80008a8: 463b mov r3, r7 + 80008aa: 4618 mov r0, r3 + 80008ac: f000 fd16 bl 80012dc + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Number = MPU_REGION_NUMBER2; + 80008b0: 2302 movs r3, #2 + 80008b2: 707b strb r3, [r7, #1] + MPU_InitStruct.Size = MPU_REGION_SIZE_512B; + 80008b4: 2308 movs r3, #8 + 80008b6: 723b strb r3, [r7, #8] + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + 80008b8: 2300 movs r3, #0 + 80008ba: 72bb strb r3, [r7, #10] + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + 80008bc: 2301 movs r3, #1 + 80008be: 737b strb r3, [r7, #13] + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; + 80008c0: 2301 movs r3, #1 + 80008c2: 73fb strb r3, [r7, #15] + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + 80008c4: 463b mov r3, r7 + 80008c6: 4618 mov r0, r3 + 80008c8: f000 fd08 bl 80012dc + /* Enables the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + 80008cc: 2004 movs r0, #4 + 80008ce: f000 fce5 bl 800129c + +} + 80008d2: bf00 nop + 80008d4: 3710 adds r7, #16 + 80008d6: 46bd mov sp, r7 + 80008d8: bd80 pop {r7, pc} + +080008da : + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) { + 80008da: b480 push {r7} + 80008dc: af00 add r7, sp, #0 + __ASM volatile ("cpsid i" : : : "memory"); + 80008de: b672 cpsid i +} + 80008e0: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) { + 80008e2: e7fe b.n 80008e2 + +080008e4 : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 80008e4: b480 push {r7} + 80008e6: b083 sub sp, #12 + 80008e8: af00 add r7, sp, #0 + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 80008ea: 4b0a ldr r3, [pc, #40] ; (8000914 ) + 80008ec: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 + 80008f0: 4a08 ldr r2, [pc, #32] ; (8000914 ) + 80008f2: f043 0302 orr.w r3, r3, #2 + 80008f6: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 + 80008fa: 4b06 ldr r3, [pc, #24] ; (8000914 ) + 80008fc: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 + 8000900: f003 0302 and.w r3, r3, #2 + 8000904: 607b str r3, [r7, #4] + 8000906: 687b ldr r3, [r7, #4] + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000908: bf00 nop + 800090a: 370c adds r7, #12 + 800090c: 46bd mov sp, r7 + 800090e: f85d 7b04 ldr.w r7, [sp], #4 + 8000912: 4770 bx lr + 8000914: 58024400 .word 0x58024400 + +08000918 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000918: b480 push {r7} + 800091a: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 800091c: e7fe b.n 800091c + +0800091e : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 800091e: b480 push {r7} + 8000920: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000922: e7fe b.n 8000922 + +08000924 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000924: b480 push {r7} + 8000926: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000928: e7fe b.n 8000928 + +0800092a : + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 800092a: b480 push {r7} + 800092c: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 800092e: e7fe b.n 800092e + +08000930 : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000930: b480 push {r7} + 8000932: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000934: e7fe b.n 8000934 + +08000936 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000936: b480 push {r7} + 8000938: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 800093a: bf00 nop + 800093c: 46bd mov sp, r7 + 800093e: f85d 7b04 ldr.w r7, [sp], #4 + 8000942: 4770 bx lr + +08000944 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000944: b480 push {r7} + 8000946: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000948: bf00 nop + 800094a: 46bd mov sp, r7 + 800094c: f85d 7b04 ldr.w r7, [sp], #4 + 8000950: 4770 bx lr + +08000952 : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000952: b480 push {r7} + 8000954: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000956: bf00 nop + 8000958: 46bd mov sp, r7 + 800095a: f85d 7b04 ldr.w r7, [sp], #4 + 800095e: 4770 bx lr + +08000960 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000960: b580 push {r7, lr} + 8000962: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000964: f000 fb3e bl 8000fe4 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000968: bf00 nop + 800096a: bd80 pop {r7, pc} + +0800096c : + +/** + * @brief This function handles Ethernet global interrupt. + */ +void ETH_IRQHandler(void) +{ + 800096c: b580 push {r7, lr} + 800096e: af00 add r7, sp, #0 + /* USER CODE BEGIN ETH_IRQn 0 */ + + /* USER CODE END ETH_IRQn 0 */ + HAL_ETH_IRQHandler(&heth); + 8000970: 4802 ldr r0, [pc, #8] ; (800097c ) + 8000972: f001 f855 bl 8001a20 + /* USER CODE BEGIN ETH_IRQn 1 */ + + /* USER CODE END ETH_IRQn 1 */ +} + 8000976: bf00 nop + 8000978: bd80 pop {r7, pc} + 800097a: bf00 nop + 800097c: 24004b08 .word 0x24004b08 + +08000980 <_getpid>: +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + 8000980: b480 push {r7} + 8000982: af00 add r7, sp, #0 + return 1; + 8000984: 2301 movs r3, #1 +} + 8000986: 4618 mov r0, r3 + 8000988: 46bd mov sp, r7 + 800098a: f85d 7b04 ldr.w r7, [sp], #4 + 800098e: 4770 bx lr + +08000990 <_kill>: + +int _kill(int pid, int sig) +{ + 8000990: b480 push {r7} + 8000992: b083 sub sp, #12 + 8000994: af00 add r7, sp, #0 + 8000996: 6078 str r0, [r7, #4] + 8000998: 6039 str r1, [r7, #0] + (void)pid; + (void)sig; + errno = EINVAL; + 800099a: 4b05 ldr r3, [pc, #20] ; (80009b0 <_kill+0x20>) + 800099c: 2216 movs r2, #22 + 800099e: 601a str r2, [r3, #0] + return -1; + 80009a0: f04f 33ff mov.w r3, #4294967295 +} + 80009a4: 4618 mov r0, r3 + 80009a6: 370c adds r7, #12 + 80009a8: 46bd mov sp, r7 + 80009aa: f85d 7b04 ldr.w r7, [sp], #4 + 80009ae: 4770 bx lr + 80009b0: 24007e08 .word 0x24007e08 + +080009b4 <_exit>: + +void _exit (int status) +{ + 80009b4: b580 push {r7, lr} + 80009b6: b082 sub sp, #8 + 80009b8: af00 add r7, sp, #0 + 80009ba: 6078 str r0, [r7, #4] + _kill(status, -1); + 80009bc: f04f 31ff mov.w r1, #4294967295 + 80009c0: 6878 ldr r0, [r7, #4] + 80009c2: f7ff ffe5 bl 8000990 <_kill> + while (1) {} /* Make sure we hang here */ + 80009c6: e7fe b.n 80009c6 <_exit+0x12> + +080009c8 <_read>: +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + 80009c8: b580 push {r7, lr} + 80009ca: b086 sub sp, #24 + 80009cc: af00 add r7, sp, #0 + 80009ce: 60f8 str r0, [r7, #12] + 80009d0: 60b9 str r1, [r7, #8] + 80009d2: 607a str r2, [r7, #4] + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 80009d4: 2300 movs r3, #0 + 80009d6: 617b str r3, [r7, #20] + 80009d8: e00a b.n 80009f0 <_read+0x28> + { + *ptr++ = __io_getchar(); + 80009da: f3af 8000 nop.w + 80009de: 4601 mov r1, r0 + 80009e0: 68bb ldr r3, [r7, #8] + 80009e2: 1c5a adds r2, r3, #1 + 80009e4: 60ba str r2, [r7, #8] + 80009e6: b2ca uxtb r2, r1 + 80009e8: 701a strb r2, [r3, #0] + for (DataIdx = 0; DataIdx < len; DataIdx++) + 80009ea: 697b ldr r3, [r7, #20] + 80009ec: 3301 adds r3, #1 + 80009ee: 617b str r3, [r7, #20] + 80009f0: 697a ldr r2, [r7, #20] + 80009f2: 687b ldr r3, [r7, #4] + 80009f4: 429a cmp r2, r3 + 80009f6: dbf0 blt.n 80009da <_read+0x12> + } + + return len; + 80009f8: 687b ldr r3, [r7, #4] +} + 80009fa: 4618 mov r0, r3 + 80009fc: 3718 adds r7, #24 + 80009fe: 46bd mov sp, r7 + 8000a00: bd80 pop {r7, pc} + +08000a02 <_close>: + } + return len; +} + +int _close(int file) +{ + 8000a02: b480 push {r7} + 8000a04: b083 sub sp, #12 + 8000a06: af00 add r7, sp, #0 + 8000a08: 6078 str r0, [r7, #4] + (void)file; + return -1; + 8000a0a: f04f 33ff mov.w r3, #4294967295 +} + 8000a0e: 4618 mov r0, r3 + 8000a10: 370c adds r7, #12 + 8000a12: 46bd mov sp, r7 + 8000a14: f85d 7b04 ldr.w r7, [sp], #4 + 8000a18: 4770 bx lr + +08000a1a <_fstat>: + + +int _fstat(int file, struct stat *st) +{ + 8000a1a: b480 push {r7} + 8000a1c: b083 sub sp, #12 + 8000a1e: af00 add r7, sp, #0 + 8000a20: 6078 str r0, [r7, #4] + 8000a22: 6039 str r1, [r7, #0] + (void)file; + st->st_mode = S_IFCHR; + 8000a24: 683b ldr r3, [r7, #0] + 8000a26: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8000a2a: 605a str r2, [r3, #4] + return 0; + 8000a2c: 2300 movs r3, #0 +} + 8000a2e: 4618 mov r0, r3 + 8000a30: 370c adds r7, #12 + 8000a32: 46bd mov sp, r7 + 8000a34: f85d 7b04 ldr.w r7, [sp], #4 + 8000a38: 4770 bx lr + +08000a3a <_isatty>: + +int _isatty(int file) +{ + 8000a3a: b480 push {r7} + 8000a3c: b083 sub sp, #12 + 8000a3e: af00 add r7, sp, #0 + 8000a40: 6078 str r0, [r7, #4] + (void)file; + return 1; + 8000a42: 2301 movs r3, #1 +} + 8000a44: 4618 mov r0, r3 + 8000a46: 370c adds r7, #12 + 8000a48: 46bd mov sp, r7 + 8000a4a: f85d 7b04 ldr.w r7, [sp], #4 + 8000a4e: 4770 bx lr + +08000a50 <_lseek>: + +int _lseek(int file, int ptr, int dir) +{ + 8000a50: b480 push {r7} + 8000a52: b085 sub sp, #20 + 8000a54: af00 add r7, sp, #0 + 8000a56: 60f8 str r0, [r7, #12] + 8000a58: 60b9 str r1, [r7, #8] + 8000a5a: 607a str r2, [r7, #4] + (void)file; + (void)ptr; + (void)dir; + return 0; + 8000a5c: 2300 movs r3, #0 +} + 8000a5e: 4618 mov r0, r3 + 8000a60: 3714 adds r7, #20 + 8000a62: 46bd mov sp, r7 + 8000a64: f85d 7b04 ldr.w r7, [sp], #4 + 8000a68: 4770 bx lr + ... + +08000a6c <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 8000a6c: b480 push {r7} + 8000a6e: b087 sub sp, #28 + 8000a70: af00 add r7, sp, #0 + 8000a72: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 8000a74: 4a14 ldr r2, [pc, #80] ; (8000ac8 <_sbrk+0x5c>) + 8000a76: 4b15 ldr r3, [pc, #84] ; (8000acc <_sbrk+0x60>) + 8000a78: 1ad3 subs r3, r2, r3 + 8000a7a: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 8000a7c: 697b ldr r3, [r7, #20] + 8000a7e: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 8000a80: 4b13 ldr r3, [pc, #76] ; (8000ad0 <_sbrk+0x64>) + 8000a82: 681b ldr r3, [r3, #0] + 8000a84: 2b00 cmp r3, #0 + 8000a86: d102 bne.n 8000a8e <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 8000a88: 4b11 ldr r3, [pc, #68] ; (8000ad0 <_sbrk+0x64>) + 8000a8a: 4a12 ldr r2, [pc, #72] ; (8000ad4 <_sbrk+0x68>) + 8000a8c: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 8000a8e: 4b10 ldr r3, [pc, #64] ; (8000ad0 <_sbrk+0x64>) + 8000a90: 681a ldr r2, [r3, #0] + 8000a92: 687b ldr r3, [r7, #4] + 8000a94: 4413 add r3, r2 + 8000a96: 693a ldr r2, [r7, #16] + 8000a98: 429a cmp r2, r3 + 8000a9a: d205 bcs.n 8000aa8 <_sbrk+0x3c> + { + errno = ENOMEM; + 8000a9c: 4b0e ldr r3, [pc, #56] ; (8000ad8 <_sbrk+0x6c>) + 8000a9e: 220c movs r2, #12 + 8000aa0: 601a str r2, [r3, #0] + return (void *)-1; + 8000aa2: f04f 33ff mov.w r3, #4294967295 + 8000aa6: e009 b.n 8000abc <_sbrk+0x50> + } + + prev_heap_end = __sbrk_heap_end; + 8000aa8: 4b09 ldr r3, [pc, #36] ; (8000ad0 <_sbrk+0x64>) + 8000aaa: 681b ldr r3, [r3, #0] + 8000aac: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 8000aae: 4b08 ldr r3, [pc, #32] ; (8000ad0 <_sbrk+0x64>) + 8000ab0: 681a ldr r2, [r3, #0] + 8000ab2: 687b ldr r3, [r7, #4] + 8000ab4: 4413 add r3, r2 + 8000ab6: 4a06 ldr r2, [pc, #24] ; (8000ad0 <_sbrk+0x64>) + 8000ab8: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 8000aba: 68fb ldr r3, [r7, #12] +} + 8000abc: 4618 mov r0, r3 + 8000abe: 371c adds r7, #28 + 8000ac0: 46bd mov sp, r7 + 8000ac2: f85d 7b04 ldr.w r7, [sp], #4 + 8000ac6: 4770 bx lr + 8000ac8: 24050000 .word 0x24050000 + 8000acc: 00000400 .word 0x00000400 + 8000ad0: 24000124 .word 0x24000124 + 8000ad4: 24007e18 .word 0x24007e18 + 8000ad8: 24007e08 .word 0x24007e08 + +08000adc : + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ + 8000adc: b480 push {r7} + 8000ade: b083 sub sp, #12 + 8000ae0: af00 add r7, sp, #0 + __IO uint32_t tmpreg; +#endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + 8000ae2: 4b3a ldr r3, [pc, #232] ; (8000bcc ) + 8000ae4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8000ae8: 4a38 ldr r2, [pc, #224] ; (8000bcc ) + 8000aea: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8000aee: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + 8000af2: 4b37 ldr r3, [pc, #220] ; (8000bd0 ) + 8000af4: 681b ldr r3, [r3, #0] + 8000af6: f003 030f and.w r3, r3, #15 + 8000afa: 2b06 cmp r3, #6 + 8000afc: d807 bhi.n 8000b0e + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + 8000afe: 4b34 ldr r3, [pc, #208] ; (8000bd0 ) + 8000b00: 681b ldr r3, [r3, #0] + 8000b02: f023 030f bic.w r3, r3, #15 + 8000b06: 4a32 ldr r2, [pc, #200] ; (8000bd0 ) + 8000b08: f043 0307 orr.w r3, r3, #7 + 8000b0c: 6013 str r3, [r2, #0] + } + + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + 8000b0e: 4b31 ldr r3, [pc, #196] ; (8000bd4 ) + 8000b10: 681b ldr r3, [r3, #0] + 8000b12: 4a30 ldr r2, [pc, #192] ; (8000bd4 ) + 8000b14: f043 0301 orr.w r3, r3, #1 + 8000b18: 6013 str r3, [r2, #0] + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + 8000b1a: 4b2e ldr r3, [pc, #184] ; (8000bd4 ) + 8000b1c: 2200 movs r2, #0 + 8000b1e: 611a str r2, [r3, #16] + + /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + 8000b20: 4b2c ldr r3, [pc, #176] ; (8000bd4 ) + 8000b22: 681a ldr r2, [r3, #0] + 8000b24: 492b ldr r1, [pc, #172] ; (8000bd4 ) + 8000b26: 4b2c ldr r3, [pc, #176] ; (8000bd8 ) + 8000b28: 4013 ands r3, r2 + 8000b2a: 600b str r3, [r1, #0] + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + 8000b2c: 4b28 ldr r3, [pc, #160] ; (8000bd0 ) + 8000b2e: 681b ldr r3, [r3, #0] + 8000b30: f003 0308 and.w r3, r3, #8 + 8000b34: 2b00 cmp r3, #0 + 8000b36: d007 beq.n 8000b48 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + 8000b38: 4b25 ldr r3, [pc, #148] ; (8000bd0 ) + 8000b3a: 681b ldr r3, [r3, #0] + 8000b3c: f023 030f bic.w r3, r3, #15 + 8000b40: 4a23 ldr r2, [pc, #140] ; (8000bd0 ) + 8000b42: f043 0307 orr.w r3, r3, #7 + 8000b46: 6013 str r3, [r2, #0] + } + +#if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + 8000b48: 4b22 ldr r3, [pc, #136] ; (8000bd4 ) + 8000b4a: 2200 movs r2, #0 + 8000b4c: 619a str r2, [r3, #24] + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + 8000b4e: 4b21 ldr r3, [pc, #132] ; (8000bd4 ) + 8000b50: 2200 movs r2, #0 + 8000b52: 61da str r2, [r3, #28] + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; + 8000b54: 4b1f ldr r3, [pc, #124] ; (8000bd4 ) + 8000b56: 2200 movs r2, #0 + 8000b58: 621a str r2, [r3, #32] + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x02020200; + 8000b5a: 4b1e ldr r3, [pc, #120] ; (8000bd4 ) + 8000b5c: 4a1f ldr r2, [pc, #124] ; (8000bdc ) + 8000b5e: 629a str r2, [r3, #40] ; 0x28 + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x01FF0000; + 8000b60: 4b1c ldr r3, [pc, #112] ; (8000bd4 ) + 8000b62: 4a1f ldr r2, [pc, #124] ; (8000be0 ) + 8000b64: 62da str r2, [r3, #44] ; 0x2c + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280; + 8000b66: 4b1b ldr r3, [pc, #108] ; (8000bd4 ) + 8000b68: 4a1e ldr r2, [pc, #120] ; (8000be4 ) + 8000b6a: 631a str r2, [r3, #48] ; 0x30 + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + 8000b6c: 4b19 ldr r3, [pc, #100] ; (8000bd4 ) + 8000b6e: 2200 movs r2, #0 + 8000b70: 635a str r2, [r3, #52] ; 0x34 + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280; + 8000b72: 4b18 ldr r3, [pc, #96] ; (8000bd4 ) + 8000b74: 4a1b ldr r2, [pc, #108] ; (8000be4 ) + 8000b76: 639a str r2, [r3, #56] ; 0x38 + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + 8000b78: 4b16 ldr r3, [pc, #88] ; (8000bd4 ) + 8000b7a: 2200 movs r2, #0 + 8000b7c: 63da str r2, [r3, #60] ; 0x3c + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280; + 8000b7e: 4b15 ldr r3, [pc, #84] ; (8000bd4 ) + 8000b80: 4a18 ldr r2, [pc, #96] ; (8000be4 ) + 8000b82: 641a str r2, [r3, #64] ; 0x40 + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + 8000b84: 4b13 ldr r3, [pc, #76] ; (8000bd4 ) + 8000b86: 2200 movs r2, #0 + 8000b88: 645a str r2, [r3, #68] ; 0x44 + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + 8000b8a: 4b12 ldr r3, [pc, #72] ; (8000bd4 ) + 8000b8c: 681b ldr r3, [r3, #0] + 8000b8e: 4a11 ldr r2, [pc, #68] ; (8000bd4 ) + 8000b90: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8000b94: 6013 str r3, [r2, #0] + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + 8000b96: 4b0f ldr r3, [pc, #60] ; (8000bd4 ) + 8000b98: 2200 movs r2, #0 + 8000b9a: 661a str r2, [r3, #96] ; 0x60 +#if defined(DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); + 8000b9c: 4b0d ldr r3, [pc, #52] ; (8000bd4 ) + 8000b9e: f8d3 30dc ldr.w r3, [r3, #220] ; 0xdc + 8000ba2: 4a0c ldr r2, [pc, #48] ; (8000bd4 ) + 8000ba4: f043 43c0 orr.w r3, r3, #1610612736 ; 0x60000000 + 8000ba8: f8c2 30dc str.w r3, [r2, #220] ; 0xdc +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + 8000bac: 4b09 ldr r3, [pc, #36] ; (8000bd4 ) + 8000bae: f8d3 30dc ldr.w r3, [r3, #220] ; 0xdc + 8000bb2: 607b str r3, [r7, #4] + (void) tmpreg; + 8000bb4: 687b ldr r3, [r7, #4] + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + 8000bb6: 4b0c ldr r3, [pc, #48] ; (8000be8 ) + 8000bb8: f243 02d2 movw r2, #12498 ; 0x30d2 + 8000bbc: 601a str r2, [r3, #0] +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#endif /*DUAL_CORE && CORE_CM4*/ +} + 8000bbe: bf00 nop + 8000bc0: 370c adds r7, #12 + 8000bc2: 46bd mov sp, r7 + 8000bc4: f85d 7b04 ldr.w r7, [sp], #4 + 8000bc8: 4770 bx lr + 8000bca: bf00 nop + 8000bcc: e000ed00 .word 0xe000ed00 + 8000bd0: 52002000 .word 0x52002000 + 8000bd4: 58024400 .word 0x58024400 + 8000bd8: eaf6ed7f .word 0xeaf6ed7f + 8000bdc: 02020200 .word 0x02020200 + 8000be0: 01ff0000 .word 0x01ff0000 + 8000be4: 01010280 .word 0x01010280 + 8000be8: 52004000 .word 0x52004000 + +08000bec : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + 8000bec: f8df d034 ldr.w sp, [pc, #52] ; 8000c24 + +/* Call the clock system initialization function.*/ + bl SystemInit + 8000bf0: f7ff ff74 bl 8000adc + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8000bf4: 480c ldr r0, [pc, #48] ; (8000c28 ) + ldr r1, =_edata + 8000bf6: 490d ldr r1, [pc, #52] ; (8000c2c ) + ldr r2, =_sidata + 8000bf8: 4a0d ldr r2, [pc, #52] ; (8000c30 ) + movs r3, #0 + 8000bfa: 2300 movs r3, #0 + b LoopCopyDataInit + 8000bfc: e002 b.n 8000c04 + +08000bfe : + +CopyDataInit: + ldr r4, [r2, r3] + 8000bfe: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8000c00: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8000c02: 3304 adds r3, #4 + +08000c04 : + +LoopCopyDataInit: + adds r4, r0, r3 + 8000c04: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8000c06: 428c cmp r4, r1 + bcc CopyDataInit + 8000c08: d3f9 bcc.n 8000bfe +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8000c0a: 4a0a ldr r2, [pc, #40] ; (8000c34 ) + ldr r4, =_ebss + 8000c0c: 4c0a ldr r4, [pc, #40] ; (8000c38 ) + movs r3, #0 + 8000c0e: 2300 movs r3, #0 + b LoopFillZerobss + 8000c10: e001 b.n 8000c16 + +08000c12 : + +FillZerobss: + str r3, [r2] + 8000c12: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8000c14: 3204 adds r2, #4 + +08000c16 : + +LoopFillZerobss: + cmp r2, r4 + 8000c16: 42a2 cmp r2, r4 + bcc FillZerobss + 8000c18: d3fb bcc.n 8000c12 + +/* Call static constructors */ + bl __libc_init_array + 8000c1a: f010 f98f bl 8010f3c <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8000c1e: f7ff fce1 bl 80005e4
+ bx lr + 8000c22: 4770 bx lr + ldr sp, =_estack /* set stack pointer */ + 8000c24: 24050000 .word 0x24050000 + ldr r0, =_sdata + 8000c28: 24000000 .word 0x24000000 + ldr r1, =_edata + 8000c2c: 240000d0 .word 0x240000d0 + ldr r2, =_sidata + 8000c30: 08014f90 .word 0x08014f90 + ldr r2, =_sbss + 8000c34: 240000d0 .word 0x240000d0 + ldr r4, =_ebss + 8000c38: 24007e18 .word 0x24007e18 + +08000c3c : + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000c3c: e7fe b.n 8000c3c + +08000c3e : + * @param ioctx: holds device IO functions. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_ERROR if missing mandatory function + */ +int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx) +{ + 8000c3e: b480 push {r7} + 8000c40: b083 sub sp, #12 + 8000c42: af00 add r7, sp, #0 + 8000c44: 6078 str r0, [r7, #4] + 8000c46: 6039 str r1, [r7, #0] + if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick) + 8000c48: 687b ldr r3, [r7, #4] + 8000c4a: 2b00 cmp r3, #0 + 8000c4c: d00b beq.n 8000c66 + 8000c4e: 683b ldr r3, [r7, #0] + 8000c50: 68db ldr r3, [r3, #12] + 8000c52: 2b00 cmp r3, #0 + 8000c54: d007 beq.n 8000c66 + 8000c56: 683b ldr r3, [r7, #0] + 8000c58: 689b ldr r3, [r3, #8] + 8000c5a: 2b00 cmp r3, #0 + 8000c5c: d003 beq.n 8000c66 + 8000c5e: 683b ldr r3, [r7, #0] + 8000c60: 691b ldr r3, [r3, #16] + 8000c62: 2b00 cmp r3, #0 + 8000c64: d102 bne.n 8000c6c + { + return LAN8742_STATUS_ERROR; + 8000c66: f04f 33ff mov.w r3, #4294967295 + 8000c6a: e014 b.n 8000c96 + } + + pObj->IO.Init = ioctx->Init; + 8000c6c: 683b ldr r3, [r7, #0] + 8000c6e: 681a ldr r2, [r3, #0] + 8000c70: 687b ldr r3, [r7, #4] + 8000c72: 609a str r2, [r3, #8] + pObj->IO.DeInit = ioctx->DeInit; + 8000c74: 683b ldr r3, [r7, #0] + 8000c76: 685a ldr r2, [r3, #4] + 8000c78: 687b ldr r3, [r7, #4] + 8000c7a: 60da str r2, [r3, #12] + pObj->IO.ReadReg = ioctx->ReadReg; + 8000c7c: 683b ldr r3, [r7, #0] + 8000c7e: 68da ldr r2, [r3, #12] + 8000c80: 687b ldr r3, [r7, #4] + 8000c82: 615a str r2, [r3, #20] + pObj->IO.WriteReg = ioctx->WriteReg; + 8000c84: 683b ldr r3, [r7, #0] + 8000c86: 689a ldr r2, [r3, #8] + 8000c88: 687b ldr r3, [r7, #4] + 8000c8a: 611a str r2, [r3, #16] + pObj->IO.GetTick = ioctx->GetTick; + 8000c8c: 683b ldr r3, [r7, #0] + 8000c8e: 691a ldr r2, [r3, #16] + 8000c90: 687b ldr r3, [r7, #4] + 8000c92: 619a str r2, [r3, #24] + + return LAN8742_STATUS_OK; + 8000c94: 2300 movs r3, #0 +} + 8000c96: 4618 mov r0, r3 + 8000c98: 370c adds r7, #12 + 8000c9a: 46bd mov sp, r7 + 8000c9c: f85d 7b04 ldr.w r7, [sp], #4 + 8000ca0: 4770 bx lr + +08000ca2 : + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + * LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset + */ + int32_t LAN8742_Init(lan8742_Object_t *pObj) + { + 8000ca2: b580 push {r7, lr} + 8000ca4: b086 sub sp, #24 + 8000ca6: af00 add r7, sp, #0 + 8000ca8: 6078 str r0, [r7, #4] + uint32_t tickstart = 0, regvalue = 0, addr = 0; + 8000caa: 2300 movs r3, #0 + 8000cac: 60fb str r3, [r7, #12] + 8000cae: 2300 movs r3, #0 + 8000cb0: 60bb str r3, [r7, #8] + 8000cb2: 2300 movs r3, #0 + 8000cb4: 617b str r3, [r7, #20] + int32_t status = LAN8742_STATUS_OK; + 8000cb6: 2300 movs r3, #0 + 8000cb8: 613b str r3, [r7, #16] + + if(pObj->Is_Initialized == 0) + 8000cba: 687b ldr r3, [r7, #4] + 8000cbc: 685b ldr r3, [r3, #4] + 8000cbe: 2b00 cmp r3, #0 + 8000cc0: d17c bne.n 8000dbc + { + if(pObj->IO.Init != 0) + 8000cc2: 687b ldr r3, [r7, #4] + 8000cc4: 689b ldr r3, [r3, #8] + 8000cc6: 2b00 cmp r3, #0 + 8000cc8: d002 beq.n 8000cd0 + { + /* GPIO and Clocks initialization */ + pObj->IO.Init(); + 8000cca: 687b ldr r3, [r7, #4] + 8000ccc: 689b ldr r3, [r3, #8] + 8000cce: 4798 blx r3 + } + + /* for later check */ + pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1; + 8000cd0: 687b ldr r3, [r7, #4] + 8000cd2: 2220 movs r2, #32 + 8000cd4: 601a str r2, [r3, #0] + + /* Get the device address from special mode register */ + for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) + 8000cd6: 2300 movs r3, #0 + 8000cd8: 617b str r3, [r7, #20] + 8000cda: e01c b.n 8000d16 + { + if(pObj->IO.ReadReg(addr, LAN8742_SMR, ®value) < 0) + 8000cdc: 687b ldr r3, [r7, #4] + 8000cde: 695b ldr r3, [r3, #20] + 8000ce0: f107 0208 add.w r2, r7, #8 + 8000ce4: 2112 movs r1, #18 + 8000ce6: 6978 ldr r0, [r7, #20] + 8000ce8: 4798 blx r3 + 8000cea: 4603 mov r3, r0 + 8000cec: 2b00 cmp r3, #0 + 8000cee: da03 bge.n 8000cf8 + { + status = LAN8742_STATUS_READ_ERROR; + 8000cf0: f06f 0304 mvn.w r3, #4 + 8000cf4: 613b str r3, [r7, #16] + /* Can't read from this device address + continue with next address */ + continue; + 8000cf6: e00b b.n 8000d10 + } + + if((regvalue & LAN8742_SMR_PHY_ADDR) == addr) + 8000cf8: 68bb ldr r3, [r7, #8] + 8000cfa: f003 031f and.w r3, r3, #31 + 8000cfe: 697a ldr r2, [r7, #20] + 8000d00: 429a cmp r2, r3 + 8000d02: d105 bne.n 8000d10 + { + pObj->DevAddr = addr; + 8000d04: 687b ldr r3, [r7, #4] + 8000d06: 697a ldr r2, [r7, #20] + 8000d08: 601a str r2, [r3, #0] + status = LAN8742_STATUS_OK; + 8000d0a: 2300 movs r3, #0 + 8000d0c: 613b str r3, [r7, #16] + break; + 8000d0e: e005 b.n 8000d1c + for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) + 8000d10: 697b ldr r3, [r7, #20] + 8000d12: 3301 adds r3, #1 + 8000d14: 617b str r3, [r7, #20] + 8000d16: 697b ldr r3, [r7, #20] + 8000d18: 2b1f cmp r3, #31 + 8000d1a: d9df bls.n 8000cdc + } + } + + if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR) + 8000d1c: 687b ldr r3, [r7, #4] + 8000d1e: 681b ldr r3, [r3, #0] + 8000d20: 2b1f cmp r3, #31 + 8000d22: d902 bls.n 8000d2a + { + status = LAN8742_STATUS_ADDRESS_ERROR; + 8000d24: f06f 0302 mvn.w r3, #2 + 8000d28: 613b str r3, [r7, #16] + } + + /* if device address is matched */ + if(status == LAN8742_STATUS_OK) + 8000d2a: 693b ldr r3, [r7, #16] + 8000d2c: 2b00 cmp r3, #0 + 8000d2e: d145 bne.n 8000dbc + { + /* set a software reset */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0) + 8000d30: 687b ldr r3, [r7, #4] + 8000d32: 691b ldr r3, [r3, #16] + 8000d34: 687a ldr r2, [r7, #4] + 8000d36: 6810 ldr r0, [r2, #0] + 8000d38: f44f 4200 mov.w r2, #32768 ; 0x8000 + 8000d3c: 2100 movs r1, #0 + 8000d3e: 4798 blx r3 + 8000d40: 4603 mov r3, r0 + 8000d42: 2b00 cmp r3, #0 + 8000d44: db37 blt.n 8000db6 + { + /* get software reset status */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) >= 0) + 8000d46: 687b ldr r3, [r7, #4] + 8000d48: 695b ldr r3, [r3, #20] + 8000d4a: 687a ldr r2, [r7, #4] + 8000d4c: 6810 ldr r0, [r2, #0] + 8000d4e: f107 0208 add.w r2, r7, #8 + 8000d52: 2100 movs r1, #0 + 8000d54: 4798 blx r3 + 8000d56: 4603 mov r3, r0 + 8000d58: 2b00 cmp r3, #0 + 8000d5a: db28 blt.n 8000dae + { + tickstart = pObj->IO.GetTick(); + 8000d5c: 687b ldr r3, [r7, #4] + 8000d5e: 699b ldr r3, [r3, #24] + 8000d60: 4798 blx r3 + 8000d62: 4603 mov r3, r0 + 8000d64: 60fb str r3, [r7, #12] + + /* wait until software reset is done or timeout occured */ + while(regvalue & LAN8742_BCR_SOFT_RESET) + 8000d66: e01c b.n 8000da2 + { + if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO) + 8000d68: 687b ldr r3, [r7, #4] + 8000d6a: 699b ldr r3, [r3, #24] + 8000d6c: 4798 blx r3 + 8000d6e: 4603 mov r3, r0 + 8000d70: 461a mov r2, r3 + 8000d72: 68fb ldr r3, [r7, #12] + 8000d74: 1ad3 subs r3, r2, r3 + 8000d76: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 + 8000d7a: d80e bhi.n 8000d9a + { + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) < 0) + 8000d7c: 687b ldr r3, [r7, #4] + 8000d7e: 695b ldr r3, [r3, #20] + 8000d80: 687a ldr r2, [r7, #4] + 8000d82: 6810 ldr r0, [r2, #0] + 8000d84: f107 0208 add.w r2, r7, #8 + 8000d88: 2100 movs r1, #0 + 8000d8a: 4798 blx r3 + 8000d8c: 4603 mov r3, r0 + 8000d8e: 2b00 cmp r3, #0 + 8000d90: da07 bge.n 8000da2 + { + status = LAN8742_STATUS_READ_ERROR; + 8000d92: f06f 0304 mvn.w r3, #4 + 8000d96: 613b str r3, [r7, #16] + break; + 8000d98: e010 b.n 8000dbc + } + } + else + { + status = LAN8742_STATUS_RESET_TIMEOUT; + 8000d9a: f06f 0301 mvn.w r3, #1 + 8000d9e: 613b str r3, [r7, #16] + break; + 8000da0: e00c b.n 8000dbc + while(regvalue & LAN8742_BCR_SOFT_RESET) + 8000da2: 68bb ldr r3, [r7, #8] + 8000da4: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8000da8: 2b00 cmp r3, #0 + 8000daa: d1dd bne.n 8000d68 + 8000dac: e006 b.n 8000dbc + } + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + 8000dae: f06f 0304 mvn.w r3, #4 + 8000db2: 613b str r3, [r7, #16] + 8000db4: e002 b.n 8000dbc + } + } + else + { + status = LAN8742_STATUS_WRITE_ERROR; + 8000db6: f06f 0303 mvn.w r3, #3 + 8000dba: 613b str r3, [r7, #16] + } + } + } + + if(status == LAN8742_STATUS_OK) + 8000dbc: 693b ldr r3, [r7, #16] + 8000dbe: 2b00 cmp r3, #0 + 8000dc0: d112 bne.n 8000de8 + { + tickstart = pObj->IO.GetTick(); + 8000dc2: 687b ldr r3, [r7, #4] + 8000dc4: 699b ldr r3, [r3, #24] + 8000dc6: 4798 blx r3 + 8000dc8: 4603 mov r3, r0 + 8000dca: 60fb str r3, [r7, #12] + + /* Wait for 2s to perform initialization */ + while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO) + 8000dcc: bf00 nop + 8000dce: 687b ldr r3, [r7, #4] + 8000dd0: 699b ldr r3, [r3, #24] + 8000dd2: 4798 blx r3 + 8000dd4: 4603 mov r3, r0 + 8000dd6: 461a mov r2, r3 + 8000dd8: 68fb ldr r3, [r7, #12] + 8000dda: 1ad3 subs r3, r2, r3 + 8000ddc: f5b3 6ffa cmp.w r3, #2000 ; 0x7d0 + 8000de0: d9f5 bls.n 8000dce + { + } + pObj->Is_Initialized = 1; + 8000de2: 687b ldr r3, [r7, #4] + 8000de4: 2201 movs r2, #1 + 8000de6: 605a str r2, [r3, #4] + } + + return status; + 8000de8: 693b ldr r3, [r7, #16] + } + 8000dea: 4618 mov r0, r3 + 8000dec: 3718 adds r7, #24 + 8000dee: 46bd mov sp, r7 + 8000df0: bd80 pop {r7, pc} + +08000df2 : + * LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj) +{ + 8000df2: b580 push {r7, lr} + 8000df4: b084 sub sp, #16 + 8000df6: af00 add r7, sp, #0 + 8000df8: 6078 str r0, [r7, #4] + uint32_t readval = 0; + 8000dfa: 2300 movs r3, #0 + 8000dfc: 60fb str r3, [r7, #12] + + /* Read Status register */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) + 8000dfe: 687b ldr r3, [r7, #4] + 8000e00: 695b ldr r3, [r3, #20] + 8000e02: 687a ldr r2, [r7, #4] + 8000e04: 6810 ldr r0, [r2, #0] + 8000e06: f107 020c add.w r2, r7, #12 + 8000e0a: 2101 movs r1, #1 + 8000e0c: 4798 blx r3 + 8000e0e: 4603 mov r3, r0 + 8000e10: 2b00 cmp r3, #0 + 8000e12: da02 bge.n 8000e1a + { + return LAN8742_STATUS_READ_ERROR; + 8000e14: f06f 0304 mvn.w r3, #4 + 8000e18: e06e b.n 8000ef8 + } + + /* Read Status register again */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) + 8000e1a: 687b ldr r3, [r7, #4] + 8000e1c: 695b ldr r3, [r3, #20] + 8000e1e: 687a ldr r2, [r7, #4] + 8000e20: 6810 ldr r0, [r2, #0] + 8000e22: f107 020c add.w r2, r7, #12 + 8000e26: 2101 movs r1, #1 + 8000e28: 4798 blx r3 + 8000e2a: 4603 mov r3, r0 + 8000e2c: 2b00 cmp r3, #0 + 8000e2e: da02 bge.n 8000e36 + { + return LAN8742_STATUS_READ_ERROR; + 8000e30: f06f 0304 mvn.w r3, #4 + 8000e34: e060 b.n 8000ef8 + } + + if((readval & LAN8742_BSR_LINK_STATUS) == 0) + 8000e36: 68fb ldr r3, [r7, #12] + 8000e38: f003 0304 and.w r3, r3, #4 + 8000e3c: 2b00 cmp r3, #0 + 8000e3e: d101 bne.n 8000e44 + { + /* Return Link Down status */ + return LAN8742_STATUS_LINK_DOWN; + 8000e40: 2301 movs r3, #1 + 8000e42: e059 b.n 8000ef8 + } + + /* Check Auto negotiaition */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0) + 8000e44: 687b ldr r3, [r7, #4] + 8000e46: 695b ldr r3, [r3, #20] + 8000e48: 687a ldr r2, [r7, #4] + 8000e4a: 6810 ldr r0, [r2, #0] + 8000e4c: f107 020c add.w r2, r7, #12 + 8000e50: 2100 movs r1, #0 + 8000e52: 4798 blx r3 + 8000e54: 4603 mov r3, r0 + 8000e56: 2b00 cmp r3, #0 + 8000e58: da02 bge.n 8000e60 + { + return LAN8742_STATUS_READ_ERROR; + 8000e5a: f06f 0304 mvn.w r3, #4 + 8000e5e: e04b b.n 8000ef8 + } + + if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN) + 8000e60: 68fb ldr r3, [r7, #12] + 8000e62: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8000e66: 2b00 cmp r3, #0 + 8000e68: d11b bne.n 8000ea2 + { + if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)) + 8000e6a: 68fb ldr r3, [r7, #12] + 8000e6c: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8000e70: 2b00 cmp r3, #0 + 8000e72: d006 beq.n 8000e82 + 8000e74: 68fb ldr r3, [r7, #12] + 8000e76: f403 7380 and.w r3, r3, #256 ; 0x100 + 8000e7a: 2b00 cmp r3, #0 + 8000e7c: d001 beq.n 8000e82 + { + return LAN8742_STATUS_100MBITS_FULLDUPLEX; + 8000e7e: 2302 movs r3, #2 + 8000e80: e03a b.n 8000ef8 + } + else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) + 8000e82: 68fb ldr r3, [r7, #12] + 8000e84: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8000e88: 2b00 cmp r3, #0 + 8000e8a: d001 beq.n 8000e90 + { + return LAN8742_STATUS_100MBITS_HALFDUPLEX; + 8000e8c: 2303 movs r3, #3 + 8000e8e: e033 b.n 8000ef8 + } + else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE) + 8000e90: 68fb ldr r3, [r7, #12] + 8000e92: f403 7380 and.w r3, r3, #256 ; 0x100 + 8000e96: 2b00 cmp r3, #0 + 8000e98: d001 beq.n 8000e9e + { + return LAN8742_STATUS_10MBITS_FULLDUPLEX; + 8000e9a: 2304 movs r3, #4 + 8000e9c: e02c b.n 8000ef8 + } + else + { + return LAN8742_STATUS_10MBITS_HALFDUPLEX; + 8000e9e: 2305 movs r3, #5 + 8000ea0: e02a b.n 8000ef8 + } + } + else /* Auto Nego enabled */ + { + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0) + 8000ea2: 687b ldr r3, [r7, #4] + 8000ea4: 695b ldr r3, [r3, #20] + 8000ea6: 687a ldr r2, [r7, #4] + 8000ea8: 6810 ldr r0, [r2, #0] + 8000eaa: f107 020c add.w r2, r7, #12 + 8000eae: 211f movs r1, #31 + 8000eb0: 4798 blx r3 + 8000eb2: 4603 mov r3, r0 + 8000eb4: 2b00 cmp r3, #0 + 8000eb6: da02 bge.n 8000ebe + { + return LAN8742_STATUS_READ_ERROR; + 8000eb8: f06f 0304 mvn.w r3, #4 + 8000ebc: e01c b.n 8000ef8 + } + + /* Check if auto nego not done */ + if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0) + 8000ebe: 68fb ldr r3, [r7, #12] + 8000ec0: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8000ec4: 2b00 cmp r3, #0 + 8000ec6: d101 bne.n 8000ecc + { + return LAN8742_STATUS_AUTONEGO_NOTDONE; + 8000ec8: 2306 movs r3, #6 + 8000eca: e015 b.n 8000ef8 + } + + if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD) + 8000ecc: 68fb ldr r3, [r7, #12] + 8000ece: f003 031c and.w r3, r3, #28 + 8000ed2: 2b18 cmp r3, #24 + 8000ed4: d101 bne.n 8000eda + { + return LAN8742_STATUS_100MBITS_FULLDUPLEX; + 8000ed6: 2302 movs r3, #2 + 8000ed8: e00e b.n 8000ef8 + } + else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD) + 8000eda: 68fb ldr r3, [r7, #12] + 8000edc: f003 031c and.w r3, r3, #28 + 8000ee0: 2b08 cmp r3, #8 + 8000ee2: d101 bne.n 8000ee8 + { + return LAN8742_STATUS_100MBITS_HALFDUPLEX; + 8000ee4: 2303 movs r3, #3 + 8000ee6: e007 b.n 8000ef8 + } + else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD) + 8000ee8: 68fb ldr r3, [r7, #12] + 8000eea: f003 031c and.w r3, r3, #28 + 8000eee: 2b14 cmp r3, #20 + 8000ef0: d101 bne.n 8000ef6 + { + return LAN8742_STATUS_10MBITS_FULLDUPLEX; + 8000ef2: 2304 movs r3, #4 + 8000ef4: e000 b.n 8000ef8 + } + else + { + return LAN8742_STATUS_10MBITS_HALFDUPLEX; + 8000ef6: 2305 movs r3, #5 + } + } +} + 8000ef8: 4618 mov r0, r3 + 8000efa: 3710 adds r7, #16 + 8000efc: 46bd mov sp, r7 + 8000efe: bd80 pop {r7, pc} + +08000f00 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8000f00: b580 push {r7, lr} + 8000f02: b082 sub sp, #8 + 8000f04: af00 add r7, sp, #0 + __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ + __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8000f06: 2003 movs r0, #3 + 8000f08: f000 f970 bl 80011ec + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); + 8000f0c: f002 fea8 bl 8003c60 + 8000f10: 4602 mov r2, r0 + 8000f12: 4b15 ldr r3, [pc, #84] ; (8000f68 ) + 8000f14: 699b ldr r3, [r3, #24] + 8000f16: 0a1b lsrs r3, r3, #8 + 8000f18: f003 030f and.w r3, r3, #15 + 8000f1c: 4913 ldr r1, [pc, #76] ; (8000f6c ) + 8000f1e: 5ccb ldrb r3, [r1, r3] + 8000f20: f003 031f and.w r3, r3, #31 + 8000f24: fa22 f303 lsr.w r3, r2, r3 + 8000f28: 607b str r3, [r7, #4] + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + 8000f2a: 4b0f ldr r3, [pc, #60] ; (8000f68 ) + 8000f2c: 699b ldr r3, [r3, #24] + 8000f2e: f003 030f and.w r3, r3, #15 + 8000f32: 4a0e ldr r2, [pc, #56] ; (8000f6c ) + 8000f34: 5cd3 ldrb r3, [r2, r3] + 8000f36: f003 031f and.w r3, r3, #31 + 8000f3a: 687a ldr r2, [r7, #4] + 8000f3c: fa22 f303 lsr.w r3, r2, r3 + 8000f40: 4a0b ldr r2, [pc, #44] ; (8000f70 ) + 8000f42: 6013 str r3, [r2, #0] +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; + 8000f44: 4a0b ldr r2, [pc, #44] ; (8000f74 ) + 8000f46: 687b ldr r3, [r7, #4] + 8000f48: 6013 str r3, [r2, #0] +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000f4a: 200f movs r0, #15 + 8000f4c: f000 f814 bl 8000f78 + 8000f50: 4603 mov r3, r0 + 8000f52: 2b00 cmp r3, #0 + 8000f54: d001 beq.n 8000f5a + { + return HAL_ERROR; + 8000f56: 2301 movs r3, #1 + 8000f58: e002 b.n 8000f60 + } + + /* Init the low level hardware */ + HAL_MspInit(); + 8000f5a: f7ff fcc3 bl 80008e4 + + /* Return function status */ + return HAL_OK; + 8000f5e: 2300 movs r3, #0 +} + 8000f60: 4618 mov r0, r3 + 8000f62: 3708 adds r7, #8 + 8000f64: 46bd mov sp, r7 + 8000f66: bd80 pop {r7, pc} + 8000f68: 58024400 .word 0x58024400 + 8000f6c: 08014c80 .word 0x08014c80 + 8000f70: 24000004 .word 0x24000004 + 8000f74: 24000000 .word 0x24000000 + +08000f78 : + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8000f78: b580 push {r7, lr} + 8000f7a: b082 sub sp, #8 + 8000f7c: af00 add r7, sp, #0 + 8000f7e: 6078 str r0, [r7, #4] + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if((uint32_t)uwTickFreq == 0UL) + 8000f80: 4b15 ldr r3, [pc, #84] ; (8000fd8 ) + 8000f82: 781b ldrb r3, [r3, #0] + 8000f84: 2b00 cmp r3, #0 + 8000f86: d101 bne.n 8000f8c + { + return HAL_ERROR; + 8000f88: 2301 movs r3, #1 + 8000f8a: e021 b.n 8000fd0 + } + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + 8000f8c: 4b13 ldr r3, [pc, #76] ; (8000fdc ) + 8000f8e: 681a ldr r2, [r3, #0] + 8000f90: 4b11 ldr r3, [pc, #68] ; (8000fd8 ) + 8000f92: 781b ldrb r3, [r3, #0] + 8000f94: 4619 mov r1, r3 + 8000f96: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8000f9a: fbb3 f3f1 udiv r3, r3, r1 + 8000f9e: fbb2 f3f3 udiv r3, r2, r3 + 8000fa2: 4618 mov r0, r3 + 8000fa4: f000 f955 bl 8001252 + 8000fa8: 4603 mov r3, r0 + 8000faa: 2b00 cmp r3, #0 + 8000fac: d001 beq.n 8000fb2 + { + return HAL_ERROR; + 8000fae: 2301 movs r3, #1 + 8000fb0: e00e b.n 8000fd0 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000fb2: 687b ldr r3, [r7, #4] + 8000fb4: 2b0f cmp r3, #15 + 8000fb6: d80a bhi.n 8000fce + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000fb8: 2200 movs r2, #0 + 8000fba: 6879 ldr r1, [r7, #4] + 8000fbc: f04f 30ff mov.w r0, #4294967295 + 8000fc0: f000 f91f bl 8001202 + uwTickPrio = TickPriority; + 8000fc4: 4a06 ldr r2, [pc, #24] ; (8000fe0 ) + 8000fc6: 687b ldr r3, [r7, #4] + 8000fc8: 6013 str r3, [r2, #0] + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; + 8000fca: 2300 movs r3, #0 + 8000fcc: e000 b.n 8000fd0 + return HAL_ERROR; + 8000fce: 2301 movs r3, #1 +} + 8000fd0: 4618 mov r0, r3 + 8000fd2: 3708 adds r7, #8 + 8000fd4: 46bd mov sp, r7 + 8000fd6: bd80 pop {r7, pc} + 8000fd8: 2400000c .word 0x2400000c + 8000fdc: 24000000 .word 0x24000000 + 8000fe0: 24000008 .word 0x24000008 + +08000fe4 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8000fe4: b480 push {r7} + 8000fe6: af00 add r7, sp, #0 + uwTick += (uint32_t)uwTickFreq; + 8000fe8: 4b06 ldr r3, [pc, #24] ; (8001004 ) + 8000fea: 781b ldrb r3, [r3, #0] + 8000fec: 461a mov r2, r3 + 8000fee: 4b06 ldr r3, [pc, #24] ; (8001008 ) + 8000ff0: 681b ldr r3, [r3, #0] + 8000ff2: 4413 add r3, r2 + 8000ff4: 4a04 ldr r2, [pc, #16] ; (8001008 ) + 8000ff6: 6013 str r3, [r2, #0] +} + 8000ff8: bf00 nop + 8000ffa: 46bd mov sp, r7 + 8000ffc: f85d 7b04 ldr.w r7, [sp], #4 + 8001000: 4770 bx lr + 8001002: bf00 nop + 8001004: 2400000c .word 0x2400000c + 8001008: 24000128 .word 0x24000128 + +0800100c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + 800100c: b480 push {r7} + 800100e: af00 add r7, sp, #0 + return uwTick; + 8001010: 4b03 ldr r3, [pc, #12] ; (8001020 ) + 8001012: 681b ldr r3, [r3, #0] +} + 8001014: 4618 mov r0, r3 + 8001016: 46bd mov sp, r7 + 8001018: f85d 7b04 ldr.w r7, [sp], #4 + 800101c: 4770 bx lr + 800101e: bf00 nop + 8001020: 24000128 .word 0x24000128 + +08001024 : + * @arg SYSCFG_ETH_MII : Select the Media Independent Interface + * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface + * @retval None + */ +void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface) +{ + 8001024: b480 push {r7} + 8001026: b083 sub sp, #12 + 8001028: af00 add r7, sp, #0 + 800102a: 6078 str r0, [r7, #4] + /* Check the parameter */ + assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface)); + + MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); + 800102c: 4b06 ldr r3, [pc, #24] ; (8001048 ) + 800102e: 685b ldr r3, [r3, #4] + 8001030: f423 0260 bic.w r2, r3, #14680064 ; 0xe00000 + 8001034: 4904 ldr r1, [pc, #16] ; (8001048 ) + 8001036: 687b ldr r3, [r7, #4] + 8001038: 4313 orrs r3, r2 + 800103a: 604b str r3, [r1, #4] +} + 800103c: bf00 nop + 800103e: 370c adds r7, #12 + 8001040: 46bd mov sp, r7 + 8001042: f85d 7b04 ldr.w r7, [sp], #4 + 8001046: 4770 bx lr + 8001048: 58000400 .word 0x58000400 + +0800104c <__NVIC_SetPriorityGrouping>: +{ + 800104c: b480 push {r7} + 800104e: b085 sub sp, #20 + 8001050: af00 add r7, sp, #0 + 8001052: 6078 str r0, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8001054: 687b ldr r3, [r7, #4] + 8001056: f003 0307 and.w r3, r3, #7 + 800105a: 60fb str r3, [r7, #12] + reg_value = SCB->AIRCR; /* read old register configuration */ + 800105c: 4b0b ldr r3, [pc, #44] ; (800108c <__NVIC_SetPriorityGrouping+0x40>) + 800105e: 68db ldr r3, [r3, #12] + 8001060: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8001062: 68ba ldr r2, [r7, #8] + 8001064: f64f 03ff movw r3, #63743 ; 0xf8ff + 8001068: 4013 ands r3, r2 + 800106a: 60bb str r3, [r7, #8] + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 800106c: 68fb ldr r3, [r7, #12] + 800106e: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8001070: 68bb ldr r3, [r7, #8] + 8001072: 431a orrs r2, r3 + reg_value = (reg_value | + 8001074: 4b06 ldr r3, [pc, #24] ; (8001090 <__NVIC_SetPriorityGrouping+0x44>) + 8001076: 4313 orrs r3, r2 + 8001078: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 800107a: 4a04 ldr r2, [pc, #16] ; (800108c <__NVIC_SetPriorityGrouping+0x40>) + 800107c: 68bb ldr r3, [r7, #8] + 800107e: 60d3 str r3, [r2, #12] +} + 8001080: bf00 nop + 8001082: 3714 adds r7, #20 + 8001084: 46bd mov sp, r7 + 8001086: f85d 7b04 ldr.w r7, [sp], #4 + 800108a: 4770 bx lr + 800108c: e000ed00 .word 0xe000ed00 + 8001090: 05fa0000 .word 0x05fa0000 + +08001094 <__NVIC_GetPriorityGrouping>: +{ + 8001094: b480 push {r7} + 8001096: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8001098: 4b04 ldr r3, [pc, #16] ; (80010ac <__NVIC_GetPriorityGrouping+0x18>) + 800109a: 68db ldr r3, [r3, #12] + 800109c: 0a1b lsrs r3, r3, #8 + 800109e: f003 0307 and.w r3, r3, #7 +} + 80010a2: 4618 mov r0, r3 + 80010a4: 46bd mov sp, r7 + 80010a6: f85d 7b04 ldr.w r7, [sp], #4 + 80010aa: 4770 bx lr + 80010ac: e000ed00 .word 0xe000ed00 + +080010b0 <__NVIC_EnableIRQ>: +{ + 80010b0: b480 push {r7} + 80010b2: b083 sub sp, #12 + 80010b4: af00 add r7, sp, #0 + 80010b6: 4603 mov r3, r0 + 80010b8: 80fb strh r3, [r7, #6] + if ((int32_t)(IRQn) >= 0) + 80010ba: f9b7 3006 ldrsh.w r3, [r7, #6] + 80010be: 2b00 cmp r3, #0 + 80010c0: db0b blt.n 80010da <__NVIC_EnableIRQ+0x2a> + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80010c2: 88fb ldrh r3, [r7, #6] + 80010c4: f003 021f and.w r2, r3, #31 + 80010c8: 4907 ldr r1, [pc, #28] ; (80010e8 <__NVIC_EnableIRQ+0x38>) + 80010ca: f9b7 3006 ldrsh.w r3, [r7, #6] + 80010ce: 095b lsrs r3, r3, #5 + 80010d0: 2001 movs r0, #1 + 80010d2: fa00 f202 lsl.w r2, r0, r2 + 80010d6: f841 2023 str.w r2, [r1, r3, lsl #2] +} + 80010da: bf00 nop + 80010dc: 370c adds r7, #12 + 80010de: 46bd mov sp, r7 + 80010e0: f85d 7b04 ldr.w r7, [sp], #4 + 80010e4: 4770 bx lr + 80010e6: bf00 nop + 80010e8: e000e100 .word 0xe000e100 + +080010ec <__NVIC_SetPriority>: +{ + 80010ec: b480 push {r7} + 80010ee: b083 sub sp, #12 + 80010f0: af00 add r7, sp, #0 + 80010f2: 4603 mov r3, r0 + 80010f4: 6039 str r1, [r7, #0] + 80010f6: 80fb strh r3, [r7, #6] + if ((int32_t)(IRQn) >= 0) + 80010f8: f9b7 3006 ldrsh.w r3, [r7, #6] + 80010fc: 2b00 cmp r3, #0 + 80010fe: db0a blt.n 8001116 <__NVIC_SetPriority+0x2a> + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001100: 683b ldr r3, [r7, #0] + 8001102: b2da uxtb r2, r3 + 8001104: 490c ldr r1, [pc, #48] ; (8001138 <__NVIC_SetPriority+0x4c>) + 8001106: f9b7 3006 ldrsh.w r3, [r7, #6] + 800110a: 0112 lsls r2, r2, #4 + 800110c: b2d2 uxtb r2, r2 + 800110e: 440b add r3, r1 + 8001110: f883 2300 strb.w r2, [r3, #768] ; 0x300 +} + 8001114: e00a b.n 800112c <__NVIC_SetPriority+0x40> + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8001116: 683b ldr r3, [r7, #0] + 8001118: b2da uxtb r2, r3 + 800111a: 4908 ldr r1, [pc, #32] ; (800113c <__NVIC_SetPriority+0x50>) + 800111c: 88fb ldrh r3, [r7, #6] + 800111e: f003 030f and.w r3, r3, #15 + 8001122: 3b04 subs r3, #4 + 8001124: 0112 lsls r2, r2, #4 + 8001126: b2d2 uxtb r2, r2 + 8001128: 440b add r3, r1 + 800112a: 761a strb r2, [r3, #24] +} + 800112c: bf00 nop + 800112e: 370c adds r7, #12 + 8001130: 46bd mov sp, r7 + 8001132: f85d 7b04 ldr.w r7, [sp], #4 + 8001136: 4770 bx lr + 8001138: e000e100 .word 0xe000e100 + 800113c: e000ed00 .word 0xe000ed00 + +08001140 : +{ + 8001140: b480 push {r7} + 8001142: b089 sub sp, #36 ; 0x24 + 8001144: af00 add r7, sp, #0 + 8001146: 60f8 str r0, [r7, #12] + 8001148: 60b9 str r1, [r7, #8] + 800114a: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 800114c: 68fb ldr r3, [r7, #12] + 800114e: f003 0307 and.w r3, r3, #7 + 8001152: 61fb str r3, [r7, #28] + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8001154: 69fb ldr r3, [r7, #28] + 8001156: f1c3 0307 rsb r3, r3, #7 + 800115a: 2b04 cmp r3, #4 + 800115c: bf28 it cs + 800115e: 2304 movcs r3, #4 + 8001160: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8001162: 69fb ldr r3, [r7, #28] + 8001164: 3304 adds r3, #4 + 8001166: 2b06 cmp r3, #6 + 8001168: d902 bls.n 8001170 + 800116a: 69fb ldr r3, [r7, #28] + 800116c: 3b03 subs r3, #3 + 800116e: e000 b.n 8001172 + 8001170: 2300 movs r3, #0 + 8001172: 617b str r3, [r7, #20] + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001174: f04f 32ff mov.w r2, #4294967295 + 8001178: 69bb ldr r3, [r7, #24] + 800117a: fa02 f303 lsl.w r3, r2, r3 + 800117e: 43da mvns r2, r3 + 8001180: 68bb ldr r3, [r7, #8] + 8001182: 401a ands r2, r3 + 8001184: 697b ldr r3, [r7, #20] + 8001186: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 8001188: f04f 31ff mov.w r1, #4294967295 + 800118c: 697b ldr r3, [r7, #20] + 800118e: fa01 f303 lsl.w r3, r1, r3 + 8001192: 43d9 mvns r1, r3 + 8001194: 687b ldr r3, [r7, #4] + 8001196: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8001198: 4313 orrs r3, r2 +} + 800119a: 4618 mov r0, r3 + 800119c: 3724 adds r7, #36 ; 0x24 + 800119e: 46bd mov sp, r7 + 80011a0: f85d 7b04 ldr.w r7, [sp], #4 + 80011a4: 4770 bx lr + ... + +080011a8 : +{ + 80011a8: b580 push {r7, lr} + 80011aa: b082 sub sp, #8 + 80011ac: af00 add r7, sp, #0 + 80011ae: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 80011b0: 687b ldr r3, [r7, #4] + 80011b2: 3b01 subs r3, #1 + 80011b4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 80011b8: d301 bcc.n 80011be + return (1UL); /* Reload value impossible */ + 80011ba: 2301 movs r3, #1 + 80011bc: e00f b.n 80011de + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 80011be: 4a0a ldr r2, [pc, #40] ; (80011e8 ) + 80011c0: 687b ldr r3, [r7, #4] + 80011c2: 3b01 subs r3, #1 + 80011c4: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 80011c6: 210f movs r1, #15 + 80011c8: f04f 30ff mov.w r0, #4294967295 + 80011cc: f7ff ff8e bl 80010ec <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 80011d0: 4b05 ldr r3, [pc, #20] ; (80011e8 ) + 80011d2: 2200 movs r2, #0 + 80011d4: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 80011d6: 4b04 ldr r3, [pc, #16] ; (80011e8 ) + 80011d8: 2207 movs r2, #7 + 80011da: 601a str r2, [r3, #0] + return (0UL); /* Function successful */ + 80011dc: 2300 movs r3, #0 +} + 80011de: 4618 mov r0, r3 + 80011e0: 3708 adds r7, #8 + 80011e2: 46bd mov sp, r7 + 80011e4: bd80 pop {r7, pc} + 80011e6: bf00 nop + 80011e8: e000e010 .word 0xe000e010 + +080011ec : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80011ec: b580 push {r7, lr} + 80011ee: b082 sub sp, #8 + 80011f0: af00 add r7, sp, #0 + 80011f2: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 80011f4: 6878 ldr r0, [r7, #4] + 80011f6: f7ff ff29 bl 800104c <__NVIC_SetPriorityGrouping> +} + 80011fa: bf00 nop + 80011fc: 3708 adds r7, #8 + 80011fe: 46bd mov sp, r7 + 8001200: bd80 pop {r7, pc} + +08001202 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8001202: b580 push {r7, lr} + 8001204: b086 sub sp, #24 + 8001206: af00 add r7, sp, #0 + 8001208: 4603 mov r3, r0 + 800120a: 60b9 str r1, [r7, #8] + 800120c: 607a str r2, [r7, #4] + 800120e: 81fb strh r3, [r7, #14] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8001210: f7ff ff40 bl 8001094 <__NVIC_GetPriorityGrouping> + 8001214: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8001216: 687a ldr r2, [r7, #4] + 8001218: 68b9 ldr r1, [r7, #8] + 800121a: 6978 ldr r0, [r7, #20] + 800121c: f7ff ff90 bl 8001140 + 8001220: 4602 mov r2, r0 + 8001222: f9b7 300e ldrsh.w r3, [r7, #14] + 8001226: 4611 mov r1, r2 + 8001228: 4618 mov r0, r3 + 800122a: f7ff ff5f bl 80010ec <__NVIC_SetPriority> +} + 800122e: bf00 nop + 8001230: 3718 adds r7, #24 + 8001232: 46bd mov sp, r7 + 8001234: bd80 pop {r7, pc} + +08001236 : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8001236: b580 push {r7, lr} + 8001238: b082 sub sp, #8 + 800123a: af00 add r7, sp, #0 + 800123c: 4603 mov r3, r0 + 800123e: 80fb strh r3, [r7, #6] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8001240: f9b7 3006 ldrsh.w r3, [r7, #6] + 8001244: 4618 mov r0, r3 + 8001246: f7ff ff33 bl 80010b0 <__NVIC_EnableIRQ> +} + 800124a: bf00 nop + 800124c: 3708 adds r7, #8 + 800124e: 46bd mov sp, r7 + 8001250: bd80 pop {r7, pc} + +08001252 : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 8001252: b580 push {r7, lr} + 8001254: b082 sub sp, #8 + 8001256: af00 add r7, sp, #0 + 8001258: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 800125a: 6878 ldr r0, [r7, #4] + 800125c: f7ff ffa4 bl 80011a8 + 8001260: 4603 mov r3, r0 +} + 8001262: 4618 mov r0, r3 + 8001264: 3708 adds r7, #8 + 8001266: 46bd mov sp, r7 + 8001268: bd80 pop {r7, pc} + ... + +0800126c : +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + 800126c: b480 push {r7} + 800126e: af00 add r7, sp, #0 + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); + 8001270: f3bf 8f5f dmb sy +} + 8001274: bf00 nop + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + 8001276: 4b07 ldr r3, [pc, #28] ; (8001294 ) + 8001278: 6a5b ldr r3, [r3, #36] ; 0x24 + 800127a: 4a06 ldr r2, [pc, #24] ; (8001294 ) + 800127c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8001280: 6253 str r3, [r2, #36] ; 0x24 + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; + 8001282: 4b05 ldr r3, [pc, #20] ; (8001298 ) + 8001284: 2200 movs r2, #0 + 8001286: 605a str r2, [r3, #4] +} + 8001288: bf00 nop + 800128a: 46bd mov sp, r7 + 800128c: f85d 7b04 ldr.w r7, [sp], #4 + 8001290: 4770 bx lr + 8001292: bf00 nop + 8001294: e000ed00 .word 0xe000ed00 + 8001298: e000ed90 .word 0xe000ed90 + +0800129c : + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + 800129c: b480 push {r7} + 800129e: b083 sub sp, #12 + 80012a0: af00 add r7, sp, #0 + 80012a2: 6078 str r0, [r7, #4] + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + 80012a4: 4a0b ldr r2, [pc, #44] ; (80012d4 ) + 80012a6: 687b ldr r3, [r7, #4] + 80012a8: f043 0301 orr.w r3, r3, #1 + 80012ac: 6053 str r3, [r2, #4] + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + 80012ae: 4b0a ldr r3, [pc, #40] ; (80012d8 ) + 80012b0: 6a5b ldr r3, [r3, #36] ; 0x24 + 80012b2: 4a09 ldr r2, [pc, #36] ; (80012d8 ) + 80012b4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80012b8: 6253 str r3, [r2, #36] ; 0x24 + __ASM volatile ("dsb 0xF":::"memory"); + 80012ba: f3bf 8f4f dsb sy +} + 80012be: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 80012c0: f3bf 8f6f isb sy +} + 80012c4: bf00 nop + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + 80012c6: bf00 nop + 80012c8: 370c adds r7, #12 + 80012ca: 46bd mov sp, r7 + 80012cc: f85d 7b04 ldr.w r7, [sp], #4 + 80012d0: 4770 bx lr + 80012d2: bf00 nop + 80012d4: e000ed90 .word 0xe000ed90 + 80012d8: e000ed00 .word 0xe000ed00 + +080012dc : + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + 80012dc: b480 push {r7} + 80012de: b083 sub sp, #12 + 80012e0: af00 add r7, sp, #0 + 80012e2: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + 80012e4: 687b ldr r3, [r7, #4] + 80012e6: 785a ldrb r2, [r3, #1] + 80012e8: 4b1d ldr r3, [pc, #116] ; (8001360 ) + 80012ea: 609a str r2, [r3, #8] + + if ((MPU_Init->Enable) != 0UL) + 80012ec: 687b ldr r3, [r7, #4] + 80012ee: 781b ldrb r3, [r3, #0] + 80012f0: 2b00 cmp r3, #0 + 80012f2: d029 beq.n 8001348 + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + 80012f4: 4a1a ldr r2, [pc, #104] ; (8001360 ) + 80012f6: 687b ldr r3, [r7, #4] + 80012f8: 685b ldr r3, [r3, #4] + 80012fa: 60d3 str r3, [r2, #12] + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 80012fc: 687b ldr r3, [r7, #4] + 80012fe: 7b1b ldrb r3, [r3, #12] + 8001300: 071a lsls r2, r3, #28 + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 8001302: 687b ldr r3, [r7, #4] + 8001304: 7adb ldrb r3, [r3, #11] + 8001306: 061b lsls r3, r3, #24 + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 8001308: 431a orrs r2, r3 + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 800130a: 687b ldr r3, [r7, #4] + 800130c: 7a9b ldrb r3, [r3, #10] + 800130e: 04db lsls r3, r3, #19 + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 8001310: 431a orrs r2, r3 + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 8001312: 687b ldr r3, [r7, #4] + 8001314: 7b5b ldrb r3, [r3, #13] + 8001316: 049b lsls r3, r3, #18 + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 8001318: 431a orrs r2, r3 + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 800131a: 687b ldr r3, [r7, #4] + 800131c: 7b9b ldrb r3, [r3, #14] + 800131e: 045b lsls r3, r3, #17 + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 8001320: 431a orrs r2, r3 + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 8001322: 687b ldr r3, [r7, #4] + 8001324: 7bdb ldrb r3, [r3, #15] + 8001326: 041b lsls r3, r3, #16 + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 8001328: 431a orrs r2, r3 + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 800132a: 687b ldr r3, [r7, #4] + 800132c: 7a5b ldrb r3, [r3, #9] + 800132e: 021b lsls r3, r3, #8 + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 8001330: 431a orrs r2, r3 + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 8001332: 687b ldr r3, [r7, #4] + 8001334: 7a1b ldrb r3, [r3, #8] + 8001336: 005b lsls r3, r3, #1 + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 8001338: 4313 orrs r3, r2 + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 800133a: 687a ldr r2, [r7, #4] + 800133c: 7812 ldrb r2, [r2, #0] + 800133e: 4611 mov r1, r2 + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 8001340: 4a07 ldr r2, [pc, #28] ; (8001360 ) + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 8001342: 430b orrs r3, r1 + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 8001344: 6113 str r3, [r2, #16] + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} + 8001346: e005 b.n 8001354 + MPU->RBAR = 0x00; + 8001348: 4b05 ldr r3, [pc, #20] ; (8001360 ) + 800134a: 2200 movs r2, #0 + 800134c: 60da str r2, [r3, #12] + MPU->RASR = 0x00; + 800134e: 4b04 ldr r3, [pc, #16] ; (8001360 ) + 8001350: 2200 movs r2, #0 + 8001352: 611a str r2, [r3, #16] +} + 8001354: bf00 nop + 8001356: 370c adds r7, #12 + 8001358: 46bd mov sp, r7 + 800135a: f85d 7b04 ldr.w r7, [sp], #4 + 800135e: 4770 bx lr + 8001360: e000ed90 .word 0xe000ed90 + +08001364 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + 8001364: b580 push {r7, lr} + 8001366: b084 sub sp, #16 + 8001368: af00 add r7, sp, #0 + 800136a: 6078 str r0, [r7, #4] + uint32_t tickstart; + + if (heth == NULL) + 800136c: 687b ldr r3, [r7, #4] + 800136e: 2b00 cmp r3, #0 + 8001370: d101 bne.n 8001376 + { + return HAL_ERROR; + 8001372: 2301 movs r3, #1 + 8001374: e0cf b.n 8001516 + } + if (heth->gState == HAL_ETH_STATE_RESET) + 8001376: 687b ldr r3, [r7, #4] + 8001378: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800137c: 2b00 cmp r3, #0 + 800137e: d106 bne.n 800138e + { + heth->gState = HAL_ETH_STATE_BUSY; + 8001380: 687b ldr r3, [r7, #4] + 8001382: 2223 movs r2, #35 ; 0x23 + 8001384: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* Init the low level hardware */ + heth->MspInitCallback(heth); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit(heth); + 8001388: 6878 ldr r0, [r7, #4] + 800138a: f003 fe99 bl 80050c0 + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + } + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 800138e: 4b64 ldr r3, [pc, #400] ; (8001520 ) + 8001390: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 + 8001394: 4a62 ldr r2, [pc, #392] ; (8001520 ) + 8001396: f043 0302 orr.w r3, r3, #2 + 800139a: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 + 800139e: 4b60 ldr r3, [pc, #384] ; (8001520 ) + 80013a0: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 + 80013a4: f003 0302 and.w r3, r3, #2 + 80013a8: 60bb str r3, [r7, #8] + 80013aa: 68bb ldr r3, [r7, #8] + + if (heth->Init.MediaInterface == HAL_ETH_MII_MODE) + 80013ac: 687b ldr r3, [r7, #4] + 80013ae: 7a1b ldrb r3, [r3, #8] + 80013b0: 2b00 cmp r3, #0 + 80013b2: d103 bne.n 80013bc + { + HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII); + 80013b4: 2000 movs r0, #0 + 80013b6: f7ff fe35 bl 8001024 + 80013ba: e003 b.n 80013c4 + } + else + { + HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII); + 80013bc: f44f 0000 mov.w r0, #8388608 ; 0x800000 + 80013c0: f7ff fe30 bl 8001024 + } + + /* Dummy read to sync with ETH */ + (void)SYSCFG->PMCR; + 80013c4: 4b57 ldr r3, [pc, #348] ; (8001524 ) + 80013c6: 685b ldr r3, [r3, #4] + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR); + 80013c8: 687b ldr r3, [r7, #4] + 80013ca: 681b ldr r3, [r3, #0] + 80013cc: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80013d0: 681b ldr r3, [r3, #0] + 80013d2: 687a ldr r2, [r7, #4] + 80013d4: 6812 ldr r2, [r2, #0] + 80013d6: f043 0301 orr.w r3, r3, #1 + 80013da: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80013de: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 80013e0: f7ff fe14 bl 800100c + 80013e4: 60f8 str r0, [r7, #12] + + /* Wait for software reset */ + while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U) + 80013e6: e011 b.n 800140c + { + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) + 80013e8: f7ff fe10 bl 800100c + 80013ec: 4602 mov r2, r0 + 80013ee: 68fb ldr r3, [r7, #12] + 80013f0: 1ad3 subs r3, r2, r3 + 80013f2: f5b3 7ffa cmp.w r3, #500 ; 0x1f4 + 80013f6: d909 bls.n 800140c + { + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; + 80013f8: 687b ldr r3, [r7, #4] + 80013fa: 2204 movs r2, #4 + 80013fc: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + 8001400: 687b ldr r3, [r7, #4] + 8001402: 22e0 movs r2, #224 ; 0xe0 + 8001404: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + /* Return Error */ + return HAL_ERROR; + 8001408: 2301 movs r3, #1 + 800140a: e084 b.n 8001516 + while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U) + 800140c: 687b ldr r3, [r7, #4] + 800140e: 681b ldr r3, [r3, #0] + 8001410: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001414: 681b ldr r3, [r3, #0] + 8001416: f003 0301 and.w r3, r3, #1 + 800141a: 2b00 cmp r3, #0 + 800141c: d1e4 bne.n 80013e8 + } + } + + /*------------------ MDIO CSR Clock Range Configuration --------------------*/ + HAL_ETH_SetMDIOClockRange(heth); + 800141e: 6878 ldr r0, [r7, #4] + 8001420: f000 fee0 bl 80021e4 + + /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/ + WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U)); + 8001424: f002 fd96 bl 8003f54 + 8001428: 4603 mov r3, r0 + 800142a: 4a3f ldr r2, [pc, #252] ; (8001528 ) + 800142c: fba2 2303 umull r2, r3, r2, r3 + 8001430: 0c9a lsrs r2, r3, #18 + 8001432: 687b ldr r3, [r7, #4] + 8001434: 681b ldr r3, [r3, #0] + 8001436: 3a01 subs r2, #1 + 8001438: f8c3 20dc str.w r2, [r3, #220] ; 0xdc + + /*------------------ MAC, MTL and DMA default Configuration ----------------*/ + ETH_MACDMAConfig(heth); + 800143c: 6878 ldr r0, [r7, #4] + 800143e: f001 f8cb bl 80025d8 + + /* SET DSL to 64 bit */ + MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT); + 8001442: 687b ldr r3, [r7, #4] + 8001444: 681b ldr r3, [r3, #0] + 8001446: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800144a: f8d3 3100 ldr.w r3, [r3, #256] ; 0x100 + 800144e: f423 13e0 bic.w r3, r3, #1835008 ; 0x1c0000 + 8001452: 687a ldr r2, [r7, #4] + 8001454: 6812 ldr r2, [r2, #0] + 8001456: f443 2300 orr.w r3, r3, #524288 ; 0x80000 + 800145a: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 800145e: f8c2 3100 str.w r3, [r2, #256] ; 0x100 + + /* Set Receive Buffers Length (must be a multiple of 4) */ + if ((heth->Init.RxBuffLen % 0x4U) != 0x0U) + 8001462: 687b ldr r3, [r7, #4] + 8001464: 695b ldr r3, [r3, #20] + 8001466: f003 0303 and.w r3, r3, #3 + 800146a: 2b00 cmp r3, #0 + 800146c: d009 beq.n 8001482 + { + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_PARAM; + 800146e: 687b ldr r3, [r7, #4] + 8001470: 2201 movs r2, #1 + 8001472: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + 8001476: 687b ldr r3, [r7, #4] + 8001478: 22e0 movs r2, #224 ; 0xe0 + 800147a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + /* Return Error */ + return HAL_ERROR; + 800147e: 2301 movs r3, #1 + 8001480: e049 b.n 8001516 + } + else + { + MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1)); + 8001482: 687b ldr r3, [r7, #4] + 8001484: 681b ldr r3, [r3, #0] + 8001486: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800148a: f8d3 2108 ldr.w r2, [r3, #264] ; 0x108 + 800148e: 4b27 ldr r3, [pc, #156] ; (800152c ) + 8001490: 4013 ands r3, r2 + 8001492: 687a ldr r2, [r7, #4] + 8001494: 6952 ldr r2, [r2, #20] + 8001496: 0051 lsls r1, r2, #1 + 8001498: 687a ldr r2, [r7, #4] + 800149a: 6812 ldr r2, [r2, #0] + 800149c: 430b orrs r3, r1 + 800149e: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80014a2: f8c2 3108 str.w r3, [r2, #264] ; 0x108 + } + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + ETH_DMATxDescListInit(heth); + 80014a6: 6878 ldr r0, [r7, #4] + 80014a8: f001 f933 bl 8002712 + + /*------------------ DMA Rx Descriptors Configuration ----------------------*/ + ETH_DMARxDescListInit(heth); + 80014ac: 6878 ldr r0, [r7, #4] + 80014ae: f001 f979 bl 80027a4 + + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + /* Set MAC addr bits 32 to 47 */ + heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]); + 80014b2: 687b ldr r3, [r7, #4] + 80014b4: 685b ldr r3, [r3, #4] + 80014b6: 3305 adds r3, #5 + 80014b8: 781b ldrb r3, [r3, #0] + 80014ba: 021a lsls r2, r3, #8 + 80014bc: 687b ldr r3, [r7, #4] + 80014be: 685b ldr r3, [r3, #4] + 80014c0: 3304 adds r3, #4 + 80014c2: 781b ldrb r3, [r3, #0] + 80014c4: 4619 mov r1, r3 + 80014c6: 687b ldr r3, [r7, #4] + 80014c8: 681b ldr r3, [r3, #0] + 80014ca: 430a orrs r2, r1 + 80014cc: f8c3 2300 str.w r2, [r3, #768] ; 0x300 + /* Set MAC addr bits 0 to 31 */ + heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | + 80014d0: 687b ldr r3, [r7, #4] + 80014d2: 685b ldr r3, [r3, #4] + 80014d4: 3303 adds r3, #3 + 80014d6: 781b ldrb r3, [r3, #0] + 80014d8: 061a lsls r2, r3, #24 + 80014da: 687b ldr r3, [r7, #4] + 80014dc: 685b ldr r3, [r3, #4] + 80014de: 3302 adds r3, #2 + 80014e0: 781b ldrb r3, [r3, #0] + 80014e2: 041b lsls r3, r3, #16 + 80014e4: 431a orrs r2, r3 + ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); + 80014e6: 687b ldr r3, [r7, #4] + 80014e8: 685b ldr r3, [r3, #4] + 80014ea: 3301 adds r3, #1 + 80014ec: 781b ldrb r3, [r3, #0] + 80014ee: 021b lsls r3, r3, #8 + heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | + 80014f0: 431a orrs r2, r3 + ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); + 80014f2: 687b ldr r3, [r7, #4] + 80014f4: 685b ldr r3, [r3, #4] + 80014f6: 781b ldrb r3, [r3, #0] + 80014f8: 4619 mov r1, r3 + heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | + 80014fa: 687b ldr r3, [r7, #4] + 80014fc: 681b ldr r3, [r3, #0] + ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); + 80014fe: 430a orrs r2, r1 + heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | + 8001500: f8c3 2304 str.w r2, [r3, #772] ; 0x304 + + heth->ErrorCode = HAL_ETH_ERROR_NONE; + 8001504: 687b ldr r3, [r7, #4] + 8001506: 2200 movs r2, #0 + 8001508: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + heth->gState = HAL_ETH_STATE_READY; + 800150c: 687b ldr r3, [r7, #4] + 800150e: 2210 movs r2, #16 + 8001510: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8001514: 2300 movs r3, #0 +} + 8001516: 4618 mov r0, r3 + 8001518: 3710 adds r7, #16 + 800151a: 46bd mov sp, r7 + 800151c: bd80 pop {r7, pc} + 800151e: bf00 nop + 8001520: 58024400 .word 0x58024400 + 8001524: 58000400 .word 0x58000400 + 8001528: 431bde83 .word 0x431bde83 + 800152c: ffff8001 .word 0xffff8001 + +08001530 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) +{ + 8001530: b580 push {r7, lr} + 8001532: b082 sub sp, #8 + 8001534: af00 add r7, sp, #0 + 8001536: 6078 str r0, [r7, #4] + if (heth->gState == HAL_ETH_STATE_READY) + 8001538: 687b ldr r3, [r7, #4] + 800153a: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800153e: 2b10 cmp r3, #16 + 8001540: d153 bne.n 80015ea + { + heth->gState = HAL_ETH_STATE_BUSY; + 8001542: 687b ldr r3, [r7, #4] + 8001544: 2223 movs r2, #35 ; 0x23 + 8001546: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + 800154a: 687b ldr r3, [r7, #4] + 800154c: 2204 movs r2, #4 + 800154e: 66da str r2, [r3, #108] ; 0x6c + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + 8001550: 6878 ldr r0, [r7, #4] + 8001552: f000 f9f6 bl 8001942 + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + 8001556: 687b ldr r3, [r7, #4] + 8001558: 681b ldr r3, [r3, #0] + 800155a: 681a ldr r2, [r3, #0] + 800155c: 687b ldr r3, [r7, #4] + 800155e: 681b ldr r3, [r3, #0] + 8001560: f042 0202 orr.w r2, r2, #2 + 8001564: 601a str r2, [r3, #0] + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + 8001566: 687b ldr r3, [r7, #4] + 8001568: 681b ldr r3, [r3, #0] + 800156a: 681a ldr r2, [r3, #0] + 800156c: 687b ldr r3, [r7, #4] + 800156e: 681b ldr r3, [r3, #0] + 8001570: f042 0201 orr.w r2, r2, #1 + 8001574: 601a str r2, [r3, #0] + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + 8001576: 687b ldr r3, [r7, #4] + 8001578: 681b ldr r3, [r3, #0] + 800157a: f8d3 2d00 ldr.w r2, [r3, #3328] ; 0xd00 + 800157e: 687b ldr r3, [r7, #4] + 8001580: 681b ldr r3, [r3, #0] + 8001582: f042 0201 orr.w r2, r2, #1 + 8001586: f8c3 2d00 str.w r2, [r3, #3328] ; 0xd00 + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + 800158a: 687b ldr r3, [r7, #4] + 800158c: 681b ldr r3, [r3, #0] + 800158e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001592: f8d3 3104 ldr.w r3, [r3, #260] ; 0x104 + 8001596: 687a ldr r2, [r7, #4] + 8001598: 6812 ldr r2, [r2, #0] + 800159a: f043 0301 orr.w r3, r3, #1 + 800159e: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80015a2: f8c2 3104 str.w r3, [r2, #260] ; 0x104 + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + 80015a6: 687b ldr r3, [r7, #4] + 80015a8: 681b ldr r3, [r3, #0] + 80015aa: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80015ae: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 80015b2: 687a ldr r2, [r7, #4] + 80015b4: 6812 ldr r2, [r2, #0] + 80015b6: f043 0301 orr.w r3, r3, #1 + 80015ba: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80015be: f8c2 3108 str.w r3, [r2, #264] ; 0x108 + + /* Clear Tx and Rx process stopped flags */ + heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); + 80015c2: 687b ldr r3, [r7, #4] + 80015c4: 681b ldr r3, [r3, #0] + 80015c6: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80015ca: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 + 80015ce: 687a ldr r2, [r7, #4] + 80015d0: 6812 ldr r2, [r2, #0] + 80015d2: f443 7381 orr.w r3, r3, #258 ; 0x102 + 80015d6: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80015da: f8c2 3160 str.w r3, [r2, #352] ; 0x160 + + heth->gState = HAL_ETH_STATE_STARTED; + 80015de: 687b ldr r3, [r7, #4] + 80015e0: 2223 movs r2, #35 ; 0x23 + 80015e2: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 80015e6: 2300 movs r3, #0 + 80015e8: e000 b.n 80015ec + } + else + { + return HAL_ERROR; + 80015ea: 2301 movs r3, #1 + } +} + 80015ec: 4618 mov r0, r3 + 80015ee: 3708 adds r7, #8 + 80015f0: 46bd mov sp, r7 + 80015f2: bd80 pop {r7, pc} + +080015f4 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + 80015f4: b480 push {r7} + 80015f6: b083 sub sp, #12 + 80015f8: af00 add r7, sp, #0 + 80015fa: 6078 str r0, [r7, #4] + if (heth->gState == HAL_ETH_STATE_STARTED) + 80015fc: 687b ldr r3, [r7, #4] + 80015fe: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8001602: 2b23 cmp r3, #35 ; 0x23 + 8001604: d13f bne.n 8001686 + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + 8001606: 687b ldr r3, [r7, #4] + 8001608: 2223 movs r2, #35 ; 0x23 + 800160a: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + 800160e: 687b ldr r3, [r7, #4] + 8001610: 681b ldr r3, [r3, #0] + 8001612: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001616: f8d3 3104 ldr.w r3, [r3, #260] ; 0x104 + 800161a: 687a ldr r2, [r7, #4] + 800161c: 6812 ldr r2, [r2, #0] + 800161e: f023 0301 bic.w r3, r3, #1 + 8001622: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8001626: f8c2 3104 str.w r3, [r2, #260] ; 0x104 + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + 800162a: 687b ldr r3, [r7, #4] + 800162c: 681b ldr r3, [r3, #0] + 800162e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001632: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 8001636: 687a ldr r2, [r7, #4] + 8001638: 6812 ldr r2, [r2, #0] + 800163a: f023 0301 bic.w r3, r3, #1 + 800163e: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8001642: f8c2 3108 str.w r3, [r2, #264] ; 0x108 + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + 8001646: 687b ldr r3, [r7, #4] + 8001648: 681b ldr r3, [r3, #0] + 800164a: 681a ldr r2, [r3, #0] + 800164c: 687b ldr r3, [r7, #4] + 800164e: 681b ldr r3, [r3, #0] + 8001650: f022 0201 bic.w r2, r2, #1 + 8001654: 601a str r2, [r3, #0] + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + 8001656: 687b ldr r3, [r7, #4] + 8001658: 681b ldr r3, [r3, #0] + 800165a: f8d3 2d00 ldr.w r2, [r3, #3328] ; 0xd00 + 800165e: 687b ldr r3, [r7, #4] + 8001660: 681b ldr r3, [r3, #0] + 8001662: f042 0201 orr.w r2, r2, #1 + 8001666: f8c3 2d00 str.w r2, [r3, #3328] ; 0xd00 + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + 800166a: 687b ldr r3, [r7, #4] + 800166c: 681b ldr r3, [r3, #0] + 800166e: 681a ldr r2, [r3, #0] + 8001670: 687b ldr r3, [r7, #4] + 8001672: 681b ldr r3, [r3, #0] + 8001674: f022 0202 bic.w r2, r2, #2 + 8001678: 601a str r2, [r3, #0] + + heth->gState = HAL_ETH_STATE_READY; + 800167a: 687b ldr r3, [r7, #4] + 800167c: 2210 movs r2, #16 + 800167e: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + + /* Return function status */ + return HAL_OK; + 8001682: 2300 movs r3, #0 + 8001684: e000 b.n 8001688 + } + else + { + return HAL_ERROR; + 8001686: 2301 movs r3, #1 + } +} + 8001688: 4618 mov r0, r3 + 800168a: 370c adds r7, #12 + 800168c: 46bd mov sp, r7 + 800168e: f85d 7b04 ldr.w r7, [sp], #4 + 8001692: 4770 bx lr + +08001694 : + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @param Timeout: timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout) +{ + 8001694: b580 push {r7, lr} + 8001696: b086 sub sp, #24 + 8001698: af00 add r7, sp, #0 + 800169a: 60f8 str r0, [r7, #12] + 800169c: 60b9 str r1, [r7, #8] + 800169e: 607a str r2, [r7, #4] + uint32_t tickstart; + ETH_DMADescTypeDef *dmatxdesc; + + if (pTxConfig == NULL) + 80016a0: 68bb ldr r3, [r7, #8] + 80016a2: 2b00 cmp r3, #0 + 80016a4: d109 bne.n 80016ba + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + 80016a6: 68fb ldr r3, [r7, #12] + 80016a8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80016ac: f043 0201 orr.w r2, r3, #1 + 80016b0: 68fb ldr r3, [r7, #12] + 80016b2: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + return HAL_ERROR; + 80016b6: 2301 movs r3, #1 + 80016b8: e07f b.n 80017ba + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + 80016ba: 68fb ldr r3, [r7, #12] + 80016bc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80016c0: 2b23 cmp r3, #35 ; 0x23 + 80016c2: d179 bne.n 80017b8 + { + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE) + 80016c4: 2200 movs r2, #0 + 80016c6: 68b9 ldr r1, [r7, #8] + 80016c8: 68f8 ldr r0, [r7, #12] + 80016ca: f001 f8c9 bl 8002860 + 80016ce: 4603 mov r3, r0 + 80016d0: 2b00 cmp r3, #0 + 80016d2: d009 beq.n 80016e8 + { + /* Set the ETH error code */ + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + 80016d4: 68fb ldr r3, [r7, #12] + 80016d6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80016da: f043 0202 orr.w r2, r3, #2 + 80016de: 68fb ldr r3, [r7, #12] + 80016e0: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + return HAL_ERROR; + 80016e4: 2301 movs r3, #1 + 80016e6: e068 b.n 80017ba + __ASM volatile ("dsb 0xF":::"memory"); + 80016e8: f3bf 8f4f dsb sy +} + 80016ec: bf00 nop + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; + 80016ee: 68fb ldr r3, [r7, #12] + 80016f0: 6a9a ldr r2, [r3, #40] ; 0x28 + 80016f2: 68fb ldr r3, [r7, #12] + 80016f4: 3206 adds r2, #6 + 80016f6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80016fa: 617b str r3, [r7, #20] + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + 80016fc: 68fb ldr r3, [r7, #12] + 80016fe: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001700: 1c5a adds r2, r3, #1 + 8001702: 68fb ldr r3, [r7, #12] + 8001704: 629a str r2, [r3, #40] ; 0x28 + 8001706: 68fb ldr r3, [r7, #12] + 8001708: 6a9b ldr r3, [r3, #40] ; 0x28 + 800170a: 2b03 cmp r3, #3 + 800170c: d904 bls.n 8001718 + 800170e: 68fb ldr r3, [r7, #12] + 8001710: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001712: 1f1a subs r2, r3, #4 + 8001714: 68fb ldr r3, [r7, #12] + 8001716: 629a str r2, [r3, #40] ; 0x28 + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + 8001718: 68fb ldr r3, [r7, #12] + 800171a: 6a99 ldr r1, [r3, #40] ; 0x28 + 800171c: 68fb ldr r3, [r7, #12] + 800171e: 681a ldr r2, [r3, #0] + 8001720: 68fb ldr r3, [r7, #12] + 8001722: 3106 adds r1, #6 + 8001724: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 8001728: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 800172c: f8c2 3120 str.w r3, [r2, #288] ; 0x120 + + tickstart = HAL_GetTick(); + 8001730: f7ff fc6c bl 800100c + 8001734: 6138 str r0, [r7, #16] + + /* Wait for data to be transmitted or timeout occurred */ + while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET) + 8001736: e039 b.n 80017ac + { + if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET) + 8001738: 68fb ldr r3, [r7, #12] + 800173a: 681b ldr r3, [r3, #0] + 800173c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001740: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 + 8001744: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001748: 2b00 cmp r3, #0 + 800174a: d012 beq.n 8001772 + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + 800174c: 68fb ldr r3, [r7, #12] + 800174e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001752: f043 0208 orr.w r2, r3, #8 + 8001756: 68fb ldr r3, [r7, #12] + 8001758: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + heth->DMAErrorCode = heth->Instance->DMACSR; + 800175c: 68fb ldr r3, [r7, #12] + 800175e: 681b ldr r3, [r3, #0] + 8001760: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001764: f8d3 2160 ldr.w r2, [r3, #352] ; 0x160 + 8001768: 68fb ldr r3, [r7, #12] + 800176a: f8c3 208c str.w r2, [r3, #140] ; 0x8c + /* Return function status */ + return HAL_ERROR; + 800176e: 2301 movs r3, #1 + 8001770: e023 b.n 80017ba + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8001772: 687b ldr r3, [r7, #4] + 8001774: f1b3 3fff cmp.w r3, #4294967295 + 8001778: d018 beq.n 80017ac + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 800177a: f7ff fc47 bl 800100c + 800177e: 4602 mov r2, r0 + 8001780: 693b ldr r3, [r7, #16] + 8001782: 1ad3 subs r3, r2, r3 + 8001784: 687a ldr r2, [r7, #4] + 8001786: 429a cmp r2, r3 + 8001788: d302 bcc.n 8001790 + 800178a: 687b ldr r3, [r7, #4] + 800178c: 2b00 cmp r3, #0 + 800178e: d10d bne.n 80017ac + { + heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; + 8001790: 68fb ldr r3, [r7, #12] + 8001792: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001796: f043 0204 orr.w r2, r3, #4 + 800179a: 68fb ldr r3, [r7, #12] + 800179c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + /* Clear TX descriptor so that we can proceed */ + dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD); + 80017a0: 697b ldr r3, [r7, #20] + 80017a2: f04f 5240 mov.w r2, #805306368 ; 0x30000000 + 80017a6: 60da str r2, [r3, #12] + return HAL_ERROR; + 80017a8: 2301 movs r3, #1 + 80017aa: e006 b.n 80017ba + while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET) + 80017ac: 697b ldr r3, [r7, #20] + 80017ae: 68db ldr r3, [r3, #12] + 80017b0: 2b00 cmp r3, #0 + 80017b2: dbc1 blt.n 8001738 + } + } + } + + /* Return function status */ + return HAL_OK; + 80017b4: 2300 movs r3, #0 + 80017b6: e000 b.n 80017ba + } + else + { + return HAL_ERROR; + 80017b8: 2301 movs r3, #1 + } +} + 80017ba: 4618 mov r0, r3 + 80017bc: 3718 adds r7, #24 + 80017be: 46bd mov sp, r7 + 80017c0: bd80 pop {r7, pc} + +080017c2 : + * the configuration information for ETHERNET module + * @param pAppBuff: Pointer to an application buffer to receive the packet. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) +{ + 80017c2: b580 push {r7, lr} + 80017c4: b088 sub sp, #32 + 80017c6: af00 add r7, sp, #0 + 80017c8: 6078 str r0, [r7, #4] + 80017ca: 6039 str r1, [r7, #0] + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + 80017cc: 2300 movs r3, #0 + 80017ce: 617b str r3, [r7, #20] + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; + 80017d0: 2300 movs r3, #0 + 80017d2: 73fb strb r3, [r7, #15] + + + if (pAppBuff == NULL) + 80017d4: 683b ldr r3, [r7, #0] + 80017d6: 2b00 cmp r3, #0 + 80017d8: d109 bne.n 80017ee + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + 80017da: 687b ldr r3, [r7, #4] + 80017dc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80017e0: f043 0201 orr.w r2, r3, #1 + 80017e4: 687b ldr r3, [r7, #4] + 80017e6: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + return HAL_ERROR; + 80017ea: 2301 movs r3, #1 + 80017ec: e0a5 b.n 800193a + } + + if (heth->gState != HAL_ETH_STATE_STARTED) + 80017ee: 687b ldr r3, [r7, #4] + 80017f0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80017f4: 2b23 cmp r3, #35 ; 0x23 + 80017f6: d001 beq.n 80017fc + { + return HAL_ERROR; + 80017f8: 2301 movs r3, #1 + 80017fa: e09e b.n 800193a + } + + descidx = heth->RxDescList.RxDescIdx; + 80017fc: 687b ldr r3, [r7, #4] + 80017fe: 6ddb ldr r3, [r3, #92] ; 0x5c + 8001800: 61fb str r3, [r7, #28] + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 8001802: 687b ldr r3, [r7, #4] + 8001804: 69fa ldr r2, [r7, #28] + 8001806: 3212 adds r2, #18 + 8001808: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800180c: 61bb str r3, [r7, #24] + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; + 800180e: 687b ldr r3, [r7, #4] + 8001810: 6edb ldr r3, [r3, #108] ; 0x6c + 8001812: f1c3 0304 rsb r3, r3, #4 + 8001816: 60bb str r3, [r7, #8] + + /* Check if descriptor is not owned by DMA */ + while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + 8001818: e067 b.n 80018ea + && (rxdataready == 0U)) + { + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET) + 800181a: 69bb ldr r3, [r7, #24] + 800181c: 68db ldr r3, [r3, #12] + 800181e: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 + 8001822: 2b00 cmp r3, #0 + 8001824: d007 beq.n 8001836 + { + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1; + 8001826: 69bb ldr r3, [r7, #24] + 8001828: 685a ldr r2, [r3, #4] + 800182a: 687b ldr r3, [r7, #4] + 800182c: 679a str r2, [r3, #120] ; 0x78 + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0; + 800182e: 69bb ldr r3, [r7, #24] + 8001830: 681a ldr r2, [r3, #0] + 8001832: 687b ldr r3, [r7, #4] + 8001834: 675a str r2, [r3, #116] ; 0x74 + } + if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) + 8001836: 69bb ldr r3, [r7, #24] + 8001838: 68db ldr r3, [r3, #12] + 800183a: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 800183e: 2b00 cmp r3, #0 + 8001840: d103 bne.n 800184a + 8001842: 687b ldr r3, [r7, #4] + 8001844: 6fdb ldr r3, [r3, #124] ; 0x7c + 8001846: 2b00 cmp r3, #0 + 8001848: d03d beq.n 80018c6 + { + /* Check if first descriptor */ + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) + 800184a: 69bb ldr r3, [r7, #24] + 800184c: 68db ldr r3, [r3, #12] + 800184e: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8001852: 2b00 cmp r3, #0 + 8001854: d005 beq.n 8001862 + { + heth->RxDescList.RxDescCnt = 0; + 8001856: 687b ldr r3, [r7, #4] + 8001858: 2200 movs r2, #0 + 800185a: 661a str r2, [r3, #96] ; 0x60 + heth->RxDescList.RxDataLength = 0; + 800185c: 687b ldr r3, [r7, #4] + 800185e: 2200 movs r2, #0 + 8001860: 665a str r2, [r3, #100] ; 0x64 + } + + /* Check if last descriptor */ + bufflength = heth->Init.RxBuffLen; + 8001862: 687b ldr r3, [r7, #4] + 8001864: 695b ldr r3, [r3, #20] + 8001866: 613b str r3, [r7, #16] + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET) + 8001868: 69bb ldr r3, [r7, #24] + 800186a: 68db ldr r3, [r3, #12] + 800186c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001870: 2b00 cmp r3, #0 + 8001872: d00d beq.n 8001890 + { + bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; + 8001874: 69bb ldr r3, [r7, #24] + 8001876: 68db ldr r3, [r3, #12] + 8001878: f3c3 020e ubfx r2, r3, #0, #15 + 800187c: 687b ldr r3, [r7, #4] + 800187e: 6e5b ldr r3, [r3, #100] ; 0x64 + 8001880: 1ad3 subs r3, r2, r3 + 8001882: 613b str r3, [r7, #16] + + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3; + 8001884: 69bb ldr r3, [r7, #24] + 8001886: 68da ldr r2, [r3, #12] + 8001888: 687b ldr r3, [r7, #4] + 800188a: 671a str r2, [r3, #112] ; 0x70 + + /* Packet ready */ + rxdataready = 1; + 800188c: 2301 movs r3, #1 + 800188e: 73fb strb r3, [r7, #15] + /*Call registered Link callback*/ + heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, bufflength); +#else + /* Link callback */ + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + 8001890: 687b ldr r3, [r7, #4] + 8001892: f103 007c add.w r0, r3, #124 ; 0x7c + 8001896: 687b ldr r3, [r7, #4] + 8001898: f103 0180 add.w r1, r3, #128 ; 0x80 + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); + 800189c: 69bb ldr r3, [r7, #24] + 800189e: 691b ldr r3, [r3, #16] + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + 80018a0: 461a mov r2, r3 + 80018a2: 693b ldr r3, [r7, #16] + 80018a4: b29b uxth r3, r3 + 80018a6: f003 fdc9 bl 800543c +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->RxDescList.RxDescCnt++; + 80018aa: 687b ldr r3, [r7, #4] + 80018ac: 6e1b ldr r3, [r3, #96] ; 0x60 + 80018ae: 1c5a adds r2, r3, #1 + 80018b0: 687b ldr r3, [r7, #4] + 80018b2: 661a str r2, [r3, #96] ; 0x60 + heth->RxDescList.RxDataLength += bufflength; + 80018b4: 687b ldr r3, [r7, #4] + 80018b6: 6e5a ldr r2, [r3, #100] ; 0x64 + 80018b8: 693b ldr r3, [r7, #16] + 80018ba: 441a add r2, r3 + 80018bc: 687b ldr r3, [r7, #4] + 80018be: 665a str r2, [r3, #100] ; 0x64 + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; + 80018c0: 69bb ldr r3, [r7, #24] + 80018c2: 2200 movs r2, #0 + 80018c4: 611a str r2, [r3, #16] + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + 80018c6: 69fb ldr r3, [r7, #28] + 80018c8: 3301 adds r3, #1 + 80018ca: 61fb str r3, [r7, #28] + 80018cc: 69fb ldr r3, [r7, #28] + 80018ce: 2b03 cmp r3, #3 + 80018d0: d902 bls.n 80018d8 + 80018d2: 69fb ldr r3, [r7, #28] + 80018d4: 3b04 subs r3, #4 + 80018d6: 61fb str r3, [r7, #28] + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 80018d8: 687b ldr r3, [r7, #4] + 80018da: 69fa ldr r2, [r7, #28] + 80018dc: 3212 adds r2, #18 + 80018de: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80018e2: 61bb str r3, [r7, #24] + desccnt++; + 80018e4: 697b ldr r3, [r7, #20] + 80018e6: 3301 adds r3, #1 + 80018e8: 617b str r3, [r7, #20] + while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + 80018ea: 69bb ldr r3, [r7, #24] + 80018ec: 68db ldr r3, [r3, #12] + && (rxdataready == 0U)) + 80018ee: 2b00 cmp r3, #0 + 80018f0: db06 blt.n 8001900 + while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + 80018f2: 697a ldr r2, [r7, #20] + 80018f4: 68bb ldr r3, [r7, #8] + 80018f6: 429a cmp r2, r3 + 80018f8: d202 bcs.n 8001900 + && (rxdataready == 0U)) + 80018fa: 7bfb ldrb r3, [r7, #15] + 80018fc: 2b00 cmp r3, #0 + 80018fe: d08c beq.n 800181a + } + + heth->RxDescList.RxBuildDescCnt += desccnt; + 8001900: 687b ldr r3, [r7, #4] + 8001902: 6eda ldr r2, [r3, #108] ; 0x6c + 8001904: 697b ldr r3, [r7, #20] + 8001906: 441a add r2, r3 + 8001908: 687b ldr r3, [r7, #4] + 800190a: 66da str r2, [r3, #108] ; 0x6c + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + 800190c: 687b ldr r3, [r7, #4] + 800190e: 6edb ldr r3, [r3, #108] ; 0x6c + 8001910: 2b00 cmp r3, #0 + 8001912: d002 beq.n 800191a + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); + 8001914: 6878 ldr r0, [r7, #4] + 8001916: f000 f814 bl 8001942 + } + + heth->RxDescList.RxDescIdx = descidx; + 800191a: 687b ldr r3, [r7, #4] + 800191c: 69fa ldr r2, [r7, #28] + 800191e: 65da str r2, [r3, #92] ; 0x5c + + if (rxdataready == 1U) + 8001920: 7bfb ldrb r3, [r7, #15] + 8001922: 2b01 cmp r3, #1 + 8001924: d108 bne.n 8001938 + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + 8001926: 687b ldr r3, [r7, #4] + 8001928: 6fda ldr r2, [r3, #124] ; 0x7c + 800192a: 683b ldr r3, [r7, #0] + 800192c: 601a str r2, [r3, #0] + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; + 800192e: 687b ldr r3, [r7, #4] + 8001930: 2200 movs r2, #0 + 8001932: 67da str r2, [r3, #124] ; 0x7c + + return HAL_OK; + 8001934: 2300 movs r3, #0 + 8001936: e000 b.n 800193a + } + + /* Packet not ready */ + return HAL_ERROR; + 8001938: 2301 movs r3, #1 +} + 800193a: 4618 mov r0, r3 + 800193c: 3720 adds r7, #32 + 800193e: 46bd mov sp, r7 + 8001940: bd80 pop {r7, pc} + +08001942 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) +{ + 8001942: b580 push {r7, lr} + 8001944: b088 sub sp, #32 + 8001946: af00 add r7, sp, #0 + 8001948: 6078 str r0, [r7, #4] + uint32_t descidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + 800194a: 2300 movs r3, #0 + 800194c: 60fb str r3, [r7, #12] + uint8_t allocStatus = 1U; + 800194e: 2301 movs r3, #1 + 8001950: 74fb strb r3, [r7, #19] + + descidx = heth->RxDescList.RxBuildDescIdx; + 8001952: 687b ldr r3, [r7, #4] + 8001954: 6e9b ldr r3, [r3, #104] ; 0x68 + 8001956: 61fb str r3, [r7, #28] + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 8001958: 687b ldr r3, [r7, #4] + 800195a: 69fa ldr r2, [r7, #28] + 800195c: 3212 adds r2, #18 + 800195e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8001962: 617b str r3, [r7, #20] + desccount = heth->RxDescList.RxBuildDescCnt; + 8001964: 687b ldr r3, [r7, #4] + 8001966: 6edb ldr r3, [r3, #108] ; 0x6c + 8001968: 61bb str r3, [r7, #24] + + while ((desccount > 0U) && (allocStatus != 0U)) + 800196a: e03b b.n 80019e4 + { + /* Check if a buffer's attached the descriptor */ + if (READ_REG(dmarxdesc->BackupAddr0) == 0U) + 800196c: 697b ldr r3, [r7, #20] + 800196e: 691b ldr r3, [r3, #16] + 8001970: 2b00 cmp r3, #0 + 8001972: d112 bne.n 800199a +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Allocate callback*/ + heth->rxAllocateCallback(&buff); +#else + /* Allocate callback */ + HAL_ETH_RxAllocateCallback(&buff); + 8001974: f107 030c add.w r3, r7, #12 + 8001978: 4618 mov r0, r3 + 800197a: f003 fd2f bl 80053dc +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + if (buff == NULL) + 800197e: 68fb ldr r3, [r7, #12] + 8001980: 2b00 cmp r3, #0 + 8001982: d102 bne.n 800198a + { + allocStatus = 0U; + 8001984: 2300 movs r3, #0 + 8001986: 74fb strb r3, [r7, #19] + 8001988: e007 b.n 800199a + } + else + { + WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); + 800198a: 68fb ldr r3, [r7, #12] + 800198c: 461a mov r2, r3 + 800198e: 697b ldr r3, [r7, #20] + 8001990: 611a str r2, [r3, #16] + WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff); + 8001992: 68fb ldr r3, [r7, #12] + 8001994: 461a mov r2, r3 + 8001996: 697b ldr r3, [r7, #20] + 8001998: 601a str r2, [r3, #0] + } + } + + if (allocStatus != 0U) + 800199a: 7cfb ldrb r3, [r7, #19] + 800199c: 2b00 cmp r3, #0 + 800199e: d021 beq.n 80019e4 + __ASM volatile ("dmb 0xF":::"memory"); + 80019a0: f3bf 8f5f dmb sy +} + 80019a4: bf00 nop + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + if (heth->RxDescList.ItMode != 0U) + 80019a6: 687b ldr r3, [r7, #4] + 80019a8: 6d9b ldr r3, [r3, #88] ; 0x58 + 80019aa: 2b00 cmp r3, #0 + 80019ac: d004 beq.n 80019b8 + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC); + 80019ae: 697b ldr r3, [r7, #20] + 80019b0: f04f 4241 mov.w r2, #3238002688 ; 0xc1000000 + 80019b4: 60da str r2, [r3, #12] + 80019b6: e003 b.n 80019c0 + } + else + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V); + 80019b8: 697b ldr r3, [r7, #20] + 80019ba: f04f 4201 mov.w r2, #2164260864 ; 0x81000000 + 80019be: 60da str r2, [r3, #12] + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + 80019c0: 69fb ldr r3, [r7, #28] + 80019c2: 3301 adds r3, #1 + 80019c4: 61fb str r3, [r7, #28] + 80019c6: 69fb ldr r3, [r7, #28] + 80019c8: 2b03 cmp r3, #3 + 80019ca: d902 bls.n 80019d2 + 80019cc: 69fb ldr r3, [r7, #28] + 80019ce: 3b04 subs r3, #4 + 80019d0: 61fb str r3, [r7, #28] + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + 80019d2: 687b ldr r3, [r7, #4] + 80019d4: 69fa ldr r2, [r7, #28] + 80019d6: 3212 adds r2, #18 + 80019d8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80019dc: 617b str r3, [r7, #20] + desccount--; + 80019de: 69bb ldr r3, [r7, #24] + 80019e0: 3b01 subs r3, #1 + 80019e2: 61bb str r3, [r7, #24] + while ((desccount > 0U) && (allocStatus != 0U)) + 80019e4: 69bb ldr r3, [r7, #24] + 80019e6: 2b00 cmp r3, #0 + 80019e8: d002 beq.n 80019f0 + 80019ea: 7cfb ldrb r3, [r7, #19] + 80019ec: 2b00 cmp r3, #0 + 80019ee: d1bd bne.n 800196c + } + } + + if (heth->RxDescList.RxBuildDescCnt != desccount) + 80019f0: 687b ldr r3, [r7, #4] + 80019f2: 6edb ldr r3, [r3, #108] ; 0x6c + 80019f4: 69ba ldr r2, [r7, #24] + 80019f6: 429a cmp r2, r3 + 80019f8: d00d beq.n 8001a16 + { + /* Set the Tail pointer address */ + WRITE_REG(heth->Instance->DMACRDTPR, 0); + 80019fa: 687b ldr r3, [r7, #4] + 80019fc: 681b ldr r3, [r3, #0] + 80019fe: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001a02: 461a mov r2, r3 + 8001a04: 2300 movs r3, #0 + 8001a06: f8c2 3128 str.w r3, [r2, #296] ; 0x128 + + heth->RxDescList.RxBuildDescIdx = descidx; + 8001a0a: 687b ldr r3, [r7, #4] + 8001a0c: 69fa ldr r2, [r7, #28] + 8001a0e: 669a str r2, [r3, #104] ; 0x68 + heth->RxDescList.RxBuildDescCnt = desccount; + 8001a10: 687b ldr r3, [r7, #4] + 8001a12: 69ba ldr r2, [r7, #24] + 8001a14: 66da str r2, [r3, #108] ; 0x6c + } +} + 8001a16: bf00 nop + 8001a18: 3720 adds r7, #32 + 8001a1a: 46bd mov sp, r7 + 8001a1c: bd80 pop {r7, pc} + ... + +08001a20 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + 8001a20: b580 push {r7, lr} + 8001a22: b084 sub sp, #16 + 8001a24: af00 add r7, sp, #0 + 8001a26: 6078 str r0, [r7, #4] + uint32_t macirqenable; + /* Packet received */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI)) + 8001a28: 687b ldr r3, [r7, #4] + 8001a2a: 681b ldr r3, [r3, #0] + 8001a2c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001a30: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 + 8001a34: f003 0340 and.w r3, r3, #64 ; 0x40 + 8001a38: 2b40 cmp r3, #64 ; 0x40 + 8001a3a: d115 bne.n 8001a68 + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE)) + 8001a3c: 687b ldr r3, [r7, #4] + 8001a3e: 681b ldr r3, [r3, #0] + 8001a40: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001a44: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 + 8001a48: f003 0340 and.w r3, r3, #64 ; 0x40 + 8001a4c: 2b40 cmp r3, #64 ; 0x40 + 8001a4e: d10b bne.n 8001a68 + { + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); + 8001a50: 687b ldr r3, [r7, #4] + 8001a52: 681b ldr r3, [r3, #0] + 8001a54: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001a58: 461a mov r2, r3 + 8001a5a: f248 0340 movw r3, #32832 ; 0x8040 + 8001a5e: f8c2 3160 str.w r3, [r2, #352] ; 0x160 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); + 8001a62: 6878 ldr r0, [r7, #4] + 8001a64: f000 f8f6 bl 8001c54 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + /* Packet transmitted */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI)) + 8001a68: 687b ldr r3, [r7, #4] + 8001a6a: 681b ldr r3, [r3, #0] + 8001a6c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001a70: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 + 8001a74: f003 0301 and.w r3, r3, #1 + 8001a78: 2b01 cmp r3, #1 + 8001a7a: d115 bne.n 8001aa8 + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE)) + 8001a7c: 687b ldr r3, [r7, #4] + 8001a7e: 681b ldr r3, [r3, #0] + 8001a80: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001a84: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 + 8001a88: f003 0301 and.w r3, r3, #1 + 8001a8c: 2b01 cmp r3, #1 + 8001a8e: d10b bne.n 8001aa8 + { + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); + 8001a90: 687b ldr r3, [r7, #4] + 8001a92: 681b ldr r3, [r3, #0] + 8001a94: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001a98: 461a mov r2, r3 + 8001a9a: f248 0301 movw r3, #32769 ; 0x8001 + 8001a9e: f8c2 3160 str.w r3, [r2, #352] ; 0x160 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); + 8001aa2: 6878 ldr r0, [r7, #4] + 8001aa4: f000 f8cc bl 8001c40 + } + } + + + /* ETH DMA Error */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS)) + 8001aa8: 687b ldr r3, [r7, #4] + 8001aaa: 681b ldr r3, [r3, #0] + 8001aac: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001ab0: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 + 8001ab4: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8001ab8: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8001abc: d153 bne.n 8001b66 + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE)) + 8001abe: 687b ldr r3, [r7, #4] + 8001ac0: 681b ldr r3, [r3, #0] + 8001ac2: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001ac6: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 + 8001aca: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8001ace: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8001ad2: d148 bne.n 8001b66 + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + 8001ad4: 687b ldr r3, [r7, #4] + 8001ad6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001ada: f043 0208 orr.w r2, r3, #8 + 8001ade: 687b ldr r3, [r7, #4] + 8001ae0: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* if fatal bus error occurred */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE)) + 8001ae4: 687b ldr r3, [r7, #4] + 8001ae6: 681b ldr r3, [r3, #0] + 8001ae8: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001aec: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 + 8001af0: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001af4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8001af8: d11e bne.n 8001b38 + { + /* Get DMA error code */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS)); + 8001afa: 687b ldr r3, [r7, #4] + 8001afc: 681b ldr r3, [r3, #0] + 8001afe: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001b02: f8d3 2160 ldr.w r2, [r3, #352] ; 0x160 + 8001b06: f241 1302 movw r3, #4354 ; 0x1102 + 8001b0a: 4013 ands r3, r2 + 8001b0c: 687a ldr r2, [r7, #4] + 8001b0e: f8c2 308c str.w r3, [r2, #140] ; 0x8c + + /* Disable all interrupts */ + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE); + 8001b12: 687b ldr r3, [r7, #4] + 8001b14: 681b ldr r3, [r3, #0] + 8001b16: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001b1a: f8d3 3134 ldr.w r3, [r3, #308] ; 0x134 + 8001b1e: 687a ldr r2, [r7, #4] + 8001b20: 6812 ldr r2, [r2, #0] + 8001b22: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8001b26: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8001b2a: f8c2 3134 str.w r3, [r2, #308] ; 0x134 + + /* Set HAL state to ERROR */ + heth->gState = HAL_ETH_STATE_ERROR; + 8001b2e: 687b ldr r3, [r7, #4] + 8001b30: 22e0 movs r2, #224 ; 0xe0 + 8001b32: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + 8001b36: e013 b.n 8001b60 + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + 8001b38: 687b ldr r3, [r7, #4] + 8001b3a: 681b ldr r3, [r3, #0] + 8001b3c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001b40: f8d3 3160 ldr.w r3, [r3, #352] ; 0x160 + 8001b44: f403 42cd and.w r2, r3, #26240 ; 0x6680 + 8001b48: 687b ldr r3, [r7, #4] + 8001b4a: f8c3 208c str.w r2, [r3, #140] ; 0x8c + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + + /* Clear the interrupt summary flag */ + __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + 8001b4e: 687b ldr r3, [r7, #4] + 8001b50: 681b ldr r3, [r3, #0] + 8001b52: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8001b56: 461a mov r2, r3 + 8001b58: f44f 43cd mov.w r3, #26240 ; 0x6680 + 8001b5c: f8c2 3160 str.w r3, [r2, #352] ; 0x160 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet DMA Error callback */ + HAL_ETH_ErrorCallback(heth); + 8001b60: 6878 ldr r0, [r7, #4] + 8001b62: f000 f881 bl 8001c68 + + } + } + + /* ETH MAC Error IT */ + macirqenable = heth->Instance->MACIER; + 8001b66: 687b ldr r3, [r7, #4] + 8001b68: 681b ldr r3, [r3, #0] + 8001b6a: f8d3 30b4 ldr.w r3, [r3, #180] ; 0xb4 + 8001b6e: 60fb str r3, [r7, #12] + if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ + 8001b70: 68fb ldr r3, [r7, #12] + 8001b72: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8001b76: 2b00 cmp r3, #0 + 8001b78: d104 bne.n 8001b84 + ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE)) + 8001b7a: 68fb ldr r3, [r7, #12] + 8001b7c: f403 5300 and.w r3, r3, #8192 ; 0x2000 + if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ + 8001b80: 2b00 cmp r3, #0 + 8001b82: d019 beq.n 8001bb8 + { + heth->ErrorCode |= HAL_ETH_ERROR_MAC; + 8001b84: 687b ldr r3, [r7, #4] + 8001b86: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001b8a: f043 0210 orr.w r2, r3, #16 + 8001b8e: 687b ldr r3, [r7, #4] + 8001b90: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Get MAC Rx Tx status and clear Status register pending bit */ + heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR); + 8001b94: 687b ldr r3, [r7, #4] + 8001b96: 681b ldr r3, [r3, #0] + 8001b98: f8d3 20b8 ldr.w r2, [r3, #184] ; 0xb8 + 8001b9c: 687b ldr r3, [r7, #4] + 8001b9e: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + + heth->gState = HAL_ETH_STATE_ERROR; + 8001ba2: 687b ldr r3, [r7, #4] + 8001ba4: 22e0 movs r2, #224 ; 0xe0 + 8001ba6: f8c3 2084 str.w r2, [r3, #132] ; 0x84 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback(heth); + 8001baa: 6878 ldr r0, [r7, #4] + 8001bac: f000 f85c bl 8001c68 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACErrorCode = (uint32_t)(0x0U); + 8001bb0: 687b ldr r3, [r7, #4] + 8001bb2: 2200 movs r2, #0 + 8001bb4: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* ETH PMT IT */ + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) + 8001bb8: 687b ldr r3, [r7, #4] + 8001bba: 681b ldr r3, [r3, #0] + 8001bbc: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 + 8001bc0: f003 0310 and.w r3, r3, #16 + 8001bc4: 2b10 cmp r3, #16 + 8001bc6: d10f bne.n 8001be8 + { + /* Get MAC Wake-up source and clear the status register pending bit */ + heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD)); + 8001bc8: 687b ldr r3, [r7, #4] + 8001bca: 681b ldr r3, [r3, #0] + 8001bcc: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 + 8001bd0: f003 0260 and.w r2, r3, #96 ; 0x60 + 8001bd4: 687b ldr r3, [r7, #4] + 8001bd6: f8c3 2094 str.w r2, [r3, #148] ; 0x94 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered PMT callback*/ + heth->PMTCallback(heth); +#else + /* Ethernet PMT callback */ + HAL_ETH_PMTCallback(heth); + 8001bda: 6878 ldr r0, [r7, #4] + 8001bdc: f000 f84e bl 8001c7c +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACWakeUpEvent = (uint32_t)(0x0U); + 8001be0: 687b ldr r3, [r7, #4] + 8001be2: 2200 movs r2, #0 + 8001be4: f8c3 2094 str.w r2, [r3, #148] ; 0x94 + } + + /* ETH EEE IT */ + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT)) + 8001be8: 687b ldr r3, [r7, #4] + 8001bea: 681b ldr r3, [r3, #0] + 8001bec: f8d3 30b0 ldr.w r3, [r3, #176] ; 0xb0 + 8001bf0: f003 0320 and.w r3, r3, #32 + 8001bf4: 2b20 cmp r3, #32 + 8001bf6: d10f bne.n 8001c18 + { + /* Get MAC LPI interrupt source and clear the status register pending bit */ + heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); + 8001bf8: 687b ldr r3, [r7, #4] + 8001bfa: 681b ldr r3, [r3, #0] + 8001bfc: f8d3 30c0 ldr.w r3, [r3, #192] ; 0xc0 + 8001c00: f003 020f and.w r2, r3, #15 + 8001c04: 687b ldr r3, [r7, #4] + 8001c06: f8c3 2098 str.w r2, [r3, #152] ; 0x98 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered EEE callback*/ + heth->EEECallback(heth); +#else + /* Ethernet EEE callback */ + HAL_ETH_EEECallback(heth); + 8001c0a: 6878 ldr r0, [r7, #4] + 8001c0c: f000 f840 bl 8001c90 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACLPIEvent = (uint32_t)(0x0U); + 8001c10: 687b ldr r3, [r7, #4] + 8001c12: 2200 movs r2, #0 + 8001c14: f8c3 2098 str.w r2, [r3, #152] ; 0x98 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + /* check ETH WAKEUP exti flag */ + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + 8001c18: 4b08 ldr r3, [pc, #32] ; (8001c3c ) + 8001c1a: 6a9b ldr r3, [r3, #40] ; 0x28 + 8001c1c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8001c20: 2b00 cmp r3, #0 + 8001c22: d006 beq.n 8001c32 + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); + 8001c24: 4b05 ldr r3, [pc, #20] ; (8001c3c ) + 8001c26: f44f 0280 mov.w r2, #4194304 ; 0x400000 + 8001c2a: 629a str r2, [r3, #40] ; 0x28 +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); + 8001c2c: 6878 ldr r0, [r7, #4] + 8001c2e: f000 f839 bl 8001ca4 +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +} + 8001c32: bf00 nop + 8001c34: 3710 adds r7, #16 + 8001c36: 46bd mov sp, r7 + 8001c38: bd80 pop {r7, pc} + 8001c3a: bf00 nop + 8001c3c: 58000080 .word 0x58000080 + +08001c40 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + 8001c40: b480 push {r7} + 8001c42: b083 sub sp, #12 + 8001c44: af00 add r7, sp, #0 + 8001c46: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + 8001c48: bf00 nop + 8001c4a: 370c adds r7, #12 + 8001c4c: 46bd mov sp, r7 + 8001c4e: f85d 7b04 ldr.w r7, [sp], #4 + 8001c52: 4770 bx lr + +08001c54 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + 8001c54: b480 push {r7} + 8001c56: b083 sub sp, #12 + 8001c58: af00 add r7, sp, #0 + 8001c5a: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxCpltCallback could be implemented in the user file + */ +} + 8001c5c: bf00 nop + 8001c5e: 370c adds r7, #12 + 8001c60: 46bd mov sp, r7 + 8001c62: f85d 7b04 ldr.w r7, [sp], #4 + 8001c66: 4770 bx lr + +08001c68 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + 8001c68: b480 push {r7} + 8001c6a: b083 sub sp, #12 + 8001c6c: af00 add r7, sp, #0 + 8001c6e: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_ErrorCallback could be implemented in the user file + */ +} + 8001c70: bf00 nop + 8001c72: 370c adds r7, #12 + 8001c74: 46bd mov sp, r7 + 8001c76: f85d 7b04 ldr.w r7, [sp], #4 + 8001c7a: 4770 bx lr + +08001c7c : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + 8001c7c: b480 push {r7} + 8001c7e: b083 sub sp, #12 + 8001c80: af00 add r7, sp, #0 + 8001c82: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_PMTCallback could be implemented in the user file + */ +} + 8001c84: bf00 nop + 8001c86: 370c adds r7, #12 + 8001c88: 46bd mov sp, r7 + 8001c8a: f85d 7b04 ldr.w r7, [sp], #4 + 8001c8e: 4770 bx lr + +08001c90 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth) +{ + 8001c90: b480 push {r7} + 8001c92: b083 sub sp, #12 + 8001c94: af00 add r7, sp, #0 + 8001c96: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_EEECallback could be implemented in the user file + */ +} + 8001c98: bf00 nop + 8001c9a: 370c adds r7, #12 + 8001c9c: 46bd mov sp, r7 + 8001c9e: f85d 7b04 ldr.w r7, [sp], #4 + 8001ca2: 4770 bx lr + +08001ca4 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +{ + 8001ca4: b480 push {r7} + 8001ca6: b083 sub sp, #12 + 8001ca8: af00 add r7, sp, #0 + 8001caa: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_WakeUpCallback could be implemented in the user file + */ +} + 8001cac: bf00 nop + 8001cae: 370c adds r7, #12 + 8001cb0: 46bd mov sp, r7 + 8001cb2: f85d 7b04 ldr.w r7, [sp], #4 + 8001cb6: 4770 bx lr + +08001cb8 : + * @param pRegValue: parameter to hold read value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) +{ + 8001cb8: b580 push {r7, lr} + 8001cba: b086 sub sp, #24 + 8001cbc: af00 add r7, sp, #0 + 8001cbe: 60f8 str r0, [r7, #12] + 8001cc0: 60b9 str r1, [r7, #8] + 8001cc2: 607a str r2, [r7, #4] + 8001cc4: 603b str r3, [r7, #0] + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) + 8001cc6: 68fb ldr r3, [r7, #12] + 8001cc8: 681b ldr r3, [r3, #0] + 8001cca: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 8001cce: f003 0301 and.w r3, r3, #1 + 8001cd2: 2b00 cmp r3, #0 + 8001cd4: d001 beq.n 8001cda + { + return HAL_ERROR; + 8001cd6: 2301 movs r3, #1 + 8001cd8: e03e b.n 8001d58 + } + + /* Get the MACMDIOAR value */ + WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); + 8001cda: 68fb ldr r3, [r7, #12] + 8001cdc: 681b ldr r3, [r3, #0] + 8001cde: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 8001ce2: 617b str r3, [r7, #20] + - Set the PHY device address + - Set the PHY register address + - Set the read mode + - Set the MII Busy bit */ + + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); + 8001ce4: 697b ldr r3, [r7, #20] + 8001ce6: f023 7278 bic.w r2, r3, #65011712 ; 0x3e00000 + 8001cea: 68bb ldr r3, [r7, #8] + 8001cec: 055b lsls r3, r3, #21 + 8001cee: 4313 orrs r3, r2 + 8001cf0: 617b str r3, [r7, #20] + MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); + 8001cf2: 697b ldr r3, [r7, #20] + 8001cf4: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8001cf8: 687b ldr r3, [r7, #4] + 8001cfa: 041b lsls r3, r3, #16 + 8001cfc: 4313 orrs r3, r2 + 8001cfe: 617b str r3, [r7, #20] + MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD); + 8001d00: 697b ldr r3, [r7, #20] + 8001d02: f043 030c orr.w r3, r3, #12 + 8001d06: 617b str r3, [r7, #20] + SET_BIT(tmpreg, ETH_MACMDIOAR_MB); + 8001d08: 697b ldr r3, [r7, #20] + 8001d0a: f043 0301 orr.w r3, r3, #1 + 8001d0e: 617b str r3, [r7, #20] + + /* Write the result value into the MDII Address register */ + WRITE_REG(heth->Instance->MACMDIOAR, tmpreg); + 8001d10: 68fb ldr r3, [r7, #12] + 8001d12: 681b ldr r3, [r3, #0] + 8001d14: 697a ldr r2, [r7, #20] + 8001d16: f8c3 2200 str.w r2, [r3, #512] ; 0x200 + + tickstart = HAL_GetTick(); + 8001d1a: f7ff f977 bl 800100c + 8001d1e: 6138 str r0, [r7, #16] + + /* Wait for the Busy flag */ + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + 8001d20: e009 b.n 8001d36 + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + 8001d22: f7ff f973 bl 800100c + 8001d26: 4602 mov r2, r0 + 8001d28: 693b ldr r3, [r7, #16] + 8001d2a: 1ad3 subs r3, r2, r3 + 8001d2c: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8001d30: d901 bls.n 8001d36 + { + return HAL_ERROR; + 8001d32: 2301 movs r3, #1 + 8001d34: e010 b.n 8001d58 + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + 8001d36: 68fb ldr r3, [r7, #12] + 8001d38: 681b ldr r3, [r3, #0] + 8001d3a: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 8001d3e: f003 0301 and.w r3, r3, #1 + 8001d42: 2b00 cmp r3, #0 + 8001d44: d1ed bne.n 8001d22 + } + } + + /* Get MACMIIDR value */ + WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR); + 8001d46: 68fb ldr r3, [r7, #12] + 8001d48: 681b ldr r3, [r3, #0] + 8001d4a: f8d3 3204 ldr.w r3, [r3, #516] ; 0x204 + 8001d4e: b29b uxth r3, r3 + 8001d50: 461a mov r2, r3 + 8001d52: 683b ldr r3, [r7, #0] + 8001d54: 601a str r2, [r3, #0] + + return HAL_OK; + 8001d56: 2300 movs r3, #0 +} + 8001d58: 4618 mov r0, r3 + 8001d5a: 3718 adds r7, #24 + 8001d5c: 46bd mov sp, r7 + 8001d5e: bd80 pop {r7, pc} + +08001d60 : + * @param RegValue: the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) +{ + 8001d60: b580 push {r7, lr} + 8001d62: b086 sub sp, #24 + 8001d64: af00 add r7, sp, #0 + 8001d66: 60f8 str r0, [r7, #12] + 8001d68: 60b9 str r1, [r7, #8] + 8001d6a: 607a str r2, [r7, #4] + 8001d6c: 603b str r3, [r7, #0] + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) + 8001d6e: 68fb ldr r3, [r7, #12] + 8001d70: 681b ldr r3, [r3, #0] + 8001d72: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 8001d76: f003 0301 and.w r3, r3, #1 + 8001d7a: 2b00 cmp r3, #0 + 8001d7c: d001 beq.n 8001d82 + { + return HAL_ERROR; + 8001d7e: 2301 movs r3, #1 + 8001d80: e03c b.n 8001dfc + } + + /* Get the MACMDIOAR value */ + WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); + 8001d82: 68fb ldr r3, [r7, #12] + 8001d84: 681b ldr r3, [r3, #0] + 8001d86: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 8001d8a: 617b str r3, [r7, #20] + - Set the PHY device address + - Set the PHY register address + - Set the write mode + - Set the MII Busy bit */ + + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); + 8001d8c: 697b ldr r3, [r7, #20] + 8001d8e: f023 7278 bic.w r2, r3, #65011712 ; 0x3e00000 + 8001d92: 68bb ldr r3, [r7, #8] + 8001d94: 055b lsls r3, r3, #21 + 8001d96: 4313 orrs r3, r2 + 8001d98: 617b str r3, [r7, #20] + MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); + 8001d9a: 697b ldr r3, [r7, #20] + 8001d9c: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8001da0: 687b ldr r3, [r7, #4] + 8001da2: 041b lsls r3, r3, #16 + 8001da4: 4313 orrs r3, r2 + 8001da6: 617b str r3, [r7, #20] + MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR); + 8001da8: 697b ldr r3, [r7, #20] + 8001daa: f023 030c bic.w r3, r3, #12 + 8001dae: f043 0304 orr.w r3, r3, #4 + 8001db2: 617b str r3, [r7, #20] + SET_BIT(tmpreg, ETH_MACMDIOAR_MB); + 8001db4: 697b ldr r3, [r7, #20] + 8001db6: f043 0301 orr.w r3, r3, #1 + 8001dba: 617b str r3, [r7, #20] + + + /* Give the value to the MII data register */ + WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue); + 8001dbc: 683b ldr r3, [r7, #0] + 8001dbe: b29a uxth r2, r3 + 8001dc0: 4b10 ldr r3, [pc, #64] ; (8001e04 ) + 8001dc2: f8c3 2204 str.w r2, [r3, #516] ; 0x204 + + /* Write the result value into the MII Address register */ + WRITE_REG(ETH->MACMDIOAR, tmpreg); + 8001dc6: 4a0f ldr r2, [pc, #60] ; (8001e04 ) + 8001dc8: 697b ldr r3, [r7, #20] + 8001dca: f8c2 3200 str.w r3, [r2, #512] ; 0x200 + + tickstart = HAL_GetTick(); + 8001dce: f7ff f91d bl 800100c + 8001dd2: 6138 str r0, [r7, #16] + + /* Wait for the Busy flag */ + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + 8001dd4: e009 b.n 8001dea + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + 8001dd6: f7ff f919 bl 800100c + 8001dda: 4602 mov r2, r0 + 8001ddc: 693b ldr r3, [r7, #16] + 8001dde: 1ad3 subs r3, r2, r3 + 8001de0: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8001de4: d901 bls.n 8001dea + { + return HAL_ERROR; + 8001de6: 2301 movs r3, #1 + 8001de8: e008 b.n 8001dfc + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + 8001dea: 68fb ldr r3, [r7, #12] + 8001dec: 681b ldr r3, [r3, #0] + 8001dee: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 8001df2: f003 0301 and.w r3, r3, #1 + 8001df6: 2b00 cmp r3, #0 + 8001df8: d1ed bne.n 8001dd6 + } + } + + return HAL_OK; + 8001dfa: 2300 movs r3, #0 +} + 8001dfc: 4618 mov r0, r3 + 8001dfe: 3718 adds r7, #24 + 8001e00: 46bd mov sp, r7 + 8001e02: bd80 pop {r7, pc} + 8001e04: 40028000 .word 0x40028000 + +08001e08 : + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold + * the configuration of the MAC. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + 8001e08: b480 push {r7} + 8001e0a: b083 sub sp, #12 + 8001e0c: af00 add r7, sp, #0 + 8001e0e: 6078 str r0, [r7, #4] + 8001e10: 6039 str r1, [r7, #0] + if (macconf == NULL) + 8001e12: 683b ldr r3, [r7, #0] + 8001e14: 2b00 cmp r3, #0 + 8001e16: d101 bne.n 8001e1c + { + return HAL_ERROR; + 8001e18: 2301 movs r3, #1 + 8001e1a: e1c3 b.n 80021a4 + } + + /* Get MAC parameters */ + macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN); + 8001e1c: 687b ldr r3, [r7, #4] + 8001e1e: 681b ldr r3, [r3, #0] + 8001e20: 681b ldr r3, [r3, #0] + 8001e22: f003 020c and.w r2, r3, #12 + 8001e26: 683b ldr r3, [r7, #0] + 8001e28: 62da str r2, [r3, #44] ; 0x2c + macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; + 8001e2a: 687b ldr r3, [r7, #4] + 8001e2c: 681b ldr r3, [r3, #0] + 8001e2e: 681b ldr r3, [r3, #0] + 8001e30: f003 0310 and.w r3, r3, #16 + 8001e34: 2b00 cmp r3, #0 + 8001e36: bf14 ite ne + 8001e38: 2301 movne r3, #1 + 8001e3a: 2300 moveq r3, #0 + 8001e3c: b2db uxtb r3, r3 + 8001e3e: 461a mov r2, r3 + 8001e40: 683b ldr r3, [r7, #0] + 8001e42: f883 2028 strb.w r2, [r3, #40] ; 0x28 + macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); + 8001e46: 687b ldr r3, [r7, #4] + 8001e48: 681b ldr r3, [r3, #0] + 8001e4a: 681b ldr r3, [r3, #0] + 8001e4c: f003 0260 and.w r2, r3, #96 ; 0x60 + 8001e50: 683b ldr r3, [r7, #0] + 8001e52: 625a str r2, [r3, #36] ; 0x24 + macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE; + 8001e54: 687b ldr r3, [r7, #4] + 8001e56: 681b ldr r3, [r3, #0] + 8001e58: 681b ldr r3, [r3, #0] + 8001e5a: f403 7380 and.w r3, r3, #256 ; 0x100 + 8001e5e: 2b00 cmp r3, #0 + 8001e60: bf0c ite eq + 8001e62: 2301 moveq r3, #1 + 8001e64: 2300 movne r3, #0 + 8001e66: b2db uxtb r3, r3 + 8001e68: 461a mov r2, r3 + 8001e6a: 683b ldr r3, [r7, #0] + 8001e6c: f883 2020 strb.w r2, [r3, #32] + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) + 8001e70: 687b ldr r3, [r7, #4] + 8001e72: 681b ldr r3, [r3, #0] + 8001e74: 681b ldr r3, [r3, #0] + 8001e76: f403 7300 and.w r3, r3, #512 ; 0x200 + ? ENABLE : DISABLE; + 8001e7a: 2b00 cmp r3, #0 + 8001e7c: bf14 ite ne + 8001e7e: 2301 movne r3, #1 + 8001e80: 2300 moveq r3, #0 + 8001e82: b2db uxtb r3, r3 + 8001e84: 461a mov r2, r3 + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) + 8001e86: 683b ldr r3, [r7, #0] + 8001e88: 77da strb r2, [r3, #31] + macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE; + 8001e8a: 687b ldr r3, [r7, #4] + 8001e8c: 681b ldr r3, [r3, #0] + 8001e8e: 681b ldr r3, [r3, #0] + 8001e90: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8001e94: 2b00 cmp r3, #0 + 8001e96: bf0c ite eq + 8001e98: 2301 moveq r3, #1 + 8001e9a: 2300 movne r3, #0 + 8001e9c: b2db uxtb r3, r3 + 8001e9e: 461a mov r2, r3 + 8001ea0: 683b ldr r3, [r7, #0] + 8001ea2: 779a strb r2, [r3, #30] + macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, + 8001ea4: 687b ldr r3, [r7, #4] + 8001ea6: 681b ldr r3, [r3, #0] + 8001ea8: 681b ldr r3, [r3, #0] + ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE; + 8001eaa: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8001eae: 2b00 cmp r3, #0 + 8001eb0: bf14 ite ne + 8001eb2: 2301 movne r3, #1 + 8001eb4: 2300 moveq r3, #0 + 8001eb6: b2db uxtb r3, r3 + 8001eb8: 461a mov r2, r3 + macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, + 8001eba: 683b ldr r3, [r7, #0] + 8001ebc: 775a strb r2, [r3, #29] + macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; + 8001ebe: 687b ldr r3, [r7, #4] + 8001ec0: 681b ldr r3, [r3, #0] + 8001ec2: 681b ldr r3, [r3, #0] + 8001ec4: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001ec8: 2b00 cmp r3, #0 + 8001eca: bf14 ite ne + 8001ecc: 2301 movne r3, #1 + 8001ece: 2300 moveq r3, #0 + 8001ed0: b2db uxtb r3, r3 + 8001ed2: 461a mov r2, r3 + 8001ed4: 683b ldr r3, [r7, #0] + 8001ed6: 771a strb r2, [r3, #28] + macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); + 8001ed8: 687b ldr r3, [r7, #4] + 8001eda: 681b ldr r3, [r3, #0] + 8001edc: 681b ldr r3, [r3, #0] + 8001ede: f403 5200 and.w r2, r3, #8192 ; 0x2000 + 8001ee2: 683b ldr r3, [r7, #0] + 8001ee4: 619a str r2, [r3, #24] + macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); + 8001ee6: 687b ldr r3, [r7, #4] + 8001ee8: 681b ldr r3, [r3, #0] + 8001eea: 681b ldr r3, [r3, #0] + 8001eec: f403 4280 and.w r2, r3, #16384 ; 0x4000 + 8001ef0: 683b ldr r3, [r7, #0] + 8001ef2: 615a str r2, [r3, #20] + macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE; + 8001ef4: 687b ldr r3, [r7, #4] + 8001ef6: 681b ldr r3, [r3, #0] + 8001ef8: 681b ldr r3, [r3, #0] + 8001efa: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8001efe: 2b00 cmp r3, #0 + 8001f00: bf14 ite ne + 8001f02: 2301 movne r3, #1 + 8001f04: 2300 moveq r3, #0 + 8001f06: b2db uxtb r3, r3 + 8001f08: 461a mov r2, r3 + 8001f0a: 683b ldr r3, [r7, #0] + 8001f0c: 749a strb r2, [r3, #18] + macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE; + 8001f0e: 687b ldr r3, [r7, #4] + 8001f10: 681b ldr r3, [r3, #0] + 8001f12: 681b ldr r3, [r3, #0] + 8001f14: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001f18: 2b00 cmp r3, #0 + 8001f1a: bf0c ite eq + 8001f1c: 2301 moveq r3, #1 + 8001f1e: 2300 movne r3, #0 + 8001f20: b2db uxtb r3, r3 + 8001f22: 461a mov r2, r3 + 8001f24: 683b ldr r3, [r7, #0] + 8001f26: 745a strb r2, [r3, #17] + macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE; + 8001f28: 687b ldr r3, [r7, #4] + 8001f2a: 681b ldr r3, [r3, #0] + 8001f2c: 681b ldr r3, [r3, #0] + 8001f2e: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8001f32: 2b00 cmp r3, #0 + 8001f34: bf0c ite eq + 8001f36: 2301 moveq r3, #1 + 8001f38: 2300 movne r3, #0 + 8001f3a: b2db uxtb r3, r3 + 8001f3c: 461a mov r2, r3 + 8001f3e: 683b ldr r3, [r7, #0] + 8001f40: 741a strb r2, [r3, #16] + macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE; + 8001f42: 687b ldr r3, [r7, #4] + 8001f44: 681b ldr r3, [r3, #0] + 8001f46: 681b ldr r3, [r3, #0] + 8001f48: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8001f4c: 2b00 cmp r3, #0 + 8001f4e: bf14 ite ne + 8001f50: 2301 movne r3, #1 + 8001f52: 2300 moveq r3, #0 + 8001f54: b2db uxtb r3, r3 + 8001f56: 461a mov r2, r3 + 8001f58: 683b ldr r3, [r7, #0] + 8001f5a: 73da strb r2, [r3, #15] + macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE; + 8001f5c: 687b ldr r3, [r7, #4] + 8001f5e: 681b ldr r3, [r3, #0] + 8001f60: 681b ldr r3, [r3, #0] + 8001f62: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001f66: 2b00 cmp r3, #0 + 8001f68: bf14 ite ne + 8001f6a: 2301 movne r3, #1 + 8001f6c: 2300 moveq r3, #0 + 8001f6e: b2db uxtb r3, r3 + 8001f70: 461a mov r2, r3 + 8001f72: 683b ldr r3, [r7, #0] + 8001f74: 739a strb r2, [r3, #14] + macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE; + 8001f76: 687b ldr r3, [r7, #4] + 8001f78: 681b ldr r3, [r3, #0] + 8001f7a: 681b ldr r3, [r3, #0] + 8001f7c: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8001f80: 2b00 cmp r3, #0 + 8001f82: bf14 ite ne + 8001f84: 2301 movne r3, #1 + 8001f86: 2300 moveq r3, #0 + 8001f88: b2db uxtb r3, r3 + 8001f8a: 461a mov r2, r3 + 8001f8c: 683b ldr r3, [r7, #0] + 8001f8e: 735a strb r2, [r3, #13] + macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, + 8001f90: 687b ldr r3, [r7, #4] + 8001f92: 681b ldr r3, [r3, #0] + 8001f94: 681b ldr r3, [r3, #0] + ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE; + 8001f96: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8001f9a: 2b00 cmp r3, #0 + 8001f9c: bf14 ite ne + 8001f9e: 2301 movne r3, #1 + 8001fa0: 2300 moveq r3, #0 + 8001fa2: b2db uxtb r3, r3 + 8001fa4: 461a mov r2, r3 + macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, + 8001fa6: 683b ldr r3, [r7, #0] + 8001fa8: 731a strb r2, [r3, #12] + macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG); + 8001faa: 687b ldr r3, [r7, #4] + 8001fac: 681b ldr r3, [r3, #0] + 8001fae: 681b ldr r3, [r3, #0] + 8001fb0: f003 62e0 and.w r2, r3, #117440512 ; 0x7000000 + 8001fb4: 683b ldr r3, [r7, #0] + 8001fb6: 609a str r2, [r3, #8] + macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE; + 8001fb8: 687b ldr r3, [r7, #4] + 8001fba: 681b ldr r3, [r3, #0] + 8001fbc: 681b ldr r3, [r3, #0] + 8001fbe: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8001fc2: 2b00 cmp r3, #0 + 8001fc4: bf14 ite ne + 8001fc6: 2301 movne r3, #1 + 8001fc8: 2300 moveq r3, #0 + 8001fca: b2db uxtb r3, r3 + 8001fcc: 461a mov r2, r3 + 8001fce: 683b ldr r3, [r7, #0] + 8001fd0: 711a strb r2, [r3, #4] + macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC); + 8001fd2: 687b ldr r3, [r7, #4] + 8001fd4: 681b ldr r3, [r3, #0] + 8001fd6: 681b ldr r3, [r3, #0] + 8001fd8: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 + 8001fdc: 683b ldr r3, [r7, #0] + 8001fde: 601a str r2, [r3, #0] + + macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL); + 8001fe0: 687b ldr r3, [r7, #4] + 8001fe2: 681b ldr r3, [r3, #0] + 8001fe4: 685b ldr r3, [r3, #4] + 8001fe6: f3c3 020d ubfx r2, r3, #0, #14 + 8001fea: 683b ldr r3, [r7, #0] + 8001fec: 635a str r2, [r3, #52] ; 0x34 + macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE; + 8001fee: 687b ldr r3, [r7, #4] + 8001ff0: 681b ldr r3, [r3, #0] + 8001ff2: 685b ldr r3, [r3, #4] + 8001ff4: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8001ff8: 2b00 cmp r3, #0 + 8001ffa: bf0c ite eq + 8001ffc: 2301 moveq r3, #1 + 8001ffe: 2300 movne r3, #0 + 8002000: b2db uxtb r3, r3 + 8002002: 461a mov r2, r3 + 8002004: 683b ldr r3, [r7, #0] + 8002006: f883 2032 strb.w r2, [r3, #50] ; 0x32 + macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE; + 800200a: 687b ldr r3, [r7, #4] + 800200c: 681b ldr r3, [r3, #0] + 800200e: 685b ldr r3, [r3, #4] + 8002010: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002014: 2b00 cmp r3, #0 + 8002016: bf14 ite ne + 8002018: 2301 movne r3, #1 + 800201a: 2300 moveq r3, #0 + 800201c: b2db uxtb r3, r3 + 800201e: 461a mov r2, r3 + 8002020: 683b ldr r3, [r7, #0] + 8002022: f883 2031 strb.w r2, [r3, #49] ; 0x31 + macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, + 8002026: 687b ldr r3, [r7, #4] + 8002028: 681b ldr r3, [r3, #0] + 800202a: 685b ldr r3, [r3, #4] + ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE; + 800202c: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8002030: 2b00 cmp r3, #0 + 8002032: bf14 ite ne + 8002034: 2301 movne r3, #1 + 8002036: 2300 moveq r3, #0 + 8002038: b2db uxtb r3, r3 + 800203a: 461a mov r2, r3 + macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, + 800203c: 683b ldr r3, [r7, #0] + 800203e: f883 2030 strb.w r2, [r3, #48] ; 0x30 + macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) + 8002042: 687b ldr r3, [r7, #4] + 8002044: 681b ldr r3, [r3, #0] + 8002046: 685b ldr r3, [r3, #4] + 8002048: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + ? ENABLE : DISABLE; + 800204c: 2b00 cmp r3, #0 + 800204e: bf14 ite ne + 8002050: 2301 movne r3, #1 + 8002052: 2300 moveq r3, #0 + 8002054: b2db uxtb r3, r3 + 8002056: 461a mov r2, r3 + macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) + 8002058: 683b ldr r3, [r7, #0] + 800205a: f883 2038 strb.w r2, [r3, #56] ; 0x38 + macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25; + 800205e: 687b ldr r3, [r7, #4] + 8002060: 681b ldr r3, [r3, #0] + 8002062: 685b ldr r3, [r3, #4] + 8002064: 0e5b lsrs r3, r3, #25 + 8002066: f003 021f and.w r2, r3, #31 + 800206a: 683b ldr r3, [r7, #0] + 800206c: 63da str r2, [r3, #60] ; 0x3c + + + macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE; + 800206e: 687b ldr r3, [r7, #4] + 8002070: 681b ldr r3, [r3, #0] + 8002072: 68db ldr r3, [r3, #12] + 8002074: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002078: 2b00 cmp r3, #0 + 800207a: bf14 ite ne + 800207c: 2301 movne r3, #1 + 800207e: 2300 moveq r3, #0 + 8002080: b2db uxtb r3, r3 + 8002082: 461a mov r2, r3 + 8002084: 683b ldr r3, [r7, #0] + 8002086: f883 2040 strb.w r2, [r3, #64] ; 0x40 + macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO); + 800208a: 687b ldr r3, [r7, #4] + 800208c: 681b ldr r3, [r3, #0] + 800208e: 68db ldr r3, [r3, #12] + 8002090: f003 020f and.w r2, r3, #15 + 8002094: 683b ldr r3, [r7, #0] + 8002096: 645a str r2, [r3, #68] ; 0x44 + + macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE; + 8002098: 687b ldr r3, [r7, #4] + 800209a: 681b ldr r3, [r3, #0] + 800209c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800209e: f003 0302 and.w r3, r3, #2 + 80020a2: 2b00 cmp r3, #0 + 80020a4: bf14 ite ne + 80020a6: 2301 movne r3, #1 + 80020a8: 2300 moveq r3, #0 + 80020aa: b2db uxtb r3, r3 + 80020ac: 461a mov r2, r3 + 80020ae: 683b ldr r3, [r7, #0] + 80020b0: f883 2054 strb.w r2, [r3, #84] ; 0x54 + macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE; + 80020b4: 687b ldr r3, [r7, #4] + 80020b6: 681b ldr r3, [r3, #0] + 80020b8: 6f1b ldr r3, [r3, #112] ; 0x70 + 80020ba: f003 0380 and.w r3, r3, #128 ; 0x80 + 80020be: 2b00 cmp r3, #0 + 80020c0: bf0c ite eq + 80020c2: 2301 moveq r3, #1 + 80020c4: 2300 movne r3, #0 + 80020c6: b2db uxtb r3, r3 + 80020c8: 461a mov r2, r3 + 80020ca: 683b ldr r3, [r7, #0] + 80020cc: f883 204c strb.w r2, [r3, #76] ; 0x4c + macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT); + 80020d0: 687b ldr r3, [r7, #4] + 80020d2: 681b ldr r3, [r3, #0] + 80020d4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80020d6: f003 0270 and.w r2, r3, #112 ; 0x70 + 80020da: 683b ldr r3, [r7, #0] + 80020dc: 651a str r2, [r3, #80] ; 0x50 + macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16); + 80020de: 687b ldr r3, [r7, #4] + 80020e0: 681b ldr r3, [r3, #0] + 80020e2: 6f1b ldr r3, [r3, #112] ; 0x70 + 80020e4: 0c1b lsrs r3, r3, #16 + 80020e6: b29a uxth r2, r3 + 80020e8: 683b ldr r3, [r7, #0] + 80020ea: 649a str r2, [r3, #72] ; 0x48 + + + macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE; + 80020ec: 687b ldr r3, [r7, #4] + 80020ee: 681b ldr r3, [r3, #0] + 80020f0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80020f4: f003 0301 and.w r3, r3, #1 + 80020f8: 2b00 cmp r3, #0 + 80020fa: bf14 ite ne + 80020fc: 2301 movne r3, #1 + 80020fe: 2300 moveq r3, #0 + 8002100: b2db uxtb r3, r3 + 8002102: 461a mov r2, r3 + 8002104: 683b ldr r3, [r7, #0] + 8002106: f883 2056 strb.w r2, [r3, #86] ; 0x56 + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) + 800210a: 687b ldr r3, [r7, #4] + 800210c: 681b ldr r3, [r3, #0] + 800210e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002112: f003 0302 and.w r3, r3, #2 + ? ENABLE : DISABLE; + 8002116: 2b00 cmp r3, #0 + 8002118: bf14 ite ne + 800211a: 2301 movne r3, #1 + 800211c: 2300 moveq r3, #0 + 800211e: b2db uxtb r3, r3 + 8002120: 461a mov r2, r3 + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) + 8002122: 683b ldr r3, [r7, #0] + 8002124: f883 2055 strb.w r2, [r3, #85] ; 0x55 + + macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF)); + 8002128: 687b ldr r3, [r7, #4] + 800212a: 681b ldr r3, [r3, #0] + 800212c: f8d3 3d00 ldr.w r3, [r3, #3328] ; 0xd00 + 8002130: f003 0272 and.w r2, r3, #114 ; 0x72 + 8002134: 683b ldr r3, [r7, #0] + 8002136: 659a str r2, [r3, #88] ; 0x58 + + macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF)); + 8002138: 687b ldr r3, [r7, #4] + 800213a: 681b ldr r3, [r3, #0] + 800213c: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 + 8002140: f003 0223 and.w r2, r3, #35 ; 0x23 + 8002144: 683b ldr r3, [r7, #0] + 8002146: 65da str r2, [r3, #92] ; 0x5c + macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + 8002148: 687b ldr r3, [r7, #4] + 800214a: 681b ldr r3, [r3, #0] + 800214c: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 + ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE; + 8002150: f003 0308 and.w r3, r3, #8 + 8002154: 2b00 cmp r3, #0 + 8002156: bf14 ite ne + 8002158: 2301 movne r3, #1 + 800215a: 2300 moveq r3, #0 + 800215c: b2db uxtb r3, r3 + 800215e: 461a mov r2, r3 + macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + 8002160: 683b ldr r3, [r7, #0] + 8002162: f883 2062 strb.w r2, [r3, #98] ; 0x62 + macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE; + 8002166: 687b ldr r3, [r7, #4] + 8002168: 681b ldr r3, [r3, #0] + 800216a: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 + 800216e: f003 0310 and.w r3, r3, #16 + 8002172: 2b00 cmp r3, #0 + 8002174: bf14 ite ne + 8002176: 2301 movne r3, #1 + 8002178: 2300 moveq r3, #0 + 800217a: b2db uxtb r3, r3 + 800217c: 461a mov r2, r3 + 800217e: 683b ldr r3, [r7, #0] + 8002180: f883 2061 strb.w r2, [r3, #97] ; 0x61 + macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + 8002184: 687b ldr r3, [r7, #4] + 8002186: 681b ldr r3, [r3, #0] + 8002188: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 + ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE; + 800218c: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002190: 2b00 cmp r3, #0 + 8002192: bf0c ite eq + 8002194: 2301 moveq r3, #1 + 8002196: 2300 movne r3, #0 + 8002198: b2db uxtb r3, r3 + 800219a: 461a mov r2, r3 + macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + 800219c: 683b ldr r3, [r7, #0] + 800219e: f883 2060 strb.w r2, [r3, #96] ; 0x60 + + return HAL_OK; + 80021a2: 2300 movs r3, #0 +} + 80021a4: 4618 mov r0, r3 + 80021a6: 370c adds r7, #12 + 80021a8: 46bd mov sp, r7 + 80021aa: f85d 7b04 ldr.w r7, [sp], #4 + 80021ae: 4770 bx lr + +080021b0 : + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains + * the configuration of the MAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + 80021b0: b580 push {r7, lr} + 80021b2: b082 sub sp, #8 + 80021b4: af00 add r7, sp, #0 + 80021b6: 6078 str r0, [r7, #4] + 80021b8: 6039 str r1, [r7, #0] + if (macconf == NULL) + 80021ba: 683b ldr r3, [r7, #0] + 80021bc: 2b00 cmp r3, #0 + 80021be: d101 bne.n 80021c4 + { + return HAL_ERROR; + 80021c0: 2301 movs r3, #1 + 80021c2: e00b b.n 80021dc + } + + if (heth->gState == HAL_ETH_STATE_READY) + 80021c4: 687b ldr r3, [r7, #4] + 80021c6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80021ca: 2b10 cmp r3, #16 + 80021cc: d105 bne.n 80021da + { + ETH_SetMACConfig(heth, macconf); + 80021ce: 6839 ldr r1, [r7, #0] + 80021d0: 6878 ldr r0, [r7, #4] + 80021d2: f000 f85f bl 8002294 + + return HAL_OK; + 80021d6: 2300 movs r3, #0 + 80021d8: e000 b.n 80021dc + } + else + { + return HAL_ERROR; + 80021da: 2301 movs r3, #1 + } +} + 80021dc: 4618 mov r0, r3 + 80021de: 3708 adds r7, #8 + 80021e0: 46bd mov sp, r7 + 80021e2: bd80 pop {r7, pc} + +080021e4 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) +{ + 80021e4: b580 push {r7, lr} + 80021e6: b084 sub sp, #16 + 80021e8: af00 add r7, sp, #0 + 80021ea: 6078 str r0, [r7, #4] + uint32_t hclk; + uint32_t tmpreg; + + /* Get the ETHERNET MACMDIOAR value */ + tmpreg = (heth->Instance)->MACMDIOAR; + 80021ec: 687b ldr r3, [r7, #4] + 80021ee: 681b ldr r3, [r3, #0] + 80021f0: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200 + 80021f4: 60fb str r3, [r7, #12] + + /* Clear CSR Clock Range bits */ + tmpreg &= ~ETH_MACMDIOAR_CR; + 80021f6: 68fb ldr r3, [r7, #12] + 80021f8: f423 6370 bic.w r3, r3, #3840 ; 0xf00 + 80021fc: 60fb str r3, [r7, #12] + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + 80021fe: f001 fea9 bl 8003f54 + 8002202: 60b8 str r0, [r7, #8] + + /* Set CR bits depending on hclk value */ + if ((hclk >= 20000000U) && (hclk < 35000000U)) + 8002204: 68bb ldr r3, [r7, #8] + 8002206: 4a1e ldr r2, [pc, #120] ; (8002280 ) + 8002208: 4293 cmp r3, r2 + 800220a: d908 bls.n 800221e + 800220c: 68bb ldr r3, [r7, #8] + 800220e: 4a1d ldr r2, [pc, #116] ; (8002284 ) + 8002210: 4293 cmp r3, r2 + 8002212: d804 bhi.n 800221e + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16; + 8002214: 68fb ldr r3, [r7, #12] + 8002216: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800221a: 60fb str r3, [r7, #12] + 800221c: e027 b.n 800226e + } + else if ((hclk >= 35000000U) && (hclk < 60000000U)) + 800221e: 68bb ldr r3, [r7, #8] + 8002220: 4a18 ldr r2, [pc, #96] ; (8002284 ) + 8002222: 4293 cmp r3, r2 + 8002224: d908 bls.n 8002238 + 8002226: 68bb ldr r3, [r7, #8] + 8002228: 4a17 ldr r2, [pc, #92] ; (8002288 ) + 800222a: 4293 cmp r3, r2 + 800222c: d204 bcs.n 8002238 + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26; + 800222e: 68fb ldr r3, [r7, #12] + 8002230: f443 7340 orr.w r3, r3, #768 ; 0x300 + 8002234: 60fb str r3, [r7, #12] + 8002236: e01a b.n 800226e + } + else if ((hclk >= 60000000U) && (hclk < 100000000U)) + 8002238: 68bb ldr r3, [r7, #8] + 800223a: 4a13 ldr r2, [pc, #76] ; (8002288 ) + 800223c: 4293 cmp r3, r2 + 800223e: d303 bcc.n 8002248 + 8002240: 68bb ldr r3, [r7, #8] + 8002242: 4a12 ldr r2, [pc, #72] ; (800228c ) + 8002244: 4293 cmp r3, r2 + 8002246: d911 bls.n 800226c + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; + } + else if ((hclk >= 100000000U) && (hclk < 150000000U)) + 8002248: 68bb ldr r3, [r7, #8] + 800224a: 4a10 ldr r2, [pc, #64] ; (800228c ) + 800224c: 4293 cmp r3, r2 + 800224e: d908 bls.n 8002262 + 8002250: 68bb ldr r3, [r7, #8] + 8002252: 4a0f ldr r2, [pc, #60] ; (8002290 ) + 8002254: 4293 cmp r3, r2 + 8002256: d804 bhi.n 8002262 + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62; + 8002258: 68fb ldr r3, [r7, #12] + 800225a: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800225e: 60fb str r3, [r7, #12] + 8002260: e005 b.n 800226e + } + else /* (hclk >= 150000000)&&(hclk <= 200000000) */ + { + /* CSR Clock Range between 150-200 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102; + 8002262: 68fb ldr r3, [r7, #12] + 8002264: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8002268: 60fb str r3, [r7, #12] + 800226a: e000 b.n 800226e + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; + 800226c: bf00 nop + } + + /* Configure the CSR Clock Range */ + (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg; + 800226e: 687b ldr r3, [r7, #4] + 8002270: 681b ldr r3, [r3, #0] + 8002272: 68fa ldr r2, [r7, #12] + 8002274: f8c3 2200 str.w r2, [r3, #512] ; 0x200 +} + 8002278: bf00 nop + 800227a: 3710 adds r7, #16 + 800227c: 46bd mov sp, r7 + 800227e: bd80 pop {r7, pc} + 8002280: 01312cff .word 0x01312cff + 8002284: 02160ebf .word 0x02160ebf + 8002288: 03938700 .word 0x03938700 + 800228c: 05f5e0ff .word 0x05f5e0ff + 8002290: 08f0d17f .word 0x08f0d17f + +08002294 : + * @{ + */ + + +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + 8002294: b480 push {r7} + 8002296: b085 sub sp, #20 + 8002298: af00 add r7, sp, #0 + 800229a: 6078 str r0, [r7, #4] + 800229c: 6039 str r1, [r7, #0] + uint32_t macregval; + + /*------------------------ MACCR Configuration --------------------*/ + macregval = (macconf->InterPacketGapVal | + 800229e: 683b ldr r3, [r7, #0] + 80022a0: 689a ldr r2, [r3, #8] + macconf->SourceAddrControl | + 80022a2: 683b ldr r3, [r7, #0] + 80022a4: 681b ldr r3, [r3, #0] + macregval = (macconf->InterPacketGapVal | + 80022a6: 431a orrs r2, r3 + ((uint32_t)macconf->ChecksumOffload << 27) | + 80022a8: 683b ldr r3, [r7, #0] + 80022aa: 791b ldrb r3, [r3, #4] + 80022ac: 06db lsls r3, r3, #27 + macconf->SourceAddrControl | + 80022ae: 431a orrs r2, r3 + ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | + 80022b0: 683b ldr r3, [r7, #0] + 80022b2: 7b1b ldrb r3, [r3, #12] + 80022b4: 05db lsls r3, r3, #23 + ((uint32_t)macconf->ChecksumOffload << 27) | + 80022b6: 431a orrs r2, r3 + ((uint32_t)macconf->Support2KPacket << 22) | + 80022b8: 683b ldr r3, [r7, #0] + 80022ba: 7b5b ldrb r3, [r3, #13] + 80022bc: 059b lsls r3, r3, #22 + ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | + 80022be: 431a orrs r2, r3 + ((uint32_t)macconf->CRCStripTypePacket << 21) | + 80022c0: 683b ldr r3, [r7, #0] + 80022c2: 7b9b ldrb r3, [r3, #14] + 80022c4: 055b lsls r3, r3, #21 + ((uint32_t)macconf->Support2KPacket << 22) | + 80022c6: 431a orrs r2, r3 + ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | + 80022c8: 683b ldr r3, [r7, #0] + 80022ca: 7bdb ldrb r3, [r3, #15] + 80022cc: 051b lsls r3, r3, #20 + ((uint32_t)macconf->CRCStripTypePacket << 21) | + 80022ce: 4313 orrs r3, r2 + ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | + 80022d0: 683a ldr r2, [r7, #0] + 80022d2: 7c12 ldrb r2, [r2, #16] + 80022d4: 2a00 cmp r2, #0 + 80022d6: d102 bne.n 80022de + 80022d8: f44f 2200 mov.w r2, #524288 ; 0x80000 + 80022dc: e000 b.n 80022e0 + 80022de: 2200 movs r2, #0 + ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | + 80022e0: 4313 orrs r3, r2 + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | + 80022e2: 683a ldr r2, [r7, #0] + 80022e4: 7c52 ldrb r2, [r2, #17] + 80022e6: 2a00 cmp r2, #0 + 80022e8: d102 bne.n 80022f0 + 80022ea: f44f 3200 mov.w r2, #131072 ; 0x20000 + 80022ee: e000 b.n 80022f2 + 80022f0: 2200 movs r2, #0 + ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | + 80022f2: 431a orrs r2, r3 + ((uint32_t)macconf->JumboPacket << 16) | + 80022f4: 683b ldr r3, [r7, #0] + 80022f6: 7c9b ldrb r3, [r3, #18] + 80022f8: 041b lsls r3, r3, #16 + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | + 80022fa: 431a orrs r2, r3 + macconf->Speed | + 80022fc: 683b ldr r3, [r7, #0] + 80022fe: 695b ldr r3, [r3, #20] + ((uint32_t)macconf->JumboPacket << 16) | + 8002300: 431a orrs r2, r3 + macconf->DuplexMode | + 8002302: 683b ldr r3, [r7, #0] + 8002304: 699b ldr r3, [r3, #24] + macconf->Speed | + 8002306: 431a orrs r2, r3 + ((uint32_t)macconf->LoopbackMode << 12) | + 8002308: 683b ldr r3, [r7, #0] + 800230a: 7f1b ldrb r3, [r3, #28] + 800230c: 031b lsls r3, r3, #12 + macconf->DuplexMode | + 800230e: 431a orrs r2, r3 + ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | + 8002310: 683b ldr r3, [r7, #0] + 8002312: 7f5b ldrb r3, [r3, #29] + 8002314: 02db lsls r3, r3, #11 + ((uint32_t)macconf->LoopbackMode << 12) | + 8002316: 4313 orrs r3, r2 + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | + 8002318: 683a ldr r2, [r7, #0] + 800231a: 7f92 ldrb r2, [r2, #30] + 800231c: 2a00 cmp r2, #0 + 800231e: d102 bne.n 8002326 + 8002320: f44f 6280 mov.w r2, #1024 ; 0x400 + 8002324: e000 b.n 8002328 + 8002326: 2200 movs r2, #0 + ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | + 8002328: 431a orrs r2, r3 + ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) | + 800232a: 683b ldr r3, [r7, #0] + 800232c: 7fdb ldrb r3, [r3, #31] + 800232e: 025b lsls r3, r3, #9 + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | + 8002330: 4313 orrs r3, r2 + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | + 8002332: 683a ldr r2, [r7, #0] + 8002334: f892 2020 ldrb.w r2, [r2, #32] + 8002338: 2a00 cmp r2, #0 + 800233a: d102 bne.n 8002342 + 800233c: f44f 7280 mov.w r2, #256 ; 0x100 + 8002340: e000 b.n 8002344 + 8002342: 2200 movs r2, #0 + ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) | + 8002344: 431a orrs r2, r3 + macconf->BackOffLimit | + 8002346: 683b ldr r3, [r7, #0] + 8002348: 6a5b ldr r3, [r3, #36] ; 0x24 + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | + 800234a: 431a orrs r2, r3 + ((uint32_t)macconf->DeferralCheck << 4) | + 800234c: 683b ldr r3, [r7, #0] + 800234e: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 8002352: 011b lsls r3, r3, #4 + macconf->BackOffLimit | + 8002354: 431a orrs r2, r3 + macconf->PreambleLength); + 8002356: 683b ldr r3, [r7, #0] + 8002358: 6adb ldr r3, [r3, #44] ; 0x2c + macregval = (macconf->InterPacketGapVal | + 800235a: 4313 orrs r3, r2 + 800235c: 60fb str r3, [r7, #12] + + /* Write to MACCR */ + MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval); + 800235e: 687b ldr r3, [r7, #4] + 8002360: 681b ldr r3, [r3, #0] + 8002362: 681a ldr r2, [r3, #0] + 8002364: 4b56 ldr r3, [pc, #344] ; (80024c0 ) + 8002366: 4013 ands r3, r2 + 8002368: 687a ldr r2, [r7, #4] + 800236a: 6812 ldr r2, [r2, #0] + 800236c: 68f9 ldr r1, [r7, #12] + 800236e: 430b orrs r3, r1 + 8002370: 6013 str r3, [r2, #0] + + /*------------------------ MACECR Configuration --------------------*/ + macregval = ((macconf->ExtendedInterPacketGapVal << 25) | + 8002372: 683b ldr r3, [r7, #0] + 8002374: 6bdb ldr r3, [r3, #60] ; 0x3c + 8002376: 065a lsls r2, r3, #25 + ((uint32_t)macconf->ExtendedInterPacketGap << 24) | + 8002378: 683b ldr r3, [r7, #0] + 800237a: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 800237e: 061b lsls r3, r3, #24 + macregval = ((macconf->ExtendedInterPacketGapVal << 25) | + 8002380: 431a orrs r2, r3 + ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | + 8002382: 683b ldr r3, [r7, #0] + 8002384: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8002388: 049b lsls r3, r3, #18 + ((uint32_t)macconf->ExtendedInterPacketGap << 24) | + 800238a: 431a orrs r2, r3 + ((uint32_t)macconf->SlowProtocolDetect << 17) | + 800238c: 683b ldr r3, [r7, #0] + 800238e: f893 3031 ldrb.w r3, [r3, #49] ; 0x31 + 8002392: 045b lsls r3, r3, #17 + ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | + 8002394: 4313 orrs r3, r2 + ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) | + 8002396: 683a ldr r2, [r7, #0] + 8002398: f892 2032 ldrb.w r2, [r2, #50] ; 0x32 + 800239c: 2a00 cmp r2, #0 + 800239e: d102 bne.n 80023a6 + 80023a0: f44f 3280 mov.w r2, #65536 ; 0x10000 + 80023a4: e000 b.n 80023a8 + 80023a6: 2200 movs r2, #0 + ((uint32_t)macconf->SlowProtocolDetect << 17) | + 80023a8: 431a orrs r2, r3 + macconf->GiantPacketSizeLimit); + 80023aa: 683b ldr r3, [r7, #0] + 80023ac: 6b5b ldr r3, [r3, #52] ; 0x34 + macregval = ((macconf->ExtendedInterPacketGapVal << 25) | + 80023ae: 4313 orrs r3, r2 + 80023b0: 60fb str r3, [r7, #12] + + /* Write to MACECR */ + MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval); + 80023b2: 687b ldr r3, [r7, #4] + 80023b4: 681b ldr r3, [r3, #0] + 80023b6: 685a ldr r2, [r3, #4] + 80023b8: 4b42 ldr r3, [pc, #264] ; (80024c4 ) + 80023ba: 4013 ands r3, r2 + 80023bc: 687a ldr r2, [r7, #4] + 80023be: 6812 ldr r2, [r2, #0] + 80023c0: 68f9 ldr r1, [r7, #12] + 80023c2: 430b orrs r3, r1 + 80023c4: 6053 str r3, [r2, #4] + + /*------------------------ MACWTR Configuration --------------------*/ + macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) | + 80023c6: 683b ldr r3, [r7, #0] + 80023c8: f893 3040 ldrb.w r3, [r3, #64] ; 0x40 + 80023cc: 021a lsls r2, r3, #8 + macconf->WatchdogTimeout); + 80023ce: 683b ldr r3, [r7, #0] + 80023d0: 6c5b ldr r3, [r3, #68] ; 0x44 + macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) | + 80023d2: 4313 orrs r3, r2 + 80023d4: 60fb str r3, [r7, #12] + + /* Write to MACWTR */ + MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval); + 80023d6: 687b ldr r3, [r7, #4] + 80023d8: 681b ldr r3, [r3, #0] + 80023da: 68da ldr r2, [r3, #12] + 80023dc: 4b3a ldr r3, [pc, #232] ; (80024c8 ) + 80023de: 4013 ands r3, r2 + 80023e0: 687a ldr r2, [r7, #4] + 80023e2: 6812 ldr r2, [r2, #0] + 80023e4: 68f9 ldr r1, [r7, #12] + 80023e6: 430b orrs r3, r1 + 80023e8: 60d3 str r3, [r2, #12] + + /*------------------------ MACTFCR Configuration --------------------*/ + macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | + 80023ea: 683b ldr r3, [r7, #0] + 80023ec: f893 3054 ldrb.w r3, [r3, #84] ; 0x54 + 80023f0: 005a lsls r2, r3, #1 + macconf->PauseLowThreshold | + 80023f2: 683b ldr r3, [r7, #0] + 80023f4: 6d1b ldr r3, [r3, #80] ; 0x50 + macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | + 80023f6: 4313 orrs r3, r2 + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) | + 80023f8: 683a ldr r2, [r7, #0] + 80023fa: f892 204c ldrb.w r2, [r2, #76] ; 0x4c + 80023fe: 2a00 cmp r2, #0 + 8002400: d101 bne.n 8002406 + 8002402: 2280 movs r2, #128 ; 0x80 + 8002404: e000 b.n 8002408 + 8002406: 2200 movs r2, #0 + macconf->PauseLowThreshold | + 8002408: 431a orrs r2, r3 + (macconf->PauseTime << 16)); + 800240a: 683b ldr r3, [r7, #0] + 800240c: 6c9b ldr r3, [r3, #72] ; 0x48 + 800240e: 041b lsls r3, r3, #16 + macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | + 8002410: 4313 orrs r3, r2 + 8002412: 60fb str r3, [r7, #12] + + /* Write to MACTFCR */ + MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval); + 8002414: 687b ldr r3, [r7, #4] + 8002416: 681b ldr r3, [r3, #0] + 8002418: 6f1a ldr r2, [r3, #112] ; 0x70 + 800241a: f64f 730d movw r3, #65293 ; 0xff0d + 800241e: 4013 ands r3, r2 + 8002420: 687a ldr r2, [r7, #4] + 8002422: 6812 ldr r2, [r2, #0] + 8002424: 68f9 ldr r1, [r7, #12] + 8002426: 430b orrs r3, r1 + 8002428: 6713 str r3, [r2, #112] ; 0x70 + + /*------------------------ MACRFCR Configuration --------------------*/ + macregval = ((uint32_t)macconf->ReceiveFlowControl | + 800242a: 683b ldr r3, [r7, #0] + 800242c: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 8002430: 461a mov r2, r3 + ((uint32_t)macconf->UnicastPausePacketDetect << 1)); + 8002432: 683b ldr r3, [r7, #0] + 8002434: f893 3055 ldrb.w r3, [r3, #85] ; 0x55 + 8002438: 005b lsls r3, r3, #1 + macregval = ((uint32_t)macconf->ReceiveFlowControl | + 800243a: 4313 orrs r3, r2 + 800243c: 60fb str r3, [r7, #12] + + /* Write to MACRFCR */ + MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval); + 800243e: 687b ldr r3, [r7, #4] + 8002440: 681b ldr r3, [r3, #0] + 8002442: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8002446: f023 0103 bic.w r1, r3, #3 + 800244a: 687b ldr r3, [r7, #4] + 800244c: 681b ldr r3, [r3, #0] + 800244e: 68fa ldr r2, [r7, #12] + 8002450: 430a orrs r2, r1 + 8002452: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + + /*------------------------ MTLTQOMR Configuration --------------------*/ + /* Write to MTLTQOMR */ + MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode); + 8002456: 687b ldr r3, [r7, #4] + 8002458: 681b ldr r3, [r3, #0] + 800245a: f8d3 3d00 ldr.w r3, [r3, #3328] ; 0xd00 + 800245e: f023 0172 bic.w r1, r3, #114 ; 0x72 + 8002462: 683b ldr r3, [r7, #0] + 8002464: 6d9a ldr r2, [r3, #88] ; 0x58 + 8002466: 687b ldr r3, [r7, #4] + 8002468: 681b ldr r3, [r3, #0] + 800246a: 430a orrs r2, r1 + 800246c: f8c3 2d00 str.w r2, [r3, #3328] ; 0xd00 + + /*------------------------ MTLRQOMR Configuration --------------------*/ + macregval = (macconf->ReceiveQueueMode | + 8002470: 683b ldr r3, [r7, #0] + 8002472: 6ddb ldr r3, [r3, #92] ; 0x5c + ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | + 8002474: 683a ldr r2, [r7, #0] + 8002476: f892 2060 ldrb.w r2, [r2, #96] ; 0x60 + 800247a: 2a00 cmp r2, #0 + 800247c: d101 bne.n 8002482 + 800247e: 2240 movs r2, #64 ; 0x40 + 8002480: e000 b.n 8002484 + 8002482: 2200 movs r2, #0 + macregval = (macconf->ReceiveQueueMode | + 8002484: 431a orrs r2, r3 + ((uint32_t)macconf->ForwardRxErrorPacket << 4) | + 8002486: 683b ldr r3, [r7, #0] + 8002488: f893 3061 ldrb.w r3, [r3, #97] ; 0x61 + 800248c: 011b lsls r3, r3, #4 + ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | + 800248e: 431a orrs r2, r3 + ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3)); + 8002490: 683b ldr r3, [r7, #0] + 8002492: f893 3062 ldrb.w r3, [r3, #98] ; 0x62 + 8002496: 00db lsls r3, r3, #3 + macregval = (macconf->ReceiveQueueMode | + 8002498: 4313 orrs r3, r2 + 800249a: 60fb str r3, [r7, #12] + + /* Write to MTLRQOMR */ + MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval); + 800249c: 687b ldr r3, [r7, #4] + 800249e: 681b ldr r3, [r3, #0] + 80024a0: f8d3 3d30 ldr.w r3, [r3, #3376] ; 0xd30 + 80024a4: f023 017b bic.w r1, r3, #123 ; 0x7b + 80024a8: 687b ldr r3, [r7, #4] + 80024aa: 681b ldr r3, [r3, #0] + 80024ac: 68fa ldr r2, [r7, #12] + 80024ae: 430a orrs r2, r1 + 80024b0: f8c3 2d30 str.w r2, [r3, #3376] ; 0xd30 +} + 80024b4: bf00 nop + 80024b6: 3714 adds r7, #20 + 80024b8: 46bd mov sp, r7 + 80024ba: f85d 7b04 ldr.w r7, [sp], #4 + 80024be: 4770 bx lr + 80024c0: 00048083 .word 0x00048083 + 80024c4: c0f88000 .word 0xc0f88000 + 80024c8: fffffef0 .word 0xfffffef0 + +080024cc : + +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + 80024cc: b480 push {r7} + 80024ce: b085 sub sp, #20 + 80024d0: af00 add r7, sp, #0 + 80024d2: 6078 str r0, [r7, #4] + 80024d4: 6039 str r1, [r7, #0] + uint32_t dmaregval; + + /*------------------------ DMAMR Configuration --------------------*/ + MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration); + 80024d6: 687b ldr r3, [r7, #4] + 80024d8: 681b ldr r3, [r3, #0] + 80024da: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80024de: 681a ldr r2, [r3, #0] + 80024e0: 4b38 ldr r3, [pc, #224] ; (80025c4 ) + 80024e2: 4013 ands r3, r2 + 80024e4: 683a ldr r2, [r7, #0] + 80024e6: 6811 ldr r1, [r2, #0] + 80024e8: 687a ldr r2, [r7, #4] + 80024ea: 6812 ldr r2, [r2, #0] + 80024ec: 430b orrs r3, r1 + 80024ee: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80024f2: 6013 str r3, [r2, #0] + + /*------------------------ DMASBMR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | + 80024f4: 683b ldr r3, [r7, #0] + 80024f6: 791b ldrb r3, [r3, #4] + 80024f8: 031a lsls r2, r3, #12 + dmaconf->BurstMode | + 80024fa: 683b ldr r3, [r7, #0] + 80024fc: 689b ldr r3, [r3, #8] + dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | + 80024fe: 431a orrs r2, r3 + ((uint32_t)dmaconf->RebuildINCRxBurst << 15)); + 8002500: 683b ldr r3, [r7, #0] + 8002502: 7b1b ldrb r3, [r3, #12] + 8002504: 03db lsls r3, r3, #15 + dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | + 8002506: 4313 orrs r3, r2 + 8002508: 60fb str r3, [r7, #12] + + MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval); + 800250a: 687b ldr r3, [r7, #4] + 800250c: 681b ldr r3, [r3, #0] + 800250e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8002512: 685a ldr r2, [r3, #4] + 8002514: 4b2c ldr r3, [pc, #176] ; (80025c8 ) + 8002516: 4013 ands r3, r2 + 8002518: 687a ldr r2, [r7, #4] + 800251a: 6812 ldr r2, [r2, #0] + 800251c: 68f9 ldr r1, [r7, #12] + 800251e: 430b orrs r3, r1 + 8002520: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8002524: 6053 str r3, [r2, #4] + + /*------------------------ DMACCR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) | + 8002526: 683b ldr r3, [r7, #0] + 8002528: 7b5b ldrb r3, [r3, #13] + 800252a: 041a lsls r2, r3, #16 + dmaconf->MaximumSegmentSize); + 800252c: 683b ldr r3, [r7, #0] + 800252e: 6a1b ldr r3, [r3, #32] + dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) | + 8002530: 4313 orrs r3, r2 + 8002532: 60fb str r3, [r7, #12] + + MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval); + 8002534: 687b ldr r3, [r7, #4] + 8002536: 681b ldr r3, [r3, #0] + 8002538: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800253c: f8d3 2100 ldr.w r2, [r3, #256] ; 0x100 + 8002540: 4b22 ldr r3, [pc, #136] ; (80025cc ) + 8002542: 4013 ands r3, r2 + 8002544: 687a ldr r2, [r7, #4] + 8002546: 6812 ldr r2, [r2, #0] + 8002548: 68f9 ldr r1, [r7, #12] + 800254a: 430b orrs r3, r1 + 800254c: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8002550: f8c2 3100 str.w r3, [r2, #256] ; 0x100 + + /*------------------------ DMACTCR Configuration --------------------*/ + dmaregval = (dmaconf->TxDMABurstLength | + 8002554: 683b ldr r3, [r7, #0] + 8002556: 691a ldr r2, [r3, #16] + ((uint32_t)dmaconf->SecondPacketOperate << 4) | + 8002558: 683b ldr r3, [r7, #0] + 800255a: 7d1b ldrb r3, [r3, #20] + 800255c: 011b lsls r3, r3, #4 + dmaregval = (dmaconf->TxDMABurstLength | + 800255e: 431a orrs r2, r3 + ((uint32_t)dmaconf->TCPSegmentation << 12)); + 8002560: 683b ldr r3, [r7, #0] + 8002562: 7f5b ldrb r3, [r3, #29] + 8002564: 031b lsls r3, r3, #12 + dmaregval = (dmaconf->TxDMABurstLength | + 8002566: 4313 orrs r3, r2 + 8002568: 60fb str r3, [r7, #12] + + MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval); + 800256a: 687b ldr r3, [r7, #4] + 800256c: 681b ldr r3, [r3, #0] + 800256e: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8002572: f8d3 2104 ldr.w r2, [r3, #260] ; 0x104 + 8002576: 4b16 ldr r3, [pc, #88] ; (80025d0 ) + 8002578: 4013 ands r3, r2 + 800257a: 687a ldr r2, [r7, #4] + 800257c: 6812 ldr r2, [r2, #0] + 800257e: 68f9 ldr r1, [r7, #12] + 8002580: 430b orrs r3, r1 + 8002582: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 8002586: f8c2 3104 str.w r3, [r2, #260] ; 0x104 + + /*------------------------ DMACRCR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) | + 800258a: 683b ldr r3, [r7, #0] + 800258c: 7f1b ldrb r3, [r3, #28] + 800258e: 07da lsls r2, r3, #31 + dmaconf->RxDMABurstLength); + 8002590: 683b ldr r3, [r7, #0] + 8002592: 699b ldr r3, [r3, #24] + dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) | + 8002594: 4313 orrs r3, r2 + 8002596: 60fb str r3, [r7, #12] + + /* Write to DMACRCR */ + MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval); + 8002598: 687b ldr r3, [r7, #4] + 800259a: 681b ldr r3, [r3, #0] + 800259c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 80025a0: f8d3 2108 ldr.w r2, [r3, #264] ; 0x108 + 80025a4: 4b0b ldr r3, [pc, #44] ; (80025d4 ) + 80025a6: 4013 ands r3, r2 + 80025a8: 687a ldr r2, [r7, #4] + 80025aa: 6812 ldr r2, [r2, #0] + 80025ac: 68f9 ldr r1, [r7, #12] + 80025ae: 430b orrs r3, r1 + 80025b0: f502 5280 add.w r2, r2, #4096 ; 0x1000 + 80025b4: f8c2 3108 str.w r3, [r2, #264] ; 0x108 +} + 80025b8: bf00 nop + 80025ba: 3714 adds r7, #20 + 80025bc: 46bd mov sp, r7 + 80025be: f85d 7b04 ldr.w r7, [sp], #4 + 80025c2: 4770 bx lr + 80025c4: ffff87fd .word 0xffff87fd + 80025c8: ffff2ffe .word 0xffff2ffe + 80025cc: fffec000 .word 0xfffec000 + 80025d0: ffc0efef .word 0xffc0efef + 80025d4: 7fc0ffff .word 0x7fc0ffff + +080025d8 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) +{ + 80025d8: b580 push {r7, lr} + 80025da: b0a4 sub sp, #144 ; 0x90 + 80025dc: af00 add r7, sp, #0 + 80025de: 6078 str r0, [r7, #4] + ETH_MACConfigTypeDef macDefaultConf; + ETH_DMAConfigTypeDef dmaDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + macDefaultConf.AutomaticPadCRCStrip = ENABLE; + 80025e0: 2301 movs r3, #1 + 80025e2: f887 303b strb.w r3, [r7, #59] ; 0x3b + macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; + 80025e6: 2300 movs r3, #0 + 80025e8: 653b str r3, [r7, #80] ; 0x50 + macDefaultConf.CarrierSenseBeforeTransmit = DISABLE; + 80025ea: 2300 movs r3, #0 + 80025ec: f887 3049 strb.w r3, [r7, #73] ; 0x49 + macDefaultConf.CarrierSenseDuringTransmit = DISABLE; + 80025f0: 2300 movs r3, #0 + 80025f2: f887 304b strb.w r3, [r7, #75] ; 0x4b + macDefaultConf.ChecksumOffload = ENABLE; + 80025f6: 2301 movs r3, #1 + 80025f8: f887 3030 strb.w r3, [r7, #48] ; 0x30 + macDefaultConf.CRCCheckingRxPackets = ENABLE; + 80025fc: 2301 movs r3, #1 + 80025fe: f887 305e strb.w r3, [r7, #94] ; 0x5e + macDefaultConf.CRCStripTypePacket = ENABLE; + 8002602: 2301 movs r3, #1 + 8002604: f887 303a strb.w r3, [r7, #58] ; 0x3a + macDefaultConf.DeferralCheck = DISABLE; + 8002608: 2300 movs r3, #0 + 800260a: f887 3054 strb.w r3, [r7, #84] ; 0x54 + macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE; + 800260e: 2301 movs r3, #1 + 8002610: f887 308c strb.w r3, [r7, #140] ; 0x8c + macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; + 8002614: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8002618: 647b str r3, [r7, #68] ; 0x44 + macDefaultConf.ExtendedInterPacketGap = DISABLE; + 800261a: 2300 movs r3, #0 + 800261c: f887 3064 strb.w r3, [r7, #100] ; 0x64 + macDefaultConf.ExtendedInterPacketGapVal = 0x0; + 8002620: 2300 movs r3, #0 + 8002622: 66bb str r3, [r7, #104] ; 0x68 + macDefaultConf.ForwardRxErrorPacket = DISABLE; + 8002624: 2300 movs r3, #0 + 8002626: f887 308d strb.w r3, [r7, #141] ; 0x8d + macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE; + 800262a: 2300 movs r3, #0 + 800262c: f887 308e strb.w r3, [r7, #142] ; 0x8e + macDefaultConf.GiantPacketSizeLimit = 0x618; + 8002630: f44f 63c3 mov.w r3, #1560 ; 0x618 + 8002634: 663b str r3, [r7, #96] ; 0x60 + macDefaultConf.GiantPacketSizeLimitControl = DISABLE; + 8002636: 2300 movs r3, #0 + 8002638: f887 3038 strb.w r3, [r7, #56] ; 0x38 + macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT; + 800263c: 2300 movs r3, #0 + 800263e: 637b str r3, [r7, #52] ; 0x34 + macDefaultConf.Jabber = ENABLE; + 8002640: 2301 movs r3, #1 + 8002642: f887 303d strb.w r3, [r7, #61] ; 0x3d + macDefaultConf.JumboPacket = DISABLE; + 8002646: 2300 movs r3, #0 + 8002648: f887 303e strb.w r3, [r7, #62] ; 0x3e + macDefaultConf.LoopbackMode = DISABLE; + 800264c: 2300 movs r3, #0 + 800264e: f887 3048 strb.w r3, [r7, #72] ; 0x48 + macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4; + 8002652: 2300 movs r3, #0 + 8002654: 67fb str r3, [r7, #124] ; 0x7c + macDefaultConf.PauseTime = 0x0; + 8002656: 2300 movs r3, #0 + 8002658: 677b str r3, [r7, #116] ; 0x74 + macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7; + 800265a: 2300 movs r3, #0 + 800265c: 65bb str r3, [r7, #88] ; 0x58 + macDefaultConf.ProgrammableWatchdog = DISABLE; + 800265e: 2300 movs r3, #0 + 8002660: f887 306c strb.w r3, [r7, #108] ; 0x6c + macDefaultConf.ReceiveFlowControl = DISABLE; + 8002664: 2300 movs r3, #0 + 8002666: f887 3082 strb.w r3, [r7, #130] ; 0x82 + macDefaultConf.ReceiveOwn = ENABLE; + 800266a: 2301 movs r3, #1 + 800266c: f887 304a strb.w r3, [r7, #74] ; 0x4a + macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD; + 8002670: 2320 movs r3, #32 + 8002672: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + macDefaultConf.RetryTransmission = ENABLE; + 8002676: 2301 movs r3, #1 + 8002678: f887 304c strb.w r3, [r7, #76] ; 0x4c + macDefaultConf.SlowProtocolDetect = DISABLE; + 800267c: 2300 movs r3, #0 + 800267e: f887 305d strb.w r3, [r7, #93] ; 0x5d + macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0; + 8002682: f04f 5340 mov.w r3, #805306368 ; 0x30000000 + 8002686: 62fb str r3, [r7, #44] ; 0x2c + macDefaultConf.Speed = ETH_SPEED_100M; + 8002688: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800268c: 643b str r3, [r7, #64] ; 0x40 + macDefaultConf.Support2KPacket = DISABLE; + 800268e: 2300 movs r3, #0 + 8002690: f887 3039 strb.w r3, [r7, #57] ; 0x39 + macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD; + 8002694: 2302 movs r3, #2 + 8002696: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + macDefaultConf.TransmitFlowControl = DISABLE; + 800269a: 2300 movs r3, #0 + 800269c: f887 3080 strb.w r3, [r7, #128] ; 0x80 + macDefaultConf.UnicastPausePacketDetect = DISABLE; + 80026a0: 2300 movs r3, #0 + 80026a2: f887 3081 strb.w r3, [r7, #129] ; 0x81 + macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; + 80026a6: 2300 movs r3, #0 + 80026a8: f887 305c strb.w r3, [r7, #92] ; 0x5c + macDefaultConf.Watchdog = ENABLE; + 80026ac: 2301 movs r3, #1 + 80026ae: f887 303c strb.w r3, [r7, #60] ; 0x3c + macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB; + 80026b2: 2300 movs r3, #0 + 80026b4: 673b str r3, [r7, #112] ; 0x70 + macDefaultConf.ZeroQuantaPause = ENABLE; + 80026b6: 2301 movs r3, #1 + 80026b8: f887 3078 strb.w r3, [r7, #120] ; 0x78 + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); + 80026bc: f107 032c add.w r3, r7, #44 ; 0x2c + 80026c0: 4619 mov r1, r3 + 80026c2: 6878 ldr r0, [r7, #4] + 80026c4: f7ff fde6 bl 8002294 + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + dmaDefaultConf.AddressAlignedBeats = ENABLE; + 80026c8: 2301 movs r3, #1 + 80026ca: 733b strb r3, [r7, #12] + dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; + 80026cc: 2301 movs r3, #1 + 80026ce: 613b str r3, [r7, #16] + dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1; + 80026d0: 2300 movs r3, #0 + 80026d2: 60bb str r3, [r7, #8] + dmaDefaultConf.FlushRxPacket = DISABLE; + 80026d4: 2300 movs r3, #0 + 80026d6: f887 3024 strb.w r3, [r7, #36] ; 0x24 + dmaDefaultConf.PBLx8Mode = DISABLE; + 80026da: 2300 movs r3, #0 + 80026dc: 757b strb r3, [r7, #21] + dmaDefaultConf.RebuildINCRxBurst = DISABLE; + 80026de: 2300 movs r3, #0 + 80026e0: 753b strb r3, [r7, #20] + dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + 80026e2: f44f 1300 mov.w r3, #2097152 ; 0x200000 + 80026e6: 623b str r3, [r7, #32] + dmaDefaultConf.SecondPacketOperate = DISABLE; + 80026e8: 2300 movs r3, #0 + 80026ea: 773b strb r3, [r7, #28] + dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + 80026ec: f44f 1300 mov.w r3, #2097152 ; 0x200000 + 80026f0: 61bb str r3, [r7, #24] + dmaDefaultConf.TCPSegmentation = DISABLE; + 80026f2: 2300 movs r3, #0 + 80026f4: f887 3025 strb.w r3, [r7, #37] ; 0x25 + dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT; + 80026f8: f44f 7306 mov.w r3, #536 ; 0x218 + 80026fc: 62bb str r3, [r7, #40] ; 0x28 + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); + 80026fe: f107 0308 add.w r3, r7, #8 + 8002702: 4619 mov r1, r3 + 8002704: 6878 ldr r0, [r7, #4] + 8002706: f7ff fee1 bl 80024cc +} + 800270a: bf00 nop + 800270c: 3790 adds r7, #144 ; 0x90 + 800270e: 46bd mov sp, r7 + 8002710: bd80 pop {r7, pc} + +08002712 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) +{ + 8002712: b480 push {r7} + 8002714: b085 sub sp, #20 + 8002716: af00 add r7, sp, #0 + 8002718: 6078 str r0, [r7, #4] + ETH_DMADescTypeDef *dmatxdesc; + uint32_t i; + + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + 800271a: 2300 movs r3, #0 + 800271c: 60fb str r3, [r7, #12] + 800271e: e01d b.n 800275c + { + dmatxdesc = heth->Init.TxDesc + i; + 8002720: 687b ldr r3, [r7, #4] + 8002722: 68d9 ldr r1, [r3, #12] + 8002724: 68fa ldr r2, [r7, #12] + 8002726: 4613 mov r3, r2 + 8002728: 005b lsls r3, r3, #1 + 800272a: 4413 add r3, r2 + 800272c: 00db lsls r3, r3, #3 + 800272e: 440b add r3, r1 + 8002730: 60bb str r3, [r7, #8] + + WRITE_REG(dmatxdesc->DESC0, 0x0); + 8002732: 68bb ldr r3, [r7, #8] + 8002734: 2200 movs r2, #0 + 8002736: 601a str r2, [r3, #0] + WRITE_REG(dmatxdesc->DESC1, 0x0); + 8002738: 68bb ldr r3, [r7, #8] + 800273a: 2200 movs r2, #0 + 800273c: 605a str r2, [r3, #4] + WRITE_REG(dmatxdesc->DESC2, 0x0); + 800273e: 68bb ldr r3, [r7, #8] + 8002740: 2200 movs r2, #0 + 8002742: 609a str r2, [r3, #8] + WRITE_REG(dmatxdesc->DESC3, 0x0); + 8002744: 68bb ldr r3, [r7, #8] + 8002746: 2200 movs r2, #0 + 8002748: 60da str r2, [r3, #12] + + WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); + 800274a: 68b9 ldr r1, [r7, #8] + 800274c: 687b ldr r3, [r7, #4] + 800274e: 68fa ldr r2, [r7, #12] + 8002750: 3206 adds r2, #6 + 8002752: f843 1022 str.w r1, [r3, r2, lsl #2] + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + 8002756: 68fb ldr r3, [r7, #12] + 8002758: 3301 adds r3, #1 + 800275a: 60fb str r3, [r7, #12] + 800275c: 68fb ldr r3, [r7, #12] + 800275e: 2b03 cmp r3, #3 + 8002760: d9de bls.n 8002720 + + } + + heth->TxDescList.CurTxDesc = 0; + 8002762: 687b ldr r3, [r7, #4] + 8002764: 2200 movs r2, #0 + 8002766: 629a str r2, [r3, #40] ; 0x28 + + /* Set Transmit Descriptor Ring Length */ + WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U)); + 8002768: 687b ldr r3, [r7, #4] + 800276a: 681b ldr r3, [r3, #0] + 800276c: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8002770: 461a mov r2, r3 + 8002772: 2303 movs r3, #3 + 8002774: f8c2 312c str.w r3, [r2, #300] ; 0x12c + + /* Set Transmit Descriptor List Address */ + WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc); + 8002778: 687b ldr r3, [r7, #4] + 800277a: 68da ldr r2, [r3, #12] + 800277c: 687b ldr r3, [r7, #4] + 800277e: 681b ldr r3, [r3, #0] + 8002780: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8002784: f8c3 2114 str.w r2, [r3, #276] ; 0x114 + + /* Set Transmit Descriptor Tail pointer */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc); + 8002788: 687b ldr r3, [r7, #4] + 800278a: 68da ldr r2, [r3, #12] + 800278c: 687b ldr r3, [r7, #4] + 800278e: 681b ldr r3, [r3, #0] + 8002790: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8002794: f8c3 2120 str.w r2, [r3, #288] ; 0x120 +} + 8002798: bf00 nop + 800279a: 3714 adds r7, #20 + 800279c: 46bd mov sp, r7 + 800279e: f85d 7b04 ldr.w r7, [sp], #4 + 80027a2: 4770 bx lr + +080027a4 : + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) +{ + 80027a4: b480 push {r7} + 80027a6: b085 sub sp, #20 + 80027a8: af00 add r7, sp, #0 + 80027aa: 6078 str r0, [r7, #4] + ETH_DMADescTypeDef *dmarxdesc; + uint32_t i; + + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + 80027ac: 2300 movs r3, #0 + 80027ae: 60fb str r3, [r7, #12] + 80027b0: e023 b.n 80027fa + { + dmarxdesc = heth->Init.RxDesc + i; + 80027b2: 687b ldr r3, [r7, #4] + 80027b4: 6919 ldr r1, [r3, #16] + 80027b6: 68fa ldr r2, [r7, #12] + 80027b8: 4613 mov r3, r2 + 80027ba: 005b lsls r3, r3, #1 + 80027bc: 4413 add r3, r2 + 80027be: 00db lsls r3, r3, #3 + 80027c0: 440b add r3, r1 + 80027c2: 60bb str r3, [r7, #8] + + WRITE_REG(dmarxdesc->DESC0, 0x0); + 80027c4: 68bb ldr r3, [r7, #8] + 80027c6: 2200 movs r2, #0 + 80027c8: 601a str r2, [r3, #0] + WRITE_REG(dmarxdesc->DESC1, 0x0); + 80027ca: 68bb ldr r3, [r7, #8] + 80027cc: 2200 movs r2, #0 + 80027ce: 605a str r2, [r3, #4] + WRITE_REG(dmarxdesc->DESC2, 0x0); + 80027d0: 68bb ldr r3, [r7, #8] + 80027d2: 2200 movs r2, #0 + 80027d4: 609a str r2, [r3, #8] + WRITE_REG(dmarxdesc->DESC3, 0x0); + 80027d6: 68bb ldr r3, [r7, #8] + 80027d8: 2200 movs r2, #0 + 80027da: 60da str r2, [r3, #12] + WRITE_REG(dmarxdesc->BackupAddr0, 0x0); + 80027dc: 68bb ldr r3, [r7, #8] + 80027de: 2200 movs r2, #0 + 80027e0: 611a str r2, [r3, #16] + WRITE_REG(dmarxdesc->BackupAddr1, 0x0); + 80027e2: 68bb ldr r3, [r7, #8] + 80027e4: 2200 movs r2, #0 + 80027e6: 615a str r2, [r3, #20] + + + /* Set Rx descritors addresses */ + WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + 80027e8: 68b9 ldr r1, [r7, #8] + 80027ea: 687b ldr r3, [r7, #4] + 80027ec: 68fa ldr r2, [r7, #12] + 80027ee: 3212 adds r2, #18 + 80027f0: f843 1022 str.w r1, [r3, r2, lsl #2] + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + 80027f4: 68fb ldr r3, [r7, #12] + 80027f6: 3301 adds r3, #1 + 80027f8: 60fb str r3, [r7, #12] + 80027fa: 68fb ldr r3, [r7, #12] + 80027fc: 2b03 cmp r3, #3 + 80027fe: d9d8 bls.n 80027b2 + + } + + WRITE_REG(heth->RxDescList.RxDescIdx, 0); + 8002800: 687b ldr r3, [r7, #4] + 8002802: 2200 movs r2, #0 + 8002804: 65da str r2, [r3, #92] ; 0x5c + WRITE_REG(heth->RxDescList.RxDescCnt, 0); + 8002806: 687b ldr r3, [r7, #4] + 8002808: 2200 movs r2, #0 + 800280a: 661a str r2, [r3, #96] ; 0x60 + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); + 800280c: 687b ldr r3, [r7, #4] + 800280e: 2200 movs r2, #0 + 8002810: 669a str r2, [r3, #104] ; 0x68 + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); + 8002812: 687b ldr r3, [r7, #4] + 8002814: 2200 movs r2, #0 + 8002816: 66da str r2, [r3, #108] ; 0x6c + WRITE_REG(heth->RxDescList.ItMode, 0); + 8002818: 687b ldr r3, [r7, #4] + 800281a: 2200 movs r2, #0 + 800281c: 659a str r2, [r3, #88] ; 0x58 + + /* Set Receive Descriptor Ring Length */ + WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U))); + 800281e: 687b ldr r3, [r7, #4] + 8002820: 681b ldr r3, [r3, #0] + 8002822: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 8002826: 461a mov r2, r3 + 8002828: 2303 movs r3, #3 + 800282a: f8c2 3130 str.w r3, [r2, #304] ; 0x130 + + /* Set Receive Descriptor List Address */ + WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc); + 800282e: 687b ldr r3, [r7, #4] + 8002830: 691a ldr r2, [r3, #16] + 8002832: 687b ldr r3, [r7, #4] + 8002834: 681b ldr r3, [r3, #0] + 8002836: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800283a: f8c3 211c str.w r2, [r3, #284] ; 0x11c + + /* Set Receive Descriptor Tail pointer Address */ + WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U)))); + 800283e: 687b ldr r3, [r7, #4] + 8002840: 691b ldr r3, [r3, #16] + 8002842: f103 0248 add.w r2, r3, #72 ; 0x48 + 8002846: 687b ldr r3, [r7, #4] + 8002848: 681b ldr r3, [r3, #0] + 800284a: f503 5380 add.w r3, r3, #4096 ; 0x1000 + 800284e: f8c3 2128 str.w r2, [r3, #296] ; 0x128 +} + 8002852: bf00 nop + 8002854: 3714 adds r7, #20 + 8002856: 46bd mov sp, r7 + 8002858: f85d 7b04 ldr.w r7, [sp], #4 + 800285c: 4770 bx lr + ... + +08002860 : + * @param pTxConfig: Tx packet configuration + * @param ItMode: Enable or disable Tx EOT interrept + * @retval Status + */ +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode) +{ + 8002860: b480 push {r7} + 8002862: b08d sub sp, #52 ; 0x34 + 8002864: af00 add r7, sp, #0 + 8002866: 60f8 str r0, [r7, #12] + 8002868: 60b9 str r1, [r7, #8] + 800286a: 607a str r2, [r7, #4] + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + 800286c: 68fb ldr r3, [r7, #12] + 800286e: 3318 adds r3, #24 + 8002870: 617b str r3, [r7, #20] + uint32_t descidx = dmatxdesclist->CurTxDesc; + 8002872: 697b ldr r3, [r7, #20] + 8002874: 691b ldr r3, [r3, #16] + 8002876: 62fb str r3, [r7, #44] ; 0x2c + uint32_t firstdescidx = dmatxdesclist->CurTxDesc; + 8002878: 697b ldr r3, [r7, #20] + 800287a: 691b ldr r3, [r3, #16] + 800287c: 613b str r3, [r7, #16] + uint32_t idx; + uint32_t descnbr = 0; + 800287e: 2300 movs r3, #0 + 8002880: 627b str r3, [r7, #36] ; 0x24 + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 8002882: 697b ldr r3, [r7, #20] + 8002884: 6afa ldr r2, [r7, #44] ; 0x2c + 8002886: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800288a: 623b str r3, [r7, #32] + + ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + 800288c: 68bb ldr r3, [r7, #8] + 800288e: 689b ldr r3, [r3, #8] + 8002890: 61fb str r3, [r7, #28] + uint32_t bd_count = 0; + 8002892: 2300 movs r3, #0 + 8002894: 61bb str r3, [r7, #24] + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + 8002896: 6a3b ldr r3, [r7, #32] + 8002898: 68db ldr r3, [r3, #12] + 800289a: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 800289e: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 80028a2: d007 beq.n 80028b4 + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + 80028a4: 697a ldr r2, [r7, #20] + 80028a6: 6afb ldr r3, [r7, #44] ; 0x2c + 80028a8: 3304 adds r3, #4 + 80028aa: 009b lsls r3, r3, #2 + 80028ac: 4413 add r3, r2 + 80028ae: 685b ldr r3, [r3, #4] + 80028b0: 2b00 cmp r3, #0 + 80028b2: d001 beq.n 80028b8 + { + return HAL_ETH_ERROR_BUSY; + 80028b4: 2302 movs r3, #2 + 80028b6: e259 b.n 8002d6c + + /***************************************************************************/ + /***************** Context descriptor configuration (Optional) **********/ + /***************************************************************************/ + /* If VLAN tag is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + 80028b8: 68bb ldr r3, [r7, #8] + 80028ba: 681b ldr r3, [r3, #0] + 80028bc: f003 0304 and.w r3, r3, #4 + 80028c0: 2b00 cmp r3, #0 + 80028c2: d044 beq.n 800294e + { + /* Set vlan tag value */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag); + 80028c4: 6a3b ldr r3, [r7, #32] + 80028c6: 68da ldr r2, [r3, #12] + 80028c8: 4b75 ldr r3, [pc, #468] ; (8002aa0 ) + 80028ca: 4013 ands r3, r2 + 80028cc: 68ba ldr r2, [r7, #8] + 80028ce: 6a52 ldr r2, [r2, #36] ; 0x24 + 80028d0: 431a orrs r2, r3 + 80028d2: 6a3b ldr r3, [r7, #32] + 80028d4: 60da str r2, [r3, #12] + /* Set vlan tag valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV); + 80028d6: 6a3b ldr r3, [r7, #32] + 80028d8: 68db ldr r3, [r3, #12] + 80028da: f443 3280 orr.w r2, r3, #65536 ; 0x10000 + 80028de: 6a3b ldr r3, [r7, #32] + 80028e0: 60da str r2, [r3, #12] + /* Set the descriptor as the vlan input source */ + SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI); + 80028e2: 68fb ldr r3, [r7, #12] + 80028e4: 681b ldr r3, [r3, #0] + 80028e6: 6e1a ldr r2, [r3, #96] ; 0x60 + 80028e8: 68fb ldr r3, [r7, #12] + 80028ea: 681b ldr r3, [r3, #0] + 80028ec: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 + 80028f0: 661a str r2, [r3, #96] ; 0x60 + + /* if inner VLAN is enabled */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET) + 80028f2: 68bb ldr r3, [r7, #8] + 80028f4: 681b ldr r3, [r3, #0] + 80028f6: f003 0308 and.w r3, r3, #8 + 80028fa: 2b00 cmp r3, #0 + 80028fc: d027 beq.n 800294e + { + /* Set inner vlan tag value */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); + 80028fe: 6a3b ldr r3, [r7, #32] + 8002900: 689b ldr r3, [r3, #8] + 8002902: b29a uxth r2, r3 + 8002904: 68bb ldr r3, [r7, #8] + 8002906: 6adb ldr r3, [r3, #44] ; 0x2c + 8002908: 041b lsls r3, r3, #16 + 800290a: 431a orrs r2, r3 + 800290c: 6a3b ldr r3, [r7, #32] + 800290e: 609a str r2, [r3, #8] + /* Set inner vlan tag valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV); + 8002910: 6a3b ldr r3, [r7, #32] + 8002912: 68db ldr r3, [r3, #12] + 8002914: f443 3200 orr.w r2, r3, #131072 ; 0x20000 + 8002918: 6a3b ldr r3, [r7, #32] + 800291a: 60da str r2, [r3, #12] + + /* Set Vlan Tag control */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl); + 800291c: 6a3b ldr r3, [r7, #32] + 800291e: 68db ldr r3, [r3, #12] + 8002920: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 8002924: 68bb ldr r3, [r7, #8] + 8002926: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002928: 431a orrs r2, r3 + 800292a: 6a3b ldr r3, [r7, #32] + 800292c: 60da str r2, [r3, #12] + + /* Set the descriptor as the inner vlan input source */ + SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI); + 800292e: 68fb ldr r3, [r7, #12] + 8002930: 681b ldr r3, [r3, #0] + 8002932: 6e5a ldr r2, [r3, #100] ; 0x64 + 8002934: 68fb ldr r3, [r7, #12] + 8002936: 681b ldr r3, [r3, #0] + 8002938: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 + 800293c: 665a str r2, [r3, #100] ; 0x64 + /* Enable double VLAN processing */ + SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP); + 800293e: 68fb ldr r3, [r7, #12] + 8002940: 681b ldr r3, [r3, #0] + 8002942: 6d1a ldr r2, [r3, #80] ; 0x50 + 8002944: 68fb ldr r3, [r7, #12] + 8002946: 681b ldr r3, [r3, #0] + 8002948: f042 6280 orr.w r2, r2, #67108864 ; 0x4000000 + 800294c: 651a str r2, [r3, #80] ; 0x50 + } + } + + /* if tcp segmentation is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + 800294e: 68bb ldr r3, [r7, #8] + 8002950: 681b ldr r3, [r3, #0] + 8002952: f003 0310 and.w r3, r3, #16 + 8002956: 2b00 cmp r3, #0 + 8002958: d00e beq.n 8002978 + { + /* Set MSS value */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); + 800295a: 6a3b ldr r3, [r7, #32] + 800295c: 689a ldr r2, [r3, #8] + 800295e: 4b51 ldr r3, [pc, #324] ; (8002aa4 ) + 8002960: 4013 ands r3, r2 + 8002962: 68ba ldr r2, [r7, #8] + 8002964: 6992 ldr r2, [r2, #24] + 8002966: 431a orrs r2, r3 + 8002968: 6a3b ldr r3, [r7, #32] + 800296a: 609a str r2, [r3, #8] + /* Set MSS valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV); + 800296c: 6a3b ldr r3, [r7, #32] + 800296e: 68db ldr r3, [r3, #12] + 8002970: f043 6280 orr.w r2, r3, #67108864 ; 0x4000000 + 8002974: 6a3b ldr r3, [r7, #32] + 8002976: 60da str r2, [r3, #12] + } + + if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + 8002978: 68bb ldr r3, [r7, #8] + 800297a: 681b ldr r3, [r3, #0] + 800297c: f003 0304 and.w r3, r3, #4 + 8002980: 2b00 cmp r3, #0 + 8002982: d105 bne.n 8002990 + || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)) + 8002984: 68bb ldr r3, [r7, #8] + 8002986: 681b ldr r3, [r3, #0] + 8002988: f003 0310 and.w r3, r3, #16 + 800298c: 2b00 cmp r3, #0 + 800298e: d036 beq.n 80029fe + { + /* Set as context descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT); + 8002990: 6a3b ldr r3, [r7, #32] + 8002992: 68db ldr r3, [r3, #12] + 8002994: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000 + 8002998: 6a3b ldr r3, [r7, #32] + 800299a: 60da str r2, [r3, #12] + __ASM volatile ("dmb 0xF":::"memory"); + 800299c: f3bf 8f5f dmb sy +} + 80029a0: bf00 nop + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set own bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); + 80029a2: 6a3b ldr r3, [r7, #32] + 80029a4: 68db ldr r3, [r3, #12] + 80029a6: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 80029aa: 6a3b ldr r3, [r7, #32] + 80029ac: 60da str r2, [r3, #12] + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + 80029ae: 6afb ldr r3, [r7, #44] ; 0x2c + 80029b0: 3301 adds r3, #1 + 80029b2: 62fb str r3, [r7, #44] ; 0x2c + 80029b4: 6afb ldr r3, [r7, #44] ; 0x2c + 80029b6: 2b03 cmp r3, #3 + 80029b8: d902 bls.n 80029c0 + 80029ba: 6afb ldr r3, [r7, #44] ; 0x2c + 80029bc: 3b04 subs r3, #4 + 80029be: 62fb str r3, [r7, #44] ; 0x2c + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 80029c0: 697b ldr r3, [r7, #20] + 80029c2: 6afa ldr r2, [r7, #44] ; 0x2c + 80029c4: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80029c8: 623b str r3, [r7, #32] + + descnbr += 1U; + 80029ca: 6a7b ldr r3, [r7, #36] ; 0x24 + 80029cc: 3301 adds r3, #1 + 80029ce: 627b str r3, [r7, #36] ; 0x24 + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + 80029d0: 6a3b ldr r3, [r7, #32] + 80029d2: 68db ldr r3, [r3, #12] + 80029d4: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 80029d8: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 80029dc: d10f bne.n 80029fe + { + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx]; + 80029de: 697b ldr r3, [r7, #20] + 80029e0: 693a ldr r2, [r7, #16] + 80029e2: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80029e6: 623b str r3, [r7, #32] + __ASM volatile ("dmb 0xF":::"memory"); + 80029e8: f3bf 8f5f dmb sy +} + 80029ec: bf00 nop + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Clear own bit */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); + 80029ee: 6a3b ldr r3, [r7, #32] + 80029f0: 68db ldr r3, [r3, #12] + 80029f2: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 + 80029f6: 6a3b ldr r3, [r7, #32] + 80029f8: 60da str r2, [r3, #12] + + return HAL_ETH_ERROR_BUSY; + 80029fa: 2302 movs r3, #2 + 80029fc: e1b6 b.n 8002d6c + + /***************************************************************************/ + /***************** Normal descriptors configuration *****************/ + /***************************************************************************/ + + descnbr += 1U; + 80029fe: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002a00: 3301 adds r3, #1 + 8002a02: 627b str r3, [r7, #36] ; 0x24 + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + 8002a04: 69fb ldr r3, [r7, #28] + 8002a06: 681b ldr r3, [r3, #0] + 8002a08: 461a mov r2, r3 + 8002a0a: 6a3b ldr r3, [r7, #32] + 8002a0c: 601a str r2, [r3, #0] + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + 8002a0e: 6a3b ldr r3, [r7, #32] + 8002a10: 689a ldr r2, [r3, #8] + 8002a12: 4b24 ldr r3, [pc, #144] ; (8002aa4 ) + 8002a14: 4013 ands r3, r2 + 8002a16: 69fa ldr r2, [r7, #28] + 8002a18: 6852 ldr r2, [r2, #4] + 8002a1a: 431a orrs r2, r3 + 8002a1c: 6a3b ldr r3, [r7, #32] + 8002a1e: 609a str r2, [r3, #8] + + if (txbuffer->next != NULL) + 8002a20: 69fb ldr r3, [r7, #28] + 8002a22: 689b ldr r3, [r3, #8] + 8002a24: 2b00 cmp r3, #0 + 8002a26: d012 beq.n 8002a4e + { + txbuffer = txbuffer->next; + 8002a28: 69fb ldr r3, [r7, #28] + 8002a2a: 689b ldr r3, [r3, #8] + 8002a2c: 61fb str r3, [r7, #28] + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + 8002a2e: 69fb ldr r3, [r7, #28] + 8002a30: 681b ldr r3, [r3, #0] + 8002a32: 461a mov r2, r3 + 8002a34: 6a3b ldr r3, [r7, #32] + 8002a36: 605a str r2, [r3, #4] + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + 8002a38: 6a3b ldr r3, [r7, #32] + 8002a3a: 689a ldr r2, [r3, #8] + 8002a3c: 4b1a ldr r3, [pc, #104] ; (8002aa8 ) + 8002a3e: 4013 ands r3, r2 + 8002a40: 69fa ldr r2, [r7, #28] + 8002a42: 6852 ldr r2, [r2, #4] + 8002a44: 0412 lsls r2, r2, #16 + 8002a46: 431a orrs r2, r3 + 8002a48: 6a3b ldr r3, [r7, #32] + 8002a4a: 609a str r2, [r3, #8] + 8002a4c: e008 b.n 8002a60 + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0); + 8002a4e: 6a3b ldr r3, [r7, #32] + 8002a50: 2200 movs r2, #0 + 8002a52: 605a str r2, [r3, #4] + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + 8002a54: 6a3b ldr r3, [r7, #32] + 8002a56: 689a ldr r2, [r3, #8] + 8002a58: 4b13 ldr r3, [pc, #76] ; (8002aa8 ) + 8002a5a: 4013 ands r3, r2 + 8002a5c: 6a3a ldr r2, [r7, #32] + 8002a5e: 6093 str r3, [r2, #8] + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + 8002a60: 68bb ldr r3, [r7, #8] + 8002a62: 681b ldr r3, [r3, #0] + 8002a64: f003 0310 and.w r3, r3, #16 + 8002a68: 2b00 cmp r3, #0 + 8002a6a: d021 beq.n 8002ab0 + { + /* Set TCP Header length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19)); + 8002a6c: 6a3b ldr r3, [r7, #32] + 8002a6e: 68db ldr r3, [r3, #12] + 8002a70: f423 02f0 bic.w r2, r3, #7864320 ; 0x780000 + 8002a74: 68bb ldr r3, [r7, #8] + 8002a76: 6a1b ldr r3, [r3, #32] + 8002a78: 04db lsls r3, r3, #19 + 8002a7a: 431a orrs r2, r3 + 8002a7c: 6a3b ldr r3, [r7, #32] + 8002a7e: 60da str r2, [r3, #12] + /* Set TCP payload length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + 8002a80: 6a3b ldr r3, [r7, #32] + 8002a82: 68da ldr r2, [r3, #12] + 8002a84: 4b09 ldr r3, [pc, #36] ; (8002aac ) + 8002a86: 4013 ands r3, r2 + 8002a88: 68ba ldr r2, [r7, #8] + 8002a8a: 69d2 ldr r2, [r2, #28] + 8002a8c: 431a orrs r2, r3 + 8002a8e: 6a3b ldr r3, [r7, #32] + 8002a90: 60da str r2, [r3, #12] + /* Set TCP Segmentation Enabled bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); + 8002a92: 6a3b ldr r3, [r7, #32] + 8002a94: 68db ldr r3, [r3, #12] + 8002a96: f443 2280 orr.w r2, r3, #262144 ; 0x40000 + 8002a9a: 6a3b ldr r3, [r7, #32] + 8002a9c: 60da str r2, [r3, #12] + 8002a9e: e02e b.n 8002afe + 8002aa0: ffff0000 .word 0xffff0000 + 8002aa4: ffffc000 .word 0xffffc000 + 8002aa8: c000ffff .word 0xc000ffff + 8002aac: fffc0000 .word 0xfffc0000 + } + else + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + 8002ab0: 6a3b ldr r3, [r7, #32] + 8002ab2: 68da ldr r2, [r3, #12] + 8002ab4: 4b7b ldr r3, [pc, #492] ; (8002ca4 ) + 8002ab6: 4013 ands r3, r2 + 8002ab8: 68ba ldr r2, [r7, #8] + 8002aba: 6852 ldr r2, [r2, #4] + 8002abc: 431a orrs r2, r3 + 8002abe: 6a3b ldr r3, [r7, #32] + 8002ac0: 60da str r2, [r3, #12] + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + 8002ac2: 68bb ldr r3, [r7, #8] + 8002ac4: 681b ldr r3, [r3, #0] + 8002ac6: f003 0301 and.w r3, r3, #1 + 8002aca: 2b00 cmp r3, #0 + 8002acc: d008 beq.n 8002ae0 + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + 8002ace: 6a3b ldr r3, [r7, #32] + 8002ad0: 68db ldr r3, [r3, #12] + 8002ad2: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8002ad6: 68bb ldr r3, [r7, #8] + 8002ad8: 695b ldr r3, [r3, #20] + 8002ada: 431a orrs r2, r3 + 8002adc: 6a3b ldr r3, [r7, #32] + 8002ade: 60da str r2, [r3, #12] + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET) + 8002ae0: 68bb ldr r3, [r7, #8] + 8002ae2: 681b ldr r3, [r3, #0] + 8002ae4: f003 0320 and.w r3, r3, #32 + 8002ae8: 2b00 cmp r3, #0 + 8002aea: d008 beq.n 8002afe + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl); + 8002aec: 6a3b ldr r3, [r7, #32] + 8002aee: 68db ldr r3, [r3, #12] + 8002af0: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 + 8002af4: 68bb ldr r3, [r7, #8] + 8002af6: 691b ldr r3, [r3, #16] + 8002af8: 431a orrs r2, r3 + 8002afa: 6a3b ldr r3, [r7, #32] + 8002afc: 60da str r2, [r3, #12] + } + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + 8002afe: 68bb ldr r3, [r7, #8] + 8002b00: 681b ldr r3, [r3, #0] + 8002b02: f003 0304 and.w r3, r3, #4 + 8002b06: 2b00 cmp r3, #0 + 8002b08: d008 beq.n 8002b1c + { + /* Set Vlan Tag control */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); + 8002b0a: 6a3b ldr r3, [r7, #32] + 8002b0c: 689b ldr r3, [r3, #8] + 8002b0e: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8002b12: 68bb ldr r3, [r7, #8] + 8002b14: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002b16: 431a orrs r2, r3 + 8002b18: 6a3b ldr r3, [r7, #32] + 8002b1a: 609a str r2, [r3, #8] + } + + /* Mark it as First Descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + 8002b1c: 6a3b ldr r3, [r7, #32] + 8002b1e: 68db ldr r3, [r3, #12] + 8002b20: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000 + 8002b24: 6a3b ldr r3, [r7, #32] + 8002b26: 60da str r2, [r3, #12] + /* Mark it as NORMAL descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + 8002b28: 6a3b ldr r3, [r7, #32] + 8002b2a: 68db ldr r3, [r3, #12] + 8002b2c: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 + 8002b30: 6a3b ldr r3, [r7, #32] + 8002b32: 60da str r2, [r3, #12] + __ASM volatile ("dmb 0xF":::"memory"); + 8002b34: f3bf 8f5f dmb sy +} + 8002b38: bf00 nop + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* set OWN bit of FIRST descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + 8002b3a: 6a3b ldr r3, [r7, #32] + 8002b3c: 68db ldr r3, [r3, #12] + 8002b3e: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 8002b42: 6a3b ldr r3, [r7, #32] + 8002b44: 60da str r2, [r3, #12] + + /* If source address insertion/replacement is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET) + 8002b46: 68bb ldr r3, [r7, #8] + 8002b48: 681b ldr r3, [r3, #0] + 8002b4a: f003 0302 and.w r3, r3, #2 + 8002b4e: 2b00 cmp r3, #0 + 8002b50: f000 80da beq.w 8002d08 + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl); + 8002b54: 6a3b ldr r3, [r7, #32] + 8002b56: 68db ldr r3, [r3, #12] + 8002b58: f023 7260 bic.w r2, r3, #58720256 ; 0x3800000 + 8002b5c: 68bb ldr r3, [r7, #8] + 8002b5e: 68db ldr r3, [r3, #12] + 8002b60: 431a orrs r2, r3 + 8002b62: 6a3b ldr r3, [r7, #32] + 8002b64: 60da str r2, [r3, #12] + } + + /* only if the packet is split into more than one descriptors > 1 */ + while (txbuffer->next != NULL) + 8002b66: e0cf b.n 8002d08 + { + /* Clear the LD bit of previous descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + 8002b68: 6a3b ldr r3, [r7, #32] + 8002b6a: 68db ldr r3, [r3, #12] + 8002b6c: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 8002b70: 6a3b ldr r3, [r7, #32] + 8002b72: 60da str r2, [r3, #12] + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + 8002b74: 6afb ldr r3, [r7, #44] ; 0x2c + 8002b76: 3301 adds r3, #1 + 8002b78: 62fb str r3, [r7, #44] ; 0x2c + 8002b7a: 6afb ldr r3, [r7, #44] ; 0x2c + 8002b7c: 2b03 cmp r3, #3 + 8002b7e: d902 bls.n 8002b86 + 8002b80: 6afb ldr r3, [r7, #44] ; 0x2c + 8002b82: 3b04 subs r3, #4 + 8002b84: 62fb str r3, [r7, #44] ; 0x2c + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 8002b86: 697b ldr r3, [r7, #20] + 8002b88: 6afa ldr r2, [r7, #44] ; 0x2c + 8002b8a: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002b8e: 623b str r3, [r7, #32] + + /* Clear the FD bit of new Descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + 8002b90: 6a3b ldr r3, [r7, #32] + 8002b92: 68db ldr r3, [r3, #12] + 8002b94: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 + 8002b98: 6a3b ldr r3, [r7, #32] + 8002b9a: 60da str r2, [r3, #12] + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) + 8002b9c: 6a3b ldr r3, [r7, #32] + 8002b9e: 68db ldr r3, [r3, #12] + 8002ba0: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 + 8002ba4: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 8002ba8: d007 beq.n 8002bba + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + 8002baa: 697a ldr r2, [r7, #20] + 8002bac: 6afb ldr r3, [r7, #44] ; 0x2c + 8002bae: 3304 adds r3, #4 + 8002bb0: 009b lsls r3, r3, #2 + 8002bb2: 4413 add r3, r2 + 8002bb4: 685b ldr r3, [r3, #4] + 8002bb6: 2b00 cmp r3, #0 + 8002bb8: d029 beq.n 8002c0e + { + descidx = firstdescidx; + 8002bba: 693b ldr r3, [r7, #16] + 8002bbc: 62fb str r3, [r7, #44] ; 0x2c + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 8002bbe: 697b ldr r3, [r7, #20] + 8002bc0: 6afa ldr r2, [r7, #44] ; 0x2c + 8002bc2: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002bc6: 623b str r3, [r7, #32] + + /* clear previous desc own bit */ + for (idx = 0; idx < descnbr; idx ++) + 8002bc8: 2300 movs r3, #0 + 8002bca: 62bb str r3, [r7, #40] ; 0x28 + 8002bcc: e019 b.n 8002c02 + __ASM volatile ("dmb 0xF":::"memory"); + 8002bce: f3bf 8f5f dmb sy +} + 8002bd2: bf00 nop + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + 8002bd4: 6a3b ldr r3, [r7, #32] + 8002bd6: 68db ldr r3, [r3, #12] + 8002bd8: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 + 8002bdc: 6a3b ldr r3, [r7, #32] + 8002bde: 60da str r2, [r3, #12] + + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + 8002be0: 6afb ldr r3, [r7, #44] ; 0x2c + 8002be2: 3301 adds r3, #1 + 8002be4: 62fb str r3, [r7, #44] ; 0x2c + 8002be6: 6afb ldr r3, [r7, #44] ; 0x2c + 8002be8: 2b03 cmp r3, #3 + 8002bea: d902 bls.n 8002bf2 + 8002bec: 6afb ldr r3, [r7, #44] ; 0x2c + 8002bee: 3b04 subs r3, #4 + 8002bf0: 62fb str r3, [r7, #44] ; 0x2c + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + 8002bf2: 697b ldr r3, [r7, #20] + 8002bf4: 6afa ldr r2, [r7, #44] ; 0x2c + 8002bf6: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002bfa: 623b str r3, [r7, #32] + for (idx = 0; idx < descnbr; idx ++) + 8002bfc: 6abb ldr r3, [r7, #40] ; 0x28 + 8002bfe: 3301 adds r3, #1 + 8002c00: 62bb str r3, [r7, #40] ; 0x28 + 8002c02: 6aba ldr r2, [r7, #40] ; 0x28 + 8002c04: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002c06: 429a cmp r2, r3 + 8002c08: d3e1 bcc.n 8002bce + } + + return HAL_ETH_ERROR_BUSY; + 8002c0a: 2302 movs r3, #2 + 8002c0c: e0ae b.n 8002d6c + } + + descnbr += 1U; + 8002c0e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002c10: 3301 adds r3, #1 + 8002c12: 627b str r3, [r7, #36] ; 0x24 + + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + 8002c14: 69fb ldr r3, [r7, #28] + 8002c16: 689b ldr r3, [r3, #8] + 8002c18: 61fb str r3, [r7, #28] + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + 8002c1a: 69fb ldr r3, [r7, #28] + 8002c1c: 681b ldr r3, [r3, #0] + 8002c1e: 461a mov r2, r3 + 8002c20: 6a3b ldr r3, [r7, #32] + 8002c22: 601a str r2, [r3, #0] + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + 8002c24: 6a3b ldr r3, [r7, #32] + 8002c26: 689a ldr r2, [r3, #8] + 8002c28: 4b1f ldr r3, [pc, #124] ; (8002ca8 ) + 8002c2a: 4013 ands r3, r2 + 8002c2c: 69fa ldr r2, [r7, #28] + 8002c2e: 6852 ldr r2, [r2, #4] + 8002c30: 431a orrs r2, r3 + 8002c32: 6a3b ldr r3, [r7, #32] + 8002c34: 609a str r2, [r3, #8] + + if (txbuffer->next != NULL) + 8002c36: 69fb ldr r3, [r7, #28] + 8002c38: 689b ldr r3, [r3, #8] + 8002c3a: 2b00 cmp r3, #0 + 8002c3c: d012 beq.n 8002c64 + { + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + 8002c3e: 69fb ldr r3, [r7, #28] + 8002c40: 689b ldr r3, [r3, #8] + 8002c42: 61fb str r3, [r7, #28] + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + 8002c44: 69fb ldr r3, [r7, #28] + 8002c46: 681b ldr r3, [r3, #0] + 8002c48: 461a mov r2, r3 + 8002c4a: 6a3b ldr r3, [r7, #32] + 8002c4c: 605a str r2, [r3, #4] + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + 8002c4e: 6a3b ldr r3, [r7, #32] + 8002c50: 689a ldr r2, [r3, #8] + 8002c52: 4b16 ldr r3, [pc, #88] ; (8002cac ) + 8002c54: 4013 ands r3, r2 + 8002c56: 69fa ldr r2, [r7, #28] + 8002c58: 6852 ldr r2, [r2, #4] + 8002c5a: 0412 lsls r2, r2, #16 + 8002c5c: 431a orrs r2, r3 + 8002c5e: 6a3b ldr r3, [r7, #32] + 8002c60: 609a str r2, [r3, #8] + 8002c62: e008 b.n 8002c76 + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0); + 8002c64: 6a3b ldr r3, [r7, #32] + 8002c66: 2200 movs r2, #0 + 8002c68: 605a str r2, [r3, #4] + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + 8002c6a: 6a3b ldr r3, [r7, #32] + 8002c6c: 689a ldr r2, [r3, #8] + 8002c6e: 4b0f ldr r3, [pc, #60] ; (8002cac ) + 8002c70: 4013 ands r3, r2 + 8002c72: 6a3a ldr r2, [r7, #32] + 8002c74: 6093 str r3, [r2, #8] + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + 8002c76: 68bb ldr r3, [r7, #8] + 8002c78: 681b ldr r3, [r3, #0] + 8002c7a: f003 0310 and.w r3, r3, #16 + 8002c7e: 2b00 cmp r3, #0 + 8002c80: d018 beq.n 8002cb4 + { + /* Set TCP payload length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + 8002c82: 6a3b ldr r3, [r7, #32] + 8002c84: 68da ldr r2, [r3, #12] + 8002c86: 4b0a ldr r3, [pc, #40] ; (8002cb0 ) + 8002c88: 4013 ands r3, r2 + 8002c8a: 68ba ldr r2, [r7, #8] + 8002c8c: 69d2 ldr r2, [r2, #28] + 8002c8e: 431a orrs r2, r3 + 8002c90: 6a3b ldr r3, [r7, #32] + 8002c92: 60da str r2, [r3, #12] + /* Set TCP Segmentation Enabled bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); + 8002c94: 6a3b ldr r3, [r7, #32] + 8002c96: 68db ldr r3, [r3, #12] + 8002c98: f443 2280 orr.w r2, r3, #262144 ; 0x40000 + 8002c9c: 6a3b ldr r3, [r7, #32] + 8002c9e: 60da str r2, [r3, #12] + 8002ca0: e020 b.n 8002ce4 + 8002ca2: bf00 nop + 8002ca4: ffff8000 .word 0xffff8000 + 8002ca8: ffffc000 .word 0xffffc000 + 8002cac: c000ffff .word 0xc000ffff + 8002cb0: fffc0000 .word 0xfffc0000 + } + else + { + /* Set the packet length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + 8002cb4: 6a3b ldr r3, [r7, #32] + 8002cb6: 68da ldr r2, [r3, #12] + 8002cb8: 4b2f ldr r3, [pc, #188] ; (8002d78 ) + 8002cba: 4013 ands r3, r2 + 8002cbc: 68ba ldr r2, [r7, #8] + 8002cbe: 6852 ldr r2, [r2, #4] + 8002cc0: 431a orrs r2, r3 + 8002cc2: 6a3b ldr r3, [r7, #32] + 8002cc4: 60da str r2, [r3, #12] + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + 8002cc6: 68bb ldr r3, [r7, #8] + 8002cc8: 681b ldr r3, [r3, #0] + 8002cca: f003 0301 and.w r3, r3, #1 + 8002cce: 2b00 cmp r3, #0 + 8002cd0: d008 beq.n 8002ce4 + { + /* Checksum Insertion Control */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + 8002cd2: 6a3b ldr r3, [r7, #32] + 8002cd4: 68db ldr r3, [r3, #12] + 8002cd6: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8002cda: 68bb ldr r3, [r7, #8] + 8002cdc: 695b ldr r3, [r3, #20] + 8002cde: 431a orrs r2, r3 + 8002ce0: 6a3b ldr r3, [r7, #32] + 8002ce2: 60da str r2, [r3, #12] + } + } + + bd_count += 1U; + 8002ce4: 69bb ldr r3, [r7, #24] + 8002ce6: 3301 adds r3, #1 + 8002ce8: 61bb str r3, [r7, #24] + __ASM volatile ("dmb 0xF":::"memory"); + 8002cea: f3bf 8f5f dmb sy +} + 8002cee: bf00 nop + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set Own bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + 8002cf0: 6a3b ldr r3, [r7, #32] + 8002cf2: 68db ldr r3, [r3, #12] + 8002cf4: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 8002cf8: 6a3b ldr r3, [r7, #32] + 8002cfa: 60da str r2, [r3, #12] + /* Mark it as NORMAL descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + 8002cfc: 6a3b ldr r3, [r7, #32] + 8002cfe: 68db ldr r3, [r3, #12] + 8002d00: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 + 8002d04: 6a3b ldr r3, [r7, #32] + 8002d06: 60da str r2, [r3, #12] + while (txbuffer->next != NULL) + 8002d08: 69fb ldr r3, [r7, #28] + 8002d0a: 689b ldr r3, [r3, #8] + 8002d0c: 2b00 cmp r3, #0 + 8002d0e: f47f af2b bne.w 8002b68 + } + + if (ItMode != ((uint32_t)RESET)) + 8002d12: 687b ldr r3, [r7, #4] + 8002d14: 2b00 cmp r3, #0 + 8002d16: d006 beq.n 8002d26 + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + 8002d18: 6a3b ldr r3, [r7, #32] + 8002d1a: 689b ldr r3, [r3, #8] + 8002d1c: f043 4200 orr.w r2, r3, #2147483648 ; 0x80000000 + 8002d20: 6a3b ldr r3, [r7, #32] + 8002d22: 609a str r2, [r3, #8] + 8002d24: e005 b.n 8002d32 + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + 8002d26: 6a3b ldr r3, [r7, #32] + 8002d28: 689b ldr r3, [r3, #8] + 8002d2a: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 + 8002d2e: 6a3b ldr r3, [r7, #32] + 8002d30: 609a str r2, [r3, #8] + } + + /* Mark it as LAST descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + 8002d32: 6a3b ldr r3, [r7, #32] + 8002d34: 68db ldr r3, [r3, #12] + 8002d36: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 + 8002d3a: 6a3b ldr r3, [r7, #32] + 8002d3c: 60da str r2, [r3, #12] + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; + 8002d3e: 697b ldr r3, [r7, #20] + 8002d40: 6a5a ldr r2, [r3, #36] ; 0x24 + 8002d42: 6979 ldr r1, [r7, #20] + 8002d44: 6afb ldr r3, [r7, #44] ; 0x2c + 8002d46: 3304 adds r3, #4 + 8002d48: 009b lsls r3, r3, #2 + 8002d4a: 440b add r3, r1 + 8002d4c: 605a str r2, [r3, #4] + + dmatxdesclist->CurTxDesc = descidx; + 8002d4e: 697b ldr r3, [r7, #20] + 8002d50: 6afa ldr r2, [r7, #44] ; 0x2c + 8002d52: 611a str r2, [r3, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 8002d54: b672 cpsid i +} + 8002d56: bf00 nop + + /* disable the interrupt */ + __disable_irq(); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + 8002d58: 697b ldr r3, [r7, #20] + 8002d5a: 6a9a ldr r2, [r3, #40] ; 0x28 + 8002d5c: 69bb ldr r3, [r7, #24] + 8002d5e: 4413 add r3, r2 + 8002d60: 1c5a adds r2, r3, #1 + 8002d62: 697b ldr r3, [r7, #20] + 8002d64: 629a str r2, [r3, #40] ; 0x28 + __ASM volatile ("cpsie i" : : : "memory"); + 8002d66: b662 cpsie i +} + 8002d68: bf00 nop + /* Enable interrupts back */ + __enable_irq(); + + + /* Return function status */ + return HAL_ETH_ERROR_NONE; + 8002d6a: 2300 movs r3, #0 +} + 8002d6c: 4618 mov r0, r3 + 8002d6e: 3734 adds r7, #52 ; 0x34 + 8002d70: 46bd mov sp, r7 + 8002d72: f85d 7b04 ldr.w r7, [sp], #4 + 8002d76: 4770 bx lr + 8002d78: ffff8000 .word 0xffff8000 + +08002d7c : + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8002d7c: b480 push {r7} + 8002d7e: b089 sub sp, #36 ; 0x24 + 8002d80: af00 add r7, sp, #0 + 8002d82: 6078 str r0, [r7, #4] + 8002d84: 6039 str r1, [r7, #0] + uint32_t position = 0x00U; + 8002d86: 2300 movs r3, #0 + 8002d88: 61fb str r3, [r7, #28] + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ + 8002d8a: 4b86 ldr r3, [pc, #536] ; (8002fa4 ) + 8002d8c: 617b str r3, [r7, #20] + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00U) + 8002d8e: e18c b.n 80030aa + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1UL << position); + 8002d90: 683b ldr r3, [r7, #0] + 8002d92: 681a ldr r2, [r3, #0] + 8002d94: 2101 movs r1, #1 + 8002d96: 69fb ldr r3, [r7, #28] + 8002d98: fa01 f303 lsl.w r3, r1, r3 + 8002d9c: 4013 ands r3, r2 + 8002d9e: 613b str r3, [r7, #16] + + if (iocurrent != 0x00U) + 8002da0: 693b ldr r3, [r7, #16] + 8002da2: 2b00 cmp r3, #0 + 8002da4: f000 817e beq.w 80030a4 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8002da8: 683b ldr r3, [r7, #0] + 8002daa: 685b ldr r3, [r3, #4] + 8002dac: f003 0303 and.w r3, r3, #3 + 8002db0: 2b01 cmp r3, #1 + 8002db2: d005 beq.n 8002dc0 + 8002db4: 683b ldr r3, [r7, #0] + 8002db6: 685b ldr r3, [r3, #4] + 8002db8: f003 0303 and.w r3, r3, #3 + 8002dbc: 2b02 cmp r3, #2 + 8002dbe: d130 bne.n 8002e22 + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8002dc0: 687b ldr r3, [r7, #4] + 8002dc2: 689b ldr r3, [r3, #8] + 8002dc4: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 8002dc6: 69fb ldr r3, [r7, #28] + 8002dc8: 005b lsls r3, r3, #1 + 8002dca: 2203 movs r2, #3 + 8002dcc: fa02 f303 lsl.w r3, r2, r3 + 8002dd0: 43db mvns r3, r3 + 8002dd2: 69ba ldr r2, [r7, #24] + 8002dd4: 4013 ands r3, r2 + 8002dd6: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2U)); + 8002dd8: 683b ldr r3, [r7, #0] + 8002dda: 68da ldr r2, [r3, #12] + 8002ddc: 69fb ldr r3, [r7, #28] + 8002dde: 005b lsls r3, r3, #1 + 8002de0: fa02 f303 lsl.w r3, r2, r3 + 8002de4: 69ba ldr r2, [r7, #24] + 8002de6: 4313 orrs r3, r2 + 8002de8: 61bb str r3, [r7, #24] + GPIOx->OSPEEDR = temp; + 8002dea: 687b ldr r3, [r7, #4] + 8002dec: 69ba ldr r2, [r7, #24] + 8002dee: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8002df0: 687b ldr r3, [r7, #4] + 8002df2: 685b ldr r3, [r3, #4] + 8002df4: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT0 << position) ; + 8002df6: 2201 movs r2, #1 + 8002df8: 69fb ldr r3, [r7, #28] + 8002dfa: fa02 f303 lsl.w r3, r2, r3 + 8002dfe: 43db mvns r3, r3 + 8002e00: 69ba ldr r2, [r7, #24] + 8002e02: 4013 ands r3, r2 + 8002e04: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8002e06: 683b ldr r3, [r7, #0] + 8002e08: 685b ldr r3, [r3, #4] + 8002e0a: 091b lsrs r3, r3, #4 + 8002e0c: f003 0201 and.w r2, r3, #1 + 8002e10: 69fb ldr r3, [r7, #28] + 8002e12: fa02 f303 lsl.w r3, r2, r3 + 8002e16: 69ba ldr r2, [r7, #24] + 8002e18: 4313 orrs r3, r2 + 8002e1a: 61bb str r3, [r7, #24] + GPIOx->OTYPER = temp; + 8002e1c: 687b ldr r3, [r7, #4] + 8002e1e: 69ba ldr r2, [r7, #24] + 8002e20: 605a str r2, [r3, #4] + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8002e22: 683b ldr r3, [r7, #0] + 8002e24: 685b ldr r3, [r3, #4] + 8002e26: f003 0303 and.w r3, r3, #3 + 8002e2a: 2b03 cmp r3, #3 + 8002e2c: d017 beq.n 8002e5e + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + 8002e2e: 687b ldr r3, [r7, #4] + 8002e30: 68db ldr r3, [r3, #12] + 8002e32: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 8002e34: 69fb ldr r3, [r7, #28] + 8002e36: 005b lsls r3, r3, #1 + 8002e38: 2203 movs r2, #3 + 8002e3a: fa02 f303 lsl.w r3, r2, r3 + 8002e3e: 43db mvns r3, r3 + 8002e40: 69ba ldr r2, [r7, #24] + 8002e42: 4013 ands r3, r2 + 8002e44: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 8002e46: 683b ldr r3, [r7, #0] + 8002e48: 689a ldr r2, [r3, #8] + 8002e4a: 69fb ldr r3, [r7, #28] + 8002e4c: 005b lsls r3, r3, #1 + 8002e4e: fa02 f303 lsl.w r3, r2, r3 + 8002e52: 69ba ldr r2, [r7, #24] + 8002e54: 4313 orrs r3, r2 + 8002e56: 61bb str r3, [r7, #24] + GPIOx->PUPDR = temp; + 8002e58: 687b ldr r3, [r7, #4] + 8002e5a: 69ba ldr r2, [r7, #24] + 8002e5c: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8002e5e: 683b ldr r3, [r7, #0] + 8002e60: 685b ldr r3, [r3, #4] + 8002e62: f003 0303 and.w r3, r3, #3 + 8002e66: 2b02 cmp r3, #2 + 8002e68: d123 bne.n 8002eb2 + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + 8002e6a: 69fb ldr r3, [r7, #28] + 8002e6c: 08da lsrs r2, r3, #3 + 8002e6e: 687b ldr r3, [r7, #4] + 8002e70: 3208 adds r2, #8 + 8002e72: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002e76: 61bb str r3, [r7, #24] + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 8002e78: 69fb ldr r3, [r7, #28] + 8002e7a: f003 0307 and.w r3, r3, #7 + 8002e7e: 009b lsls r3, r3, #2 + 8002e80: 220f movs r2, #15 + 8002e82: fa02 f303 lsl.w r3, r2, r3 + 8002e86: 43db mvns r3, r3 + 8002e88: 69ba ldr r2, [r7, #24] + 8002e8a: 4013 ands r3, r2 + 8002e8c: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 8002e8e: 683b ldr r3, [r7, #0] + 8002e90: 691a ldr r2, [r3, #16] + 8002e92: 69fb ldr r3, [r7, #28] + 8002e94: f003 0307 and.w r3, r3, #7 + 8002e98: 009b lsls r3, r3, #2 + 8002e9a: fa02 f303 lsl.w r3, r2, r3 + 8002e9e: 69ba ldr r2, [r7, #24] + 8002ea0: 4313 orrs r3, r2 + 8002ea2: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3U] = temp; + 8002ea4: 69fb ldr r3, [r7, #28] + 8002ea6: 08da lsrs r2, r3, #3 + 8002ea8: 687b ldr r3, [r7, #4] + 8002eaa: 3208 adds r2, #8 + 8002eac: 69b9 ldr r1, [r7, #24] + 8002eae: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8002eb2: 687b ldr r3, [r7, #4] + 8002eb4: 681b ldr r3, [r3, #0] + 8002eb6: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 8002eb8: 69fb ldr r3, [r7, #28] + 8002eba: 005b lsls r3, r3, #1 + 8002ebc: 2203 movs r2, #3 + 8002ebe: fa02 f303 lsl.w r3, r2, r3 + 8002ec2: 43db mvns r3, r3 + 8002ec4: 69ba ldr r2, [r7, #24] + 8002ec6: 4013 ands r3, r2 + 8002ec8: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8002eca: 683b ldr r3, [r7, #0] + 8002ecc: 685b ldr r3, [r3, #4] + 8002ece: f003 0203 and.w r2, r3, #3 + 8002ed2: 69fb ldr r3, [r7, #28] + 8002ed4: 005b lsls r3, r3, #1 + 8002ed6: fa02 f303 lsl.w r3, r2, r3 + 8002eda: 69ba ldr r2, [r7, #24] + 8002edc: 4313 orrs r3, r2 + 8002ede: 61bb str r3, [r7, #24] + GPIOx->MODER = temp; + 8002ee0: 687b ldr r3, [r7, #4] + 8002ee2: 69ba ldr r2, [r7, #24] + 8002ee4: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + 8002ee6: 683b ldr r3, [r7, #0] + 8002ee8: 685b ldr r3, [r3, #4] + 8002eea: f403 3340 and.w r3, r3, #196608 ; 0x30000 + 8002eee: 2b00 cmp r3, #0 + 8002ef0: f000 80d8 beq.w 80030a4 + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8002ef4: 4b2c ldr r3, [pc, #176] ; (8002fa8 ) + 8002ef6: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 + 8002efa: 4a2b ldr r2, [pc, #172] ; (8002fa8 ) + 8002efc: f043 0302 orr.w r3, r3, #2 + 8002f00: f8c2 30f4 str.w r3, [r2, #244] ; 0xf4 + 8002f04: 4b28 ldr r3, [pc, #160] ; (8002fa8 ) + 8002f06: f8d3 30f4 ldr.w r3, [r3, #244] ; 0xf4 + 8002f0a: f003 0302 and.w r3, r3, #2 + 8002f0e: 60fb str r3, [r7, #12] + 8002f10: 68fb ldr r3, [r7, #12] + + temp = SYSCFG->EXTICR[position >> 2U]; + 8002f12: 4a26 ldr r2, [pc, #152] ; (8002fac ) + 8002f14: 69fb ldr r3, [r7, #28] + 8002f16: 089b lsrs r3, r3, #2 + 8002f18: 3302 adds r3, #2 + 8002f1a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002f1e: 61bb str r3, [r7, #24] + temp &= ~(0x0FUL << (4U * (position & 0x03U))); + 8002f20: 69fb ldr r3, [r7, #28] + 8002f22: f003 0303 and.w r3, r3, #3 + 8002f26: 009b lsls r3, r3, #2 + 8002f28: 220f movs r2, #15 + 8002f2a: fa02 f303 lsl.w r3, r2, r3 + 8002f2e: 43db mvns r3, r3 + 8002f30: 69ba ldr r2, [r7, #24] + 8002f32: 4013 ands r3, r2 + 8002f34: 61bb str r3, [r7, #24] + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 8002f36: 687b ldr r3, [r7, #4] + 8002f38: 4a1d ldr r2, [pc, #116] ; (8002fb0 ) + 8002f3a: 4293 cmp r3, r2 + 8002f3c: d04a beq.n 8002fd4 + 8002f3e: 687b ldr r3, [r7, #4] + 8002f40: 4a1c ldr r2, [pc, #112] ; (8002fb4 ) + 8002f42: 4293 cmp r3, r2 + 8002f44: d02b beq.n 8002f9e + 8002f46: 687b ldr r3, [r7, #4] + 8002f48: 4a1b ldr r2, [pc, #108] ; (8002fb8 ) + 8002f4a: 4293 cmp r3, r2 + 8002f4c: d025 beq.n 8002f9a + 8002f4e: 687b ldr r3, [r7, #4] + 8002f50: 4a1a ldr r2, [pc, #104] ; (8002fbc ) + 8002f52: 4293 cmp r3, r2 + 8002f54: d01f beq.n 8002f96 + 8002f56: 687b ldr r3, [r7, #4] + 8002f58: 4a19 ldr r2, [pc, #100] ; (8002fc0 ) + 8002f5a: 4293 cmp r3, r2 + 8002f5c: d019 beq.n 8002f92 + 8002f5e: 687b ldr r3, [r7, #4] + 8002f60: 4a18 ldr r2, [pc, #96] ; (8002fc4 ) + 8002f62: 4293 cmp r3, r2 + 8002f64: d013 beq.n 8002f8e + 8002f66: 687b ldr r3, [r7, #4] + 8002f68: 4a17 ldr r2, [pc, #92] ; (8002fc8 ) + 8002f6a: 4293 cmp r3, r2 + 8002f6c: d00d beq.n 8002f8a + 8002f6e: 687b ldr r3, [r7, #4] + 8002f70: 4a16 ldr r2, [pc, #88] ; (8002fcc ) + 8002f72: 4293 cmp r3, r2 + 8002f74: d007 beq.n 8002f86 + 8002f76: 687b ldr r3, [r7, #4] + 8002f78: 4a15 ldr r2, [pc, #84] ; (8002fd0 ) + 8002f7a: 4293 cmp r3, r2 + 8002f7c: d101 bne.n 8002f82 + 8002f7e: 2309 movs r3, #9 + 8002f80: e029 b.n 8002fd6 + 8002f82: 230a movs r3, #10 + 8002f84: e027 b.n 8002fd6 + 8002f86: 2307 movs r3, #7 + 8002f88: e025 b.n 8002fd6 + 8002f8a: 2306 movs r3, #6 + 8002f8c: e023 b.n 8002fd6 + 8002f8e: 2305 movs r3, #5 + 8002f90: e021 b.n 8002fd6 + 8002f92: 2304 movs r3, #4 + 8002f94: e01f b.n 8002fd6 + 8002f96: 2303 movs r3, #3 + 8002f98: e01d b.n 8002fd6 + 8002f9a: 2302 movs r3, #2 + 8002f9c: e01b b.n 8002fd6 + 8002f9e: 2301 movs r3, #1 + 8002fa0: e019 b.n 8002fd6 + 8002fa2: bf00 nop + 8002fa4: 58000080 .word 0x58000080 + 8002fa8: 58024400 .word 0x58024400 + 8002fac: 58000400 .word 0x58000400 + 8002fb0: 58020000 .word 0x58020000 + 8002fb4: 58020400 .word 0x58020400 + 8002fb8: 58020800 .word 0x58020800 + 8002fbc: 58020c00 .word 0x58020c00 + 8002fc0: 58021000 .word 0x58021000 + 8002fc4: 58021400 .word 0x58021400 + 8002fc8: 58021800 .word 0x58021800 + 8002fcc: 58021c00 .word 0x58021c00 + 8002fd0: 58022400 .word 0x58022400 + 8002fd4: 2300 movs r3, #0 + 8002fd6: 69fa ldr r2, [r7, #28] + 8002fd8: f002 0203 and.w r2, r2, #3 + 8002fdc: 0092 lsls r2, r2, #2 + 8002fde: 4093 lsls r3, r2 + 8002fe0: 69ba ldr r2, [r7, #24] + 8002fe2: 4313 orrs r3, r2 + 8002fe4: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2U] = temp; + 8002fe6: 4938 ldr r1, [pc, #224] ; (80030c8 ) + 8002fe8: 69fb ldr r3, [r7, #28] + 8002fea: 089b lsrs r3, r3, #2 + 8002fec: 3302 adds r3, #2 + 8002fee: 69ba ldr r2, [r7, #24] + 8002ff0: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + 8002ff4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8002ff8: 681b ldr r3, [r3, #0] + 8002ffa: 61bb str r3, [r7, #24] + temp &= ~(iocurrent); + 8002ffc: 693b ldr r3, [r7, #16] + 8002ffe: 43db mvns r3, r3 + 8003000: 69ba ldr r2, [r7, #24] + 8003002: 4013 ands r3, r2 + 8003004: 61bb str r3, [r7, #24] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + 8003006: 683b ldr r3, [r7, #0] + 8003008: 685b ldr r3, [r3, #4] + 800300a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800300e: 2b00 cmp r3, #0 + 8003010: d003 beq.n 800301a + { + temp |= iocurrent; + 8003012: 69ba ldr r2, [r7, #24] + 8003014: 693b ldr r3, [r7, #16] + 8003016: 4313 orrs r3, r2 + 8003018: 61bb str r3, [r7, #24] + } + EXTI->RTSR1 = temp; + 800301a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800301e: 69bb ldr r3, [r7, #24] + 8003020: 6013 str r3, [r2, #0] + + temp = EXTI->FTSR1; + 8003022: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003026: 685b ldr r3, [r3, #4] + 8003028: 61bb str r3, [r7, #24] + temp &= ~(iocurrent); + 800302a: 693b ldr r3, [r7, #16] + 800302c: 43db mvns r3, r3 + 800302e: 69ba ldr r2, [r7, #24] + 8003030: 4013 ands r3, r2 + 8003032: 61bb str r3, [r7, #24] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + 8003034: 683b ldr r3, [r7, #0] + 8003036: 685b ldr r3, [r3, #4] + 8003038: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800303c: 2b00 cmp r3, #0 + 800303e: d003 beq.n 8003048 + { + temp |= iocurrent; + 8003040: 69ba ldr r2, [r7, #24] + 8003042: 693b ldr r3, [r7, #16] + 8003044: 4313 orrs r3, r2 + 8003046: 61bb str r3, [r7, #24] + } + EXTI->FTSR1 = temp; + 8003048: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800304c: 69bb ldr r3, [r7, #24] + 800304e: 6053 str r3, [r2, #4] + + temp = EXTI_CurrentCPU->EMR1; + 8003050: 697b ldr r3, [r7, #20] + 8003052: 685b ldr r3, [r3, #4] + 8003054: 61bb str r3, [r7, #24] + temp &= ~(iocurrent); + 8003056: 693b ldr r3, [r7, #16] + 8003058: 43db mvns r3, r3 + 800305a: 69ba ldr r2, [r7, #24] + 800305c: 4013 ands r3, r2 + 800305e: 61bb str r3, [r7, #24] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + 8003060: 683b ldr r3, [r7, #0] + 8003062: 685b ldr r3, [r3, #4] + 8003064: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8003068: 2b00 cmp r3, #0 + 800306a: d003 beq.n 8003074 + { + temp |= iocurrent; + 800306c: 69ba ldr r2, [r7, #24] + 800306e: 693b ldr r3, [r7, #16] + 8003070: 4313 orrs r3, r2 + 8003072: 61bb str r3, [r7, #24] + } + EXTI_CurrentCPU->EMR1 = temp; + 8003074: 697b ldr r3, [r7, #20] + 8003076: 69ba ldr r2, [r7, #24] + 8003078: 605a str r2, [r3, #4] + + /* Clear EXTI line configuration */ + temp = EXTI_CurrentCPU->IMR1; + 800307a: 697b ldr r3, [r7, #20] + 800307c: 681b ldr r3, [r3, #0] + 800307e: 61bb str r3, [r7, #24] + temp &= ~(iocurrent); + 8003080: 693b ldr r3, [r7, #16] + 8003082: 43db mvns r3, r3 + 8003084: 69ba ldr r2, [r7, #24] + 8003086: 4013 ands r3, r2 + 8003088: 61bb str r3, [r7, #24] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + 800308a: 683b ldr r3, [r7, #0] + 800308c: 685b ldr r3, [r3, #4] + 800308e: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8003092: 2b00 cmp r3, #0 + 8003094: d003 beq.n 800309e + { + temp |= iocurrent; + 8003096: 69ba ldr r2, [r7, #24] + 8003098: 693b ldr r3, [r7, #16] + 800309a: 4313 orrs r3, r2 + 800309c: 61bb str r3, [r7, #24] + } + EXTI_CurrentCPU->IMR1 = temp; + 800309e: 697b ldr r3, [r7, #20] + 80030a0: 69ba ldr r2, [r7, #24] + 80030a2: 601a str r2, [r3, #0] + } + } + + position++; + 80030a4: 69fb ldr r3, [r7, #28] + 80030a6: 3301 adds r3, #1 + 80030a8: 61fb str r3, [r7, #28] + while (((GPIO_Init->Pin) >> position) != 0x00U) + 80030aa: 683b ldr r3, [r7, #0] + 80030ac: 681a ldr r2, [r3, #0] + 80030ae: 69fb ldr r3, [r7, #28] + 80030b0: fa22 f303 lsr.w r3, r2, r3 + 80030b4: 2b00 cmp r3, #0 + 80030b6: f47f ae6b bne.w 8002d90 + } +} + 80030ba: bf00 nop + 80030bc: bf00 nop + 80030be: 3724 adds r7, #36 ; 0x24 + 80030c0: 46bd mov sp, r7 + 80030c2: f85d 7b04 ldr.w r7, [sp], #4 + 80030c6: 4770 bx lr + 80030c8: 58000400 .word 0x58000400 + +080030cc : + * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS + * regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) +{ + 80030cc: b580 push {r7, lr} + 80030ce: b084 sub sp, #16 + 80030d0: af00 add r7, sp, #0 + 80030d2: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param (IS_PWR_SUPPLY (SupplySource)); + + /* Check if supply source was configured */ +#if defined (PWR_FLAG_SCUEN) + if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) + 80030d4: 4b19 ldr r3, [pc, #100] ; (800313c ) + 80030d6: 68db ldr r3, [r3, #12] + 80030d8: f003 0304 and.w r3, r3, #4 + 80030dc: 2b04 cmp r3, #4 + 80030de: d00a beq.n 80030f6 +#else + if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) +#endif /* defined (PWR_FLAG_SCUEN) */ + { + /* Check supply configuration */ + if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) + 80030e0: 4b16 ldr r3, [pc, #88] ; (800313c ) + 80030e2: 68db ldr r3, [r3, #12] + 80030e4: f003 0307 and.w r3, r3, #7 + 80030e8: 687a ldr r2, [r7, #4] + 80030ea: 429a cmp r2, r3 + 80030ec: d001 beq.n 80030f2 + { + /* Supply configuration update locked, can't apply a new supply config */ + return HAL_ERROR; + 80030ee: 2301 movs r3, #1 + 80030f0: e01f b.n 8003132 + else + { + /* Supply configuration update locked, but new supply configuration + matches with old supply configuration : nothing to do + */ + return HAL_OK; + 80030f2: 2300 movs r3, #0 + 80030f4: e01d b.n 8003132 + } + } + + /* Set the power supply configuration */ + MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); + 80030f6: 4b11 ldr r3, [pc, #68] ; (800313c ) + 80030f8: 68db ldr r3, [r3, #12] + 80030fa: f023 0207 bic.w r2, r3, #7 + 80030fe: 490f ldr r1, [pc, #60] ; (800313c ) + 8003100: 687b ldr r3, [r7, #4] + 8003102: 4313 orrs r3, r2 + 8003104: 60cb str r3, [r1, #12] + + /* Get tick */ + tickstart = HAL_GetTick (); + 8003106: f7fd ff81 bl 800100c + 800310a: 60f8 str r0, [r7, #12] + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + 800310c: e009 b.n 8003122 + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + 800310e: f7fd ff7d bl 800100c + 8003112: 4602 mov r2, r0 + 8003114: 68fb ldr r3, [r7, #12] + 8003116: 1ad3 subs r3, r2, r3 + 8003118: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 800311c: d901 bls.n 8003122 + { + return HAL_ERROR; + 800311e: 2301 movs r3, #1 + 8003120: e007 b.n 8003132 + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + 8003122: 4b06 ldr r3, [pc, #24] ; (800313c ) + 8003124: 685b ldr r3, [r3, #4] + 8003126: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 800312a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800312e: d1ee bne.n 800310e + } + } + } +#endif /* defined (SMPS) */ + + return HAL_OK; + 8003130: 2300 movs r3, #0 +} + 8003132: 4618 mov r0, r3 + 8003134: 3710 adds r7, #16 + 8003136: 46bd mov sp, r7 + 8003138: bd80 pop {r7, pc} + 800313a: bf00 nop + 800313c: 58024800 .word 0x58024800 + +08003140 : + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8003140: b580 push {r7, lr} + 8003142: b08c sub sp, #48 ; 0x30 + 8003144: af00 add r7, sp, #0 + 8003146: 6078 str r0, [r7, #4] + uint32_t tickstart; + uint32_t temp1_pllckcfg, temp2_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 8003148: 687b ldr r3, [r7, #4] + 800314a: 2b00 cmp r3, #0 + 800314c: d101 bne.n 8003152 + { + return HAL_ERROR; + 800314e: 2301 movs r3, #1 + 8003150: e3c8 b.n 80038e4 + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8003152: 687b ldr r3, [r7, #4] + 8003154: 681b ldr r3, [r3, #0] + 8003156: f003 0301 and.w r3, r3, #1 + 800315a: 2b00 cmp r3, #0 + 800315c: f000 8087 beq.w 800326e + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8003160: 4b88 ldr r3, [pc, #544] ; (8003384 ) + 8003162: 691b ldr r3, [r3, #16] + 8003164: f003 0338 and.w r3, r3, #56 ; 0x38 + 8003168: 62fb str r3, [r7, #44] ; 0x2c + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + 800316a: 4b86 ldr r3, [pc, #536] ; (8003384 ) + 800316c: 6a9b ldr r3, [r3, #40] ; 0x28 + 800316e: 62bb str r3, [r7, #40] ; 0x28 + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) + 8003170: 6afb ldr r3, [r7, #44] ; 0x2c + 8003172: 2b10 cmp r3, #16 + 8003174: d007 beq.n 8003186 + 8003176: 6afb ldr r3, [r7, #44] ; 0x2c + 8003178: 2b18 cmp r3, #24 + 800317a: d110 bne.n 800319e + 800317c: 6abb ldr r3, [r7, #40] ; 0x28 + 800317e: f003 0303 and.w r3, r3, #3 + 8003182: 2b02 cmp r3, #2 + 8003184: d10b bne.n 800319e + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8003186: 4b7f ldr r3, [pc, #508] ; (8003384 ) + 8003188: 681b ldr r3, [r3, #0] + 800318a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800318e: 2b00 cmp r3, #0 + 8003190: d06c beq.n 800326c + 8003192: 687b ldr r3, [r7, #4] + 8003194: 685b ldr r3, [r3, #4] + 8003196: 2b00 cmp r3, #0 + 8003198: d168 bne.n 800326c + { + return HAL_ERROR; + 800319a: 2301 movs r3, #1 + 800319c: e3a2 b.n 80038e4 + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 800319e: 687b ldr r3, [r7, #4] + 80031a0: 685b ldr r3, [r3, #4] + 80031a2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80031a6: d106 bne.n 80031b6 + 80031a8: 4b76 ldr r3, [pc, #472] ; (8003384 ) + 80031aa: 681b ldr r3, [r3, #0] + 80031ac: 4a75 ldr r2, [pc, #468] ; (8003384 ) + 80031ae: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80031b2: 6013 str r3, [r2, #0] + 80031b4: e02e b.n 8003214 + 80031b6: 687b ldr r3, [r7, #4] + 80031b8: 685b ldr r3, [r3, #4] + 80031ba: 2b00 cmp r3, #0 + 80031bc: d10c bne.n 80031d8 + 80031be: 4b71 ldr r3, [pc, #452] ; (8003384 ) + 80031c0: 681b ldr r3, [r3, #0] + 80031c2: 4a70 ldr r2, [pc, #448] ; (8003384 ) + 80031c4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80031c8: 6013 str r3, [r2, #0] + 80031ca: 4b6e ldr r3, [pc, #440] ; (8003384 ) + 80031cc: 681b ldr r3, [r3, #0] + 80031ce: 4a6d ldr r2, [pc, #436] ; (8003384 ) + 80031d0: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80031d4: 6013 str r3, [r2, #0] + 80031d6: e01d b.n 8003214 + 80031d8: 687b ldr r3, [r7, #4] + 80031da: 685b ldr r3, [r3, #4] + 80031dc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 80031e0: d10c bne.n 80031fc + 80031e2: 4b68 ldr r3, [pc, #416] ; (8003384 ) + 80031e4: 681b ldr r3, [r3, #0] + 80031e6: 4a67 ldr r2, [pc, #412] ; (8003384 ) + 80031e8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 80031ec: 6013 str r3, [r2, #0] + 80031ee: 4b65 ldr r3, [pc, #404] ; (8003384 ) + 80031f0: 681b ldr r3, [r3, #0] + 80031f2: 4a64 ldr r2, [pc, #400] ; (8003384 ) + 80031f4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80031f8: 6013 str r3, [r2, #0] + 80031fa: e00b b.n 8003214 + 80031fc: 4b61 ldr r3, [pc, #388] ; (8003384 ) + 80031fe: 681b ldr r3, [r3, #0] + 8003200: 4a60 ldr r2, [pc, #384] ; (8003384 ) + 8003202: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8003206: 6013 str r3, [r2, #0] + 8003208: 4b5e ldr r3, [pc, #376] ; (8003384 ) + 800320a: 681b ldr r3, [r3, #0] + 800320c: 4a5d ldr r2, [pc, #372] ; (8003384 ) + 800320e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8003212: 6013 str r3, [r2, #0] + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8003214: 687b ldr r3, [r7, #4] + 8003216: 685b ldr r3, [r3, #4] + 8003218: 2b00 cmp r3, #0 + 800321a: d013 beq.n 8003244 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800321c: f7fd fef6 bl 800100c + 8003220: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8003222: e008 b.n 8003236 + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8003224: f7fd fef2 bl 800100c + 8003228: 4602 mov r2, r0 + 800322a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800322c: 1ad3 subs r3, r2, r3 + 800322e: 2b64 cmp r3, #100 ; 0x64 + 8003230: d901 bls.n 8003236 + { + return HAL_TIMEOUT; + 8003232: 2303 movs r3, #3 + 8003234: e356 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8003236: 4b53 ldr r3, [pc, #332] ; (8003384 ) + 8003238: 681b ldr r3, [r3, #0] + 800323a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800323e: 2b00 cmp r3, #0 + 8003240: d0f0 beq.n 8003224 + 8003242: e014 b.n 800326e + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003244: f7fd fee2 bl 800100c + 8003248: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 800324a: e008 b.n 800325e + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 800324c: f7fd fede bl 800100c + 8003250: 4602 mov r2, r0 + 8003252: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003254: 1ad3 subs r3, r2, r3 + 8003256: 2b64 cmp r3, #100 ; 0x64 + 8003258: d901 bls.n 800325e + { + return HAL_TIMEOUT; + 800325a: 2303 movs r3, #3 + 800325c: e342 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 800325e: 4b49 ldr r3, [pc, #292] ; (8003384 ) + 8003260: 681b ldr r3, [r3, #0] + 8003262: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8003266: 2b00 cmp r3, #0 + 8003268: d1f0 bne.n 800324c + 800326a: e000 b.n 800326e + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 800326c: bf00 nop + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 800326e: 687b ldr r3, [r7, #4] + 8003270: 681b ldr r3, [r3, #0] + 8003272: f003 0302 and.w r3, r3, #2 + 8003276: 2b00 cmp r3, #0 + 8003278: f000 808c beq.w 8003394 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* When the HSI is used as system clock it will not be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 800327c: 4b41 ldr r3, [pc, #260] ; (8003384 ) + 800327e: 691b ldr r3, [r3, #16] + 8003280: f003 0338 and.w r3, r3, #56 ; 0x38 + 8003284: 623b str r3, [r7, #32] + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + 8003286: 4b3f ldr r3, [pc, #252] ; (8003384 ) + 8003288: 6a9b ldr r3, [r3, #40] ; 0x28 + 800328a: 61fb str r3, [r7, #28] + if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) + 800328c: 6a3b ldr r3, [r7, #32] + 800328e: 2b00 cmp r3, #0 + 8003290: d007 beq.n 80032a2 + 8003292: 6a3b ldr r3, [r7, #32] + 8003294: 2b18 cmp r3, #24 + 8003296: d137 bne.n 8003308 + 8003298: 69fb ldr r3, [r7, #28] + 800329a: f003 0303 and.w r3, r3, #3 + 800329e: 2b00 cmp r3, #0 + 80032a0: d132 bne.n 8003308 + { + /* When HSI is used as system clock it will not be disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + 80032a2: 4b38 ldr r3, [pc, #224] ; (8003384 ) + 80032a4: 681b ldr r3, [r3, #0] + 80032a6: f003 0304 and.w r3, r3, #4 + 80032aa: 2b00 cmp r3, #0 + 80032ac: d005 beq.n 80032ba + 80032ae: 687b ldr r3, [r7, #4] + 80032b0: 68db ldr r3, [r3, #12] + 80032b2: 2b00 cmp r3, #0 + 80032b4: d101 bne.n 80032ba + { + return HAL_ERROR; + 80032b6: 2301 movs r3, #1 + 80032b8: e314 b.n 80038e4 + } + /* Otherwise, only HSI division and calibration are allowed */ + else + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + 80032ba: 4b32 ldr r3, [pc, #200] ; (8003384 ) + 80032bc: 681b ldr r3, [r3, #0] + 80032be: f023 0219 bic.w r2, r3, #25 + 80032c2: 687b ldr r3, [r7, #4] + 80032c4: 68db ldr r3, [r3, #12] + 80032c6: 492f ldr r1, [pc, #188] ; (8003384 ) + 80032c8: 4313 orrs r3, r2 + 80032ca: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80032cc: f7fd fe9e bl 800100c + 80032d0: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80032d2: e008 b.n 80032e6 + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 80032d4: f7fd fe9a bl 800100c + 80032d8: 4602 mov r2, r0 + 80032da: 6a7b ldr r3, [r7, #36] ; 0x24 + 80032dc: 1ad3 subs r3, r2, r3 + 80032de: 2b02 cmp r3, #2 + 80032e0: d901 bls.n 80032e6 + { + return HAL_TIMEOUT; + 80032e2: 2303 movs r3, #3 + 80032e4: e2fe b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 80032e6: 4b27 ldr r3, [pc, #156] ; (8003384 ) + 80032e8: 681b ldr r3, [r3, #0] + 80032ea: f003 0304 and.w r3, r3, #4 + 80032ee: 2b00 cmp r3, #0 + 80032f0: d0f0 beq.n 80032d4 + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 80032f2: 4b24 ldr r3, [pc, #144] ; (8003384 ) + 80032f4: 685b ldr r3, [r3, #4] + 80032f6: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 + 80032fa: 687b ldr r3, [r7, #4] + 80032fc: 691b ldr r3, [r3, #16] + 80032fe: 061b lsls r3, r3, #24 + 8003300: 4920 ldr r1, [pc, #128] ; (8003384 ) + 8003302: 4313 orrs r3, r2 + 8003304: 604b str r3, [r1, #4] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + 8003306: e045 b.n 8003394 + } + + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + 8003308: 687b ldr r3, [r7, #4] + 800330a: 68db ldr r3, [r3, #12] + 800330c: 2b00 cmp r3, #0 + 800330e: d026 beq.n 800335e + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + 8003310: 4b1c ldr r3, [pc, #112] ; (8003384 ) + 8003312: 681b ldr r3, [r3, #0] + 8003314: f023 0219 bic.w r2, r3, #25 + 8003318: 687b ldr r3, [r7, #4] + 800331a: 68db ldr r3, [r3, #12] + 800331c: 4919 ldr r1, [pc, #100] ; (8003384 ) + 800331e: 4313 orrs r3, r2 + 8003320: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003322: f7fd fe73 bl 800100c + 8003326: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8003328: e008 b.n 800333c + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 800332a: f7fd fe6f bl 800100c + 800332e: 4602 mov r2, r0 + 8003330: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003332: 1ad3 subs r3, r2, r3 + 8003334: 2b02 cmp r3, #2 + 8003336: d901 bls.n 800333c + { + return HAL_TIMEOUT; + 8003338: 2303 movs r3, #3 + 800333a: e2d3 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800333c: 4b11 ldr r3, [pc, #68] ; (8003384 ) + 800333e: 681b ldr r3, [r3, #0] + 8003340: f003 0304 and.w r3, r3, #4 + 8003344: 2b00 cmp r3, #0 + 8003346: d0f0 beq.n 800332a + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8003348: 4b0e ldr r3, [pc, #56] ; (8003384 ) + 800334a: 685b ldr r3, [r3, #4] + 800334c: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 + 8003350: 687b ldr r3, [r7, #4] + 8003352: 691b ldr r3, [r3, #16] + 8003354: 061b lsls r3, r3, #24 + 8003356: 490b ldr r1, [pc, #44] ; (8003384 ) + 8003358: 4313 orrs r3, r2 + 800335a: 604b str r3, [r1, #4] + 800335c: e01a b.n 8003394 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 800335e: 4b09 ldr r3, [pc, #36] ; (8003384 ) + 8003360: 681b ldr r3, [r3, #0] + 8003362: 4a08 ldr r2, [pc, #32] ; (8003384 ) + 8003364: f023 0301 bic.w r3, r3, #1 + 8003368: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800336a: f7fd fe4f bl 800100c + 800336e: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8003370: e00a b.n 8003388 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8003372: f7fd fe4b bl 800100c + 8003376: 4602 mov r2, r0 + 8003378: 6a7b ldr r3, [r7, #36] ; 0x24 + 800337a: 1ad3 subs r3, r2, r3 + 800337c: 2b02 cmp r3, #2 + 800337e: d903 bls.n 8003388 + { + return HAL_TIMEOUT; + 8003380: 2303 movs r3, #3 + 8003382: e2af b.n 80038e4 + 8003384: 58024400 .word 0x58024400 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8003388: 4b96 ldr r3, [pc, #600] ; (80035e4 ) + 800338a: 681b ldr r3, [r3, #0] + 800338c: f003 0304 and.w r3, r3, #4 + 8003390: 2b00 cmp r3, #0 + 8003392: d1ee bne.n 8003372 + } + } + } + } + /*----------------------------- CSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + 8003394: 687b ldr r3, [r7, #4] + 8003396: 681b ldr r3, [r3, #0] + 8003398: f003 0310 and.w r3, r3, #16 + 800339c: 2b00 cmp r3, #0 + 800339e: d06a beq.n 8003476 + /* Check the parameters */ + assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); + assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); + + /* When the CSI is used as system clock it will not disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80033a0: 4b90 ldr r3, [pc, #576] ; (80035e4 ) + 80033a2: 691b ldr r3, [r3, #16] + 80033a4: f003 0338 and.w r3, r3, #56 ; 0x38 + 80033a8: 61bb str r3, [r7, #24] + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + 80033aa: 4b8e ldr r3, [pc, #568] ; (80035e4 ) + 80033ac: 6a9b ldr r3, [r3, #40] ; 0x28 + 80033ae: 617b str r3, [r7, #20] + if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) + 80033b0: 69bb ldr r3, [r7, #24] + 80033b2: 2b08 cmp r3, #8 + 80033b4: d007 beq.n 80033c6 + 80033b6: 69bb ldr r3, [r7, #24] + 80033b8: 2b18 cmp r3, #24 + 80033ba: d11b bne.n 80033f4 + 80033bc: 697b ldr r3, [r7, #20] + 80033be: f003 0303 and.w r3, r3, #3 + 80033c2: 2b01 cmp r3, #1 + 80033c4: d116 bne.n 80033f4 + { + /* When CSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) + 80033c6: 4b87 ldr r3, [pc, #540] ; (80035e4 ) + 80033c8: 681b ldr r3, [r3, #0] + 80033ca: f403 7380 and.w r3, r3, #256 ; 0x100 + 80033ce: 2b00 cmp r3, #0 + 80033d0: d005 beq.n 80033de + 80033d2: 687b ldr r3, [r7, #4] + 80033d4: 69db ldr r3, [r3, #28] + 80033d6: 2b80 cmp r3, #128 ; 0x80 + 80033d8: d001 beq.n 80033de + { + return HAL_ERROR; + 80033da: 2301 movs r3, #1 + 80033dc: e282 b.n 80038e4 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + 80033de: 4b81 ldr r3, [pc, #516] ; (80035e4 ) + 80033e0: 68db ldr r3, [r3, #12] + 80033e2: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 + 80033e6: 687b ldr r3, [r7, #4] + 80033e8: 6a1b ldr r3, [r3, #32] + 80033ea: 061b lsls r3, r3, #24 + 80033ec: 497d ldr r1, [pc, #500] ; (80035e4 ) + 80033ee: 4313 orrs r3, r2 + 80033f0: 60cb str r3, [r1, #12] + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) + 80033f2: e040 b.n 8003476 + } + } + else + { + /* Check the CSI State */ + if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) + 80033f4: 687b ldr r3, [r7, #4] + 80033f6: 69db ldr r3, [r3, #28] + 80033f8: 2b00 cmp r3, #0 + 80033fa: d023 beq.n 8003444 + { + /* Enable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_ENABLE(); + 80033fc: 4b79 ldr r3, [pc, #484] ; (80035e4 ) + 80033fe: 681b ldr r3, [r3, #0] + 8003400: 4a78 ldr r2, [pc, #480] ; (80035e4 ) + 8003402: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8003406: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003408: f7fd fe00 bl 800100c + 800340c: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till CSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + 800340e: e008 b.n 8003422 + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + 8003410: f7fd fdfc bl 800100c + 8003414: 4602 mov r2, r0 + 8003416: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003418: 1ad3 subs r3, r2, r3 + 800341a: 2b02 cmp r3, #2 + 800341c: d901 bls.n 8003422 + { + return HAL_TIMEOUT; + 800341e: 2303 movs r3, #3 + 8003420: e260 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + 8003422: 4b70 ldr r3, [pc, #448] ; (80035e4 ) + 8003424: 681b ldr r3, [r3, #0] + 8003426: f403 7380 and.w r3, r3, #256 ; 0x100 + 800342a: 2b00 cmp r3, #0 + 800342c: d0f0 beq.n 8003410 + } + } + + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + 800342e: 4b6d ldr r3, [pc, #436] ; (80035e4 ) + 8003430: 68db ldr r3, [r3, #12] + 8003432: f023 527c bic.w r2, r3, #1056964608 ; 0x3f000000 + 8003436: 687b ldr r3, [r7, #4] + 8003438: 6a1b ldr r3, [r3, #32] + 800343a: 061b lsls r3, r3, #24 + 800343c: 4969 ldr r1, [pc, #420] ; (80035e4 ) + 800343e: 4313 orrs r3, r2 + 8003440: 60cb str r3, [r1, #12] + 8003442: e018 b.n 8003476 + } + else + { + /* Disable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_DISABLE(); + 8003444: 4b67 ldr r3, [pc, #412] ; (80035e4 ) + 8003446: 681b ldr r3, [r3, #0] + 8003448: 4a66 ldr r2, [pc, #408] ; (80035e4 ) + 800344a: f023 0380 bic.w r3, r3, #128 ; 0x80 + 800344e: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003450: f7fd fddc bl 800100c + 8003454: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till CSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) + 8003456: e008 b.n 800346a + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + 8003458: f7fd fdd8 bl 800100c + 800345c: 4602 mov r2, r0 + 800345e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003460: 1ad3 subs r3, r2, r3 + 8003462: 2b02 cmp r3, #2 + 8003464: d901 bls.n 800346a + { + return HAL_TIMEOUT; + 8003466: 2303 movs r3, #3 + 8003468: e23c b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) + 800346a: 4b5e ldr r3, [pc, #376] ; (80035e4 ) + 800346c: 681b ldr r3, [r3, #0] + 800346e: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003472: 2b00 cmp r3, #0 + 8003474: d1f0 bne.n 8003458 + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8003476: 687b ldr r3, [r7, #4] + 8003478: 681b ldr r3, [r3, #0] + 800347a: f003 0308 and.w r3, r3, #8 + 800347e: 2b00 cmp r3, #0 + 8003480: d036 beq.n 80034f0 + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + 8003482: 687b ldr r3, [r7, #4] + 8003484: 695b ldr r3, [r3, #20] + 8003486: 2b00 cmp r3, #0 + 8003488: d019 beq.n 80034be + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 800348a: 4b56 ldr r3, [pc, #344] ; (80035e4 ) + 800348c: 6f5b ldr r3, [r3, #116] ; 0x74 + 800348e: 4a55 ldr r2, [pc, #340] ; (80035e4 ) + 8003490: f043 0301 orr.w r3, r3, #1 + 8003494: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003496: f7fd fdb9 bl 800100c + 800349a: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 800349c: e008 b.n 80034b0 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 800349e: f7fd fdb5 bl 800100c + 80034a2: 4602 mov r2, r0 + 80034a4: 6a7b ldr r3, [r7, #36] ; 0x24 + 80034a6: 1ad3 subs r3, r2, r3 + 80034a8: 2b02 cmp r3, #2 + 80034aa: d901 bls.n 80034b0 + { + return HAL_TIMEOUT; + 80034ac: 2303 movs r3, #3 + 80034ae: e219 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 80034b0: 4b4c ldr r3, [pc, #304] ; (80035e4 ) + 80034b2: 6f5b ldr r3, [r3, #116] ; 0x74 + 80034b4: f003 0302 and.w r3, r3, #2 + 80034b8: 2b00 cmp r3, #0 + 80034ba: d0f0 beq.n 800349e + 80034bc: e018 b.n 80034f0 + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 80034be: 4b49 ldr r3, [pc, #292] ; (80035e4 ) + 80034c0: 6f5b ldr r3, [r3, #116] ; 0x74 + 80034c2: 4a48 ldr r2, [pc, #288] ; (80035e4 ) + 80034c4: f023 0301 bic.w r3, r3, #1 + 80034c8: 6753 str r3, [r2, #116] ; 0x74 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80034ca: f7fd fd9f bl 800100c + 80034ce: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 80034d0: e008 b.n 80034e4 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 80034d2: f7fd fd9b bl 800100c + 80034d6: 4602 mov r2, r0 + 80034d8: 6a7b ldr r3, [r7, #36] ; 0x24 + 80034da: 1ad3 subs r3, r2, r3 + 80034dc: 2b02 cmp r3, #2 + 80034de: d901 bls.n 80034e4 + { + return HAL_TIMEOUT; + 80034e0: 2303 movs r3, #3 + 80034e2: e1ff b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 80034e4: 4b3f ldr r3, [pc, #252] ; (80035e4 ) + 80034e6: 6f5b ldr r3, [r3, #116] ; 0x74 + 80034e8: f003 0302 and.w r3, r3, #2 + 80034ec: 2b00 cmp r3, #0 + 80034ee: d1f0 bne.n 80034d2 + } + } + } + + /*------------------------------ HSI48 Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + 80034f0: 687b ldr r3, [r7, #4] + 80034f2: 681b ldr r3, [r3, #0] + 80034f4: f003 0320 and.w r3, r3, #32 + 80034f8: 2b00 cmp r3, #0 + 80034fa: d036 beq.n 800356a + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) + 80034fc: 687b ldr r3, [r7, #4] + 80034fe: 699b ldr r3, [r3, #24] + 8003500: 2b00 cmp r3, #0 + 8003502: d019 beq.n 8003538 + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + 8003504: 4b37 ldr r3, [pc, #220] ; (80035e4 ) + 8003506: 681b ldr r3, [r3, #0] + 8003508: 4a36 ldr r2, [pc, #216] ; (80035e4 ) + 800350a: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 800350e: 6013 str r3, [r2, #0] + + /* Get time-out */ + tickstart = HAL_GetTick(); + 8003510: f7fd fd7c bl 800100c + 8003514: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) + 8003516: e008 b.n 800352a + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 8003518: f7fd fd78 bl 800100c + 800351c: 4602 mov r2, r0 + 800351e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003520: 1ad3 subs r3, r2, r3 + 8003522: 2b02 cmp r3, #2 + 8003524: d901 bls.n 800352a + { + return HAL_TIMEOUT; + 8003526: 2303 movs r3, #3 + 8003528: e1dc b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) + 800352a: 4b2e ldr r3, [pc, #184] ; (80035e4 ) + 800352c: 681b ldr r3, [r3, #0] + 800352e: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8003532: 2b00 cmp r3, #0 + 8003534: d0f0 beq.n 8003518 + 8003536: e018 b.n 800356a + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + 8003538: 4b2a ldr r3, [pc, #168] ; (80035e4 ) + 800353a: 681b ldr r3, [r3, #0] + 800353c: 4a29 ldr r2, [pc, #164] ; (80035e4 ) + 800353e: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8003542: 6013 str r3, [r2, #0] + + /* Get time-out */ + tickstart = HAL_GetTick(); + 8003544: f7fd fd62 bl 800100c + 8003548: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) + 800354a: e008 b.n 800355e + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + 800354c: f7fd fd5e bl 800100c + 8003550: 4602 mov r2, r0 + 8003552: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003554: 1ad3 subs r3, r2, r3 + 8003556: 2b02 cmp r3, #2 + 8003558: d901 bls.n 800355e + { + return HAL_TIMEOUT; + 800355a: 2303 movs r3, #3 + 800355c: e1c2 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) + 800355e: 4b21 ldr r3, [pc, #132] ; (80035e4 ) + 8003560: 681b ldr r3, [r3, #0] + 8003562: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8003566: 2b00 cmp r3, #0 + 8003568: d1f0 bne.n 800354c + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 800356a: 687b ldr r3, [r7, #4] + 800356c: 681b ldr r3, [r3, #0] + 800356e: f003 0304 and.w r3, r3, #4 + 8003572: 2b00 cmp r3, #0 + 8003574: f000 8086 beq.w 8003684 + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + 8003578: 4b1b ldr r3, [pc, #108] ; (80035e8 ) + 800357a: 681b ldr r3, [r3, #0] + 800357c: 4a1a ldr r2, [pc, #104] ; (80035e8 ) + 800357e: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003582: 6013 str r3, [r2, #0] + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8003584: f7fd fd42 bl 800100c + 8003588: 6278 str r0, [r7, #36] ; 0x24 + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + 800358a: e008 b.n 800359e + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 800358c: f7fd fd3e bl 800100c + 8003590: 4602 mov r2, r0 + 8003592: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003594: 1ad3 subs r3, r2, r3 + 8003596: 2b64 cmp r3, #100 ; 0x64 + 8003598: d901 bls.n 800359e + { + return HAL_TIMEOUT; + 800359a: 2303 movs r3, #3 + 800359c: e1a2 b.n 80038e4 + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + 800359e: 4b12 ldr r3, [pc, #72] ; (80035e8 ) + 80035a0: 681b ldr r3, [r3, #0] + 80035a2: f403 7380 and.w r3, r3, #256 ; 0x100 + 80035a6: 2b00 cmp r3, #0 + 80035a8: d0f0 beq.n 800358c + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 80035aa: 687b ldr r3, [r7, #4] + 80035ac: 689b ldr r3, [r3, #8] + 80035ae: 2b01 cmp r3, #1 + 80035b0: d106 bne.n 80035c0 + 80035b2: 4b0c ldr r3, [pc, #48] ; (80035e4 ) + 80035b4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80035b6: 4a0b ldr r2, [pc, #44] ; (80035e4 ) + 80035b8: f043 0301 orr.w r3, r3, #1 + 80035bc: 6713 str r3, [r2, #112] ; 0x70 + 80035be: e032 b.n 8003626 + 80035c0: 687b ldr r3, [r7, #4] + 80035c2: 689b ldr r3, [r3, #8] + 80035c4: 2b00 cmp r3, #0 + 80035c6: d111 bne.n 80035ec + 80035c8: 4b06 ldr r3, [pc, #24] ; (80035e4 ) + 80035ca: 6f1b ldr r3, [r3, #112] ; 0x70 + 80035cc: 4a05 ldr r2, [pc, #20] ; (80035e4 ) + 80035ce: f023 0301 bic.w r3, r3, #1 + 80035d2: 6713 str r3, [r2, #112] ; 0x70 + 80035d4: 4b03 ldr r3, [pc, #12] ; (80035e4 ) + 80035d6: 6f1b ldr r3, [r3, #112] ; 0x70 + 80035d8: 4a02 ldr r2, [pc, #8] ; (80035e4 ) + 80035da: f023 0304 bic.w r3, r3, #4 + 80035de: 6713 str r3, [r2, #112] ; 0x70 + 80035e0: e021 b.n 8003626 + 80035e2: bf00 nop + 80035e4: 58024400 .word 0x58024400 + 80035e8: 58024800 .word 0x58024800 + 80035ec: 687b ldr r3, [r7, #4] + 80035ee: 689b ldr r3, [r3, #8] + 80035f0: 2b05 cmp r3, #5 + 80035f2: d10c bne.n 800360e + 80035f4: 4b83 ldr r3, [pc, #524] ; (8003804 ) + 80035f6: 6f1b ldr r3, [r3, #112] ; 0x70 + 80035f8: 4a82 ldr r2, [pc, #520] ; (8003804 ) + 80035fa: f043 0304 orr.w r3, r3, #4 + 80035fe: 6713 str r3, [r2, #112] ; 0x70 + 8003600: 4b80 ldr r3, [pc, #512] ; (8003804 ) + 8003602: 6f1b ldr r3, [r3, #112] ; 0x70 + 8003604: 4a7f ldr r2, [pc, #508] ; (8003804 ) + 8003606: f043 0301 orr.w r3, r3, #1 + 800360a: 6713 str r3, [r2, #112] ; 0x70 + 800360c: e00b b.n 8003626 + 800360e: 4b7d ldr r3, [pc, #500] ; (8003804 ) + 8003610: 6f1b ldr r3, [r3, #112] ; 0x70 + 8003612: 4a7c ldr r2, [pc, #496] ; (8003804 ) + 8003614: f023 0301 bic.w r3, r3, #1 + 8003618: 6713 str r3, [r2, #112] ; 0x70 + 800361a: 4b7a ldr r3, [pc, #488] ; (8003804 ) + 800361c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800361e: 4a79 ldr r2, [pc, #484] ; (8003804 ) + 8003620: f023 0304 bic.w r3, r3, #4 + 8003624: 6713 str r3, [r2, #112] ; 0x70 + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 8003626: 687b ldr r3, [r7, #4] + 8003628: 689b ldr r3, [r3, #8] + 800362a: 2b00 cmp r3, #0 + 800362c: d015 beq.n 800365a + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800362e: f7fd fced bl 800100c + 8003632: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8003634: e00a b.n 800364c + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003636: f7fd fce9 bl 800100c + 800363a: 4602 mov r2, r0 + 800363c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800363e: 1ad3 subs r3, r2, r3 + 8003640: f241 3288 movw r2, #5000 ; 0x1388 + 8003644: 4293 cmp r3, r2 + 8003646: d901 bls.n 800364c + { + return HAL_TIMEOUT; + 8003648: 2303 movs r3, #3 + 800364a: e14b b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800364c: 4b6d ldr r3, [pc, #436] ; (8003804 ) + 800364e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8003650: f003 0302 and.w r3, r3, #2 + 8003654: 2b00 cmp r3, #0 + 8003656: d0ee beq.n 8003636 + 8003658: e014 b.n 8003684 + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 800365a: f7fd fcd7 bl 800100c + 800365e: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8003660: e00a b.n 8003678 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003662: f7fd fcd3 bl 800100c + 8003666: 4602 mov r2, r0 + 8003668: 6a7b ldr r3, [r7, #36] ; 0x24 + 800366a: 1ad3 subs r3, r2, r3 + 800366c: f241 3288 movw r2, #5000 ; 0x1388 + 8003670: 4293 cmp r3, r2 + 8003672: d901 bls.n 8003678 + { + return HAL_TIMEOUT; + 8003674: 2303 movs r3, #3 + 8003676: e135 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8003678: 4b62 ldr r3, [pc, #392] ; (8003804 ) + 800367a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800367c: f003 0302 and.w r3, r3, #2 + 8003680: 2b00 cmp r3, #0 + 8003682: d1ee bne.n 8003662 + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8003684: 687b ldr r3, [r7, #4] + 8003686: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003688: 2b00 cmp r3, #0 + 800368a: f000 812a beq.w 80038e2 + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) + 800368e: 4b5d ldr r3, [pc, #372] ; (8003804 ) + 8003690: 691b ldr r3, [r3, #16] + 8003692: f003 0338 and.w r3, r3, #56 ; 0x38 + 8003696: 2b18 cmp r3, #24 + 8003698: f000 80ba beq.w 8003810 + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 800369c: 687b ldr r3, [r7, #4] + 800369e: 6a5b ldr r3, [r3, #36] ; 0x24 + 80036a0: 2b02 cmp r3, #2 + 80036a2: f040 8095 bne.w 80037d0 + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80036a6: 4b57 ldr r3, [pc, #348] ; (8003804 ) + 80036a8: 681b ldr r3, [r3, #0] + 80036aa: 4a56 ldr r2, [pc, #344] ; (8003804 ) + 80036ac: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 80036b0: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80036b2: f7fd fcab bl 800100c + 80036b6: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80036b8: e008 b.n 80036cc + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80036ba: f7fd fca7 bl 800100c + 80036be: 4602 mov r2, r0 + 80036c0: 6a7b ldr r3, [r7, #36] ; 0x24 + 80036c2: 1ad3 subs r3, r2, r3 + 80036c4: 2b02 cmp r3, #2 + 80036c6: d901 bls.n 80036cc + { + return HAL_TIMEOUT; + 80036c8: 2303 movs r3, #3 + 80036ca: e10b b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80036cc: 4b4d ldr r3, [pc, #308] ; (8003804 ) + 80036ce: 681b ldr r3, [r3, #0] + 80036d0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80036d4: 2b00 cmp r3, #0 + 80036d6: d1f0 bne.n 80036ba + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 80036d8: 4b4a ldr r3, [pc, #296] ; (8003804 ) + 80036da: 6a9a ldr r2, [r3, #40] ; 0x28 + 80036dc: 4b4a ldr r3, [pc, #296] ; (8003808 ) + 80036de: 4013 ands r3, r2 + 80036e0: 687a ldr r2, [r7, #4] + 80036e2: 6a91 ldr r1, [r2, #40] ; 0x28 + 80036e4: 687a ldr r2, [r7, #4] + 80036e6: 6ad2 ldr r2, [r2, #44] ; 0x2c + 80036e8: 0112 lsls r2, r2, #4 + 80036ea: 430a orrs r2, r1 + 80036ec: 4945 ldr r1, [pc, #276] ; (8003804 ) + 80036ee: 4313 orrs r3, r2 + 80036f0: 628b str r3, [r1, #40] ; 0x28 + 80036f2: 687b ldr r3, [r7, #4] + 80036f4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80036f6: 3b01 subs r3, #1 + 80036f8: f3c3 0208 ubfx r2, r3, #0, #9 + 80036fc: 687b ldr r3, [r7, #4] + 80036fe: 6b5b ldr r3, [r3, #52] ; 0x34 + 8003700: 3b01 subs r3, #1 + 8003702: 025b lsls r3, r3, #9 + 8003704: b29b uxth r3, r3 + 8003706: 431a orrs r2, r3 + 8003708: 687b ldr r3, [r7, #4] + 800370a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800370c: 3b01 subs r3, #1 + 800370e: 041b lsls r3, r3, #16 + 8003710: f403 03fe and.w r3, r3, #8323072 ; 0x7f0000 + 8003714: 431a orrs r2, r3 + 8003716: 687b ldr r3, [r7, #4] + 8003718: 6bdb ldr r3, [r3, #60] ; 0x3c + 800371a: 3b01 subs r3, #1 + 800371c: 061b lsls r3, r3, #24 + 800371e: f003 43fe and.w r3, r3, #2130706432 ; 0x7f000000 + 8003722: 4938 ldr r1, [pc, #224] ; (8003804 ) + 8003724: 4313 orrs r3, r2 + 8003726: 630b str r3, [r1, #48] ; 0x30 + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Disable PLLFRACN . */ + __HAL_RCC_PLLFRACN_DISABLE(); + 8003728: 4b36 ldr r3, [pc, #216] ; (8003804 ) + 800372a: 6adb ldr r3, [r3, #44] ; 0x2c + 800372c: 4a35 ldr r2, [pc, #212] ; (8003804 ) + 800372e: f023 0301 bic.w r3, r3, #1 + 8003732: 62d3 str r3, [r2, #44] ; 0x2c + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + 8003734: 4b33 ldr r3, [pc, #204] ; (8003804 ) + 8003736: 6b5a ldr r2, [r3, #52] ; 0x34 + 8003738: 4b34 ldr r3, [pc, #208] ; (800380c ) + 800373a: 4013 ands r3, r2 + 800373c: 687a ldr r2, [r7, #4] + 800373e: 6c92 ldr r2, [r2, #72] ; 0x48 + 8003740: 00d2 lsls r2, r2, #3 + 8003742: 4930 ldr r1, [pc, #192] ; (8003804 ) + 8003744: 4313 orrs r3, r2 + 8003746: 634b str r3, [r1, #52] ; 0x34 + + /* Select PLL1 input reference frequency range: VCI */ + __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; + 8003748: 4b2e ldr r3, [pc, #184] ; (8003804 ) + 800374a: 6adb ldr r3, [r3, #44] ; 0x2c + 800374c: f023 020c bic.w r2, r3, #12 + 8003750: 687b ldr r3, [r7, #4] + 8003752: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003754: 492b ldr r1, [pc, #172] ; (8003804 ) + 8003756: 4313 orrs r3, r2 + 8003758: 62cb str r3, [r1, #44] ; 0x2c + + /* Select PLL1 output frequency range : VCO */ + __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; + 800375a: 4b2a ldr r3, [pc, #168] ; (8003804 ) + 800375c: 6adb ldr r3, [r3, #44] ; 0x2c + 800375e: f023 0202 bic.w r2, r3, #2 + 8003762: 687b ldr r3, [r7, #4] + 8003764: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003766: 4927 ldr r1, [pc, #156] ; (8003804 ) + 8003768: 4313 orrs r3, r2 + 800376a: 62cb str r3, [r1, #44] ; 0x2c + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + 800376c: 4b25 ldr r3, [pc, #148] ; (8003804 ) + 800376e: 6adb ldr r3, [r3, #44] ; 0x2c + 8003770: 4a24 ldr r2, [pc, #144] ; (8003804 ) + 8003772: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8003776: 62d3 str r3, [r2, #44] ; 0x2c + + /* Enable PLL1Q Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + 8003778: 4b22 ldr r3, [pc, #136] ; (8003804 ) + 800377a: 6adb ldr r3, [r3, #44] ; 0x2c + 800377c: 4a21 ldr r2, [pc, #132] ; (8003804 ) + 800377e: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8003782: 62d3 str r3, [r2, #44] ; 0x2c + + /* Enable PLL1R Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + 8003784: 4b1f ldr r3, [pc, #124] ; (8003804 ) + 8003786: 6adb ldr r3, [r3, #44] ; 0x2c + 8003788: 4a1e ldr r2, [pc, #120] ; (8003804 ) + 800378a: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 800378e: 62d3 str r3, [r2, #44] ; 0x2c + + /* Enable PLL1FRACN . */ + __HAL_RCC_PLLFRACN_ENABLE(); + 8003790: 4b1c ldr r3, [pc, #112] ; (8003804 ) + 8003792: 6adb ldr r3, [r3, #44] ; 0x2c + 8003794: 4a1b ldr r2, [pc, #108] ; (8003804 ) + 8003796: f043 0301 orr.w r3, r3, #1 + 800379a: 62d3 str r3, [r2, #44] ; 0x2c + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 800379c: 4b19 ldr r3, [pc, #100] ; (8003804 ) + 800379e: 681b ldr r3, [r3, #0] + 80037a0: 4a18 ldr r2, [pc, #96] ; (8003804 ) + 80037a2: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 80037a6: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80037a8: f7fd fc30 bl 800100c + 80037ac: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 80037ae: e008 b.n 80037c2 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80037b0: f7fd fc2c bl 800100c + 80037b4: 4602 mov r2, r0 + 80037b6: 6a7b ldr r3, [r7, #36] ; 0x24 + 80037b8: 1ad3 subs r3, r2, r3 + 80037ba: 2b02 cmp r3, #2 + 80037bc: d901 bls.n 80037c2 + { + return HAL_TIMEOUT; + 80037be: 2303 movs r3, #3 + 80037c0: e090 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 80037c2: 4b10 ldr r3, [pc, #64] ; (8003804 ) + 80037c4: 681b ldr r3, [r3, #0] + 80037c6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80037ca: 2b00 cmp r3, #0 + 80037cc: d0f0 beq.n 80037b0 + 80037ce: e088 b.n 80038e2 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 80037d0: 4b0c ldr r3, [pc, #48] ; (8003804 ) + 80037d2: 681b ldr r3, [r3, #0] + 80037d4: 4a0b ldr r2, [pc, #44] ; (8003804 ) + 80037d6: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 80037da: 6013 str r3, [r2, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80037dc: f7fd fc16 bl 800100c + 80037e0: 6278 str r0, [r7, #36] ; 0x24 + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80037e2: e008 b.n 80037f6 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 80037e4: f7fd fc12 bl 800100c + 80037e8: 4602 mov r2, r0 + 80037ea: 6a7b ldr r3, [r7, #36] ; 0x24 + 80037ec: 1ad3 subs r3, r2, r3 + 80037ee: 2b02 cmp r3, #2 + 80037f0: d901 bls.n 80037f6 + { + return HAL_TIMEOUT; + 80037f2: 2303 movs r3, #3 + 80037f4: e076 b.n 80038e4 + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 80037f6: 4b03 ldr r3, [pc, #12] ; (8003804 ) + 80037f8: 681b ldr r3, [r3, #0] + 80037fa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80037fe: 2b00 cmp r3, #0 + 8003800: d1f0 bne.n 80037e4 + 8003802: e06e b.n 80038e2 + 8003804: 58024400 .word 0x58024400 + 8003808: fffffc0c .word 0xfffffc0c + 800380c: ffff0007 .word 0xffff0007 + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLLCKSELR; + 8003810: 4b36 ldr r3, [pc, #216] ; (80038ec ) + 8003812: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003814: 613b str r3, [r7, #16] + temp2_pllckcfg = RCC->PLL1DIVR; + 8003816: 4b35 ldr r3, [pc, #212] ; (80038ec ) + 8003818: 6b1b ldr r3, [r3, #48] ; 0x30 + 800381a: 60fb str r3, [r7, #12] + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 800381c: 687b ldr r3, [r7, #4] + 800381e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003820: 2b01 cmp r3, #1 + 8003822: d031 beq.n 8003888 + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8003824: 693b ldr r3, [r7, #16] + 8003826: f003 0203 and.w r2, r3, #3 + 800382a: 687b ldr r3, [r7, #4] + 800382c: 6a9b ldr r3, [r3, #40] ; 0x28 + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + 800382e: 429a cmp r2, r3 + 8003830: d12a bne.n 8003888 + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + 8003832: 693b ldr r3, [r7, #16] + 8003834: 091b lsrs r3, r3, #4 + 8003836: f003 023f and.w r2, r3, #63 ; 0x3f + 800383a: 687b ldr r3, [r7, #4] + 800383c: 6adb ldr r3, [r3, #44] ; 0x2c + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 800383e: 429a cmp r2, r3 + 8003840: d122 bne.n 8003888 + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + 8003842: 68fb ldr r3, [r7, #12] + 8003844: f3c3 0208 ubfx r2, r3, #0, #9 + 8003848: 687b ldr r3, [r7, #4] + 800384a: 6b1b ldr r3, [r3, #48] ; 0x30 + 800384c: 3b01 subs r3, #1 + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + 800384e: 429a cmp r2, r3 + 8003850: d11a bne.n 8003888 + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + 8003852: 68fb ldr r3, [r7, #12] + 8003854: 0a5b lsrs r3, r3, #9 + 8003856: f003 027f and.w r2, r3, #127 ; 0x7f + 800385a: 687b ldr r3, [r7, #4] + 800385c: 6b5b ldr r3, [r3, #52] ; 0x34 + 800385e: 3b01 subs r3, #1 + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + 8003860: 429a cmp r2, r3 + 8003862: d111 bne.n 8003888 + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + 8003864: 68fb ldr r3, [r7, #12] + 8003866: 0c1b lsrs r3, r3, #16 + 8003868: f003 027f and.w r2, r3, #127 ; 0x7f + 800386c: 687b ldr r3, [r7, #4] + 800386e: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003870: 3b01 subs r3, #1 + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + 8003872: 429a cmp r2, r3 + 8003874: d108 bne.n 8003888 + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) + 8003876: 68fb ldr r3, [r7, #12] + 8003878: 0e1b lsrs r3, r3, #24 + 800387a: f003 027f and.w r2, r3, #127 ; 0x7f + 800387e: 687b ldr r3, [r7, #4] + 8003880: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003882: 3b01 subs r3, #1 + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + 8003884: 429a cmp r2, r3 + 8003886: d001 beq.n 800388c + { + return HAL_ERROR; + 8003888: 2301 movs r3, #1 + 800388a: e02b b.n 80038e4 + } + else + { + /* Check if only fractional part needs to be updated */ + temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); + 800388c: 4b17 ldr r3, [pc, #92] ; (80038ec ) + 800388e: 6b5b ldr r3, [r3, #52] ; 0x34 + 8003890: 08db lsrs r3, r3, #3 + 8003892: f3c3 030c ubfx r3, r3, #0, #13 + 8003896: 613b str r3, [r7, #16] + if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) + 8003898: 687b ldr r3, [r7, #4] + 800389a: 6c9b ldr r3, [r3, #72] ; 0x48 + 800389c: 693a ldr r2, [r7, #16] + 800389e: 429a cmp r2, r3 + 80038a0: d01f beq.n 80038e2 + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + /* Disable PLL1FRACEN */ + __HAL_RCC_PLLFRACN_DISABLE(); + 80038a2: 4b12 ldr r3, [pc, #72] ; (80038ec ) + 80038a4: 6adb ldr r3, [r3, #44] ; 0x2c + 80038a6: 4a11 ldr r2, [pc, #68] ; (80038ec ) + 80038a8: f023 0301 bic.w r3, r3, #1 + 80038ac: 62d3 str r3, [r2, #44] ; 0x2c + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80038ae: f7fd fbad bl 800100c + 80038b2: 6278 str r0, [r7, #36] ; 0x24 + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) + 80038b4: bf00 nop + 80038b6: f7fd fba9 bl 800100c + 80038ba: 4602 mov r2, r0 + 80038bc: 6a7b ldr r3, [r7, #36] ; 0x24 + 80038be: 4293 cmp r3, r2 + 80038c0: d0f9 beq.n 80038b6 + { + } + /* Configure PLL1 PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + 80038c2: 4b0a ldr r3, [pc, #40] ; (80038ec ) + 80038c4: 6b5a ldr r2, [r3, #52] ; 0x34 + 80038c6: 4b0a ldr r3, [pc, #40] ; (80038f0 ) + 80038c8: 4013 ands r3, r2 + 80038ca: 687a ldr r2, [r7, #4] + 80038cc: 6c92 ldr r2, [r2, #72] ; 0x48 + 80038ce: 00d2 lsls r2, r2, #3 + 80038d0: 4906 ldr r1, [pc, #24] ; (80038ec ) + 80038d2: 4313 orrs r3, r2 + 80038d4: 634b str r3, [r1, #52] ; 0x34 + /* Enable PLL1FRACEN to latch new value. */ + __HAL_RCC_PLLFRACN_ENABLE(); + 80038d6: 4b05 ldr r3, [pc, #20] ; (80038ec ) + 80038d8: 6adb ldr r3, [r3, #44] ; 0x2c + 80038da: 4a04 ldr r2, [pc, #16] ; (80038ec ) + 80038dc: f043 0301 orr.w r3, r3, #1 + 80038e0: 62d3 str r3, [r2, #44] ; 0x2c + } + } + } + } + return HAL_OK; + 80038e2: 2300 movs r3, #0 +} + 80038e4: 4618 mov r0, r3 + 80038e6: 3730 adds r7, #48 ; 0x30 + 80038e8: 46bd mov sp, r7 + 80038ea: bd80 pop {r7, pc} + 80038ec: 58024400 .word 0x58024400 + 80038f0: ffff0007 .word 0xffff0007 + +080038f4 : + * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 80038f4: b580 push {r7, lr} + 80038f6: b086 sub sp, #24 + 80038f8: af00 add r7, sp, #0 + 80038fa: 6078 str r0, [r7, #4] + 80038fc: 6039 str r1, [r7, #0] + HAL_StatusTypeDef halstatus; + uint32_t tickstart; + uint32_t common_system_clock; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 80038fe: 687b ldr r3, [r7, #4] + 8003900: 2b00 cmp r3, #0 + 8003902: d101 bne.n 8003908 + { + return HAL_ERROR; + 8003904: 2301 movs r3, #1 + 8003906: e19c b.n 8003c42 + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8003908: 4b8a ldr r3, [pc, #552] ; (8003b34 ) + 800390a: 681b ldr r3, [r3, #0] + 800390c: f003 030f and.w r3, r3, #15 + 8003910: 683a ldr r2, [r7, #0] + 8003912: 429a cmp r2, r3 + 8003914: d910 bls.n 8003938 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8003916: 4b87 ldr r3, [pc, #540] ; (8003b34 ) + 8003918: 681b ldr r3, [r3, #0] + 800391a: f023 020f bic.w r2, r3, #15 + 800391e: 4985 ldr r1, [pc, #532] ; (8003b34 ) + 8003920: 683b ldr r3, [r7, #0] + 8003922: 4313 orrs r3, r2 + 8003924: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003926: 4b83 ldr r3, [pc, #524] ; (8003b34 ) + 8003928: 681b ldr r3, [r3, #0] + 800392a: f003 030f and.w r3, r3, #15 + 800392e: 683a ldr r2, [r7, #0] + 8003930: 429a cmp r2, r3 + 8003932: d001 beq.n 8003938 + { + return HAL_ERROR; + 8003934: 2301 movs r3, #1 + 8003936: e184 b.n 8003c42 + + } + + /* Increasing the BUS frequency divider */ + /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + 8003938: 687b ldr r3, [r7, #4] + 800393a: 681b ldr r3, [r3, #0] + 800393c: f003 0304 and.w r3, r3, #4 + 8003940: 2b00 cmp r3, #0 + 8003942: d010 beq.n 8003966 + { +#if defined (RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + 8003944: 687b ldr r3, [r7, #4] + 8003946: 691a ldr r2, [r3, #16] + 8003948: 4b7b ldr r3, [pc, #492] ; (8003b38 ) + 800394a: 699b ldr r3, [r3, #24] + 800394c: f003 0370 and.w r3, r3, #112 ; 0x70 + 8003950: 429a cmp r2, r3 + 8003952: d908 bls.n 8003966 + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + 8003954: 4b78 ldr r3, [pc, #480] ; (8003b38 ) + 8003956: 699b ldr r3, [r3, #24] + 8003958: f023 0270 bic.w r2, r3, #112 ; 0x70 + 800395c: 687b ldr r3, [r7, #4] + 800395e: 691b ldr r3, [r3, #16] + 8003960: 4975 ldr r1, [pc, #468] ; (8003b38 ) + 8003962: 4313 orrs r3, r2 + 8003964: 618b str r3, [r1, #24] + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8003966: 687b ldr r3, [r7, #4] + 8003968: 681b ldr r3, [r3, #0] + 800396a: f003 0308 and.w r3, r3, #8 + 800396e: 2b00 cmp r3, #0 + 8003970: d010 beq.n 8003994 + { +#if defined (RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + 8003972: 687b ldr r3, [r7, #4] + 8003974: 695a ldr r2, [r3, #20] + 8003976: 4b70 ldr r3, [pc, #448] ; (8003b38 ) + 8003978: 69db ldr r3, [r3, #28] + 800397a: f003 0370 and.w r3, r3, #112 ; 0x70 + 800397e: 429a cmp r2, r3 + 8003980: d908 bls.n 8003994 + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + 8003982: 4b6d ldr r3, [pc, #436] ; (8003b38 ) + 8003984: 69db ldr r3, [r3, #28] + 8003986: f023 0270 bic.w r2, r3, #112 ; 0x70 + 800398a: 687b ldr r3, [r7, #4] + 800398c: 695b ldr r3, [r3, #20] + 800398e: 496a ldr r1, [pc, #424] ; (8003b38 ) + 8003990: 4313 orrs r3, r2 + 8003992: 61cb str r3, [r1, #28] + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8003994: 687b ldr r3, [r7, #4] + 8003996: 681b ldr r3, [r3, #0] + 8003998: f003 0310 and.w r3, r3, #16 + 800399c: 2b00 cmp r3, #0 + 800399e: d010 beq.n 80039c2 + { +#if defined(RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + 80039a0: 687b ldr r3, [r7, #4] + 80039a2: 699a ldr r2, [r3, #24] + 80039a4: 4b64 ldr r3, [pc, #400] ; (8003b38 ) + 80039a6: 69db ldr r3, [r3, #28] + 80039a8: f403 63e0 and.w r3, r3, #1792 ; 0x700 + 80039ac: 429a cmp r2, r3 + 80039ae: d908 bls.n 80039c2 + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + 80039b0: 4b61 ldr r3, [pc, #388] ; (8003b38 ) + 80039b2: 69db ldr r3, [r3, #28] + 80039b4: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 80039b8: 687b ldr r3, [r7, #4] + 80039ba: 699b ldr r3, [r3, #24] + 80039bc: 495e ldr r1, [pc, #376] ; (8003b38 ) + 80039be: 4313 orrs r3, r2 + 80039c0: 61cb str r3, [r1, #28] + } +#endif + } + + /*-------------------------- D3PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + 80039c2: 687b ldr r3, [r7, #4] + 80039c4: 681b ldr r3, [r3, #0] + 80039c6: f003 0320 and.w r3, r3, #32 + 80039ca: 2b00 cmp r3, #0 + 80039cc: d010 beq.n 80039f0 + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + 80039ce: 687b ldr r3, [r7, #4] + 80039d0: 69da ldr r2, [r3, #28] + 80039d2: 4b59 ldr r3, [pc, #356] ; (8003b38 ) + 80039d4: 6a1b ldr r3, [r3, #32] + 80039d6: f003 0370 and.w r3, r3, #112 ; 0x70 + 80039da: 429a cmp r2, r3 + 80039dc: d908 bls.n 80039f0 + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + 80039de: 4b56 ldr r3, [pc, #344] ; (8003b38 ) + 80039e0: 6a1b ldr r3, [r3, #32] + 80039e2: f023 0270 bic.w r2, r3, #112 ; 0x70 + 80039e6: 687b ldr r3, [r7, #4] + 80039e8: 69db ldr r3, [r3, #28] + 80039ea: 4953 ldr r1, [pc, #332] ; (8003b38 ) + 80039ec: 4313 orrs r3, r2 + 80039ee: 620b str r3, [r1, #32] + } +#endif + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 80039f0: 687b ldr r3, [r7, #4] + 80039f2: 681b ldr r3, [r3, #0] + 80039f4: f003 0302 and.w r3, r3, #2 + 80039f8: 2b00 cmp r3, #0 + 80039fa: d010 beq.n 8003a1e + { +#if defined (RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + 80039fc: 687b ldr r3, [r7, #4] + 80039fe: 68da ldr r2, [r3, #12] + 8003a00: 4b4d ldr r3, [pc, #308] ; (8003b38 ) + 8003a02: 699b ldr r3, [r3, #24] + 8003a04: f003 030f and.w r3, r3, #15 + 8003a08: 429a cmp r2, r3 + 8003a0a: d908 bls.n 8003a1e + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8003a0c: 4b4a ldr r3, [pc, #296] ; (8003b38 ) + 8003a0e: 699b ldr r3, [r3, #24] + 8003a10: f023 020f bic.w r2, r3, #15 + 8003a14: 687b ldr r3, [r7, #4] + 8003a16: 68db ldr r3, [r3, #12] + 8003a18: 4947 ldr r1, [pc, #284] ; (8003b38 ) + 8003a1a: 4313 orrs r3, r2 + 8003a1c: 618b str r3, [r1, #24] + } +#endif + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8003a1e: 687b ldr r3, [r7, #4] + 8003a20: 681b ldr r3, [r3, #0] + 8003a22: f003 0301 and.w r3, r3, #1 + 8003a26: 2b00 cmp r3, #0 + 8003a28: d055 beq.n 8003ad6 + { + assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); +#if defined(RCC_D1CFGR_D1CPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); + 8003a2a: 4b43 ldr r3, [pc, #268] ; (8003b38 ) + 8003a2c: 699b ldr r3, [r3, #24] + 8003a2e: f423 6270 bic.w r2, r3, #3840 ; 0xf00 + 8003a32: 687b ldr r3, [r7, #4] + 8003a34: 689b ldr r3, [r3, #8] + 8003a36: 4940 ldr r1, [pc, #256] ; (8003b38 ) + 8003a38: 4313 orrs r3, r2 + 8003a3a: 618b str r3, [r1, #24] +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); +#endif + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8003a3c: 687b ldr r3, [r7, #4] + 8003a3e: 685b ldr r3, [r3, #4] + 8003a40: 2b02 cmp r3, #2 + 8003a42: d107 bne.n 8003a54 + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8003a44: 4b3c ldr r3, [pc, #240] ; (8003b38 ) + 8003a46: 681b ldr r3, [r3, #0] + 8003a48: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8003a4c: 2b00 cmp r3, #0 + 8003a4e: d121 bne.n 8003a94 + { + return HAL_ERROR; + 8003a50: 2301 movs r3, #1 + 8003a52: e0f6 b.n 8003c42 + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8003a54: 687b ldr r3, [r7, #4] + 8003a56: 685b ldr r3, [r3, #4] + 8003a58: 2b03 cmp r3, #3 + 8003a5a: d107 bne.n 8003a6c + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8003a5c: 4b36 ldr r3, [pc, #216] ; (8003b38 ) + 8003a5e: 681b ldr r3, [r3, #0] + 8003a60: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8003a64: 2b00 cmp r3, #0 + 8003a66: d115 bne.n 8003a94 + { + return HAL_ERROR; + 8003a68: 2301 movs r3, #1 + 8003a6a: e0ea b.n 8003c42 + } + } + /* CSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + 8003a6c: 687b ldr r3, [r7, #4] + 8003a6e: 685b ldr r3, [r3, #4] + 8003a70: 2b01 cmp r3, #1 + 8003a72: d107 bne.n 8003a84 + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + 8003a74: 4b30 ldr r3, [pc, #192] ; (8003b38 ) + 8003a76: 681b ldr r3, [r3, #0] + 8003a78: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003a7c: 2b00 cmp r3, #0 + 8003a7e: d109 bne.n 8003a94 + { + return HAL_ERROR; + 8003a80: 2301 movs r3, #1 + 8003a82: e0de b.n 8003c42 + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8003a84: 4b2c ldr r3, [pc, #176] ; (8003b38 ) + 8003a86: 681b ldr r3, [r3, #0] + 8003a88: f003 0304 and.w r3, r3, #4 + 8003a8c: 2b00 cmp r3, #0 + 8003a8e: d101 bne.n 8003a94 + { + return HAL_ERROR; + 8003a90: 2301 movs r3, #1 + 8003a92: e0d6 b.n 8003c42 + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + 8003a94: 4b28 ldr r3, [pc, #160] ; (8003b38 ) + 8003a96: 691b ldr r3, [r3, #16] + 8003a98: f023 0207 bic.w r2, r3, #7 + 8003a9c: 687b ldr r3, [r7, #4] + 8003a9e: 685b ldr r3, [r3, #4] + 8003aa0: 4925 ldr r1, [pc, #148] ; (8003b38 ) + 8003aa2: 4313 orrs r3, r2 + 8003aa4: 610b str r3, [r1, #16] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003aa6: f7fd fab1 bl 800100c + 8003aaa: 6178 str r0, [r7, #20] + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8003aac: e00a b.n 8003ac4 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8003aae: f7fd faad bl 800100c + 8003ab2: 4602 mov r2, r0 + 8003ab4: 697b ldr r3, [r7, #20] + 8003ab6: 1ad3 subs r3, r2, r3 + 8003ab8: f241 3288 movw r2, #5000 ; 0x1388 + 8003abc: 4293 cmp r3, r2 + 8003abe: d901 bls.n 8003ac4 + { + return HAL_TIMEOUT; + 8003ac0: 2303 movs r3, #3 + 8003ac2: e0be b.n 8003c42 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8003ac4: 4b1c ldr r3, [pc, #112] ; (8003b38 ) + 8003ac6: 691b ldr r3, [r3, #16] + 8003ac8: f003 0238 and.w r2, r3, #56 ; 0x38 + 8003acc: 687b ldr r3, [r7, #4] + 8003ace: 685b ldr r3, [r3, #4] + 8003ad0: 00db lsls r3, r3, #3 + 8003ad2: 429a cmp r2, r3 + 8003ad4: d1eb bne.n 8003aae + + } + + /* Decreasing the BUS frequency divider */ + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8003ad6: 687b ldr r3, [r7, #4] + 8003ad8: 681b ldr r3, [r3, #0] + 8003ada: f003 0302 and.w r3, r3, #2 + 8003ade: 2b00 cmp r3, #0 + 8003ae0: d010 beq.n 8003b04 + { +#if defined(RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + 8003ae2: 687b ldr r3, [r7, #4] + 8003ae4: 68da ldr r2, [r3, #12] + 8003ae6: 4b14 ldr r3, [pc, #80] ; (8003b38 ) + 8003ae8: 699b ldr r3, [r3, #24] + 8003aea: f003 030f and.w r3, r3, #15 + 8003aee: 429a cmp r2, r3 + 8003af0: d208 bcs.n 8003b04 + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8003af2: 4b11 ldr r3, [pc, #68] ; (8003b38 ) + 8003af4: 699b ldr r3, [r3, #24] + 8003af6: f023 020f bic.w r2, r3, #15 + 8003afa: 687b ldr r3, [r7, #4] + 8003afc: 68db ldr r3, [r3, #12] + 8003afe: 490e ldr r1, [pc, #56] ; (8003b38 ) + 8003b00: 4313 orrs r3, r2 + 8003b02: 618b str r3, [r1, #24] + } +#endif + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8003b04: 4b0b ldr r3, [pc, #44] ; (8003b34 ) + 8003b06: 681b ldr r3, [r3, #0] + 8003b08: f003 030f and.w r3, r3, #15 + 8003b0c: 683a ldr r2, [r7, #0] + 8003b0e: 429a cmp r2, r3 + 8003b10: d214 bcs.n 8003b3c + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8003b12: 4b08 ldr r3, [pc, #32] ; (8003b34 ) + 8003b14: 681b ldr r3, [r3, #0] + 8003b16: f023 020f bic.w r2, r3, #15 + 8003b1a: 4906 ldr r1, [pc, #24] ; (8003b34 ) + 8003b1c: 683b ldr r3, [r7, #0] + 8003b1e: 4313 orrs r3, r2 + 8003b20: 600b str r3, [r1, #0] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003b22: 4b04 ldr r3, [pc, #16] ; (8003b34 ) + 8003b24: 681b ldr r3, [r3, #0] + 8003b26: f003 030f and.w r3, r3, #15 + 8003b2a: 683a ldr r2, [r7, #0] + 8003b2c: 429a cmp r2, r3 + 8003b2e: d005 beq.n 8003b3c + { + return HAL_ERROR; + 8003b30: 2301 movs r3, #1 + 8003b32: e086 b.n 8003c42 + 8003b34: 52002000 .word 0x52002000 + 8003b38: 58024400 .word 0x58024400 + } + } + + /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + 8003b3c: 687b ldr r3, [r7, #4] + 8003b3e: 681b ldr r3, [r3, #0] + 8003b40: f003 0304 and.w r3, r3, #4 + 8003b44: 2b00 cmp r3, #0 + 8003b46: d010 beq.n 8003b6a + { +#if defined(RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + 8003b48: 687b ldr r3, [r7, #4] + 8003b4a: 691a ldr r2, [r3, #16] + 8003b4c: 4b3f ldr r3, [pc, #252] ; (8003c4c ) + 8003b4e: 699b ldr r3, [r3, #24] + 8003b50: f003 0370 and.w r3, r3, #112 ; 0x70 + 8003b54: 429a cmp r2, r3 + 8003b56: d208 bcs.n 8003b6a + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + 8003b58: 4b3c ldr r3, [pc, #240] ; (8003c4c ) + 8003b5a: 699b ldr r3, [r3, #24] + 8003b5c: f023 0270 bic.w r2, r3, #112 ; 0x70 + 8003b60: 687b ldr r3, [r7, #4] + 8003b62: 691b ldr r3, [r3, #16] + 8003b64: 4939 ldr r1, [pc, #228] ; (8003c4c ) + 8003b66: 4313 orrs r3, r2 + 8003b68: 618b str r3, [r1, #24] + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8003b6a: 687b ldr r3, [r7, #4] + 8003b6c: 681b ldr r3, [r3, #0] + 8003b6e: f003 0308 and.w r3, r3, #8 + 8003b72: 2b00 cmp r3, #0 + 8003b74: d010 beq.n 8003b98 + { +#if defined(RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + 8003b76: 687b ldr r3, [r7, #4] + 8003b78: 695a ldr r2, [r3, #20] + 8003b7a: 4b34 ldr r3, [pc, #208] ; (8003c4c ) + 8003b7c: 69db ldr r3, [r3, #28] + 8003b7e: f003 0370 and.w r3, r3, #112 ; 0x70 + 8003b82: 429a cmp r2, r3 + 8003b84: d208 bcs.n 8003b98 + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + 8003b86: 4b31 ldr r3, [pc, #196] ; (8003c4c ) + 8003b88: 69db ldr r3, [r3, #28] + 8003b8a: f023 0270 bic.w r2, r3, #112 ; 0x70 + 8003b8e: 687b ldr r3, [r7, #4] + 8003b90: 695b ldr r3, [r3, #20] + 8003b92: 492e ldr r1, [pc, #184] ; (8003c4c ) + 8003b94: 4313 orrs r3, r2 + 8003b96: 61cb str r3, [r1, #28] + } +#endif + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8003b98: 687b ldr r3, [r7, #4] + 8003b9a: 681b ldr r3, [r3, #0] + 8003b9c: f003 0310 and.w r3, r3, #16 + 8003ba0: 2b00 cmp r3, #0 + 8003ba2: d010 beq.n 8003bc6 + { +#if defined (RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + 8003ba4: 687b ldr r3, [r7, #4] + 8003ba6: 699a ldr r2, [r3, #24] + 8003ba8: 4b28 ldr r3, [pc, #160] ; (8003c4c ) + 8003baa: 69db ldr r3, [r3, #28] + 8003bac: f403 63e0 and.w r3, r3, #1792 ; 0x700 + 8003bb0: 429a cmp r2, r3 + 8003bb2: d208 bcs.n 8003bc6 + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + 8003bb4: 4b25 ldr r3, [pc, #148] ; (8003c4c ) + 8003bb6: 69db ldr r3, [r3, #28] + 8003bb8: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 8003bbc: 687b ldr r3, [r7, #4] + 8003bbe: 699b ldr r3, [r3, #24] + 8003bc0: 4922 ldr r1, [pc, #136] ; (8003c4c ) + 8003bc2: 4313 orrs r3, r2 + 8003bc4: 61cb str r3, [r1, #28] + } +#endif + } + + /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + 8003bc6: 687b ldr r3, [r7, #4] + 8003bc8: 681b ldr r3, [r3, #0] + 8003bca: f003 0320 and.w r3, r3, #32 + 8003bce: 2b00 cmp r3, #0 + 8003bd0: d010 beq.n 8003bf4 + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + 8003bd2: 687b ldr r3, [r7, #4] + 8003bd4: 69da ldr r2, [r3, #28] + 8003bd6: 4b1d ldr r3, [pc, #116] ; (8003c4c ) + 8003bd8: 6a1b ldr r3, [r3, #32] + 8003bda: f003 0370 and.w r3, r3, #112 ; 0x70 + 8003bde: 429a cmp r2, r3 + 8003be0: d208 bcs.n 8003bf4 + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + 8003be2: 4b1a ldr r3, [pc, #104] ; (8003c4c ) + 8003be4: 6a1b ldr r3, [r3, #32] + 8003be6: f023 0270 bic.w r2, r3, #112 ; 0x70 + 8003bea: 687b ldr r3, [r7, #4] + 8003bec: 69db ldr r3, [r3, #28] + 8003bee: 4917 ldr r1, [pc, #92] ; (8003c4c ) + 8003bf0: 4313 orrs r3, r2 + 8003bf2: 620b str r3, [r1, #32] +#endif + } + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); + 8003bf4: f000 f834 bl 8003c60 + 8003bf8: 4602 mov r2, r0 + 8003bfa: 4b14 ldr r3, [pc, #80] ; (8003c4c ) + 8003bfc: 699b ldr r3, [r3, #24] + 8003bfe: 0a1b lsrs r3, r3, #8 + 8003c00: f003 030f and.w r3, r3, #15 + 8003c04: 4912 ldr r1, [pc, #72] ; (8003c50 ) + 8003c06: 5ccb ldrb r3, [r1, r3] + 8003c08: f003 031f and.w r3, r3, #31 + 8003c0c: fa22 f303 lsr.w r3, r2, r3 + 8003c10: 613b str r3, [r7, #16] +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + 8003c12: 4b0e ldr r3, [pc, #56] ; (8003c4c ) + 8003c14: 699b ldr r3, [r3, #24] + 8003c16: f003 030f and.w r3, r3, #15 + 8003c1a: 4a0d ldr r2, [pc, #52] ; (8003c50 ) + 8003c1c: 5cd3 ldrb r3, [r2, r3] + 8003c1e: f003 031f and.w r3, r3, #31 + 8003c22: 693a ldr r2, [r7, #16] + 8003c24: fa22 f303 lsr.w r3, r2, r3 + 8003c28: 4a0a ldr r2, [pc, #40] ; (8003c54 ) + 8003c2a: 6013 str r3, [r2, #0] +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; + 8003c2c: 4a0a ldr r2, [pc, #40] ; (8003c58 ) + 8003c2e: 693b ldr r3, [r7, #16] + 8003c30: 6013 str r3, [r2, #0] +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Configure the source of time base considering new system clocks settings*/ + halstatus = HAL_InitTick(uwTickPrio); + 8003c32: 4b0a ldr r3, [pc, #40] ; (8003c5c ) + 8003c34: 681b ldr r3, [r3, #0] + 8003c36: 4618 mov r0, r3 + 8003c38: f7fd f99e bl 8000f78 + 8003c3c: 4603 mov r3, r0 + 8003c3e: 73fb strb r3, [r7, #15] + + return halstatus; + 8003c40: 7bfb ldrb r3, [r7, #15] +} + 8003c42: 4618 mov r0, r3 + 8003c44: 3718 adds r7, #24 + 8003c46: 46bd mov sp, r7 + 8003c48: bd80 pop {r7, pc} + 8003c4a: bf00 nop + 8003c4c: 58024400 .word 0x58024400 + 8003c50: 08014c80 .word 0x08014c80 + 8003c54: 24000004 .word 0x24000004 + 8003c58: 24000000 .word 0x24000000 + 8003c5c: 24000008 .word 0x24000008 + +08003c60 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 8003c60: b480 push {r7} + 8003c62: b089 sub sp, #36 ; 0x24 + 8003c64: af00 add r7, sp, #0 + float_t fracn1, pllvco; + uint32_t sysclockfreq; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + 8003c66: 4bb3 ldr r3, [pc, #716] ; (8003f34 ) + 8003c68: 691b ldr r3, [r3, #16] + 8003c6a: f003 0338 and.w r3, r3, #56 ; 0x38 + 8003c6e: 2b18 cmp r3, #24 + 8003c70: f200 8155 bhi.w 8003f1e + 8003c74: a201 add r2, pc, #4 ; (adr r2, 8003c7c ) + 8003c76: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003c7a: bf00 nop + 8003c7c: 08003ce1 .word 0x08003ce1 + 8003c80: 08003f1f .word 0x08003f1f + 8003c84: 08003f1f .word 0x08003f1f + 8003c88: 08003f1f .word 0x08003f1f + 8003c8c: 08003f1f .word 0x08003f1f + 8003c90: 08003f1f .word 0x08003f1f + 8003c94: 08003f1f .word 0x08003f1f + 8003c98: 08003f1f .word 0x08003f1f + 8003c9c: 08003d07 .word 0x08003d07 + 8003ca0: 08003f1f .word 0x08003f1f + 8003ca4: 08003f1f .word 0x08003f1f + 8003ca8: 08003f1f .word 0x08003f1f + 8003cac: 08003f1f .word 0x08003f1f + 8003cb0: 08003f1f .word 0x08003f1f + 8003cb4: 08003f1f .word 0x08003f1f + 8003cb8: 08003f1f .word 0x08003f1f + 8003cbc: 08003d0d .word 0x08003d0d + 8003cc0: 08003f1f .word 0x08003f1f + 8003cc4: 08003f1f .word 0x08003f1f + 8003cc8: 08003f1f .word 0x08003f1f + 8003ccc: 08003f1f .word 0x08003f1f + 8003cd0: 08003f1f .word 0x08003f1f + 8003cd4: 08003f1f .word 0x08003f1f + 8003cd8: 08003f1f .word 0x08003f1f + 8003cdc: 08003d13 .word 0x08003d13 + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + 8003ce0: 4b94 ldr r3, [pc, #592] ; (8003f34 ) + 8003ce2: 681b ldr r3, [r3, #0] + 8003ce4: f003 0320 and.w r3, r3, #32 + 8003ce8: 2b00 cmp r3, #0 + 8003cea: d009 beq.n 8003d00 + { + sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + 8003cec: 4b91 ldr r3, [pc, #580] ; (8003f34 ) + 8003cee: 681b ldr r3, [r3, #0] + 8003cf0: 08db lsrs r3, r3, #3 + 8003cf2: f003 0303 and.w r3, r3, #3 + 8003cf6: 4a90 ldr r2, [pc, #576] ; (8003f38 ) + 8003cf8: fa22 f303 lsr.w r3, r2, r3 + 8003cfc: 61bb str r3, [r7, #24] + else + { + sysclockfreq = (uint32_t) HSI_VALUE; + } + + break; + 8003cfe: e111 b.n 8003f24 + sysclockfreq = (uint32_t) HSI_VALUE; + 8003d00: 4b8d ldr r3, [pc, #564] ; (8003f38 ) + 8003d02: 61bb str r3, [r7, #24] + break; + 8003d04: e10e b.n 8003f24 + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + 8003d06: 4b8d ldr r3, [pc, #564] ; (8003f3c ) + 8003d08: 61bb str r3, [r7, #24] + break; + 8003d0a: e10b b.n 8003f24 + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + 8003d0c: 4b8c ldr r3, [pc, #560] ; (8003f40 ) + 8003d0e: 61bb str r3, [r7, #24] + break; + 8003d10: e108 b.n 8003f24 + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + 8003d12: 4b88 ldr r3, [pc, #544] ; (8003f34 ) + 8003d14: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003d16: f003 0303 and.w r3, r3, #3 + 8003d1a: 617b str r3, [r7, #20] + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; + 8003d1c: 4b85 ldr r3, [pc, #532] ; (8003f34 ) + 8003d1e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003d20: 091b lsrs r3, r3, #4 + 8003d22: f003 033f and.w r3, r3, #63 ; 0x3f + 8003d26: 613b str r3, [r7, #16] + pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + 8003d28: 4b82 ldr r3, [pc, #520] ; (8003f34 ) + 8003d2a: 6adb ldr r3, [r3, #44] ; 0x2c + 8003d2c: f003 0301 and.w r3, r3, #1 + 8003d30: 60fb str r3, [r7, #12] + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + 8003d32: 4b80 ldr r3, [pc, #512] ; (8003f34 ) + 8003d34: 6b5b ldr r3, [r3, #52] ; 0x34 + 8003d36: 08db lsrs r3, r3, #3 + 8003d38: f3c3 030c ubfx r3, r3, #0, #13 + 8003d3c: 68fa ldr r2, [r7, #12] + 8003d3e: fb02 f303 mul.w r3, r2, r3 + 8003d42: ee07 3a90 vmov s15, r3 + 8003d46: eef8 7a67 vcvt.f32.u32 s15, s15 + 8003d4a: edc7 7a02 vstr s15, [r7, #8] + + if (pllm != 0U) + 8003d4e: 693b ldr r3, [r7, #16] + 8003d50: 2b00 cmp r3, #0 + 8003d52: f000 80e1 beq.w 8003f18 + 8003d56: 697b ldr r3, [r7, #20] + 8003d58: 2b02 cmp r3, #2 + 8003d5a: f000 8083 beq.w 8003e64 + 8003d5e: 697b ldr r3, [r7, #20] + 8003d60: 2b02 cmp r3, #2 + 8003d62: f200 80a1 bhi.w 8003ea8 + 8003d66: 697b ldr r3, [r7, #20] + 8003d68: 2b00 cmp r3, #0 + 8003d6a: d003 beq.n 8003d74 + 8003d6c: 697b ldr r3, [r7, #20] + 8003d6e: 2b01 cmp r3, #1 + 8003d70: d056 beq.n 8003e20 + 8003d72: e099 b.n 8003ea8 + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + 8003d74: 4b6f ldr r3, [pc, #444] ; (8003f34 ) + 8003d76: 681b ldr r3, [r3, #0] + 8003d78: f003 0320 and.w r3, r3, #32 + 8003d7c: 2b00 cmp r3, #0 + 8003d7e: d02d beq.n 8003ddc + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + 8003d80: 4b6c ldr r3, [pc, #432] ; (8003f34 ) + 8003d82: 681b ldr r3, [r3, #0] + 8003d84: 08db lsrs r3, r3, #3 + 8003d86: f003 0303 and.w r3, r3, #3 + 8003d8a: 4a6b ldr r2, [pc, #428] ; (8003f38 ) + 8003d8c: fa22 f303 lsr.w r3, r2, r3 + 8003d90: 607b str r3, [r7, #4] + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + 8003d92: 687b ldr r3, [r7, #4] + 8003d94: ee07 3a90 vmov s15, r3 + 8003d98: eef8 6a67 vcvt.f32.u32 s13, s15 + 8003d9c: 693b ldr r3, [r7, #16] + 8003d9e: ee07 3a90 vmov s15, r3 + 8003da2: eef8 7a67 vcvt.f32.u32 s15, s15 + 8003da6: ee86 7aa7 vdiv.f32 s14, s13, s15 + 8003daa: 4b62 ldr r3, [pc, #392] ; (8003f34 ) + 8003dac: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003dae: f3c3 0308 ubfx r3, r3, #0, #9 + 8003db2: ee07 3a90 vmov s15, r3 + 8003db6: eef8 6a67 vcvt.f32.u32 s13, s15 + 8003dba: ed97 6a02 vldr s12, [r7, #8] + 8003dbe: eddf 5a61 vldr s11, [pc, #388] ; 8003f44 + 8003dc2: eec6 7a25 vdiv.f32 s15, s12, s11 + 8003dc6: ee76 7aa7 vadd.f32 s15, s13, s15 + 8003dca: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 + 8003dce: ee77 7aa6 vadd.f32 s15, s15, s13 + 8003dd2: ee67 7a27 vmul.f32 s15, s14, s15 + 8003dd6: edc7 7a07 vstr s15, [r7, #28] + } + else + { + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + 8003dda: e087 b.n 8003eec + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + 8003ddc: 693b ldr r3, [r7, #16] + 8003dde: ee07 3a90 vmov s15, r3 + 8003de2: eef8 7a67 vcvt.f32.u32 s15, s15 + 8003de6: eddf 6a58 vldr s13, [pc, #352] ; 8003f48 + 8003dea: ee86 7aa7 vdiv.f32 s14, s13, s15 + 8003dee: 4b51 ldr r3, [pc, #324] ; (8003f34 ) + 8003df0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003df2: f3c3 0308 ubfx r3, r3, #0, #9 + 8003df6: ee07 3a90 vmov s15, r3 + 8003dfa: eef8 6a67 vcvt.f32.u32 s13, s15 + 8003dfe: ed97 6a02 vldr s12, [r7, #8] + 8003e02: eddf 5a50 vldr s11, [pc, #320] ; 8003f44 + 8003e06: eec6 7a25 vdiv.f32 s15, s12, s11 + 8003e0a: ee76 7aa7 vadd.f32 s15, s13, s15 + 8003e0e: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 + 8003e12: ee77 7aa6 vadd.f32 s15, s15, s13 + 8003e16: ee67 7a27 vmul.f32 s15, s14, s15 + 8003e1a: edc7 7a07 vstr s15, [r7, #28] + break; + 8003e1e: e065 b.n 8003eec + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + 8003e20: 693b ldr r3, [r7, #16] + 8003e22: ee07 3a90 vmov s15, r3 + 8003e26: eef8 7a67 vcvt.f32.u32 s15, s15 + 8003e2a: eddf 6a48 vldr s13, [pc, #288] ; 8003f4c + 8003e2e: ee86 7aa7 vdiv.f32 s14, s13, s15 + 8003e32: 4b40 ldr r3, [pc, #256] ; (8003f34 ) + 8003e34: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003e36: f3c3 0308 ubfx r3, r3, #0, #9 + 8003e3a: ee07 3a90 vmov s15, r3 + 8003e3e: eef8 6a67 vcvt.f32.u32 s13, s15 + 8003e42: ed97 6a02 vldr s12, [r7, #8] + 8003e46: eddf 5a3f vldr s11, [pc, #252] ; 8003f44 + 8003e4a: eec6 7a25 vdiv.f32 s15, s12, s11 + 8003e4e: ee76 7aa7 vadd.f32 s15, s13, s15 + 8003e52: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 + 8003e56: ee77 7aa6 vadd.f32 s15, s15, s13 + 8003e5a: ee67 7a27 vmul.f32 s15, s14, s15 + 8003e5e: edc7 7a07 vstr s15, [r7, #28] + break; + 8003e62: e043 b.n 8003eec + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + 8003e64: 693b ldr r3, [r7, #16] + 8003e66: ee07 3a90 vmov s15, r3 + 8003e6a: eef8 7a67 vcvt.f32.u32 s15, s15 + 8003e6e: eddf 6a38 vldr s13, [pc, #224] ; 8003f50 + 8003e72: ee86 7aa7 vdiv.f32 s14, s13, s15 + 8003e76: 4b2f ldr r3, [pc, #188] ; (8003f34 ) + 8003e78: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003e7a: f3c3 0308 ubfx r3, r3, #0, #9 + 8003e7e: ee07 3a90 vmov s15, r3 + 8003e82: eef8 6a67 vcvt.f32.u32 s13, s15 + 8003e86: ed97 6a02 vldr s12, [r7, #8] + 8003e8a: eddf 5a2e vldr s11, [pc, #184] ; 8003f44 + 8003e8e: eec6 7a25 vdiv.f32 s15, s12, s11 + 8003e92: ee76 7aa7 vadd.f32 s15, s13, s15 + 8003e96: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 + 8003e9a: ee77 7aa6 vadd.f32 s15, s15, s13 + 8003e9e: ee67 7a27 vmul.f32 s15, s14, s15 + 8003ea2: edc7 7a07 vstr s15, [r7, #28] + break; + 8003ea6: e021 b.n 8003eec + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + 8003ea8: 693b ldr r3, [r7, #16] + 8003eaa: ee07 3a90 vmov s15, r3 + 8003eae: eef8 7a67 vcvt.f32.u32 s15, s15 + 8003eb2: eddf 6a26 vldr s13, [pc, #152] ; 8003f4c + 8003eb6: ee86 7aa7 vdiv.f32 s14, s13, s15 + 8003eba: 4b1e ldr r3, [pc, #120] ; (8003f34 ) + 8003ebc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003ebe: f3c3 0308 ubfx r3, r3, #0, #9 + 8003ec2: ee07 3a90 vmov s15, r3 + 8003ec6: eef8 6a67 vcvt.f32.u32 s13, s15 + 8003eca: ed97 6a02 vldr s12, [r7, #8] + 8003ece: eddf 5a1d vldr s11, [pc, #116] ; 8003f44 + 8003ed2: eec6 7a25 vdiv.f32 s15, s12, s11 + 8003ed6: ee76 7aa7 vadd.f32 s15, s13, s15 + 8003eda: eef7 6a00 vmov.f32 s13, #112 ; 0x3f800000 1.0 + 8003ede: ee77 7aa6 vadd.f32 s15, s15, s13 + 8003ee2: ee67 7a27 vmul.f32 s15, s14, s15 + 8003ee6: edc7 7a07 vstr s15, [r7, #28] + break; + 8003eea: bf00 nop + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; + 8003eec: 4b11 ldr r3, [pc, #68] ; (8003f34 ) + 8003eee: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003ef0: 0a5b lsrs r3, r3, #9 + 8003ef2: f003 037f and.w r3, r3, #127 ; 0x7f + 8003ef6: 3301 adds r3, #1 + 8003ef8: 603b str r3, [r7, #0] + sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); + 8003efa: 683b ldr r3, [r7, #0] + 8003efc: ee07 3a90 vmov s15, r3 + 8003f00: eeb8 7a67 vcvt.f32.u32 s14, s15 + 8003f04: edd7 6a07 vldr s13, [r7, #28] + 8003f08: eec6 7a87 vdiv.f32 s15, s13, s14 + 8003f0c: eefc 7ae7 vcvt.u32.f32 s15, s15 + 8003f10: ee17 3a90 vmov r3, s15 + 8003f14: 61bb str r3, [r7, #24] + } + else + { + sysclockfreq = 0U; + } + break; + 8003f16: e005 b.n 8003f24 + sysclockfreq = 0U; + 8003f18: 2300 movs r3, #0 + 8003f1a: 61bb str r3, [r7, #24] + break; + 8003f1c: e002 b.n 8003f24 + + default: + sysclockfreq = CSI_VALUE; + 8003f1e: 4b07 ldr r3, [pc, #28] ; (8003f3c ) + 8003f20: 61bb str r3, [r7, #24] + break; + 8003f22: bf00 nop + } + + return sysclockfreq; + 8003f24: 69bb ldr r3, [r7, #24] +} + 8003f26: 4618 mov r0, r3 + 8003f28: 3724 adds r7, #36 ; 0x24 + 8003f2a: 46bd mov sp, r7 + 8003f2c: f85d 7b04 ldr.w r7, [sp], #4 + 8003f30: 4770 bx lr + 8003f32: bf00 nop + 8003f34: 58024400 .word 0x58024400 + 8003f38: 03d09000 .word 0x03d09000 + 8003f3c: 003d0900 .word 0x003d0900 + 8003f40: 017d7840 .word 0x017d7840 + 8003f44: 46000000 .word 0x46000000 + 8003f48: 4c742400 .word 0x4c742400 + 8003f4c: 4a742400 .word 0x4a742400 + 8003f50: 4bbebc20 .word 0x4bbebc20 + +08003f54 : + * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8003f54: b580 push {r7, lr} + 8003f56: b082 sub sp, #8 + 8003f58: af00 add r7, sp, #0 + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); + 8003f5a: f7ff fe81 bl 8003c60 + 8003f5e: 4602 mov r2, r0 + 8003f60: 4b10 ldr r3, [pc, #64] ; (8003fa4 ) + 8003f62: 699b ldr r3, [r3, #24] + 8003f64: 0a1b lsrs r3, r3, #8 + 8003f66: f003 030f and.w r3, r3, #15 + 8003f6a: 490f ldr r1, [pc, #60] ; (8003fa8 ) + 8003f6c: 5ccb ldrb r3, [r1, r3] + 8003f6e: f003 031f and.w r3, r3, #31 + 8003f72: fa22 f303 lsr.w r3, r2, r3 + 8003f76: 607b str r3, [r7, #4] +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + 8003f78: 4b0a ldr r3, [pc, #40] ; (8003fa4 ) + 8003f7a: 699b ldr r3, [r3, #24] + 8003f7c: f003 030f and.w r3, r3, #15 + 8003f80: 4a09 ldr r2, [pc, #36] ; (8003fa8 ) + 8003f82: 5cd3 ldrb r3, [r2, r3] + 8003f84: f003 031f and.w r3, r3, #31 + 8003f88: 687a ldr r2, [r7, #4] + 8003f8a: fa22 f303 lsr.w r3, r2, r3 + 8003f8e: 4a07 ldr r2, [pc, #28] ; (8003fac ) + 8003f90: 6013 str r3, [r2, #0] +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; + 8003f92: 4a07 ldr r2, [pc, #28] ; (8003fb0 ) + 8003f94: 687b ldr r3, [r7, #4] + 8003f96: 6013 str r3, [r2, #0] +#endif /* DUAL_CORE && CORE_CM4 */ + + return SystemD2Clock; + 8003f98: 4b04 ldr r3, [pc, #16] ; (8003fac ) + 8003f9a: 681b ldr r3, [r3, #0] +} + 8003f9c: 4618 mov r0, r3 + 8003f9e: 3708 adds r7, #8 + 8003fa0: 46bd mov sp, r7 + 8003fa2: bd80 pop {r7, pc} + 8003fa4: 58024400 .word 0x58024400 + 8003fa8: 08014c80 .word 0x08014c80 + 8003fac: 24000004 .word 0x24000004 + 8003fb0: 24000000 .word 0x24000000 + +08003fb4 : + struct pbuf *p); + +/** Close control or data pcb + * @param pointer to lwftp session data + */ +static err_t lwftp_pcb_close(struct tcp_pcb *tpcb) { + 8003fb4: b580 push {r7, lr} + 8003fb6: b084 sub sp, #16 + 8003fb8: af00 add r7, sp, #0 + 8003fba: 6078 str r0, [r7, #4] + err_t error; + + tcp_err(tpcb, NULL); + 8003fbc: 2100 movs r1, #0 + 8003fbe: 6878 ldr r0, [r7, #4] + 8003fc0: f004 fe24 bl 8008c0c + tcp_recv(tpcb, NULL); + 8003fc4: 2100 movs r1, #0 + 8003fc6: 6878 ldr r0, [r7, #4] + 8003fc8: f004 fddc bl 8008b84 + tcp_sent(tpcb, NULL); + 8003fcc: 2100 movs r1, #0 + 8003fce: 6878 ldr r0, [r7, #4] + 8003fd0: f004 fdfa bl 8008bc8 + error = tcp_close(tpcb); + 8003fd4: 6878 ldr r0, [r7, #4] + 8003fd6: f003 fc9b bl 8007910 + 8003fda: 4603 mov r3, r0 + 8003fdc: 73fb strb r3, [r7, #15] + if (error != ERR_OK) { + 8003fde: f997 300f ldrsb.w r3, [r7, #15] + 8003fe2: 2b00 cmp r3, #0 + 8003fe4: d002 beq.n 8003fec + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:pcb close failure, not implemented\n")); + 8003fe6: 4804 ldr r0, [pc, #16] ; (8003ff8 ) + 8003fe8: f00c fe5c bl 8010ca4 + } + return ERR_OK; + 8003fec: 2300 movs r3, #0 +} + 8003fee: 4618 mov r0, r3 + 8003ff0: 3710 adds r7, #16 + 8003ff2: 46bd mov sp, r7 + 8003ff4: bd80 pop {r7, pc} + 8003ff6: bf00 nop + 8003ff8: 0801167c .word 0x0801167c + +08003ffc : +/** Send data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_send_next_data(lwftp_session_t *s) { + 8003ffc: b580 push {r7, lr} + 8003ffe: b086 sub sp, #24 + 8004000: af00 add r7, sp, #0 + 8004002: 6078 str r0, [r7, #4] + const char *data; + int len = 0; + 8004004: 2300 movs r3, #0 + 8004006: 617b str r3, [r7, #20] + err_t error = ERR_OK; + 8004008: 2300 movs r3, #0 + 800400a: 74fb strb r3, [r7, #19] + + if (s->data_source) { + 800400c: 687b ldr r3, [r7, #4] + 800400e: 699b ldr r3, [r3, #24] + 8004010: 2b00 cmp r3, #0 + 8004012: d026 beq.n 8004062 + len = s->data_source(s->handle, &data, s->data_pcb->mss); + 8004014: 687b ldr r3, [r7, #4] + 8004016: 699b ldr r3, [r3, #24] + 8004018: 687a ldr r2, [r7, #4] + 800401a: 6950 ldr r0, [r2, #20] + 800401c: 687a ldr r2, [r7, #4] + 800401e: 6b12 ldr r2, [r2, #48] ; 0x30 + 8004020: 8e52 ldrh r2, [r2, #50] ; 0x32 + 8004022: f107 010c add.w r1, r7, #12 + 8004026: 4798 blx r3 + 8004028: 4603 mov r3, r0 + 800402a: 617b str r3, [r7, #20] + if (len) { + 800402c: 697b ldr r3, [r7, #20] + 800402e: 2b00 cmp r3, #0 + 8004030: d017 beq.n 8004062 + error = tcp_write(s->data_pcb, data, len, 0); + 8004032: 687b ldr r3, [r7, #4] + 8004034: 6b18 ldr r0, [r3, #48] ; 0x30 + 8004036: 68f9 ldr r1, [r7, #12] + 8004038: 697b ldr r3, [r7, #20] + 800403a: b29a uxth r2, r3 + 800403c: 2300 movs r3, #0 + 800403e: f007 fc91 bl 800b964 + 8004042: 4603 mov r3, r0 + 8004044: 74fb strb r3, [r7, #19] + if (error != ERR_OK) { + 8004046: f997 3013 ldrsb.w r3, [r7, #19] + 800404a: 2b00 cmp r3, #0 + 800404c: d009 beq.n 8004062 + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:write failure (%s), not implemented\n",lwip_strerr(error))); + 800404e: f997 3013 ldrsb.w r3, [r7, #19] + 8004052: 4618 mov r0, r3 + 8004054: f001 fa5a bl 800550c + 8004058: 4603 mov r3, r0 + 800405a: 4619 mov r1, r3 + 800405c: 480a ldr r0, [pc, #40] ; (8004088 ) + 800405e: f00c fdb3 bl 8010bc8 + } + } + } + if (!len) { + 8004062: 697b ldr r3, [r7, #20] + 8004064: 2b00 cmp r3, #0 + 8004066: d10a bne.n 800407e + LWIP_DEBUGF(LWFTP_STATE, ("lwftp:end of file\n")); + 8004068: 4808 ldr r0, [pc, #32] ; (800408c ) + 800406a: f00c fe1b bl 8010ca4 + lwftp_pcb_close(s->data_pcb); + 800406e: 687b ldr r3, [r7, #4] + 8004070: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004072: 4618 mov r0, r3 + 8004074: f7ff ff9e bl 8003fb4 + s->data_pcb = NULL; + 8004078: 687b ldr r3, [r7, #4] + 800407a: 2200 movs r2, #0 + 800407c: 631a str r2, [r3, #48] ; 0x30 + } + return ERR_OK; + 800407e: 2300 movs r3, #0 +} + 8004080: 4618 mov r0, r3 + 8004082: 3718 adds r7, #24 + 8004084: 46bd mov sp, r7 + 8004086: bd80 pop {r7, pc} + 8004088: 080116a8 .word 0x080116a8 + 800408c: 080116d4 .word 0x080116d4 + +08004090 : + * @param pointer to PCB + * @param pointer to incoming pbuf + * @param state of incoming process + */ +static err_t lwftp_data_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, + err_t err) { + 8004090: b580 push {r7, lr} + 8004092: b086 sub sp, #24 + 8004094: af00 add r7, sp, #0 + 8004096: 60f8 str r0, [r7, #12] + 8004098: 60b9 str r1, [r7, #8] + 800409a: 607a str r2, [r7, #4] + 800409c: 70fb strb r3, [r7, #3] + lwftp_session_t *s = (lwftp_session_t*) arg; + 800409e: 68fb ldr r3, [r7, #12] + 80040a0: 613b str r3, [r7, #16] + if (p) { + 80040a2: 687b ldr r3, [r7, #4] + 80040a4: 2b00 cmp r3, #0 + 80040a6: d026 beq.n 80040f6 + if (s->data_sink) { + 80040a8: 693b ldr r3, [r7, #16] + 80040aa: 69db ldr r3, [r3, #28] + 80040ac: 2b00 cmp r3, #0 + 80040ae: d012 beq.n 80040d6 + struct pbuf *q; + for (q = p; q; q = q->next) { + 80040b0: 687b ldr r3, [r7, #4] + 80040b2: 617b str r3, [r7, #20] + 80040b4: e00b b.n 80040ce + s->data_sink(s->handle, q->payload, q->len); + 80040b6: 693b ldr r3, [r7, #16] + 80040b8: 69db ldr r3, [r3, #28] + 80040ba: 693a ldr r2, [r7, #16] + 80040bc: 6950 ldr r0, [r2, #20] + 80040be: 697a ldr r2, [r7, #20] + 80040c0: 6851 ldr r1, [r2, #4] + 80040c2: 697a ldr r2, [r7, #20] + 80040c4: 8952 ldrh r2, [r2, #10] + 80040c6: 4798 blx r3 + for (q = p; q; q = q->next) { + 80040c8: 697b ldr r3, [r7, #20] + 80040ca: 681b ldr r3, [r3, #0] + 80040cc: 617b str r3, [r7, #20] + 80040ce: 697b ldr r3, [r7, #20] + 80040d0: 2b00 cmp r3, #0 + 80040d2: d1f0 bne.n 80040b6 + 80040d4: e005 b.n 80040e2 + } + } else { + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp: sinking %d bytes\n",p->tot_len)); + 80040d6: 687b ldr r3, [r7, #4] + 80040d8: 891b ldrh r3, [r3, #8] + 80040da: 4619 mov r1, r3 + 80040dc: 480e ldr r0, [pc, #56] ; (8004118 ) + 80040de: f00c fd73 bl 8010bc8 + } + tcp_recved(tpcb, p->tot_len); + 80040e2: 687b ldr r3, [r7, #4] + 80040e4: 891b ldrh r3, [r3, #8] + 80040e6: 4619 mov r1, r3 + 80040e8: 68b8 ldr r0, [r7, #8] + 80040ea: f003 fd61 bl 8007bb0 + pbuf_free(p); + 80040ee: 6878 ldr r0, [r7, #4] + 80040f0: f002 ff70 bl 8006fd4 + 80040f4: e00a b.n 800410c + } else { + // NULL pbuf shall lead to close the pcb. Close is postponed after + // the session state machine updates. No need to close right here. + // Instead we kindly tell data sink we are done + if (s->data_sink) { + 80040f6: 693b ldr r3, [r7, #16] + 80040f8: 69db ldr r3, [r3, #28] + 80040fa: 2b00 cmp r3, #0 + 80040fc: d006 beq.n 800410c + s->data_sink(s->handle, NULL, 0); + 80040fe: 693b ldr r3, [r7, #16] + 8004100: 69db ldr r3, [r3, #28] + 8004102: 693a ldr r2, [r7, #16] + 8004104: 6950 ldr r0, [r2, #20] + 8004106: 2200 movs r2, #0 + 8004108: 2100 movs r1, #0 + 800410a: 4798 blx r3 + } + } + return ERR_OK; + 800410c: 2300 movs r3, #0 +} + 800410e: 4618 mov r0, r3 + 8004110: 3718 adds r7, #24 + 8004112: 46bd mov sp, r7 + 8004114: bd80 pop {r7, pc} + 8004116: bf00 nop + 8004118: 080116e8 .word 0x080116e8 + +0800411c : +/** Handle data connection acknowledge of sent data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_data_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) { + 800411c: b580 push {r7, lr} + 800411e: b086 sub sp, #24 + 8004120: af00 add r7, sp, #0 + 8004122: 60f8 str r0, [r7, #12] + 8004124: 60b9 str r1, [r7, #8] + 8004126: 4613 mov r3, r2 + 8004128: 80fb strh r3, [r7, #6] + lwftp_session_t *s = (lwftp_session_t*) arg; + 800412a: 68fb ldr r3, [r7, #12] + 800412c: 617b str r3, [r7, #20] + + if (s->data_source) { + 800412e: 697b ldr r3, [r7, #20] + 8004130: 699b ldr r3, [r3, #24] + 8004132: 2b00 cmp r3, #0 + 8004134: d006 beq.n 8004144 + s->data_source(s->handle, NULL, len); + 8004136: 697b ldr r3, [r7, #20] + 8004138: 699b ldr r3, [r3, #24] + 800413a: 697a ldr r2, [r7, #20] + 800413c: 6950 ldr r0, [r2, #20] + 800413e: 88fa ldrh r2, [r7, #6] + 8004140: 2100 movs r1, #0 + 8004142: 4798 blx r3 + } + return lwftp_send_next_data(s); + 8004144: 6978 ldr r0, [r7, #20] + 8004146: f7ff ff59 bl 8003ffc + 800414a: 4603 mov r3, r0 +} + 800414c: 4618 mov r0, r3 + 800414e: 3718 adds r7, #24 + 8004150: 46bd mov sp, r7 + 8004152: bd80 pop {r7, pc} + +08004154 : + +/** Handle data connection error + * @param pointer to lwftp session data + * @param state of connection + */ +static void lwftp_data_err(void *arg, err_t err) { + 8004154: b580 push {r7, lr} + 8004156: b084 sub sp, #16 + 8004158: af00 add r7, sp, #0 + 800415a: 6078 str r0, [r7, #4] + 800415c: 460b mov r3, r1 + 800415e: 70fb strb r3, [r7, #3] + LWIP_UNUSED_ARG(err); + if (arg != NULL) { + 8004160: 687b ldr r3, [r7, #4] + 8004162: 2b00 cmp r3, #0 + 8004164: d01c beq.n 80041a0 + lwftp_session_t *s = (lwftp_session_t*) arg; + 8004166: 687b ldr r3, [r7, #4] + 8004168: 60fb str r3, [r7, #12] + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed/error connecting for data to server (%s)\n",lwip_strerr(err))); + 800416a: f997 3003 ldrsb.w r3, [r7, #3] + 800416e: 4618 mov r0, r3 + 8004170: f001 f9cc bl 800550c + 8004174: 4603 mov r3, r0 + 8004176: 4619 mov r1, r3 + 8004178: 480b ldr r0, [pc, #44] ; (80041a8 ) + 800417a: f00c fd25 bl 8010bc8 + s->data_pcb = NULL; // No need to de-allocate PCB + 800417e: 68fb ldr r3, [r7, #12] + 8004180: 2200 movs r2, #0 + 8004182: 631a str r2, [r3, #48] ; 0x30 + if (s->control_state == LWFTP_XFERING) { // gracefully move control session ahead + 8004184: 68fb ldr r3, [r7, #12] + 8004186: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 800418a: 2b09 cmp r3, #9 + 800418c: d108 bne.n 80041a0 + s->control_state = LWFTP_DATAEND; + 800418e: 68fb ldr r3, [r7, #12] + 8004190: 220a movs r2, #10 + 8004192: f883 2028 strb.w r2, [r3, #40] ; 0x28 + lwftp_control_process(s, NULL, NULL); + 8004196: 2200 movs r2, #0 + 8004198: 2100 movs r1, #0 + 800419a: 68f8 ldr r0, [r7, #12] + 800419c: f000 f97c bl 8004498 + } + } +} + 80041a0: bf00 nop + 80041a2: 3710 adds r7, #16 + 80041a4: 46bd mov sp, r7 + 80041a6: bd80 pop {r7, pc} + 80041a8: 08011704 .word 0x08011704 + +080041ac : +/** Process newly connected PCB + * @param pointer to lwftp session data + * @param pointer to PCB + * @param state of connection + */ +static err_t lwftp_data_connected(void *arg, struct tcp_pcb *tpcb, err_t err) { + 80041ac: b580 push {r7, lr} + 80041ae: b086 sub sp, #24 + 80041b0: af00 add r7, sp, #0 + 80041b2: 60f8 str r0, [r7, #12] + 80041b4: 60b9 str r1, [r7, #8] + 80041b6: 4613 mov r3, r2 + 80041b8: 71fb strb r3, [r7, #7] + lwftp_session_t *s = (lwftp_session_t*) arg; + 80041ba: 68fb ldr r3, [r7, #12] + 80041bc: 617b str r3, [r7, #20] + + if (err == ERR_OK) { + 80041be: f997 3007 ldrsb.w r3, [r7, #7] + 80041c2: 2b00 cmp r3, #0 + 80041c4: d107 bne.n 80041d6 + LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected for data to server\n")); + 80041c6: 480c ldr r0, [pc, #48] ; (80041f8 ) + 80041c8: f00c fd6c bl 8010ca4 + s->data_state = LWFTP_CONNECTED; + 80041cc: 697b ldr r3, [r7, #20] + 80041ce: 2201 movs r2, #1 + 80041d0: f883 202a strb.w r2, [r3, #42] ; 0x2a + 80041d4: e009 b.n 80041ea + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in data_connected (%s)\n",lwip_strerr(err))); + 80041d6: f997 3007 ldrsb.w r3, [r7, #7] + 80041da: 4618 mov r0, r3 + 80041dc: f001 f996 bl 800550c + 80041e0: 4603 mov r3, r0 + 80041e2: 4619 mov r1, r3 + 80041e4: 4805 ldr r0, [pc, #20] ; (80041fc ) + 80041e6: f00c fcef bl 8010bc8 + } + return err; + 80041ea: f997 3007 ldrsb.w r3, [r7, #7] +} + 80041ee: 4618 mov r0, r3 + 80041f0: 3718 adds r7, #24 + 80041f2: 46bd mov sp, r7 + 80041f4: bd80 pop {r7, pc} + 80041f6: bf00 nop + 80041f8: 0801173c .word 0x0801173c + 80041fc: 08011760 .word 0x08011760 + +08004200 : + +/** Open data connection for passive transfer + * @param pointer to lwftp session data + * @param pointer to incoming PASV response + */ +static err_t lwftp_data_open(lwftp_session_t *s, struct pbuf *p) { + 8004200: b580 push {r7, lr} + 8004202: b08a sub sp, #40 ; 0x28 + 8004204: af00 add r7, sp, #0 + 8004206: 6078 str r0, [r7, #4] + 8004208: 6039 str r1, [r7, #0] + char *ptr; + ip_addr_t data_server; + u16_t data_port; + + // Find server connection parameter + ptr = strchr(p->payload, '('); + 800420a: 683b ldr r3, [r7, #0] + 800420c: 685b ldr r3, [r3, #4] + 800420e: 2128 movs r1, #40 ; 0x28 + 8004210: 4618 mov r0, r3 + 8004212: f00c fe3f bl 8010e94 + 8004216: 4603 mov r3, r0 + 8004218: 613b str r3, [r7, #16] + if (!ptr) + 800421a: 693b ldr r3, [r7, #16] + 800421c: 2b00 cmp r3, #0 + 800421e: d102 bne.n 8004226 + return ERR_BUF; + 8004220: f06f 0301 mvn.w r3, #1 + 8004224: e0ac b.n 8004380 + do { + unsigned int a = strtoul(ptr + 1, &ptr, 10); + 8004226: 693b ldr r3, [r7, #16] + 8004228: 3301 adds r3, #1 + 800422a: f107 0110 add.w r1, r7, #16 + 800422e: 220a movs r2, #10 + 8004230: 4618 mov r0, r3 + 8004232: f00c f8c5 bl 80103c0 + 8004236: 6278 str r0, [r7, #36] ; 0x24 + unsigned int b = strtoul(ptr + 1, &ptr, 10); + 8004238: 693b ldr r3, [r7, #16] + 800423a: 3301 adds r3, #1 + 800423c: f107 0110 add.w r1, r7, #16 + 8004240: 220a movs r2, #10 + 8004242: 4618 mov r0, r3 + 8004244: f00c f8bc bl 80103c0 + 8004248: 6238 str r0, [r7, #32] + unsigned int c = strtoul(ptr + 1, &ptr, 10); + 800424a: 693b ldr r3, [r7, #16] + 800424c: 3301 adds r3, #1 + 800424e: f107 0110 add.w r1, r7, #16 + 8004252: 220a movs r2, #10 + 8004254: 4618 mov r0, r3 + 8004256: f00c f8b3 bl 80103c0 + 800425a: 61f8 str r0, [r7, #28] + unsigned int d = strtoul(ptr + 1, &ptr, 10); + 800425c: 693b ldr r3, [r7, #16] + 800425e: 3301 adds r3, #1 + 8004260: f107 0110 add.w r1, r7, #16 + 8004264: 220a movs r2, #10 + 8004266: 4618 mov r0, r3 + 8004268: f00c f8aa bl 80103c0 + 800426c: 61b8 str r0, [r7, #24] + IP4_ADDR(&data_server, a, b, c, d); + 800426e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004270: 061a lsls r2, r3, #24 + 8004272: 6a3b ldr r3, [r7, #32] + 8004274: 041b lsls r3, r3, #16 + 8004276: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 800427a: 431a orrs r2, r3 + 800427c: 69fb ldr r3, [r7, #28] + 800427e: 021b lsls r3, r3, #8 + 8004280: b29b uxth r3, r3 + 8004282: 431a orrs r2, r3 + 8004284: 69bb ldr r3, [r7, #24] + 8004286: b2db uxtb r3, r3 + 8004288: 4313 orrs r3, r2 + 800428a: 061a lsls r2, r3, #24 + 800428c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800428e: 0619 lsls r1, r3, #24 + 8004290: 6a3b ldr r3, [r7, #32] + 8004292: 041b lsls r3, r3, #16 + 8004294: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8004298: 4319 orrs r1, r3 + 800429a: 69fb ldr r3, [r7, #28] + 800429c: 021b lsls r3, r3, #8 + 800429e: b29b uxth r3, r3 + 80042a0: 4319 orrs r1, r3 + 80042a2: 69bb ldr r3, [r7, #24] + 80042a4: b2db uxtb r3, r3 + 80042a6: 430b orrs r3, r1 + 80042a8: 021b lsls r3, r3, #8 + 80042aa: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 80042ae: 431a orrs r2, r3 + 80042b0: 6a7b ldr r3, [r7, #36] ; 0x24 + 80042b2: 0619 lsls r1, r3, #24 + 80042b4: 6a3b ldr r3, [r7, #32] + 80042b6: 041b lsls r3, r3, #16 + 80042b8: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 80042bc: 4319 orrs r1, r3 + 80042be: 69fb ldr r3, [r7, #28] + 80042c0: 021b lsls r3, r3, #8 + 80042c2: b29b uxth r3, r3 + 80042c4: 4319 orrs r1, r3 + 80042c6: 69bb ldr r3, [r7, #24] + 80042c8: b2db uxtb r3, r3 + 80042ca: 430b orrs r3, r1 + 80042cc: 0a1b lsrs r3, r3, #8 + 80042ce: f403 437f and.w r3, r3, #65280 ; 0xff00 + 80042d2: 431a orrs r2, r3 + 80042d4: 6a7b ldr r3, [r7, #36] ; 0x24 + 80042d6: 0619 lsls r1, r3, #24 + 80042d8: 6a3b ldr r3, [r7, #32] + 80042da: 041b lsls r3, r3, #16 + 80042dc: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 80042e0: 4319 orrs r1, r3 + 80042e2: 69fb ldr r3, [r7, #28] + 80042e4: 021b lsls r3, r3, #8 + 80042e6: b29b uxth r3, r3 + 80042e8: 4319 orrs r1, r3 + 80042ea: 69bb ldr r3, [r7, #24] + 80042ec: b2db uxtb r3, r3 + 80042ee: 430b orrs r3, r1 + 80042f0: 0e1b lsrs r3, r3, #24 + 80042f2: 4313 orrs r3, r2 + 80042f4: 60fb str r3, [r7, #12] + } while (0); + data_port = strtoul(ptr + 1, &ptr, 10) << 8; + 80042f6: 693b ldr r3, [r7, #16] + 80042f8: 3301 adds r3, #1 + 80042fa: f107 0110 add.w r1, r7, #16 + 80042fe: 220a movs r2, #10 + 8004300: 4618 mov r0, r3 + 8004302: f00c f85d bl 80103c0 + 8004306: 4603 mov r3, r0 + 8004308: b29b uxth r3, r3 + 800430a: 021b lsls r3, r3, #8 + 800430c: 82fb strh r3, [r7, #22] + data_port |= strtoul(ptr + 1, &ptr, 10) & 255; + 800430e: 693b ldr r3, [r7, #16] + 8004310: 3301 adds r3, #1 + 8004312: f107 0110 add.w r1, r7, #16 + 8004316: 220a movs r2, #10 + 8004318: 4618 mov r0, r3 + 800431a: f00c f851 bl 80103c0 + 800431e: 4603 mov r3, r0 + 8004320: b2db uxtb r3, r3 + 8004322: b29a uxth r2, r3 + 8004324: 8afb ldrh r3, [r7, #22] + 8004326: 4313 orrs r3, r2 + 8004328: 82fb strh r3, [r7, #22] + if (*ptr != ')') + 800432a: 693b ldr r3, [r7, #16] + 800432c: 781b ldrb r3, [r3, #0] + 800432e: 2b29 cmp r3, #41 ; 0x29 + 8004330: d002 beq.n 8004338 + return ERR_BUF; + 8004332: f06f 0301 mvn.w r3, #1 + 8004336: e023 b.n 8004380 + + // Open data session + tcp_arg(s->data_pcb, s); + 8004338: 687b ldr r3, [r7, #4] + 800433a: 6b1b ldr r3, [r3, #48] ; 0x30 + 800433c: 6879 ldr r1, [r7, #4] + 800433e: 4618 mov r0, r3 + 8004340: f004 fc0e bl 8008b60 + tcp_err(s->data_pcb, lwftp_data_err); + 8004344: 687b ldr r3, [r7, #4] + 8004346: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004348: 490f ldr r1, [pc, #60] ; (8004388 ) + 800434a: 4618 mov r0, r3 + 800434c: f004 fc5e bl 8008c0c + tcp_recv(s->data_pcb, lwftp_data_recv); + 8004350: 687b ldr r3, [r7, #4] + 8004352: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004354: 490d ldr r1, [pc, #52] ; (800438c ) + 8004356: 4618 mov r0, r3 + 8004358: f004 fc14 bl 8008b84 + tcp_sent(s->data_pcb, lwftp_data_sent); + 800435c: 687b ldr r3, [r7, #4] + 800435e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004360: 490b ldr r1, [pc, #44] ; (8004390 ) + 8004362: 4618 mov r0, r3 + 8004364: f004 fc30 bl 8008bc8 + error = tcp_connect(s->data_pcb, &data_server, data_port, + 8004368: 687b ldr r3, [r7, #4] + 800436a: 6b18 ldr r0, [r3, #48] ; 0x30 + 800436c: 8afa ldrh r2, [r7, #22] + 800436e: f107 010c add.w r1, r7, #12 + 8004372: 4b08 ldr r3, [pc, #32] ; (8004394 ) + 8004374: f003 fcb2 bl 8007cdc + 8004378: 4603 mov r3, r0 + 800437a: 757b strb r3, [r7, #21] + lwftp_data_connected); + return error; + 800437c: f997 3015 ldrsb.w r3, [r7, #21] +} + 8004380: 4618 mov r0, r3 + 8004382: 3728 adds r7, #40 ; 0x28 + 8004384: 46bd mov sp, r7 + 8004386: bd80 pop {r7, pc} + 8004388: 08004155 .word 0x08004155 + 800438c: 08004091 .word 0x08004091 + 8004390: 0800411d .word 0x0800411d + 8004394: 080041ad .word 0x080041ad + +08004398 : + +/** Send a message to control connection + * @param pointer to lwftp session data + * @param pointer to message string + */ +static err_t lwftp_send_msg(lwftp_session_t *s, const char *msg, size_t len) { + 8004398: b580 push {r7, lr} + 800439a: b086 sub sp, #24 + 800439c: af00 add r7, sp, #0 + 800439e: 60f8 str r0, [r7, #12] + 80043a0: 60b9 str r1, [r7, #8] + 80043a2: 607a str r2, [r7, #4] + err_t error; + + LWIP_DEBUGF(LWFTP_TRACE,("lwftp:sending %s",msg)); + 80043a4: 68b9 ldr r1, [r7, #8] + 80043a6: 4810 ldr r0, [pc, #64] ; (80043e8 ) + 80043a8: f00c fc0e bl 8010bc8 + error = tcp_write(s->control_pcb, msg, len, 0); + 80043ac: 68fb ldr r3, [r7, #12] + 80043ae: 6ad8 ldr r0, [r3, #44] ; 0x2c + 80043b0: 687b ldr r3, [r7, #4] + 80043b2: b29a uxth r2, r3 + 80043b4: 2300 movs r3, #0 + 80043b6: 68b9 ldr r1, [r7, #8] + 80043b8: f007 fad4 bl 800b964 + 80043bc: 4603 mov r3, r0 + 80043be: 75fb strb r3, [r7, #23] + if (error != ERR_OK) { + 80043c0: f997 3017 ldrsb.w r3, [r7, #23] + 80043c4: 2b00 cmp r3, #0 + 80043c6: d009 beq.n 80043dc + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:cannot write (%s)\n",lwip_strerr(error))); + 80043c8: f997 3017 ldrsb.w r3, [r7, #23] + 80043cc: 4618 mov r0, r3 + 80043ce: f001 f89d bl 800550c + 80043d2: 4603 mov r3, r0 + 80043d4: 4619 mov r1, r3 + 80043d6: 4805 ldr r0, [pc, #20] ; (80043ec ) + 80043d8: f00c fbf6 bl 8010bc8 + } + return error; + 80043dc: f997 3017 ldrsb.w r3, [r7, #23] +} + 80043e0: 4618 mov r0, r3 + 80043e2: 3718 adds r7, #24 + 80043e4: 46bd mov sp, r7 + 80043e6: bd80 pop {r7, pc} + 80043e8: 08011784 .word 0x08011784 + 80043ec: 08011798 .word 0x08011798 + +080043f0 : + +/** Close data connection + * @param pointer to lwftp session data + * @param result to pass to callback fn (if called) + */ +static void lwftp_data_close(lwftp_session_t *s, int result) { + 80043f0: b580 push {r7, lr} + 80043f2: b082 sub sp, #8 + 80043f4: af00 add r7, sp, #0 + 80043f6: 6078 str r0, [r7, #4] + 80043f8: 6039 str r1, [r7, #0] + if (s->data_pcb) { + 80043fa: 687b ldr r3, [r7, #4] + 80043fc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80043fe: 2b00 cmp r3, #0 + 8004400: d007 beq.n 8004412 + lwftp_pcb_close(s->data_pcb); + 8004402: 687b ldr r3, [r7, #4] + 8004404: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004406: 4618 mov r0, r3 + 8004408: f7ff fdd4 bl 8003fb4 + s->data_pcb = NULL; + 800440c: 687b ldr r3, [r7, #4] + 800440e: 2200 movs r2, #0 + 8004410: 631a str r2, [r3, #48] ; 0x30 + } + if (s->done_fn) { + 8004412: 687b ldr r3, [r7, #4] + 8004414: 6a1b ldr r3, [r3, #32] + 8004416: 2b00 cmp r3, #0 + 8004418: d006 beq.n 8004428 + s->done_fn(s->handle, result); + 800441a: 687b ldr r3, [r7, #4] + 800441c: 6a1b ldr r3, [r3, #32] + 800441e: 687a ldr r2, [r7, #4] + 8004420: 6952 ldr r2, [r2, #20] + 8004422: 6839 ldr r1, [r7, #0] + 8004424: 4610 mov r0, r2 + 8004426: 4798 blx r3 + } +} + 8004428: bf00 nop + 800442a: 3708 adds r7, #8 + 800442c: 46bd mov sp, r7 + 800442e: bd80 pop {r7, pc} + +08004430 : + +/** Close control connection + * @param pointer to lwftp session data + * @param result to pass to callback fn (if called) + */ +static void lwftp_control_close(lwftp_session_t *s, int result) { + 8004430: b580 push {r7, lr} + 8004432: b082 sub sp, #8 + 8004434: af00 add r7, sp, #0 + 8004436: 6078 str r0, [r7, #4] + 8004438: 6039 str r1, [r7, #0] + if (s->data_pcb) { + 800443a: 687b ldr r3, [r7, #4] + 800443c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800443e: 2b00 cmp r3, #0 + 8004440: d007 beq.n 8004452 + lwftp_pcb_close(s->data_pcb); + 8004442: 687b ldr r3, [r7, #4] + 8004444: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004446: 4618 mov r0, r3 + 8004448: f7ff fdb4 bl 8003fb4 + s->data_pcb = NULL; + 800444c: 687b ldr r3, [r7, #4] + 800444e: 2200 movs r2, #0 + 8004450: 631a str r2, [r3, #48] ; 0x30 + } + if (s->control_pcb) { + 8004452: 687b ldr r3, [r7, #4] + 8004454: 6adb ldr r3, [r3, #44] ; 0x2c + 8004456: 2b00 cmp r3, #0 + 8004458: d007 beq.n 800446a + lwftp_pcb_close(s->control_pcb); + 800445a: 687b ldr r3, [r7, #4] + 800445c: 6adb ldr r3, [r3, #44] ; 0x2c + 800445e: 4618 mov r0, r3 + 8004460: f7ff fda8 bl 8003fb4 + s->control_pcb = NULL; + 8004464: 687b ldr r3, [r7, #4] + 8004466: 2200 movs r2, #0 + 8004468: 62da str r2, [r3, #44] ; 0x2c + } + s->control_state = LWFTP_CLOSED; + 800446a: 687b ldr r3, [r7, #4] + 800446c: 2200 movs r2, #0 + 800446e: f883 2028 strb.w r2, [r3, #40] ; 0x28 + if ((result >= 0) && s->done_fn) { + 8004472: 683b ldr r3, [r7, #0] + 8004474: 2b00 cmp r3, #0 + 8004476: db0a blt.n 800448e + 8004478: 687b ldr r3, [r7, #4] + 800447a: 6a1b ldr r3, [r3, #32] + 800447c: 2b00 cmp r3, #0 + 800447e: d006 beq.n 800448e + s->done_fn(s->handle, result); + 8004480: 687b ldr r3, [r7, #4] + 8004482: 6a1b ldr r3, [r3, #32] + 8004484: 687a ldr r2, [r7, #4] + 8004486: 6952 ldr r2, [r2, #20] + 8004488: 6839 ldr r1, [r7, #0] + 800448a: 4610 mov r0, r2 + 800448c: 4798 blx r3 + } +} + 800448e: bf00 nop + 8004490: 3708 adds r7, #8 + 8004492: 46bd mov sp, r7 + 8004494: bd80 pop {r7, pc} + ... + +08004498 : + * @param pointer to lwftp session data + * @param pointer to PCB + * @param pointer to incoming data + */ +static void lwftp_control_process(lwftp_session_t *s, struct tcp_pcb *tpcb, + struct pbuf *p) { + 8004498: b590 push {r4, r7, lr} + 800449a: b087 sub sp, #28 + 800449c: af00 add r7, sp, #0 + 800449e: 60f8 str r0, [r7, #12] + 80044a0: 60b9 str r1, [r7, #8] + 80044a2: 607a str r2, [r7, #4] + uint response = 0; + 80044a4: 2300 movs r3, #0 + 80044a6: 617b str r3, [r7, #20] + int result = LWFTP_RESULT_ERR_SRVR_RESP; + 80044a8: 230a movs r3, #10 + 80044aa: 613b str r3, [r7, #16] + + // Try to get response number + if (p) { + 80044ac: 687b ldr r3, [r7, #4] + 80044ae: 2b00 cmp r3, #0 + 80044b0: d00b beq.n 80044ca + response = strtoul(p->payload, NULL, 10); + 80044b2: 687b ldr r3, [r7, #4] + 80044b4: 685b ldr r3, [r3, #4] + 80044b6: 220a movs r2, #10 + 80044b8: 2100 movs r1, #0 + 80044ba: 4618 mov r0, r3 + 80044bc: f00b ff80 bl 80103c0 + 80044c0: 6178 str r0, [r7, #20] + LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:got response %d\n",response)); + 80044c2: 6979 ldr r1, [r7, #20] + 80044c4: 48a8 ldr r0, [pc, #672] ; (8004768 ) + 80044c6: f00c fb7f bl 8010bc8 + } + + switch (s->control_state) { + 80044ca: 68fb ldr r3, [r7, #12] + 80044cc: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80044d0: 3b01 subs r3, #1 + 80044d2: 2b0b cmp r3, #11 + 80044d4: f200 816d bhi.w 80047b2 + 80044d8: a201 add r2, pc, #4 ; (adr r2, 80044e0 ) + 80044da: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80044de: bf00 nop + 80044e0: 08004511 .word 0x08004511 + 80044e4: 08004561 .word 0x08004561 + 80044e8: 080045b5 .word 0x080045b5 + 80044ec: 080047b3 .word 0x080047b3 + 80044f0: 080045f5 .word 0x080045f5 + 80044f4: 08004621 .word 0x08004621 + 80044f8: 080046a7 .word 0x080046a7 + 80044fc: 080046f5 .word 0x080046f5 + 8004500: 08004727 .word 0x08004727 + 8004504: 0800474f .word 0x0800474f + 8004508: 080047b3 .word 0x080047b3 + 800450c: 08004757 .word 0x08004757 + case LWFTP_CONNECTED: + if (response > 0) { + 8004510: 697b ldr r3, [r7, #20] + 8004512: 2b00 cmp r3, #0 + 8004514: f000 8155 beq.w 80047c2 + if (response == 220) { + 8004518: 697b ldr r3, [r7, #20] + 800451a: 2bdc cmp r3, #220 ; 0xdc + 800451c: d11b bne.n 8004556 + lwftp_send_msg(s, PTRNLEN("USER ")); + 800451e: 2205 movs r2, #5 + 8004520: 4992 ldr r1, [pc, #584] ; (800476c ) + 8004522: 68f8 ldr r0, [r7, #12] + 8004524: f7ff ff38 bl 8004398 + lwftp_send_msg(s, s->user, strlen(s->user)); + 8004528: 68fb ldr r3, [r7, #12] + 800452a: 68dc ldr r4, [r3, #12] + 800452c: 68fb ldr r3, [r7, #12] + 800452e: 68db ldr r3, [r3, #12] + 8004530: 4618 mov r0, r3 + 8004532: f7fb ff3d bl 80003b0 + 8004536: 4603 mov r3, r0 + 8004538: 461a mov r2, r3 + 800453a: 4621 mov r1, r4 + 800453c: 68f8 ldr r0, [r7, #12] + 800453e: f7ff ff2b bl 8004398 + lwftp_send_msg(s, PTRNLEN("\r\n")); + 8004542: 2202 movs r2, #2 + 8004544: 498a ldr r1, [pc, #552] ; (8004770 ) + 8004546: 68f8 ldr r0, [r7, #12] + 8004548: f7ff ff26 bl 8004398 + s->control_state = LWFTP_USER_SENT; + 800454c: 68fb ldr r3, [r7, #12] + 800454e: 2202 movs r2, #2 + 8004550: f883 2028 strb.w r2, [r3, #40] ; 0x28 + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + 8004554: e135 b.n 80047c2 + s->control_state = LWFTP_QUIT; + 8004556: 68fb ldr r3, [r7, #12] + 8004558: 220b movs r2, #11 + 800455a: f883 2028 strb.w r2, [r3, #40] ; 0x28 + break; + 800455e: e130 b.n 80047c2 + case LWFTP_USER_SENT: + if (response > 0) { + 8004560: 697b ldr r3, [r7, #20] + 8004562: 2b00 cmp r3, #0 + 8004564: f000 812f beq.w 80047c6 + if (response == 331) { + 8004568: 697b ldr r3, [r7, #20] + 800456a: f240 124b movw r2, #331 ; 0x14b + 800456e: 4293 cmp r3, r2 + 8004570: d11b bne.n 80045aa + lwftp_send_msg(s, PTRNLEN("PASS ")); + 8004572: 2205 movs r2, #5 + 8004574: 497f ldr r1, [pc, #508] ; (8004774 ) + 8004576: 68f8 ldr r0, [r7, #12] + 8004578: f7ff ff0e bl 8004398 + lwftp_send_msg(s, s->pass, strlen(s->pass)); + 800457c: 68fb ldr r3, [r7, #12] + 800457e: 691c ldr r4, [r3, #16] + 8004580: 68fb ldr r3, [r7, #12] + 8004582: 691b ldr r3, [r3, #16] + 8004584: 4618 mov r0, r3 + 8004586: f7fb ff13 bl 80003b0 + 800458a: 4603 mov r3, r0 + 800458c: 461a mov r2, r3 + 800458e: 4621 mov r1, r4 + 8004590: 68f8 ldr r0, [r7, #12] + 8004592: f7ff ff01 bl 8004398 + lwftp_send_msg(s, PTRNLEN("\r\n")); + 8004596: 2202 movs r2, #2 + 8004598: 4975 ldr r1, [pc, #468] ; (8004770 ) + 800459a: 68f8 ldr r0, [r7, #12] + 800459c: f7ff fefc bl 8004398 + s->control_state = LWFTP_PASS_SENT; + 80045a0: 68fb ldr r3, [r7, #12] + 80045a2: 2203 movs r2, #3 + 80045a4: f883 2028 strb.w r2, [r3, #40] ; 0x28 + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + 80045a8: e10d b.n 80047c6 + s->control_state = LWFTP_QUIT; + 80045aa: 68fb ldr r3, [r7, #12] + 80045ac: 220b movs r2, #11 + 80045ae: f883 2028 strb.w r2, [r3, #40] ; 0x28 + break; + 80045b2: e108 b.n 80047c6 + case LWFTP_PASS_SENT: + if (response > 0) { + 80045b4: 697b ldr r3, [r7, #20] + 80045b6: 2b00 cmp r3, #0 + 80045b8: f000 8107 beq.w 80047ca + if (response == 230) { + 80045bc: 697b ldr r3, [r7, #20] + 80045be: 2be6 cmp r3, #230 ; 0xe6 + 80045c0: d113 bne.n 80045ea + s->control_state = LWFTP_LOGGED; + 80045c2: 68fb ldr r3, [r7, #12] + 80045c4: 2204 movs r2, #4 + 80045c6: f883 2028 strb.w r2, [r3, #40] ; 0x28 + LWIP_DEBUGF(LWFTP_STATE, ("lwftp: now logged in\n")); + 80045ca: 486b ldr r0, [pc, #428] ; (8004778 ) + 80045cc: f00c fb6a bl 8010ca4 + if (s->done_fn) { + 80045d0: 68fb ldr r3, [r7, #12] + 80045d2: 6a1b ldr r3, [r3, #32] + 80045d4: 2b00 cmp r3, #0 + 80045d6: f000 80f8 beq.w 80047ca + s->done_fn(s->handle, LWFTP_RESULT_LOGGED); + 80045da: 68fb ldr r3, [r7, #12] + 80045dc: 6a1b ldr r3, [r3, #32] + 80045de: 68fa ldr r2, [r7, #12] + 80045e0: 6952 ldr r2, [r2, #20] + 80045e2: 2102 movs r1, #2 + 80045e4: 4610 mov r0, r2 + 80045e6: 4798 blx r3 + } + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + 80045e8: e0ef b.n 80047ca + s->control_state = LWFTP_QUIT; + 80045ea: 68fb ldr r3, [r7, #12] + 80045ec: 220b movs r2, #11 + 80045ee: f883 2028 strb.w r2, [r3, #40] ; 0x28 + break; + 80045f2: e0ea b.n 80047ca + case LWFTP_TYPE_SENT: + if (response > 0) { + 80045f4: 697b ldr r3, [r7, #20] + 80045f6: 2b00 cmp r3, #0 + 80045f8: f000 80e9 beq.w 80047ce + if (response == 200) { + 80045fc: 697b ldr r3, [r7, #20] + 80045fe: 2bc8 cmp r3, #200 ; 0xc8 + 8004600: d109 bne.n 8004616 + lwftp_send_msg(s, PTRNLEN("PASV\r\n")); + 8004602: 2206 movs r2, #6 + 8004604: 495d ldr r1, [pc, #372] ; (800477c ) + 8004606: 68f8 ldr r0, [r7, #12] + 8004608: f7ff fec6 bl 8004398 + s->control_state = LWFTP_PASV_SENT; + 800460c: 68fb ldr r3, [r7, #12] + 800460e: 2206 movs r2, #6 + 8004610: f883 2028 strb.w r2, [r3, #40] ; 0x28 + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + 8004614: e0db b.n 80047ce + s->control_state = LWFTP_QUIT; + 8004616: 68fb ldr r3, [r7, #12] + 8004618: 220b movs r2, #11 + 800461a: f883 2028 strb.w r2, [r3, #40] ; 0x28 + break; + 800461e: e0d6 b.n 80047ce + case LWFTP_PASV_SENT: + if (response > 0) { + 8004620: 697b ldr r3, [r7, #20] + 8004622: 2b00 cmp r3, #0 + 8004624: f000 80d5 beq.w 80047d2 + if (response == 227) { + 8004628: 697b ldr r3, [r7, #20] + 800462a: 2be3 cmp r3, #227 ; 0xe3 + 800462c: d136 bne.n 800469c + lwftp_data_open(s, p); + 800462e: 6879 ldr r1, [r7, #4] + 8004630: 68f8 ldr r0, [r7, #12] + 8004632: f7ff fde5 bl 8004200 + switch (s->target_state) { + 8004636: 68fb ldr r3, [r7, #12] + 8004638: f893 3029 ldrb.w r3, [r3, #41] ; 0x29 + 800463c: 2b07 cmp r3, #7 + 800463e: d007 beq.n 8004650 + 8004640: 2b08 cmp r3, #8 + 8004642: d10b bne.n 800465c + case LWFTP_STOR_SENT: + lwftp_send_msg(s, PTRNLEN("STOR ")); + 8004644: 2205 movs r2, #5 + 8004646: 494e ldr r1, [pc, #312] ; (8004780 ) + 8004648: 68f8 ldr r0, [r7, #12] + 800464a: f7ff fea5 bl 8004398 + break; + 800464e: e00c b.n 800466a + case LWFTP_RETR_SENT: + lwftp_send_msg(s, PTRNLEN("RETR ")); + 8004650: 2205 movs r2, #5 + 8004652: 494c ldr r1, [pc, #304] ; (8004784 ) + 8004654: 68f8 ldr r0, [r7, #12] + 8004656: f7ff fe9f bl 8004398 + break; + 800465a: e006 b.n 800466a + default: + LOG_ERROR("Unexpected internal state"); + 800465c: 484a ldr r0, [pc, #296] ; (8004788 ) + 800465e: f7fb fef3 bl 8000448 + s->target_state = LWFTP_QUIT; + 8004662: 68fb ldr r3, [r7, #12] + 8004664: 220b movs r2, #11 + 8004666: f883 2029 strb.w r2, [r3, #41] ; 0x29 + } + lwftp_send_msg(s, s->remote_path, strlen(s->remote_path)); + 800466a: 68fb ldr r3, [r7, #12] + 800466c: 689c ldr r4, [r3, #8] + 800466e: 68fb ldr r3, [r7, #12] + 8004670: 689b ldr r3, [r3, #8] + 8004672: 4618 mov r0, r3 + 8004674: f7fb fe9c bl 80003b0 + 8004678: 4603 mov r3, r0 + 800467a: 461a mov r2, r3 + 800467c: 4621 mov r1, r4 + 800467e: 68f8 ldr r0, [r7, #12] + 8004680: f7ff fe8a bl 8004398 + lwftp_send_msg(s, PTRNLEN("\r\n")); + 8004684: 2202 movs r2, #2 + 8004686: 493a ldr r1, [pc, #232] ; (8004770 ) + 8004688: 68f8 ldr r0, [r7, #12] + 800468a: f7ff fe85 bl 8004398 + s->control_state = s->target_state; + 800468e: 68fb ldr r3, [r7, #12] + 8004690: f893 2029 ldrb.w r2, [r3, #41] ; 0x29 + 8004694: 68fb ldr r3, [r7, #12] + 8004696: f883 2028 strb.w r2, [r3, #40] ; 0x28 + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + 800469a: e09a b.n 80047d2 + s->control_state = LWFTP_QUIT; + 800469c: 68fb ldr r3, [r7, #12] + 800469e: 220b movs r2, #11 + 80046a0: f883 2028 strb.w r2, [r3, #40] ; 0x28 + break; + 80046a4: e095 b.n 80047d2 + case LWFTP_RETR_SENT: + if (response > 0) { + 80046a6: 697b ldr r3, [r7, #20] + 80046a8: 2b00 cmp r3, #0 + 80046aa: f000 8094 beq.w 80047d6 + if (response == 150) { + 80046ae: 697b ldr r3, [r7, #20] + 80046b0: 2b96 cmp r3, #150 ; 0x96 + 80046b2: d104 bne.n 80046be + s->control_state = LWFTP_XFERING; + 80046b4: 68fb ldr r3, [r7, #12] + 80046b6: 2209 movs r2, #9 + 80046b8: f883 2028 strb.w r2, [r3, #40] ; 0x28 + } else { + s->control_state = LWFTP_DATAEND; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response)); + } + } + break; + 80046bc: e08b b.n 80047d6 + } else if (response == 550) { + 80046be: 697b ldr r3, [r7, #20] + 80046c0: f240 2226 movw r2, #550 ; 0x226 + 80046c4: 4293 cmp r3, r2 + 80046c6: d10c bne.n 80046e2 + s->control_state = LWFTP_DATAEND; + 80046c8: 68fb ldr r3, [r7, #12] + 80046ca: 220a movs r2, #10 + 80046cc: f883 2028 strb.w r2, [r3, #40] ; 0x28 + result = LWFTP_RESULT_ERR_FILENAME; + 80046d0: 230d movs r3, #13 + 80046d2: 613b str r3, [r7, #16] + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: Failed to open file '%s'\n", s->remote_path)); + 80046d4: 68fb ldr r3, [r7, #12] + 80046d6: 689b ldr r3, [r3, #8] + 80046d8: 4619 mov r1, r3 + 80046da: 482c ldr r0, [pc, #176] ; (800478c ) + 80046dc: f00c fa74 bl 8010bc8 + break; + 80046e0: e079 b.n 80047d6 + s->control_state = LWFTP_DATAEND; + 80046e2: 68fb ldr r3, [r7, #12] + 80046e4: 220a movs r2, #10 + 80046e6: f883 2028 strb.w r2, [r3, #40] ; 0x28 + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response)); + 80046ea: 6979 ldr r1, [r7, #20] + 80046ec: 4828 ldr r0, [pc, #160] ; (8004790 ) + 80046ee: f00c fa6b bl 8010bc8 + break; + 80046f2: e070 b.n 80047d6 + case LWFTP_STOR_SENT: + if (response > 0) { + 80046f4: 697b ldr r3, [r7, #20] + 80046f6: 2b00 cmp r3, #0 + 80046f8: d06f beq.n 80047da + if (response == 150) { + 80046fa: 697b ldr r3, [r7, #20] + 80046fc: 2b96 cmp r3, #150 ; 0x96 + 80046fe: d109 bne.n 8004714 + s->control_state = LWFTP_XFERING; + 8004700: 68fb ldr r3, [r7, #12] + 8004702: 2209 movs r2, #9 + 8004704: f883 2028 strb.w r2, [r3, #40] ; 0x28 + lwftp_data_sent(s, NULL, 0); + 8004708: 2200 movs r2, #0 + 800470a: 2100 movs r1, #0 + 800470c: 68f8 ldr r0, [r7, #12] + 800470e: f7ff fd05 bl 800411c + } else { + s->control_state = LWFTP_DATAEND; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response)); + } + } + break; + 8004712: e062 b.n 80047da + s->control_state = LWFTP_DATAEND; + 8004714: 68fb ldr r3, [r7, #12] + 8004716: 220a movs r2, #10 + 8004718: f883 2028 strb.w r2, [r3, #40] ; 0x28 + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response)); + 800471c: 6979 ldr r1, [r7, #20] + 800471e: 481c ldr r0, [pc, #112] ; (8004790 ) + 8004720: f00c fa52 bl 8010bc8 + break; + 8004724: e059 b.n 80047da + case LWFTP_XFERING: + if (response > 0) { + 8004726: 697b ldr r3, [r7, #20] + 8004728: 2b00 cmp r3, #0 + 800472a: d058 beq.n 80047de + if (response == 226) { + 800472c: 697b ldr r3, [r7, #20] + 800472e: 2be2 cmp r3, #226 ; 0xe2 + 8004730: d102 bne.n 8004738 + result = LWFTP_RESULT_OK; + 8004732: 2300 movs r3, #0 + 8004734: 613b str r3, [r7, #16] + 8004736: e005 b.n 8004744 + } else { + result = LWFTP_RESULT_ERR_CLOSED; + 8004738: 2308 movs r3, #8 + 800473a: 613b str r3, [r7, #16] + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 226, received %d\n",response)); + 800473c: 6979 ldr r1, [r7, #20] + 800473e: 4815 ldr r0, [pc, #84] ; (8004794 ) + 8004740: f00c fa42 bl 8010bc8 + } + s->control_state = LWFTP_DATAEND; + 8004744: 68fb ldr r3, [r7, #12] + 8004746: 220a movs r2, #10 + 8004748: f883 2028 strb.w r2, [r3, #40] ; 0x28 + } + break; + 800474c: e047 b.n 80047de + case LWFTP_DATAEND: + LOG_TRACE("forced end of data session"); + 800474e: 4812 ldr r0, [pc, #72] ; (8004798 ) + 8004750: f7fb fea6 bl 80004a0 + break; + 8004754: e046 b.n 80047e4 + case LWFTP_QUIT_SENT: + if (response > 0) { + 8004756: 697b ldr r3, [r7, #20] + 8004758: 2b00 cmp r3, #0 + 800475a: d042 beq.n 80047e2 + if (response == 221) { + 800475c: 697b ldr r3, [r7, #20] + 800475e: 2bdd cmp r3, #221 ; 0xdd + 8004760: d11c bne.n 800479c + result = LWFTP_RESULT_OK; + 8004762: 2300 movs r3, #0 + 8004764: 613b str r3, [r7, #16] + 8004766: e01f b.n 80047a8 + 8004768: 080117b4 .word 0x080117b4 + 800476c: 080117cc .word 0x080117cc + 8004770: 080117d4 .word 0x080117d4 + 8004774: 080117d8 .word 0x080117d8 + 8004778: 080117e0 .word 0x080117e0 + 800477c: 080117f8 .word 0x080117f8 + 8004780: 08011800 .word 0x08011800 + 8004784: 08011808 .word 0x08011808 + 8004788: 08011810 .word 0x08011810 + 800478c: 0801182c .word 0x0801182c + 8004790: 08011850 .word 0x08011850 + 8004794: 08011874 .word 0x08011874 + 8004798: 08011898 .word 0x08011898 + } else { + result = LWFTP_RESULT_ERR_UNKNOWN; + 800479c: 2303 movs r3, #3 + 800479e: 613b str r3, [r7, #16] + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 221, received %d\n",response)); + 80047a0: 6979 ldr r1, [r7, #20] + 80047a2: 482a ldr r0, [pc, #168] ; (800484c ) + 80047a4: f00c fa10 bl 8010bc8 + } + s->control_state = LWFTP_CLOSING; + 80047a8: 68fb ldr r3, [r7, #12] + 80047aa: 220d movs r2, #13 + 80047ac: f883 2028 strb.w r2, [r3, #40] ; 0x28 + } + break; + 80047b0: e017 b.n 80047e2 + default: + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:unhandled state (%d)\n",s->control_state)); + 80047b2: 68fb ldr r3, [r7, #12] + 80047b4: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80047b8: 4619 mov r1, r3 + 80047ba: 4825 ldr r0, [pc, #148] ; (8004850 ) + 80047bc: f00c fa04 bl 8010bc8 + 80047c0: e010 b.n 80047e4 + break; + 80047c2: bf00 nop + 80047c4: e00e b.n 80047e4 + break; + 80047c6: bf00 nop + 80047c8: e00c b.n 80047e4 + break; + 80047ca: bf00 nop + 80047cc: e00a b.n 80047e4 + break; + 80047ce: bf00 nop + 80047d0: e008 b.n 80047e4 + break; + 80047d2: bf00 nop + 80047d4: e006 b.n 80047e4 + break; + 80047d6: bf00 nop + 80047d8: e004 b.n 80047e4 + break; + 80047da: bf00 nop + 80047dc: e002 b.n 80047e4 + break; + 80047de: bf00 nop + 80047e0: e000 b.n 80047e4 + break; + 80047e2: bf00 nop + } + + // Free receiving pbuf if any + if (p) { + 80047e4: 687b ldr r3, [r7, #4] + 80047e6: 2b00 cmp r3, #0 + 80047e8: d002 beq.n 80047f0 + pbuf_free(p); + 80047ea: 6878 ldr r0, [r7, #4] + 80047ec: f002 fbf2 bl 8006fd4 + } + + // Handle second step in state machine + switch (s->control_state) { + 80047f0: 68fb ldr r3, [r7, #12] + 80047f2: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80047f6: 2b0d cmp r3, #13 + 80047f8: d01e beq.n 8004838 + 80047fa: 2b0d cmp r3, #13 + 80047fc: dc21 bgt.n 8004842 + 80047fe: 2b0a cmp r3, #10 + 8004800: d002 beq.n 8004808 + 8004802: 2b0b cmp r3, #11 + 8004804: d009 beq.n 800481a + lwftp_control_close(s, result); + break; + default: + ; + } +} + 8004806: e01c b.n 8004842 + lwftp_data_close(s, result); + 8004808: 6939 ldr r1, [r7, #16] + 800480a: 68f8 ldr r0, [r7, #12] + 800480c: f7ff fdf0 bl 80043f0 + s->control_state = LWFTP_LOGGED; + 8004810: 68fb ldr r3, [r7, #12] + 8004812: 2204 movs r2, #4 + 8004814: f883 2028 strb.w r2, [r3, #40] ; 0x28 + break; + 8004818: e013 b.n 8004842 + lwftp_send_msg(s, PTRNLEN("QUIT\r\n")); + 800481a: 2206 movs r2, #6 + 800481c: 490d ldr r1, [pc, #52] ; (8004854 ) + 800481e: 68f8 ldr r0, [r7, #12] + 8004820: f7ff fdba bl 8004398 + tcp_output(s->control_pcb); + 8004824: 68fb ldr r3, [r7, #12] + 8004826: 6adb ldr r3, [r3, #44] ; 0x2c + 8004828: 4618 mov r0, r3 + 800482a: f007 fee3 bl 800c5f4 + s->control_state = LWFTP_QUIT_SENT; + 800482e: 68fb ldr r3, [r7, #12] + 8004830: 220c movs r2, #12 + 8004832: f883 2028 strb.w r2, [r3, #40] ; 0x28 + break; + 8004836: e004 b.n 8004842 + lwftp_control_close(s, result); + 8004838: 6939 ldr r1, [r7, #16] + 800483a: 68f8 ldr r0, [r7, #12] + 800483c: f7ff fdf8 bl 8004430 + break; + 8004840: bf00 nop +} + 8004842: bf00 nop + 8004844: 371c adds r7, #28 + 8004846: 46bd mov sp, r7 + 8004848: bd90 pop {r4, r7, pc} + 800484a: bf00 nop + 800484c: 080118b4 .word 0x080118b4 + 8004850: 080118d8 .word 0x080118d8 + 8004854: 080118f4 .word 0x080118f4 + +08004858 : + * @param pointer to PCB + * @param pointer to incoming pbuf + * @param state of incoming process + */ +static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, + err_t err) { + 8004858: b580 push {r7, lr} + 800485a: b086 sub sp, #24 + 800485c: af00 add r7, sp, #0 + 800485e: 60f8 str r0, [r7, #12] + 8004860: 60b9 str r1, [r7, #8] + 8004862: 607a str r2, [r7, #4] + 8004864: 70fb strb r3, [r7, #3] + lwftp_session_t *s = (lwftp_session_t*) arg; + 8004866: 68fb ldr r3, [r7, #12] + 8004868: 617b str r3, [r7, #20] + + if (err == ERR_OK) { + 800486a: f997 3003 ldrsb.w r3, [r7, #3] + 800486e: 2b00 cmp r3, #0 + 8004870: d116 bne.n 80048a0 + if (p) { + 8004872: 687b ldr r3, [r7, #4] + 8004874: 2b00 cmp r3, #0 + 8004876: d00b beq.n 8004890 + tcp_recved(tpcb, p->tot_len); + 8004878: 687b ldr r3, [r7, #4] + 800487a: 891b ldrh r3, [r3, #8] + 800487c: 4619 mov r1, r3 + 800487e: 68b8 ldr r0, [r7, #8] + 8004880: f003 f996 bl 8007bb0 + lwftp_control_process(s, tpcb, p); + 8004884: 687a ldr r2, [r7, #4] + 8004886: 68b9 ldr r1, [r7, #8] + 8004888: 6978 ldr r0, [r7, #20] + 800488a: f7ff fe05 bl 8004498 + 800488e: e015 b.n 80048bc + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n")); + 8004890: 480d ldr r0, [pc, #52] ; (80048c8 ) + 8004892: f00c fa07 bl 8010ca4 + lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED); + 8004896: 2108 movs r1, #8 + 8004898: 6978 ldr r0, [r7, #20] + 800489a: f7ff fdc9 bl 8004430 + 800489e: e00d b.n 80048bc + } + } else { + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:failed to receive (%s)\n",lwip_strerr(err))); + 80048a0: f997 3003 ldrsb.w r3, [r7, #3] + 80048a4: 4618 mov r0, r3 + 80048a6: f000 fe31 bl 800550c + 80048aa: 4603 mov r3, r0 + 80048ac: 4619 mov r1, r3 + 80048ae: 4807 ldr r0, [pc, #28] ; (80048cc ) + 80048b0: f00c f98a bl 8010bc8 + lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN); + 80048b4: 2103 movs r1, #3 + 80048b6: 6978 ldr r0, [r7, #20] + 80048b8: f7ff fdba bl 8004430 + } + return err; + 80048bc: f997 3003 ldrsb.w r3, [r7, #3] +} + 80048c0: 4618 mov r0, r3 + 80048c2: 3718 adds r7, #24 + 80048c4: 46bd mov sp, r7 + 80048c6: bd80 pop {r7, pc} + 80048c8: 08011920 .word 0x08011920 + 80048cc: 08011948 .word 0x08011948 + +080048d0 : +/** Handle control connection acknowledge of sent data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) { + 80048d0: b580 push {r7, lr} + 80048d2: b084 sub sp, #16 + 80048d4: af00 add r7, sp, #0 + 80048d6: 60f8 str r0, [r7, #12] + 80048d8: 60b9 str r1, [r7, #8] + 80048da: 4613 mov r3, r2 + 80048dc: 80fb strh r3, [r7, #6] + LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:successfully sent %d bytes\n",len)); + 80048de: 88fb ldrh r3, [r7, #6] + 80048e0: 4619 mov r1, r3 + 80048e2: 4804 ldr r0, [pc, #16] ; (80048f4 ) + 80048e4: f00c f970 bl 8010bc8 + return ERR_OK; + 80048e8: 2300 movs r3, #0 +} + 80048ea: 4618 mov r0, r3 + 80048ec: 3710 adds r7, #16 + 80048ee: 46bd mov sp, r7 + 80048f0: bd80 pop {r7, pc} + 80048f2: bf00 nop + 80048f4: 08011968 .word 0x08011968 + +080048f8 : + +/** Handle control connection error + * @param pointer to lwftp session data + * @param state of connection + */ +static void lwftp_control_err(void *arg, err_t err) { + 80048f8: b580 push {r7, lr} + 80048fa: b084 sub sp, #16 + 80048fc: af00 add r7, sp, #0 + 80048fe: 6078 str r0, [r7, #4] + 8004900: 460b mov r3, r1 + 8004902: 70fb strb r3, [r7, #3] + LWIP_UNUSED_ARG(err); + if (arg != NULL) { + 8004904: 687b ldr r3, [r7, #4] + 8004906: 2b00 cmp r3, #0 + 8004908: d01f beq.n 800494a + lwftp_session_t *s = (lwftp_session_t*) arg; + 800490a: 687b ldr r3, [r7, #4] + 800490c: 60bb str r3, [r7, #8] + int result; + if (s->control_state == LWFTP_CLOSED) { + 800490e: 68bb ldr r3, [r7, #8] + 8004910: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 8004914: 2b00 cmp r3, #0 + 8004916: d10c bne.n 8004932 + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed to connect to server (%s)\n",lwip_strerr(err))); + 8004918: f997 3003 ldrsb.w r3, [r7, #3] + 800491c: 4618 mov r0, r3 + 800491e: f000 fdf5 bl 800550c + 8004922: 4603 mov r3, r0 + 8004924: 4619 mov r1, r3 + 8004926: 480b ldr r0, [pc, #44] ; (8004954 ) + 8004928: f00c f94e bl 8010bc8 + result = LWFTP_RESULT_ERR_CONNECT; + 800492c: 2306 movs r3, #6 + 800492e: 60fb str r3, [r7, #12] + 8004930: e004 b.n 800493c + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n")); + 8004932: 4809 ldr r0, [pc, #36] ; (8004958 ) + 8004934: f00c f9b6 bl 8010ca4 + result = LWFTP_RESULT_ERR_CLOSED; + 8004938: 2308 movs r3, #8 + 800493a: 60fb str r3, [r7, #12] + } + s->control_pcb = NULL; // No need to de-allocate PCB + 800493c: 68bb ldr r3, [r7, #8] + 800493e: 2200 movs r2, #0 + 8004940: 62da str r2, [r3, #44] ; 0x2c + lwftp_control_close(s, result); + 8004942: 68f9 ldr r1, [r7, #12] + 8004944: 68b8 ldr r0, [r7, #8] + 8004946: f7ff fd73 bl 8004430 + } +} + 800494a: bf00 nop + 800494c: 3710 adds r7, #16 + 800494e: 46bd mov sp, r7 + 8004950: bd80 pop {r7, pc} + 8004952: bf00 nop + 8004954: 0801198c .word 0x0801198c + 8004958: 08011920 .word 0x08011920 + +0800495c : +/** Process newly connected PCB + * @param pointer to lwftp session data + * @param pointer to PCB + * @param state of connection + */ +static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) { + 800495c: b580 push {r7, lr} + 800495e: b086 sub sp, #24 + 8004960: af00 add r7, sp, #0 + 8004962: 60f8 str r0, [r7, #12] + 8004964: 60b9 str r1, [r7, #8] + 8004966: 4613 mov r3, r2 + 8004968: 71fb strb r3, [r7, #7] + lwftp_session_t *s = (lwftp_session_t*) arg; + 800496a: 68fb ldr r3, [r7, #12] + 800496c: 617b str r3, [r7, #20] + + if (err == ERR_OK) { + 800496e: f997 3007 ldrsb.w r3, [r7, #7] + 8004972: 2b00 cmp r3, #0 + 8004974: d103 bne.n 800497e + LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected to server\n")); + 8004976: 480f ldr r0, [pc, #60] ; (80049b4 ) + 8004978: f00c f994 bl 8010ca4 + 800497c: e014 b.n 80049a8 + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in control_connected (%s)\n", lwip_strerr(err))); + 800497e: f997 3007 ldrsb.w r3, [r7, #7] + 8004982: 4618 mov r0, r3 + 8004984: f000 fdc2 bl 800550c + 8004988: 4603 mov r3, r0 + 800498a: 4619 mov r1, r3 + 800498c: 480a ldr r0, [pc, #40] ; (80049b8 ) + 800498e: f00c f91b bl 8010bc8 + if (s->done_fn) { + 8004992: 697b ldr r3, [r7, #20] + 8004994: 6a1b ldr r3, [r3, #32] + 8004996: 2b00 cmp r3, #0 + 8004998: d006 beq.n 80049a8 + s->done_fn(s->handle, LWFTP_RESULT_ERR_CONNECT); // 연결 실패 상태 전달 + 800499a: 697b ldr r3, [r7, #20] + 800499c: 6a1b ldr r3, [r3, #32] + 800499e: 697a ldr r2, [r7, #20] + 80049a0: 6952 ldr r2, [r2, #20] + 80049a2: 2106 movs r1, #6 + 80049a4: 4610 mov r0, r2 + 80049a6: 4798 blx r3 + } + } + return err; + 80049a8: f997 3007 ldrsb.w r3, [r7, #7] +} + 80049ac: 4618 mov r0, r3 + 80049ae: 3718 adds r7, #24 + 80049b0: 46bd mov sp, r7 + 80049b2: bd80 pop {r7, pc} + 80049b4: 080119b4 .word 0x080119b4 + 80049b8: 080119d0 .word 0x080119d0 + +080049bc : + +/** Open a control session + * @param Session structure + */ +err_t lwftp_connect(lwftp_session_t *s) { + 80049bc: b580 push {r7, lr} + 80049be: b084 sub sp, #16 + 80049c0: af00 add r7, sp, #0 + 80049c2: 6078 str r0, [r7, #4] + err_t error; + enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN; + 80049c4: 2303 movs r3, #3 + 80049c6: 73fb strb r3, [r7, #15] + + // Check user supplied data + if ((s->control_state != LWFTP_CLOSED) || s->control_pcb || s->data_pcb + 80049c8: 687b ldr r3, [r7, #4] + 80049ca: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80049ce: 2b00 cmp r3, #0 + 80049d0: d10f bne.n 80049f2 + 80049d2: 687b ldr r3, [r7, #4] + 80049d4: 6adb ldr r3, [r3, #44] ; 0x2c + 80049d6: 2b00 cmp r3, #0 + 80049d8: d10b bne.n 80049f2 + 80049da: 687b ldr r3, [r7, #4] + 80049dc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80049de: 2b00 cmp r3, #0 + 80049e0: d107 bne.n 80049f2 + || !s->user || !s->pass) { + 80049e2: 687b ldr r3, [r7, #4] + 80049e4: 68db ldr r3, [r3, #12] + 80049e6: 2b00 cmp r3, #0 + 80049e8: d003 beq.n 80049f2 + 80049ea: 687b ldr r3, [r7, #4] + 80049ec: 691b ldr r3, [r3, #16] + 80049ee: 2b00 cmp r3, #0 + 80049f0: d105 bne.n 80049fe + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid control session\n")); + 80049f2: 482f ldr r0, [pc, #188] ; (8004ab0 ) + 80049f4: f00c f956 bl 8010ca4 + retval = LWFTP_RESULT_ERR_ARGUMENT; + 80049f8: 2304 movs r3, #4 + 80049fa: 73fb strb r3, [r7, #15] + goto exit; + 80049fc: e046 b.n 8004a8c + } + // Get sessions pcb + s->control_pcb = tcp_new(); + 80049fe: f004 f8a7 bl 8008b50 + 8004a02: 4602 mov r2, r0 + 8004a04: 687b ldr r3, [r7, #4] + 8004a06: 62da str r2, [r3, #44] ; 0x2c + if (!s->control_pcb) { + 8004a08: 687b ldr r3, [r7, #4] + 8004a0a: 6adb ldr r3, [r3, #44] ; 0x2c + 8004a0c: 2b00 cmp r3, #0 + 8004a0e: d105 bne.n 8004a1c + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc control_pcb (low memory?)\n")); + 8004a10: 4828 ldr r0, [pc, #160] ; (8004ab4 ) + 8004a12: f00c f947 bl 8010ca4 + retval = LWFTP_RESULT_ERR_MEMORY; + 8004a16: 2305 movs r3, #5 + 8004a18: 73fb strb r3, [r7, #15] + goto exit; + 8004a1a: e037 b.n 8004a8c + } + // Open control session + tcp_arg(s->control_pcb, s); + 8004a1c: 687b ldr r3, [r7, #4] + 8004a1e: 6adb ldr r3, [r3, #44] ; 0x2c + 8004a20: 6879 ldr r1, [r7, #4] + 8004a22: 4618 mov r0, r3 + 8004a24: f004 f89c bl 8008b60 + tcp_err(s->control_pcb, lwftp_control_err); + 8004a28: 687b ldr r3, [r7, #4] + 8004a2a: 6adb ldr r3, [r3, #44] ; 0x2c + 8004a2c: 4922 ldr r1, [pc, #136] ; (8004ab8 ) + 8004a2e: 4618 mov r0, r3 + 8004a30: f004 f8ec bl 8008c0c + tcp_recv(s->control_pcb, lwftp_control_recv); + 8004a34: 687b ldr r3, [r7, #4] + 8004a36: 6adb ldr r3, [r3, #44] ; 0x2c + 8004a38: 4920 ldr r1, [pc, #128] ; (8004abc ) + 8004a3a: 4618 mov r0, r3 + 8004a3c: f004 f8a2 bl 8008b84 + tcp_sent(s->control_pcb, lwftp_control_sent); + 8004a40: 687b ldr r3, [r7, #4] + 8004a42: 6adb ldr r3, [r3, #44] ; 0x2c + 8004a44: 491e ldr r1, [pc, #120] ; (8004ac0 ) + 8004a46: 4618 mov r0, r3 + 8004a48: f004 f8be bl 8008bc8 + error = tcp_connect(s->control_pcb, &s->server_ip, s->server_port, + 8004a4c: 687b ldr r3, [r7, #4] + 8004a4e: 6ad8 ldr r0, [r3, #44] ; 0x2c + 8004a50: 6879 ldr r1, [r7, #4] + 8004a52: 687b ldr r3, [r7, #4] + 8004a54: 889a ldrh r2, [r3, #4] + 8004a56: 4b1b ldr r3, [pc, #108] ; (8004ac4 ) + 8004a58: f003 f940 bl 8007cdc + 8004a5c: 4603 mov r3, r0 + 8004a5e: 73bb strb r3, [r7, #14] + lwftp_control_connected); + if (error == ERR_OK) { + 8004a60: f997 300e ldrsb.w r3, [r7, #14] + 8004a64: 2b00 cmp r3, #0 + 8004a66: d102 bne.n 8004a6e + retval = LWFTP_RESULT_INPROGRESS; + 8004a68: 2301 movs r3, #1 + 8004a6a: 73fb strb r3, [r7, #15] + goto exit; + 8004a6c: e00e b.n 8004a8c + } + + // Release pcbs in case of failure + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot connect control_pcb (%s)\n", lwip_strerr(error))); + 8004a6e: f997 300e ldrsb.w r3, [r7, #14] + 8004a72: 4618 mov r0, r3 + 8004a74: f000 fd4a bl 800550c + 8004a78: 4603 mov r3, r0 + 8004a7a: 4619 mov r1, r3 + 8004a7c: 4812 ldr r0, [pc, #72] ; (8004ac8 ) + 8004a7e: f00c f8a3 bl 8010bc8 + lwftp_control_close(s, -1); + 8004a82: f04f 31ff mov.w r1, #4294967295 + 8004a86: 6878 ldr r0, [r7, #4] + 8004a88: f7ff fcd2 bl 8004430 + + exit: if (s->done_fn) + 8004a8c: 687b ldr r3, [r7, #4] + 8004a8e: 6a1b ldr r3, [r3, #32] + 8004a90: 2b00 cmp r3, #0 + 8004a92: d006 beq.n 8004aa2 + s->done_fn(s->handle, retval); + 8004a94: 687b ldr r3, [r7, #4] + 8004a96: 6a1b ldr r3, [r3, #32] + 8004a98: 687a ldr r2, [r7, #4] + 8004a9a: 6952 ldr r2, [r2, #20] + 8004a9c: 7bf9 ldrb r1, [r7, #15] + 8004a9e: 4610 mov r0, r2 + 8004aa0: 4798 blx r3 + return retval; + 8004aa2: f997 300f ldrsb.w r3, [r7, #15] +} + 8004aa6: 4618 mov r0, r3 + 8004aa8: 3710 adds r7, #16 + 8004aaa: 46bd mov sp, r7 + 8004aac: bd80 pop {r7, pc} + 8004aae: bf00 nop + 8004ab0: 080119f8 .word 0x080119f8 + 8004ab4: 08011a18 .word 0x08011a18 + 8004ab8: 080048f9 .word 0x080048f9 + 8004abc: 08004859 .word 0x08004859 + 8004ac0: 080048d1 .word 0x080048d1 + 8004ac4: 0800495d .word 0x0800495d + 8004ac8: 08011a48 .word 0x08011a48 + +08004acc : + +/** + * LwIP initialization function + */ +void MX_LWIP_Init(void) +{ + 8004acc: b580 push {r7, lr} + 8004ace: b084 sub sp, #16 + 8004ad0: af04 add r7, sp, #16 + /* IP addresses initialization */ + IP_ADDRESS[0] = 192; + 8004ad2: 4b87 ldr r3, [pc, #540] ; (8004cf0 ) + 8004ad4: 22c0 movs r2, #192 ; 0xc0 + 8004ad6: 701a strb r2, [r3, #0] + IP_ADDRESS[1] = 168; + 8004ad8: 4b85 ldr r3, [pc, #532] ; (8004cf0 ) + 8004ada: 22a8 movs r2, #168 ; 0xa8 + 8004adc: 705a strb r2, [r3, #1] + IP_ADDRESS[2] = 0; + 8004ade: 4b84 ldr r3, [pc, #528] ; (8004cf0 ) + 8004ae0: 2200 movs r2, #0 + 8004ae2: 709a strb r2, [r3, #2] + IP_ADDRESS[3] = 120; + 8004ae4: 4b82 ldr r3, [pc, #520] ; (8004cf0 ) + 8004ae6: 2278 movs r2, #120 ; 0x78 + 8004ae8: 70da strb r2, [r3, #3] + NETMASK_ADDRESS[0] = 255; + 8004aea: 4b82 ldr r3, [pc, #520] ; (8004cf4 ) + 8004aec: 22ff movs r2, #255 ; 0xff + 8004aee: 701a strb r2, [r3, #0] + NETMASK_ADDRESS[1] = 255; + 8004af0: 4b80 ldr r3, [pc, #512] ; (8004cf4 ) + 8004af2: 22ff movs r2, #255 ; 0xff + 8004af4: 705a strb r2, [r3, #1] + NETMASK_ADDRESS[2] = 255; + 8004af6: 4b7f ldr r3, [pc, #508] ; (8004cf4 ) + 8004af8: 22ff movs r2, #255 ; 0xff + 8004afa: 709a strb r2, [r3, #2] + NETMASK_ADDRESS[3] = 0; + 8004afc: 4b7d ldr r3, [pc, #500] ; (8004cf4 ) + 8004afe: 2200 movs r2, #0 + 8004b00: 70da strb r2, [r3, #3] + GATEWAY_ADDRESS[0] = 0; + 8004b02: 4b7d ldr r3, [pc, #500] ; (8004cf8 ) + 8004b04: 2200 movs r2, #0 + 8004b06: 701a strb r2, [r3, #0] + GATEWAY_ADDRESS[1] = 0; + 8004b08: 4b7b ldr r3, [pc, #492] ; (8004cf8 ) + 8004b0a: 2200 movs r2, #0 + 8004b0c: 705a strb r2, [r3, #1] + GATEWAY_ADDRESS[2] = 0; + 8004b0e: 4b7a ldr r3, [pc, #488] ; (8004cf8 ) + 8004b10: 2200 movs r2, #0 + 8004b12: 709a strb r2, [r3, #2] + GATEWAY_ADDRESS[3] = 0; + 8004b14: 4b78 ldr r3, [pc, #480] ; (8004cf8 ) + 8004b16: 2200 movs r2, #0 + 8004b18: 70da strb r2, [r3, #3] + +/* USER CODE BEGIN IP_ADDRESSES */ +/* USER CODE END IP_ADDRESSES */ + + /* Initilialize the LwIP stack without RTOS */ + lwip_init(); + 8004b1a: f000 fe01 bl 8005720 + + /* IP addresses initialization without DHCP (IPv4) */ + IP4_ADDR(&ipaddr, IP_ADDRESS[0], IP_ADDRESS[1], IP_ADDRESS[2], IP_ADDRESS[3]); + 8004b1e: 4b74 ldr r3, [pc, #464] ; (8004cf0 ) + 8004b20: 781b ldrb r3, [r3, #0] + 8004b22: 061a lsls r2, r3, #24 + 8004b24: 4b72 ldr r3, [pc, #456] ; (8004cf0 ) + 8004b26: 785b ldrb r3, [r3, #1] + 8004b28: 041b lsls r3, r3, #16 + 8004b2a: 431a orrs r2, r3 + 8004b2c: 4b70 ldr r3, [pc, #448] ; (8004cf0 ) + 8004b2e: 789b ldrb r3, [r3, #2] + 8004b30: 021b lsls r3, r3, #8 + 8004b32: 4313 orrs r3, r2 + 8004b34: 4a6e ldr r2, [pc, #440] ; (8004cf0 ) + 8004b36: 78d2 ldrb r2, [r2, #3] + 8004b38: 4313 orrs r3, r2 + 8004b3a: 061a lsls r2, r3, #24 + 8004b3c: 4b6c ldr r3, [pc, #432] ; (8004cf0 ) + 8004b3e: 781b ldrb r3, [r3, #0] + 8004b40: 0619 lsls r1, r3, #24 + 8004b42: 4b6b ldr r3, [pc, #428] ; (8004cf0 ) + 8004b44: 785b ldrb r3, [r3, #1] + 8004b46: 041b lsls r3, r3, #16 + 8004b48: 4319 orrs r1, r3 + 8004b4a: 4b69 ldr r3, [pc, #420] ; (8004cf0 ) + 8004b4c: 789b ldrb r3, [r3, #2] + 8004b4e: 021b lsls r3, r3, #8 + 8004b50: 430b orrs r3, r1 + 8004b52: 4967 ldr r1, [pc, #412] ; (8004cf0 ) + 8004b54: 78c9 ldrb r1, [r1, #3] + 8004b56: 430b orrs r3, r1 + 8004b58: 021b lsls r3, r3, #8 + 8004b5a: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8004b5e: 431a orrs r2, r3 + 8004b60: 4b63 ldr r3, [pc, #396] ; (8004cf0 ) + 8004b62: 781b ldrb r3, [r3, #0] + 8004b64: 0619 lsls r1, r3, #24 + 8004b66: 4b62 ldr r3, [pc, #392] ; (8004cf0 ) + 8004b68: 785b ldrb r3, [r3, #1] + 8004b6a: 041b lsls r3, r3, #16 + 8004b6c: 4319 orrs r1, r3 + 8004b6e: 4b60 ldr r3, [pc, #384] ; (8004cf0 ) + 8004b70: 789b ldrb r3, [r3, #2] + 8004b72: 021b lsls r3, r3, #8 + 8004b74: 430b orrs r3, r1 + 8004b76: 495e ldr r1, [pc, #376] ; (8004cf0 ) + 8004b78: 78c9 ldrb r1, [r1, #3] + 8004b7a: 430b orrs r3, r1 + 8004b7c: 0a1b lsrs r3, r3, #8 + 8004b7e: f403 437f and.w r3, r3, #65280 ; 0xff00 + 8004b82: 431a orrs r2, r3 + 8004b84: 4b5a ldr r3, [pc, #360] ; (8004cf0 ) + 8004b86: 781b ldrb r3, [r3, #0] + 8004b88: 0619 lsls r1, r3, #24 + 8004b8a: 4b59 ldr r3, [pc, #356] ; (8004cf0 ) + 8004b8c: 785b ldrb r3, [r3, #1] + 8004b8e: 041b lsls r3, r3, #16 + 8004b90: 4319 orrs r1, r3 + 8004b92: 4b57 ldr r3, [pc, #348] ; (8004cf0 ) + 8004b94: 789b ldrb r3, [r3, #2] + 8004b96: 021b lsls r3, r3, #8 + 8004b98: 430b orrs r3, r1 + 8004b9a: 4955 ldr r1, [pc, #340] ; (8004cf0 ) + 8004b9c: 78c9 ldrb r1, [r1, #3] + 8004b9e: 430b orrs r3, r1 + 8004ba0: 0e1b lsrs r3, r3, #24 + 8004ba2: 4313 orrs r3, r2 + 8004ba4: 4a55 ldr r2, [pc, #340] ; (8004cfc ) + 8004ba6: 6013 str r3, [r2, #0] + IP4_ADDR(&netmask, NETMASK_ADDRESS[0], NETMASK_ADDRESS[1] , NETMASK_ADDRESS[2], NETMASK_ADDRESS[3]); + 8004ba8: 4b52 ldr r3, [pc, #328] ; (8004cf4 ) + 8004baa: 781b ldrb r3, [r3, #0] + 8004bac: 061a lsls r2, r3, #24 + 8004bae: 4b51 ldr r3, [pc, #324] ; (8004cf4 ) + 8004bb0: 785b ldrb r3, [r3, #1] + 8004bb2: 041b lsls r3, r3, #16 + 8004bb4: 431a orrs r2, r3 + 8004bb6: 4b4f ldr r3, [pc, #316] ; (8004cf4 ) + 8004bb8: 789b ldrb r3, [r3, #2] + 8004bba: 021b lsls r3, r3, #8 + 8004bbc: 4313 orrs r3, r2 + 8004bbe: 4a4d ldr r2, [pc, #308] ; (8004cf4 ) + 8004bc0: 78d2 ldrb r2, [r2, #3] + 8004bc2: 4313 orrs r3, r2 + 8004bc4: 061a lsls r2, r3, #24 + 8004bc6: 4b4b ldr r3, [pc, #300] ; (8004cf4 ) + 8004bc8: 781b ldrb r3, [r3, #0] + 8004bca: 0619 lsls r1, r3, #24 + 8004bcc: 4b49 ldr r3, [pc, #292] ; (8004cf4 ) + 8004bce: 785b ldrb r3, [r3, #1] + 8004bd0: 041b lsls r3, r3, #16 + 8004bd2: 4319 orrs r1, r3 + 8004bd4: 4b47 ldr r3, [pc, #284] ; (8004cf4 ) + 8004bd6: 789b ldrb r3, [r3, #2] + 8004bd8: 021b lsls r3, r3, #8 + 8004bda: 430b orrs r3, r1 + 8004bdc: 4945 ldr r1, [pc, #276] ; (8004cf4 ) + 8004bde: 78c9 ldrb r1, [r1, #3] + 8004be0: 430b orrs r3, r1 + 8004be2: 021b lsls r3, r3, #8 + 8004be4: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8004be8: 431a orrs r2, r3 + 8004bea: 4b42 ldr r3, [pc, #264] ; (8004cf4 ) + 8004bec: 781b ldrb r3, [r3, #0] + 8004bee: 0619 lsls r1, r3, #24 + 8004bf0: 4b40 ldr r3, [pc, #256] ; (8004cf4 ) + 8004bf2: 785b ldrb r3, [r3, #1] + 8004bf4: 041b lsls r3, r3, #16 + 8004bf6: 4319 orrs r1, r3 + 8004bf8: 4b3e ldr r3, [pc, #248] ; (8004cf4 ) + 8004bfa: 789b ldrb r3, [r3, #2] + 8004bfc: 021b lsls r3, r3, #8 + 8004bfe: 430b orrs r3, r1 + 8004c00: 493c ldr r1, [pc, #240] ; (8004cf4 ) + 8004c02: 78c9 ldrb r1, [r1, #3] + 8004c04: 430b orrs r3, r1 + 8004c06: 0a1b lsrs r3, r3, #8 + 8004c08: f403 437f and.w r3, r3, #65280 ; 0xff00 + 8004c0c: 431a orrs r2, r3 + 8004c0e: 4b39 ldr r3, [pc, #228] ; (8004cf4 ) + 8004c10: 781b ldrb r3, [r3, #0] + 8004c12: 0619 lsls r1, r3, #24 + 8004c14: 4b37 ldr r3, [pc, #220] ; (8004cf4 ) + 8004c16: 785b ldrb r3, [r3, #1] + 8004c18: 041b lsls r3, r3, #16 + 8004c1a: 4319 orrs r1, r3 + 8004c1c: 4b35 ldr r3, [pc, #212] ; (8004cf4 ) + 8004c1e: 789b ldrb r3, [r3, #2] + 8004c20: 021b lsls r3, r3, #8 + 8004c22: 430b orrs r3, r1 + 8004c24: 4933 ldr r1, [pc, #204] ; (8004cf4 ) + 8004c26: 78c9 ldrb r1, [r1, #3] + 8004c28: 430b orrs r3, r1 + 8004c2a: 0e1b lsrs r3, r3, #24 + 8004c2c: 4313 orrs r3, r2 + 8004c2e: 4a34 ldr r2, [pc, #208] ; (8004d00 ) + 8004c30: 6013 str r3, [r2, #0] + IP4_ADDR(&gw, GATEWAY_ADDRESS[0], GATEWAY_ADDRESS[1], GATEWAY_ADDRESS[2], GATEWAY_ADDRESS[3]); + 8004c32: 4b31 ldr r3, [pc, #196] ; (8004cf8 ) + 8004c34: 781b ldrb r3, [r3, #0] + 8004c36: 061a lsls r2, r3, #24 + 8004c38: 4b2f ldr r3, [pc, #188] ; (8004cf8 ) + 8004c3a: 785b ldrb r3, [r3, #1] + 8004c3c: 041b lsls r3, r3, #16 + 8004c3e: 431a orrs r2, r3 + 8004c40: 4b2d ldr r3, [pc, #180] ; (8004cf8 ) + 8004c42: 789b ldrb r3, [r3, #2] + 8004c44: 021b lsls r3, r3, #8 + 8004c46: 4313 orrs r3, r2 + 8004c48: 4a2b ldr r2, [pc, #172] ; (8004cf8 ) + 8004c4a: 78d2 ldrb r2, [r2, #3] + 8004c4c: 4313 orrs r3, r2 + 8004c4e: 061a lsls r2, r3, #24 + 8004c50: 4b29 ldr r3, [pc, #164] ; (8004cf8 ) + 8004c52: 781b ldrb r3, [r3, #0] + 8004c54: 0619 lsls r1, r3, #24 + 8004c56: 4b28 ldr r3, [pc, #160] ; (8004cf8 ) + 8004c58: 785b ldrb r3, [r3, #1] + 8004c5a: 041b lsls r3, r3, #16 + 8004c5c: 4319 orrs r1, r3 + 8004c5e: 4b26 ldr r3, [pc, #152] ; (8004cf8 ) + 8004c60: 789b ldrb r3, [r3, #2] + 8004c62: 021b lsls r3, r3, #8 + 8004c64: 430b orrs r3, r1 + 8004c66: 4924 ldr r1, [pc, #144] ; (8004cf8 ) + 8004c68: 78c9 ldrb r1, [r1, #3] + 8004c6a: 430b orrs r3, r1 + 8004c6c: 021b lsls r3, r3, #8 + 8004c6e: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 8004c72: 431a orrs r2, r3 + 8004c74: 4b20 ldr r3, [pc, #128] ; (8004cf8 ) + 8004c76: 781b ldrb r3, [r3, #0] + 8004c78: 0619 lsls r1, r3, #24 + 8004c7a: 4b1f ldr r3, [pc, #124] ; (8004cf8 ) + 8004c7c: 785b ldrb r3, [r3, #1] + 8004c7e: 041b lsls r3, r3, #16 + 8004c80: 4319 orrs r1, r3 + 8004c82: 4b1d ldr r3, [pc, #116] ; (8004cf8 ) + 8004c84: 789b ldrb r3, [r3, #2] + 8004c86: 021b lsls r3, r3, #8 + 8004c88: 430b orrs r3, r1 + 8004c8a: 491b ldr r1, [pc, #108] ; (8004cf8 ) + 8004c8c: 78c9 ldrb r1, [r1, #3] + 8004c8e: 430b orrs r3, r1 + 8004c90: 0a1b lsrs r3, r3, #8 + 8004c92: f403 437f and.w r3, r3, #65280 ; 0xff00 + 8004c96: 431a orrs r2, r3 + 8004c98: 4b17 ldr r3, [pc, #92] ; (8004cf8 ) + 8004c9a: 781b ldrb r3, [r3, #0] + 8004c9c: 0619 lsls r1, r3, #24 + 8004c9e: 4b16 ldr r3, [pc, #88] ; (8004cf8 ) + 8004ca0: 785b ldrb r3, [r3, #1] + 8004ca2: 041b lsls r3, r3, #16 + 8004ca4: 4319 orrs r1, r3 + 8004ca6: 4b14 ldr r3, [pc, #80] ; (8004cf8 ) + 8004ca8: 789b ldrb r3, [r3, #2] + 8004caa: 021b lsls r3, r3, #8 + 8004cac: 430b orrs r3, r1 + 8004cae: 4912 ldr r1, [pc, #72] ; (8004cf8 ) + 8004cb0: 78c9 ldrb r1, [r1, #3] + 8004cb2: 430b orrs r3, r1 + 8004cb4: 0e1b lsrs r3, r3, #24 + 8004cb6: 4313 orrs r3, r2 + 8004cb8: 4a12 ldr r2, [pc, #72] ; (8004d04 ) + 8004cba: 6013 str r3, [r2, #0] + + /* add the network interface (IPv4/IPv6) without RTOS */ + netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, ðernet_input); + 8004cbc: 4b12 ldr r3, [pc, #72] ; (8004d08 ) + 8004cbe: 9302 str r3, [sp, #8] + 8004cc0: 4b12 ldr r3, [pc, #72] ; (8004d0c ) + 8004cc2: 9301 str r3, [sp, #4] + 8004cc4: 2300 movs r3, #0 + 8004cc6: 9300 str r3, [sp, #0] + 8004cc8: 4b0e ldr r3, [pc, #56] ; (8004d04 ) + 8004cca: 4a0d ldr r2, [pc, #52] ; (8004d00 ) + 8004ccc: 490b ldr r1, [pc, #44] ; (8004cfc ) + 8004cce: 4810 ldr r0, [pc, #64] ; (8004d10 ) + 8004cd0: f001 fa46 bl 8006160 + + /* Registers the default network interface */ + netif_set_default(&gnetif); + 8004cd4: 480e ldr r0, [pc, #56] ; (8004d10 ) + 8004cd6: f001 fcd7 bl 8006688 + + /* We must always bring the network interface up connection or not... */ + netif_set_up(&gnetif); + 8004cda: 480d ldr r0, [pc, #52] ; (8004d10 ) + 8004cdc: f001 fcf8 bl 80066d0 + + /* Set the link callback function, this function is called on change of link status*/ + netif_set_link_callback(&gnetif, ethernet_link_status_updated); + 8004ce0: 490c ldr r1, [pc, #48] ; (8004d14 ) + 8004ce2: 480b ldr r0, [pc, #44] ; (8004d10 ) + 8004ce4: f001 fdf6 bl 80068d4 + /* Create the Ethernet link handler thread */ + +/* USER CODE BEGIN 3 */ + +/* USER CODE END 3 */ +} + 8004ce8: bf00 nop + 8004cea: 46bd mov sp, r7 + 8004cec: bd80 pop {r7, pc} + 8004cee: bf00 nop + 8004cf0: 24000170 .word 0x24000170 + 8004cf4: 24000174 .word 0x24000174 + 8004cf8: 24000178 .word 0x24000178 + 8004cfc: 24000164 .word 0x24000164 + 8004d00: 24000168 .word 0x24000168 + 8004d04: 2400016c .word 0x2400016c + 8004d08: 080100b5 .word 0x080100b5 + 8004d0c: 08005021 .word 0x08005021 + 8004d10: 24000130 .word 0x24000130 + 8004d14: 08004d69 .word 0x08004d69 + +08004d18 : + * @brief Ethernet Link periodic check + * @param netif + * @retval None + */ +static void Ethernet_Link_Periodic_Handle(struct netif *netif) +{ + 8004d18: b580 push {r7, lr} + 8004d1a: b082 sub sp, #8 + 8004d1c: af00 add r7, sp, #0 + 8004d1e: 6078 str r0, [r7, #4] +/* USER CODE BEGIN 4_4_1 */ +/* USER CODE END 4_4_1 */ + + /* Ethernet Link every 100ms */ + if (HAL_GetTick() - EthernetLinkTimer >= 100) + 8004d20: f7fc f974 bl 800100c + 8004d24: 4602 mov r2, r0 + 8004d26: 4b08 ldr r3, [pc, #32] ; (8004d48 ) + 8004d28: 681b ldr r3, [r3, #0] + 8004d2a: 1ad3 subs r3, r2, r3 + 8004d2c: 2b63 cmp r3, #99 ; 0x63 + 8004d2e: d907 bls.n 8004d40 + { + EthernetLinkTimer = HAL_GetTick(); + 8004d30: f7fc f96c bl 800100c + 8004d34: 4603 mov r3, r0 + 8004d36: 4a04 ldr r2, [pc, #16] ; (8004d48 ) + 8004d38: 6013 str r3, [r2, #0] + ethernet_link_check_state(netif); + 8004d3a: 6878 ldr r0, [r7, #4] + 8004d3c: f000 fac2 bl 80052c4 + } +/* USER CODE BEGIN 4_4 */ +/* USER CODE END 4_4 */ +} + 8004d40: bf00 nop + 8004d42: 3708 adds r7, #8 + 8004d44: 46bd mov sp, r7 + 8004d46: bd80 pop {r7, pc} + 8004d48: 2400012c .word 0x2400012c + +08004d4c : + * Send it to the lwIP stack for handling + * Handle timeouts if LWIP_TIMERS is set and without RTOS + * Handle the llink status if LWIP_NETIF_LINK_CALLBACK is set and without RTOS + */ +void MX_LWIP_Process(void) +{ + 8004d4c: b580 push {r7, lr} + 8004d4e: af00 add r7, sp, #0 +/* USER CODE BEGIN 4_1 */ +/* USER CODE END 4_1 */ + ethernetif_input(&gnetif); + 8004d50: 4804 ldr r0, [pc, #16] ; (8004d64 ) + 8004d52: f000 f945 bl 8004fe0 + +/* USER CODE BEGIN 4_2 */ +/* USER CODE END 4_2 */ + /* Handle timeouts */ + sys_check_timeouts(); + 8004d56: f008 fcd7 bl 800d708 + + Ethernet_Link_Periodic_Handle(&gnetif); + 8004d5a: 4802 ldr r0, [pc, #8] ; (8004d64 ) + 8004d5c: f7ff ffdc bl 8004d18 + +/* USER CODE BEGIN 4_3 */ +/* USER CODE END 4_3 */ +} + 8004d60: bf00 nop + 8004d62: bd80 pop {r7, pc} + 8004d64: 24000130 .word 0x24000130 + +08004d68 : + * @brief Notify the User about the network interface config status + * @param netif: the network interface + * @retval None + */ +static void ethernet_link_status_updated(struct netif *netif) +{ + 8004d68: b480 push {r7} + 8004d6a: b083 sub sp, #12 + 8004d6c: af00 add r7, sp, #0 + 8004d6e: 6078 str r0, [r7, #4] + else /* netif is down */ + { +/* USER CODE BEGIN 6 */ +/* USER CODE END 6 */ + } +} + 8004d70: bf00 nop + 8004d72: 370c adds r7, #12 + 8004d74: 46bd mov sp, r7 + 8004d76: f85d 7b04 ldr.w r7, [sp], #4 + 8004d7a: 4770 bx lr + +08004d7c : + * + * @param netif the already initialized lwip network interface structure + * for this ethernetif + */ +static void low_level_init(struct netif *netif) +{ + 8004d7c: b580 push {r7, lr} + 8004d7e: b084 sub sp, #16 + 8004d80: af00 add r7, sp, #0 + 8004d82: 6078 str r0, [r7, #4] + HAL_StatusTypeDef hal_eth_init_status = HAL_OK; + 8004d84: 2300 movs r3, #0 + 8004d86: 73fb strb r3, [r7, #15] + /* Start ETH HAL Init */ + + uint8_t MACAddr[6] ; + heth.Instance = ETH; + 8004d88: 4b3f ldr r3, [pc, #252] ; (8004e88 ) + 8004d8a: 4a40 ldr r2, [pc, #256] ; (8004e8c ) + 8004d8c: 601a str r2, [r3, #0] + MACAddr[0] = 0x00; + 8004d8e: 2300 movs r3, #0 + 8004d90: 723b strb r3, [r7, #8] + MACAddr[1] = 0x80; + 8004d92: 2380 movs r3, #128 ; 0x80 + 8004d94: 727b strb r3, [r7, #9] + MACAddr[2] = 0xE1; + 8004d96: 23e1 movs r3, #225 ; 0xe1 + 8004d98: 72bb strb r3, [r7, #10] + MACAddr[3] = 0x00; + 8004d9a: 2300 movs r3, #0 + 8004d9c: 72fb strb r3, [r7, #11] + MACAddr[4] = 0x00; + 8004d9e: 2300 movs r3, #0 + 8004da0: 733b strb r3, [r7, #12] + MACAddr[5] = 0x00; + 8004da2: 2300 movs r3, #0 + 8004da4: 737b strb r3, [r7, #13] + heth.Init.MACAddr = &MACAddr[0]; + 8004da6: 4a38 ldr r2, [pc, #224] ; (8004e88 ) + 8004da8: f107 0308 add.w r3, r7, #8 + 8004dac: 6053 str r3, [r2, #4] + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + 8004dae: 4b36 ldr r3, [pc, #216] ; (8004e88 ) + 8004db0: 2201 movs r2, #1 + 8004db2: 721a strb r2, [r3, #8] + heth.Init.TxDesc = DMATxDscrTab; + 8004db4: 4b34 ldr r3, [pc, #208] ; (8004e88 ) + 8004db6: 4a36 ldr r2, [pc, #216] ; (8004e90 ) + 8004db8: 60da str r2, [r3, #12] + heth.Init.RxDesc = DMARxDscrTab; + 8004dba: 4b33 ldr r3, [pc, #204] ; (8004e88 ) + 8004dbc: 4a35 ldr r2, [pc, #212] ; (8004e94 ) + 8004dbe: 611a str r2, [r3, #16] + heth.Init.RxBuffLen = 1536; + 8004dc0: 4b31 ldr r3, [pc, #196] ; (8004e88 ) + 8004dc2: f44f 62c0 mov.w r2, #1536 ; 0x600 + 8004dc6: 615a str r2, [r3, #20] + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + hal_eth_init_status = HAL_ETH_Init(&heth); + 8004dc8: 482f ldr r0, [pc, #188] ; (8004e88 ) + 8004dca: f7fc facb bl 8001364 + 8004dce: 4603 mov r3, r0 + 8004dd0: 73fb strb r3, [r7, #15] + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + 8004dd2: 2238 movs r2, #56 ; 0x38 + 8004dd4: 2100 movs r1, #0 + 8004dd6: 4830 ldr r0, [pc, #192] ; (8004e98 ) + 8004dd8: f00c f854 bl 8010e84 + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + 8004ddc: 4b2e ldr r3, [pc, #184] ; (8004e98 ) + 8004dde: 2221 movs r2, #33 ; 0x21 + 8004de0: 601a str r2, [r3, #0] + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + 8004de2: 4b2d ldr r3, [pc, #180] ; (8004e98 ) + 8004de4: f44f 3240 mov.w r2, #196608 ; 0x30000 + 8004de8: 615a str r2, [r3, #20] + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + 8004dea: 4b2b ldr r3, [pc, #172] ; (8004e98 ) + 8004dec: 2200 movs r2, #0 + 8004dee: 611a str r2, [r3, #16] + + /* End ETH HAL Init */ + + /* Initialize the RX POOL */ + LWIP_MEMPOOL_INIT(RX_POOL); + 8004df0: 482a ldr r0, [pc, #168] ; (8004e9c ) + 8004df2: f001 f875 bl 8005ee0 + +#if LWIP_ARP || LWIP_ETHERNET + + /* set MAC hardware address length */ + netif->hwaddr_len = ETH_HWADDR_LEN; + 8004df6: 687b ldr r3, [r7, #4] + 8004df8: 2206 movs r2, #6 + 8004dfa: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* set MAC hardware address */ + netif->hwaddr[0] = heth.Init.MACAddr[0]; + 8004dfe: 4b22 ldr r3, [pc, #136] ; (8004e88 ) + 8004e00: 685b ldr r3, [r3, #4] + 8004e02: 781a ldrb r2, [r3, #0] + 8004e04: 687b ldr r3, [r7, #4] + 8004e06: f883 2026 strb.w r2, [r3, #38] ; 0x26 + netif->hwaddr[1] = heth.Init.MACAddr[1]; + 8004e0a: 4b1f ldr r3, [pc, #124] ; (8004e88 ) + 8004e0c: 685b ldr r3, [r3, #4] + 8004e0e: 785a ldrb r2, [r3, #1] + 8004e10: 687b ldr r3, [r7, #4] + 8004e12: f883 2027 strb.w r2, [r3, #39] ; 0x27 + netif->hwaddr[2] = heth.Init.MACAddr[2]; + 8004e16: 4b1c ldr r3, [pc, #112] ; (8004e88 ) + 8004e18: 685b ldr r3, [r3, #4] + 8004e1a: 789a ldrb r2, [r3, #2] + 8004e1c: 687b ldr r3, [r7, #4] + 8004e1e: f883 2028 strb.w r2, [r3, #40] ; 0x28 + netif->hwaddr[3] = heth.Init.MACAddr[3]; + 8004e22: 4b19 ldr r3, [pc, #100] ; (8004e88 ) + 8004e24: 685b ldr r3, [r3, #4] + 8004e26: 78da ldrb r2, [r3, #3] + 8004e28: 687b ldr r3, [r7, #4] + 8004e2a: f883 2029 strb.w r2, [r3, #41] ; 0x29 + netif->hwaddr[4] = heth.Init.MACAddr[4]; + 8004e2e: 4b16 ldr r3, [pc, #88] ; (8004e88 ) + 8004e30: 685b ldr r3, [r3, #4] + 8004e32: 791a ldrb r2, [r3, #4] + 8004e34: 687b ldr r3, [r7, #4] + 8004e36: f883 202a strb.w r2, [r3, #42] ; 0x2a + netif->hwaddr[5] = heth.Init.MACAddr[5]; + 8004e3a: 4b13 ldr r3, [pc, #76] ; (8004e88 ) + 8004e3c: 685b ldr r3, [r3, #4] + 8004e3e: 795a ldrb r2, [r3, #5] + 8004e40: 687b ldr r3, [r7, #4] + 8004e42: f883 202b strb.w r2, [r3, #43] ; 0x2b + + /* maximum transfer unit */ + netif->mtu = ETH_MAX_PAYLOAD; + 8004e46: 687b ldr r3, [r7, #4] + 8004e48: f240 52dc movw r2, #1500 ; 0x5dc + 8004e4c: 849a strh r2, [r3, #36] ; 0x24 + + /* Accept broadcast address and ARP traffic */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + #if LWIP_ARP + netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; + 8004e4e: 687b ldr r3, [r7, #4] + 8004e50: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8004e54: f043 030a orr.w r3, r3, #10 + 8004e58: b2da uxtb r2, r3 + 8004e5a: 687b ldr r3, [r7, #4] + 8004e5c: f883 202d strb.w r2, [r3, #45] ; 0x2d + +/* USER CODE BEGIN PHY_PRE_CONFIG */ + +/* USER CODE END PHY_PRE_CONFIG */ + /* Set PHY IO functions */ + LAN8742_RegisterBusIO(&LAN8742, &LAN8742_IOCtx); + 8004e60: 490f ldr r1, [pc, #60] ; (8004ea0 ) + 8004e62: 4810 ldr r0, [pc, #64] ; (8004ea4 ) + 8004e64: f7fb feeb bl 8000c3e + + /* Initialize the LAN8742 ETH PHY */ + LAN8742_Init(&LAN8742); + 8004e68: 480e ldr r0, [pc, #56] ; (8004ea4 ) + 8004e6a: f7fb ff1a bl 8000ca2 + + if (hal_eth_init_status == HAL_OK) + 8004e6e: 7bfb ldrb r3, [r7, #15] + 8004e70: 2b00 cmp r3, #0 + 8004e72: d103 bne.n 8004e7c + { + /* Get link state */ + ethernet_link_check_state(netif); + 8004e74: 6878 ldr r0, [r7, #4] + 8004e76: f000 fa25 bl 80052c4 +#endif /* LWIP_ARP || LWIP_ETHERNET */ + +/* USER CODE BEGIN LOW_LEVEL_INIT */ + +/* USER CODE END LOW_LEVEL_INIT */ +} + 8004e7a: e001 b.n 8004e80 + Error_Handler(); + 8004e7c: f7fb fd2d bl 80008da +} + 8004e80: bf00 nop + 8004e82: 3710 adds r7, #16 + 8004e84: 46bd mov sp, r7 + 8004e86: bd80 pop {r7, pc} + 8004e88: 24004b08 .word 0x24004b08 + 8004e8c: 40028000 .word 0x40028000 + 8004e90: 30000100 .word 0x30000100 + 8004e94: 30000000 .word 0x30000000 + 8004e98: 24004bb8 .word 0x24004bb8 + 8004e9c: 08014c90 .word 0x08014c90 + 8004ea0: 24000010 .word 0x24000010 + 8004ea4: 24004bf0 .word 0x24004bf0 + +08004ea8 : + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ + +static err_t low_level_output(struct netif *netif, struct pbuf *p) +{ + 8004ea8: b580 push {r7, lr} + 8004eaa: b092 sub sp, #72 ; 0x48 + 8004eac: af00 add r7, sp, #0 + 8004eae: 6078 str r0, [r7, #4] + 8004eb0: 6039 str r1, [r7, #0] + uint32_t i = 0U; + 8004eb2: 2300 movs r3, #0 + 8004eb4: 647b str r3, [r7, #68] ; 0x44 + struct pbuf *q = NULL; + 8004eb6: 2300 movs r3, #0 + 8004eb8: 643b str r3, [r7, #64] ; 0x40 + err_t errval = ERR_OK; + 8004eba: 2300 movs r3, #0 + 8004ebc: f887 303f strb.w r3, [r7, #63] ; 0x3f + ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0}; + 8004ec0: f107 030c add.w r3, r7, #12 + 8004ec4: 2230 movs r2, #48 ; 0x30 + 8004ec6: 2100 movs r1, #0 + 8004ec8: 4618 mov r0, r3 + 8004eca: f00b ffdb bl 8010e84 + + memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef)); + 8004ece: f107 030c add.w r3, r7, #12 + 8004ed2: 2230 movs r2, #48 ; 0x30 + 8004ed4: 2100 movs r1, #0 + 8004ed6: 4618 mov r0, r3 + 8004ed8: f00b ffd4 bl 8010e84 + + for(q = p; q != NULL; q = q->next) + 8004edc: 683b ldr r3, [r7, #0] + 8004ede: 643b str r3, [r7, #64] ; 0x40 + 8004ee0: e045 b.n 8004f6e + { + if(i >= ETH_TX_DESC_CNT) + 8004ee2: 6c7b ldr r3, [r7, #68] ; 0x44 + 8004ee4: 2b03 cmp r3, #3 + 8004ee6: d902 bls.n 8004eee + return ERR_IF; + 8004ee8: f06f 030b mvn.w r3, #11 + 8004eec: e055 b.n 8004f9a + + Txbuffer[i].buffer = q->payload; + 8004eee: 6c3b ldr r3, [r7, #64] ; 0x40 + 8004ef0: 6859 ldr r1, [r3, #4] + 8004ef2: 6c7a ldr r2, [r7, #68] ; 0x44 + 8004ef4: 4613 mov r3, r2 + 8004ef6: 005b lsls r3, r3, #1 + 8004ef8: 4413 add r3, r2 + 8004efa: 009b lsls r3, r3, #2 + 8004efc: 3348 adds r3, #72 ; 0x48 + 8004efe: 443b add r3, r7 + 8004f00: 3b3c subs r3, #60 ; 0x3c + 8004f02: 6019 str r1, [r3, #0] + Txbuffer[i].len = q->len; + 8004f04: 6c3b ldr r3, [r7, #64] ; 0x40 + 8004f06: 895b ldrh r3, [r3, #10] + 8004f08: 4619 mov r1, r3 + 8004f0a: 6c7a ldr r2, [r7, #68] ; 0x44 + 8004f0c: 4613 mov r3, r2 + 8004f0e: 005b lsls r3, r3, #1 + 8004f10: 4413 add r3, r2 + 8004f12: 009b lsls r3, r3, #2 + 8004f14: 3348 adds r3, #72 ; 0x48 + 8004f16: 443b add r3, r7 + 8004f18: 3b38 subs r3, #56 ; 0x38 + 8004f1a: 6019 str r1, [r3, #0] + + if(i>0) + 8004f1c: 6c7b ldr r3, [r7, #68] ; 0x44 + 8004f1e: 2b00 cmp r3, #0 + 8004f20: d011 beq.n 8004f46 + { + Txbuffer[i-1].next = &Txbuffer[i]; + 8004f22: 6c7b ldr r3, [r7, #68] ; 0x44 + 8004f24: 1e5a subs r2, r3, #1 + 8004f26: f107 000c add.w r0, r7, #12 + 8004f2a: 6c79 ldr r1, [r7, #68] ; 0x44 + 8004f2c: 460b mov r3, r1 + 8004f2e: 005b lsls r3, r3, #1 + 8004f30: 440b add r3, r1 + 8004f32: 009b lsls r3, r3, #2 + 8004f34: 18c1 adds r1, r0, r3 + 8004f36: 4613 mov r3, r2 + 8004f38: 005b lsls r3, r3, #1 + 8004f3a: 4413 add r3, r2 + 8004f3c: 009b lsls r3, r3, #2 + 8004f3e: 3348 adds r3, #72 ; 0x48 + 8004f40: 443b add r3, r7 + 8004f42: 3b34 subs r3, #52 ; 0x34 + 8004f44: 6019 str r1, [r3, #0] + } + + if(q->next == NULL) + 8004f46: 6c3b ldr r3, [r7, #64] ; 0x40 + 8004f48: 681b ldr r3, [r3, #0] + 8004f4a: 2b00 cmp r3, #0 + 8004f4c: d109 bne.n 8004f62 + { + Txbuffer[i].next = NULL; + 8004f4e: 6c7a ldr r2, [r7, #68] ; 0x44 + 8004f50: 4613 mov r3, r2 + 8004f52: 005b lsls r3, r3, #1 + 8004f54: 4413 add r3, r2 + 8004f56: 009b lsls r3, r3, #2 + 8004f58: 3348 adds r3, #72 ; 0x48 + 8004f5a: 443b add r3, r7 + 8004f5c: 3b34 subs r3, #52 ; 0x34 + 8004f5e: 2200 movs r2, #0 + 8004f60: 601a str r2, [r3, #0] + } + + i++; + 8004f62: 6c7b ldr r3, [r7, #68] ; 0x44 + 8004f64: 3301 adds r3, #1 + 8004f66: 647b str r3, [r7, #68] ; 0x44 + for(q = p; q != NULL; q = q->next) + 8004f68: 6c3b ldr r3, [r7, #64] ; 0x40 + 8004f6a: 681b ldr r3, [r3, #0] + 8004f6c: 643b str r3, [r7, #64] ; 0x40 + 8004f6e: 6c3b ldr r3, [r7, #64] ; 0x40 + 8004f70: 2b00 cmp r3, #0 + 8004f72: d1b6 bne.n 8004ee2 + } + + TxConfig.Length = p->tot_len; + 8004f74: 683b ldr r3, [r7, #0] + 8004f76: 891b ldrh r3, [r3, #8] + 8004f78: 461a mov r2, r3 + 8004f7a: 4b0a ldr r3, [pc, #40] ; (8004fa4 ) + 8004f7c: 605a str r2, [r3, #4] + TxConfig.TxBuffer = Txbuffer; + 8004f7e: 4a09 ldr r2, [pc, #36] ; (8004fa4 ) + 8004f80: f107 030c add.w r3, r7, #12 + 8004f84: 6093 str r3, [r2, #8] + TxConfig.pData = p; + 8004f86: 4a07 ldr r2, [pc, #28] ; (8004fa4 ) + 8004f88: 683b ldr r3, [r7, #0] + 8004f8a: 6353 str r3, [r2, #52] ; 0x34 + + HAL_ETH_Transmit(&heth, &TxConfig, ETH_DMA_TRANSMIT_TIMEOUT); + 8004f8c: 2214 movs r2, #20 + 8004f8e: 4905 ldr r1, [pc, #20] ; (8004fa4 ) + 8004f90: 4805 ldr r0, [pc, #20] ; (8004fa8 ) + 8004f92: f7fc fb7f bl 8001694 + + return errval; + 8004f96: f997 303f ldrsb.w r3, [r7, #63] ; 0x3f +} + 8004f9a: 4618 mov r0, r3 + 8004f9c: 3748 adds r7, #72 ; 0x48 + 8004f9e: 46bd mov sp, r7 + 8004fa0: bd80 pop {r7, pc} + 8004fa2: bf00 nop + 8004fa4: 24004bb8 .word 0x24004bb8 + 8004fa8: 24004b08 .word 0x24004b08 + +08004fac : + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf * low_level_input(struct netif *netif) +{ + 8004fac: b580 push {r7, lr} + 8004fae: b084 sub sp, #16 + 8004fb0: af00 add r7, sp, #0 + 8004fb2: 6078 str r0, [r7, #4] + struct pbuf *p = NULL; + 8004fb4: 2300 movs r3, #0 + 8004fb6: 60fb str r3, [r7, #12] + + if(RxAllocStatus == RX_ALLOC_OK) + 8004fb8: 4b07 ldr r3, [pc, #28] ; (8004fd8 ) + 8004fba: 781b ldrb r3, [r3, #0] + 8004fbc: 2b00 cmp r3, #0 + 8004fbe: d105 bne.n 8004fcc + { + HAL_ETH_ReadData(&heth, (void **)&p); + 8004fc0: f107 030c add.w r3, r7, #12 + 8004fc4: 4619 mov r1, r3 + 8004fc6: 4805 ldr r0, [pc, #20] ; (8004fdc ) + 8004fc8: f7fc fbfb bl 80017c2 + } + + return p; + 8004fcc: 68fb ldr r3, [r7, #12] +} + 8004fce: 4618 mov r0, r3 + 8004fd0: 3710 adds r7, #16 + 8004fd2: 46bd mov sp, r7 + 8004fd4: bd80 pop {r7, pc} + 8004fd6: bf00 nop + 8004fd8: 24004b04 .word 0x24004b04 + 8004fdc: 24004b08 .word 0x24004b08 + +08004fe0 : + * the appropriate input function is called. + * + * @param netif the lwip network interface structure for this ethernetif + */ +void ethernetif_input(struct netif *netif) +{ + 8004fe0: b580 push {r7, lr} + 8004fe2: b084 sub sp, #16 + 8004fe4: af00 add r7, sp, #0 + 8004fe6: 6078 str r0, [r7, #4] + struct pbuf *p = NULL; + 8004fe8: 2300 movs r3, #0 + 8004fea: 60fb str r3, [r7, #12] + + do + { + p = low_level_input( netif ); + 8004fec: 6878 ldr r0, [r7, #4] + 8004fee: f7ff ffdd bl 8004fac + 8004ff2: 60f8 str r0, [r7, #12] + if (p != NULL) + 8004ff4: 68fb ldr r3, [r7, #12] + 8004ff6: 2b00 cmp r3, #0 + 8004ff8: d00a beq.n 8005010 + { + if (netif->input( p, netif) != ERR_OK ) + 8004ffa: 687b ldr r3, [r7, #4] + 8004ffc: 691b ldr r3, [r3, #16] + 8004ffe: 6879 ldr r1, [r7, #4] + 8005000: 68f8 ldr r0, [r7, #12] + 8005002: 4798 blx r3 + 8005004: 4603 mov r3, r0 + 8005006: 2b00 cmp r3, #0 + 8005008: d002 beq.n 8005010 + { + pbuf_free(p); + 800500a: 68f8 ldr r0, [r7, #12] + 800500c: f001 ffe2 bl 8006fd4 + } + } + } while(p!=NULL); + 8005010: 68fb ldr r3, [r7, #12] + 8005012: 2b00 cmp r3, #0 + 8005014: d1ea bne.n 8004fec +} + 8005016: bf00 nop + 8005018: bf00 nop + 800501a: 3710 adds r7, #16 + 800501c: 46bd mov sp, r7 + 800501e: bd80 pop {r7, pc} + +08005020 : + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif_init(struct netif *netif) +{ + 8005020: b580 push {r7, lr} + 8005022: b082 sub sp, #8 + 8005024: af00 add r7, sp, #0 + 8005026: 6078 str r0, [r7, #4] + LWIP_ASSERT("netif != NULL", (netif != NULL)); + 8005028: 687b ldr r3, [r7, #4] + 800502a: 2b00 cmp r3, #0 + 800502c: d106 bne.n 800503c + 800502e: 4b0e ldr r3, [pc, #56] ; (8005068 ) + 8005030: f240 127b movw r2, #379 ; 0x17b + 8005034: 490d ldr r1, [pc, #52] ; (800506c ) + 8005036: 480e ldr r0, [pc, #56] ; (8005070 ) + 8005038: f00b fdc6 bl 8010bc8 + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + // MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); + + netif->name[0] = IFNAME0; + 800503c: 687b ldr r3, [r7, #4] + 800503e: 2273 movs r2, #115 ; 0x73 + 8005040: f883 202e strb.w r2, [r3, #46] ; 0x2e + netif->name[1] = IFNAME1; + 8005044: 687b ldr r3, [r7, #4] + 8005046: 2274 movs r2, #116 ; 0x74 + 8005048: f883 202f strb.w r2, [r3, #47] ; 0x2f + * is available...) */ + +#if LWIP_IPV4 +#if LWIP_ARP || LWIP_ETHERNET +#if LWIP_ARP + netif->output = etharp_output; + 800504c: 687b ldr r3, [r7, #4] + 800504e: 4a09 ldr r2, [pc, #36] ; (8005074 ) + 8005050: 615a str r2, [r3, #20] + +#if LWIP_IPV6 + netif->output_ip6 = ethip6_output; +#endif /* LWIP_IPV6 */ + + netif->linkoutput = low_level_output; + 8005052: 687b ldr r3, [r7, #4] + 8005054: 4a08 ldr r2, [pc, #32] ; (8005078 ) + 8005056: 619a str r2, [r3, #24] + + /* initialize the hardware */ + low_level_init(netif); + 8005058: 6878 ldr r0, [r7, #4] + 800505a: f7ff fe8f bl 8004d7c + + return ERR_OK; + 800505e: 2300 movs r3, #0 +} + 8005060: 4618 mov r0, r3 + 8005062: 3708 adds r7, #8 + 8005064: 46bd mov sp, r7 + 8005066: bd80 pop {r7, pc} + 8005068: 08011b00 .word 0x08011b00 + 800506c: 08011b1c .word 0x08011b1c + 8005070: 08011b2c .word 0x08011b2c + 8005074: 0800e3f5 .word 0x0800e3f5 + 8005078: 08004ea9 .word 0x08004ea9 + +0800507c : + * @brief Custom Rx pbuf free callback + * @param pbuf: pbuf to be freed + * @retval None + */ +void pbuf_free_custom(struct pbuf *p) +{ + 800507c: b580 push {r7, lr} + 800507e: b084 sub sp, #16 + 8005080: af00 add r7, sp, #0 + 8005082: 6078 str r0, [r7, #4] + struct pbuf_custom* custom_pbuf = (struct pbuf_custom*)p; + 8005084: 687b ldr r3, [r7, #4] + 8005086: 60fb str r3, [r7, #12] + LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); + 8005088: 68f9 ldr r1, [r7, #12] + 800508a: 4807 ldr r0, [pc, #28] ; (80050a8 ) + 800508c: f001 f812 bl 80060b4 + + /* If the Rx Buffer Pool was exhausted, signal the ethernetif_input task to + * call HAL_ETH_GetRxDataBuffer to rebuild the Rx descriptors. */ + + if (RxAllocStatus == RX_ALLOC_ERROR) + 8005090: 4b06 ldr r3, [pc, #24] ; (80050ac ) + 8005092: 781b ldrb r3, [r3, #0] + 8005094: 2b01 cmp r3, #1 + 8005096: d102 bne.n 800509e + { + RxAllocStatus = RX_ALLOC_OK; + 8005098: 4b04 ldr r3, [pc, #16] ; (80050ac ) + 800509a: 2200 movs r2, #0 + 800509c: 701a strb r2, [r3, #0] + } +} + 800509e: bf00 nop + 80050a0: 3710 adds r7, #16 + 80050a2: 46bd mov sp, r7 + 80050a4: bd80 pop {r7, pc} + 80050a6: bf00 nop + 80050a8: 08014c90 .word 0x08014c90 + 80050ac: 24004b04 .word 0x24004b04 + +080050b0 : +* when LWIP_TIMERS == 1 and NO_SYS == 1 +* @param None +* @retval Current Time value +*/ +u32_t sys_now(void) +{ + 80050b0: b580 push {r7, lr} + 80050b2: af00 add r7, sp, #0 + return HAL_GetTick(); + 80050b4: f7fb ffaa bl 800100c + 80050b8: 4603 mov r3, r0 +} + 80050ba: 4618 mov r0, r3 + 80050bc: bd80 pop {r7, pc} + ... + +080050c0 : + * @param ethHandle: ETH handle + * @retval None + */ + +void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle) +{ + 80050c0: b580 push {r7, lr} + 80050c2: b08e sub sp, #56 ; 0x38 + 80050c4: af00 add r7, sp, #0 + 80050c6: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80050c8: f107 0324 add.w r3, r7, #36 ; 0x24 + 80050cc: 2200 movs r2, #0 + 80050ce: 601a str r2, [r3, #0] + 80050d0: 605a str r2, [r3, #4] + 80050d2: 609a str r2, [r3, #8] + 80050d4: 60da str r2, [r3, #12] + 80050d6: 611a str r2, [r3, #16] + if(ethHandle->Instance==ETH) + 80050d8: 687b ldr r3, [r7, #4] + 80050da: 681b ldr r3, [r3, #0] + 80050dc: 4a4d ldr r2, [pc, #308] ; (8005214 ) + 80050de: 4293 cmp r3, r2 + 80050e0: f040 8093 bne.w 800520a + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Enable Peripheral clock */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + 80050e4: 4b4c ldr r3, [pc, #304] ; (8005218 ) + 80050e6: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 + 80050ea: 4a4b ldr r2, [pc, #300] ; (8005218 ) + 80050ec: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 80050f0: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 + 80050f4: 4b48 ldr r3, [pc, #288] ; (8005218 ) + 80050f6: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 + 80050fa: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 80050fe: 623b str r3, [r7, #32] + 8005100: 6a3b ldr r3, [r7, #32] + __HAL_RCC_ETH1TX_CLK_ENABLE(); + 8005102: 4b45 ldr r3, [pc, #276] ; (8005218 ) + 8005104: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 + 8005108: 4a43 ldr r2, [pc, #268] ; (8005218 ) + 800510a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 800510e: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 + 8005112: 4b41 ldr r3, [pc, #260] ; (8005218 ) + 8005114: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 + 8005118: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800511c: 61fb str r3, [r7, #28] + 800511e: 69fb ldr r3, [r7, #28] + __HAL_RCC_ETH1RX_CLK_ENABLE(); + 8005120: 4b3d ldr r3, [pc, #244] ; (8005218 ) + 8005122: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 + 8005126: 4a3c ldr r2, [pc, #240] ; (8005218 ) + 8005128: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 800512c: f8c2 30d8 str.w r3, [r2, #216] ; 0xd8 + 8005130: 4b39 ldr r3, [pc, #228] ; (8005218 ) + 8005132: f8d3 30d8 ldr.w r3, [r3, #216] ; 0xd8 + 8005136: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800513a: 61bb str r3, [r7, #24] + 800513c: 69bb ldr r3, [r7, #24] + + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800513e: 4b36 ldr r3, [pc, #216] ; (8005218 ) + 8005140: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8005144: 4a34 ldr r2, [pc, #208] ; (8005218 ) + 8005146: f043 0304 orr.w r3, r3, #4 + 800514a: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 + 800514e: 4b32 ldr r3, [pc, #200] ; (8005218 ) + 8005150: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8005154: f003 0304 and.w r3, r3, #4 + 8005158: 617b str r3, [r7, #20] + 800515a: 697b ldr r3, [r7, #20] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800515c: 4b2e ldr r3, [pc, #184] ; (8005218 ) + 800515e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8005162: 4a2d ldr r2, [pc, #180] ; (8005218 ) + 8005164: f043 0301 orr.w r3, r3, #1 + 8005168: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 + 800516c: 4b2a ldr r3, [pc, #168] ; (8005218 ) + 800516e: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8005172: f003 0301 and.w r3, r3, #1 + 8005176: 613b str r3, [r7, #16] + 8005178: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800517a: 4b27 ldr r3, [pc, #156] ; (8005218 ) + 800517c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8005180: 4a25 ldr r2, [pc, #148] ; (8005218 ) + 8005182: f043 0302 orr.w r3, r3, #2 + 8005186: f8c2 30e0 str.w r3, [r2, #224] ; 0xe0 + 800518a: 4b23 ldr r3, [pc, #140] ; (8005218 ) + 800518c: f8d3 30e0 ldr.w r3, [r3, #224] ; 0xe0 + 8005190: f003 0302 and.w r3, r3, #2 + 8005194: 60fb str r3, [r7, #12] + 8005196: 68fb ldr r3, [r7, #12] + PB13 ------> ETH_TXD1 + PA7 ------> ETH_CRS_DV + PB11 ------> ETH_TX_EN + PB12 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + 8005198: 2332 movs r3, #50 ; 0x32 + 800519a: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800519c: 2302 movs r3, #2 + 800519e: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80051a0: 2300 movs r3, #0 + 80051a2: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80051a4: 2303 movs r3, #3 + 80051a6: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + 80051a8: 230b movs r3, #11 + 80051aa: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80051ac: f107 0324 add.w r3, r7, #36 ; 0x24 + 80051b0: 4619 mov r1, r3 + 80051b2: 481a ldr r0, [pc, #104] ; (800521c ) + 80051b4: f7fd fde2 bl 8002d7c + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + 80051b8: 2386 movs r3, #134 ; 0x86 + 80051ba: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80051bc: 2302 movs r3, #2 + 80051be: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80051c0: 2300 movs r3, #0 + 80051c2: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80051c4: 2303 movs r3, #3 + 80051c6: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + 80051c8: 230b movs r3, #11 + 80051ca: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80051cc: f107 0324 add.w r3, r7, #36 ; 0x24 + 80051d0: 4619 mov r1, r3 + 80051d2: 4813 ldr r0, [pc, #76] ; (8005220 ) + 80051d4: f7fd fdd2 bl 8002d7c + + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_11|GPIO_PIN_12; + 80051d8: f44f 5360 mov.w r3, #14336 ; 0x3800 + 80051dc: 627b str r3, [r7, #36] ; 0x24 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 80051de: 2302 movs r3, #2 + 80051e0: 62bb str r3, [r7, #40] ; 0x28 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80051e2: 2300 movs r3, #0 + 80051e4: 62fb str r3, [r7, #44] ; 0x2c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 80051e6: 2303 movs r3, #3 + 80051e8: 633b str r3, [r7, #48] ; 0x30 + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + 80051ea: 230b movs r3, #11 + 80051ec: 637b str r3, [r7, #52] ; 0x34 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 80051ee: f107 0324 add.w r3, r7, #36 ; 0x24 + 80051f2: 4619 mov r1, r3 + 80051f4: 480b ldr r0, [pc, #44] ; (8005224 ) + 80051f6: f7fd fdc1 bl 8002d7c + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(ETH_IRQn, 0, 0); + 80051fa: 2200 movs r2, #0 + 80051fc: 2100 movs r1, #0 + 80051fe: 203d movs r0, #61 ; 0x3d + 8005200: f7fb ffff bl 8001202 + HAL_NVIC_EnableIRQ(ETH_IRQn); + 8005204: 203d movs r0, #61 ; 0x3d + 8005206: f7fc f816 bl 8001236 + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } +} + 800520a: bf00 nop + 800520c: 3738 adds r7, #56 ; 0x38 + 800520e: 46bd mov sp, r7 + 8005210: bd80 pop {r7, pc} + 8005212: bf00 nop + 8005214: 40028000 .word 0x40028000 + 8005218: 58024400 .word 0x58024400 + 800521c: 58020800 .word 0x58020800 + 8005220: 58020000 .word 0x58020000 + 8005224: 58020400 .word 0x58020400 + +08005228 : + * @brief Initializes the MDIO interface GPIO and clocks. + * @param None + * @retval 0 if OK, -1 if ERROR + */ +int32_t ETH_PHY_IO_Init(void) +{ + 8005228: b580 push {r7, lr} + 800522a: af00 add r7, sp, #0 + /* We assume that MDIO GPIO configuration is already done + in the ETH_MspInit() else it should be done here + */ + + /* Configure the MDIO Clock */ + HAL_ETH_SetMDIOClockRange(&heth); + 800522c: 4802 ldr r0, [pc, #8] ; (8005238 ) + 800522e: f7fc ffd9 bl 80021e4 + + return 0; + 8005232: 2300 movs r3, #0 +} + 8005234: 4618 mov r0, r3 + 8005236: bd80 pop {r7, pc} + 8005238: 24004b08 .word 0x24004b08 + +0800523c : + * @brief De-Initializes the MDIO interface . + * @param None + * @retval 0 if OK, -1 if ERROR + */ +int32_t ETH_PHY_IO_DeInit (void) +{ + 800523c: b480 push {r7} + 800523e: af00 add r7, sp, #0 + return 0; + 8005240: 2300 movs r3, #0 +} + 8005242: 4618 mov r0, r3 + 8005244: 46bd mov sp, r7 + 8005246: f85d 7b04 ldr.w r7, [sp], #4 + 800524a: 4770 bx lr + +0800524c : + * @param RegAddr: PHY register address + * @param pRegVal: pointer to hold the register value + * @retval 0 if OK -1 if Error + */ +int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal) +{ + 800524c: b580 push {r7, lr} + 800524e: b084 sub sp, #16 + 8005250: af00 add r7, sp, #0 + 8005252: 60f8 str r0, [r7, #12] + 8005254: 60b9 str r1, [r7, #8] + 8005256: 607a str r2, [r7, #4] + if(HAL_ETH_ReadPHYRegister(&heth, DevAddr, RegAddr, pRegVal) != HAL_OK) + 8005258: 687b ldr r3, [r7, #4] + 800525a: 68ba ldr r2, [r7, #8] + 800525c: 68f9 ldr r1, [r7, #12] + 800525e: 4807 ldr r0, [pc, #28] ; (800527c ) + 8005260: f7fc fd2a bl 8001cb8 + 8005264: 4603 mov r3, r0 + 8005266: 2b00 cmp r3, #0 + 8005268: d002 beq.n 8005270 + { + return -1; + 800526a: f04f 33ff mov.w r3, #4294967295 + 800526e: e000 b.n 8005272 + } + + return 0; + 8005270: 2300 movs r3, #0 +} + 8005272: 4618 mov r0, r3 + 8005274: 3710 adds r7, #16 + 8005276: 46bd mov sp, r7 + 8005278: bd80 pop {r7, pc} + 800527a: bf00 nop + 800527c: 24004b08 .word 0x24004b08 + +08005280 : + * @param RegAddr: PHY register address + * @param RegVal: Value to be written + * @retval 0 if OK -1 if Error + */ +int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal) +{ + 8005280: b580 push {r7, lr} + 8005282: b084 sub sp, #16 + 8005284: af00 add r7, sp, #0 + 8005286: 60f8 str r0, [r7, #12] + 8005288: 60b9 str r1, [r7, #8] + 800528a: 607a str r2, [r7, #4] + if(HAL_ETH_WritePHYRegister(&heth, DevAddr, RegAddr, RegVal) != HAL_OK) + 800528c: 687b ldr r3, [r7, #4] + 800528e: 68ba ldr r2, [r7, #8] + 8005290: 68f9 ldr r1, [r7, #12] + 8005292: 4807 ldr r0, [pc, #28] ; (80052b0 ) + 8005294: f7fc fd64 bl 8001d60 + 8005298: 4603 mov r3, r0 + 800529a: 2b00 cmp r3, #0 + 800529c: d002 beq.n 80052a4 + { + return -1; + 800529e: f04f 33ff mov.w r3, #4294967295 + 80052a2: e000 b.n 80052a6 + } + + return 0; + 80052a4: 2300 movs r3, #0 +} + 80052a6: 4618 mov r0, r3 + 80052a8: 3710 adds r7, #16 + 80052aa: 46bd mov sp, r7 + 80052ac: bd80 pop {r7, pc} + 80052ae: bf00 nop + 80052b0: 24004b08 .word 0x24004b08 + +080052b4 : +/** + * @brief Get the time in millisecons used for internal PHY driver process. + * @retval Time value + */ +int32_t ETH_PHY_IO_GetTick(void) +{ + 80052b4: b580 push {r7, lr} + 80052b6: af00 add r7, sp, #0 + return HAL_GetTick(); + 80052b8: f7fb fea8 bl 800100c + 80052bc: 4603 mov r3, r0 +} + 80052be: 4618 mov r0, r3 + 80052c0: bd80 pop {r7, pc} + ... + +080052c4 : +/** + * @brief Check the ETH link state then update ETH driver and netif link accordingly. + * @retval None + */ +void ethernet_link_check_state(struct netif *netif) +{ + 80052c4: b580 push {r7, lr} + 80052c6: b0a0 sub sp, #128 ; 0x80 + 80052c8: af00 add r7, sp, #0 + 80052ca: 6078 str r0, [r7, #4] + ETH_MACConfigTypeDef MACConf = {0}; + 80052cc: f107 030c add.w r3, r7, #12 + 80052d0: 2264 movs r2, #100 ; 0x64 + 80052d2: 2100 movs r1, #0 + 80052d4: 4618 mov r0, r3 + 80052d6: f00b fdd5 bl 8010e84 + int32_t PHYLinkState = 0; + 80052da: 2300 movs r3, #0 + 80052dc: 673b str r3, [r7, #112] ; 0x70 + uint32_t linkchanged = 0U, speed = 0U, duplex = 0U; + 80052de: 2300 movs r3, #0 + 80052e0: 67fb str r3, [r7, #124] ; 0x7c + 80052e2: 2300 movs r3, #0 + 80052e4: 67bb str r3, [r7, #120] ; 0x78 + 80052e6: 2300 movs r3, #0 + 80052e8: 677b str r3, [r7, #116] ; 0x74 + + PHYLinkState = LAN8742_GetLinkState(&LAN8742); + 80052ea: 483a ldr r0, [pc, #232] ; (80053d4 ) + 80052ec: f7fb fd81 bl 8000df2 + 80052f0: 6738 str r0, [r7, #112] ; 0x70 + + if(netif_is_link_up(netif) && (PHYLinkState <= LAN8742_STATUS_LINK_DOWN)) + 80052f2: 687b ldr r3, [r7, #4] + 80052f4: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 80052f8: 089b lsrs r3, r3, #2 + 80052fa: f003 0301 and.w r3, r3, #1 + 80052fe: b2db uxtb r3, r3 + 8005300: 2b00 cmp r3, #0 + 8005302: d00c beq.n 800531e + 8005304: 6f3b ldr r3, [r7, #112] ; 0x70 + 8005306: 2b01 cmp r3, #1 + 8005308: dc09 bgt.n 800531e + { + HAL_ETH_Stop(&heth); + 800530a: 4833 ldr r0, [pc, #204] ; (80053d8 ) + 800530c: f7fc f972 bl 80015f4 + netif_set_down(netif); + 8005310: 6878 ldr r0, [r7, #4] + 8005312: f001 fa49 bl 80067a8 + netif_set_link_down(netif); + 8005316: 6878 ldr r0, [r7, #4] + 8005318: f001 faac bl 8006874 + netif_set_up(netif); + netif_set_link_up(netif); + } + } + +} + 800531c: e055 b.n 80053ca + else if(!netif_is_link_up(netif) && (PHYLinkState > LAN8742_STATUS_LINK_DOWN)) + 800531e: 687b ldr r3, [r7, #4] + 8005320: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8005324: f003 0304 and.w r3, r3, #4 + 8005328: 2b00 cmp r3, #0 + 800532a: d14e bne.n 80053ca + 800532c: 6f3b ldr r3, [r7, #112] ; 0x70 + 800532e: 2b01 cmp r3, #1 + 8005330: dd4b ble.n 80053ca + switch (PHYLinkState) + 8005332: 6f3b ldr r3, [r7, #112] ; 0x70 + 8005334: 3b02 subs r3, #2 + 8005336: 2b03 cmp r3, #3 + 8005338: d82a bhi.n 8005390 + 800533a: a201 add r2, pc, #4 ; (adr r2, 8005340 ) + 800533c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8005340: 08005351 .word 0x08005351 + 8005344: 08005363 .word 0x08005363 + 8005348: 08005373 .word 0x08005373 + 800534c: 08005383 .word 0x08005383 + duplex = ETH_FULLDUPLEX_MODE; + 8005350: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8005354: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_100M; + 8005356: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800535a: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800535c: 2301 movs r3, #1 + 800535e: 67fb str r3, [r7, #124] ; 0x7c + break; + 8005360: e017 b.n 8005392 + duplex = ETH_HALFDUPLEX_MODE; + 8005362: 2300 movs r3, #0 + 8005364: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_100M; + 8005366: f44f 4380 mov.w r3, #16384 ; 0x4000 + 800536a: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800536c: 2301 movs r3, #1 + 800536e: 67fb str r3, [r7, #124] ; 0x7c + break; + 8005370: e00f b.n 8005392 + duplex = ETH_FULLDUPLEX_MODE; + 8005372: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8005376: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_10M; + 8005378: 2300 movs r3, #0 + 800537a: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800537c: 2301 movs r3, #1 + 800537e: 67fb str r3, [r7, #124] ; 0x7c + break; + 8005380: e007 b.n 8005392 + duplex = ETH_HALFDUPLEX_MODE; + 8005382: 2300 movs r3, #0 + 8005384: 677b str r3, [r7, #116] ; 0x74 + speed = ETH_SPEED_10M; + 8005386: 2300 movs r3, #0 + 8005388: 67bb str r3, [r7, #120] ; 0x78 + linkchanged = 1; + 800538a: 2301 movs r3, #1 + 800538c: 67fb str r3, [r7, #124] ; 0x7c + break; + 800538e: e000 b.n 8005392 + break; + 8005390: bf00 nop + if(linkchanged) + 8005392: 6ffb ldr r3, [r7, #124] ; 0x7c + 8005394: 2b00 cmp r3, #0 + 8005396: d018 beq.n 80053ca + HAL_ETH_GetMACConfig(&heth, &MACConf); + 8005398: f107 030c add.w r3, r7, #12 + 800539c: 4619 mov r1, r3 + 800539e: 480e ldr r0, [pc, #56] ; (80053d8 ) + 80053a0: f7fc fd32 bl 8001e08 + MACConf.DuplexMode = duplex; + 80053a4: 6f7b ldr r3, [r7, #116] ; 0x74 + 80053a6: 627b str r3, [r7, #36] ; 0x24 + MACConf.Speed = speed; + 80053a8: 6fbb ldr r3, [r7, #120] ; 0x78 + 80053aa: 623b str r3, [r7, #32] + HAL_ETH_SetMACConfig(&heth, &MACConf); + 80053ac: f107 030c add.w r3, r7, #12 + 80053b0: 4619 mov r1, r3 + 80053b2: 4809 ldr r0, [pc, #36] ; (80053d8 ) + 80053b4: f7fc fefc bl 80021b0 + HAL_ETH_Start(&heth); + 80053b8: 4807 ldr r0, [pc, #28] ; (80053d8 ) + 80053ba: f7fc f8b9 bl 8001530 + netif_set_up(netif); + 80053be: 6878 ldr r0, [r7, #4] + 80053c0: f001 f986 bl 80066d0 + netif_set_link_up(netif); + 80053c4: 6878 ldr r0, [r7, #4] + 80053c6: f001 fa21 bl 800680c +} + 80053ca: bf00 nop + 80053cc: 3780 adds r7, #128 ; 0x80 + 80053ce: 46bd mov sp, r7 + 80053d0: bd80 pop {r7, pc} + 80053d2: bf00 nop + 80053d4: 24004bf0 .word 0x24004bf0 + 80053d8: 24004b08 .word 0x24004b08 + +080053dc : + +void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ + 80053dc: b580 push {r7, lr} + 80053de: b086 sub sp, #24 + 80053e0: af02 add r7, sp, #8 + 80053e2: 6078 str r0, [r7, #4] +/* USER CODE BEGIN HAL ETH RxAllocateCallback */ + struct pbuf_custom *p = LWIP_MEMPOOL_ALLOC(RX_POOL); + 80053e4: 4812 ldr r0, [pc, #72] ; (8005430 ) + 80053e6: f000 fdf7 bl 8005fd8 + 80053ea: 60f8 str r0, [r7, #12] + if (p) + 80053ec: 68fb ldr r3, [r7, #12] + 80053ee: 2b00 cmp r3, #0 + 80053f0: d014 beq.n 800541c + { + /* Get the buff from the struct pbuf address. */ + *buff = (uint8_t *)p + offsetof(RxBuff_t, buff); + 80053f2: 68fb ldr r3, [r7, #12] + 80053f4: f103 0220 add.w r2, r3, #32 + 80053f8: 687b ldr r3, [r7, #4] + 80053fa: 601a str r2, [r3, #0] + p->custom_free_function = pbuf_free_custom; + 80053fc: 68fb ldr r3, [r7, #12] + 80053fe: 4a0d ldr r2, [pc, #52] ; (8005434 ) + 8005400: 611a str r2, [r3, #16] + /* Initialize the struct pbuf. + * This must be performed whenever a buffer's allocated because it may be + * changed by lwIP or the app, e.g., pbuf_free decrements ref. */ + pbuf_alloced_custom(PBUF_RAW, 0, PBUF_REF, p, *buff, ETH_RX_BUFFER_SIZE); + 8005402: 687b ldr r3, [r7, #4] + 8005404: 681b ldr r3, [r3, #0] + 8005406: f44f 62c0 mov.w r2, #1536 ; 0x600 + 800540a: 9201 str r2, [sp, #4] + 800540c: 9300 str r3, [sp, #0] + 800540e: 68fb ldr r3, [r7, #12] + 8005410: 2241 movs r2, #65 ; 0x41 + 8005412: 2100 movs r1, #0 + 8005414: 2000 movs r0, #0 + 8005416: f001 fc23 bl 8006c60 + { + RxAllocStatus = RX_ALLOC_ERROR; + *buff = NULL; + } +/* USER CODE END HAL ETH RxAllocateCallback */ +} + 800541a: e005 b.n 8005428 + RxAllocStatus = RX_ALLOC_ERROR; + 800541c: 4b06 ldr r3, [pc, #24] ; (8005438 ) + 800541e: 2201 movs r2, #1 + 8005420: 701a strb r2, [r3, #0] + *buff = NULL; + 8005422: 687b ldr r3, [r7, #4] + 8005424: 2200 movs r2, #0 + 8005426: 601a str r2, [r3, #0] +} + 8005428: bf00 nop + 800542a: 3710 adds r7, #16 + 800542c: 46bd mov sp, r7 + 800542e: bd80 pop {r7, pc} + 8005430: 08014c90 .word 0x08014c90 + 8005434: 0800507d .word 0x0800507d + 8005438: 24004b04 .word 0x24004b04 + +0800543c : + +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + 800543c: b480 push {r7} + 800543e: b08d sub sp, #52 ; 0x34 + 8005440: af00 add r7, sp, #0 + 8005442: 60f8 str r0, [r7, #12] + 8005444: 60b9 str r1, [r7, #8] + 8005446: 607a str r2, [r7, #4] + 8005448: 807b strh r3, [r7, #2] +/* USER CODE BEGIN HAL ETH RxLinkCallback */ + + struct pbuf **ppStart = (struct pbuf **)pStart; + 800544a: 68fb ldr r3, [r7, #12] + 800544c: 62bb str r3, [r7, #40] ; 0x28 + struct pbuf **ppEnd = (struct pbuf **)pEnd; + 800544e: 68bb ldr r3, [r7, #8] + 8005450: 627b str r3, [r7, #36] ; 0x24 + struct pbuf *p = NULL; + 8005452: 2300 movs r3, #0 + 8005454: 62fb str r3, [r7, #44] ; 0x2c + + /* Get the struct pbuf from the buff address. */ + p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff)); + 8005456: 687b ldr r3, [r7, #4] + 8005458: 3b20 subs r3, #32 + 800545a: 62fb str r3, [r7, #44] ; 0x2c + p->next = NULL; + 800545c: 6afb ldr r3, [r7, #44] ; 0x2c + 800545e: 2200 movs r2, #0 + 8005460: 601a str r2, [r3, #0] + p->tot_len = 0; + 8005462: 6afb ldr r3, [r7, #44] ; 0x2c + 8005464: 2200 movs r2, #0 + 8005466: 811a strh r2, [r3, #8] + p->len = Length; + 8005468: 6afb ldr r3, [r7, #44] ; 0x2c + 800546a: 887a ldrh r2, [r7, #2] + 800546c: 815a strh r2, [r3, #10] + + /* Chain the buffer. */ + if (!*ppStart) + 800546e: 6abb ldr r3, [r7, #40] ; 0x28 + 8005470: 681b ldr r3, [r3, #0] + 8005472: 2b00 cmp r3, #0 + 8005474: d103 bne.n 800547e + { + /* The first buffer of the packet. */ + *ppStart = p; + 8005476: 6abb ldr r3, [r7, #40] ; 0x28 + 8005478: 6afa ldr r2, [r7, #44] ; 0x2c + 800547a: 601a str r2, [r3, #0] + 800547c: e003 b.n 8005486 + } + else + { + /* Chain the buffer to the end of the packet. */ + (*ppEnd)->next = p; + 800547e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005480: 681b ldr r3, [r3, #0] + 8005482: 6afa ldr r2, [r7, #44] ; 0x2c + 8005484: 601a str r2, [r3, #0] + } + *ppEnd = p; + 8005486: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005488: 6afa ldr r2, [r7, #44] ; 0x2c + 800548a: 601a str r2, [r3, #0] + + /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len + * set to its own length, plus the length of all the following pbufs in the chain. */ + for (p = *ppStart; p != NULL; p = p->next) + 800548c: 6abb ldr r3, [r7, #40] ; 0x28 + 800548e: 681b ldr r3, [r3, #0] + 8005490: 62fb str r3, [r7, #44] ; 0x2c + 8005492: e009 b.n 80054a8 + { + p->tot_len += Length; + 8005494: 6afb ldr r3, [r7, #44] ; 0x2c + 8005496: 891a ldrh r2, [r3, #8] + 8005498: 887b ldrh r3, [r7, #2] + 800549a: 4413 add r3, r2 + 800549c: b29a uxth r2, r3 + 800549e: 6afb ldr r3, [r7, #44] ; 0x2c + 80054a0: 811a strh r2, [r3, #8] + for (p = *ppStart; p != NULL; p = p->next) + 80054a2: 6afb ldr r3, [r7, #44] ; 0x2c + 80054a4: 681b ldr r3, [r3, #0] + 80054a6: 62fb str r3, [r7, #44] ; 0x2c + 80054a8: 6afb ldr r3, [r7, #44] ; 0x2c + 80054aa: 2b00 cmp r3, #0 + 80054ac: d1f2 bne.n 8005494 + } + + /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */ + SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length); + 80054ae: 887b ldrh r3, [r7, #2] + 80054b0: 687a ldr r2, [r7, #4] + 80054b2: 623a str r2, [r7, #32] + 80054b4: 61fb str r3, [r7, #28] + if ( dsize > 0 ) { + 80054b6: 69fb ldr r3, [r7, #28] + 80054b8: 2b00 cmp r3, #0 + 80054ba: dd1d ble.n 80054f8 + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + 80054bc: 6a3b ldr r3, [r7, #32] + 80054be: f003 021f and.w r2, r3, #31 + 80054c2: 69fb ldr r3, [r7, #28] + 80054c4: 4413 add r3, r2 + 80054c6: 61bb str r3, [r7, #24] + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + 80054c8: 6a3b ldr r3, [r7, #32] + 80054ca: 617b str r3, [r7, #20] + __ASM volatile ("dsb 0xF":::"memory"); + 80054cc: f3bf 8f4f dsb sy +} + 80054d0: bf00 nop + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + 80054d2: 4a0d ldr r2, [pc, #52] ; (8005508 ) + 80054d4: 697b ldr r3, [r7, #20] + 80054d6: f8c2 325c str.w r3, [r2, #604] ; 0x25c + op_addr += __SCB_DCACHE_LINE_SIZE; + 80054da: 697b ldr r3, [r7, #20] + 80054dc: 3320 adds r3, #32 + 80054de: 617b str r3, [r7, #20] + op_size -= __SCB_DCACHE_LINE_SIZE; + 80054e0: 69bb ldr r3, [r7, #24] + 80054e2: 3b20 subs r3, #32 + 80054e4: 61bb str r3, [r7, #24] + } while ( op_size > 0 ); + 80054e6: 69bb ldr r3, [r7, #24] + 80054e8: 2b00 cmp r3, #0 + 80054ea: dcf2 bgt.n 80054d2 + __ASM volatile ("dsb 0xF":::"memory"); + 80054ec: f3bf 8f4f dsb sy +} + 80054f0: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 80054f2: f3bf 8f6f isb sy +} + 80054f6: bf00 nop +} + 80054f8: bf00 nop + +/* USER CODE END HAL ETH RxLinkCallback */ +} + 80054fa: bf00 nop + 80054fc: 3734 adds r7, #52 ; 0x34 + 80054fe: 46bd mov sp, r7 + 8005500: f85d 7b04 ldr.w r7, [sp], #4 + 8005504: 4770 bx lr + 8005506: bf00 nop + 8005508: e000ed00 .word 0xe000ed00 + +0800550c : + * @param err an lwip internal err_t + * @return a string representation for err + */ +const char * +lwip_strerr(err_t err) +{ + 800550c: b480 push {r7} + 800550e: b083 sub sp, #12 + 8005510: af00 add r7, sp, #0 + 8005512: 4603 mov r3, r0 + 8005514: 71fb strb r3, [r7, #7] + if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_strerr))) { + 8005516: f997 3007 ldrsb.w r3, [r7, #7] + 800551a: 2b00 cmp r3, #0 + 800551c: dc04 bgt.n 8005528 + 800551e: f997 3007 ldrsb.w r3, [r7, #7] + 8005522: f113 0f10 cmn.w r3, #16 + 8005526: da01 bge.n 800552c + return "Unknown error."; + 8005528: 4b06 ldr r3, [pc, #24] ; (8005544 ) + 800552a: e005 b.n 8005538 + } + return err_strerr[-err]; + 800552c: f997 3007 ldrsb.w r3, [r7, #7] + 8005530: 425b negs r3, r3 + 8005532: 4a05 ldr r2, [pc, #20] ; (8005548 ) + 8005534: f852 3023 ldr.w r3, [r2, r3, lsl #2] +} + 8005538: 4618 mov r0, r3 + 800553a: 370c adds r7, #12 + 800553c: 46bd mov sp, r7 + 800553e: f85d 7b04 ldr.w r7, [sp], #4 + 8005542: 4770 bx lr + 8005544: 08011c90 .word 0x08011c90 + 8005548: 24000024 .word 0x24000024 + +0800554c : + * @param n u16_t in host byte order + * @return n in network byte order + */ +u16_t +lwip_htons(u16_t n) +{ + 800554c: b480 push {r7} + 800554e: b083 sub sp, #12 + 8005550: af00 add r7, sp, #0 + 8005552: 4603 mov r3, r0 + 8005554: 80fb strh r3, [r7, #6] + return PP_HTONS(n); + 8005556: 88fb ldrh r3, [r7, #6] + 8005558: 021b lsls r3, r3, #8 + 800555a: b21a sxth r2, r3 + 800555c: 88fb ldrh r3, [r7, #6] + 800555e: 0a1b lsrs r3, r3, #8 + 8005560: b29b uxth r3, r3 + 8005562: b21b sxth r3, r3 + 8005564: 4313 orrs r3, r2 + 8005566: b21b sxth r3, r3 + 8005568: b29b uxth r3, r3 +} + 800556a: 4618 mov r0, r3 + 800556c: 370c adds r7, #12 + 800556e: 46bd mov sp, r7 + 8005570: f85d 7b04 ldr.w r7, [sp], #4 + 8005574: 4770 bx lr + +08005576 : + * @param n u32_t in host byte order + * @return n in network byte order + */ +u32_t +lwip_htonl(u32_t n) +{ + 8005576: b480 push {r7} + 8005578: b083 sub sp, #12 + 800557a: af00 add r7, sp, #0 + 800557c: 6078 str r0, [r7, #4] + return PP_HTONL(n); + 800557e: 687b ldr r3, [r7, #4] + 8005580: 061a lsls r2, r3, #24 + 8005582: 687b ldr r3, [r7, #4] + 8005584: 021b lsls r3, r3, #8 + 8005586: f403 037f and.w r3, r3, #16711680 ; 0xff0000 + 800558a: 431a orrs r2, r3 + 800558c: 687b ldr r3, [r7, #4] + 800558e: 0a1b lsrs r3, r3, #8 + 8005590: f403 437f and.w r3, r3, #65280 ; 0xff00 + 8005594: 431a orrs r2, r3 + 8005596: 687b ldr r3, [r7, #4] + 8005598: 0e1b lsrs r3, r3, #24 + 800559a: 4313 orrs r3, r2 +} + 800559c: 4618 mov r0, r3 + 800559e: 370c adds r7, #12 + 80055a0: 46bd mov sp, r7 + 80055a2: f85d 7b04 ldr.w r7, [sp], #4 + 80055a6: 4770 bx lr + +080055a8 : + * @param len length of data to be summed + * @return host order (!) lwip checksum (non-inverted Internet sum) + */ +u16_t +lwip_standard_chksum(const void *dataptr, int len) +{ + 80055a8: b480 push {r7} + 80055aa: b089 sub sp, #36 ; 0x24 + 80055ac: af00 add r7, sp, #0 + 80055ae: 6078 str r0, [r7, #4] + 80055b0: 6039 str r1, [r7, #0] + const u8_t *pb = (const u8_t *)dataptr; + 80055b2: 687b ldr r3, [r7, #4] + 80055b4: 61fb str r3, [r7, #28] + const u16_t *ps; + u16_t t = 0; + 80055b6: 2300 movs r3, #0 + 80055b8: 81fb strh r3, [r7, #14] + u32_t sum = 0; + 80055ba: 2300 movs r3, #0 + 80055bc: 617b str r3, [r7, #20] + int odd = ((mem_ptr_t)pb & 1); + 80055be: 69fb ldr r3, [r7, #28] + 80055c0: f003 0301 and.w r3, r3, #1 + 80055c4: 613b str r3, [r7, #16] + + /* Get aligned to u16_t */ + if (odd && len > 0) { + 80055c6: 693b ldr r3, [r7, #16] + 80055c8: 2b00 cmp r3, #0 + 80055ca: d00d beq.n 80055e8 + 80055cc: 683b ldr r3, [r7, #0] + 80055ce: 2b00 cmp r3, #0 + 80055d0: dd0a ble.n 80055e8 + ((u8_t *)&t)[1] = *pb++; + 80055d2: 69fa ldr r2, [r7, #28] + 80055d4: 1c53 adds r3, r2, #1 + 80055d6: 61fb str r3, [r7, #28] + 80055d8: f107 030e add.w r3, r7, #14 + 80055dc: 3301 adds r3, #1 + 80055de: 7812 ldrb r2, [r2, #0] + 80055e0: 701a strb r2, [r3, #0] + len--; + 80055e2: 683b ldr r3, [r7, #0] + 80055e4: 3b01 subs r3, #1 + 80055e6: 603b str r3, [r7, #0] + } + + /* Add the bulk of the data */ + ps = (const u16_t *)(const void *)pb; + 80055e8: 69fb ldr r3, [r7, #28] + 80055ea: 61bb str r3, [r7, #24] + while (len > 1) { + 80055ec: e00a b.n 8005604 + sum += *ps++; + 80055ee: 69bb ldr r3, [r7, #24] + 80055f0: 1c9a adds r2, r3, #2 + 80055f2: 61ba str r2, [r7, #24] + 80055f4: 881b ldrh r3, [r3, #0] + 80055f6: 461a mov r2, r3 + 80055f8: 697b ldr r3, [r7, #20] + 80055fa: 4413 add r3, r2 + 80055fc: 617b str r3, [r7, #20] + len -= 2; + 80055fe: 683b ldr r3, [r7, #0] + 8005600: 3b02 subs r3, #2 + 8005602: 603b str r3, [r7, #0] + while (len > 1) { + 8005604: 683b ldr r3, [r7, #0] + 8005606: 2b01 cmp r3, #1 + 8005608: dcf1 bgt.n 80055ee + } + + /* Consume left-over byte, if any */ + if (len > 0) { + 800560a: 683b ldr r3, [r7, #0] + 800560c: 2b00 cmp r3, #0 + 800560e: dd04 ble.n 800561a + ((u8_t *)&t)[0] = *(const u8_t *)ps; + 8005610: f107 030e add.w r3, r7, #14 + 8005614: 69ba ldr r2, [r7, #24] + 8005616: 7812 ldrb r2, [r2, #0] + 8005618: 701a strb r2, [r3, #0] + } + + /* Add end bytes */ + sum += t; + 800561a: 89fb ldrh r3, [r7, #14] + 800561c: 461a mov r2, r3 + 800561e: 697b ldr r3, [r7, #20] + 8005620: 4413 add r3, r2 + 8005622: 617b str r3, [r7, #20] + + /* Fold 32-bit sum to 16 bits + calling this twice is probably faster than if statements... */ + sum = FOLD_U32T(sum); + 8005624: 697b ldr r3, [r7, #20] + 8005626: 0c1a lsrs r2, r3, #16 + 8005628: 697b ldr r3, [r7, #20] + 800562a: b29b uxth r3, r3 + 800562c: 4413 add r3, r2 + 800562e: 617b str r3, [r7, #20] + sum = FOLD_U32T(sum); + 8005630: 697b ldr r3, [r7, #20] + 8005632: 0c1a lsrs r2, r3, #16 + 8005634: 697b ldr r3, [r7, #20] + 8005636: b29b uxth r3, r3 + 8005638: 4413 add r3, r2 + 800563a: 617b str r3, [r7, #20] + + /* Swap if alignment was odd */ + if (odd) { + 800563c: 693b ldr r3, [r7, #16] + 800563e: 2b00 cmp r3, #0 + 8005640: d007 beq.n 8005652 + sum = SWAP_BYTES_IN_WORD(sum); + 8005642: 697b ldr r3, [r7, #20] + 8005644: 021b lsls r3, r3, #8 + 8005646: b29a uxth r2, r3 + 8005648: 697b ldr r3, [r7, #20] + 800564a: 0a1b lsrs r3, r3, #8 + 800564c: b2db uxtb r3, r3 + 800564e: 4313 orrs r3, r2 + 8005650: 617b str r3, [r7, #20] + } + + return (u16_t)sum; + 8005652: 697b ldr r3, [r7, #20] + 8005654: b29b uxth r3, r3 +} + 8005656: 4618 mov r0, r3 + 8005658: 3724 adds r7, #36 ; 0x24 + 800565a: 46bd mov sp, r7 + 800565c: f85d 7b04 ldr.w r7, [sp], #4 + 8005660: 4770 bx lr + +08005662 : + * @return checksum (as u16_t) to be saved directly in the protocol header + */ + +u16_t +inet_chksum(const void *dataptr, u16_t len) +{ + 8005662: b580 push {r7, lr} + 8005664: b082 sub sp, #8 + 8005666: af00 add r7, sp, #0 + 8005668: 6078 str r0, [r7, #4] + 800566a: 460b mov r3, r1 + 800566c: 807b strh r3, [r7, #2] + return (u16_t)~(unsigned int)LWIP_CHKSUM(dataptr, len); + 800566e: 887b ldrh r3, [r7, #2] + 8005670: 4619 mov r1, r3 + 8005672: 6878 ldr r0, [r7, #4] + 8005674: f7ff ff98 bl 80055a8 + 8005678: 4603 mov r3, r0 + 800567a: 43db mvns r3, r3 + 800567c: b29b uxth r3, r3 +} + 800567e: 4618 mov r0, r3 + 8005680: 3708 adds r7, #8 + 8005682: 46bd mov sp, r7 + 8005684: bd80 pop {r7, pc} + +08005686 : + * @param p pbuf chain over that the checksum should be calculated + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + 8005686: b580 push {r7, lr} + 8005688: b086 sub sp, #24 + 800568a: af00 add r7, sp, #0 + 800568c: 6078 str r0, [r7, #4] + u32_t acc; + struct pbuf *q; + int swapped = 0; + 800568e: 2300 movs r3, #0 + 8005690: 60fb str r3, [r7, #12] + + acc = 0; + 8005692: 2300 movs r3, #0 + 8005694: 617b str r3, [r7, #20] + for (q = p; q != NULL; q = q->next) { + 8005696: 687b ldr r3, [r7, #4] + 8005698: 613b str r3, [r7, #16] + 800569a: e02b b.n 80056f4 + acc += LWIP_CHKSUM(q->payload, q->len); + 800569c: 693b ldr r3, [r7, #16] + 800569e: 685a ldr r2, [r3, #4] + 80056a0: 693b ldr r3, [r7, #16] + 80056a2: 895b ldrh r3, [r3, #10] + 80056a4: 4619 mov r1, r3 + 80056a6: 4610 mov r0, r2 + 80056a8: f7ff ff7e bl 80055a8 + 80056ac: 4603 mov r3, r0 + 80056ae: 461a mov r2, r3 + 80056b0: 697b ldr r3, [r7, #20] + 80056b2: 4413 add r3, r2 + 80056b4: 617b str r3, [r7, #20] + acc = FOLD_U32T(acc); + 80056b6: 697b ldr r3, [r7, #20] + 80056b8: 0c1a lsrs r2, r3, #16 + 80056ba: 697b ldr r3, [r7, #20] + 80056bc: b29b uxth r3, r3 + 80056be: 4413 add r3, r2 + 80056c0: 617b str r3, [r7, #20] + if (q->len % 2 != 0) { + 80056c2: 693b ldr r3, [r7, #16] + 80056c4: 895b ldrh r3, [r3, #10] + 80056c6: f003 0301 and.w r3, r3, #1 + 80056ca: b29b uxth r3, r3 + 80056cc: 2b00 cmp r3, #0 + 80056ce: d00e beq.n 80056ee + swapped = !swapped; + 80056d0: 68fb ldr r3, [r7, #12] + 80056d2: 2b00 cmp r3, #0 + 80056d4: bf0c ite eq + 80056d6: 2301 moveq r3, #1 + 80056d8: 2300 movne r3, #0 + 80056da: b2db uxtb r3, r3 + 80056dc: 60fb str r3, [r7, #12] + acc = SWAP_BYTES_IN_WORD(acc); + 80056de: 697b ldr r3, [r7, #20] + 80056e0: 021b lsls r3, r3, #8 + 80056e2: b29a uxth r2, r3 + 80056e4: 697b ldr r3, [r7, #20] + 80056e6: 0a1b lsrs r3, r3, #8 + 80056e8: b2db uxtb r3, r3 + 80056ea: 4313 orrs r3, r2 + 80056ec: 617b str r3, [r7, #20] + for (q = p; q != NULL; q = q->next) { + 80056ee: 693b ldr r3, [r7, #16] + 80056f0: 681b ldr r3, [r3, #0] + 80056f2: 613b str r3, [r7, #16] + 80056f4: 693b ldr r3, [r7, #16] + 80056f6: 2b00 cmp r3, #0 + 80056f8: d1d0 bne.n 800569c + } + } + + if (swapped) { + 80056fa: 68fb ldr r3, [r7, #12] + 80056fc: 2b00 cmp r3, #0 + 80056fe: d007 beq.n 8005710 + acc = SWAP_BYTES_IN_WORD(acc); + 8005700: 697b ldr r3, [r7, #20] + 8005702: 021b lsls r3, r3, #8 + 8005704: b29a uxth r2, r3 + 8005706: 697b ldr r3, [r7, #20] + 8005708: 0a1b lsrs r3, r3, #8 + 800570a: b2db uxtb r3, r3 + 800570c: 4313 orrs r3, r2 + 800570e: 617b str r3, [r7, #20] + } + return (u16_t)~(acc & 0xffffUL); + 8005710: 697b ldr r3, [r7, #20] + 8005712: b29b uxth r3, r3 + 8005714: 43db mvns r3, r3 + 8005716: b29b uxth r3, r3 +} + 8005718: 4618 mov r0, r3 + 800571a: 3718 adds r7, #24 + 800571c: 46bd mov sp, r7 + 800571e: bd80 pop {r7, pc} + +08005720 : + * Initialize all modules. + * Use this in NO_SYS mode. Use tcpip_init() otherwise. + */ +void +lwip_init(void) +{ + 8005720: b580 push {r7, lr} + 8005722: b082 sub sp, #8 + 8005724: af00 add r7, sp, #0 +#ifndef LWIP_SKIP_CONST_CHECK + int a = 0; + 8005726: 2300 movs r3, #0 + 8005728: 607b str r3, [r7, #4] + /* Modules initialization */ + stats_init(); +#if !NO_SYS + sys_init(); +#endif /* !NO_SYS */ + mem_init(); + 800572a: f000 f8d9 bl 80058e0 + memp_init(); + 800572e: f000 fc07 bl 8005f40 + pbuf_init(); + netif_init(); + 8005732: f000 fd0d bl 8006150 +#endif /* LWIP_IPV4 */ +#if LWIP_RAW + raw_init(); +#endif /* LWIP_RAW */ +#if LWIP_UDP + udp_init(); + 8005736: f008 f829 bl 800d78c +#endif /* LWIP_UDP */ +#if LWIP_TCP + tcp_init(); + 800573a: f001 fed9 bl 80074f0 +#if PPP_SUPPORT + ppp_init(); +#endif + +#if LWIP_TIMERS + sys_timeouts_init(); + 800573e: f007 ff9b bl 800d678 +#endif /* LWIP_TIMERS */ +} + 8005742: bf00 nop + 8005744: 3708 adds r7, #8 + 8005746: 46bd mov sp, r7 + 8005748: bd80 pop {r7, pc} + ... + +0800574c : +#define mem_overflow_check_element(mem) +#endif /* MEM_OVERFLOW_CHECK */ + +static struct mem * +ptr_to_mem(mem_size_t ptr) +{ + 800574c: b480 push {r7} + 800574e: b083 sub sp, #12 + 8005750: af00 add r7, sp, #0 + 8005752: 4603 mov r3, r0 + 8005754: 80fb strh r3, [r7, #6] + return (struct mem *)(void *)&ram[ptr]; + 8005756: 4b05 ldr r3, [pc, #20] ; (800576c ) + 8005758: 681a ldr r2, [r3, #0] + 800575a: 88fb ldrh r3, [r7, #6] + 800575c: 4413 add r3, r2 +} + 800575e: 4618 mov r0, r3 + 8005760: 370c adds r7, #12 + 8005762: 46bd mov sp, r7 + 8005764: f85d 7b04 ldr.w r7, [sp], #4 + 8005768: 4770 bx lr + 800576a: bf00 nop + 800576c: 24004c28 .word 0x24004c28 + +08005770 : + +static mem_size_t +mem_to_ptr(void *mem) +{ + 8005770: b480 push {r7} + 8005772: b083 sub sp, #12 + 8005774: af00 add r7, sp, #0 + 8005776: 6078 str r0, [r7, #4] + return (mem_size_t)((u8_t *)mem - ram); + 8005778: 4b05 ldr r3, [pc, #20] ; (8005790 ) + 800577a: 681b ldr r3, [r3, #0] + 800577c: 687a ldr r2, [r7, #4] + 800577e: 1ad3 subs r3, r2, r3 + 8005780: b29b uxth r3, r3 +} + 8005782: 4618 mov r0, r3 + 8005784: 370c adds r7, #12 + 8005786: 46bd mov sp, r7 + 8005788: f85d 7b04 ldr.w r7, [sp], #4 + 800578c: 4770 bx lr + 800578e: bf00 nop + 8005790: 24004c28 .word 0x24004c28 + +08005794 : + * This assumes access to the heap is protected by the calling function + * already. + */ +static void +plug_holes(struct mem *mem) +{ + 8005794: b590 push {r4, r7, lr} + 8005796: b085 sub sp, #20 + 8005798: af00 add r7, sp, #0 + 800579a: 6078 str r0, [r7, #4] + struct mem *nmem; + struct mem *pmem; + + LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); + 800579c: 4b47 ldr r3, [pc, #284] ; (80058bc ) + 800579e: 681b ldr r3, [r3, #0] + 80057a0: 687a ldr r2, [r7, #4] + 80057a2: 429a cmp r2, r3 + 80057a4: d206 bcs.n 80057b4 + 80057a6: 4b46 ldr r3, [pc, #280] ; (80058c0 ) + 80057a8: f240 12df movw r2, #479 ; 0x1df + 80057ac: 4945 ldr r1, [pc, #276] ; (80058c4 ) + 80057ae: 4846 ldr r0, [pc, #280] ; (80058c8 ) + 80057b0: f00b fa0a bl 8010bc8 + LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); + 80057b4: 4b45 ldr r3, [pc, #276] ; (80058cc ) + 80057b6: 681b ldr r3, [r3, #0] + 80057b8: 687a ldr r2, [r7, #4] + 80057ba: 429a cmp r2, r3 + 80057bc: d306 bcc.n 80057cc + 80057be: 4b40 ldr r3, [pc, #256] ; (80058c0 ) + 80057c0: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 80057c4: 4942 ldr r1, [pc, #264] ; (80058d0 ) + 80057c6: 4840 ldr r0, [pc, #256] ; (80058c8 ) + 80057c8: f00b f9fe bl 8010bc8 + LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); + 80057cc: 687b ldr r3, [r7, #4] + 80057ce: 791b ldrb r3, [r3, #4] + 80057d0: 2b00 cmp r3, #0 + 80057d2: d006 beq.n 80057e2 + 80057d4: 4b3a ldr r3, [pc, #232] ; (80058c0 ) + 80057d6: f240 12e1 movw r2, #481 ; 0x1e1 + 80057da: 493e ldr r1, [pc, #248] ; (80058d4 ) + 80057dc: 483a ldr r0, [pc, #232] ; (80058c8 ) + 80057de: f00b f9f3 bl 8010bc8 + + /* plug hole forward */ + LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED); + 80057e2: 687b ldr r3, [r7, #4] + 80057e4: 881b ldrh r3, [r3, #0] + 80057e6: f647 52e8 movw r2, #32232 ; 0x7de8 + 80057ea: 4293 cmp r3, r2 + 80057ec: d906 bls.n 80057fc + 80057ee: 4b34 ldr r3, [pc, #208] ; (80058c0 ) + 80057f0: f44f 72f2 mov.w r2, #484 ; 0x1e4 + 80057f4: 4938 ldr r1, [pc, #224] ; (80058d8 ) + 80057f6: 4834 ldr r0, [pc, #208] ; (80058c8 ) + 80057f8: f00b f9e6 bl 8010bc8 + + nmem = ptr_to_mem(mem->next); + 80057fc: 687b ldr r3, [r7, #4] + 80057fe: 881b ldrh r3, [r3, #0] + 8005800: 4618 mov r0, r3 + 8005802: f7ff ffa3 bl 800574c + 8005806: 60f8 str r0, [r7, #12] + if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { + 8005808: 687a ldr r2, [r7, #4] + 800580a: 68fb ldr r3, [r7, #12] + 800580c: 429a cmp r2, r3 + 800580e: d025 beq.n 800585c + 8005810: 68fb ldr r3, [r7, #12] + 8005812: 791b ldrb r3, [r3, #4] + 8005814: 2b00 cmp r3, #0 + 8005816: d121 bne.n 800585c + 8005818: 4b2c ldr r3, [pc, #176] ; (80058cc ) + 800581a: 681b ldr r3, [r3, #0] + 800581c: 68fa ldr r2, [r7, #12] + 800581e: 429a cmp r2, r3 + 8005820: d01c beq.n 800585c + /* if mem->next is unused and not end of ram, combine mem and mem->next */ + if (lfree == nmem) { + 8005822: 4b2e ldr r3, [pc, #184] ; (80058dc ) + 8005824: 681b ldr r3, [r3, #0] + 8005826: 68fa ldr r2, [r7, #12] + 8005828: 429a cmp r2, r3 + 800582a: d102 bne.n 8005832 + lfree = mem; + 800582c: 4a2b ldr r2, [pc, #172] ; (80058dc ) + 800582e: 687b ldr r3, [r7, #4] + 8005830: 6013 str r3, [r2, #0] + } + mem->next = nmem->next; + 8005832: 68fb ldr r3, [r7, #12] + 8005834: 881a ldrh r2, [r3, #0] + 8005836: 687b ldr r3, [r7, #4] + 8005838: 801a strh r2, [r3, #0] + if (nmem->next != MEM_SIZE_ALIGNED) { + 800583a: 68fb ldr r3, [r7, #12] + 800583c: 881b ldrh r3, [r3, #0] + 800583e: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005842: 4293 cmp r3, r2 + 8005844: d00a beq.n 800585c + ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem); + 8005846: 68fb ldr r3, [r7, #12] + 8005848: 881b ldrh r3, [r3, #0] + 800584a: 4618 mov r0, r3 + 800584c: f7ff ff7e bl 800574c + 8005850: 4604 mov r4, r0 + 8005852: 6878 ldr r0, [r7, #4] + 8005854: f7ff ff8c bl 8005770 + 8005858: 4603 mov r3, r0 + 800585a: 8063 strh r3, [r4, #2] + } + } + + /* plug hole backward */ + pmem = ptr_to_mem(mem->prev); + 800585c: 687b ldr r3, [r7, #4] + 800585e: 885b ldrh r3, [r3, #2] + 8005860: 4618 mov r0, r3 + 8005862: f7ff ff73 bl 800574c + 8005866: 60b8 str r0, [r7, #8] + if (pmem != mem && pmem->used == 0) { + 8005868: 68ba ldr r2, [r7, #8] + 800586a: 687b ldr r3, [r7, #4] + 800586c: 429a cmp r2, r3 + 800586e: d020 beq.n 80058b2 + 8005870: 68bb ldr r3, [r7, #8] + 8005872: 791b ldrb r3, [r3, #4] + 8005874: 2b00 cmp r3, #0 + 8005876: d11c bne.n 80058b2 + /* if mem->prev is unused, combine mem and mem->prev */ + if (lfree == mem) { + 8005878: 4b18 ldr r3, [pc, #96] ; (80058dc ) + 800587a: 681b ldr r3, [r3, #0] + 800587c: 687a ldr r2, [r7, #4] + 800587e: 429a cmp r2, r3 + 8005880: d102 bne.n 8005888 + lfree = pmem; + 8005882: 4a16 ldr r2, [pc, #88] ; (80058dc ) + 8005884: 68bb ldr r3, [r7, #8] + 8005886: 6013 str r3, [r2, #0] + } + pmem->next = mem->next; + 8005888: 687b ldr r3, [r7, #4] + 800588a: 881a ldrh r2, [r3, #0] + 800588c: 68bb ldr r3, [r7, #8] + 800588e: 801a strh r2, [r3, #0] + if (mem->next != MEM_SIZE_ALIGNED) { + 8005890: 687b ldr r3, [r7, #4] + 8005892: 881b ldrh r3, [r3, #0] + 8005894: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005898: 4293 cmp r3, r2 + 800589a: d00a beq.n 80058b2 + ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem); + 800589c: 687b ldr r3, [r7, #4] + 800589e: 881b ldrh r3, [r3, #0] + 80058a0: 4618 mov r0, r3 + 80058a2: f7ff ff53 bl 800574c + 80058a6: 4604 mov r4, r0 + 80058a8: 68b8 ldr r0, [r7, #8] + 80058aa: f7ff ff61 bl 8005770 + 80058ae: 4603 mov r3, r0 + 80058b0: 8063 strh r3, [r4, #2] + } + } +} + 80058b2: bf00 nop + 80058b4: 3714 adds r7, #20 + 80058b6: 46bd mov sp, r7 + 80058b8: bd90 pop {r4, r7, pc} + 80058ba: bf00 nop + 80058bc: 24004c28 .word 0x24004c28 + 80058c0: 08011ca0 .word 0x08011ca0 + 80058c4: 08011cd0 .word 0x08011cd0 + 80058c8: 08011ce8 .word 0x08011ce8 + 80058cc: 24004c2c .word 0x24004c2c + 80058d0: 08011d10 .word 0x08011d10 + 80058d4: 08011d2c .word 0x08011d2c + 80058d8: 08011d48 .word 0x08011d48 + 80058dc: 24004c30 .word 0x24004c30 + +080058e0 : +/** + * Zero the heap and initialize start, end and lowest-free + */ +void +mem_init(void) +{ + 80058e0: b580 push {r7, lr} + 80058e2: b082 sub sp, #8 + 80058e4: af00 add r7, sp, #0 + + LWIP_ASSERT("Sanity check alignment", + (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0); + + /* align the heap */ + ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER); + 80058e6: 4b16 ldr r3, [pc, #88] ; (8005940 ) + 80058e8: 4a16 ldr r2, [pc, #88] ; (8005944 ) + 80058ea: 601a str r2, [r3, #0] + /* initialize the start of the heap */ + mem = (struct mem *)(void *)ram; + 80058ec: 4b14 ldr r3, [pc, #80] ; (8005940 ) + 80058ee: 681b ldr r3, [r3, #0] + 80058f0: 607b str r3, [r7, #4] + mem->next = MEM_SIZE_ALIGNED; + 80058f2: 687b ldr r3, [r7, #4] + 80058f4: f647 52e8 movw r2, #32232 ; 0x7de8 + 80058f8: 801a strh r2, [r3, #0] + mem->prev = 0; + 80058fa: 687b ldr r3, [r7, #4] + 80058fc: 2200 movs r2, #0 + 80058fe: 805a strh r2, [r3, #2] + mem->used = 0; + 8005900: 687b ldr r3, [r7, #4] + 8005902: 2200 movs r2, #0 + 8005904: 711a strb r2, [r3, #4] + /* initialize the end of the heap */ + ram_end = ptr_to_mem(MEM_SIZE_ALIGNED); + 8005906: f647 50e8 movw r0, #32232 ; 0x7de8 + 800590a: f7ff ff1f bl 800574c + 800590e: 4603 mov r3, r0 + 8005910: 4a0d ldr r2, [pc, #52] ; (8005948 ) + 8005912: 6013 str r3, [r2, #0] + ram_end->used = 1; + 8005914: 4b0c ldr r3, [pc, #48] ; (8005948 ) + 8005916: 681b ldr r3, [r3, #0] + 8005918: 2201 movs r2, #1 + 800591a: 711a strb r2, [r3, #4] + ram_end->next = MEM_SIZE_ALIGNED; + 800591c: 4b0a ldr r3, [pc, #40] ; (8005948 ) + 800591e: 681b ldr r3, [r3, #0] + 8005920: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005924: 801a strh r2, [r3, #0] + ram_end->prev = MEM_SIZE_ALIGNED; + 8005926: 4b08 ldr r3, [pc, #32] ; (8005948 ) + 8005928: 681b ldr r3, [r3, #0] + 800592a: f647 52e8 movw r2, #32232 ; 0x7de8 + 800592e: 805a strh r2, [r3, #2] + MEM_SANITY(); + + /* initialize the lowest-free pointer to the start of the heap */ + lfree = (struct mem *)(void *)ram; + 8005930: 4b03 ldr r3, [pc, #12] ; (8005940 ) + 8005932: 681b ldr r3, [r3, #0] + 8005934: 4a05 ldr r2, [pc, #20] ; (800594c ) + 8005936: 6013 str r3, [r2, #0] + MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED); + + if (sys_mutex_new(&mem_mutex) != ERR_OK) { + LWIP_ASSERT("failed to create mem_mutex", 0); + } +} + 8005938: bf00 nop + 800593a: 3708 adds r7, #8 + 800593c: 46bd mov sp, r7 + 800593e: bd80 pop {r7, pc} + 8005940: 24004c28 .word 0x24004c28 + 8005944: 30000200 .word 0x30000200 + 8005948: 24004c2c .word 0x24004c2c + 800594c: 24004c30 .word 0x24004c30 + +08005950 : +/* Check if a struct mem is correctly linked. + * If not, double-free is a possible reason. + */ +static int +mem_link_valid(struct mem *mem) +{ + 8005950: b580 push {r7, lr} + 8005952: b086 sub sp, #24 + 8005954: af00 add r7, sp, #0 + 8005956: 6078 str r0, [r7, #4] + struct mem *nmem, *pmem; + mem_size_t rmem_idx; + rmem_idx = mem_to_ptr(mem); + 8005958: 6878 ldr r0, [r7, #4] + 800595a: f7ff ff09 bl 8005770 + 800595e: 4603 mov r3, r0 + 8005960: 82fb strh r3, [r7, #22] + nmem = ptr_to_mem(mem->next); + 8005962: 687b ldr r3, [r7, #4] + 8005964: 881b ldrh r3, [r3, #0] + 8005966: 4618 mov r0, r3 + 8005968: f7ff fef0 bl 800574c + 800596c: 6138 str r0, [r7, #16] + pmem = ptr_to_mem(mem->prev); + 800596e: 687b ldr r3, [r7, #4] + 8005970: 885b ldrh r3, [r3, #2] + 8005972: 4618 mov r0, r3 + 8005974: f7ff feea bl 800574c + 8005978: 60f8 str r0, [r7, #12] + if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) || + 800597a: 687b ldr r3, [r7, #4] + 800597c: 881b ldrh r3, [r3, #0] + 800597e: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005982: 4293 cmp r3, r2 + 8005984: d819 bhi.n 80059ba + 8005986: 687b ldr r3, [r7, #4] + 8005988: 885b ldrh r3, [r3, #2] + 800598a: f647 52e8 movw r2, #32232 ; 0x7de8 + 800598e: 4293 cmp r3, r2 + 8005990: d813 bhi.n 80059ba + ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || + 8005992: 687b ldr r3, [r7, #4] + 8005994: 885b ldrh r3, [r3, #2] + if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) || + 8005996: 8afa ldrh r2, [r7, #22] + 8005998: 429a cmp r2, r3 + 800599a: d004 beq.n 80059a6 + ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || + 800599c: 68fb ldr r3, [r7, #12] + 800599e: 881b ldrh r3, [r3, #0] + 80059a0: 8afa ldrh r2, [r7, #22] + 80059a2: 429a cmp r2, r3 + 80059a4: d109 bne.n 80059ba + ((nmem != ram_end) && (nmem->prev != rmem_idx))) { + 80059a6: 4b08 ldr r3, [pc, #32] ; (80059c8 ) + 80059a8: 681b ldr r3, [r3, #0] + ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || + 80059aa: 693a ldr r2, [r7, #16] + 80059ac: 429a cmp r2, r3 + 80059ae: d006 beq.n 80059be + ((nmem != ram_end) && (nmem->prev != rmem_idx))) { + 80059b0: 693b ldr r3, [r7, #16] + 80059b2: 885b ldrh r3, [r3, #2] + 80059b4: 8afa ldrh r2, [r7, #22] + 80059b6: 429a cmp r2, r3 + 80059b8: d001 beq.n 80059be + return 0; + 80059ba: 2300 movs r3, #0 + 80059bc: e000 b.n 80059c0 + } + return 1; + 80059be: 2301 movs r3, #1 +} + 80059c0: 4618 mov r0, r3 + 80059c2: 3718 adds r7, #24 + 80059c4: 46bd mov sp, r7 + 80059c6: bd80 pop {r7, pc} + 80059c8: 24004c2c .word 0x24004c2c + +080059cc : + * @param rmem is the data portion of a struct mem as returned by a previous + * call to mem_malloc() + */ +void +mem_free(void *rmem) +{ + 80059cc: b580 push {r7, lr} + 80059ce: b084 sub sp, #16 + 80059d0: af00 add r7, sp, #0 + 80059d2: 6078 str r0, [r7, #4] + struct mem *mem; + LWIP_MEM_FREE_DECL_PROTECT(); + + if (rmem == NULL) { + 80059d4: 687b ldr r3, [r7, #4] + 80059d6: 2b00 cmp r3, #0 + 80059d8: d103 bne.n 80059e2 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n")); + 80059da: 482f ldr r0, [pc, #188] ; (8005a98 ) + 80059dc: f00b f962 bl 8010ca4 + return; + 80059e0: e057 b.n 8005a92 + } + if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) { + 80059e2: 687b ldr r3, [r7, #4] + 80059e4: f003 0303 and.w r3, r3, #3 + 80059e8: 2b00 cmp r3, #0 + 80059ea: d00a beq.n 8005a02 + LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment"); + 80059ec: 4b2b ldr r3, [pc, #172] ; (8005a9c ) + 80059ee: f240 2273 movw r2, #627 ; 0x273 + 80059f2: 492b ldr r1, [pc, #172] ; (8005aa0 ) + 80059f4: 482b ldr r0, [pc, #172] ; (8005aa4 ) + 80059f6: f00b f8e7 bl 8010bc8 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n")); + 80059fa: 4829 ldr r0, [pc, #164] ; (8005aa0 ) + 80059fc: f00b f952 bl 8010ca4 + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + 8005a00: e047 b.n 8005a92 + } + + /* Get the corresponding struct mem: */ + /* cast through void* to get rid of alignment warnings */ + mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); + 8005a02: 687b ldr r3, [r7, #4] + 8005a04: 3b08 subs r3, #8 + 8005a06: 60fb str r3, [r7, #12] + + if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) { + 8005a08: 4b27 ldr r3, [pc, #156] ; (8005aa8 ) + 8005a0a: 681b ldr r3, [r3, #0] + 8005a0c: 68fa ldr r2, [r7, #12] + 8005a0e: 429a cmp r2, r3 + 8005a10: d306 bcc.n 8005a20 + 8005a12: 687b ldr r3, [r7, #4] + 8005a14: f103 020c add.w r2, r3, #12 + 8005a18: 4b24 ldr r3, [pc, #144] ; (8005aac ) + 8005a1a: 681b ldr r3, [r3, #0] + 8005a1c: 429a cmp r2, r3 + 8005a1e: d90a bls.n 8005a36 + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory"); + 8005a20: 4b1e ldr r3, [pc, #120] ; (8005a9c ) + 8005a22: f240 227f movw r2, #639 ; 0x27f + 8005a26: 4922 ldr r1, [pc, #136] ; (8005ab0 ) + 8005a28: 481e ldr r0, [pc, #120] ; (8005aa4 ) + 8005a2a: f00b f8cd bl 8010bc8 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n")); + 8005a2e: 4820 ldr r0, [pc, #128] ; (8005ab0 ) + 8005a30: f00b f938 bl 8010ca4 + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + 8005a34: e02d b.n 8005a92 + mem_overflow_check_element(mem); +#endif + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + /* mem has to be in a used state */ + if (!mem->used) { + 8005a36: 68fb ldr r3, [r7, #12] + 8005a38: 791b ldrb r3, [r3, #4] + 8005a3a: 2b00 cmp r3, #0 + 8005a3c: d10a bne.n 8005a54 + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free"); + 8005a3e: 4b17 ldr r3, [pc, #92] ; (8005a9c ) + 8005a40: f44f 7223 mov.w r2, #652 ; 0x28c + 8005a44: 491b ldr r1, [pc, #108] ; (8005ab4 ) + 8005a46: 4817 ldr r0, [pc, #92] ; (8005aa4 ) + 8005a48: f00b f8be bl 8010bc8 + LWIP_MEM_FREE_UNPROTECT(); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n")); + 8005a4c: 481a ldr r0, [pc, #104] ; (8005ab8 ) + 8005a4e: f00b f929 bl 8010ca4 + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + 8005a52: e01e b.n 8005a92 + } + + if (!mem_link_valid(mem)) { + 8005a54: 68f8 ldr r0, [r7, #12] + 8005a56: f7ff ff7b bl 8005950 + 8005a5a: 4603 mov r3, r0 + 8005a5c: 2b00 cmp r3, #0 + 8005a5e: d10a bne.n 8005a76 + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free"); + 8005a60: 4b0e ldr r3, [pc, #56] ; (8005a9c ) + 8005a62: f240 2295 movw r2, #661 ; 0x295 + 8005a66: 4915 ldr r1, [pc, #84] ; (8005abc ) + 8005a68: 480e ldr r0, [pc, #56] ; (8005aa4 ) + 8005a6a: f00b f8ad bl 8010bc8 + LWIP_MEM_FREE_UNPROTECT(); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n")); + 8005a6e: 4814 ldr r0, [pc, #80] ; (8005ac0 ) + 8005a70: f00b f918 bl 8010ca4 + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + 8005a74: e00d b.n 8005a92 + } + + /* mem is now unused. */ + mem->used = 0; + 8005a76: 68fb ldr r3, [r7, #12] + 8005a78: 2200 movs r2, #0 + 8005a7a: 711a strb r2, [r3, #4] + + if (mem < lfree) { + 8005a7c: 4b11 ldr r3, [pc, #68] ; (8005ac4 ) + 8005a7e: 681b ldr r3, [r3, #0] + 8005a80: 68fa ldr r2, [r7, #12] + 8005a82: 429a cmp r2, r3 + 8005a84: d202 bcs.n 8005a8c + /* the newly freed struct is now the lowest */ + lfree = mem; + 8005a86: 4a0f ldr r2, [pc, #60] ; (8005ac4 ) + 8005a88: 68fb ldr r3, [r7, #12] + 8005a8a: 6013 str r3, [r2, #0] + } + + MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram))); + + /* finally, see if prev or next are free also */ + plug_holes(mem); + 8005a8c: 68f8 ldr r0, [r7, #12] + 8005a8e: f7ff fe81 bl 8005794 + MEM_SANITY(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); +} + 8005a92: 3710 adds r7, #16 + 8005a94: 46bd mov sp, r7 + 8005a96: bd80 pop {r7, pc} + 8005a98: 08011d74 .word 0x08011d74 + 8005a9c: 08011ca0 .word 0x08011ca0 + 8005aa0: 08011d94 .word 0x08011d94 + 8005aa4: 08011ce8 .word 0x08011ce8 + 8005aa8: 24004c28 .word 0x24004c28 + 8005aac: 24004c2c .word 0x24004c2c + 8005ab0: 08011db8 .word 0x08011db8 + 8005ab4: 08011dd4 .word 0x08011dd4 + 8005ab8: 08011dfc .word 0x08011dfc + 8005abc: 08011e24 .word 0x08011e24 + 8005ac0: 08011e58 .word 0x08011e58 + 8005ac4: 24004c30 .word 0x24004c30 + +08005ac8 : + * or NULL if newsize is > old size, in which case rmem is NOT touched + * or freed! + */ +void * +mem_trim(void *rmem, mem_size_t new_size) +{ + 8005ac8: b580 push {r7, lr} + 8005aca: b088 sub sp, #32 + 8005acc: af00 add r7, sp, #0 + 8005ace: 6078 str r0, [r7, #4] + 8005ad0: 460b mov r3, r1 + 8005ad2: 807b strh r3, [r7, #2] + /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */ + LWIP_MEM_FREE_DECL_PROTECT(); + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size); + 8005ad4: 887b ldrh r3, [r7, #2] + 8005ad6: 3303 adds r3, #3 + 8005ad8: b29b uxth r3, r3 + 8005ada: f023 0303 bic.w r3, r3, #3 + 8005ade: 83fb strh r3, [r7, #30] + if (newsize < MIN_SIZE_ALIGNED) { + 8005ae0: 8bfb ldrh r3, [r7, #30] + 8005ae2: 2b0b cmp r3, #11 + 8005ae4: d801 bhi.n 8005aea + /* every data block must be at least MIN_SIZE_ALIGNED long */ + newsize = MIN_SIZE_ALIGNED; + 8005ae6: 230c movs r3, #12 + 8005ae8: 83fb strh r3, [r7, #30] + } +#if MEM_OVERFLOW_CHECK + newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; +#endif + if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) { + 8005aea: 8bfb ldrh r3, [r7, #30] + 8005aec: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005af0: 4293 cmp r3, r2 + 8005af2: d803 bhi.n 8005afc + 8005af4: 8bfa ldrh r2, [r7, #30] + 8005af6: 887b ldrh r3, [r7, #2] + 8005af8: 429a cmp r2, r3 + 8005afa: d201 bcs.n 8005b00 + return NULL; + 8005afc: 2300 movs r3, #0 + 8005afe: e0d3 b.n 8005ca8 + } + + LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram && + 8005b00: 4b6b ldr r3, [pc, #428] ; (8005cb0 ) + 8005b02: 681b ldr r3, [r3, #0] + 8005b04: 687a ldr r2, [r7, #4] + 8005b06: 429a cmp r2, r3 + 8005b08: d304 bcc.n 8005b14 + 8005b0a: 4b6a ldr r3, [pc, #424] ; (8005cb4 ) + 8005b0c: 681b ldr r3, [r3, #0] + 8005b0e: 687a ldr r2, [r7, #4] + 8005b10: 429a cmp r2, r3 + 8005b12: d306 bcc.n 8005b22 + 8005b14: 4b68 ldr r3, [pc, #416] ; (8005cb8 ) + 8005b16: f240 22d1 movw r2, #721 ; 0x2d1 + 8005b1a: 4968 ldr r1, [pc, #416] ; (8005cbc ) + 8005b1c: 4868 ldr r0, [pc, #416] ; (8005cc0 ) + 8005b1e: f00b f853 bl 8010bc8 + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + 8005b22: 4b63 ldr r3, [pc, #396] ; (8005cb0 ) + 8005b24: 681b ldr r3, [r3, #0] + 8005b26: 687a ldr r2, [r7, #4] + 8005b28: 429a cmp r2, r3 + 8005b2a: d304 bcc.n 8005b36 + 8005b2c: 4b61 ldr r3, [pc, #388] ; (8005cb4 ) + 8005b2e: 681b ldr r3, [r3, #0] + 8005b30: 687a ldr r2, [r7, #4] + 8005b32: 429a cmp r2, r3 + 8005b34: d304 bcc.n 8005b40 + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n")); + 8005b36: 4863 ldr r0, [pc, #396] ; (8005cc4 ) + 8005b38: f00b f8b4 bl 8010ca4 + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return rmem; + 8005b3c: 687b ldr r3, [r7, #4] + 8005b3e: e0b3 b.n 8005ca8 + } + /* Get the corresponding struct mem ... */ + /* cast through void* to get rid of alignment warnings */ + mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); + 8005b40: 687b ldr r3, [r7, #4] + 8005b42: 3b08 subs r3, #8 + 8005b44: 61bb str r3, [r7, #24] +#if MEM_OVERFLOW_CHECK + mem_overflow_check_element(mem); +#endif + /* ... and its offset pointer */ + ptr = mem_to_ptr(mem); + 8005b46: 69b8 ldr r0, [r7, #24] + 8005b48: f7ff fe12 bl 8005770 + 8005b4c: 4603 mov r3, r0 + 8005b4e: 82fb strh r3, [r7, #22] + + size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD)); + 8005b50: 69bb ldr r3, [r7, #24] + 8005b52: 881a ldrh r2, [r3, #0] + 8005b54: 8afb ldrh r3, [r7, #22] + 8005b56: 1ad3 subs r3, r2, r3 + 8005b58: b29b uxth r3, r3 + 8005b5a: 3b08 subs r3, #8 + 8005b5c: 82bb strh r3, [r7, #20] + LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size); + 8005b5e: 8bfa ldrh r2, [r7, #30] + 8005b60: 8abb ldrh r3, [r7, #20] + 8005b62: 429a cmp r2, r3 + 8005b64: d906 bls.n 8005b74 + 8005b66: 4b54 ldr r3, [pc, #336] ; (8005cb8 ) + 8005b68: f44f 7239 mov.w r2, #740 ; 0x2e4 + 8005b6c: 4956 ldr r1, [pc, #344] ; (8005cc8 ) + 8005b6e: 4854 ldr r0, [pc, #336] ; (8005cc0 ) + 8005b70: f00b f82a bl 8010bc8 + if (newsize > size) { + 8005b74: 8bfa ldrh r2, [r7, #30] + 8005b76: 8abb ldrh r3, [r7, #20] + 8005b78: 429a cmp r2, r3 + 8005b7a: d901 bls.n 8005b80 + /* not supported */ + return NULL; + 8005b7c: 2300 movs r3, #0 + 8005b7e: e093 b.n 8005ca8 + } + if (newsize == size) { + 8005b80: 8bfa ldrh r2, [r7, #30] + 8005b82: 8abb ldrh r3, [r7, #20] + 8005b84: 429a cmp r2, r3 + 8005b86: d101 bne.n 8005b8c + /* No change in size, simply return */ + return rmem; + 8005b88: 687b ldr r3, [r7, #4] + 8005b8a: e08d b.n 8005ca8 + } + + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + + mem2 = ptr_to_mem(mem->next); + 8005b8c: 69bb ldr r3, [r7, #24] + 8005b8e: 881b ldrh r3, [r3, #0] + 8005b90: 4618 mov r0, r3 + 8005b92: f7ff fddb bl 800574c + 8005b96: 6138 str r0, [r7, #16] + if (mem2->used == 0) { + 8005b98: 693b ldr r3, [r7, #16] + 8005b9a: 791b ldrb r3, [r3, #4] + 8005b9c: 2b00 cmp r3, #0 + 8005b9e: d141 bne.n 8005c24 + /* The next struct is unused, we can simply move it at little */ + mem_size_t next; + LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); + 8005ba0: 69bb ldr r3, [r7, #24] + 8005ba2: 881b ldrh r3, [r3, #0] + 8005ba4: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005ba8: 4293 cmp r3, r2 + 8005baa: d106 bne.n 8005bba + 8005bac: 4b42 ldr r3, [pc, #264] ; (8005cb8 ) + 8005bae: f240 22f5 movw r2, #757 ; 0x2f5 + 8005bb2: 4946 ldr r1, [pc, #280] ; (8005ccc ) + 8005bb4: 4842 ldr r0, [pc, #264] ; (8005cc0 ) + 8005bb6: f00b f807 bl 8010bc8 + /* remember the old next pointer */ + next = mem2->next; + 8005bba: 693b ldr r3, [r7, #16] + 8005bbc: 881b ldrh r3, [r3, #0] + 8005bbe: 81bb strh r3, [r7, #12] + /* create new struct mem which is moved directly after the shrinked mem */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); + 8005bc0: 8afa ldrh r2, [r7, #22] + 8005bc2: 8bfb ldrh r3, [r7, #30] + 8005bc4: 4413 add r3, r2 + 8005bc6: b29b uxth r3, r3 + 8005bc8: 3308 adds r3, #8 + 8005bca: 81fb strh r3, [r7, #14] + if (lfree == mem2) { + 8005bcc: 4b40 ldr r3, [pc, #256] ; (8005cd0 ) + 8005bce: 681b ldr r3, [r3, #0] + 8005bd0: 693a ldr r2, [r7, #16] + 8005bd2: 429a cmp r2, r3 + 8005bd4: d106 bne.n 8005be4 + lfree = ptr_to_mem(ptr2); + 8005bd6: 89fb ldrh r3, [r7, #14] + 8005bd8: 4618 mov r0, r3 + 8005bda: f7ff fdb7 bl 800574c + 8005bde: 4603 mov r3, r0 + 8005be0: 4a3b ldr r2, [pc, #236] ; (8005cd0 ) + 8005be2: 6013 str r3, [r2, #0] + } + mem2 = ptr_to_mem(ptr2); + 8005be4: 89fb ldrh r3, [r7, #14] + 8005be6: 4618 mov r0, r3 + 8005be8: f7ff fdb0 bl 800574c + 8005bec: 6138 str r0, [r7, #16] + mem2->used = 0; + 8005bee: 693b ldr r3, [r7, #16] + 8005bf0: 2200 movs r2, #0 + 8005bf2: 711a strb r2, [r3, #4] + /* restore the next pointer */ + mem2->next = next; + 8005bf4: 693b ldr r3, [r7, #16] + 8005bf6: 89ba ldrh r2, [r7, #12] + 8005bf8: 801a strh r2, [r3, #0] + /* link it back to mem */ + mem2->prev = ptr; + 8005bfa: 693b ldr r3, [r7, #16] + 8005bfc: 8afa ldrh r2, [r7, #22] + 8005bfe: 805a strh r2, [r3, #2] + /* link mem to it */ + mem->next = ptr2; + 8005c00: 69bb ldr r3, [r7, #24] + 8005c02: 89fa ldrh r2, [r7, #14] + 8005c04: 801a strh r2, [r3, #0] + /* last thing to restore linked list: as we have moved mem2, + * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not + * the end of the heap */ + if (mem2->next != MEM_SIZE_ALIGNED) { + 8005c06: 693b ldr r3, [r7, #16] + 8005c08: 881b ldrh r3, [r3, #0] + 8005c0a: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005c0e: 4293 cmp r3, r2 + 8005c10: d049 beq.n 8005ca6 + ptr_to_mem(mem2->next)->prev = ptr2; + 8005c12: 693b ldr r3, [r7, #16] + 8005c14: 881b ldrh r3, [r3, #0] + 8005c16: 4618 mov r0, r3 + 8005c18: f7ff fd98 bl 800574c + 8005c1c: 4602 mov r2, r0 + 8005c1e: 89fb ldrh r3, [r7, #14] + 8005c20: 8053 strh r3, [r2, #2] + 8005c22: e040 b.n 8005ca6 + } + MEM_STATS_DEC_USED(used, (size - newsize)); + /* no need to plug holes, we've already done that */ + } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) { + 8005c24: 8bfb ldrh r3, [r7, #30] + 8005c26: f103 0214 add.w r2, r3, #20 + 8005c2a: 8abb ldrh r3, [r7, #20] + 8005c2c: 429a cmp r2, r3 + 8005c2e: d83a bhi.n 8005ca6 + * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem + * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED'). + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); + 8005c30: 8afa ldrh r2, [r7, #22] + 8005c32: 8bfb ldrh r3, [r7, #30] + 8005c34: 4413 add r3, r2 + 8005c36: b29b uxth r3, r3 + 8005c38: 3308 adds r3, #8 + 8005c3a: 81fb strh r3, [r7, #14] + LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); + 8005c3c: 69bb ldr r3, [r7, #24] + 8005c3e: 881b ldrh r3, [r3, #0] + 8005c40: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005c44: 4293 cmp r3, r2 + 8005c46: d106 bne.n 8005c56 + 8005c48: 4b1b ldr r3, [pc, #108] ; (8005cb8 ) + 8005c4a: f240 3216 movw r2, #790 ; 0x316 + 8005c4e: 491f ldr r1, [pc, #124] ; (8005ccc ) + 8005c50: 481b ldr r0, [pc, #108] ; (8005cc0 ) + 8005c52: f00a ffb9 bl 8010bc8 + mem2 = ptr_to_mem(ptr2); + 8005c56: 89fb ldrh r3, [r7, #14] + 8005c58: 4618 mov r0, r3 + 8005c5a: f7ff fd77 bl 800574c + 8005c5e: 6138 str r0, [r7, #16] + if (mem2 < lfree) { + 8005c60: 4b1b ldr r3, [pc, #108] ; (8005cd0 ) + 8005c62: 681b ldr r3, [r3, #0] + 8005c64: 693a ldr r2, [r7, #16] + 8005c66: 429a cmp r2, r3 + 8005c68: d202 bcs.n 8005c70 + lfree = mem2; + 8005c6a: 4a19 ldr r2, [pc, #100] ; (8005cd0 ) + 8005c6c: 693b ldr r3, [r7, #16] + 8005c6e: 6013 str r3, [r2, #0] + } + mem2->used = 0; + 8005c70: 693b ldr r3, [r7, #16] + 8005c72: 2200 movs r2, #0 + 8005c74: 711a strb r2, [r3, #4] + mem2->next = mem->next; + 8005c76: 69bb ldr r3, [r7, #24] + 8005c78: 881a ldrh r2, [r3, #0] + 8005c7a: 693b ldr r3, [r7, #16] + 8005c7c: 801a strh r2, [r3, #0] + mem2->prev = ptr; + 8005c7e: 693b ldr r3, [r7, #16] + 8005c80: 8afa ldrh r2, [r7, #22] + 8005c82: 805a strh r2, [r3, #2] + mem->next = ptr2; + 8005c84: 69bb ldr r3, [r7, #24] + 8005c86: 89fa ldrh r2, [r7, #14] + 8005c88: 801a strh r2, [r3, #0] + if (mem2->next != MEM_SIZE_ALIGNED) { + 8005c8a: 693b ldr r3, [r7, #16] + 8005c8c: 881b ldrh r3, [r3, #0] + 8005c8e: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005c92: 4293 cmp r3, r2 + 8005c94: d007 beq.n 8005ca6 + ptr_to_mem(mem2->next)->prev = ptr2; + 8005c96: 693b ldr r3, [r7, #16] + 8005c98: 881b ldrh r3, [r3, #0] + 8005c9a: 4618 mov r0, r3 + 8005c9c: f7ff fd56 bl 800574c + 8005ca0: 4602 mov r2, r0 + 8005ca2: 89fb ldrh r3, [r7, #14] + 8005ca4: 8053 strh r3, [r2, #2] + MEM_SANITY(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); + return rmem; + 8005ca6: 687b ldr r3, [r7, #4] +} + 8005ca8: 4618 mov r0, r3 + 8005caa: 3720 adds r7, #32 + 8005cac: 46bd mov sp, r7 + 8005cae: bd80 pop {r7, pc} + 8005cb0: 24004c28 .word 0x24004c28 + 8005cb4: 24004c2c .word 0x24004c2c + 8005cb8: 08011ca0 .word 0x08011ca0 + 8005cbc: 08011e8c .word 0x08011e8c + 8005cc0: 08011ce8 .word 0x08011ce8 + 8005cc4: 08011ea4 .word 0x08011ea4 + 8005cc8: 08011ec0 .word 0x08011ec0 + 8005ccc: 08011ee0 .word 0x08011ee0 + 8005cd0: 24004c30 .word 0x24004c30 + +08005cd4 : + * + * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT). + */ +void * +mem_malloc(mem_size_t size_in) +{ + 8005cd4: b580 push {r7, lr} + 8005cd6: b088 sub sp, #32 + 8005cd8: af00 add r7, sp, #0 + 8005cda: 4603 mov r3, r0 + 8005cdc: 80fb strh r3, [r7, #6] +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + u8_t local_mem_free_count = 0; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_ALLOC_DECL_PROTECT(); + + if (size_in == 0) { + 8005cde: 88fb ldrh r3, [r7, #6] + 8005ce0: 2b00 cmp r3, #0 + 8005ce2: d101 bne.n 8005ce8 + return NULL; + 8005ce4: 2300 movs r3, #0 + 8005ce6: e0e3 b.n 8005eb0 + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in); + 8005ce8: 88fb ldrh r3, [r7, #6] + 8005cea: 3303 adds r3, #3 + 8005cec: b29b uxth r3, r3 + 8005cee: f023 0303 bic.w r3, r3, #3 + 8005cf2: 83bb strh r3, [r7, #28] + if (size < MIN_SIZE_ALIGNED) { + 8005cf4: 8bbb ldrh r3, [r7, #28] + 8005cf6: 2b0b cmp r3, #11 + 8005cf8: d801 bhi.n 8005cfe + /* every data block must be at least MIN_SIZE_ALIGNED long */ + size = MIN_SIZE_ALIGNED; + 8005cfa: 230c movs r3, #12 + 8005cfc: 83bb strh r3, [r7, #28] + } +#if MEM_OVERFLOW_CHECK + size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; +#endif + if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) { + 8005cfe: 8bbb ldrh r3, [r7, #28] + 8005d00: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005d04: 4293 cmp r3, r2 + 8005d06: d803 bhi.n 8005d10 + 8005d08: 8bba ldrh r2, [r7, #28] + 8005d0a: 88fb ldrh r3, [r7, #6] + 8005d0c: 429a cmp r2, r3 + 8005d0e: d201 bcs.n 8005d14 + return NULL; + 8005d10: 2300 movs r3, #0 + 8005d12: e0cd b.n 8005eb0 +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + /* Scan through the heap searching for a free block that is big enough, + * beginning with the lowest free block. + */ + for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size; + 8005d14: 4b68 ldr r3, [pc, #416] ; (8005eb8 ) + 8005d16: 681b ldr r3, [r3, #0] + 8005d18: 4618 mov r0, r3 + 8005d1a: f7ff fd29 bl 8005770 + 8005d1e: 4603 mov r3, r0 + 8005d20: 83fb strh r3, [r7, #30] + 8005d22: e0b6 b.n 8005e92 + ptr = ptr_to_mem(ptr)->next) { + mem = ptr_to_mem(ptr); + 8005d24: 8bfb ldrh r3, [r7, #30] + 8005d26: 4618 mov r0, r3 + 8005d28: f7ff fd10 bl 800574c + 8005d2c: 6178 str r0, [r7, #20] + local_mem_free_count = 1; + break; + } +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + if ((!mem->used) && + 8005d2e: 697b ldr r3, [r7, #20] + 8005d30: 791b ldrb r3, [r3, #4] + 8005d32: 2b00 cmp r3, #0 + 8005d34: f040 80a6 bne.w 8005e84 + (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) { + 8005d38: 697b ldr r3, [r7, #20] + 8005d3a: 881b ldrh r3, [r3, #0] + 8005d3c: 461a mov r2, r3 + 8005d3e: 8bfb ldrh r3, [r7, #30] + 8005d40: 1ad3 subs r3, r2, r3 + 8005d42: f1a3 0208 sub.w r2, r3, #8 + 8005d46: 8bbb ldrh r3, [r7, #28] + if ((!mem->used) && + 8005d48: 429a cmp r2, r3 + 8005d4a: f0c0 809b bcc.w 8005e84 + /* mem is not used and at least perfect fit is possible: + * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ + + if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) { + 8005d4e: 697b ldr r3, [r7, #20] + 8005d50: 881b ldrh r3, [r3, #0] + 8005d52: 461a mov r2, r3 + 8005d54: 8bfb ldrh r3, [r7, #30] + 8005d56: 1ad3 subs r3, r2, r3 + 8005d58: f1a3 0208 sub.w r2, r3, #8 + 8005d5c: 8bbb ldrh r3, [r7, #28] + 8005d5e: 3314 adds r3, #20 + 8005d60: 429a cmp r2, r3 + 8005d62: d335 bcc.n 8005dd0 + * struct mem would fit in but no data between mem2 and mem2->next + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory + */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size); + 8005d64: 8bfa ldrh r2, [r7, #30] + 8005d66: 8bbb ldrh r3, [r7, #28] + 8005d68: 4413 add r3, r2 + 8005d6a: b29b uxth r3, r3 + 8005d6c: 3308 adds r3, #8 + 8005d6e: 827b strh r3, [r7, #18] + LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED); + 8005d70: 8a7b ldrh r3, [r7, #18] + 8005d72: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005d76: 4293 cmp r3, r2 + 8005d78: d106 bne.n 8005d88 + 8005d7a: 4b50 ldr r3, [pc, #320] ; (8005ebc ) + 8005d7c: f240 3287 movw r2, #903 ; 0x387 + 8005d80: 494f ldr r1, [pc, #316] ; (8005ec0 ) + 8005d82: 4850 ldr r0, [pc, #320] ; (8005ec4 ) + 8005d84: f00a ff20 bl 8010bc8 + /* create mem2 struct */ + mem2 = ptr_to_mem(ptr2); + 8005d88: 8a7b ldrh r3, [r7, #18] + 8005d8a: 4618 mov r0, r3 + 8005d8c: f7ff fcde bl 800574c + 8005d90: 60f8 str r0, [r7, #12] + mem2->used = 0; + 8005d92: 68fb ldr r3, [r7, #12] + 8005d94: 2200 movs r2, #0 + 8005d96: 711a strb r2, [r3, #4] + mem2->next = mem->next; + 8005d98: 697b ldr r3, [r7, #20] + 8005d9a: 881a ldrh r2, [r3, #0] + 8005d9c: 68fb ldr r3, [r7, #12] + 8005d9e: 801a strh r2, [r3, #0] + mem2->prev = ptr; + 8005da0: 68fb ldr r3, [r7, #12] + 8005da2: 8bfa ldrh r2, [r7, #30] + 8005da4: 805a strh r2, [r3, #2] + /* and insert it between mem and mem->next */ + mem->next = ptr2; + 8005da6: 697b ldr r3, [r7, #20] + 8005da8: 8a7a ldrh r2, [r7, #18] + 8005daa: 801a strh r2, [r3, #0] + mem->used = 1; + 8005dac: 697b ldr r3, [r7, #20] + 8005dae: 2201 movs r2, #1 + 8005db0: 711a strb r2, [r3, #4] + + if (mem2->next != MEM_SIZE_ALIGNED) { + 8005db2: 68fb ldr r3, [r7, #12] + 8005db4: 881b ldrh r3, [r3, #0] + 8005db6: f647 52e8 movw r2, #32232 ; 0x7de8 + 8005dba: 4293 cmp r3, r2 + 8005dbc: d00b beq.n 8005dd6 + ptr_to_mem(mem2->next)->prev = ptr2; + 8005dbe: 68fb ldr r3, [r7, #12] + 8005dc0: 881b ldrh r3, [r3, #0] + 8005dc2: 4618 mov r0, r3 + 8005dc4: f7ff fcc2 bl 800574c + 8005dc8: 4602 mov r2, r0 + 8005dca: 8a7b ldrh r3, [r7, #18] + 8005dcc: 8053 strh r3, [r2, #2] + 8005dce: e002 b.n 8005dd6 + * take care of this). + * -> near fit or exact fit: do not split, no mem2 creation + * also can't move mem->next directly behind mem, since mem->next + * will always be used at this point! + */ + mem->used = 1; + 8005dd0: 697b ldr r3, [r7, #20] + 8005dd2: 2201 movs r2, #1 + 8005dd4: 711a strb r2, [r3, #4] + MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem)); + } +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +mem_malloc_adjust_lfree: +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + if (mem == lfree) { + 8005dd6: 4b38 ldr r3, [pc, #224] ; (8005eb8 ) + 8005dd8: 681b ldr r3, [r3, #0] + 8005dda: 697a ldr r2, [r7, #20] + 8005ddc: 429a cmp r2, r3 + 8005dde: d127 bne.n 8005e30 + struct mem *cur = lfree; + 8005de0: 4b35 ldr r3, [pc, #212] ; (8005eb8 ) + 8005de2: 681b ldr r3, [r3, #0] + 8005de4: 61bb str r3, [r7, #24] + /* Find next free block after mem and update lowest free pointer */ + while (cur->used && cur != ram_end) { + 8005de6: e005 b.n 8005df4 + /* If mem_free or mem_trim have run, we have to restart since they + could have altered our current struct mem or lfree. */ + goto mem_malloc_adjust_lfree; + } +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + cur = ptr_to_mem(cur->next); + 8005de8: 69bb ldr r3, [r7, #24] + 8005dea: 881b ldrh r3, [r3, #0] + 8005dec: 4618 mov r0, r3 + 8005dee: f7ff fcad bl 800574c + 8005df2: 61b8 str r0, [r7, #24] + while (cur->used && cur != ram_end) { + 8005df4: 69bb ldr r3, [r7, #24] + 8005df6: 791b ldrb r3, [r3, #4] + 8005df8: 2b00 cmp r3, #0 + 8005dfa: d004 beq.n 8005e06 + 8005dfc: 4b32 ldr r3, [pc, #200] ; (8005ec8 ) + 8005dfe: 681b ldr r3, [r3, #0] + 8005e00: 69ba ldr r2, [r7, #24] + 8005e02: 429a cmp r2, r3 + 8005e04: d1f0 bne.n 8005de8 + } + lfree = cur; + 8005e06: 4a2c ldr r2, [pc, #176] ; (8005eb8 ) + 8005e08: 69bb ldr r3, [r7, #24] + 8005e0a: 6013 str r3, [r2, #0] + LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used))); + 8005e0c: 4b2a ldr r3, [pc, #168] ; (8005eb8 ) + 8005e0e: 681a ldr r2, [r3, #0] + 8005e10: 4b2d ldr r3, [pc, #180] ; (8005ec8 ) + 8005e12: 681b ldr r3, [r3, #0] + 8005e14: 429a cmp r2, r3 + 8005e16: d00b beq.n 8005e30 + 8005e18: 4b27 ldr r3, [pc, #156] ; (8005eb8 ) + 8005e1a: 681b ldr r3, [r3, #0] + 8005e1c: 791b ldrb r3, [r3, #4] + 8005e1e: 2b00 cmp r3, #0 + 8005e20: d006 beq.n 8005e30 + 8005e22: 4b26 ldr r3, [pc, #152] ; (8005ebc ) + 8005e24: f240 32b5 movw r2, #949 ; 0x3b5 + 8005e28: 4928 ldr r1, [pc, #160] ; (8005ecc ) + 8005e2a: 4826 ldr r0, [pc, #152] ; (8005ec4 ) + 8005e2c: f00a fecc bl 8010bc8 + } + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + 8005e30: 8bba ldrh r2, [r7, #28] + 8005e32: 697b ldr r3, [r7, #20] + 8005e34: 4413 add r3, r2 + 8005e36: 3308 adds r3, #8 + 8005e38: 4a23 ldr r2, [pc, #140] ; (8005ec8 ) + 8005e3a: 6812 ldr r2, [r2, #0] + 8005e3c: 4293 cmp r3, r2 + 8005e3e: d906 bls.n 8005e4e + 8005e40: 4b1e ldr r3, [pc, #120] ; (8005ebc ) + 8005e42: f240 32b9 movw r2, #953 ; 0x3b9 + 8005e46: 4922 ldr r1, [pc, #136] ; (8005ed0 ) + 8005e48: 481e ldr r0, [pc, #120] ; (8005ec4 ) + 8005e4a: f00a febd bl 8010bc8 + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + 8005e4e: 697b ldr r3, [r7, #20] + 8005e50: f003 0303 and.w r3, r3, #3 + 8005e54: 2b00 cmp r3, #0 + 8005e56: d006 beq.n 8005e66 + 8005e58: 4b18 ldr r3, [pc, #96] ; (8005ebc ) + 8005e5a: f240 32bb movw r2, #955 ; 0x3bb + 8005e5e: 491d ldr r1, [pc, #116] ; (8005ed4 ) + 8005e60: 4818 ldr r0, [pc, #96] ; (8005ec4 ) + 8005e62: f00a feb1 bl 8010bc8 + ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + LWIP_ASSERT("mem_malloc: sanity check alignment", + 8005e66: 697b ldr r3, [r7, #20] + 8005e68: f003 0303 and.w r3, r3, #3 + 8005e6c: 2b00 cmp r3, #0 + 8005e6e: d006 beq.n 8005e7e + 8005e70: 4b12 ldr r3, [pc, #72] ; (8005ebc ) + 8005e72: f240 32bd movw r2, #957 ; 0x3bd + 8005e76: 4918 ldr r1, [pc, #96] ; (8005ed8 ) + 8005e78: 4812 ldr r0, [pc, #72] ; (8005ec4 ) + 8005e7a: f00a fea5 bl 8010bc8 + +#if MEM_OVERFLOW_CHECK + mem_overflow_init_element(mem, size_in); +#endif + MEM_SANITY(); + return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET; + 8005e7e: 697b ldr r3, [r7, #20] + 8005e80: 3308 adds r3, #8 + 8005e82: e015 b.n 8005eb0 + ptr = ptr_to_mem(ptr)->next) { + 8005e84: 8bfb ldrh r3, [r7, #30] + 8005e86: 4618 mov r0, r3 + 8005e88: f7ff fc60 bl 800574c + 8005e8c: 4603 mov r3, r0 + 8005e8e: 881b ldrh r3, [r3, #0] + 8005e90: 83fb strh r3, [r7, #30] + for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size; + 8005e92: 8bfa ldrh r2, [r7, #30] + 8005e94: 8bb9 ldrh r1, [r7, #28] + 8005e96: f647 53e8 movw r3, #32232 ; 0x7de8 + 8005e9a: 1a5b subs r3, r3, r1 + 8005e9c: 429a cmp r2, r3 + 8005e9e: f4ff af41 bcc.w 8005d24 + } while (local_mem_free_count != 0); +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + MEM_STATS_INC(err); + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); + 8005ea2: f9b7 301c ldrsh.w r3, [r7, #28] + 8005ea6: 4619 mov r1, r3 + 8005ea8: 480c ldr r0, [pc, #48] ; (8005edc ) + 8005eaa: f00a fe8d bl 8010bc8 + return NULL; + 8005eae: 2300 movs r3, #0 +} + 8005eb0: 4618 mov r0, r3 + 8005eb2: 3720 adds r7, #32 + 8005eb4: 46bd mov sp, r7 + 8005eb6: bd80 pop {r7, pc} + 8005eb8: 24004c30 .word 0x24004c30 + 8005ebc: 08011ca0 .word 0x08011ca0 + 8005ec0: 08011ee0 .word 0x08011ee0 + 8005ec4: 08011ce8 .word 0x08011ce8 + 8005ec8: 24004c2c .word 0x24004c2c + 8005ecc: 08011ef4 .word 0x08011ef4 + 8005ed0: 08011f10 .word 0x08011f10 + 8005ed4: 08011f40 .word 0x08011f40 + 8005ed8: 08011f70 .word 0x08011f70 + 8005edc: 08011f94 .word 0x08011f94 + +08005ee0 : + * + * @param desc pool to initialize + */ +void +memp_init_pool(const struct memp_desc *desc) +{ + 8005ee0: b480 push {r7} + 8005ee2: b085 sub sp, #20 + 8005ee4: af00 add r7, sp, #0 + 8005ee6: 6078 str r0, [r7, #4] + LWIP_UNUSED_ARG(desc); +#else + int i; + struct memp *memp; + + *desc->tab = NULL; + 8005ee8: 687b ldr r3, [r7, #4] + 8005eea: 68db ldr r3, [r3, #12] + 8005eec: 2200 movs r2, #0 + 8005eee: 601a str r2, [r3, #0] + memp = (struct memp *)LWIP_MEM_ALIGN(desc->base); + 8005ef0: 687b ldr r3, [r7, #4] + 8005ef2: 689b ldr r3, [r3, #8] + 8005ef4: 3303 adds r3, #3 + 8005ef6: f023 0303 bic.w r3, r3, #3 + 8005efa: 60bb str r3, [r7, #8] + + MEM_SANITY_REGION_AFTER_ALIGNED +#endif + )); +#endif + /* create a linked list of memp elements */ + for (i = 0; i < desc->num; ++i) { + 8005efc: 2300 movs r3, #0 + 8005efe: 60fb str r3, [r7, #12] + 8005f00: e011 b.n 8005f26 + memp->next = *desc->tab; + 8005f02: 687b ldr r3, [r7, #4] + 8005f04: 68db ldr r3, [r3, #12] + 8005f06: 681a ldr r2, [r3, #0] + 8005f08: 68bb ldr r3, [r7, #8] + 8005f0a: 601a str r2, [r3, #0] + *desc->tab = memp; + 8005f0c: 687b ldr r3, [r7, #4] + 8005f0e: 68db ldr r3, [r3, #12] + 8005f10: 68ba ldr r2, [r7, #8] + 8005f12: 601a str r2, [r3, #0] +#if MEMP_OVERFLOW_CHECK + memp_overflow_init_element(memp, desc); +#endif /* MEMP_OVERFLOW_CHECK */ + /* cast through void* to get rid of alignment warnings */ + memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size + 8005f14: 687b ldr r3, [r7, #4] + 8005f16: 889b ldrh r3, [r3, #4] + 8005f18: 461a mov r2, r3 + 8005f1a: 68bb ldr r3, [r7, #8] + 8005f1c: 4413 add r3, r2 + 8005f1e: 60bb str r3, [r7, #8] + for (i = 0; i < desc->num; ++i) { + 8005f20: 68fb ldr r3, [r7, #12] + 8005f22: 3301 adds r3, #1 + 8005f24: 60fb str r3, [r7, #12] + 8005f26: 687b ldr r3, [r7, #4] + 8005f28: 88db ldrh r3, [r3, #6] + 8005f2a: 461a mov r2, r3 + 8005f2c: 68fb ldr r3, [r7, #12] + 8005f2e: 4293 cmp r3, r2 + 8005f30: dbe7 blt.n 8005f02 +#endif /* !MEMP_MEM_MALLOC */ + +#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) + desc->stats->name = desc->desc; +#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */ +} + 8005f32: bf00 nop + 8005f34: bf00 nop + 8005f36: 3714 adds r7, #20 + 8005f38: 46bd mov sp, r7 + 8005f3a: f85d 7b04 ldr.w r7, [sp], #4 + 8005f3e: 4770 bx lr + +08005f40 : + * + * Carves out memp_memory into linked lists for each pool-type. + */ +void +memp_init(void) +{ + 8005f40: b580 push {r7, lr} + 8005f42: b082 sub sp, #8 + 8005f44: af00 add r7, sp, #0 + u16_t i; + + /* for every pool: */ + for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { + 8005f46: 2300 movs r3, #0 + 8005f48: 80fb strh r3, [r7, #6] + 8005f4a: e009 b.n 8005f60 + memp_init_pool(memp_pools[i]); + 8005f4c: 88fb ldrh r3, [r7, #6] + 8005f4e: 4a08 ldr r2, [pc, #32] ; (8005f70 ) + 8005f50: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8005f54: 4618 mov r0, r3 + 8005f56: f7ff ffc3 bl 8005ee0 + for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { + 8005f5a: 88fb ldrh r3, [r7, #6] + 8005f5c: 3301 adds r3, #1 + 8005f5e: 80fb strh r3, [r7, #6] + 8005f60: 88fb ldrh r3, [r7, #6] + 8005f62: 2b08 cmp r3, #8 + 8005f64: d9f2 bls.n 8005f4c + +#if MEMP_OVERFLOW_CHECK >= 2 + /* check everything a first time to see if it worked */ + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ +} + 8005f66: bf00 nop + 8005f68: bf00 nop + 8005f6a: 3708 adds r7, #8 + 8005f6c: 46bd mov sp, r7 + 8005f6e: bd80 pop {r7, pc} + 8005f70: 08014d30 .word 0x08014d30 + +08005f74 : +#if !MEMP_OVERFLOW_CHECK +do_memp_malloc_pool(const struct memp_desc *desc) +#else +do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) +#endif +{ + 8005f74: b580 push {r7, lr} + 8005f76: b084 sub sp, #16 + 8005f78: af00 add r7, sp, #0 + 8005f7a: 6078 str r0, [r7, #4] + memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size)); + SYS_ARCH_PROTECT(old_level); +#else /* MEMP_MEM_MALLOC */ + SYS_ARCH_PROTECT(old_level); + + memp = *desc->tab; + 8005f7c: 687b ldr r3, [r7, #4] + 8005f7e: 68db ldr r3, [r3, #12] + 8005f80: 681b ldr r3, [r3, #0] + 8005f82: 60fb str r3, [r7, #12] +#endif /* MEMP_MEM_MALLOC */ + + if (memp != NULL) { + 8005f84: 68fb ldr r3, [r7, #12] + 8005f86: 2b00 cmp r3, #0 + 8005f88: d012 beq.n 8005fb0 +#if !MEMP_MEM_MALLOC +#if MEMP_OVERFLOW_CHECK == 1 + memp_overflow_check_element(memp, desc); +#endif /* MEMP_OVERFLOW_CHECK */ + + *desc->tab = memp->next; + 8005f8a: 687b ldr r3, [r7, #4] + 8005f8c: 68db ldr r3, [r3, #12] + 8005f8e: 68fa ldr r2, [r7, #12] + 8005f90: 6812 ldr r2, [r2, #0] + 8005f92: 601a str r2, [r3, #0] + memp->line = line; +#if MEMP_MEM_MALLOC + memp_overflow_init_element(memp, desc); +#endif /* MEMP_MEM_MALLOC */ +#endif /* MEMP_OVERFLOW_CHECK */ + LWIP_ASSERT("memp_malloc: memp properly aligned", + 8005f94: 68fb ldr r3, [r7, #12] + 8005f96: f003 0303 and.w r3, r3, #3 + 8005f9a: 2b00 cmp r3, #0 + 8005f9c: d006 beq.n 8005fac + 8005f9e: 4b0a ldr r3, [pc, #40] ; (8005fc8 ) + 8005fa0: f44f 728c mov.w r2, #280 ; 0x118 + 8005fa4: 4909 ldr r1, [pc, #36] ; (8005fcc ) + 8005fa6: 480a ldr r0, [pc, #40] ; (8005fd0 ) + 8005fa8: f00a fe0e bl 8010bc8 + desc->stats->max = desc->stats->used; + } +#endif + SYS_ARCH_UNPROTECT(old_level); + /* cast through u8_t* to get rid of alignment warnings */ + return ((u8_t *)memp + MEMP_SIZE); + 8005fac: 68fb ldr r3, [r7, #12] + 8005fae: e006 b.n 8005fbe + } else { +#if MEMP_STATS + desc->stats->err++; +#endif + SYS_ARCH_UNPROTECT(old_level); + LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc)); + 8005fb0: 687b ldr r3, [r7, #4] + 8005fb2: 681b ldr r3, [r3, #0] + 8005fb4: 4619 mov r1, r3 + 8005fb6: 4807 ldr r0, [pc, #28] ; (8005fd4 ) + 8005fb8: f00a fe06 bl 8010bc8 + } + + return NULL; + 8005fbc: 2300 movs r3, #0 +} + 8005fbe: 4618 mov r0, r3 + 8005fc0: 3710 adds r7, #16 + 8005fc2: 46bd mov sp, r7 + 8005fc4: bd80 pop {r7, pc} + 8005fc6: bf00 nop + 8005fc8: 08012054 .word 0x08012054 + 8005fcc: 08012084 .word 0x08012084 + 8005fd0: 080120a8 .word 0x080120a8 + 8005fd4: 080120d0 .word 0x080120d0 + +08005fd8 : +#if !MEMP_OVERFLOW_CHECK +memp_malloc_pool(const struct memp_desc *desc) +#else +memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) +#endif +{ + 8005fd8: b580 push {r7, lr} + 8005fda: b082 sub sp, #8 + 8005fdc: af00 add r7, sp, #0 + 8005fde: 6078 str r0, [r7, #4] + LWIP_ASSERT("invalid pool desc", desc != NULL); + 8005fe0: 687b ldr r3, [r7, #4] + 8005fe2: 2b00 cmp r3, #0 + 8005fe4: d106 bne.n 8005ff4 + 8005fe6: 4b0a ldr r3, [pc, #40] ; (8006010 ) + 8005fe8: f44f 729e mov.w r2, #316 ; 0x13c + 8005fec: 4909 ldr r1, [pc, #36] ; (8006014 ) + 8005fee: 480a ldr r0, [pc, #40] ; (8006018 ) + 8005ff0: f00a fdea bl 8010bc8 + if (desc == NULL) { + 8005ff4: 687b ldr r3, [r7, #4] + 8005ff6: 2b00 cmp r3, #0 + 8005ff8: d101 bne.n 8005ffe + return NULL; + 8005ffa: 2300 movs r3, #0 + 8005ffc: e003 b.n 8006006 + } + +#if !MEMP_OVERFLOW_CHECK + return do_memp_malloc_pool(desc); + 8005ffe: 6878 ldr r0, [r7, #4] + 8006000: f7ff ffb8 bl 8005f74 + 8006004: 4603 mov r3, r0 +#else + return do_memp_malloc_pool_fn(desc, file, line); +#endif +} + 8006006: 4618 mov r0, r3 + 8006008: 3708 adds r7, #8 + 800600a: 46bd mov sp, r7 + 800600c: bd80 pop {r7, pc} + 800600e: bf00 nop + 8006010: 08012054 .word 0x08012054 + 8006014: 080120f8 .word 0x080120f8 + 8006018: 080120a8 .word 0x080120a8 + +0800601c : +#if !MEMP_OVERFLOW_CHECK +memp_malloc(memp_t type) +#else +memp_malloc_fn(memp_t type, const char *file, const int line) +#endif +{ + 800601c: b580 push {r7, lr} + 800601e: b084 sub sp, #16 + 8006020: af00 add r7, sp, #0 + 8006022: 4603 mov r3, r0 + 8006024: 71fb strb r3, [r7, #7] + void *memp; + LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;); + 8006026: 79fb ldrb r3, [r7, #7] + 8006028: 2b08 cmp r3, #8 + 800602a: d908 bls.n 800603e + 800602c: 4b0a ldr r3, [pc, #40] ; (8006058 ) + 800602e: f240 1257 movw r2, #343 ; 0x157 + 8006032: 490a ldr r1, [pc, #40] ; (800605c ) + 8006034: 480a ldr r0, [pc, #40] ; (8006060 ) + 8006036: f00a fdc7 bl 8010bc8 + 800603a: 2300 movs r3, #0 + 800603c: e008 b.n 8006050 +#if MEMP_OVERFLOW_CHECK >= 2 + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ + +#if !MEMP_OVERFLOW_CHECK + memp = do_memp_malloc_pool(memp_pools[type]); + 800603e: 79fb ldrb r3, [r7, #7] + 8006040: 4a08 ldr r2, [pc, #32] ; (8006064 ) + 8006042: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8006046: 4618 mov r0, r3 + 8006048: f7ff ff94 bl 8005f74 + 800604c: 60f8 str r0, [r7, #12] +#else + memp = do_memp_malloc_pool_fn(memp_pools[type], file, line); +#endif + + return memp; + 800604e: 68fb ldr r3, [r7, #12] +} + 8006050: 4618 mov r0, r3 + 8006052: 3710 adds r7, #16 + 8006054: 46bd mov sp, r7 + 8006056: bd80 pop {r7, pc} + 8006058: 08012054 .word 0x08012054 + 800605c: 0801210c .word 0x0801210c + 8006060: 080120a8 .word 0x080120a8 + 8006064: 08014d30 .word 0x08014d30 + +08006068 : + +static void +do_memp_free_pool(const struct memp_desc *desc, void *mem) +{ + 8006068: b580 push {r7, lr} + 800606a: b084 sub sp, #16 + 800606c: af00 add r7, sp, #0 + 800606e: 6078 str r0, [r7, #4] + 8006070: 6039 str r1, [r7, #0] + struct memp *memp; + SYS_ARCH_DECL_PROTECT(old_level); + + LWIP_ASSERT("memp_free: mem properly aligned", + 8006072: 683b ldr r3, [r7, #0] + 8006074: f003 0303 and.w r3, r3, #3 + 8006078: 2b00 cmp r3, #0 + 800607a: d006 beq.n 800608a + 800607c: 4b0a ldr r3, [pc, #40] ; (80060a8 ) + 800607e: f44f 72b6 mov.w r2, #364 ; 0x16c + 8006082: 490a ldr r1, [pc, #40] ; (80060ac ) + 8006084: 480a ldr r0, [pc, #40] ; (80060b0 ) + 8006086: f00a fd9f bl 8010bc8 + ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0); + + /* cast through void* to get rid of alignment warnings */ + memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE); + 800608a: 683b ldr r3, [r7, #0] + 800608c: 60fb str r3, [r7, #12] +#if MEMP_MEM_MALLOC + LWIP_UNUSED_ARG(desc); + SYS_ARCH_UNPROTECT(old_level); + mem_free(memp); +#else /* MEMP_MEM_MALLOC */ + memp->next = *desc->tab; + 800608e: 687b ldr r3, [r7, #4] + 8006090: 68db ldr r3, [r3, #12] + 8006092: 681a ldr r2, [r3, #0] + 8006094: 68fb ldr r3, [r7, #12] + 8006096: 601a str r2, [r3, #0] + *desc->tab = memp; + 8006098: 687b ldr r3, [r7, #4] + 800609a: 68db ldr r3, [r3, #12] + 800609c: 68fa ldr r2, [r7, #12] + 800609e: 601a str r2, [r3, #0] + LWIP_ASSERT("memp sanity", memp_sanity(desc)); +#endif /* MEMP_SANITY_CHECK */ + + SYS_ARCH_UNPROTECT(old_level); +#endif /* !MEMP_MEM_MALLOC */ +} + 80060a0: bf00 nop + 80060a2: 3710 adds r7, #16 + 80060a4: 46bd mov sp, r7 + 80060a6: bd80 pop {r7, pc} + 80060a8: 08012054 .word 0x08012054 + 80060ac: 0801212c .word 0x0801212c + 80060b0: 080120a8 .word 0x080120a8 + +080060b4 : + * @param desc the pool where to put mem + * @param mem the memp element to free + */ +void +memp_free_pool(const struct memp_desc *desc, void *mem) +{ + 80060b4: b580 push {r7, lr} + 80060b6: b082 sub sp, #8 + 80060b8: af00 add r7, sp, #0 + 80060ba: 6078 str r0, [r7, #4] + 80060bc: 6039 str r1, [r7, #0] + LWIP_ASSERT("invalid pool desc", desc != NULL); + 80060be: 687b ldr r3, [r7, #4] + 80060c0: 2b00 cmp r3, #0 + 80060c2: d106 bne.n 80060d2 + 80060c4: 4b0a ldr r3, [pc, #40] ; (80060f0 ) + 80060c6: f240 1295 movw r2, #405 ; 0x195 + 80060ca: 490a ldr r1, [pc, #40] ; (80060f4 ) + 80060cc: 480a ldr r0, [pc, #40] ; (80060f8 ) + 80060ce: f00a fd7b bl 8010bc8 + if ((desc == NULL) || (mem == NULL)) { + 80060d2: 687b ldr r3, [r7, #4] + 80060d4: 2b00 cmp r3, #0 + 80060d6: d007 beq.n 80060e8 + 80060d8: 683b ldr r3, [r7, #0] + 80060da: 2b00 cmp r3, #0 + 80060dc: d004 beq.n 80060e8 + return; + } + + do_memp_free_pool(desc, mem); + 80060de: 6839 ldr r1, [r7, #0] + 80060e0: 6878 ldr r0, [r7, #4] + 80060e2: f7ff ffc1 bl 8006068 + 80060e6: e000 b.n 80060ea + return; + 80060e8: bf00 nop +} + 80060ea: 3708 adds r7, #8 + 80060ec: 46bd mov sp, r7 + 80060ee: bd80 pop {r7, pc} + 80060f0: 08012054 .word 0x08012054 + 80060f4: 080120f8 .word 0x080120f8 + 80060f8: 080120a8 .word 0x080120a8 + +080060fc : + * @param type the pool where to put mem + * @param mem the memp element to free + */ +void +memp_free(memp_t type, void *mem) +{ + 80060fc: b580 push {r7, lr} + 80060fe: b082 sub sp, #8 + 8006100: af00 add r7, sp, #0 + 8006102: 4603 mov r3, r0 + 8006104: 6039 str r1, [r7, #0] + 8006106: 71fb strb r3, [r7, #7] +#ifdef LWIP_HOOK_MEMP_AVAILABLE + struct memp *old_first; +#endif + + LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;); + 8006108: 79fb ldrb r3, [r7, #7] + 800610a: 2b08 cmp r3, #8 + 800610c: d907 bls.n 800611e + 800610e: 4b0c ldr r3, [pc, #48] ; (8006140 ) + 8006110: f44f 72d5 mov.w r2, #426 ; 0x1aa + 8006114: 490b ldr r1, [pc, #44] ; (8006144 ) + 8006116: 480c ldr r0, [pc, #48] ; (8006148 ) + 8006118: f00a fd56 bl 8010bc8 + 800611c: e00c b.n 8006138 + + if (mem == NULL) { + 800611e: 683b ldr r3, [r7, #0] + 8006120: 2b00 cmp r3, #0 + 8006122: d008 beq.n 8006136 + +#ifdef LWIP_HOOK_MEMP_AVAILABLE + old_first = *memp_pools[type]->tab; +#endif + + do_memp_free_pool(memp_pools[type], mem); + 8006124: 79fb ldrb r3, [r7, #7] + 8006126: 4a09 ldr r2, [pc, #36] ; (800614c ) + 8006128: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800612c: 6839 ldr r1, [r7, #0] + 800612e: 4618 mov r0, r3 + 8006130: f7ff ff9a bl 8006068 + 8006134: e000 b.n 8006138 + return; + 8006136: bf00 nop +#ifdef LWIP_HOOK_MEMP_AVAILABLE + if (old_first == NULL) { + LWIP_HOOK_MEMP_AVAILABLE(type); + } +#endif +} + 8006138: 3708 adds r7, #8 + 800613a: 46bd mov sp, r7 + 800613c: bd80 pop {r7, pc} + 800613e: bf00 nop + 8006140: 08012054 .word 0x08012054 + 8006144: 0801214c .word 0x0801214c + 8006148: 080120a8 .word 0x080120a8 + 800614c: 08014d30 .word 0x08014d30 + +08006150 : +} +#endif /* LWIP_HAVE_LOOPIF */ + +void +netif_init(void) +{ + 8006150: b480 push {r7} + 8006152: af00 add r7, sp, #0 + + netif_set_link_up(&loop_netif); + netif_set_up(&loop_netif); + +#endif /* LWIP_HAVE_LOOPIF */ +} + 8006154: bf00 nop + 8006156: 46bd mov sp, r7 + 8006158: f85d 7b04 ldr.w r7, [sp], #4 + 800615c: 4770 bx lr + ... + +08006160 : +netif_add(struct netif *netif, +#if LWIP_IPV4 + const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, +#endif /* LWIP_IPV4 */ + void *state, netif_init_fn init, netif_input_fn input) +{ + 8006160: b580 push {r7, lr} + 8006162: b088 sub sp, #32 + 8006164: af02 add r7, sp, #8 + 8006166: 60f8 str r0, [r7, #12] + 8006168: 60b9 str r1, [r7, #8] + 800616a: 607a str r2, [r7, #4] + 800616c: 603b str r3, [r7, #0] + LWIP_ASSERT("single netif already set", 0); + return NULL; + } +#endif + + LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL); + 800616e: 68fb ldr r3, [r7, #12] + 8006170: 2b00 cmp r3, #0 + 8006172: d108 bne.n 8006186 + 8006174: 4b96 ldr r3, [pc, #600] ; (80063d0 ) + 8006176: f240 1227 movw r2, #295 ; 0x127 + 800617a: 4996 ldr r1, [pc, #600] ; (80063d4 ) + 800617c: 4896 ldr r0, [pc, #600] ; (80063d8 ) + 800617e: f00a fd23 bl 8010bc8 + 8006182: 2300 movs r3, #0 + 8006184: e14c b.n 8006420 + LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL); + 8006186: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006188: 2b00 cmp r3, #0 + 800618a: d108 bne.n 800619e + 800618c: 4b90 ldr r3, [pc, #576] ; (80063d0 ) + 800618e: f44f 7294 mov.w r2, #296 ; 0x128 + 8006192: 4992 ldr r1, [pc, #584] ; (80063dc ) + 8006194: 4890 ldr r0, [pc, #576] ; (80063d8 ) + 8006196: f00a fd17 bl 8010bc8 + 800619a: 2300 movs r3, #0 + 800619c: e140 b.n 8006420 + +#if LWIP_IPV4 + if (ipaddr == NULL) { + 800619e: 68bb ldr r3, [r7, #8] + 80061a0: 2b00 cmp r3, #0 + 80061a2: d101 bne.n 80061a8 + ipaddr = ip_2_ip4(IP4_ADDR_ANY); + 80061a4: 4b8e ldr r3, [pc, #568] ; (80063e0 ) + 80061a6: 60bb str r3, [r7, #8] + } + if (netmask == NULL) { + 80061a8: 687b ldr r3, [r7, #4] + 80061aa: 2b00 cmp r3, #0 + 80061ac: d101 bne.n 80061b2 + netmask = ip_2_ip4(IP4_ADDR_ANY); + 80061ae: 4b8c ldr r3, [pc, #560] ; (80063e0 ) + 80061b0: 607b str r3, [r7, #4] + } + if (gw == NULL) { + 80061b2: 683b ldr r3, [r7, #0] + 80061b4: 2b00 cmp r3, #0 + 80061b6: d101 bne.n 80061bc + gw = ip_2_ip4(IP4_ADDR_ANY); + 80061b8: 4b89 ldr r3, [pc, #548] ; (80063e0 ) + 80061ba: 603b str r3, [r7, #0] + } + + /* reset new interface configuration state */ + ip_addr_set_zero_ip4(&netif->ip_addr); + 80061bc: 68fb ldr r3, [r7, #12] + 80061be: 2200 movs r2, #0 + 80061c0: 605a str r2, [r3, #4] + ip_addr_set_zero_ip4(&netif->netmask); + 80061c2: 68fb ldr r3, [r7, #12] + 80061c4: 2200 movs r2, #0 + 80061c6: 609a str r2, [r3, #8] + ip_addr_set_zero_ip4(&netif->gw); + 80061c8: 68fb ldr r3, [r7, #12] + 80061ca: 2200 movs r2, #0 + 80061cc: 60da str r2, [r3, #12] + netif->output = netif_null_output_ip4; + 80061ce: 68fb ldr r3, [r7, #12] + 80061d0: 4a84 ldr r2, [pc, #528] ; (80063e4 ) + 80061d2: 615a str r2, [r3, #20] +#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ + } + netif->output_ip6 = netif_null_output_ip6; +#endif /* LWIP_IPV6 */ + NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL); + netif->mtu = 0; + 80061d4: 68fb ldr r3, [r7, #12] + 80061d6: 2200 movs r2, #0 + 80061d8: 849a strh r2, [r3, #36] ; 0x24 + netif->flags = 0; + 80061da: 68fb ldr r3, [r7, #12] + 80061dc: 2200 movs r2, #0 + 80061de: f883 202d strb.w r2, [r3, #45] ; 0x2d +#endif /* LWIP_IPV6 */ +#if LWIP_NETIF_STATUS_CALLBACK + netif->status_callback = NULL; +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + netif->link_callback = NULL; + 80061e2: 68fb ldr r3, [r7, #12] + 80061e4: 2200 movs r2, #0 + 80061e6: 61da str r2, [r3, #28] + netif->loop_first = NULL; + netif->loop_last = NULL; +#endif /* ENABLE_LOOPBACK */ + + /* remember netif specific state information data */ + netif->state = state; + 80061e8: 68fb ldr r3, [r7, #12] + 80061ea: 6a3a ldr r2, [r7, #32] + 80061ec: 621a str r2, [r3, #32] + netif->num = netif_num; + 80061ee: 4b7e ldr r3, [pc, #504] ; (80063e8 ) + 80061f0: 781a ldrb r2, [r3, #0] + 80061f2: 68fb ldr r3, [r7, #12] + 80061f4: f883 2030 strb.w r2, [r3, #48] ; 0x30 + netif->input = input; + 80061f8: 68fb ldr r3, [r7, #12] + 80061fa: 6aba ldr r2, [r7, #40] ; 0x28 + 80061fc: 611a str r2, [r3, #16] +#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS + netif->loop_cnt_current = 0; +#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */ + +#if LWIP_IPV4 + netif_set_addr(netif, ipaddr, netmask, gw); + 80061fe: 683b ldr r3, [r7, #0] + 8006200: 687a ldr r2, [r7, #4] + 8006202: 68b9 ldr r1, [r7, #8] + 8006204: 68f8 ldr r0, [r7, #12] + 8006206: f000 f9f5 bl 80065f4 +#endif /* LWIP_IPV4 */ + + /* call user specified initialization function for netif */ + if (init(netif) != ERR_OK) { + 800620a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800620c: 68f8 ldr r0, [r7, #12] + 800620e: 4798 blx r3 + 8006210: 4603 mov r3, r0 + 8006212: 2b00 cmp r3, #0 + 8006214: d001 beq.n 800621a + return NULL; + 8006216: 2300 movs r3, #0 + 8006218: e102 b.n 8006420 + */ + { + struct netif *netif2; + int num_netifs; + do { + if (netif->num == 255) { + 800621a: 68fb ldr r3, [r7, #12] + 800621c: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8006220: 2bff cmp r3, #255 ; 0xff + 8006222: d103 bne.n 800622c + netif->num = 0; + 8006224: 68fb ldr r3, [r7, #12] + 8006226: 2200 movs r2, #0 + 8006228: f883 2030 strb.w r2, [r3, #48] ; 0x30 + } + num_netifs = 0; + 800622c: 2300 movs r3, #0 + 800622e: 613b str r3, [r7, #16] + for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) { + 8006230: 4b6e ldr r3, [pc, #440] ; (80063ec ) + 8006232: 681b ldr r3, [r3, #0] + 8006234: 617b str r3, [r7, #20] + 8006236: e02b b.n 8006290 + LWIP_ASSERT("netif already added", netif2 != netif); + 8006238: 697a ldr r2, [r7, #20] + 800623a: 68fb ldr r3, [r7, #12] + 800623c: 429a cmp r2, r3 + 800623e: d106 bne.n 800624e + 8006240: 4b63 ldr r3, [pc, #396] ; (80063d0 ) + 8006242: f240 128b movw r2, #395 ; 0x18b + 8006246: 496a ldr r1, [pc, #424] ; (80063f0 ) + 8006248: 4863 ldr r0, [pc, #396] ; (80063d8 ) + 800624a: f00a fcbd bl 8010bc8 + num_netifs++; + 800624e: 693b ldr r3, [r7, #16] + 8006250: 3301 adds r3, #1 + 8006252: 613b str r3, [r7, #16] + LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255); + 8006254: 693b ldr r3, [r7, #16] + 8006256: 2bff cmp r3, #255 ; 0xff + 8006258: dd06 ble.n 8006268 + 800625a: 4b5d ldr r3, [pc, #372] ; (80063d0 ) + 800625c: f240 128d movw r2, #397 ; 0x18d + 8006260: 4964 ldr r1, [pc, #400] ; (80063f4 ) + 8006262: 485d ldr r0, [pc, #372] ; (80063d8 ) + 8006264: f00a fcb0 bl 8010bc8 + if (netif2->num == netif->num) { + 8006268: 697b ldr r3, [r7, #20] + 800626a: f893 2030 ldrb.w r2, [r3, #48] ; 0x30 + 800626e: 68fb ldr r3, [r7, #12] + 8006270: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8006274: 429a cmp r2, r3 + 8006276: d108 bne.n 800628a + netif->num++; + 8006278: 68fb ldr r3, [r7, #12] + 800627a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 800627e: 3301 adds r3, #1 + 8006280: b2da uxtb r2, r3 + 8006282: 68fb ldr r3, [r7, #12] + 8006284: f883 2030 strb.w r2, [r3, #48] ; 0x30 + break; + 8006288: e005 b.n 8006296 + for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) { + 800628a: 697b ldr r3, [r7, #20] + 800628c: 681b ldr r3, [r3, #0] + 800628e: 617b str r3, [r7, #20] + 8006290: 697b ldr r3, [r7, #20] + 8006292: 2b00 cmp r3, #0 + 8006294: d1d0 bne.n 8006238 + } + } + } while (netif2 != NULL); + 8006296: 697b ldr r3, [r7, #20] + 8006298: 2b00 cmp r3, #0 + 800629a: d1be bne.n 800621a + } + if (netif->num == 254) { + 800629c: 68fb ldr r3, [r7, #12] + 800629e: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 80062a2: 2bfe cmp r3, #254 ; 0xfe + 80062a4: d103 bne.n 80062ae + netif_num = 0; + 80062a6: 4b50 ldr r3, [pc, #320] ; (80063e8 ) + 80062a8: 2200 movs r2, #0 + 80062aa: 701a strb r2, [r3, #0] + 80062ac: e006 b.n 80062bc + } else { + netif_num = (u8_t)(netif->num + 1); + 80062ae: 68fb ldr r3, [r7, #12] + 80062b0: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 80062b4: 3301 adds r3, #1 + 80062b6: b2da uxtb r2, r3 + 80062b8: 4b4b ldr r3, [pc, #300] ; (80063e8 ) + 80062ba: 701a strb r2, [r3, #0] + } + + /* add this netif to the list */ + netif->next = netif_list; + 80062bc: 4b4b ldr r3, [pc, #300] ; (80063ec ) + 80062be: 681a ldr r2, [r3, #0] + 80062c0: 68fb ldr r3, [r7, #12] + 80062c2: 601a str r2, [r3, #0] + netif_list = netif; + 80062c4: 4a49 ldr r2, [pc, #292] ; (80063ec ) + 80062c6: 68fb ldr r3, [r7, #12] + 80062c8: 6013 str r3, [r2, #0] + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_start(netif); + } +#endif /* LWIP_IGMP */ + + LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP", + 80062ca: 68fb ldr r3, [r7, #12] + 80062cc: f893 302e ldrb.w r3, [r3, #46] ; 0x2e + 80062d0: 4619 mov r1, r3 + 80062d2: 68fb ldr r3, [r7, #12] + 80062d4: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 80062d8: 461a mov r2, r3 + 80062da: 4847 ldr r0, [pc, #284] ; (80063f8 ) + 80062dc: f00a fc74 bl 8010bc8 + netif->name[0], netif->name[1])); +#if LWIP_IPV4 + LWIP_DEBUGF(NETIF_DEBUG, (" addr ")); + 80062e0: 4846 ldr r0, [pc, #280] ; (80063fc ) + 80062e2: f00a fc71 bl 8010bc8 + ip4_addr_debug_print(NETIF_DEBUG, ipaddr); + 80062e6: 68bb ldr r3, [r7, #8] + 80062e8: 2b00 cmp r3, #0 + 80062ea: d003 beq.n 80062f4 + 80062ec: 68bb ldr r3, [r7, #8] + 80062ee: 781b ldrb r3, [r3, #0] + 80062f0: 4619 mov r1, r3 + 80062f2: e000 b.n 80062f6 + 80062f4: 2100 movs r1, #0 + 80062f6: 68bb ldr r3, [r7, #8] + 80062f8: 2b00 cmp r3, #0 + 80062fa: d004 beq.n 8006306 + 80062fc: 68bb ldr r3, [r7, #8] + 80062fe: 3301 adds r3, #1 + 8006300: 781b ldrb r3, [r3, #0] + 8006302: 461a mov r2, r3 + 8006304: e000 b.n 8006308 + 8006306: 2200 movs r2, #0 + 8006308: 68bb ldr r3, [r7, #8] + 800630a: 2b00 cmp r3, #0 + 800630c: d004 beq.n 8006318 + 800630e: 68bb ldr r3, [r7, #8] + 8006310: 3302 adds r3, #2 + 8006312: 781b ldrb r3, [r3, #0] + 8006314: 4618 mov r0, r3 + 8006316: e000 b.n 800631a + 8006318: 2000 movs r0, #0 + 800631a: 68bb ldr r3, [r7, #8] + 800631c: 2b00 cmp r3, #0 + 800631e: d003 beq.n 8006328 + 8006320: 68bb ldr r3, [r7, #8] + 8006322: 3303 adds r3, #3 + 8006324: 781b ldrb r3, [r3, #0] + 8006326: e000 b.n 800632a + 8006328: 2300 movs r3, #0 + 800632a: 9300 str r3, [sp, #0] + 800632c: 4603 mov r3, r0 + 800632e: 4834 ldr r0, [pc, #208] ; (8006400 ) + 8006330: f00a fc4a bl 8010bc8 + LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); + 8006334: 4833 ldr r0, [pc, #204] ; (8006404 ) + 8006336: f00a fc47 bl 8010bc8 + ip4_addr_debug_print(NETIF_DEBUG, netmask); + 800633a: 687b ldr r3, [r7, #4] + 800633c: 2b00 cmp r3, #0 + 800633e: d003 beq.n 8006348 + 8006340: 687b ldr r3, [r7, #4] + 8006342: 781b ldrb r3, [r3, #0] + 8006344: 4619 mov r1, r3 + 8006346: e000 b.n 800634a + 8006348: 2100 movs r1, #0 + 800634a: 687b ldr r3, [r7, #4] + 800634c: 2b00 cmp r3, #0 + 800634e: d004 beq.n 800635a + 8006350: 687b ldr r3, [r7, #4] + 8006352: 3301 adds r3, #1 + 8006354: 781b ldrb r3, [r3, #0] + 8006356: 461a mov r2, r3 + 8006358: e000 b.n 800635c + 800635a: 2200 movs r2, #0 + 800635c: 687b ldr r3, [r7, #4] + 800635e: 2b00 cmp r3, #0 + 8006360: d004 beq.n 800636c + 8006362: 687b ldr r3, [r7, #4] + 8006364: 3302 adds r3, #2 + 8006366: 781b ldrb r3, [r3, #0] + 8006368: 4618 mov r0, r3 + 800636a: e000 b.n 800636e + 800636c: 2000 movs r0, #0 + 800636e: 687b ldr r3, [r7, #4] + 8006370: 2b00 cmp r3, #0 + 8006372: d003 beq.n 800637c + 8006374: 687b ldr r3, [r7, #4] + 8006376: 3303 adds r3, #3 + 8006378: 781b ldrb r3, [r3, #0] + 800637a: e000 b.n 800637e + 800637c: 2300 movs r3, #0 + 800637e: 9300 str r3, [sp, #0] + 8006380: 4603 mov r3, r0 + 8006382: 481f ldr r0, [pc, #124] ; (8006400 ) + 8006384: f00a fc20 bl 8010bc8 + LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); + 8006388: 481f ldr r0, [pc, #124] ; (8006408 ) + 800638a: f00a fc1d bl 8010bc8 + ip4_addr_debug_print(NETIF_DEBUG, gw); + 800638e: 683b ldr r3, [r7, #0] + 8006390: 2b00 cmp r3, #0 + 8006392: d003 beq.n 800639c + 8006394: 683b ldr r3, [r7, #0] + 8006396: 781b ldrb r3, [r3, #0] + 8006398: 4619 mov r1, r3 + 800639a: e000 b.n 800639e + 800639c: 2100 movs r1, #0 + 800639e: 683b ldr r3, [r7, #0] + 80063a0: 2b00 cmp r3, #0 + 80063a2: d004 beq.n 80063ae + 80063a4: 683b ldr r3, [r7, #0] + 80063a6: 3301 adds r3, #1 + 80063a8: 781b ldrb r3, [r3, #0] + 80063aa: 461a mov r2, r3 + 80063ac: e000 b.n 80063b0 + 80063ae: 2200 movs r2, #0 + 80063b0: 683b ldr r3, [r7, #0] + 80063b2: 2b00 cmp r3, #0 + 80063b4: d004 beq.n 80063c0 + 80063b6: 683b ldr r3, [r7, #0] + 80063b8: 3302 adds r3, #2 + 80063ba: 781b ldrb r3, [r3, #0] + 80063bc: 4618 mov r0, r3 + 80063be: e000 b.n 80063c2 + 80063c0: 2000 movs r0, #0 + 80063c2: 683b ldr r3, [r7, #0] + 80063c4: 2b00 cmp r3, #0 + 80063c6: d021 beq.n 800640c + 80063c8: 683b ldr r3, [r7, #0] + 80063ca: 3303 adds r3, #3 + 80063cc: 781b ldrb r3, [r3, #0] + 80063ce: e01e b.n 800640e + 80063d0: 08012168 .word 0x08012168 + 80063d4: 080121fc .word 0x080121fc + 80063d8: 080121b8 .word 0x080121b8 + 80063dc: 08012218 .word 0x08012218 + 80063e0: 08014d94 .word 0x08014d94 + 80063e4: 080068f7 .word 0x080068f7 + 80063e8: 24007b68 .word 0x24007b68 + 80063ec: 24007b60 .word 0x24007b60 + 80063f0: 0801223c .word 0x0801223c + 80063f4: 08012250 .word 0x08012250 + 80063f8: 08012280 .word 0x08012280 + 80063fc: 080122a0 .word 0x080122a0 + 8006400: 080122a8 .word 0x080122a8 + 8006404: 080122b8 .word 0x080122b8 + 8006408: 080122c4 .word 0x080122c4 + 800640c: 2300 movs r3, #0 + 800640e: 9300 str r3, [sp, #0] + 8006410: 4603 mov r3, r0 + 8006412: 4805 ldr r0, [pc, #20] ; (8006428 ) + 8006414: f00a fbd8 bl 8010bc8 +#endif /* LWIP_IPV4 */ + LWIP_DEBUGF(NETIF_DEBUG, ("\n")); + 8006418: 200a movs r0, #10 + 800641a: f00a fbe7 bl 8010bec + + netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL); + + return netif; + 800641e: 68fb ldr r3, [r7, #12] +} + 8006420: 4618 mov r0, r3 + 8006422: 3718 adds r7, #24 + 8006424: 46bd mov sp, r7 + 8006426: bd80 pop {r7, pc} + 8006428: 080122a8 .word 0x080122a8 + +0800642c : + +static void +netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + 800642c: b580 push {r7, lr} + 800642e: b082 sub sp, #8 + 8006430: af00 add r7, sp, #0 + 8006432: 6078 str r0, [r7, #4] + 8006434: 6039 str r1, [r7, #0] +#if LWIP_TCP + tcp_netif_ip_addr_changed(old_addr, new_addr); + 8006436: 6839 ldr r1, [r7, #0] + 8006438: 6878 ldr r0, [r7, #4] + 800643a: f002 fd85 bl 8008f48 +#endif /* LWIP_TCP */ +#if LWIP_UDP + udp_netif_ip_addr_changed(old_addr, new_addr); + 800643e: 6839 ldr r1, [r7, #0] + 8006440: 6878 ldr r0, [r7, #4] + 8006442: f007 fb2d bl 800daa0 +#endif /* LWIP_UDP */ +#if LWIP_RAW + raw_netif_ip_addr_changed(old_addr, new_addr); +#endif /* LWIP_RAW */ +} + 8006446: bf00 nop + 8006448: 3708 adds r7, #8 + 800644a: 46bd mov sp, r7 + 800644c: bd80 pop {r7, pc} + ... + +08006450 : + +#if LWIP_IPV4 +static int +netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr) +{ + 8006450: b580 push {r7, lr} + 8006452: b086 sub sp, #24 + 8006454: af00 add r7, sp, #0 + 8006456: 60f8 str r0, [r7, #12] + 8006458: 60b9 str r1, [r7, #8] + 800645a: 607a str r2, [r7, #4] + LWIP_ASSERT("invalid pointer", ipaddr != NULL); + 800645c: 68bb ldr r3, [r7, #8] + 800645e: 2b00 cmp r3, #0 + 8006460: d106 bne.n 8006470 + 8006462: 4b1e ldr r3, [pc, #120] ; (80064dc ) + 8006464: f240 12cb movw r2, #459 ; 0x1cb + 8006468: 491d ldr r1, [pc, #116] ; (80064e0 ) + 800646a: 481e ldr r0, [pc, #120] ; (80064e4 ) + 800646c: f00a fbac bl 8010bc8 + LWIP_ASSERT("invalid pointer", old_addr != NULL); + 8006470: 687b ldr r3, [r7, #4] + 8006472: 2b00 cmp r3, #0 + 8006474: d106 bne.n 8006484 + 8006476: 4b19 ldr r3, [pc, #100] ; (80064dc ) + 8006478: f44f 72e6 mov.w r2, #460 ; 0x1cc + 800647c: 4918 ldr r1, [pc, #96] ; (80064e0 ) + 800647e: 4819 ldr r0, [pc, #100] ; (80064e4 ) + 8006480: f00a fba2 bl 8010bc8 + + /* address is actually being changed? */ + if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) { + 8006484: 68bb ldr r3, [r7, #8] + 8006486: 681a ldr r2, [r3, #0] + 8006488: 68fb ldr r3, [r7, #12] + 800648a: 3304 adds r3, #4 + 800648c: 681b ldr r3, [r3, #0] + 800648e: 429a cmp r2, r3 + 8006490: d01f beq.n 80064d2 + ip_addr_t new_addr; + *ip_2_ip4(&new_addr) = *ipaddr; + 8006492: 68bb ldr r3, [r7, #8] + 8006494: 681b ldr r3, [r3, #0] + 8006496: 617b str r3, [r7, #20] + IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4); + + ip_addr_copy(*old_addr, *netif_ip_addr4(netif)); + 8006498: 68fb ldr r3, [r7, #12] + 800649a: 3304 adds r3, #4 + 800649c: 681a ldr r2, [r3, #0] + 800649e: 687b ldr r3, [r7, #4] + 80064a0: 601a str r2, [r3, #0] + + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n")); + 80064a2: 4811 ldr r0, [pc, #68] ; (80064e8 ) + 80064a4: f00a fbfe bl 8010ca4 + netif_do_ip_addr_changed(old_addr, &new_addr); + 80064a8: f107 0314 add.w r3, r7, #20 + 80064ac: 4619 mov r1, r3 + 80064ae: 6878 ldr r0, [r7, #4] + 80064b0: f7ff ffbc bl 800642c + + mib2_remove_ip4(netif); + mib2_remove_route_ip4(0, netif); + /* set new IP address to netif */ + ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr); + 80064b4: 68bb ldr r3, [r7, #8] + 80064b6: 2b00 cmp r3, #0 + 80064b8: d002 beq.n 80064c0 + 80064ba: 68bb ldr r3, [r7, #8] + 80064bc: 681b ldr r3, [r3, #0] + 80064be: e000 b.n 80064c2 + 80064c0: 2300 movs r3, #0 + 80064c2: 68fa ldr r2, [r7, #12] + 80064c4: 6053 str r3, [r2, #4] + IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4); + mib2_add_ip4(netif); + mib2_add_route_ip4(0, netif); + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4); + 80064c6: 2101 movs r1, #1 + 80064c8: 68f8 ldr r0, [r7, #12] + 80064ca: f000 f92d bl 8006728 + + NETIF_STATUS_CALLBACK(netif); + return 1; /* address changed */ + 80064ce: 2301 movs r3, #1 + 80064d0: e000 b.n 80064d4 + } + return 0; /* address unchanged */ + 80064d2: 2300 movs r3, #0 +} + 80064d4: 4618 mov r0, r3 + 80064d6: 3718 adds r7, #24 + 80064d8: 46bd mov sp, r7 + 80064da: bd80 pop {r7, pc} + 80064dc: 08012168 .word 0x08012168 + 80064e0: 080122cc .word 0x080122cc + 80064e4: 080121b8 .word 0x080121b8 + 80064e8: 080122dc .word 0x080122dc + +080064ec : + } +} + +static int +netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm) +{ + 80064ec: b5b0 push {r4, r5, r7, lr} + 80064ee: b088 sub sp, #32 + 80064f0: af04 add r7, sp, #16 + 80064f2: 60f8 str r0, [r7, #12] + 80064f4: 60b9 str r1, [r7, #8] + 80064f6: 607a str r2, [r7, #4] + /* address is actually being changed? */ + if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) { + 80064f8: 68bb ldr r3, [r7, #8] + 80064fa: 681a ldr r2, [r3, #0] + 80064fc: 68fb ldr r3, [r7, #12] + 80064fe: 3308 adds r3, #8 + 8006500: 681b ldr r3, [r3, #0] + 8006502: 429a cmp r2, r3 + 8006504: d02d beq.n 8006562 +#else + LWIP_UNUSED_ARG(old_nm); +#endif + mib2_remove_route_ip4(0, netif); + /* set new netmask to netif */ + ip4_addr_set(ip_2_ip4(&netif->netmask), netmask); + 8006506: 68bb ldr r3, [r7, #8] + 8006508: 2b00 cmp r3, #0 + 800650a: d002 beq.n 8006512 + 800650c: 68bb ldr r3, [r7, #8] + 800650e: 681b ldr r3, [r3, #0] + 8006510: e000 b.n 8006514 + 8006512: 2300 movs r3, #0 + 8006514: 68fa ldr r2, [r7, #12] + 8006516: 6093 str r3, [r2, #8] + IP_SET_TYPE_VAL(netif->netmask, IPADDR_TYPE_V4); + mib2_add_route_ip4(0, netif); + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + 8006518: 68fb ldr r3, [r7, #12] + 800651a: f893 302e ldrb.w r3, [r3, #46] ; 0x2e + 800651e: 4618 mov r0, r3 + 8006520: 68fb ldr r3, [r7, #12] + 8006522: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 8006526: 461c mov r4, r3 + 8006528: 68fb ldr r3, [r7, #12] + 800652a: 3308 adds r3, #8 + 800652c: 781b ldrb r3, [r3, #0] + 800652e: 461d mov r5, r3 + 8006530: 68fb ldr r3, [r7, #12] + 8006532: 3308 adds r3, #8 + 8006534: 3301 adds r3, #1 + 8006536: 781b ldrb r3, [r3, #0] + 8006538: 461a mov r2, r3 + 800653a: 68fb ldr r3, [r7, #12] + 800653c: 3308 adds r3, #8 + 800653e: 3302 adds r3, #2 + 8006540: 781b ldrb r3, [r3, #0] + 8006542: 4619 mov r1, r3 + 8006544: 68fb ldr r3, [r7, #12] + 8006546: 3308 adds r3, #8 + 8006548: 3303 adds r3, #3 + 800654a: 781b ldrb r3, [r3, #0] + 800654c: 9302 str r3, [sp, #8] + 800654e: 9101 str r1, [sp, #4] + 8006550: 9200 str r2, [sp, #0] + 8006552: 462b mov r3, r5 + 8006554: 4622 mov r2, r4 + 8006556: 4601 mov r1, r0 + 8006558: 4804 ldr r0, [pc, #16] ; (800656c ) + 800655a: f00a fb35 bl 8010bc8 + netif->name[0], netif->name[1], + ip4_addr1_16(netif_ip4_netmask(netif)), + ip4_addr2_16(netif_ip4_netmask(netif)), + ip4_addr3_16(netif_ip4_netmask(netif)), + ip4_addr4_16(netif_ip4_netmask(netif)))); + return 1; /* netmask changed */ + 800655e: 2301 movs r3, #1 + 8006560: e000 b.n 8006564 + } + return 0; /* netmask unchanged */ + 8006562: 2300 movs r3, #0 +} + 8006564: 4618 mov r0, r3 + 8006566: 3710 adds r7, #16 + 8006568: 46bd mov sp, r7 + 800656a: bdb0 pop {r4, r5, r7, pc} + 800656c: 0801232c .word 0x0801232c + +08006570 : + } +} + +static int +netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw) +{ + 8006570: b5b0 push {r4, r5, r7, lr} + 8006572: b088 sub sp, #32 + 8006574: af04 add r7, sp, #16 + 8006576: 60f8 str r0, [r7, #12] + 8006578: 60b9 str r1, [r7, #8] + 800657a: 607a str r2, [r7, #4] + /* address is actually being changed? */ + if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) { + 800657c: 68bb ldr r3, [r7, #8] + 800657e: 681a ldr r2, [r3, #0] + 8006580: 68fb ldr r3, [r7, #12] + 8006582: 330c adds r3, #12 + 8006584: 681b ldr r3, [r3, #0] + 8006586: 429a cmp r2, r3 + 8006588: d02d beq.n 80065e6 + ip_addr_copy(*old_gw, *netif_ip_gw4(netif)); +#else + LWIP_UNUSED_ARG(old_gw); +#endif + + ip4_addr_set(ip_2_ip4(&netif->gw), gw); + 800658a: 68bb ldr r3, [r7, #8] + 800658c: 2b00 cmp r3, #0 + 800658e: d002 beq.n 8006596 + 8006590: 68bb ldr r3, [r7, #8] + 8006592: 681b ldr r3, [r3, #0] + 8006594: e000 b.n 8006598 + 8006596: 2300 movs r3, #0 + 8006598: 68fa ldr r2, [r7, #12] + 800659a: 60d3 str r3, [r2, #12] + IP_SET_TYPE_VAL(netif->gw, IPADDR_TYPE_V4); + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + 800659c: 68fb ldr r3, [r7, #12] + 800659e: f893 302e ldrb.w r3, [r3, #46] ; 0x2e + 80065a2: 4618 mov r0, r3 + 80065a4: 68fb ldr r3, [r7, #12] + 80065a6: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 80065aa: 461c mov r4, r3 + 80065ac: 68fb ldr r3, [r7, #12] + 80065ae: 330c adds r3, #12 + 80065b0: 781b ldrb r3, [r3, #0] + 80065b2: 461d mov r5, r3 + 80065b4: 68fb ldr r3, [r7, #12] + 80065b6: 330c adds r3, #12 + 80065b8: 3301 adds r3, #1 + 80065ba: 781b ldrb r3, [r3, #0] + 80065bc: 461a mov r2, r3 + 80065be: 68fb ldr r3, [r7, #12] + 80065c0: 330c adds r3, #12 + 80065c2: 3302 adds r3, #2 + 80065c4: 781b ldrb r3, [r3, #0] + 80065c6: 4619 mov r1, r3 + 80065c8: 68fb ldr r3, [r7, #12] + 80065ca: 330c adds r3, #12 + 80065cc: 3303 adds r3, #3 + 80065ce: 781b ldrb r3, [r3, #0] + 80065d0: 9302 str r3, [sp, #8] + 80065d2: 9101 str r1, [sp, #4] + 80065d4: 9200 str r2, [sp, #0] + 80065d6: 462b mov r3, r5 + 80065d8: 4622 mov r2, r4 + 80065da: 4601 mov r1, r0 + 80065dc: 4804 ldr r0, [pc, #16] ; (80065f0 ) + 80065de: f00a faf3 bl 8010bc8 + netif->name[0], netif->name[1], + ip4_addr1_16(netif_ip4_gw(netif)), + ip4_addr2_16(netif_ip4_gw(netif)), + ip4_addr3_16(netif_ip4_gw(netif)), + ip4_addr4_16(netif_ip4_gw(netif)))); + return 1; /* gateway changed */ + 80065e2: 2301 movs r3, #1 + 80065e4: e000 b.n 80065e8 + } + return 0; /* gateway unchanged */ + 80065e6: 2300 movs r3, #0 +} + 80065e8: 4618 mov r0, r3 + 80065ea: 3710 adds r7, #16 + 80065ec: 46bd mov sp, r7 + 80065ee: bdb0 pop {r4, r5, r7, pc} + 80065f0: 0801238c .word 0x0801238c + +080065f4 : + * @param gw the new default gateway + */ +void +netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, + const ip4_addr_t *gw) +{ + 80065f4: b580 push {r7, lr} + 80065f6: b088 sub sp, #32 + 80065f8: af00 add r7, sp, #0 + 80065fa: 60f8 str r0, [r7, #12] + 80065fc: 60b9 str r1, [r7, #8] + 80065fe: 607a str r2, [r7, #4] + 8006600: 603b str r3, [r7, #0] + ip_addr_t old_nm_val; + ip_addr_t old_gw_val; + ip_addr_t *old_nm = &old_nm_val; + ip_addr_t *old_gw = &old_gw_val; +#else + ip_addr_t *old_nm = NULL; + 8006602: 2300 movs r3, #0 + 8006604: 61fb str r3, [r7, #28] + ip_addr_t *old_gw = NULL; + 8006606: 2300 movs r3, #0 + 8006608: 61bb str r3, [r7, #24] + int remove; + + LWIP_ASSERT_CORE_LOCKED(); + + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (ipaddr == NULL) { + 800660a: 68bb ldr r3, [r7, #8] + 800660c: 2b00 cmp r3, #0 + 800660e: d101 bne.n 8006614 + ipaddr = IP4_ADDR_ANY4; + 8006610: 4b1c ldr r3, [pc, #112] ; (8006684 ) + 8006612: 60bb str r3, [r7, #8] + } + if (netmask == NULL) { + 8006614: 687b ldr r3, [r7, #4] + 8006616: 2b00 cmp r3, #0 + 8006618: d101 bne.n 800661e + netmask = IP4_ADDR_ANY4; + 800661a: 4b1a ldr r3, [pc, #104] ; (8006684 ) + 800661c: 607b str r3, [r7, #4] + } + if (gw == NULL) { + 800661e: 683b ldr r3, [r7, #0] + 8006620: 2b00 cmp r3, #0 + 8006622: d101 bne.n 8006628 + gw = IP4_ADDR_ANY4; + 8006624: 4b17 ldr r3, [pc, #92] ; (8006684 ) + 8006626: 603b str r3, [r7, #0] + } + + remove = ip4_addr_isany(ipaddr); + 8006628: 68bb ldr r3, [r7, #8] + 800662a: 2b00 cmp r3, #0 + 800662c: d003 beq.n 8006636 + 800662e: 68bb ldr r3, [r7, #8] + 8006630: 681b ldr r3, [r3, #0] + 8006632: 2b00 cmp r3, #0 + 8006634: d101 bne.n 800663a + 8006636: 2301 movs r3, #1 + 8006638: e000 b.n 800663c + 800663a: 2300 movs r3, #0 + 800663c: 617b str r3, [r7, #20] + if (remove) { + 800663e: 697b ldr r3, [r7, #20] + 8006640: 2b00 cmp r3, #0 + 8006642: d006 beq.n 8006652 + /* when removing an address, we have to remove it *before* changing netmask/gw + to ensure that tcp RST segment can be sent correctly */ + if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { + 8006644: f107 0310 add.w r3, r7, #16 + 8006648: 461a mov r2, r3 + 800664a: 68b9 ldr r1, [r7, #8] + 800664c: 68f8 ldr r0, [r7, #12] + 800664e: f7ff feff bl 8006450 + change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED; + cb_args.ipv4_changed.old_address = &old_addr; +#endif + } + } + if (netif_do_set_netmask(netif, netmask, old_nm)) { + 8006652: 69fa ldr r2, [r7, #28] + 8006654: 6879 ldr r1, [r7, #4] + 8006656: 68f8 ldr r0, [r7, #12] + 8006658: f7ff ff48 bl 80064ec +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED; + cb_args.ipv4_changed.old_netmask = old_nm; +#endif + } + if (netif_do_set_gw(netif, gw, old_gw)) { + 800665c: 69ba ldr r2, [r7, #24] + 800665e: 6839 ldr r1, [r7, #0] + 8006660: 68f8 ldr r0, [r7, #12] + 8006662: f7ff ff85 bl 8006570 +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED; + cb_args.ipv4_changed.old_gw = old_gw; +#endif + } + if (!remove) { + 8006666: 697b ldr r3, [r7, #20] + 8006668: 2b00 cmp r3, #0 + 800666a: d106 bne.n 800667a + /* set ipaddr last to ensure netmask/gw have been set when status callback is called */ + if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { + 800666c: f107 0310 add.w r3, r7, #16 + 8006670: 461a mov r2, r3 + 8006672: 68b9 ldr r1, [r7, #8] + 8006674: 68f8 ldr r0, [r7, #12] + 8006676: f7ff feeb bl 8006450 + if (change_reason != LWIP_NSC_NONE) { + change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED; + netif_invoke_ext_callback(netif, change_reason, &cb_args); + } +#endif +} + 800667a: bf00 nop + 800667c: 3720 adds r7, #32 + 800667e: 46bd mov sp, r7 + 8006680: bd80 pop {r7, pc} + 8006682: bf00 nop + 8006684: 08014d94 .word 0x08014d94 + +08006688 : + * + * @param netif the default network interface + */ +void +netif_set_default(struct netif *netif) +{ + 8006688: b580 push {r7, lr} + 800668a: b082 sub sp, #8 + 800668c: af00 add r7, sp, #0 + 800668e: 6078 str r0, [r7, #4] + mib2_remove_route_ip4(1, netif); + } else { + /* install default route */ + mib2_add_route_ip4(1, netif); + } + netif_default = netif; + 8006690: 4a0d ldr r2, [pc, #52] ; (80066c8 ) + 8006692: 687b ldr r3, [r7, #4] + 8006694: 6013 str r3, [r2, #0] + LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", + 8006696: 687b ldr r3, [r7, #4] + 8006698: 2b00 cmp r3, #0 + 800669a: d004 beq.n 80066a6 + 800669c: 687b ldr r3, [r7, #4] + 800669e: f893 302e ldrb.w r3, [r3, #46] ; 0x2e + 80066a2: 4619 mov r1, r3 + 80066a4: e000 b.n 80066a8 + 80066a6: 2127 movs r1, #39 ; 0x27 + 80066a8: 687b ldr r3, [r7, #4] + 80066aa: 2b00 cmp r3, #0 + 80066ac: d003 beq.n 80066b6 + 80066ae: 687b ldr r3, [r7, #4] + 80066b0: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 80066b4: e000 b.n 80066b8 + 80066b6: 2327 movs r3, #39 ; 0x27 + 80066b8: 461a mov r2, r3 + 80066ba: 4804 ldr r0, [pc, #16] ; (80066cc ) + 80066bc: f00a fa84 bl 8010bc8 + netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); +} + 80066c0: bf00 nop + 80066c2: 3708 adds r7, #8 + 80066c4: 46bd mov sp, r7 + 80066c6: bd80 pop {r7, pc} + 80066c8: 24007b64 .word 0x24007b64 + 80066cc: 08012400 .word 0x08012400 + +080066d0 : + * Bring an interface up, available for processing + * traffic. + */ +void +netif_set_up(struct netif *netif) +{ + 80066d0: b580 push {r7, lr} + 80066d2: b082 sub sp, #8 + 80066d4: af00 add r7, sp, #0 + 80066d6: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return); + 80066d8: 687b ldr r3, [r7, #4] + 80066da: 2b00 cmp r3, #0 + 80066dc: d107 bne.n 80066ee + 80066de: 4b0f ldr r3, [pc, #60] ; (800671c ) + 80066e0: f44f 7254 mov.w r2, #848 ; 0x350 + 80066e4: 490e ldr r1, [pc, #56] ; (8006720 ) + 80066e6: 480f ldr r0, [pc, #60] ; (8006724 ) + 80066e8: f00a fa6e bl 8010bc8 + 80066ec: e013 b.n 8006716 + + if (!(netif->flags & NETIF_FLAG_UP)) { + 80066ee: 687b ldr r3, [r7, #4] + 80066f0: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 80066f4: f003 0301 and.w r3, r3, #1 + 80066f8: 2b00 cmp r3, #0 + 80066fa: d10c bne.n 8006716 + netif_set_flags(netif, NETIF_FLAG_UP); + 80066fc: 687b ldr r3, [r7, #4] + 80066fe: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8006702: f043 0301 orr.w r3, r3, #1 + 8006706: b2da uxtb r2, r3 + 8006708: 687b ldr r3, [r7, #4] + 800670a: f883 202d strb.w r2, [r3, #45] ; 0x2d + args.status_changed.state = 1; + netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); + } +#endif + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); + 800670e: 2103 movs r1, #3 + 8006710: 6878 ldr r0, [r7, #4] + 8006712: f000 f809 bl 8006728 +#if LWIP_IPV6 + nd6_restart_netif(netif); +#endif /* LWIP_IPV6 */ + } +} + 8006716: 3708 adds r7, #8 + 8006718: 46bd mov sp, r7 + 800671a: bd80 pop {r7, pc} + 800671c: 08012168 .word 0x08012168 + 8006720: 08012428 .word 0x08012428 + 8006724: 080121b8 .word 0x080121b8 + +08006728 : + +/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change + */ +static void +netif_issue_reports(struct netif *netif, u8_t report_type) +{ + 8006728: b580 push {r7, lr} + 800672a: b082 sub sp, #8 + 800672c: af00 add r7, sp, #0 + 800672e: 6078 str r0, [r7, #4] + 8006730: 460b mov r3, r1 + 8006732: 70fb strb r3, [r7, #3] + LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL); + 8006734: 687b ldr r3, [r7, #4] + 8006736: 2b00 cmp r3, #0 + 8006738: d106 bne.n 8006748 + 800673a: 4b18 ldr r3, [pc, #96] ; (800679c ) + 800673c: f240 326d movw r2, #877 ; 0x36d + 8006740: 4917 ldr r1, [pc, #92] ; (80067a0 ) + 8006742: 4818 ldr r0, [pc, #96] ; (80067a4 ) + 8006744: f00a fa40 bl 8010bc8 + + /* Only send reports when both link and admin states are up */ + if (!(netif->flags & NETIF_FLAG_LINK_UP) || + 8006748: 687b ldr r3, [r7, #4] + 800674a: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800674e: f003 0304 and.w r3, r3, #4 + 8006752: 2b00 cmp r3, #0 + 8006754: d01e beq.n 8006794 + !(netif->flags & NETIF_FLAG_UP)) { + 8006756: 687b ldr r3, [r7, #4] + 8006758: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800675c: f003 0301 and.w r3, r3, #1 + if (!(netif->flags & NETIF_FLAG_LINK_UP) || + 8006760: 2b00 cmp r3, #0 + 8006762: d017 beq.n 8006794 + return; + } + +#if LWIP_IPV4 + if ((report_type & NETIF_REPORT_TYPE_IPV4) && + 8006764: 78fb ldrb r3, [r7, #3] + 8006766: f003 0301 and.w r3, r3, #1 + 800676a: 2b00 cmp r3, #0 + 800676c: d013 beq.n 8006796 + !ip4_addr_isany_val(*netif_ip4_addr(netif))) { + 800676e: 687b ldr r3, [r7, #4] + 8006770: 3304 adds r3, #4 + 8006772: 681b ldr r3, [r3, #0] + if ((report_type & NETIF_REPORT_TYPE_IPV4) && + 8006774: 2b00 cmp r3, #0 + 8006776: d00e beq.n 8006796 +#if LWIP_ARP + /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ + if (netif->flags & (NETIF_FLAG_ETHARP)) { + 8006778: 687b ldr r3, [r7, #4] + 800677a: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800677e: f003 0308 and.w r3, r3, #8 + 8006782: 2b00 cmp r3, #0 + 8006784: d007 beq.n 8006796 + etharp_gratuitous(netif); + 8006786: 687b ldr r3, [r7, #4] + 8006788: 3304 adds r3, #4 + 800678a: 4619 mov r1, r3 + 800678c: 6878 ldr r0, [r7, #4] + 800678e: f008 f91f bl 800e9d0 + 8006792: e000 b.n 8006796 + return; + 8006794: bf00 nop + /* send mld memberships */ + mld6_report_groups(netif); +#endif /* LWIP_IPV6_MLD */ + } +#endif /* LWIP_IPV6 */ +} + 8006796: 3708 adds r7, #8 + 8006798: 46bd mov sp, r7 + 800679a: bd80 pop {r7, pc} + 800679c: 08012168 .word 0x08012168 + 80067a0: 08012444 .word 0x08012444 + 80067a4: 080121b8 .word 0x080121b8 + +080067a8 : + * @ingroup netif + * Bring an interface down, disabling any traffic processing. + */ +void +netif_set_down(struct netif *netif) +{ + 80067a8: b580 push {r7, lr} + 80067aa: b082 sub sp, #8 + 80067ac: af00 add r7, sp, #0 + 80067ae: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return); + 80067b0: 687b ldr r3, [r7, #4] + 80067b2: 2b00 cmp r3, #0 + 80067b4: d107 bne.n 80067c6 + 80067b6: 4b12 ldr r3, [pc, #72] ; (8006800 ) + 80067b8: f240 329b movw r2, #923 ; 0x39b + 80067bc: 4911 ldr r1, [pc, #68] ; (8006804 ) + 80067be: 4812 ldr r0, [pc, #72] ; (8006808 ) + 80067c0: f00a fa02 bl 8010bc8 + 80067c4: e019 b.n 80067fa + + if (netif->flags & NETIF_FLAG_UP) { + 80067c6: 687b ldr r3, [r7, #4] + 80067c8: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 80067cc: f003 0301 and.w r3, r3, #1 + 80067d0: 2b00 cmp r3, #0 + 80067d2: d012 beq.n 80067fa + args.status_changed.state = 0; + netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); + } +#endif + + netif_clear_flags(netif, NETIF_FLAG_UP); + 80067d4: 687b ldr r3, [r7, #4] + 80067d6: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 80067da: f023 0301 bic.w r3, r3, #1 + 80067de: b2da uxtb r2, r3 + 80067e0: 687b ldr r3, [r7, #4] + 80067e2: f883 202d strb.w r2, [r3, #45] ; 0x2d + MIB2_COPY_SYSUPTIME_TO(&netif->ts); + +#if LWIP_IPV4 && LWIP_ARP + if (netif->flags & NETIF_FLAG_ETHARP) { + 80067e6: 687b ldr r3, [r7, #4] + 80067e8: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 80067ec: f003 0308 and.w r3, r3, #8 + 80067f0: 2b00 cmp r3, #0 + 80067f2: d002 beq.n 80067fa + etharp_cleanup_netif(netif); + 80067f4: 6878 ldr r0, [r7, #4] + 80067f6: f007 fca9 bl 800e14c + nd6_cleanup_netif(netif); +#endif /* LWIP_IPV6 */ + + NETIF_STATUS_CALLBACK(netif); + } +} + 80067fa: 3708 adds r7, #8 + 80067fc: 46bd mov sp, r7 + 80067fe: bd80 pop {r7, pc} + 8006800: 08012168 .word 0x08012168 + 8006804: 08012468 .word 0x08012468 + 8006808: 080121b8 .word 0x080121b8 + +0800680c : + * @ingroup netif + * Called by a driver when its link goes up + */ +void +netif_set_link_up(struct netif *netif) +{ + 800680c: b580 push {r7, lr} + 800680e: b082 sub sp, #8 + 8006810: af00 add r7, sp, #0 + 8006812: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return); + 8006814: 687b ldr r3, [r7, #4] + 8006816: 2b00 cmp r3, #0 + 8006818: d107 bne.n 800682a + 800681a: 4b13 ldr r3, [pc, #76] ; (8006868 ) + 800681c: f44f 7278 mov.w r2, #992 ; 0x3e0 + 8006820: 4912 ldr r1, [pc, #72] ; (800686c ) + 8006822: 4813 ldr r0, [pc, #76] ; (8006870 ) + 8006824: f00a f9d0 bl 8010bc8 + 8006828: e01b b.n 8006862 + + if (!(netif->flags & NETIF_FLAG_LINK_UP)) { + 800682a: 687b ldr r3, [r7, #4] + 800682c: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8006830: f003 0304 and.w r3, r3, #4 + 8006834: 2b00 cmp r3, #0 + 8006836: d114 bne.n 8006862 + netif_set_flags(netif, NETIF_FLAG_LINK_UP); + 8006838: 687b ldr r3, [r7, #4] + 800683a: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800683e: f043 0304 orr.w r3, r3, #4 + 8006842: b2da uxtb r2, r3 + 8006844: 687b ldr r3, [r7, #4] + 8006846: f883 202d strb.w r2, [r3, #45] ; 0x2d + +#if LWIP_AUTOIP + autoip_network_changed(netif); +#endif /* LWIP_AUTOIP */ + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); + 800684a: 2103 movs r1, #3 + 800684c: 6878 ldr r0, [r7, #4] + 800684e: f7ff ff6b bl 8006728 +#if LWIP_IPV6 + nd6_restart_netif(netif); +#endif /* LWIP_IPV6 */ + + NETIF_LINK_CALLBACK(netif); + 8006852: 687b ldr r3, [r7, #4] + 8006854: 69db ldr r3, [r3, #28] + 8006856: 2b00 cmp r3, #0 + 8006858: d003 beq.n 8006862 + 800685a: 687b ldr r3, [r7, #4] + 800685c: 69db ldr r3, [r3, #28] + 800685e: 6878 ldr r0, [r7, #4] + 8006860: 4798 blx r3 + args.link_changed.state = 1; + netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); + } +#endif + } +} + 8006862: 3708 adds r7, #8 + 8006864: 46bd mov sp, r7 + 8006866: bd80 pop {r7, pc} + 8006868: 08012168 .word 0x08012168 + 800686c: 08012488 .word 0x08012488 + 8006870: 080121b8 .word 0x080121b8 + +08006874 : + * @ingroup netif + * Called by a driver when its link goes down + */ +void +netif_set_link_down(struct netif *netif) +{ + 8006874: b580 push {r7, lr} + 8006876: b082 sub sp, #8 + 8006878: af00 add r7, sp, #0 + 800687a: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return); + 800687c: 687b ldr r3, [r7, #4] + 800687e: 2b00 cmp r3, #0 + 8006880: d107 bne.n 8006892 + 8006882: 4b11 ldr r3, [pc, #68] ; (80068c8 ) + 8006884: f240 4206 movw r2, #1030 ; 0x406 + 8006888: 4910 ldr r1, [pc, #64] ; (80068cc ) + 800688a: 4811 ldr r0, [pc, #68] ; (80068d0 ) + 800688c: f00a f99c bl 8010bc8 + 8006890: e017 b.n 80068c2 + + if (netif->flags & NETIF_FLAG_LINK_UP) { + 8006892: 687b ldr r3, [r7, #4] + 8006894: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8006898: f003 0304 and.w r3, r3, #4 + 800689c: 2b00 cmp r3, #0 + 800689e: d010 beq.n 80068c2 + netif_clear_flags(netif, NETIF_FLAG_LINK_UP); + 80068a0: 687b ldr r3, [r7, #4] + 80068a2: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 80068a6: f023 0304 bic.w r3, r3, #4 + 80068aa: b2da uxtb r2, r3 + 80068ac: 687b ldr r3, [r7, #4] + 80068ae: f883 202d strb.w r2, [r3, #45] ; 0x2d + NETIF_LINK_CALLBACK(netif); + 80068b2: 687b ldr r3, [r7, #4] + 80068b4: 69db ldr r3, [r3, #28] + 80068b6: 2b00 cmp r3, #0 + 80068b8: d003 beq.n 80068c2 + 80068ba: 687b ldr r3, [r7, #4] + 80068bc: 69db ldr r3, [r3, #28] + 80068be: 6878 ldr r0, [r7, #4] + 80068c0: 4798 blx r3 + args.link_changed.state = 0; + netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); + } +#endif + } +} + 80068c2: 3708 adds r7, #8 + 80068c4: 46bd mov sp, r7 + 80068c6: bd80 pop {r7, pc} + 80068c8: 08012168 .word 0x08012168 + 80068cc: 080124ac .word 0x080124ac + 80068d0: 080121b8 .word 0x080121b8 + +080068d4 : + * @ingroup netif + * Set callback to be called when link is brought up/down + */ +void +netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback) +{ + 80068d4: b480 push {r7} + 80068d6: b083 sub sp, #12 + 80068d8: af00 add r7, sp, #0 + 80068da: 6078 str r0, [r7, #4] + 80068dc: 6039 str r1, [r7, #0] + LWIP_ASSERT_CORE_LOCKED(); + + if (netif) { + 80068de: 687b ldr r3, [r7, #4] + 80068e0: 2b00 cmp r3, #0 + 80068e2: d002 beq.n 80068ea + netif->link_callback = link_callback; + 80068e4: 687b ldr r3, [r7, #4] + 80068e6: 683a ldr r2, [r7, #0] + 80068e8: 61da str r2, [r3, #28] + } +} + 80068ea: bf00 nop + 80068ec: 370c adds r7, #12 + 80068ee: 46bd mov sp, r7 + 80068f0: f85d 7b04 ldr.w r7, [sp], #4 + 80068f4: 4770 bx lr + +080068f6 : +#if LWIP_IPV4 +/** Dummy IPv4 output function for netifs not supporting IPv4 + */ +static err_t +netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr) +{ + 80068f6: b480 push {r7} + 80068f8: b085 sub sp, #20 + 80068fa: af00 add r7, sp, #0 + 80068fc: 60f8 str r0, [r7, #12] + 80068fe: 60b9 str r1, [r7, #8] + 8006900: 607a str r2, [r7, #4] + LWIP_UNUSED_ARG(netif); + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(ipaddr); + + return ERR_IF; + 8006902: f06f 030b mvn.w r3, #11 +} + 8006906: 4618 mov r0, r3 + 8006908: 3714 adds r7, #20 + 800690a: 46bd mov sp, r7 + 800690c: f85d 7b04 ldr.w r7, [sp], #4 + 8006910: 4770 bx lr + ... + +08006914 : +* +* @param idx index of netif to find +*/ +struct netif * +netif_get_by_index(u8_t idx) +{ + 8006914: b480 push {r7} + 8006916: b085 sub sp, #20 + 8006918: af00 add r7, sp, #0 + 800691a: 4603 mov r3, r0 + 800691c: 71fb strb r3, [r7, #7] + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + + if (idx != NETIF_NO_INDEX) { + 800691e: 79fb ldrb r3, [r7, #7] + 8006920: 2b00 cmp r3, #0 + 8006922: d013 beq.n 800694c + NETIF_FOREACH(netif) { + 8006924: 4b0d ldr r3, [pc, #52] ; (800695c ) + 8006926: 681b ldr r3, [r3, #0] + 8006928: 60fb str r3, [r7, #12] + 800692a: e00c b.n 8006946 + if (idx == netif_get_index(netif)) { + 800692c: 68fb ldr r3, [r7, #12] + 800692e: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 8006932: 3301 adds r3, #1 + 8006934: b2db uxtb r3, r3 + 8006936: 79fa ldrb r2, [r7, #7] + 8006938: 429a cmp r2, r3 + 800693a: d101 bne.n 8006940 + return netif; /* found! */ + 800693c: 68fb ldr r3, [r7, #12] + 800693e: e006 b.n 800694e + NETIF_FOREACH(netif) { + 8006940: 68fb ldr r3, [r7, #12] + 8006942: 681b ldr r3, [r3, #0] + 8006944: 60fb str r3, [r7, #12] + 8006946: 68fb ldr r3, [r7, #12] + 8006948: 2b00 cmp r3, #0 + 800694a: d1ef bne.n 800692c + } + } + } + + return NULL; + 800694c: 2300 movs r3, #0 +} + 800694e: 4618 mov r0, r3 + 8006950: 3714 adds r7, #20 + 8006952: 46bd mov sp, r7 + 8006954: f85d 7b04 ldr.w r7, [sp], #4 + 8006958: 4770 bx lr + 800695a: bf00 nop + 800695c: 24007b60 .word 0x24007b60 + +08006960 : +#if !NO_SYS +static +#endif /* !NO_SYS */ +void +pbuf_free_ooseq(void) +{ + 8006960: b580 push {r7, lr} + 8006962: b082 sub sp, #8 + 8006964: af00 add r7, sp, #0 + struct tcp_pcb *pcb; + SYS_ARCH_SET(pbuf_free_ooseq_pending, 0); + 8006966: 4b0c ldr r3, [pc, #48] ; (8006998 ) + 8006968: 2200 movs r2, #0 + 800696a: 701a strb r2, [r3, #0] + + for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { + 800696c: 4b0b ldr r3, [pc, #44] ; (800699c ) + 800696e: 681b ldr r3, [r3, #0] + 8006970: 607b str r3, [r7, #4] + 8006972: e00a b.n 800698a + if (pcb->ooseq != NULL) { + 8006974: 687b ldr r3, [r7, #4] + 8006976: 6f5b ldr r3, [r3, #116] ; 0x74 + 8006978: 2b00 cmp r3, #0 + 800697a: d003 beq.n 8006984 + /** Free the ooseq pbufs of one PCB only */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); + tcp_free_ooseq(pcb); + 800697c: 6878 ldr r0, [r7, #4] + 800697e: f002 fb21 bl 8008fc4 + return; + 8006982: e005 b.n 8006990 + for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { + 8006984: 687b ldr r3, [r7, #4] + 8006986: 68db ldr r3, [r3, #12] + 8006988: 607b str r3, [r7, #4] + 800698a: 687b ldr r3, [r7, #4] + 800698c: 2b00 cmp r3, #0 + 800698e: d1f1 bne.n 8006974 + } + } +} + 8006990: 3708 adds r7, #8 + 8006992: 46bd mov sp, r7 + 8006994: bd80 pop {r7, pc} + 8006996: bf00 nop + 8006998: 24007b69 .word 0x24007b69 + 800699c: 24007b78 .word 0x24007b78 + +080069a0 : +#endif /* !NO_SYS */ + +/** Queue a call to pbuf_free_ooseq if not already queued. */ +static void +pbuf_pool_is_empty(void) +{ + 80069a0: b480 push {r7} + 80069a2: af00 add r7, sp, #0 +#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL + SYS_ARCH_SET(pbuf_free_ooseq_pending, 1); + 80069a4: 4b03 ldr r3, [pc, #12] ; (80069b4 ) + 80069a6: 2201 movs r2, #1 + 80069a8: 701a strb r2, [r3, #0] + if (!queued) { + /* queue a call to pbuf_free_ooseq if not already queued */ + PBUF_POOL_FREE_OOSEQ_QUEUE_CALL(); + } +#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ +} + 80069aa: bf00 nop + 80069ac: 46bd mov sp, r7 + 80069ae: f85d 7b04 ldr.w r7, [sp], #4 + 80069b2: 4770 bx lr + 80069b4: 24007b69 .word 0x24007b69 + +080069b8 : +#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */ + +/* Initialize members of struct pbuf after allocation */ +static void +pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags) +{ + 80069b8: b480 push {r7} + 80069ba: b085 sub sp, #20 + 80069bc: af00 add r7, sp, #0 + 80069be: 60f8 str r0, [r7, #12] + 80069c0: 60b9 str r1, [r7, #8] + 80069c2: 4611 mov r1, r2 + 80069c4: 461a mov r2, r3 + 80069c6: 460b mov r3, r1 + 80069c8: 80fb strh r3, [r7, #6] + 80069ca: 4613 mov r3, r2 + 80069cc: 80bb strh r3, [r7, #4] + p->next = NULL; + 80069ce: 68fb ldr r3, [r7, #12] + 80069d0: 2200 movs r2, #0 + 80069d2: 601a str r2, [r3, #0] + p->payload = payload; + 80069d4: 68fb ldr r3, [r7, #12] + 80069d6: 68ba ldr r2, [r7, #8] + 80069d8: 605a str r2, [r3, #4] + p->tot_len = tot_len; + 80069da: 68fb ldr r3, [r7, #12] + 80069dc: 88fa ldrh r2, [r7, #6] + 80069de: 811a strh r2, [r3, #8] + p->len = len; + 80069e0: 68fb ldr r3, [r7, #12] + 80069e2: 88ba ldrh r2, [r7, #4] + 80069e4: 815a strh r2, [r3, #10] + p->type_internal = (u8_t)type; + 80069e6: 8b3b ldrh r3, [r7, #24] + 80069e8: b2da uxtb r2, r3 + 80069ea: 68fb ldr r3, [r7, #12] + 80069ec: 731a strb r2, [r3, #12] + p->flags = flags; + 80069ee: 68fb ldr r3, [r7, #12] + 80069f0: 7f3a ldrb r2, [r7, #28] + 80069f2: 735a strb r2, [r3, #13] + p->ref = 1; + 80069f4: 68fb ldr r3, [r7, #12] + 80069f6: 2201 movs r2, #1 + 80069f8: 739a strb r2, [r3, #14] + p->if_idx = NETIF_NO_INDEX; + 80069fa: 68fb ldr r3, [r7, #12] + 80069fc: 2200 movs r2, #0 + 80069fe: 73da strb r2, [r3, #15] +} + 8006a00: bf00 nop + 8006a02: 3714 adds r7, #20 + 8006a04: 46bd mov sp, r7 + 8006a06: f85d 7b04 ldr.w r7, [sp], #4 + 8006a0a: 4770 bx lr + +08006a0c : + * @return the allocated pbuf. If multiple pbufs where allocated, this + * is the first pbuf of a pbuf chain. + */ +struct pbuf * +pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) +{ + 8006a0c: b580 push {r7, lr} + 8006a0e: b08c sub sp, #48 ; 0x30 + 8006a10: af02 add r7, sp, #8 + 8006a12: 4603 mov r3, r0 + 8006a14: 71fb strb r3, [r7, #7] + 8006a16: 460b mov r3, r1 + 8006a18: 80bb strh r3, [r7, #4] + 8006a1a: 4613 mov r3, r2 + 8006a1c: 807b strh r3, [r7, #2] + struct pbuf *p; + u16_t offset = (u16_t)layer; + 8006a1e: 79fb ldrb r3, [r7, #7] + 8006a20: 847b strh r3, [r7, #34] ; 0x22 + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); + + switch (type) { + 8006a22: 887b ldrh r3, [r7, #2] + 8006a24: f5b3 7f20 cmp.w r3, #640 ; 0x280 + 8006a28: d07f beq.n 8006b2a + 8006a2a: f5b3 7f20 cmp.w r3, #640 ; 0x280 + 8006a2e: f300 80c8 bgt.w 8006bc2 + 8006a32: f5b3 7fc1 cmp.w r3, #386 ; 0x182 + 8006a36: d010 beq.n 8006a5a + 8006a38: f5b3 7fc1 cmp.w r3, #386 ; 0x182 + 8006a3c: f300 80c1 bgt.w 8006bc2 + 8006a40: 2b01 cmp r3, #1 + 8006a42: d002 beq.n 8006a4a + 8006a44: 2b41 cmp r3, #65 ; 0x41 + 8006a46: f040 80bc bne.w 8006bc2 + case PBUF_REF: /* fall through */ + case PBUF_ROM: + p = pbuf_alloc_reference(NULL, length, type); + 8006a4a: 887a ldrh r2, [r7, #2] + 8006a4c: 88bb ldrh r3, [r7, #4] + 8006a4e: 4619 mov r1, r3 + 8006a50: 2000 movs r0, #0 + 8006a52: f000 f8d1 bl 8006bf8 + 8006a56: 6278 str r0, [r7, #36] ; 0x24 + break; + 8006a58: e0bd b.n 8006bd6 + case PBUF_POOL: { + struct pbuf *q, *last; + u16_t rem_len; /* remaining length */ + p = NULL; + 8006a5a: 2300 movs r3, #0 + 8006a5c: 627b str r3, [r7, #36] ; 0x24 + last = NULL; + 8006a5e: 2300 movs r3, #0 + 8006a60: 61fb str r3, [r7, #28] + rem_len = length; + 8006a62: 88bb ldrh r3, [r7, #4] + 8006a64: 837b strh r3, [r7, #26] + do { + u16_t qlen; + q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); + 8006a66: 2008 movs r0, #8 + 8006a68: f7ff fad8 bl 800601c + 8006a6c: 6138 str r0, [r7, #16] + if (q == NULL) { + 8006a6e: 693b ldr r3, [r7, #16] + 8006a70: 2b00 cmp r3, #0 + 8006a72: d109 bne.n 8006a88 + PBUF_POOL_IS_EMPTY(); + 8006a74: f7ff ff94 bl 80069a0 + /* free chain so far allocated */ + if (p) { + 8006a78: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006a7a: 2b00 cmp r3, #0 + 8006a7c: d002 beq.n 8006a84 + pbuf_free(p); + 8006a7e: 6a78 ldr r0, [r7, #36] ; 0x24 + 8006a80: f000 faa8 bl 8006fd4 + } + /* bail out unsuccessfully */ + return NULL; + 8006a84: 2300 movs r3, #0 + 8006a86: e0a7 b.n 8006bd8 + } + qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset))); + 8006a88: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8006a8a: 3303 adds r3, #3 + 8006a8c: b29b uxth r3, r3 + 8006a8e: f023 0303 bic.w r3, r3, #3 + 8006a92: b29b uxth r3, r3 + 8006a94: f5c3 7314 rsb r3, r3, #592 ; 0x250 + 8006a98: b29b uxth r3, r3 + 8006a9a: 8b7a ldrh r2, [r7, #26] + 8006a9c: 4293 cmp r3, r2 + 8006a9e: bf28 it cs + 8006aa0: 4613 movcs r3, r2 + 8006aa2: 81fb strh r3, [r7, #14] + pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)), + 8006aa4: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8006aa6: 3310 adds r3, #16 + 8006aa8: 693a ldr r2, [r7, #16] + 8006aaa: 4413 add r3, r2 + 8006aac: 3303 adds r3, #3 + 8006aae: f023 0303 bic.w r3, r3, #3 + 8006ab2: 4618 mov r0, r3 + 8006ab4: 89f9 ldrh r1, [r7, #14] + 8006ab6: 8b7a ldrh r2, [r7, #26] + 8006ab8: 2300 movs r3, #0 + 8006aba: 9301 str r3, [sp, #4] + 8006abc: 887b ldrh r3, [r7, #2] + 8006abe: 9300 str r3, [sp, #0] + 8006ac0: 460b mov r3, r1 + 8006ac2: 4601 mov r1, r0 + 8006ac4: 6938 ldr r0, [r7, #16] + 8006ac6: f7ff ff77 bl 80069b8 + rem_len, qlen, type, 0); + LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", + 8006aca: 693b ldr r3, [r7, #16] + 8006acc: 685b ldr r3, [r3, #4] + 8006ace: f003 0303 and.w r3, r3, #3 + 8006ad2: 2b00 cmp r3, #0 + 8006ad4: d006 beq.n 8006ae4 + 8006ad6: 4b42 ldr r3, [pc, #264] ; (8006be0 ) + 8006ad8: f44f 7280 mov.w r2, #256 ; 0x100 + 8006adc: 4941 ldr r1, [pc, #260] ; (8006be4 ) + 8006ade: 4842 ldr r0, [pc, #264] ; (8006be8 ) + 8006ae0: f00a f872 bl 8010bc8 + ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); + LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", + 8006ae4: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8006ae6: 3303 adds r3, #3 + 8006ae8: f023 0303 bic.w r3, r3, #3 + 8006aec: f5b3 7f14 cmp.w r3, #592 ; 0x250 + 8006af0: d106 bne.n 8006b00 + 8006af2: 4b3b ldr r3, [pc, #236] ; (8006be0 ) + 8006af4: f44f 7281 mov.w r2, #258 ; 0x102 + 8006af8: 493c ldr r1, [pc, #240] ; (8006bec ) + 8006afa: 483b ldr r0, [pc, #236] ; (8006be8 ) + 8006afc: f00a f864 bl 8010bc8 + (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); + if (p == NULL) { + 8006b00: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006b02: 2b00 cmp r3, #0 + 8006b04: d102 bne.n 8006b0c + /* allocated head of pbuf chain (into p) */ + p = q; + 8006b06: 693b ldr r3, [r7, #16] + 8006b08: 627b str r3, [r7, #36] ; 0x24 + 8006b0a: e002 b.n 8006b12 + } else { + /* make previous pbuf point to this pbuf */ + last->next = q; + 8006b0c: 69fb ldr r3, [r7, #28] + 8006b0e: 693a ldr r2, [r7, #16] + 8006b10: 601a str r2, [r3, #0] + } + last = q; + 8006b12: 693b ldr r3, [r7, #16] + 8006b14: 61fb str r3, [r7, #28] + rem_len = (u16_t)(rem_len - qlen); + 8006b16: 8b7a ldrh r2, [r7, #26] + 8006b18: 89fb ldrh r3, [r7, #14] + 8006b1a: 1ad3 subs r3, r2, r3 + 8006b1c: 837b strh r3, [r7, #26] + offset = 0; + 8006b1e: 2300 movs r3, #0 + 8006b20: 847b strh r3, [r7, #34] ; 0x22 + } while (rem_len > 0); + 8006b22: 8b7b ldrh r3, [r7, #26] + 8006b24: 2b00 cmp r3, #0 + 8006b26: d19e bne.n 8006a66 + break; + 8006b28: e055 b.n 8006bd6 + } + case PBUF_RAM: { + u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length)); + 8006b2a: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8006b2c: 3303 adds r3, #3 + 8006b2e: b29b uxth r3, r3 + 8006b30: f023 0303 bic.w r3, r3, #3 + 8006b34: b29a uxth r2, r3 + 8006b36: 88bb ldrh r3, [r7, #4] + 8006b38: 3303 adds r3, #3 + 8006b3a: b29b uxth r3, r3 + 8006b3c: f023 0303 bic.w r3, r3, #3 + 8006b40: b29b uxth r3, r3 + 8006b42: 4413 add r3, r2 + 8006b44: 833b strh r3, [r7, #24] + mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len); + 8006b46: 8b3b ldrh r3, [r7, #24] + 8006b48: 3310 adds r3, #16 + 8006b4a: 82fb strh r3, [r7, #22] + + /* bug #50040: Check for integer overflow when calculating alloc_len */ + if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) || + 8006b4c: 8b3a ldrh r2, [r7, #24] + 8006b4e: 88bb ldrh r3, [r7, #4] + 8006b50: 3303 adds r3, #3 + 8006b52: f023 0303 bic.w r3, r3, #3 + 8006b56: 429a cmp r2, r3 + 8006b58: d306 bcc.n 8006b68 + (alloc_len < LWIP_MEM_ALIGN_SIZE(length))) { + 8006b5a: 8afa ldrh r2, [r7, #22] + 8006b5c: 88bb ldrh r3, [r7, #4] + 8006b5e: 3303 adds r3, #3 + 8006b60: f023 0303 bic.w r3, r3, #3 + if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) || + 8006b64: 429a cmp r2, r3 + 8006b66: d201 bcs.n 8006b6c + return NULL; + 8006b68: 2300 movs r3, #0 + 8006b6a: e035 b.n 8006bd8 + } + + /* If pbuf is to be allocated in RAM, allocate memory for it. */ + p = (struct pbuf *)mem_malloc(alloc_len); + 8006b6c: 8afb ldrh r3, [r7, #22] + 8006b6e: 4618 mov r0, r3 + 8006b70: f7ff f8b0 bl 8005cd4 + 8006b74: 6278 str r0, [r7, #36] ; 0x24 + if (p == NULL) { + 8006b76: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006b78: 2b00 cmp r3, #0 + 8006b7a: d101 bne.n 8006b80 + return NULL; + 8006b7c: 2300 movs r3, #0 + 8006b7e: e02b b.n 8006bd8 + } + pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)), + 8006b80: 8c7b ldrh r3, [r7, #34] ; 0x22 + 8006b82: 3310 adds r3, #16 + 8006b84: 6a7a ldr r2, [r7, #36] ; 0x24 + 8006b86: 4413 add r3, r2 + 8006b88: 3303 adds r3, #3 + 8006b8a: f023 0303 bic.w r3, r3, #3 + 8006b8e: 4618 mov r0, r3 + 8006b90: 88b9 ldrh r1, [r7, #4] + 8006b92: 88ba ldrh r2, [r7, #4] + 8006b94: 2300 movs r3, #0 + 8006b96: 9301 str r3, [sp, #4] + 8006b98: 887b ldrh r3, [r7, #2] + 8006b9a: 9300 str r3, [sp, #0] + 8006b9c: 460b mov r3, r1 + 8006b9e: 4601 mov r1, r0 + 8006ba0: 6a78 ldr r0, [r7, #36] ; 0x24 + 8006ba2: f7ff ff09 bl 80069b8 + length, length, type, 0); + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + 8006ba6: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006ba8: 685b ldr r3, [r3, #4] + 8006baa: f003 0303 and.w r3, r3, #3 + 8006bae: 2b00 cmp r3, #0 + 8006bb0: d010 beq.n 8006bd4 + 8006bb2: 4b0b ldr r3, [pc, #44] ; (8006be0 ) + 8006bb4: f44f 7291 mov.w r2, #290 ; 0x122 + 8006bb8: 490d ldr r1, [pc, #52] ; (8006bf0 ) + 8006bba: 480b ldr r0, [pc, #44] ; (8006be8 ) + 8006bbc: f00a f804 bl 8010bc8 + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; + 8006bc0: e008 b.n 8006bd4 + } + default: + LWIP_ASSERT("pbuf_alloc: erroneous type", 0); + 8006bc2: 4b07 ldr r3, [pc, #28] ; (8006be0 ) + 8006bc4: f240 1227 movw r2, #295 ; 0x127 + 8006bc8: 490a ldr r1, [pc, #40] ; (8006bf4 ) + 8006bca: 4807 ldr r0, [pc, #28] ; (8006be8 ) + 8006bcc: f009 fffc bl 8010bc8 + return NULL; + 8006bd0: 2300 movs r3, #0 + 8006bd2: e001 b.n 8006bd8 + break; + 8006bd4: bf00 nop + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); + return p; + 8006bd6: 6a7b ldr r3, [r7, #36] ; 0x24 +} + 8006bd8: 4618 mov r0, r3 + 8006bda: 3728 adds r7, #40 ; 0x28 + 8006bdc: 46bd mov sp, r7 + 8006bde: bd80 pop {r7, pc} + 8006be0: 08012508 .word 0x08012508 + 8006be4: 08012538 .word 0x08012538 + 8006be8: 08012568 .word 0x08012568 + 8006bec: 08012590 .word 0x08012590 + 8006bf0: 080125c4 .word 0x080125c4 + 8006bf4: 080125f0 .word 0x080125f0 + +08006bf8 : + * + * @return the allocated pbuf. + */ +struct pbuf * +pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type) +{ + 8006bf8: b580 push {r7, lr} + 8006bfa: b086 sub sp, #24 + 8006bfc: af02 add r7, sp, #8 + 8006bfe: 6078 str r0, [r7, #4] + 8006c00: 460b mov r3, r1 + 8006c02: 807b strh r3, [r7, #2] + 8006c04: 4613 mov r3, r2 + 8006c06: 803b strh r3, [r7, #0] + struct pbuf *p; + LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM)); + 8006c08: 883b ldrh r3, [r7, #0] + 8006c0a: 2b41 cmp r3, #65 ; 0x41 + 8006c0c: d009 beq.n 8006c22 + 8006c0e: 883b ldrh r3, [r7, #0] + 8006c10: 2b01 cmp r3, #1 + 8006c12: d006 beq.n 8006c22 + 8006c14: 4b0f ldr r3, [pc, #60] ; (8006c54 ) + 8006c16: f44f 72a5 mov.w r2, #330 ; 0x14a + 8006c1a: 490f ldr r1, [pc, #60] ; (8006c58 ) + 8006c1c: 480f ldr r0, [pc, #60] ; (8006c5c ) + 8006c1e: f009 ffd3 bl 8010bc8 + /* only allocate memory for the pbuf structure */ + p = (struct pbuf *)memp_malloc(MEMP_PBUF); + 8006c22: 2007 movs r0, #7 + 8006c24: f7ff f9fa bl 800601c + 8006c28: 60f8 str r0, [r7, #12] + if (p == NULL) { + 8006c2a: 68fb ldr r3, [r7, #12] + 8006c2c: 2b00 cmp r3, #0 + 8006c2e: d101 bne.n 8006c34 + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n", + (type == PBUF_ROM) ? "ROM" : "REF")); + return NULL; + 8006c30: 2300 movs r3, #0 + 8006c32: e00b b.n 8006c4c + } + pbuf_init_alloced_pbuf(p, payload, length, length, type, 0); + 8006c34: 8879 ldrh r1, [r7, #2] + 8006c36: 887a ldrh r2, [r7, #2] + 8006c38: 2300 movs r3, #0 + 8006c3a: 9301 str r3, [sp, #4] + 8006c3c: 883b ldrh r3, [r7, #0] + 8006c3e: 9300 str r3, [sp, #0] + 8006c40: 460b mov r3, r1 + 8006c42: 6879 ldr r1, [r7, #4] + 8006c44: 68f8 ldr r0, [r7, #12] + 8006c46: f7ff feb7 bl 80069b8 + return p; + 8006c4a: 68fb ldr r3, [r7, #12] +} + 8006c4c: 4618 mov r0, r3 + 8006c4e: 3710 adds r7, #16 + 8006c50: 46bd mov sp, r7 + 8006c52: bd80 pop {r7, pc} + 8006c54: 08012508 .word 0x08012508 + 8006c58: 0801260c .word 0x0801260c + 8006c5c: 08012568 .word 0x08012568 + +08006c60 : + * big enough to hold 'length' plus the header size + */ +struct pbuf * +pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p, + void *payload_mem, u16_t payload_mem_len) +{ + 8006c60: b580 push {r7, lr} + 8006c62: b088 sub sp, #32 + 8006c64: af02 add r7, sp, #8 + 8006c66: 607b str r3, [r7, #4] + 8006c68: 4603 mov r3, r0 + 8006c6a: 73fb strb r3, [r7, #15] + 8006c6c: 460b mov r3, r1 + 8006c6e: 81bb strh r3, [r7, #12] + 8006c70: 4613 mov r3, r2 + 8006c72: 817b strh r3, [r7, #10] + u16_t offset = (u16_t)l; + 8006c74: 7bfb ldrb r3, [r7, #15] + 8006c76: 827b strh r3, [r7, #18] + void *payload; + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length)); + + if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) { + 8006c78: 8a7b ldrh r3, [r7, #18] + 8006c7a: 3303 adds r3, #3 + 8006c7c: f023 0203 bic.w r2, r3, #3 + 8006c80: 89bb ldrh r3, [r7, #12] + 8006c82: 441a add r2, r3 + 8006c84: 8cbb ldrh r3, [r7, #36] ; 0x24 + 8006c86: 429a cmp r2, r3 + 8006c88: d901 bls.n 8006c8e + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length)); + return NULL; + 8006c8a: 2300 movs r3, #0 + 8006c8c: e018 b.n 8006cc0 + } + + if (payload_mem != NULL) { + 8006c8e: 6a3b ldr r3, [r7, #32] + 8006c90: 2b00 cmp r3, #0 + 8006c92: d007 beq.n 8006ca4 + payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset); + 8006c94: 8a7b ldrh r3, [r7, #18] + 8006c96: 3303 adds r3, #3 + 8006c98: f023 0303 bic.w r3, r3, #3 + 8006c9c: 6a3a ldr r2, [r7, #32] + 8006c9e: 4413 add r3, r2 + 8006ca0: 617b str r3, [r7, #20] + 8006ca2: e001 b.n 8006ca8 + } else { + payload = NULL; + 8006ca4: 2300 movs r3, #0 + 8006ca6: 617b str r3, [r7, #20] + } + pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM); + 8006ca8: 6878 ldr r0, [r7, #4] + 8006caa: 89b9 ldrh r1, [r7, #12] + 8006cac: 89ba ldrh r2, [r7, #12] + 8006cae: 2302 movs r3, #2 + 8006cb0: 9301 str r3, [sp, #4] + 8006cb2: 897b ldrh r3, [r7, #10] + 8006cb4: 9300 str r3, [sp, #0] + 8006cb6: 460b mov r3, r1 + 8006cb8: 6979 ldr r1, [r7, #20] + 8006cba: f7ff fe7d bl 80069b8 + return &p->pbuf; + 8006cbe: 687b ldr r3, [r7, #4] +} + 8006cc0: 4618 mov r0, r3 + 8006cc2: 3718 adds r7, #24 + 8006cc4: 46bd mov sp, r7 + 8006cc6: bd80 pop {r7, pc} + +08006cc8 : + * + * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). + */ +void +pbuf_realloc(struct pbuf *p, u16_t new_len) +{ + 8006cc8: b580 push {r7, lr} + 8006cca: b084 sub sp, #16 + 8006ccc: af00 add r7, sp, #0 + 8006cce: 6078 str r0, [r7, #4] + 8006cd0: 460b mov r3, r1 + 8006cd2: 807b strh r3, [r7, #2] + struct pbuf *q; + u16_t rem_len; /* remaining length */ + u16_t shrink; + + LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); + 8006cd4: 687b ldr r3, [r7, #4] + 8006cd6: 2b00 cmp r3, #0 + 8006cd8: d106 bne.n 8006ce8 + 8006cda: 4b3a ldr r3, [pc, #232] ; (8006dc4 ) + 8006cdc: f44f 72cc mov.w r2, #408 ; 0x198 + 8006ce0: 4939 ldr r1, [pc, #228] ; (8006dc8 ) + 8006ce2: 483a ldr r0, [pc, #232] ; (8006dcc ) + 8006ce4: f009 ff70 bl 8010bc8 + + /* desired length larger than current length? */ + if (new_len >= p->tot_len) { + 8006ce8: 687b ldr r3, [r7, #4] + 8006cea: 891b ldrh r3, [r3, #8] + 8006cec: 887a ldrh r2, [r7, #2] + 8006cee: 429a cmp r2, r3 + 8006cf0: d263 bcs.n 8006dba + return; + } + + /* the pbuf chain grows by (new_len - p->tot_len) bytes + * (which may be negative in case of shrinking) */ + shrink = (u16_t)(p->tot_len - new_len); + 8006cf2: 687b ldr r3, [r7, #4] + 8006cf4: 891a ldrh r2, [r3, #8] + 8006cf6: 887b ldrh r3, [r7, #2] + 8006cf8: 1ad3 subs r3, r2, r3 + 8006cfa: 813b strh r3, [r7, #8] + + /* first, step over any pbufs that should remain in the chain */ + rem_len = new_len; + 8006cfc: 887b ldrh r3, [r7, #2] + 8006cfe: 817b strh r3, [r7, #10] + q = p; + 8006d00: 687b ldr r3, [r7, #4] + 8006d02: 60fb str r3, [r7, #12] + /* should this pbuf be kept? */ + while (rem_len > q->len) { + 8006d04: e018 b.n 8006d38 + /* decrease remaining length by pbuf length */ + rem_len = (u16_t)(rem_len - q->len); + 8006d06: 68fb ldr r3, [r7, #12] + 8006d08: 895b ldrh r3, [r3, #10] + 8006d0a: 897a ldrh r2, [r7, #10] + 8006d0c: 1ad3 subs r3, r2, r3 + 8006d0e: 817b strh r3, [r7, #10] + /* decrease total length indicator */ + q->tot_len = (u16_t)(q->tot_len - shrink); + 8006d10: 68fb ldr r3, [r7, #12] + 8006d12: 891a ldrh r2, [r3, #8] + 8006d14: 893b ldrh r3, [r7, #8] + 8006d16: 1ad3 subs r3, r2, r3 + 8006d18: b29a uxth r2, r3 + 8006d1a: 68fb ldr r3, [r7, #12] + 8006d1c: 811a strh r2, [r3, #8] + /* proceed to next pbuf in chain */ + q = q->next; + 8006d1e: 68fb ldr r3, [r7, #12] + 8006d20: 681b ldr r3, [r3, #0] + 8006d22: 60fb str r3, [r7, #12] + LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); + 8006d24: 68fb ldr r3, [r7, #12] + 8006d26: 2b00 cmp r3, #0 + 8006d28: d106 bne.n 8006d38 + 8006d2a: 4b26 ldr r3, [pc, #152] ; (8006dc4 ) + 8006d2c: f240 12af movw r2, #431 ; 0x1af + 8006d30: 4927 ldr r1, [pc, #156] ; (8006dd0 ) + 8006d32: 4826 ldr r0, [pc, #152] ; (8006dcc ) + 8006d34: f009 ff48 bl 8010bc8 + while (rem_len > q->len) { + 8006d38: 68fb ldr r3, [r7, #12] + 8006d3a: 895b ldrh r3, [r3, #10] + 8006d3c: 897a ldrh r2, [r7, #10] + 8006d3e: 429a cmp r2, r3 + 8006d40: d8e1 bhi.n 8006d06 + /* we have now reached the new last pbuf (in q) */ + /* rem_len == desired length for pbuf q */ + + /* shrink allocated memory for PBUF_RAM */ + /* (other types merely adjust their length fields */ + if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len) + 8006d42: 68fb ldr r3, [r7, #12] + 8006d44: 7b1b ldrb r3, [r3, #12] + 8006d46: f003 030f and.w r3, r3, #15 + 8006d4a: 2b00 cmp r3, #0 + 8006d4c: d121 bne.n 8006d92 + 8006d4e: 68fb ldr r3, [r7, #12] + 8006d50: 895b ldrh r3, [r3, #10] + 8006d52: 897a ldrh r2, [r7, #10] + 8006d54: 429a cmp r2, r3 + 8006d56: d01c beq.n 8006d92 +#if LWIP_SUPPORT_CUSTOM_PBUF + && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0) + 8006d58: 68fb ldr r3, [r7, #12] + 8006d5a: 7b5b ldrb r3, [r3, #13] + 8006d5c: f003 0302 and.w r3, r3, #2 + 8006d60: 2b00 cmp r3, #0 + 8006d62: d116 bne.n 8006d92 +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + ) { + /* reallocate and adjust the length of the pbuf that will be split */ + q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len)); + 8006d64: 68fb ldr r3, [r7, #12] + 8006d66: 685a ldr r2, [r3, #4] + 8006d68: 68fb ldr r3, [r7, #12] + 8006d6a: 1ad3 subs r3, r2, r3 + 8006d6c: b29a uxth r2, r3 + 8006d6e: 897b ldrh r3, [r7, #10] + 8006d70: 4413 add r3, r2 + 8006d72: b29b uxth r3, r3 + 8006d74: 4619 mov r1, r3 + 8006d76: 68f8 ldr r0, [r7, #12] + 8006d78: f7fe fea6 bl 8005ac8 + 8006d7c: 60f8 str r0, [r7, #12] + LWIP_ASSERT("mem_trim returned q == NULL", q != NULL); + 8006d7e: 68fb ldr r3, [r7, #12] + 8006d80: 2b00 cmp r3, #0 + 8006d82: d106 bne.n 8006d92 + 8006d84: 4b0f ldr r3, [pc, #60] ; (8006dc4 ) + 8006d86: f240 12bd movw r2, #445 ; 0x1bd + 8006d8a: 4912 ldr r1, [pc, #72] ; (8006dd4 ) + 8006d8c: 480f ldr r0, [pc, #60] ; (8006dcc ) + 8006d8e: f009 ff1b bl 8010bc8 + } + /* adjust length fields for new last pbuf */ + q->len = rem_len; + 8006d92: 68fb ldr r3, [r7, #12] + 8006d94: 897a ldrh r2, [r7, #10] + 8006d96: 815a strh r2, [r3, #10] + q->tot_len = q->len; + 8006d98: 68fb ldr r3, [r7, #12] + 8006d9a: 895a ldrh r2, [r3, #10] + 8006d9c: 68fb ldr r3, [r7, #12] + 8006d9e: 811a strh r2, [r3, #8] + + /* any remaining pbufs in chain? */ + if (q->next != NULL) { + 8006da0: 68fb ldr r3, [r7, #12] + 8006da2: 681b ldr r3, [r3, #0] + 8006da4: 2b00 cmp r3, #0 + 8006da6: d004 beq.n 8006db2 + /* free remaining pbufs in chain */ + pbuf_free(q->next); + 8006da8: 68fb ldr r3, [r7, #12] + 8006daa: 681b ldr r3, [r3, #0] + 8006dac: 4618 mov r0, r3 + 8006dae: f000 f911 bl 8006fd4 + } + /* q is last packet in chain */ + q->next = NULL; + 8006db2: 68fb ldr r3, [r7, #12] + 8006db4: 2200 movs r2, #0 + 8006db6: 601a str r2, [r3, #0] + 8006db8: e000 b.n 8006dbc + return; + 8006dba: bf00 nop + +} + 8006dbc: 3710 adds r7, #16 + 8006dbe: 46bd mov sp, r7 + 8006dc0: bd80 pop {r7, pc} + 8006dc2: bf00 nop + 8006dc4: 08012508 .word 0x08012508 + 8006dc8: 08012620 .word 0x08012620 + 8006dcc: 08012568 .word 0x08012568 + 8006dd0: 08012638 .word 0x08012638 + 8006dd4: 08012650 .word 0x08012650 + +08006dd8 : + * @return non-zero on failure, zero on success. + * + */ +static u8_t +pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force) +{ + 8006dd8: b580 push {r7, lr} + 8006dda: b086 sub sp, #24 + 8006ddc: af00 add r7, sp, #0 + 8006dde: 60f8 str r0, [r7, #12] + 8006de0: 60b9 str r1, [r7, #8] + 8006de2: 4613 mov r3, r2 + 8006de4: 71fb strb r3, [r7, #7] + u16_t type_internal; + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + 8006de6: 68fb ldr r3, [r7, #12] + 8006de8: 2b00 cmp r3, #0 + 8006dea: d106 bne.n 8006dfa + 8006dec: 4b2b ldr r3, [pc, #172] ; (8006e9c ) + 8006dee: f240 12df movw r2, #479 ; 0x1df + 8006df2: 492b ldr r1, [pc, #172] ; (8006ea0 ) + 8006df4: 482b ldr r0, [pc, #172] ; (8006ea4 ) + 8006df6: f009 fee7 bl 8010bc8 + if ((p == NULL) || (header_size_increment > 0xFFFF)) { + 8006dfa: 68fb ldr r3, [r7, #12] + 8006dfc: 2b00 cmp r3, #0 + 8006dfe: d003 beq.n 8006e08 + 8006e00: 68bb ldr r3, [r7, #8] + 8006e02: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8006e06: d301 bcc.n 8006e0c + return 1; + 8006e08: 2301 movs r3, #1 + 8006e0a: e043 b.n 8006e94 + } + if (header_size_increment == 0) { + 8006e0c: 68bb ldr r3, [r7, #8] + 8006e0e: 2b00 cmp r3, #0 + 8006e10: d101 bne.n 8006e16 + return 0; + 8006e12: 2300 movs r3, #0 + 8006e14: e03e b.n 8006e94 + } + + increment_magnitude = (u16_t)header_size_increment; + 8006e16: 68bb ldr r3, [r7, #8] + 8006e18: 827b strh r3, [r7, #18] + /* Do not allow tot_len to wrap as a result. */ + if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) { + 8006e1a: 68fb ldr r3, [r7, #12] + 8006e1c: 891a ldrh r2, [r3, #8] + 8006e1e: 8a7b ldrh r3, [r7, #18] + 8006e20: 4413 add r3, r2 + 8006e22: b29b uxth r3, r3 + 8006e24: 8a7a ldrh r2, [r7, #18] + 8006e26: 429a cmp r2, r3 + 8006e28: d901 bls.n 8006e2e + return 1; + 8006e2a: 2301 movs r3, #1 + 8006e2c: e032 b.n 8006e94 + } + + type_internal = p->type_internal; + 8006e2e: 68fb ldr r3, [r7, #12] + 8006e30: 7b1b ldrb r3, [r3, #12] + 8006e32: 823b strh r3, [r7, #16] + + /* pbuf types containing payloads? */ + if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) { + 8006e34: 8a3b ldrh r3, [r7, #16] + 8006e36: f003 0380 and.w r3, r3, #128 ; 0x80 + 8006e3a: 2b00 cmp r3, #0 + 8006e3c: d00c beq.n 8006e58 + /* set new payload pointer */ + payload = (u8_t *)p->payload - header_size_increment; + 8006e3e: 68fb ldr r3, [r7, #12] + 8006e40: 685a ldr r2, [r3, #4] + 8006e42: 68bb ldr r3, [r7, #8] + 8006e44: 425b negs r3, r3 + 8006e46: 4413 add r3, r2 + 8006e48: 617b str r3, [r7, #20] + /* boundary check fails? */ + if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { + 8006e4a: 68fb ldr r3, [r7, #12] + 8006e4c: 3310 adds r3, #16 + 8006e4e: 697a ldr r2, [r7, #20] + 8006e50: 429a cmp r2, r3 + 8006e52: d20d bcs.n 8006e70 + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, + ("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n", + (void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF))); + /* bail out unsuccessfully */ + return 1; + 8006e54: 2301 movs r3, #1 + 8006e56: e01d b.n 8006e94 + } + /* pbuf types referring to external payloads? */ + } else { + /* hide a header in the payload? */ + if (force) { + 8006e58: 79fb ldrb r3, [r7, #7] + 8006e5a: 2b00 cmp r3, #0 + 8006e5c: d006 beq.n 8006e6c + payload = (u8_t *)p->payload - header_size_increment; + 8006e5e: 68fb ldr r3, [r7, #12] + 8006e60: 685a ldr r2, [r3, #4] + 8006e62: 68bb ldr r3, [r7, #8] + 8006e64: 425b negs r3, r3 + 8006e66: 4413 add r3, r2 + 8006e68: 617b str r3, [r7, #20] + 8006e6a: e001 b.n 8006e70 + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccessfully */ + return 1; + 8006e6c: 2301 movs r3, #1 + 8006e6e: e011 b.n 8006e94 + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n", + (void *)p->payload, (void *)payload, increment_magnitude)); + + /* modify pbuf fields */ + p->payload = payload; + 8006e70: 68fb ldr r3, [r7, #12] + 8006e72: 697a ldr r2, [r7, #20] + 8006e74: 605a str r2, [r3, #4] + p->len = (u16_t)(p->len + increment_magnitude); + 8006e76: 68fb ldr r3, [r7, #12] + 8006e78: 895a ldrh r2, [r3, #10] + 8006e7a: 8a7b ldrh r3, [r7, #18] + 8006e7c: 4413 add r3, r2 + 8006e7e: b29a uxth r2, r3 + 8006e80: 68fb ldr r3, [r7, #12] + 8006e82: 815a strh r2, [r3, #10] + p->tot_len = (u16_t)(p->tot_len + increment_magnitude); + 8006e84: 68fb ldr r3, [r7, #12] + 8006e86: 891a ldrh r2, [r3, #8] + 8006e88: 8a7b ldrh r3, [r7, #18] + 8006e8a: 4413 add r3, r2 + 8006e8c: b29a uxth r2, r3 + 8006e8e: 68fb ldr r3, [r7, #12] + 8006e90: 811a strh r2, [r3, #8] + + + return 0; + 8006e92: 2300 movs r3, #0 +} + 8006e94: 4618 mov r0, r3 + 8006e96: 3718 adds r7, #24 + 8006e98: 46bd mov sp, r7 + 8006e9a: bd80 pop {r7, pc} + 8006e9c: 08012508 .word 0x08012508 + 8006ea0: 0801266c .word 0x0801266c + 8006ea4: 08012568 .word 0x08012568 + +08006ea8 : + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_add_header(struct pbuf *p, size_t header_size_increment) +{ + 8006ea8: b580 push {r7, lr} + 8006eaa: b082 sub sp, #8 + 8006eac: af00 add r7, sp, #0 + 8006eae: 6078 str r0, [r7, #4] + 8006eb0: 6039 str r1, [r7, #0] + return pbuf_add_header_impl(p, header_size_increment, 0); + 8006eb2: 2200 movs r2, #0 + 8006eb4: 6839 ldr r1, [r7, #0] + 8006eb6: 6878 ldr r0, [r7, #4] + 8006eb8: f7ff ff8e bl 8006dd8 + 8006ebc: 4603 mov r3, r0 +} + 8006ebe: 4618 mov r0, r3 + 8006ec0: 3708 adds r7, #8 + 8006ec2: 46bd mov sp, r7 + 8006ec4: bd80 pop {r7, pc} + ... + +08006ec8 : + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_remove_header(struct pbuf *p, size_t header_size_decrement) +{ + 8006ec8: b580 push {r7, lr} + 8006eca: b084 sub sp, #16 + 8006ecc: af00 add r7, sp, #0 + 8006ece: 6078 str r0, [r7, #4] + 8006ed0: 6039 str r1, [r7, #0] + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + 8006ed2: 687b ldr r3, [r7, #4] + 8006ed4: 2b00 cmp r3, #0 + 8006ed6: d106 bne.n 8006ee6 + 8006ed8: 4b20 ldr r3, [pc, #128] ; (8006f5c ) + 8006eda: f240 224b movw r2, #587 ; 0x24b + 8006ede: 4920 ldr r1, [pc, #128] ; (8006f60 ) + 8006ee0: 4820 ldr r0, [pc, #128] ; (8006f64 ) + 8006ee2: f009 fe71 bl 8010bc8 + if ((p == NULL) || (header_size_decrement > 0xFFFF)) { + 8006ee6: 687b ldr r3, [r7, #4] + 8006ee8: 2b00 cmp r3, #0 + 8006eea: d003 beq.n 8006ef4 + 8006eec: 683b ldr r3, [r7, #0] + 8006eee: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8006ef2: d301 bcc.n 8006ef8 + return 1; + 8006ef4: 2301 movs r3, #1 + 8006ef6: e02c b.n 8006f52 + } + if (header_size_decrement == 0) { + 8006ef8: 683b ldr r3, [r7, #0] + 8006efa: 2b00 cmp r3, #0 + 8006efc: d101 bne.n 8006f02 + return 0; + 8006efe: 2300 movs r3, #0 + 8006f00: e027 b.n 8006f52 + } + + increment_magnitude = (u16_t)header_size_decrement; + 8006f02: 683b ldr r3, [r7, #0] + 8006f04: 81fb strh r3, [r7, #14] + /* Check that we aren't going to move off the end of the pbuf */ + LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); + 8006f06: 687b ldr r3, [r7, #4] + 8006f08: 895b ldrh r3, [r3, #10] + 8006f0a: 89fa ldrh r2, [r7, #14] + 8006f0c: 429a cmp r2, r3 + 8006f0e: d908 bls.n 8006f22 + 8006f10: 4b12 ldr r3, [pc, #72] ; (8006f5c ) + 8006f12: f240 2255 movw r2, #597 ; 0x255 + 8006f16: 4914 ldr r1, [pc, #80] ; (8006f68 ) + 8006f18: 4812 ldr r0, [pc, #72] ; (8006f64 ) + 8006f1a: f009 fe55 bl 8010bc8 + 8006f1e: 2301 movs r3, #1 + 8006f20: e017 b.n 8006f52 + + /* remember current payload pointer */ + payload = p->payload; + 8006f22: 687b ldr r3, [r7, #4] + 8006f24: 685b ldr r3, [r3, #4] + 8006f26: 60bb str r3, [r7, #8] + LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */ + + /* increase payload pointer (guarded by length check above) */ + p->payload = (u8_t *)p->payload + header_size_decrement; + 8006f28: 687b ldr r3, [r7, #4] + 8006f2a: 685a ldr r2, [r3, #4] + 8006f2c: 683b ldr r3, [r7, #0] + 8006f2e: 441a add r2, r3 + 8006f30: 687b ldr r3, [r7, #4] + 8006f32: 605a str r2, [r3, #4] + /* modify pbuf length fields */ + p->len = (u16_t)(p->len - increment_magnitude); + 8006f34: 687b ldr r3, [r7, #4] + 8006f36: 895a ldrh r2, [r3, #10] + 8006f38: 89fb ldrh r3, [r7, #14] + 8006f3a: 1ad3 subs r3, r2, r3 + 8006f3c: b29a uxth r2, r3 + 8006f3e: 687b ldr r3, [r7, #4] + 8006f40: 815a strh r2, [r3, #10] + p->tot_len = (u16_t)(p->tot_len - increment_magnitude); + 8006f42: 687b ldr r3, [r7, #4] + 8006f44: 891a ldrh r2, [r3, #8] + 8006f46: 89fb ldrh r3, [r7, #14] + 8006f48: 1ad3 subs r3, r2, r3 + 8006f4a: b29a uxth r2, r3 + 8006f4c: 687b ldr r3, [r7, #4] + 8006f4e: 811a strh r2, [r3, #8] + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n", + (void *)payload, (void *)p->payload, increment_magnitude)); + + return 0; + 8006f50: 2300 movs r3, #0 +} + 8006f52: 4618 mov r0, r3 + 8006f54: 3710 adds r7, #16 + 8006f56: 46bd mov sp, r7 + 8006f58: bd80 pop {r7, pc} + 8006f5a: bf00 nop + 8006f5c: 08012508 .word 0x08012508 + 8006f60: 0801266c .word 0x0801266c + 8006f64: 08012568 .word 0x08012568 + 8006f68: 08012678 .word 0x08012678 + +08006f6c : + +static u8_t +pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force) +{ + 8006f6c: b580 push {r7, lr} + 8006f6e: b082 sub sp, #8 + 8006f70: af00 add r7, sp, #0 + 8006f72: 6078 str r0, [r7, #4] + 8006f74: 460b mov r3, r1 + 8006f76: 807b strh r3, [r7, #2] + 8006f78: 4613 mov r3, r2 + 8006f7a: 707b strb r3, [r7, #1] + if (header_size_increment < 0) { + 8006f7c: f9b7 3002 ldrsh.w r3, [r7, #2] + 8006f80: 2b00 cmp r3, #0 + 8006f82: da08 bge.n 8006f96 + return pbuf_remove_header(p, (size_t) - header_size_increment); + 8006f84: f9b7 3002 ldrsh.w r3, [r7, #2] + 8006f88: 425b negs r3, r3 + 8006f8a: 4619 mov r1, r3 + 8006f8c: 6878 ldr r0, [r7, #4] + 8006f8e: f7ff ff9b bl 8006ec8 + 8006f92: 4603 mov r3, r0 + 8006f94: e007 b.n 8006fa6 + } else { + return pbuf_add_header_impl(p, (size_t)header_size_increment, force); + 8006f96: f9b7 3002 ldrsh.w r3, [r7, #2] + 8006f9a: 787a ldrb r2, [r7, #1] + 8006f9c: 4619 mov r1, r3 + 8006f9e: 6878 ldr r0, [r7, #4] + 8006fa0: f7ff ff1a bl 8006dd8 + 8006fa4: 4603 mov r3, r0 + } +} + 8006fa6: 4618 mov r0, r3 + 8006fa8: 3708 adds r7, #8 + 8006faa: 46bd mov sp, r7 + 8006fac: bd80 pop {r7, pc} + +08006fae : + * Same as pbuf_header but does not check if 'header_size > 0' is allowed. + * This is used internally only, to allow PBUF_REF for RX. + */ +u8_t +pbuf_header_force(struct pbuf *p, s16_t header_size_increment) +{ + 8006fae: b580 push {r7, lr} + 8006fb0: b082 sub sp, #8 + 8006fb2: af00 add r7, sp, #0 + 8006fb4: 6078 str r0, [r7, #4] + 8006fb6: 460b mov r3, r1 + 8006fb8: 807b strh r3, [r7, #2] + return pbuf_header_impl(p, header_size_increment, 1); + 8006fba: f9b7 3002 ldrsh.w r3, [r7, #2] + 8006fbe: 2201 movs r2, #1 + 8006fc0: 4619 mov r1, r3 + 8006fc2: 6878 ldr r0, [r7, #4] + 8006fc4: f7ff ffd2 bl 8006f6c + 8006fc8: 4603 mov r3, r0 +} + 8006fca: 4618 mov r0, r3 + 8006fcc: 3708 adds r7, #8 + 8006fce: 46bd mov sp, r7 + 8006fd0: bd80 pop {r7, pc} + ... + +08006fd4 : + * 1->1->1 becomes ....... + * + */ +u8_t +pbuf_free(struct pbuf *p) +{ + 8006fd4: b580 push {r7, lr} + 8006fd6: b086 sub sp, #24 + 8006fd8: af00 add r7, sp, #0 + 8006fda: 6078 str r0, [r7, #4] + u8_t alloc_src; + struct pbuf *q; + u8_t count; + + if (p == NULL) { + 8006fdc: 687b ldr r3, [r7, #4] + 8006fde: 2b00 cmp r3, #0 + 8006fe0: d10b bne.n 8006ffa + LWIP_ASSERT("p != NULL", p != NULL); + 8006fe2: 687b ldr r3, [r7, #4] + 8006fe4: 2b00 cmp r3, #0 + 8006fe6: d106 bne.n 8006ff6 + 8006fe8: 4b38 ldr r3, [pc, #224] ; (80070cc ) + 8006fea: f44f 7237 mov.w r2, #732 ; 0x2dc + 8006fee: 4938 ldr r1, [pc, #224] ; (80070d0 ) + 8006ff0: 4838 ldr r0, [pc, #224] ; (80070d4 ) + 8006ff2: f009 fde9 bl 8010bc8 + /* if assertions are disabled, proceed with debug output */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_free(p == NULL) was called.\n")); + return 0; + 8006ff6: 2300 movs r3, #0 + 8006ff8: e063 b.n 80070c2 + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); + + PERF_START; + + count = 0; + 8006ffa: 2300 movs r3, #0 + 8006ffc: 75fb strb r3, [r7, #23] + /* de-allocate all consecutive pbufs from the head of the chain that + * obtain a zero reference count after decrementing*/ + while (p != NULL) { + 8006ffe: e05c b.n 80070ba + /* Since decrementing ref cannot be guaranteed to be a single machine operation + * we must protect it. We put the new ref into a local variable to prevent + * further protection. */ + SYS_ARCH_PROTECT(old_level); + /* all pbufs in a chain are referenced at least once */ + LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); + 8007000: 687b ldr r3, [r7, #4] + 8007002: 7b9b ldrb r3, [r3, #14] + 8007004: 2b00 cmp r3, #0 + 8007006: d106 bne.n 8007016 + 8007008: 4b30 ldr r3, [pc, #192] ; (80070cc ) + 800700a: f240 22f1 movw r2, #753 ; 0x2f1 + 800700e: 4932 ldr r1, [pc, #200] ; (80070d8 ) + 8007010: 4830 ldr r0, [pc, #192] ; (80070d4 ) + 8007012: f009 fdd9 bl 8010bc8 + /* decrease reference count (number of pointers to pbuf) */ + ref = --(p->ref); + 8007016: 687b ldr r3, [r7, #4] + 8007018: 7b9b ldrb r3, [r3, #14] + 800701a: 3b01 subs r3, #1 + 800701c: b2da uxtb r2, r3 + 800701e: 687b ldr r3, [r7, #4] + 8007020: 739a strb r2, [r3, #14] + 8007022: 687b ldr r3, [r7, #4] + 8007024: 7b9b ldrb r3, [r3, #14] + 8007026: 75bb strb r3, [r7, #22] + SYS_ARCH_UNPROTECT(old_level); + /* this pbuf is no longer referenced to? */ + if (ref == 0) { + 8007028: 7dbb ldrb r3, [r7, #22] + 800702a: 2b00 cmp r3, #0 + 800702c: d143 bne.n 80070b6 + /* remember next pbuf in chain for next iteration */ + q = p->next; + 800702e: 687b ldr r3, [r7, #4] + 8007030: 681b ldr r3, [r3, #0] + 8007032: 613b str r3, [r7, #16] + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); + alloc_src = pbuf_get_allocsrc(p); + 8007034: 687b ldr r3, [r7, #4] + 8007036: 7b1b ldrb r3, [r3, #12] + 8007038: f003 030f and.w r3, r3, #15 + 800703c: 73fb strb r3, [r7, #15] +#if LWIP_SUPPORT_CUSTOM_PBUF + /* is this a custom pbuf? */ + if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) { + 800703e: 687b ldr r3, [r7, #4] + 8007040: 7b5b ldrb r3, [r3, #13] + 8007042: f003 0302 and.w r3, r3, #2 + 8007046: 2b00 cmp r3, #0 + 8007048: d011 beq.n 800706e + struct pbuf_custom *pc = (struct pbuf_custom *)p; + 800704a: 687b ldr r3, [r7, #4] + 800704c: 60bb str r3, [r7, #8] + LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL); + 800704e: 68bb ldr r3, [r7, #8] + 8007050: 691b ldr r3, [r3, #16] + 8007052: 2b00 cmp r3, #0 + 8007054: d106 bne.n 8007064 + 8007056: 4b1d ldr r3, [pc, #116] ; (80070cc ) + 8007058: f240 22ff movw r2, #767 ; 0x2ff + 800705c: 491f ldr r1, [pc, #124] ; (80070dc ) + 800705e: 481d ldr r0, [pc, #116] ; (80070d4 ) + 8007060: f009 fdb2 bl 8010bc8 + pc->custom_free_function(p); + 8007064: 68bb ldr r3, [r7, #8] + 8007066: 691b ldr r3, [r3, #16] + 8007068: 6878 ldr r0, [r7, #4] + 800706a: 4798 blx r3 + 800706c: e01d b.n 80070aa + } else +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + { + /* is this a pbuf from the pool? */ + if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) { + 800706e: 7bfb ldrb r3, [r7, #15] + 8007070: 2b02 cmp r3, #2 + 8007072: d104 bne.n 800707e + memp_free(MEMP_PBUF_POOL, p); + 8007074: 6879 ldr r1, [r7, #4] + 8007076: 2008 movs r0, #8 + 8007078: f7ff f840 bl 80060fc + 800707c: e015 b.n 80070aa + /* is this a ROM or RAM referencing pbuf? */ + } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) { + 800707e: 7bfb ldrb r3, [r7, #15] + 8007080: 2b01 cmp r3, #1 + 8007082: d104 bne.n 800708e + memp_free(MEMP_PBUF, p); + 8007084: 6879 ldr r1, [r7, #4] + 8007086: 2007 movs r0, #7 + 8007088: f7ff f838 bl 80060fc + 800708c: e00d b.n 80070aa + /* type == PBUF_RAM */ + } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) { + 800708e: 7bfb ldrb r3, [r7, #15] + 8007090: 2b00 cmp r3, #0 + 8007092: d103 bne.n 800709c + mem_free(p); + 8007094: 6878 ldr r0, [r7, #4] + 8007096: f7fe fc99 bl 80059cc + 800709a: e006 b.n 80070aa + } else { + /* @todo: support freeing other types */ + LWIP_ASSERT("invalid pbuf type", 0); + 800709c: 4b0b ldr r3, [pc, #44] ; (80070cc ) + 800709e: f240 320f movw r2, #783 ; 0x30f + 80070a2: 490f ldr r1, [pc, #60] ; (80070e0 ) + 80070a4: 480b ldr r0, [pc, #44] ; (80070d4 ) + 80070a6: f009 fd8f bl 8010bc8 + } + } + count++; + 80070aa: 7dfb ldrb r3, [r7, #23] + 80070ac: 3301 adds r3, #1 + 80070ae: 75fb strb r3, [r7, #23] + /* proceed to next pbuf */ + p = q; + 80070b0: 693b ldr r3, [r7, #16] + 80070b2: 607b str r3, [r7, #4] + 80070b4: e001 b.n 80070ba + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref)); + /* stop walking through the chain */ + p = NULL; + 80070b6: 2300 movs r3, #0 + 80070b8: 607b str r3, [r7, #4] + while (p != NULL) { + 80070ba: 687b ldr r3, [r7, #4] + 80070bc: 2b00 cmp r3, #0 + 80070be: d19f bne.n 8007000 + } + } + PERF_STOP("pbuf_free"); + /* return number of de-allocated pbufs */ + return count; + 80070c0: 7dfb ldrb r3, [r7, #23] +} + 80070c2: 4618 mov r0, r3 + 80070c4: 3718 adds r7, #24 + 80070c6: 46bd mov sp, r7 + 80070c8: bd80 pop {r7, pc} + 80070ca: bf00 nop + 80070cc: 08012508 .word 0x08012508 + 80070d0: 0801266c .word 0x0801266c + 80070d4: 08012568 .word 0x08012568 + 80070d8: 08012698 .word 0x08012698 + 80070dc: 080126b0 .word 0x080126b0 + 80070e0: 080126d4 .word 0x080126d4 + +080070e4 : + * @param p first pbuf of chain + * @return the number of pbufs in a chain + */ +u16_t +pbuf_clen(const struct pbuf *p) +{ + 80070e4: b480 push {r7} + 80070e6: b085 sub sp, #20 + 80070e8: af00 add r7, sp, #0 + 80070ea: 6078 str r0, [r7, #4] + u16_t len; + + len = 0; + 80070ec: 2300 movs r3, #0 + 80070ee: 81fb strh r3, [r7, #14] + while (p != NULL) { + 80070f0: e005 b.n 80070fe + ++len; + 80070f2: 89fb ldrh r3, [r7, #14] + 80070f4: 3301 adds r3, #1 + 80070f6: 81fb strh r3, [r7, #14] + p = p->next; + 80070f8: 687b ldr r3, [r7, #4] + 80070fa: 681b ldr r3, [r3, #0] + 80070fc: 607b str r3, [r7, #4] + while (p != NULL) { + 80070fe: 687b ldr r3, [r7, #4] + 8007100: 2b00 cmp r3, #0 + 8007102: d1f6 bne.n 80070f2 + } + return len; + 8007104: 89fb ldrh r3, [r7, #14] +} + 8007106: 4618 mov r0, r3 + 8007108: 3714 adds r7, #20 + 800710a: 46bd mov sp, r7 + 800710c: f85d 7b04 ldr.w r7, [sp], #4 + 8007110: 4770 bx lr + ... + +08007114 : + * @param p pbuf to increase reference counter of + * + */ +void +pbuf_ref(struct pbuf *p) +{ + 8007114: b580 push {r7, lr} + 8007116: b082 sub sp, #8 + 8007118: af00 add r7, sp, #0 + 800711a: 6078 str r0, [r7, #4] + /* pbuf given? */ + if (p != NULL) { + 800711c: 687b ldr r3, [r7, #4] + 800711e: 2b00 cmp r3, #0 + 8007120: d010 beq.n 8007144 + SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1)); + 8007122: 687b ldr r3, [r7, #4] + 8007124: 7b9b ldrb r3, [r3, #14] + 8007126: 3301 adds r3, #1 + 8007128: b2da uxtb r2, r3 + 800712a: 687b ldr r3, [r7, #4] + 800712c: 739a strb r2, [r3, #14] + LWIP_ASSERT("pbuf ref overflow", p->ref > 0); + 800712e: 687b ldr r3, [r7, #4] + 8007130: 7b9b ldrb r3, [r3, #14] + 8007132: 2b00 cmp r3, #0 + 8007134: d106 bne.n 8007144 + 8007136: 4b05 ldr r3, [pc, #20] ; (800714c ) + 8007138: f240 3242 movw r2, #834 ; 0x342 + 800713c: 4904 ldr r1, [pc, #16] ; (8007150 ) + 800713e: 4805 ldr r0, [pc, #20] ; (8007154 ) + 8007140: f009 fd42 bl 8010bc8 + } +} + 8007144: bf00 nop + 8007146: 3708 adds r7, #8 + 8007148: 46bd mov sp, r7 + 800714a: bd80 pop {r7, pc} + 800714c: 08012508 .word 0x08012508 + 8007150: 080126e8 .word 0x080126e8 + 8007154: 08012568 .word 0x08012568 + +08007158 : + * + * @see pbuf_chain() + */ +void +pbuf_cat(struct pbuf *h, struct pbuf *t) +{ + 8007158: b580 push {r7, lr} + 800715a: b084 sub sp, #16 + 800715c: af00 add r7, sp, #0 + 800715e: 6078 str r0, [r7, #4] + 8007160: 6039 str r1, [r7, #0] + struct pbuf *p; + + LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", + 8007162: 687b ldr r3, [r7, #4] + 8007164: 2b00 cmp r3, #0 + 8007166: d002 beq.n 800716e + 8007168: 683b ldr r3, [r7, #0] + 800716a: 2b00 cmp r3, #0 + 800716c: d107 bne.n 800717e + 800716e: 4b20 ldr r3, [pc, #128] ; (80071f0 ) + 8007170: f240 3259 movw r2, #857 ; 0x359 + 8007174: 491f ldr r1, [pc, #124] ; (80071f4 ) + 8007176: 4820 ldr r0, [pc, #128] ; (80071f8 ) + 8007178: f009 fd26 bl 8010bc8 + 800717c: e034 b.n 80071e8 + ((h != NULL) && (t != NULL)), return;); + + /* proceed to last pbuf of chain */ + for (p = h; p->next != NULL; p = p->next) { + 800717e: 687b ldr r3, [r7, #4] + 8007180: 60fb str r3, [r7, #12] + 8007182: e00a b.n 800719a + /* add total length of second chain to all totals of first chain */ + p->tot_len = (u16_t)(p->tot_len + t->tot_len); + 8007184: 68fb ldr r3, [r7, #12] + 8007186: 891a ldrh r2, [r3, #8] + 8007188: 683b ldr r3, [r7, #0] + 800718a: 891b ldrh r3, [r3, #8] + 800718c: 4413 add r3, r2 + 800718e: b29a uxth r2, r3 + 8007190: 68fb ldr r3, [r7, #12] + 8007192: 811a strh r2, [r3, #8] + for (p = h; p->next != NULL; p = p->next) { + 8007194: 68fb ldr r3, [r7, #12] + 8007196: 681b ldr r3, [r3, #0] + 8007198: 60fb str r3, [r7, #12] + 800719a: 68fb ldr r3, [r7, #12] + 800719c: 681b ldr r3, [r3, #0] + 800719e: 2b00 cmp r3, #0 + 80071a0: d1f0 bne.n 8007184 + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); + 80071a2: 68fb ldr r3, [r7, #12] + 80071a4: 891a ldrh r2, [r3, #8] + 80071a6: 68fb ldr r3, [r7, #12] + 80071a8: 895b ldrh r3, [r3, #10] + 80071aa: 429a cmp r2, r3 + 80071ac: d006 beq.n 80071bc + 80071ae: 4b10 ldr r3, [pc, #64] ; (80071f0 ) + 80071b0: f240 3262 movw r2, #866 ; 0x362 + 80071b4: 4911 ldr r1, [pc, #68] ; (80071fc ) + 80071b6: 4810 ldr r0, [pc, #64] ; (80071f8 ) + 80071b8: f009 fd06 bl 8010bc8 + LWIP_ASSERT("p->next == NULL", p->next == NULL); + 80071bc: 68fb ldr r3, [r7, #12] + 80071be: 681b ldr r3, [r3, #0] + 80071c0: 2b00 cmp r3, #0 + 80071c2: d006 beq.n 80071d2 + 80071c4: 4b0a ldr r3, [pc, #40] ; (80071f0 ) + 80071c6: f240 3263 movw r2, #867 ; 0x363 + 80071ca: 490d ldr r1, [pc, #52] ; (8007200 ) + 80071cc: 480a ldr r0, [pc, #40] ; (80071f8 ) + 80071ce: f009 fcfb bl 8010bc8 + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len = (u16_t)(p->tot_len + t->tot_len); + 80071d2: 68fb ldr r3, [r7, #12] + 80071d4: 891a ldrh r2, [r3, #8] + 80071d6: 683b ldr r3, [r7, #0] + 80071d8: 891b ldrh r3, [r3, #8] + 80071da: 4413 add r3, r2 + 80071dc: b29a uxth r2, r3 + 80071de: 68fb ldr r3, [r7, #12] + 80071e0: 811a strh r2, [r3, #8] + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; + 80071e2: 68fb ldr r3, [r7, #12] + 80071e4: 683a ldr r2, [r7, #0] + 80071e6: 601a str r2, [r3, #0] + /* p->next now references t, but the caller will drop its reference to t, + * so netto there is no change to the reference count of t. + */ +} + 80071e8: 3710 adds r7, #16 + 80071ea: 46bd mov sp, r7 + 80071ec: bd80 pop {r7, pc} + 80071ee: bf00 nop + 80071f0: 08012508 .word 0x08012508 + 80071f4: 080126fc .word 0x080126fc + 80071f8: 08012568 .word 0x08012568 + 80071fc: 08012734 .word 0x08012734 + 8007200: 08012764 .word 0x08012764 + +08007204 : + * ERR_ARG if one of the pbufs is NULL or p_to is not big + * enough to hold p_from + */ +err_t +pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from) +{ + 8007204: b580 push {r7, lr} + 8007206: b086 sub sp, #24 + 8007208: af00 add r7, sp, #0 + 800720a: 6078 str r0, [r7, #4] + 800720c: 6039 str r1, [r7, #0] + size_t offset_to = 0, offset_from = 0, len; + 800720e: 2300 movs r3, #0 + 8007210: 617b str r3, [r7, #20] + 8007212: 2300 movs r3, #0 + 8007214: 613b str r3, [r7, #16] + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", + (const void *)p_to, (const void *)p_from)); + + /* is the target big enough to hold the source? */ + LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && + 8007216: 687b ldr r3, [r7, #4] + 8007218: 2b00 cmp r3, #0 + 800721a: d008 beq.n 800722e + 800721c: 683b ldr r3, [r7, #0] + 800721e: 2b00 cmp r3, #0 + 8007220: d005 beq.n 800722e + 8007222: 687b ldr r3, [r7, #4] + 8007224: 891a ldrh r2, [r3, #8] + 8007226: 683b ldr r3, [r7, #0] + 8007228: 891b ldrh r3, [r3, #8] + 800722a: 429a cmp r2, r3 + 800722c: d209 bcs.n 8007242 + 800722e: 4b57 ldr r3, [pc, #348] ; (800738c ) + 8007230: f240 32c9 movw r2, #969 ; 0x3c9 + 8007234: 4956 ldr r1, [pc, #344] ; (8007390 ) + 8007236: 4857 ldr r0, [pc, #348] ; (8007394 ) + 8007238: f009 fcc6 bl 8010bc8 + 800723c: f06f 030f mvn.w r3, #15 + 8007240: e09f b.n 8007382 + (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); + + /* iterate through pbuf chain */ + do { + /* copy one part of the original chain */ + if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { + 8007242: 687b ldr r3, [r7, #4] + 8007244: 895b ldrh r3, [r3, #10] + 8007246: 461a mov r2, r3 + 8007248: 697b ldr r3, [r7, #20] + 800724a: 1ad2 subs r2, r2, r3 + 800724c: 683b ldr r3, [r7, #0] + 800724e: 895b ldrh r3, [r3, #10] + 8007250: 4619 mov r1, r3 + 8007252: 693b ldr r3, [r7, #16] + 8007254: 1acb subs r3, r1, r3 + 8007256: 429a cmp r2, r3 + 8007258: d306 bcc.n 8007268 + /* complete current p_from fits into current p_to */ + len = p_from->len - offset_from; + 800725a: 683b ldr r3, [r7, #0] + 800725c: 895b ldrh r3, [r3, #10] + 800725e: 461a mov r2, r3 + 8007260: 693b ldr r3, [r7, #16] + 8007262: 1ad3 subs r3, r2, r3 + 8007264: 60fb str r3, [r7, #12] + 8007266: e005 b.n 8007274 + } else { + /* current p_from does not fit into current p_to */ + len = p_to->len - offset_to; + 8007268: 687b ldr r3, [r7, #4] + 800726a: 895b ldrh r3, [r3, #10] + 800726c: 461a mov r2, r3 + 800726e: 697b ldr r3, [r7, #20] + 8007270: 1ad3 subs r3, r2, r3 + 8007272: 60fb str r3, [r7, #12] + } + MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len); + 8007274: 687b ldr r3, [r7, #4] + 8007276: 685a ldr r2, [r3, #4] + 8007278: 697b ldr r3, [r7, #20] + 800727a: 18d0 adds r0, r2, r3 + 800727c: 683b ldr r3, [r7, #0] + 800727e: 685a ldr r2, [r3, #4] + 8007280: 693b ldr r3, [r7, #16] + 8007282: 4413 add r3, r2 + 8007284: 68fa ldr r2, [r7, #12] + 8007286: 4619 mov r1, r3 + 8007288: f009 fe7f bl 8010f8a + offset_to += len; + 800728c: 697a ldr r2, [r7, #20] + 800728e: 68fb ldr r3, [r7, #12] + 8007290: 4413 add r3, r2 + 8007292: 617b str r3, [r7, #20] + offset_from += len; + 8007294: 693a ldr r2, [r7, #16] + 8007296: 68fb ldr r3, [r7, #12] + 8007298: 4413 add r3, r2 + 800729a: 613b str r3, [r7, #16] + LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); + 800729c: 687b ldr r3, [r7, #4] + 800729e: 895b ldrh r3, [r3, #10] + 80072a0: 461a mov r2, r3 + 80072a2: 697b ldr r3, [r7, #20] + 80072a4: 4293 cmp r3, r2 + 80072a6: d906 bls.n 80072b6 + 80072a8: 4b38 ldr r3, [pc, #224] ; (800738c ) + 80072aa: f240 32d9 movw r2, #985 ; 0x3d9 + 80072ae: 493a ldr r1, [pc, #232] ; (8007398 ) + 80072b0: 4838 ldr r0, [pc, #224] ; (8007394 ) + 80072b2: f009 fc89 bl 8010bc8 + LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); + 80072b6: 683b ldr r3, [r7, #0] + 80072b8: 895b ldrh r3, [r3, #10] + 80072ba: 461a mov r2, r3 + 80072bc: 693b ldr r3, [r7, #16] + 80072be: 4293 cmp r3, r2 + 80072c0: d906 bls.n 80072d0 + 80072c2: 4b32 ldr r3, [pc, #200] ; (800738c ) + 80072c4: f240 32da movw r2, #986 ; 0x3da + 80072c8: 4934 ldr r1, [pc, #208] ; (800739c ) + 80072ca: 4832 ldr r0, [pc, #200] ; (8007394 ) + 80072cc: f009 fc7c bl 8010bc8 + if (offset_from >= p_from->len) { + 80072d0: 683b ldr r3, [r7, #0] + 80072d2: 895b ldrh r3, [r3, #10] + 80072d4: 461a mov r2, r3 + 80072d6: 693b ldr r3, [r7, #16] + 80072d8: 4293 cmp r3, r2 + 80072da: d304 bcc.n 80072e6 + /* on to next p_from (if any) */ + offset_from = 0; + 80072dc: 2300 movs r3, #0 + 80072de: 613b str r3, [r7, #16] + p_from = p_from->next; + 80072e0: 683b ldr r3, [r7, #0] + 80072e2: 681b ldr r3, [r3, #0] + 80072e4: 603b str r3, [r7, #0] + } + if (offset_to == p_to->len) { + 80072e6: 687b ldr r3, [r7, #4] + 80072e8: 895b ldrh r3, [r3, #10] + 80072ea: 461a mov r2, r3 + 80072ec: 697b ldr r3, [r7, #20] + 80072ee: 4293 cmp r3, r2 + 80072f0: d114 bne.n 800731c + /* on to next p_to (if any) */ + offset_to = 0; + 80072f2: 2300 movs r3, #0 + 80072f4: 617b str r3, [r7, #20] + p_to = p_to->next; + 80072f6: 687b ldr r3, [r7, #4] + 80072f8: 681b ldr r3, [r3, #0] + 80072fa: 607b str r3, [r7, #4] + LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;); + 80072fc: 687b ldr r3, [r7, #4] + 80072fe: 2b00 cmp r3, #0 + 8007300: d10c bne.n 800731c + 8007302: 683b ldr r3, [r7, #0] + 8007304: 2b00 cmp r3, #0 + 8007306: d009 beq.n 800731c + 8007308: 4b20 ldr r3, [pc, #128] ; (800738c ) + 800730a: f44f 7279 mov.w r2, #996 ; 0x3e4 + 800730e: 4924 ldr r1, [pc, #144] ; (80073a0 ) + 8007310: 4820 ldr r0, [pc, #128] ; (8007394 ) + 8007312: f009 fc59 bl 8010bc8 + 8007316: f06f 030f mvn.w r3, #15 + 800731a: e032 b.n 8007382 + } + + if ((p_from != NULL) && (p_from->len == p_from->tot_len)) { + 800731c: 683b ldr r3, [r7, #0] + 800731e: 2b00 cmp r3, #0 + 8007320: d013 beq.n 800734a + 8007322: 683b ldr r3, [r7, #0] + 8007324: 895a ldrh r2, [r3, #10] + 8007326: 683b ldr r3, [r7, #0] + 8007328: 891b ldrh r3, [r3, #8] + 800732a: 429a cmp r2, r3 + 800732c: d10d bne.n 800734a + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!", + 800732e: 683b ldr r3, [r7, #0] + 8007330: 681b ldr r3, [r3, #0] + 8007332: 2b00 cmp r3, #0 + 8007334: d009 beq.n 800734a + 8007336: 4b15 ldr r3, [pc, #84] ; (800738c ) + 8007338: f240 32e9 movw r2, #1001 ; 0x3e9 + 800733c: 4919 ldr r1, [pc, #100] ; (80073a4 ) + 800733e: 4815 ldr r0, [pc, #84] ; (8007394 ) + 8007340: f009 fc42 bl 8010bc8 + 8007344: f06f 0305 mvn.w r3, #5 + 8007348: e01b b.n 8007382 + (p_from->next == NULL), return ERR_VAL;); + } + if ((p_to != NULL) && (p_to->len == p_to->tot_len)) { + 800734a: 687b ldr r3, [r7, #4] + 800734c: 2b00 cmp r3, #0 + 800734e: d013 beq.n 8007378 + 8007350: 687b ldr r3, [r7, #4] + 8007352: 895a ldrh r2, [r3, #10] + 8007354: 687b ldr r3, [r7, #4] + 8007356: 891b ldrh r3, [r3, #8] + 8007358: 429a cmp r2, r3 + 800735a: d10d bne.n 8007378 + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!", + 800735c: 687b ldr r3, [r7, #4] + 800735e: 681b ldr r3, [r3, #0] + 8007360: 2b00 cmp r3, #0 + 8007362: d009 beq.n 8007378 + 8007364: 4b09 ldr r3, [pc, #36] ; (800738c ) + 8007366: f240 32ee movw r2, #1006 ; 0x3ee + 800736a: 490e ldr r1, [pc, #56] ; (80073a4 ) + 800736c: 4809 ldr r0, [pc, #36] ; (8007394 ) + 800736e: f009 fc2b bl 8010bc8 + 8007372: f06f 0305 mvn.w r3, #5 + 8007376: e004 b.n 8007382 + (p_to->next == NULL), return ERR_VAL;); + } + } while (p_from); + 8007378: 683b ldr r3, [r7, #0] + 800737a: 2b00 cmp r3, #0 + 800737c: f47f af61 bne.w 8007242 + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); + return ERR_OK; + 8007380: 2300 movs r3, #0 +} + 8007382: 4618 mov r0, r3 + 8007384: 3718 adds r7, #24 + 8007386: 46bd mov sp, r7 + 8007388: bd80 pop {r7, pc} + 800738a: bf00 nop + 800738c: 08012508 .word 0x08012508 + 8007390: 080127b0 .word 0x080127b0 + 8007394: 08012568 .word 0x08012568 + 8007398: 080127e0 .word 0x080127e0 + 800739c: 080127f8 .word 0x080127f8 + 80073a0: 08012814 .word 0x08012814 + 80073a4: 08012824 .word 0x08012824 + +080073a8 : + * @param offset offset into the packet buffer from where to begin copying len bytes + * @return the number of bytes copied, or 0 on failure + */ +u16_t +pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) +{ + 80073a8: b580 push {r7, lr} + 80073aa: b088 sub sp, #32 + 80073ac: af00 add r7, sp, #0 + 80073ae: 60f8 str r0, [r7, #12] + 80073b0: 60b9 str r1, [r7, #8] + 80073b2: 4611 mov r1, r2 + 80073b4: 461a mov r2, r3 + 80073b6: 460b mov r3, r1 + 80073b8: 80fb strh r3, [r7, #6] + 80073ba: 4613 mov r3, r2 + 80073bc: 80bb strh r3, [r7, #4] + const struct pbuf *p; + u16_t left = 0; + 80073be: 2300 movs r3, #0 + 80073c0: 837b strh r3, [r7, #26] + u16_t buf_copy_len; + u16_t copied_total = 0; + 80073c2: 2300 movs r3, #0 + 80073c4: 82fb strh r3, [r7, #22] + + LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); + 80073c6: 68fb ldr r3, [r7, #12] + 80073c8: 2b00 cmp r3, #0 + 80073ca: d108 bne.n 80073de + 80073cc: 4b2b ldr r3, [pc, #172] ; (800747c ) + 80073ce: f240 420a movw r2, #1034 ; 0x40a + 80073d2: 492b ldr r1, [pc, #172] ; (8007480 ) + 80073d4: 482b ldr r0, [pc, #172] ; (8007484 ) + 80073d6: f009 fbf7 bl 8010bc8 + 80073da: 2300 movs r3, #0 + 80073dc: e04a b.n 8007474 + LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); + 80073de: 68bb ldr r3, [r7, #8] + 80073e0: 2b00 cmp r3, #0 + 80073e2: d108 bne.n 80073f6 + 80073e4: 4b25 ldr r3, [pc, #148] ; (800747c ) + 80073e6: f240 420b movw r2, #1035 ; 0x40b + 80073ea: 4927 ldr r1, [pc, #156] ; (8007488 ) + 80073ec: 4825 ldr r0, [pc, #148] ; (8007484 ) + 80073ee: f009 fbeb bl 8010bc8 + 80073f2: 2300 movs r3, #0 + 80073f4: e03e b.n 8007474 + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for (p = buf; len != 0 && p != NULL; p = p->next) { + 80073f6: 68fb ldr r3, [r7, #12] + 80073f8: 61fb str r3, [r7, #28] + 80073fa: e034 b.n 8007466 + if ((offset != 0) && (offset >= p->len)) { + 80073fc: 88bb ldrh r3, [r7, #4] + 80073fe: 2b00 cmp r3, #0 + 8007400: d00a beq.n 8007418 + 8007402: 69fb ldr r3, [r7, #28] + 8007404: 895b ldrh r3, [r3, #10] + 8007406: 88ba ldrh r2, [r7, #4] + 8007408: 429a cmp r2, r3 + 800740a: d305 bcc.n 8007418 + /* don't copy from this buffer -> on to the next */ + offset = (u16_t)(offset - p->len); + 800740c: 69fb ldr r3, [r7, #28] + 800740e: 895b ldrh r3, [r3, #10] + 8007410: 88ba ldrh r2, [r7, #4] + 8007412: 1ad3 subs r3, r2, r3 + 8007414: 80bb strh r3, [r7, #4] + 8007416: e023 b.n 8007460 + } else { + /* copy from this buffer. maybe only partially. */ + buf_copy_len = (u16_t)(p->len - offset); + 8007418: 69fb ldr r3, [r7, #28] + 800741a: 895a ldrh r2, [r3, #10] + 800741c: 88bb ldrh r3, [r7, #4] + 800741e: 1ad3 subs r3, r2, r3 + 8007420: 833b strh r3, [r7, #24] + if (buf_copy_len > len) { + 8007422: 8b3a ldrh r2, [r7, #24] + 8007424: 88fb ldrh r3, [r7, #6] + 8007426: 429a cmp r2, r3 + 8007428: d901 bls.n 800742e + buf_copy_len = len; + 800742a: 88fb ldrh r3, [r7, #6] + 800742c: 833b strh r3, [r7, #24] + } + /* copy the necessary parts of the buffer */ + MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len); + 800742e: 8b7b ldrh r3, [r7, #26] + 8007430: 68ba ldr r2, [r7, #8] + 8007432: 18d0 adds r0, r2, r3 + 8007434: 69fb ldr r3, [r7, #28] + 8007436: 685a ldr r2, [r3, #4] + 8007438: 88bb ldrh r3, [r7, #4] + 800743a: 4413 add r3, r2 + 800743c: 8b3a ldrh r2, [r7, #24] + 800743e: 4619 mov r1, r3 + 8007440: f009 fda3 bl 8010f8a + copied_total = (u16_t)(copied_total + buf_copy_len); + 8007444: 8afa ldrh r2, [r7, #22] + 8007446: 8b3b ldrh r3, [r7, #24] + 8007448: 4413 add r3, r2 + 800744a: 82fb strh r3, [r7, #22] + left = (u16_t)(left + buf_copy_len); + 800744c: 8b7a ldrh r2, [r7, #26] + 800744e: 8b3b ldrh r3, [r7, #24] + 8007450: 4413 add r3, r2 + 8007452: 837b strh r3, [r7, #26] + len = (u16_t)(len - buf_copy_len); + 8007454: 88fa ldrh r2, [r7, #6] + 8007456: 8b3b ldrh r3, [r7, #24] + 8007458: 1ad3 subs r3, r2, r3 + 800745a: 80fb strh r3, [r7, #6] + offset = 0; + 800745c: 2300 movs r3, #0 + 800745e: 80bb strh r3, [r7, #4] + for (p = buf; len != 0 && p != NULL; p = p->next) { + 8007460: 69fb ldr r3, [r7, #28] + 8007462: 681b ldr r3, [r3, #0] + 8007464: 61fb str r3, [r7, #28] + 8007466: 88fb ldrh r3, [r7, #6] + 8007468: 2b00 cmp r3, #0 + 800746a: d002 beq.n 8007472 + 800746c: 69fb ldr r3, [r7, #28] + 800746e: 2b00 cmp r3, #0 + 8007470: d1c4 bne.n 80073fc + } + } + return copied_total; + 8007472: 8afb ldrh r3, [r7, #22] +} + 8007474: 4618 mov r0, r3 + 8007476: 3720 adds r7, #32 + 8007478: 46bd mov sp, r7 + 800747a: bd80 pop {r7, pc} + 800747c: 08012508 .word 0x08012508 + 8007480: 08012850 .word 0x08012850 + 8007484: 08012568 .word 0x08012568 + 8007488: 08012870 .word 0x08012870 + +0800748c : + * + * @return a new pbuf or NULL if allocation fails + */ +struct pbuf * +pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p) +{ + 800748c: b580 push {r7, lr} + 800748e: b084 sub sp, #16 + 8007490: af00 add r7, sp, #0 + 8007492: 4603 mov r3, r0 + 8007494: 603a str r2, [r7, #0] + 8007496: 71fb strb r3, [r7, #7] + 8007498: 460b mov r3, r1 + 800749a: 80bb strh r3, [r7, #4] + struct pbuf *q; + err_t err; + q = pbuf_alloc(layer, p->tot_len, type); + 800749c: 683b ldr r3, [r7, #0] + 800749e: 8919 ldrh r1, [r3, #8] + 80074a0: 88ba ldrh r2, [r7, #4] + 80074a2: 79fb ldrb r3, [r7, #7] + 80074a4: 4618 mov r0, r3 + 80074a6: f7ff fab1 bl 8006a0c + 80074aa: 60f8 str r0, [r7, #12] + if (q == NULL) { + 80074ac: 68fb ldr r3, [r7, #12] + 80074ae: 2b00 cmp r3, #0 + 80074b0: d101 bne.n 80074b6 + return NULL; + 80074b2: 2300 movs r3, #0 + 80074b4: e011 b.n 80074da + } + err = pbuf_copy(q, p); + 80074b6: 6839 ldr r1, [r7, #0] + 80074b8: 68f8 ldr r0, [r7, #12] + 80074ba: f7ff fea3 bl 8007204 + 80074be: 4603 mov r3, r0 + 80074c0: 72fb strb r3, [r7, #11] + LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */ + LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); + 80074c2: f997 300b ldrsb.w r3, [r7, #11] + 80074c6: 2b00 cmp r3, #0 + 80074c8: d006 beq.n 80074d8 + 80074ca: 4b06 ldr r3, [pc, #24] ; (80074e4 ) + 80074cc: f240 5224 movw r2, #1316 ; 0x524 + 80074d0: 4905 ldr r1, [pc, #20] ; (80074e8 ) + 80074d2: 4806 ldr r0, [pc, #24] ; (80074ec ) + 80074d4: f009 fb78 bl 8010bc8 + return q; + 80074d8: 68fb ldr r3, [r7, #12] +} + 80074da: 4618 mov r0, r3 + 80074dc: 3710 adds r7, #16 + 80074de: 46bd mov sp, r7 + 80074e0: bd80 pop {r7, pc} + 80074e2: bf00 nop + 80074e4: 08012508 .word 0x08012508 + 80074e8: 0801297c .word 0x0801297c + 80074ec: 08012568 .word 0x08012568 + +080074f0 : +/** + * Initialize this module. + */ +void +tcp_init(void) +{ + 80074f0: b580 push {r7, lr} + 80074f2: af00 add r7, sp, #0 +#ifdef LWIP_RAND + tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); + 80074f4: f008 feb4 bl 8010260 + 80074f8: 4603 mov r3, r0 + 80074fa: b29b uxth r3, r3 + 80074fc: f3c3 030d ubfx r3, r3, #0, #14 + 8007500: b29b uxth r3, r3 + 8007502: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 + 8007506: b29a uxth r2, r3 + 8007508: 4b01 ldr r3, [pc, #4] ; (8007510 ) + 800750a: 801a strh r2, [r3, #0] +#endif /* LWIP_RAND */ +} + 800750c: bf00 nop + 800750e: bd80 pop {r7, pc} + 8007510: 24000068 .word 0x24000068 + +08007514 : + +/** Free a tcp pcb */ +void +tcp_free(struct tcp_pcb *pcb) +{ + 8007514: b580 push {r7, lr} + 8007516: b082 sub sp, #8 + 8007518: af00 add r7, sp, #0 + 800751a: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN); + 800751c: 687b ldr r3, [r7, #4] + 800751e: 7d1b ldrb r3, [r3, #20] + 8007520: 2b01 cmp r3, #1 + 8007522: d105 bne.n 8007530 + 8007524: 4b06 ldr r3, [pc, #24] ; (8007540 ) + 8007526: 22d4 movs r2, #212 ; 0xd4 + 8007528: 4906 ldr r1, [pc, #24] ; (8007544 ) + 800752a: 4807 ldr r0, [pc, #28] ; (8007548 ) + 800752c: f009 fb4c bl 8010bc8 +#if LWIP_TCP_PCB_NUM_EXT_ARGS + tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); +#endif + memp_free(MEMP_TCP_PCB, pcb); + 8007530: 6879 ldr r1, [r7, #4] + 8007532: 2001 movs r0, #1 + 8007534: f7fe fde2 bl 80060fc +} + 8007538: bf00 nop + 800753a: 3708 adds r7, #8 + 800753c: 46bd mov sp, r7 + 800753e: bd80 pop {r7, pc} + 8007540: 08012a08 .word 0x08012a08 + 8007544: 08012a38 .word 0x08012a38 + 8007548: 08012a4c .word 0x08012a4c + +0800754c : + +/** Free a tcp listen pcb */ +static void +tcp_free_listen(struct tcp_pcb *pcb) +{ + 800754c: b580 push {r7, lr} + 800754e: b082 sub sp, #8 + 8007550: af00 add r7, sp, #0 + 8007552: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN); + 8007554: 687b ldr r3, [r7, #4] + 8007556: 7d1b ldrb r3, [r3, #20] + 8007558: 2b01 cmp r3, #1 + 800755a: d105 bne.n 8007568 + 800755c: 4b06 ldr r3, [pc, #24] ; (8007578 ) + 800755e: 22df movs r2, #223 ; 0xdf + 8007560: 4906 ldr r1, [pc, #24] ; (800757c ) + 8007562: 4807 ldr r0, [pc, #28] ; (8007580 ) + 8007564: f009 fb30 bl 8010bc8 +#if LWIP_TCP_PCB_NUM_EXT_ARGS + tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); +#endif + memp_free(MEMP_TCP_PCB_LISTEN, pcb); + 8007568: 6879 ldr r1, [r7, #4] + 800756a: 2002 movs r0, #2 + 800756c: f7fe fdc6 bl 80060fc +} + 8007570: bf00 nop + 8007572: 3708 adds r7, #8 + 8007574: 46bd mov sp, r7 + 8007576: bd80 pop {r7, pc} + 8007578: 08012a08 .word 0x08012a08 + 800757c: 08012a74 .word 0x08012a74 + 8007580: 08012a4c .word 0x08012a4c + +08007584 : +/** + * Called periodically to dispatch TCP timers. + */ +void +tcp_tmr(void) +{ + 8007584: b580 push {r7, lr} + 8007586: af00 add r7, sp, #0 + /* Call tcp_fasttmr() every 250 ms */ + tcp_fasttmr(); + 8007588: f001 f800 bl 800858c + + if (++tcp_timer & 1) { + 800758c: 4b07 ldr r3, [pc, #28] ; (80075ac ) + 800758e: 781b ldrb r3, [r3, #0] + 8007590: 3301 adds r3, #1 + 8007592: b2da uxtb r2, r3 + 8007594: 4b05 ldr r3, [pc, #20] ; (80075ac ) + 8007596: 701a strb r2, [r3, #0] + 8007598: 4b04 ldr r3, [pc, #16] ; (80075ac ) + 800759a: 781b ldrb r3, [r3, #0] + 800759c: f003 0301 and.w r3, r3, #1 + 80075a0: 2b00 cmp r3, #0 + 80075a2: d001 beq.n 80075a8 + /* Call tcp_slowtmr() every 500 ms, i.e., every other timer + tcp_tmr() is called. */ + tcp_slowtmr(); + 80075a4: f000 fcb2 bl 8007f0c + } +} + 80075a8: bf00 nop + 80075aa: bd80 pop {r7, pc} + 80075ac: 24007b81 .word 0x24007b81 + +080075b0 : +/** Called when a listen pcb is closed. Iterates one pcb list and removes the + * closed listener pcb from pcb->listener if matching. + */ +static void +tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb) +{ + 80075b0: b580 push {r7, lr} + 80075b2: b084 sub sp, #16 + 80075b4: af00 add r7, sp, #0 + 80075b6: 6078 str r0, [r7, #4] + 80075b8: 6039 str r1, [r7, #0] + struct tcp_pcb *pcb; + + LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL); + 80075ba: 683b ldr r3, [r7, #0] + 80075bc: 2b00 cmp r3, #0 + 80075be: d105 bne.n 80075cc + 80075c0: 4b0d ldr r3, [pc, #52] ; (80075f8 ) + 80075c2: 22ff movs r2, #255 ; 0xff + 80075c4: 490d ldr r1, [pc, #52] ; (80075fc ) + 80075c6: 480e ldr r0, [pc, #56] ; (8007600 ) + 80075c8: f009 fafe bl 8010bc8 + + for (pcb = list; pcb != NULL; pcb = pcb->next) { + 80075cc: 687b ldr r3, [r7, #4] + 80075ce: 60fb str r3, [r7, #12] + 80075d0: e00a b.n 80075e8 + if (pcb->listener == lpcb) { + 80075d2: 68fb ldr r3, [r7, #12] + 80075d4: 6fdb ldr r3, [r3, #124] ; 0x7c + 80075d6: 683a ldr r2, [r7, #0] + 80075d8: 429a cmp r2, r3 + 80075da: d102 bne.n 80075e2 + pcb->listener = NULL; + 80075dc: 68fb ldr r3, [r7, #12] + 80075de: 2200 movs r2, #0 + 80075e0: 67da str r2, [r3, #124] ; 0x7c + for (pcb = list; pcb != NULL; pcb = pcb->next) { + 80075e2: 68fb ldr r3, [r7, #12] + 80075e4: 68db ldr r3, [r3, #12] + 80075e6: 60fb str r3, [r7, #12] + 80075e8: 68fb ldr r3, [r7, #12] + 80075ea: 2b00 cmp r3, #0 + 80075ec: d1f1 bne.n 80075d2 + } + } +} + 80075ee: bf00 nop + 80075f0: bf00 nop + 80075f2: 3710 adds r7, #16 + 80075f4: 46bd mov sp, r7 + 80075f6: bd80 pop {r7, pc} + 80075f8: 08012a08 .word 0x08012a08 + 80075fc: 08012a90 .word 0x08012a90 + 8007600: 08012a4c .word 0x08012a4c + +08007604 : +/** Called when a listen pcb is closed. Iterates all pcb lists and removes the + * closed listener pcb from pcb->listener if matching. + */ +static void +tcp_listen_closed(struct tcp_pcb *pcb) +{ + 8007604: b580 push {r7, lr} + 8007606: b084 sub sp, #16 + 8007608: af00 add r7, sp, #0 + 800760a: 6078 str r0, [r7, #4] +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + size_t i; + LWIP_ASSERT("pcb != NULL", pcb != NULL); + 800760c: 687b ldr r3, [r7, #4] + 800760e: 2b00 cmp r3, #0 + 8007610: d106 bne.n 8007620 + 8007612: 4b14 ldr r3, [pc, #80] ; (8007664 ) + 8007614: f240 1211 movw r2, #273 ; 0x111 + 8007618: 4913 ldr r1, [pc, #76] ; (8007668 ) + 800761a: 4814 ldr r0, [pc, #80] ; (800766c ) + 800761c: f009 fad4 bl 8010bc8 + LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN); + 8007620: 687b ldr r3, [r7, #4] + 8007622: 7d1b ldrb r3, [r3, #20] + 8007624: 2b01 cmp r3, #1 + 8007626: d006 beq.n 8007636 + 8007628: 4b0e ldr r3, [pc, #56] ; (8007664 ) + 800762a: f44f 7289 mov.w r2, #274 ; 0x112 + 800762e: 4910 ldr r1, [pc, #64] ; (8007670 ) + 8007630: 480e ldr r0, [pc, #56] ; (800766c ) + 8007632: f009 fac9 bl 8010bc8 + for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { + 8007636: 2301 movs r3, #1 + 8007638: 60fb str r3, [r7, #12] + 800763a: e00b b.n 8007654 + tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb); + 800763c: 4a0d ldr r2, [pc, #52] ; (8007674 ) + 800763e: 68fb ldr r3, [r7, #12] + 8007640: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8007644: 681b ldr r3, [r3, #0] + 8007646: 6879 ldr r1, [r7, #4] + 8007648: 4618 mov r0, r3 + 800764a: f7ff ffb1 bl 80075b0 + for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { + 800764e: 68fb ldr r3, [r7, #12] + 8007650: 3301 adds r3, #1 + 8007652: 60fb str r3, [r7, #12] + 8007654: 68fb ldr r3, [r7, #12] + 8007656: 2b03 cmp r3, #3 + 8007658: d9f0 bls.n 800763c + } +#endif + LWIP_UNUSED_ARG(pcb); +} + 800765a: bf00 nop + 800765c: bf00 nop + 800765e: 3710 adds r7, #16 + 8007660: 46bd mov sp, r7 + 8007662: bd80 pop {r7, pc} + 8007664: 08012a08 .word 0x08012a08 + 8007668: 08012ab8 .word 0x08012ab8 + 800766c: 08012a4c .word 0x08012a4c + 8007670: 08012ac4 .word 0x08012ac4 + 8007674: 08014d6c .word 0x08014d6c + +08007678 : + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +static err_t +tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data) +{ + 8007678: b5b0 push {r4, r5, r7, lr} + 800767a: b088 sub sp, #32 + 800767c: af04 add r7, sp, #16 + 800767e: 6078 str r0, [r7, #4] + 8007680: 460b mov r3, r1 + 8007682: 70fb strb r3, [r7, #3] + LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL); + 8007684: 687b ldr r3, [r7, #4] + 8007686: 2b00 cmp r3, #0 + 8007688: d106 bne.n 8007698 + 800768a: 4b63 ldr r3, [pc, #396] ; (8007818 ) + 800768c: f44f 72af mov.w r2, #350 ; 0x15e + 8007690: 4962 ldr r1, [pc, #392] ; (800781c ) + 8007692: 4863 ldr r0, [pc, #396] ; (8007820 ) + 8007694: f009 fa98 bl 8010bc8 + + if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { + 8007698: 78fb ldrb r3, [r7, #3] + 800769a: 2b00 cmp r3, #0 + 800769c: d066 beq.n 800776c + 800769e: 687b ldr r3, [r7, #4] + 80076a0: 7d1b ldrb r3, [r3, #20] + 80076a2: 2b04 cmp r3, #4 + 80076a4: d003 beq.n 80076ae + 80076a6: 687b ldr r3, [r7, #4] + 80076a8: 7d1b ldrb r3, [r3, #20] + 80076aa: 2b07 cmp r3, #7 + 80076ac: d15e bne.n 800776c + if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) { + 80076ae: 687b ldr r3, [r7, #4] + 80076b0: 6f9b ldr r3, [r3, #120] ; 0x78 + 80076b2: 2b00 cmp r3, #0 + 80076b4: d104 bne.n 80076c0 + 80076b6: 687b ldr r3, [r7, #4] + 80076b8: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80076ba: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 80076be: d055 beq.n 800776c + /* Not all data received by application, send RST to tell the remote + side about this. */ + LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED); + 80076c0: 687b ldr r3, [r7, #4] + 80076c2: 8b5b ldrh r3, [r3, #26] + 80076c4: f003 0310 and.w r3, r3, #16 + 80076c8: 2b00 cmp r3, #0 + 80076ca: d106 bne.n 80076da + 80076cc: 4b52 ldr r3, [pc, #328] ; (8007818 ) + 80076ce: f44f 72b2 mov.w r2, #356 ; 0x164 + 80076d2: 4954 ldr r1, [pc, #336] ; (8007824 ) + 80076d4: 4852 ldr r0, [pc, #328] ; (8007820 ) + 80076d6: f009 fa77 bl 8010bc8 + + /* don't call tcp_abort here: we must not deallocate the pcb since + that might not be expected when calling tcp_close */ + tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + 80076da: 687b ldr r3, [r7, #4] + 80076dc: 6d18 ldr r0, [r3, #80] ; 0x50 + 80076de: 687b ldr r3, [r7, #4] + 80076e0: 6a5c ldr r4, [r3, #36] ; 0x24 + 80076e2: 687d ldr r5, [r7, #4] + 80076e4: 687b ldr r3, [r7, #4] + 80076e6: 3304 adds r3, #4 + 80076e8: 687a ldr r2, [r7, #4] + 80076ea: 8ad2 ldrh r2, [r2, #22] + 80076ec: 6879 ldr r1, [r7, #4] + 80076ee: 8b09 ldrh r1, [r1, #24] + 80076f0: 9102 str r1, [sp, #8] + 80076f2: 9201 str r2, [sp, #4] + 80076f4: 9300 str r3, [sp, #0] + 80076f6: 462b mov r3, r5 + 80076f8: 4622 mov r2, r4 + 80076fa: 4601 mov r1, r0 + 80076fc: 6878 ldr r0, [r7, #4] + 80076fe: f005 fd39 bl 800d174 + pcb->local_port, pcb->remote_port); + + tcp_pcb_purge(pcb); + 8007702: 6878 ldr r0, [r7, #4] + 8007704: f001 faa4 bl 8008c50 + TCP_RMV_ACTIVE(pcb); + 8007708: 4b47 ldr r3, [pc, #284] ; (8007828 ) + 800770a: 681b ldr r3, [r3, #0] + 800770c: 687a ldr r2, [r7, #4] + 800770e: 429a cmp r2, r3 + 8007710: d105 bne.n 800771e + 8007712: 4b45 ldr r3, [pc, #276] ; (8007828 ) + 8007714: 681b ldr r3, [r3, #0] + 8007716: 68db ldr r3, [r3, #12] + 8007718: 4a43 ldr r2, [pc, #268] ; (8007828 ) + 800771a: 6013 str r3, [r2, #0] + 800771c: e013 b.n 8007746 + 800771e: 4b42 ldr r3, [pc, #264] ; (8007828 ) + 8007720: 681b ldr r3, [r3, #0] + 8007722: 60fb str r3, [r7, #12] + 8007724: e00c b.n 8007740 + 8007726: 68fb ldr r3, [r7, #12] + 8007728: 68db ldr r3, [r3, #12] + 800772a: 687a ldr r2, [r7, #4] + 800772c: 429a cmp r2, r3 + 800772e: d104 bne.n 800773a + 8007730: 687b ldr r3, [r7, #4] + 8007732: 68da ldr r2, [r3, #12] + 8007734: 68fb ldr r3, [r7, #12] + 8007736: 60da str r2, [r3, #12] + 8007738: e005 b.n 8007746 + 800773a: 68fb ldr r3, [r7, #12] + 800773c: 68db ldr r3, [r3, #12] + 800773e: 60fb str r3, [r7, #12] + 8007740: 68fb ldr r3, [r7, #12] + 8007742: 2b00 cmp r3, #0 + 8007744: d1ef bne.n 8007726 + 8007746: 687b ldr r3, [r7, #4] + 8007748: 2200 movs r2, #0 + 800774a: 60da str r2, [r3, #12] + 800774c: 4b37 ldr r3, [pc, #220] ; (800782c ) + 800774e: 2201 movs r2, #1 + 8007750: 701a strb r2, [r3, #0] + /* Deallocate the pcb since we already sent a RST for it */ + if (tcp_input_pcb == pcb) { + 8007752: 4b37 ldr r3, [pc, #220] ; (8007830 ) + 8007754: 681b ldr r3, [r3, #0] + 8007756: 687a ldr r2, [r7, #4] + 8007758: 429a cmp r2, r3 + 800775a: d102 bne.n 8007762 + /* prevent using a deallocated pcb: free it from tcp_input later */ + tcp_trigger_input_pcb_close(); + 800775c: f003 ff42 bl 800b5e4 + 8007760: e002 b.n 8007768 + } else { + tcp_free(pcb); + 8007762: 6878 ldr r0, [r7, #4] + 8007764: f7ff fed6 bl 8007514 + } + return ERR_OK; + 8007768: 2300 movs r3, #0 + 800776a: e050 b.n 800780e + } + } + + /* - states which free the pcb are handled here, + - states which send FIN and change state are handled in tcp_close_shutdown_fin() */ + switch (pcb->state) { + 800776c: 687b ldr r3, [r7, #4] + 800776e: 7d1b ldrb r3, [r3, #20] + 8007770: 2b02 cmp r3, #2 + 8007772: d03b beq.n 80077ec + 8007774: 2b02 cmp r3, #2 + 8007776: dc44 bgt.n 8007802 + 8007778: 2b00 cmp r3, #0 + 800777a: d002 beq.n 8007782 + 800777c: 2b01 cmp r3, #1 + 800777e: d02a beq.n 80077d6 + 8007780: e03f b.n 8007802 + * and the user needs some way to free it should the need arise. + * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) + * or for a pcb that has been used and then entered the CLOSED state + * is erroneous, but this should never happen as the pcb has in those cases + * been freed, and so any remaining handles are bogus. */ + if (pcb->local_port != 0) { + 8007782: 687b ldr r3, [r7, #4] + 8007784: 8adb ldrh r3, [r3, #22] + 8007786: 2b00 cmp r3, #0 + 8007788: d021 beq.n 80077ce + TCP_RMV(&tcp_bound_pcbs, pcb); + 800778a: 4b2a ldr r3, [pc, #168] ; (8007834 ) + 800778c: 681b ldr r3, [r3, #0] + 800778e: 687a ldr r2, [r7, #4] + 8007790: 429a cmp r2, r3 + 8007792: d105 bne.n 80077a0 + 8007794: 4b27 ldr r3, [pc, #156] ; (8007834 ) + 8007796: 681b ldr r3, [r3, #0] + 8007798: 68db ldr r3, [r3, #12] + 800779a: 4a26 ldr r2, [pc, #152] ; (8007834 ) + 800779c: 6013 str r3, [r2, #0] + 800779e: e013 b.n 80077c8 + 80077a0: 4b24 ldr r3, [pc, #144] ; (8007834 ) + 80077a2: 681b ldr r3, [r3, #0] + 80077a4: 60bb str r3, [r7, #8] + 80077a6: e00c b.n 80077c2 + 80077a8: 68bb ldr r3, [r7, #8] + 80077aa: 68db ldr r3, [r3, #12] + 80077ac: 687a ldr r2, [r7, #4] + 80077ae: 429a cmp r2, r3 + 80077b0: d104 bne.n 80077bc + 80077b2: 687b ldr r3, [r7, #4] + 80077b4: 68da ldr r2, [r3, #12] + 80077b6: 68bb ldr r3, [r7, #8] + 80077b8: 60da str r2, [r3, #12] + 80077ba: e005 b.n 80077c8 + 80077bc: 68bb ldr r3, [r7, #8] + 80077be: 68db ldr r3, [r3, #12] + 80077c0: 60bb str r3, [r7, #8] + 80077c2: 68bb ldr r3, [r7, #8] + 80077c4: 2b00 cmp r3, #0 + 80077c6: d1ef bne.n 80077a8 + 80077c8: 687b ldr r3, [r7, #4] + 80077ca: 2200 movs r2, #0 + 80077cc: 60da str r2, [r3, #12] + } + tcp_free(pcb); + 80077ce: 6878 ldr r0, [r7, #4] + 80077d0: f7ff fea0 bl 8007514 + break; + 80077d4: e01a b.n 800780c + case LISTEN: + tcp_listen_closed(pcb); + 80077d6: 6878 ldr r0, [r7, #4] + 80077d8: f7ff ff14 bl 8007604 + tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb); + 80077dc: 6879 ldr r1, [r7, #4] + 80077de: 4816 ldr r0, [pc, #88] ; (8007838 ) + 80077e0: f001 fa86 bl 8008cf0 + tcp_free_listen(pcb); + 80077e4: 6878 ldr r0, [r7, #4] + 80077e6: f7ff feb1 bl 800754c + break; + 80077ea: e00f b.n 800780c + case SYN_SENT: + TCP_PCB_REMOVE_ACTIVE(pcb); + 80077ec: 6879 ldr r1, [r7, #4] + 80077ee: 480e ldr r0, [pc, #56] ; (8007828 ) + 80077f0: f001 fa7e bl 8008cf0 + 80077f4: 4b0d ldr r3, [pc, #52] ; (800782c ) + 80077f6: 2201 movs r2, #1 + 80077f8: 701a strb r2, [r3, #0] + tcp_free(pcb); + 80077fa: 6878 ldr r0, [r7, #4] + 80077fc: f7ff fe8a bl 8007514 + MIB2_STATS_INC(mib2.tcpattemptfails); + break; + 8007800: e004 b.n 800780c + default: + return tcp_close_shutdown_fin(pcb); + 8007802: 6878 ldr r0, [r7, #4] + 8007804: f000 f81a bl 800783c + 8007808: 4603 mov r3, r0 + 800780a: e000 b.n 800780e + } + return ERR_OK; + 800780c: 2300 movs r3, #0 +} + 800780e: 4618 mov r0, r3 + 8007810: 3710 adds r7, #16 + 8007812: 46bd mov sp, r7 + 8007814: bdb0 pop {r4, r5, r7, pc} + 8007816: bf00 nop + 8007818: 08012a08 .word 0x08012a08 + 800781c: 08012adc .word 0x08012adc + 8007820: 08012a4c .word 0x08012a4c + 8007824: 08012afc .word 0x08012afc + 8007828: 24007b78 .word 0x24007b78 + 800782c: 24007b80 .word 0x24007b80 + 8007830: 24007bbc .word 0x24007bbc + 8007834: 24007b70 .word 0x24007b70 + 8007838: 24007b74 .word 0x24007b74 + +0800783c : + +static err_t +tcp_close_shutdown_fin(struct tcp_pcb *pcb) +{ + 800783c: b580 push {r7, lr} + 800783e: b084 sub sp, #16 + 8007840: af00 add r7, sp, #0 + 8007842: 6078 str r0, [r7, #4] + err_t err; + LWIP_ASSERT("pcb != NULL", pcb != NULL); + 8007844: 687b ldr r3, [r7, #4] + 8007846: 2b00 cmp r3, #0 + 8007848: d106 bne.n 8007858 + 800784a: 4b2e ldr r3, [pc, #184] ; (8007904 ) + 800784c: f44f 72ce mov.w r2, #412 ; 0x19c + 8007850: 492d ldr r1, [pc, #180] ; (8007908 ) + 8007852: 482e ldr r0, [pc, #184] ; (800790c ) + 8007854: f009 f9b8 bl 8010bc8 + + switch (pcb->state) { + 8007858: 687b ldr r3, [r7, #4] + 800785a: 7d1b ldrb r3, [r3, #20] + 800785c: 2b07 cmp r3, #7 + 800785e: d020 beq.n 80078a2 + 8007860: 2b07 cmp r3, #7 + 8007862: dc2b bgt.n 80078bc + 8007864: 2b03 cmp r3, #3 + 8007866: d002 beq.n 800786e + 8007868: 2b04 cmp r3, #4 + 800786a: d00d beq.n 8007888 + 800786c: e026 b.n 80078bc + case SYN_RCVD: + err = tcp_send_fin(pcb); + 800786e: 6878 ldr r0, [r7, #4] + 8007870: f004 fd82 bl 800c378 + 8007874: 4603 mov r3, r0 + 8007876: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 8007878: f997 300f ldrsb.w r3, [r7, #15] + 800787c: 2b00 cmp r3, #0 + 800787e: d11f bne.n 80078c0 + tcp_backlog_accepted(pcb); + MIB2_STATS_INC(mib2.tcpattemptfails); + pcb->state = FIN_WAIT_1; + 8007880: 687b ldr r3, [r7, #4] + 8007882: 2205 movs r2, #5 + 8007884: 751a strb r2, [r3, #20] + } + break; + 8007886: e01b b.n 80078c0 + case ESTABLISHED: + err = tcp_send_fin(pcb); + 8007888: 6878 ldr r0, [r7, #4] + 800788a: f004 fd75 bl 800c378 + 800788e: 4603 mov r3, r0 + 8007890: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 8007892: f997 300f ldrsb.w r3, [r7, #15] + 8007896: 2b00 cmp r3, #0 + 8007898: d114 bne.n 80078c4 + MIB2_STATS_INC(mib2.tcpestabresets); + pcb->state = FIN_WAIT_1; + 800789a: 687b ldr r3, [r7, #4] + 800789c: 2205 movs r2, #5 + 800789e: 751a strb r2, [r3, #20] + } + break; + 80078a0: e010 b.n 80078c4 + case CLOSE_WAIT: + err = tcp_send_fin(pcb); + 80078a2: 6878 ldr r0, [r7, #4] + 80078a4: f004 fd68 bl 800c378 + 80078a8: 4603 mov r3, r0 + 80078aa: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 80078ac: f997 300f ldrsb.w r3, [r7, #15] + 80078b0: 2b00 cmp r3, #0 + 80078b2: d109 bne.n 80078c8 + MIB2_STATS_INC(mib2.tcpestabresets); + pcb->state = LAST_ACK; + 80078b4: 687b ldr r3, [r7, #4] + 80078b6: 2209 movs r2, #9 + 80078b8: 751a strb r2, [r3, #20] + } + break; + 80078ba: e005 b.n 80078c8 + default: + /* Has already been closed, do nothing. */ + return ERR_OK; + 80078bc: 2300 movs r3, #0 + 80078be: e01c b.n 80078fa + break; + 80078c0: bf00 nop + 80078c2: e002 b.n 80078ca + break; + 80078c4: bf00 nop + 80078c6: e000 b.n 80078ca + break; + 80078c8: bf00 nop + } + + if (err == ERR_OK) { + 80078ca: f997 300f ldrsb.w r3, [r7, #15] + 80078ce: 2b00 cmp r3, #0 + 80078d0: d103 bne.n 80078da + /* To ensure all data has been sent when tcp_close returns, we have + to make sure tcp_output doesn't fail. + Since we don't really have to ensure all data has been sent when tcp_close + returns (unsent data is sent from tcp timer functions, also), we don't care + for the return value of tcp_output for now. */ + tcp_output(pcb); + 80078d2: 6878 ldr r0, [r7, #4] + 80078d4: f004 fe8e bl 800c5f4 + 80078d8: e00d b.n 80078f6 + } else if (err == ERR_MEM) { + 80078da: f997 300f ldrsb.w r3, [r7, #15] + 80078de: f1b3 3fff cmp.w r3, #4294967295 + 80078e2: d108 bne.n 80078f6 + /* Mark this pcb for closing. Closing is retried from tcp_tmr. */ + tcp_set_flags(pcb, TF_CLOSEPEND); + 80078e4: 687b ldr r3, [r7, #4] + 80078e6: 8b5b ldrh r3, [r3, #26] + 80078e8: f043 0308 orr.w r3, r3, #8 + 80078ec: b29a uxth r2, r3 + 80078ee: 687b ldr r3, [r7, #4] + 80078f0: 835a strh r2, [r3, #26] + /* We have to return ERR_OK from here to indicate to the callers that this + pcb should not be used any more as it will be freed soon via tcp_tmr. + This is OK here since sending FIN does not guarantee a time frime for + actually freeing the pcb, either (it is left in closure states for + remote ACK or timeout) */ + return ERR_OK; + 80078f2: 2300 movs r3, #0 + 80078f4: e001 b.n 80078fa + } + return err; + 80078f6: f997 300f ldrsb.w r3, [r7, #15] +} + 80078fa: 4618 mov r0, r3 + 80078fc: 3710 adds r7, #16 + 80078fe: 46bd mov sp, r7 + 8007900: bd80 pop {r7, pc} + 8007902: bf00 nop + 8007904: 08012a08 .word 0x08012a08 + 8007908: 08012ab8 .word 0x08012ab8 + 800790c: 08012a4c .word 0x08012a4c + +08007910 : + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +err_t +tcp_close(struct tcp_pcb *pcb) +{ + 8007910: b580 push {r7, lr} + 8007912: b082 sub sp, #8 + 8007914: af00 add r7, sp, #0 + 8007916: 6078 str r0, [r7, #4] + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG); + 8007918: 687b ldr r3, [r7, #4] + 800791a: 2b00 cmp r3, #0 + 800791c: d109 bne.n 8007932 + 800791e: 4b0f ldr r3, [pc, #60] ; (800795c ) + 8007920: f44f 72f4 mov.w r2, #488 ; 0x1e8 + 8007924: 490e ldr r1, [pc, #56] ; (8007960 ) + 8007926: 480f ldr r0, [pc, #60] ; (8007964 ) + 8007928: f009 f94e bl 8010bc8 + 800792c: f06f 030f mvn.w r3, #15 + 8007930: e00f b.n 8007952 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); + + tcp_debug_print_state(pcb->state); + + if (pcb->state != LISTEN) { + 8007932: 687b ldr r3, [r7, #4] + 8007934: 7d1b ldrb r3, [r3, #20] + 8007936: 2b01 cmp r3, #1 + 8007938: d006 beq.n 8007948 + /* Set a flag not to receive any more data... */ + tcp_set_flags(pcb, TF_RXCLOSED); + 800793a: 687b ldr r3, [r7, #4] + 800793c: 8b5b ldrh r3, [r3, #26] + 800793e: f043 0310 orr.w r3, r3, #16 + 8007942: b29a uxth r2, r3 + 8007944: 687b ldr r3, [r7, #4] + 8007946: 835a strh r2, [r3, #26] + } + /* ... and close */ + return tcp_close_shutdown(pcb, 1); + 8007948: 2101 movs r1, #1 + 800794a: 6878 ldr r0, [r7, #4] + 800794c: f7ff fe94 bl 8007678 + 8007950: 4603 mov r3, r0 +} + 8007952: 4618 mov r0, r3 + 8007954: 3708 adds r7, #8 + 8007956: 46bd mov sp, r7 + 8007958: bd80 pop {r7, pc} + 800795a: bf00 nop + 800795c: 08012a08 .word 0x08012a08 + 8007960: 08012b18 .word 0x08012b18 + 8007964: 08012a4c .word 0x08012a4c + +08007968 : + * @param pcb the tcp_pcb to abort + * @param reset boolean to indicate whether a reset should be sent + */ +void +tcp_abandon(struct tcp_pcb *pcb, int reset) +{ + 8007968: b580 push {r7, lr} + 800796a: b08e sub sp, #56 ; 0x38 + 800796c: af04 add r7, sp, #16 + 800796e: 6078 str r0, [r7, #4] + 8007970: 6039 str r1, [r7, #0] +#endif /* LWIP_CALLBACK_API */ + void *errf_arg; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return); + 8007972: 687b ldr r3, [r7, #4] + 8007974: 2b00 cmp r3, #0 + 8007976: d107 bne.n 8007988 + 8007978: 4b52 ldr r3, [pc, #328] ; (8007ac4 ) + 800797a: f240 223d movw r2, #573 ; 0x23d + 800797e: 4952 ldr r1, [pc, #328] ; (8007ac8 ) + 8007980: 4852 ldr r0, [pc, #328] ; (8007acc ) + 8007982: f009 f921 bl 8010bc8 + 8007986: e099 b.n 8007abc + + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs", + 8007988: 687b ldr r3, [r7, #4] + 800798a: 7d1b ldrb r3, [r3, #20] + 800798c: 2b01 cmp r3, #1 + 800798e: d106 bne.n 800799e + 8007990: 4b4c ldr r3, [pc, #304] ; (8007ac4 ) + 8007992: f44f 7210 mov.w r2, #576 ; 0x240 + 8007996: 494e ldr r1, [pc, #312] ; (8007ad0 ) + 8007998: 484c ldr r0, [pc, #304] ; (8007acc ) + 800799a: f009 f915 bl 8010bc8 + pcb->state != LISTEN); + /* Figure out on which TCP PCB list we are, and remove us. If we + are in an active state, call the receive function associated with + the PCB with a NULL argument, and send an RST to the remote end. */ + if (pcb->state == TIME_WAIT) { + 800799e: 687b ldr r3, [r7, #4] + 80079a0: 7d1b ldrb r3, [r3, #20] + 80079a2: 2b0a cmp r3, #10 + 80079a4: d107 bne.n 80079b6 + tcp_pcb_remove(&tcp_tw_pcbs, pcb); + 80079a6: 6879 ldr r1, [r7, #4] + 80079a8: 484a ldr r0, [pc, #296] ; (8007ad4 ) + 80079aa: f001 f9a1 bl 8008cf0 + tcp_free(pcb); + 80079ae: 6878 ldr r0, [r7, #4] + 80079b0: f7ff fdb0 bl 8007514 + 80079b4: e082 b.n 8007abc + } else { + int send_rst = 0; + 80079b6: 2300 movs r3, #0 + 80079b8: 627b str r3, [r7, #36] ; 0x24 + u16_t local_port = 0; + 80079ba: 2300 movs r3, #0 + 80079bc: 847b strh r3, [r7, #34] ; 0x22 + enum tcp_state last_state; + seqno = pcb->snd_nxt; + 80079be: 687b ldr r3, [r7, #4] + 80079c0: 6d1b ldr r3, [r3, #80] ; 0x50 + 80079c2: 61bb str r3, [r7, #24] + ackno = pcb->rcv_nxt; + 80079c4: 687b ldr r3, [r7, #4] + 80079c6: 6a5b ldr r3, [r3, #36] ; 0x24 + 80079c8: 617b str r3, [r7, #20] +#if LWIP_CALLBACK_API + errf = pcb->errf; + 80079ca: 687b ldr r3, [r7, #4] + 80079cc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80079d0: 613b str r3, [r7, #16] +#endif /* LWIP_CALLBACK_API */ + errf_arg = pcb->callback_arg; + 80079d2: 687b ldr r3, [r7, #4] + 80079d4: 691b ldr r3, [r3, #16] + 80079d6: 60fb str r3, [r7, #12] + if (pcb->state == CLOSED) { + 80079d8: 687b ldr r3, [r7, #4] + 80079da: 7d1b ldrb r3, [r3, #20] + 80079dc: 2b00 cmp r3, #0 + 80079de: d126 bne.n 8007a2e + if (pcb->local_port != 0) { + 80079e0: 687b ldr r3, [r7, #4] + 80079e2: 8adb ldrh r3, [r3, #22] + 80079e4: 2b00 cmp r3, #0 + 80079e6: d02e beq.n 8007a46 + /* bound, not yet opened */ + TCP_RMV(&tcp_bound_pcbs, pcb); + 80079e8: 4b3b ldr r3, [pc, #236] ; (8007ad8 ) + 80079ea: 681b ldr r3, [r3, #0] + 80079ec: 687a ldr r2, [r7, #4] + 80079ee: 429a cmp r2, r3 + 80079f0: d105 bne.n 80079fe + 80079f2: 4b39 ldr r3, [pc, #228] ; (8007ad8 ) + 80079f4: 681b ldr r3, [r3, #0] + 80079f6: 68db ldr r3, [r3, #12] + 80079f8: 4a37 ldr r2, [pc, #220] ; (8007ad8 ) + 80079fa: 6013 str r3, [r2, #0] + 80079fc: e013 b.n 8007a26 + 80079fe: 4b36 ldr r3, [pc, #216] ; (8007ad8 ) + 8007a00: 681b ldr r3, [r3, #0] + 8007a02: 61fb str r3, [r7, #28] + 8007a04: e00c b.n 8007a20 + 8007a06: 69fb ldr r3, [r7, #28] + 8007a08: 68db ldr r3, [r3, #12] + 8007a0a: 687a ldr r2, [r7, #4] + 8007a0c: 429a cmp r2, r3 + 8007a0e: d104 bne.n 8007a1a + 8007a10: 687b ldr r3, [r7, #4] + 8007a12: 68da ldr r2, [r3, #12] + 8007a14: 69fb ldr r3, [r7, #28] + 8007a16: 60da str r2, [r3, #12] + 8007a18: e005 b.n 8007a26 + 8007a1a: 69fb ldr r3, [r7, #28] + 8007a1c: 68db ldr r3, [r3, #12] + 8007a1e: 61fb str r3, [r7, #28] + 8007a20: 69fb ldr r3, [r7, #28] + 8007a22: 2b00 cmp r3, #0 + 8007a24: d1ef bne.n 8007a06 + 8007a26: 687b ldr r3, [r7, #4] + 8007a28: 2200 movs r2, #0 + 8007a2a: 60da str r2, [r3, #12] + 8007a2c: e00b b.n 8007a46 + } + } else { + send_rst = reset; + 8007a2e: 683b ldr r3, [r7, #0] + 8007a30: 627b str r3, [r7, #36] ; 0x24 + local_port = pcb->local_port; + 8007a32: 687b ldr r3, [r7, #4] + 8007a34: 8adb ldrh r3, [r3, #22] + 8007a36: 847b strh r3, [r7, #34] ; 0x22 + TCP_PCB_REMOVE_ACTIVE(pcb); + 8007a38: 6879 ldr r1, [r7, #4] + 8007a3a: 4828 ldr r0, [pc, #160] ; (8007adc ) + 8007a3c: f001 f958 bl 8008cf0 + 8007a40: 4b27 ldr r3, [pc, #156] ; (8007ae0 ) + 8007a42: 2201 movs r2, #1 + 8007a44: 701a strb r2, [r3, #0] + } + if (pcb->unacked != NULL) { + 8007a46: 687b ldr r3, [r7, #4] + 8007a48: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007a4a: 2b00 cmp r3, #0 + 8007a4c: d004 beq.n 8007a58 + tcp_segs_free(pcb->unacked); + 8007a4e: 687b ldr r3, [r7, #4] + 8007a50: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007a52: 4618 mov r0, r3 + 8007a54: f000 fe7a bl 800874c + } + if (pcb->unsent != NULL) { + 8007a58: 687b ldr r3, [r7, #4] + 8007a5a: 6edb ldr r3, [r3, #108] ; 0x6c + 8007a5c: 2b00 cmp r3, #0 + 8007a5e: d004 beq.n 8007a6a + tcp_segs_free(pcb->unsent); + 8007a60: 687b ldr r3, [r7, #4] + 8007a62: 6edb ldr r3, [r3, #108] ; 0x6c + 8007a64: 4618 mov r0, r3 + 8007a66: f000 fe71 bl 800874c + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + 8007a6a: 687b ldr r3, [r7, #4] + 8007a6c: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007a6e: 2b00 cmp r3, #0 + 8007a70: d004 beq.n 8007a7c + tcp_segs_free(pcb->ooseq); + 8007a72: 687b ldr r3, [r7, #4] + 8007a74: 6f5b ldr r3, [r3, #116] ; 0x74 + 8007a76: 4618 mov r0, r3 + 8007a78: f000 fe68 bl 800874c + } +#endif /* TCP_QUEUE_OOSEQ */ + tcp_backlog_accepted(pcb); + if (send_rst) { + 8007a7c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007a7e: 2b00 cmp r3, #0 + 8007a80: d00e beq.n 8007aa0 + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); + tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port); + 8007a82: 6879 ldr r1, [r7, #4] + 8007a84: 687b ldr r3, [r7, #4] + 8007a86: 3304 adds r3, #4 + 8007a88: 687a ldr r2, [r7, #4] + 8007a8a: 8b12 ldrh r2, [r2, #24] + 8007a8c: 9202 str r2, [sp, #8] + 8007a8e: 8c7a ldrh r2, [r7, #34] ; 0x22 + 8007a90: 9201 str r2, [sp, #4] + 8007a92: 9300 str r3, [sp, #0] + 8007a94: 460b mov r3, r1 + 8007a96: 697a ldr r2, [r7, #20] + 8007a98: 69b9 ldr r1, [r7, #24] + 8007a9a: 6878 ldr r0, [r7, #4] + 8007a9c: f005 fb6a bl 800d174 + } + last_state = pcb->state; + 8007aa0: 687b ldr r3, [r7, #4] + 8007aa2: 7d1b ldrb r3, [r3, #20] + 8007aa4: 72fb strb r3, [r7, #11] + tcp_free(pcb); + 8007aa6: 6878 ldr r0, [r7, #4] + 8007aa8: f7ff fd34 bl 8007514 + TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT); + 8007aac: 693b ldr r3, [r7, #16] + 8007aae: 2b00 cmp r3, #0 + 8007ab0: d004 beq.n 8007abc + 8007ab2: 693b ldr r3, [r7, #16] + 8007ab4: f06f 010c mvn.w r1, #12 + 8007ab8: 68f8 ldr r0, [r7, #12] + 8007aba: 4798 blx r3 + } +} + 8007abc: 3728 adds r7, #40 ; 0x28 + 8007abe: 46bd mov sp, r7 + 8007ac0: bd80 pop {r7, pc} + 8007ac2: bf00 nop + 8007ac4: 08012a08 .word 0x08012a08 + 8007ac8: 08012b4c .word 0x08012b4c + 8007acc: 08012a4c .word 0x08012a4c + 8007ad0: 08012b68 .word 0x08012b68 + 8007ad4: 24007b7c .word 0x24007b7c + 8007ad8: 24007b70 .word 0x24007b70 + 8007adc: 24007b78 .word 0x24007b78 + 8007ae0: 24007b80 .word 0x24007b80 + +08007ae4 : + * + * @param pcb the tcp pcb to abort + */ +void +tcp_abort(struct tcp_pcb *pcb) +{ + 8007ae4: b580 push {r7, lr} + 8007ae6: b082 sub sp, #8 + 8007ae8: af00 add r7, sp, #0 + 8007aea: 6078 str r0, [r7, #4] + tcp_abandon(pcb, 1); + 8007aec: 2101 movs r1, #1 + 8007aee: 6878 ldr r0, [r7, #4] + 8007af0: f7ff ff3a bl 8007968 +} + 8007af4: bf00 nop + 8007af6: 3708 adds r7, #8 + 8007af8: 46bd mov sp, r7 + 8007afa: bd80 pop {r7, pc} + +08007afc : + * Returns how much extra window would be advertised if we sent an + * update now. + */ +u32_t +tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) +{ + 8007afc: b580 push {r7, lr} + 8007afe: b084 sub sp, #16 + 8007b00: af00 add r7, sp, #0 + 8007b02: 6078 str r0, [r7, #4] + u32_t new_right_edge; + + LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL); + 8007b04: 687b ldr r3, [r7, #4] + 8007b06: 2b00 cmp r3, #0 + 8007b08: d106 bne.n 8007b18 + 8007b0a: 4b25 ldr r3, [pc, #148] ; (8007ba0 ) + 8007b0c: f240 32a6 movw r2, #934 ; 0x3a6 + 8007b10: 4924 ldr r1, [pc, #144] ; (8007ba4 ) + 8007b12: 4825 ldr r0, [pc, #148] ; (8007ba8 ) + 8007b14: f009 f858 bl 8010bc8 + new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; + 8007b18: 687b ldr r3, [r7, #4] + 8007b1a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8007b1c: 687a ldr r2, [r7, #4] + 8007b1e: 8d12 ldrh r2, [r2, #40] ; 0x28 + 8007b20: 4413 add r3, r2 + 8007b22: 60fb str r3, [r7, #12] + + if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { + 8007b24: 687b ldr r3, [r7, #4] + 8007b26: 6adb ldr r3, [r3, #44] ; 0x2c + 8007b28: 687a ldr r2, [r7, #4] + 8007b2a: 8e52 ldrh r2, [r2, #50] ; 0x32 + 8007b2c: f5b2 6f86 cmp.w r2, #1072 ; 0x430 + 8007b30: bf28 it cs + 8007b32: f44f 6286 movcs.w r2, #1072 ; 0x430 + 8007b36: b292 uxth r2, r2 + 8007b38: 4413 add r3, r2 + 8007b3a: 68fa ldr r2, [r7, #12] + 8007b3c: 1ad3 subs r3, r2, r3 + 8007b3e: 2b00 cmp r3, #0 + 8007b40: db08 blt.n 8007b54 + /* we can advertise more window */ + pcb->rcv_ann_wnd = pcb->rcv_wnd; + 8007b42: 687b ldr r3, [r7, #4] + 8007b44: 8d1a ldrh r2, [r3, #40] ; 0x28 + 8007b46: 687b ldr r3, [r7, #4] + 8007b48: 855a strh r2, [r3, #42] ; 0x2a + return new_right_edge - pcb->rcv_ann_right_edge; + 8007b4a: 687b ldr r3, [r7, #4] + 8007b4c: 6adb ldr r3, [r3, #44] ; 0x2c + 8007b4e: 68fa ldr r2, [r7, #12] + 8007b50: 1ad3 subs r3, r2, r3 + 8007b52: e020 b.n 8007b96 + } else { + if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { + 8007b54: 687b ldr r3, [r7, #4] + 8007b56: 6a5a ldr r2, [r3, #36] ; 0x24 + 8007b58: 687b ldr r3, [r7, #4] + 8007b5a: 6adb ldr r3, [r3, #44] ; 0x2c + 8007b5c: 1ad3 subs r3, r2, r3 + 8007b5e: 2b00 cmp r3, #0 + 8007b60: dd03 ble.n 8007b6a + /* Can happen due to other end sending out of advertised window, + * but within actual available (but not yet advertised) window */ + pcb->rcv_ann_wnd = 0; + 8007b62: 687b ldr r3, [r7, #4] + 8007b64: 2200 movs r2, #0 + 8007b66: 855a strh r2, [r3, #42] ; 0x2a + 8007b68: e014 b.n 8007b94 + } else { + /* keep the right edge of window constant */ + u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; + 8007b6a: 687b ldr r3, [r7, #4] + 8007b6c: 6ada ldr r2, [r3, #44] ; 0x2c + 8007b6e: 687b ldr r3, [r7, #4] + 8007b70: 6a5b ldr r3, [r3, #36] ; 0x24 + 8007b72: 1ad3 subs r3, r2, r3 + 8007b74: 60bb str r3, [r7, #8] +#if !LWIP_WND_SCALE + LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff); + 8007b76: 68bb ldr r3, [r7, #8] + 8007b78: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8007b7c: d306 bcc.n 8007b8c + 8007b7e: 4b08 ldr r3, [pc, #32] ; (8007ba0 ) + 8007b80: f240 32b6 movw r2, #950 ; 0x3b6 + 8007b84: 4909 ldr r1, [pc, #36] ; (8007bac ) + 8007b86: 4808 ldr r0, [pc, #32] ; (8007ba8 ) + 8007b88: f009 f81e bl 8010bc8 +#endif + pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd; + 8007b8c: 68bb ldr r3, [r7, #8] + 8007b8e: b29a uxth r2, r3 + 8007b90: 687b ldr r3, [r7, #4] + 8007b92: 855a strh r2, [r3, #42] ; 0x2a + } + return 0; + 8007b94: 2300 movs r3, #0 + } +} + 8007b96: 4618 mov r0, r3 + 8007b98: 3710 adds r7, #16 + 8007b9a: 46bd mov sp, r7 + 8007b9c: bd80 pop {r7, pc} + 8007b9e: bf00 nop + 8007ba0: 08012a08 .word 0x08012a08 + 8007ba4: 08012c64 .word 0x08012c64 + 8007ba8: 08012a4c .word 0x08012a4c + 8007bac: 08012c88 .word 0x08012c88 + +08007bb0 : + * @param pcb the tcp_pcb for which data is read + * @param len the amount of bytes that have been read by the application + */ +void +tcp_recved(struct tcp_pcb *pcb, u16_t len) +{ + 8007bb0: b580 push {r7, lr} + 8007bb2: b084 sub sp, #16 + 8007bb4: af00 add r7, sp, #0 + 8007bb6: 6078 str r0, [r7, #4] + 8007bb8: 460b mov r3, r1 + 8007bba: 807b strh r3, [r7, #2] + u32_t wnd_inflation; + tcpwnd_size_t rcv_wnd; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return); + 8007bbc: 687b ldr r3, [r7, #4] + 8007bbe: 2b00 cmp r3, #0 + 8007bc0: d107 bne.n 8007bd2 + 8007bc2: 4b1f ldr r3, [pc, #124] ; (8007c40 ) + 8007bc4: f240 32cf movw r2, #975 ; 0x3cf + 8007bc8: 491e ldr r1, [pc, #120] ; (8007c44 ) + 8007bca: 481f ldr r0, [pc, #124] ; (8007c48 ) + 8007bcc: f008 fffc bl 8010bc8 + 8007bd0: e032 b.n 8007c38 + + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_recved for listen-pcbs", + 8007bd2: 687b ldr r3, [r7, #4] + 8007bd4: 7d1b ldrb r3, [r3, #20] + 8007bd6: 2b01 cmp r3, #1 + 8007bd8: d106 bne.n 8007be8 + 8007bda: 4b19 ldr r3, [pc, #100] ; (8007c40 ) + 8007bdc: f240 32d2 movw r2, #978 ; 0x3d2 + 8007be0: 491a ldr r1, [pc, #104] ; (8007c4c ) + 8007be2: 4819 ldr r0, [pc, #100] ; (8007c48 ) + 8007be4: f008 fff0 bl 8010bc8 + pcb->state != LISTEN); + + rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len); + 8007be8: 687b ldr r3, [r7, #4] + 8007bea: 8d1a ldrh r2, [r3, #40] ; 0x28 + 8007bec: 887b ldrh r3, [r7, #2] + 8007bee: 4413 add r3, r2 + 8007bf0: 81fb strh r3, [r7, #14] + if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) { + 8007bf2: 89fb ldrh r3, [r7, #14] + 8007bf4: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 8007bf8: d804 bhi.n 8007c04 + 8007bfa: 687b ldr r3, [r7, #4] + 8007bfc: 8d1b ldrh r3, [r3, #40] ; 0x28 + 8007bfe: 89fa ldrh r2, [r7, #14] + 8007c00: 429a cmp r2, r3 + 8007c02: d204 bcs.n 8007c0e + /* window got too big or tcpwnd_size_t overflow */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n")); + pcb->rcv_wnd = TCP_WND_MAX(pcb); + 8007c04: 687b ldr r3, [r7, #4] + 8007c06: f44f 6206 mov.w r2, #2144 ; 0x860 + 8007c0a: 851a strh r2, [r3, #40] ; 0x28 + 8007c0c: e002 b.n 8007c14 + } else { + pcb->rcv_wnd = rcv_wnd; + 8007c0e: 687b ldr r3, [r7, #4] + 8007c10: 89fa ldrh r2, [r7, #14] + 8007c12: 851a strh r2, [r3, #40] ; 0x28 + } + + wnd_inflation = tcp_update_rcv_ann_wnd(pcb); + 8007c14: 6878 ldr r0, [r7, #4] + 8007c16: f7ff ff71 bl 8007afc + 8007c1a: 60b8 str r0, [r7, #8] + + /* If the change in the right edge of window is significant (default + * watermark is TCP_WND/4), then send an explicit update now. + * Otherwise wait for a packet to be sent in the normal course of + * events (or more window to be available later) */ + if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) { + 8007c1c: 68bb ldr r3, [r7, #8] + 8007c1e: f5b3 7f06 cmp.w r3, #536 ; 0x218 + 8007c22: d309 bcc.n 8007c38 + tcp_ack_now(pcb); + 8007c24: 687b ldr r3, [r7, #4] + 8007c26: 8b5b ldrh r3, [r3, #26] + 8007c28: f043 0302 orr.w r3, r3, #2 + 8007c2c: b29a uxth r2, r3 + 8007c2e: 687b ldr r3, [r7, #4] + 8007c30: 835a strh r2, [r3, #26] + tcp_output(pcb); + 8007c32: 6878 ldr r0, [r7, #4] + 8007c34: f004 fcde bl 800c5f4 + } + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n", + len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd))); +} + 8007c38: 3710 adds r7, #16 + 8007c3a: 46bd mov sp, r7 + 8007c3c: bd80 pop {r7, pc} + 8007c3e: bf00 nop + 8007c40: 08012a08 .word 0x08012a08 + 8007c44: 08012ca4 .word 0x08012ca4 + 8007c48: 08012a4c .word 0x08012a4c + 8007c4c: 08012cbc .word 0x08012cbc + +08007c50 : + * + * @return a new (free) local TCP port number + */ +static u16_t +tcp_new_port(void) +{ + 8007c50: b480 push {r7} + 8007c52: b083 sub sp, #12 + 8007c54: af00 add r7, sp, #0 + u8_t i; + u16_t n = 0; + 8007c56: 2300 movs r3, #0 + 8007c58: 80bb strh r3, [r7, #4] + struct tcp_pcb *pcb; + +again: + tcp_port++; + 8007c5a: 4b1e ldr r3, [pc, #120] ; (8007cd4 ) + 8007c5c: 881b ldrh r3, [r3, #0] + 8007c5e: 3301 adds r3, #1 + 8007c60: b29a uxth r2, r3 + 8007c62: 4b1c ldr r3, [pc, #112] ; (8007cd4 ) + 8007c64: 801a strh r2, [r3, #0] + if (tcp_port == TCP_LOCAL_PORT_RANGE_END) { + 8007c66: 4b1b ldr r3, [pc, #108] ; (8007cd4 ) + 8007c68: 881b ldrh r3, [r3, #0] + 8007c6a: f64f 72ff movw r2, #65535 ; 0xffff + 8007c6e: 4293 cmp r3, r2 + 8007c70: d103 bne.n 8007c7a + tcp_port = TCP_LOCAL_PORT_RANGE_START; + 8007c72: 4b18 ldr r3, [pc, #96] ; (8007cd4 ) + 8007c74: f44f 4240 mov.w r2, #49152 ; 0xc000 + 8007c78: 801a strh r2, [r3, #0] + } + /* Check all PCB lists. */ + for (i = 0; i < NUM_TCP_PCB_LISTS; i++) { + 8007c7a: 2300 movs r3, #0 + 8007c7c: 71fb strb r3, [r7, #7] + 8007c7e: e01e b.n 8007cbe + for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) { + 8007c80: 79fb ldrb r3, [r7, #7] + 8007c82: 4a15 ldr r2, [pc, #84] ; (8007cd8 ) + 8007c84: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8007c88: 681b ldr r3, [r3, #0] + 8007c8a: 603b str r3, [r7, #0] + 8007c8c: e011 b.n 8007cb2 + if (pcb->local_port == tcp_port) { + 8007c8e: 683b ldr r3, [r7, #0] + 8007c90: 8ada ldrh r2, [r3, #22] + 8007c92: 4b10 ldr r3, [pc, #64] ; (8007cd4 ) + 8007c94: 881b ldrh r3, [r3, #0] + 8007c96: 429a cmp r2, r3 + 8007c98: d108 bne.n 8007cac + n++; + 8007c9a: 88bb ldrh r3, [r7, #4] + 8007c9c: 3301 adds r3, #1 + 8007c9e: 80bb strh r3, [r7, #4] + if (n > (TCP_LOCAL_PORT_RANGE_END - TCP_LOCAL_PORT_RANGE_START)) { + 8007ca0: 88bb ldrh r3, [r7, #4] + 8007ca2: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8007ca6: d3d8 bcc.n 8007c5a + return 0; + 8007ca8: 2300 movs r3, #0 + 8007caa: e00d b.n 8007cc8 + for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) { + 8007cac: 683b ldr r3, [r7, #0] + 8007cae: 68db ldr r3, [r3, #12] + 8007cb0: 603b str r3, [r7, #0] + 8007cb2: 683b ldr r3, [r7, #0] + 8007cb4: 2b00 cmp r3, #0 + 8007cb6: d1ea bne.n 8007c8e + for (i = 0; i < NUM_TCP_PCB_LISTS; i++) { + 8007cb8: 79fb ldrb r3, [r7, #7] + 8007cba: 3301 adds r3, #1 + 8007cbc: 71fb strb r3, [r7, #7] + 8007cbe: 79fb ldrb r3, [r7, #7] + 8007cc0: 2b03 cmp r3, #3 + 8007cc2: d9dd bls.n 8007c80 + } + goto again; + } + } + } + return tcp_port; + 8007cc4: 4b03 ldr r3, [pc, #12] ; (8007cd4 ) + 8007cc6: 881b ldrh r3, [r3, #0] +} + 8007cc8: 4618 mov r0, r3 + 8007cca: 370c adds r7, #12 + 8007ccc: 46bd mov sp, r7 + 8007cce: f85d 7b04 ldr.w r7, [sp], #4 + 8007cd2: 4770 bx lr + 8007cd4: 24000068 .word 0x24000068 + 8007cd8: 08014d6c .word 0x08014d6c + +08007cdc : + * other err_t values if connect request couldn't be sent + */ +err_t +tcp_connect(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port, + tcp_connected_fn connected) +{ + 8007cdc: b580 push {r7, lr} + 8007cde: b08a sub sp, #40 ; 0x28 + 8007ce0: af00 add r7, sp, #0 + 8007ce2: 60f8 str r0, [r7, #12] + 8007ce4: 60b9 str r1, [r7, #8] + 8007ce6: 603b str r3, [r7, #0] + 8007ce8: 4613 mov r3, r2 + 8007cea: 80fb strh r3, [r7, #6] + struct netif *netif = NULL; + 8007cec: 2300 movs r3, #0 + 8007cee: 627b str r3, [r7, #36] ; 0x24 + u32_t iss; + u16_t old_local_port; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_connect: invalid pcb", pcb != NULL, return ERR_ARG); + 8007cf0: 68fb ldr r3, [r7, #12] + 8007cf2: 2b00 cmp r3, #0 + 8007cf4: d109 bne.n 8007d0a + 8007cf6: 4b7d ldr r3, [pc, #500] ; (8007eec ) + 8007cf8: f240 4235 movw r2, #1077 ; 0x435 + 8007cfc: 497c ldr r1, [pc, #496] ; (8007ef0 ) + 8007cfe: 487d ldr r0, [pc, #500] ; (8007ef4 ) + 8007d00: f008 ff62 bl 8010bc8 + 8007d04: f06f 030f mvn.w r3, #15 + 8007d08: e0ec b.n 8007ee4 + LWIP_ERROR("tcp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG); + 8007d0a: 68bb ldr r3, [r7, #8] + 8007d0c: 2b00 cmp r3, #0 + 8007d0e: d109 bne.n 8007d24 + 8007d10: 4b76 ldr r3, [pc, #472] ; (8007eec ) + 8007d12: f240 4236 movw r2, #1078 ; 0x436 + 8007d16: 4978 ldr r1, [pc, #480] ; (8007ef8 ) + 8007d18: 4876 ldr r0, [pc, #472] ; (8007ef4 ) + 8007d1a: f008 ff55 bl 8010bc8 + 8007d1e: f06f 030f mvn.w r3, #15 + 8007d22: e0df b.n 8007ee4 + + LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); + 8007d24: 68fb ldr r3, [r7, #12] + 8007d26: 7d1b ldrb r3, [r3, #20] + 8007d28: 2b00 cmp r3, #0 + 8007d2a: d009 beq.n 8007d40 + 8007d2c: 4b6f ldr r3, [pc, #444] ; (8007eec ) + 8007d2e: f44f 6287 mov.w r2, #1080 ; 0x438 + 8007d32: 4972 ldr r1, [pc, #456] ; (8007efc ) + 8007d34: 486f ldr r0, [pc, #444] ; (8007ef4 ) + 8007d36: f008 ff47 bl 8010bc8 + 8007d3a: f06f 0309 mvn.w r3, #9 + 8007d3e: e0d1 b.n 8007ee4 + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); + ip_addr_set(&pcb->remote_ip, ipaddr); + 8007d40: 68bb ldr r3, [r7, #8] + 8007d42: 2b00 cmp r3, #0 + 8007d44: d002 beq.n 8007d4c + 8007d46: 68bb ldr r3, [r7, #8] + 8007d48: 681b ldr r3, [r3, #0] + 8007d4a: e000 b.n 8007d4e + 8007d4c: 2300 movs r3, #0 + 8007d4e: 68fa ldr r2, [r7, #12] + 8007d50: 6053 str r3, [r2, #4] + pcb->remote_port = port; + 8007d52: 68fb ldr r3, [r7, #12] + 8007d54: 88fa ldrh r2, [r7, #6] + 8007d56: 831a strh r2, [r3, #24] + + if (pcb->netif_idx != NETIF_NO_INDEX) { + 8007d58: 68fb ldr r3, [r7, #12] + 8007d5a: 7a1b ldrb r3, [r3, #8] + 8007d5c: 2b00 cmp r3, #0 + 8007d5e: d006 beq.n 8007d6e + netif = netif_get_by_index(pcb->netif_idx); + 8007d60: 68fb ldr r3, [r7, #12] + 8007d62: 7a1b ldrb r3, [r3, #8] + 8007d64: 4618 mov r0, r3 + 8007d66: f7fe fdd5 bl 8006914 + 8007d6a: 6278 str r0, [r7, #36] ; 0x24 + 8007d6c: e005 b.n 8007d7a + } else { + /* check if we have a route to the remote host */ + netif = ip_route(&pcb->local_ip, &pcb->remote_ip); + 8007d6e: 68fb ldr r3, [r7, #12] + 8007d70: 3304 adds r3, #4 + 8007d72: 4618 mov r0, r3 + 8007d74: f007 f888 bl 800ee88 + 8007d78: 6278 str r0, [r7, #36] ; 0x24 + } + if (netif == NULL) { + 8007d7a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007d7c: 2b00 cmp r3, #0 + 8007d7e: d102 bne.n 8007d86 + /* Don't even try to send a SYN packet if we have no route since that will fail. */ + return ERR_RTE; + 8007d80: f06f 0303 mvn.w r3, #3 + 8007d84: e0ae b.n 8007ee4 + } + + /* check if local IP has been assigned to pcb, if not, get one */ + if (ip_addr_isany(&pcb->local_ip)) { + 8007d86: 68fb ldr r3, [r7, #12] + 8007d88: 2b00 cmp r3, #0 + 8007d8a: d003 beq.n 8007d94 + 8007d8c: 68fb ldr r3, [r7, #12] + 8007d8e: 681b ldr r3, [r3, #0] + 8007d90: 2b00 cmp r3, #0 + 8007d92: d111 bne.n 8007db8 + const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, ipaddr); + 8007d94: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007d96: 2b00 cmp r3, #0 + 8007d98: d002 beq.n 8007da0 + 8007d9a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007d9c: 3304 adds r3, #4 + 8007d9e: e000 b.n 8007da2 + 8007da0: 2300 movs r3, #0 + 8007da2: 61fb str r3, [r7, #28] + if (local_ip == NULL) { + 8007da4: 69fb ldr r3, [r7, #28] + 8007da6: 2b00 cmp r3, #0 + 8007da8: d102 bne.n 8007db0 + return ERR_RTE; + 8007daa: f06f 0303 mvn.w r3, #3 + 8007dae: e099 b.n 8007ee4 + } + ip_addr_copy(pcb->local_ip, *local_ip); + 8007db0: 69fb ldr r3, [r7, #28] + 8007db2: 681a ldr r2, [r3, #0] + 8007db4: 68fb ldr r3, [r7, #12] + 8007db6: 601a str r2, [r3, #0] + ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST)) { + ip6_addr_assign_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST, netif); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + old_local_port = pcb->local_port; + 8007db8: 68fb ldr r3, [r7, #12] + 8007dba: 8adb ldrh r3, [r3, #22] + 8007dbc: 837b strh r3, [r7, #26] + if (pcb->local_port == 0) { + 8007dbe: 68fb ldr r3, [r7, #12] + 8007dc0: 8adb ldrh r3, [r3, #22] + 8007dc2: 2b00 cmp r3, #0 + 8007dc4: d10c bne.n 8007de0 + pcb->local_port = tcp_new_port(); + 8007dc6: f7ff ff43 bl 8007c50 + 8007dca: 4603 mov r3, r0 + 8007dcc: 461a mov r2, r3 + 8007dce: 68fb ldr r3, [r7, #12] + 8007dd0: 82da strh r2, [r3, #22] + if (pcb->local_port == 0) { + 8007dd2: 68fb ldr r3, [r7, #12] + 8007dd4: 8adb ldrh r3, [r3, #22] + 8007dd6: 2b00 cmp r3, #0 + 8007dd8: d102 bne.n 8007de0 + return ERR_BUF; + 8007dda: f06f 0301 mvn.w r3, #1 + 8007dde: e081 b.n 8007ee4 + } + } +#endif /* SO_REUSE */ + } + + iss = tcp_next_iss(pcb); + 8007de0: 68f8 ldr r0, [r7, #12] + 8007de2: f001 f819 bl 8008e18 + 8007de6: 6178 str r0, [r7, #20] + pcb->rcv_nxt = 0; + 8007de8: 68fb ldr r3, [r7, #12] + 8007dea: 2200 movs r2, #0 + 8007dec: 625a str r2, [r3, #36] ; 0x24 + pcb->snd_nxt = iss; + 8007dee: 68fb ldr r3, [r7, #12] + 8007df0: 697a ldr r2, [r7, #20] + 8007df2: 651a str r2, [r3, #80] ; 0x50 + pcb->lastack = iss - 1; + 8007df4: 697b ldr r3, [r7, #20] + 8007df6: 1e5a subs r2, r3, #1 + 8007df8: 68fb ldr r3, [r7, #12] + 8007dfa: 645a str r2, [r3, #68] ; 0x44 + pcb->snd_wl2 = iss - 1; + 8007dfc: 697b ldr r3, [r7, #20] + 8007dfe: 1e5a subs r2, r3, #1 + 8007e00: 68fb ldr r3, [r7, #12] + 8007e02: 659a str r2, [r3, #88] ; 0x58 + pcb->snd_lbb = iss - 1; + 8007e04: 697b ldr r3, [r7, #20] + 8007e06: 1e5a subs r2, r3, #1 + 8007e08: 68fb ldr r3, [r7, #12] + 8007e0a: 65da str r2, [r3, #92] ; 0x5c + /* Start with a window that does not need scaling. When window scaling is + enabled and used, the window is enlarged when both sides agree on scaling. */ + pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); + 8007e0c: 68fb ldr r3, [r7, #12] + 8007e0e: f44f 6206 mov.w r2, #2144 ; 0x860 + 8007e12: 855a strh r2, [r3, #42] ; 0x2a + 8007e14: 68fb ldr r3, [r7, #12] + 8007e16: 8d5a ldrh r2, [r3, #42] ; 0x2a + 8007e18: 68fb ldr r3, [r7, #12] + 8007e1a: 851a strh r2, [r3, #40] ; 0x28 + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + 8007e1c: 68fb ldr r3, [r7, #12] + 8007e1e: 6a5a ldr r2, [r3, #36] ; 0x24 + 8007e20: 68fb ldr r3, [r7, #12] + 8007e22: 62da str r2, [r3, #44] ; 0x2c + pcb->snd_wnd = TCP_WND; + 8007e24: 68fb ldr r3, [r7, #12] + 8007e26: f44f 6206 mov.w r2, #2144 ; 0x860 + 8007e2a: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = INITIAL_MSS; + 8007e2e: 68fb ldr r3, [r7, #12] + 8007e30: f44f 7206 mov.w r2, #536 ; 0x218 + 8007e34: 865a strh r2, [r3, #50] ; 0x32 +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss_netif(pcb->mss, netif, &pcb->remote_ip); + 8007e36: 68fb ldr r3, [r7, #12] + 8007e38: 8e58 ldrh r0, [r3, #50] ; 0x32 + 8007e3a: 68fb ldr r3, [r7, #12] + 8007e3c: 3304 adds r3, #4 + 8007e3e: 461a mov r2, r3 + 8007e40: 6a79 ldr r1, [r7, #36] ; 0x24 + 8007e42: f001 f80f bl 8008e64 + 8007e46: 4603 mov r3, r0 + 8007e48: 461a mov r2, r3 + 8007e4a: 68fb ldr r3, [r7, #12] + 8007e4c: 865a strh r2, [r3, #50] ; 0x32 +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + pcb->cwnd = 1; + 8007e4e: 68fb ldr r3, [r7, #12] + 8007e50: 2201 movs r2, #1 + 8007e52: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 +#if LWIP_CALLBACK_API + pcb->connected = connected; + 8007e56: 68fb ldr r3, [r7, #12] + 8007e58: 683a ldr r2, [r7, #0] + 8007e5a: f8c3 2088 str.w r2, [r3, #136] ; 0x88 +#else /* LWIP_CALLBACK_API */ + LWIP_UNUSED_ARG(connected); +#endif /* LWIP_CALLBACK_API */ + + /* Send a SYN together with the MSS option. */ + ret = tcp_enqueue_flags(pcb, TCP_SYN); + 8007e5e: 2102 movs r1, #2 + 8007e60: 68f8 ldr r0, [r7, #12] + 8007e62: f004 fad9 bl 800c418 + 8007e66: 4603 mov r3, r0 + 8007e68: 74fb strb r3, [r7, #19] + if (ret == ERR_OK) { + 8007e6a: f997 3013 ldrsb.w r3, [r7, #19] + 8007e6e: 2b00 cmp r3, #0 + 8007e70: d136 bne.n 8007ee0 + /* SYN segment was enqueued, changed the pcbs state now */ + pcb->state = SYN_SENT; + 8007e72: 68fb ldr r3, [r7, #12] + 8007e74: 2202 movs r2, #2 + 8007e76: 751a strb r2, [r3, #20] + if (old_local_port != 0) { + 8007e78: 8b7b ldrh r3, [r7, #26] + 8007e7a: 2b00 cmp r3, #0 + 8007e7c: d021 beq.n 8007ec2 + TCP_RMV(&tcp_bound_pcbs, pcb); + 8007e7e: 4b20 ldr r3, [pc, #128] ; (8007f00 ) + 8007e80: 681b ldr r3, [r3, #0] + 8007e82: 68fa ldr r2, [r7, #12] + 8007e84: 429a cmp r2, r3 + 8007e86: d105 bne.n 8007e94 + 8007e88: 4b1d ldr r3, [pc, #116] ; (8007f00 ) + 8007e8a: 681b ldr r3, [r3, #0] + 8007e8c: 68db ldr r3, [r3, #12] + 8007e8e: 4a1c ldr r2, [pc, #112] ; (8007f00 ) + 8007e90: 6013 str r3, [r2, #0] + 8007e92: e013 b.n 8007ebc + 8007e94: 4b1a ldr r3, [pc, #104] ; (8007f00 ) + 8007e96: 681b ldr r3, [r3, #0] + 8007e98: 623b str r3, [r7, #32] + 8007e9a: e00c b.n 8007eb6 + 8007e9c: 6a3b ldr r3, [r7, #32] + 8007e9e: 68db ldr r3, [r3, #12] + 8007ea0: 68fa ldr r2, [r7, #12] + 8007ea2: 429a cmp r2, r3 + 8007ea4: d104 bne.n 8007eb0 + 8007ea6: 68fb ldr r3, [r7, #12] + 8007ea8: 68da ldr r2, [r3, #12] + 8007eaa: 6a3b ldr r3, [r7, #32] + 8007eac: 60da str r2, [r3, #12] + 8007eae: e005 b.n 8007ebc + 8007eb0: 6a3b ldr r3, [r7, #32] + 8007eb2: 68db ldr r3, [r3, #12] + 8007eb4: 623b str r3, [r7, #32] + 8007eb6: 6a3b ldr r3, [r7, #32] + 8007eb8: 2b00 cmp r3, #0 + 8007eba: d1ef bne.n 8007e9c + 8007ebc: 68fb ldr r3, [r7, #12] + 8007ebe: 2200 movs r2, #0 + 8007ec0: 60da str r2, [r3, #12] + } + TCP_REG_ACTIVE(pcb); + 8007ec2: 4b10 ldr r3, [pc, #64] ; (8007f04 ) + 8007ec4: 681a ldr r2, [r3, #0] + 8007ec6: 68fb ldr r3, [r7, #12] + 8007ec8: 60da str r2, [r3, #12] + 8007eca: 4a0e ldr r2, [pc, #56] ; (8007f04 ) + 8007ecc: 68fb ldr r3, [r7, #12] + 8007ece: 6013 str r3, [r2, #0] + 8007ed0: f005 fb12 bl 800d4f8 + 8007ed4: 4b0c ldr r3, [pc, #48] ; (8007f08 ) + 8007ed6: 2201 movs r2, #1 + 8007ed8: 701a strb r2, [r3, #0] + MIB2_STATS_INC(mib2.tcpactiveopens); + + tcp_output(pcb); + 8007eda: 68f8 ldr r0, [r7, #12] + 8007edc: f004 fb8a bl 800c5f4 + } + return ret; + 8007ee0: f997 3013 ldrsb.w r3, [r7, #19] +} + 8007ee4: 4618 mov r0, r3 + 8007ee6: 3728 adds r7, #40 ; 0x28 + 8007ee8: 46bd mov sp, r7 + 8007eea: bd80 pop {r7, pc} + 8007eec: 08012a08 .word 0x08012a08 + 8007ef0: 08012ce4 .word 0x08012ce4 + 8007ef4: 08012a4c .word 0x08012a4c + 8007ef8: 08012d00 .word 0x08012d00 + 8007efc: 08012d1c .word 0x08012d1c + 8007f00: 24007b70 .word 0x24007b70 + 8007f04: 24007b78 .word 0x24007b78 + 8007f08: 24007b80 .word 0x24007b80 + +08007f0c : + * + * Automatically called from tcp_tmr(). + */ +void +tcp_slowtmr(void) +{ + 8007f0c: b5b0 push {r4, r5, r7, lr} + 8007f0e: b090 sub sp, #64 ; 0x40 + 8007f10: af04 add r7, sp, #16 + tcpwnd_size_t eff_wnd; + u8_t pcb_remove; /* flag if a PCB should be removed */ + u8_t pcb_reset; /* flag if a RST should be sent when removing */ + err_t err; + + err = ERR_OK; + 8007f12: 2300 movs r3, #0 + 8007f14: f887 3025 strb.w r3, [r7, #37] ; 0x25 + + ++tcp_ticks; + 8007f18: 4b94 ldr r3, [pc, #592] ; (800816c ) + 8007f1a: 681b ldr r3, [r3, #0] + 8007f1c: 3301 adds r3, #1 + 8007f1e: 4a93 ldr r2, [pc, #588] ; (800816c ) + 8007f20: 6013 str r3, [r2, #0] + ++tcp_timer_ctr; + 8007f22: 4b93 ldr r3, [pc, #588] ; (8008170 ) + 8007f24: 781b ldrb r3, [r3, #0] + 8007f26: 3301 adds r3, #1 + 8007f28: b2da uxtb r2, r3 + 8007f2a: 4b91 ldr r3, [pc, #580] ; (8008170 ) + 8007f2c: 701a strb r2, [r3, #0] + +tcp_slowtmr_start: + /* Steps through all of the active PCBs. */ + prev = NULL; + 8007f2e: 2300 movs r3, #0 + 8007f30: 62bb str r3, [r7, #40] ; 0x28 + pcb = tcp_active_pcbs; + 8007f32: 4b90 ldr r3, [pc, #576] ; (8008174 ) + 8007f34: 681b ldr r3, [r3, #0] + 8007f36: 62fb str r3, [r7, #44] ; 0x2c + if (pcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + } + while (pcb != NULL) { + 8007f38: e29d b.n 8008476 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); + 8007f3a: 6afb ldr r3, [r7, #44] ; 0x2c + 8007f3c: 7d1b ldrb r3, [r3, #20] + 8007f3e: 2b00 cmp r3, #0 + 8007f40: d106 bne.n 8007f50 + 8007f42: 4b8d ldr r3, [pc, #564] ; (8008178 ) + 8007f44: f240 42be movw r2, #1214 ; 0x4be + 8007f48: 498c ldr r1, [pc, #560] ; (800817c ) + 8007f4a: 488d ldr r0, [pc, #564] ; (8008180 ) + 8007f4c: f008 fe3c bl 8010bc8 + LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); + 8007f50: 6afb ldr r3, [r7, #44] ; 0x2c + 8007f52: 7d1b ldrb r3, [r3, #20] + 8007f54: 2b01 cmp r3, #1 + 8007f56: d106 bne.n 8007f66 + 8007f58: 4b87 ldr r3, [pc, #540] ; (8008178 ) + 8007f5a: f240 42bf movw r2, #1215 ; 0x4bf + 8007f5e: 4989 ldr r1, [pc, #548] ; (8008184 ) + 8007f60: 4887 ldr r0, [pc, #540] ; (8008180 ) + 8007f62: f008 fe31 bl 8010bc8 + LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); + 8007f66: 6afb ldr r3, [r7, #44] ; 0x2c + 8007f68: 7d1b ldrb r3, [r3, #20] + 8007f6a: 2b0a cmp r3, #10 + 8007f6c: d106 bne.n 8007f7c + 8007f6e: 4b82 ldr r3, [pc, #520] ; (8008178 ) + 8007f70: f44f 6298 mov.w r2, #1216 ; 0x4c0 + 8007f74: 4984 ldr r1, [pc, #528] ; (8008188 ) + 8007f76: 4882 ldr r0, [pc, #520] ; (8008180 ) + 8007f78: f008 fe26 bl 8010bc8 + if (pcb->last_timer == tcp_timer_ctr) { + 8007f7c: 6afb ldr r3, [r7, #44] ; 0x2c + 8007f7e: 7f9a ldrb r2, [r3, #30] + 8007f80: 4b7b ldr r3, [pc, #492] ; (8008170 ) + 8007f82: 781b ldrb r3, [r3, #0] + 8007f84: 429a cmp r2, r3 + 8007f86: d105 bne.n 8007f94 + /* skip this pcb, we have already processed it */ + prev = pcb; + 8007f88: 6afb ldr r3, [r7, #44] ; 0x2c + 8007f8a: 62bb str r3, [r7, #40] ; 0x28 + pcb = pcb->next; + 8007f8c: 6afb ldr r3, [r7, #44] ; 0x2c + 8007f8e: 68db ldr r3, [r3, #12] + 8007f90: 62fb str r3, [r7, #44] ; 0x2c + continue; + 8007f92: e270 b.n 8008476 + } + pcb->last_timer = tcp_timer_ctr; + 8007f94: 4b76 ldr r3, [pc, #472] ; (8008170 ) + 8007f96: 781a ldrb r2, [r3, #0] + 8007f98: 6afb ldr r3, [r7, #44] ; 0x2c + 8007f9a: 779a strb r2, [r3, #30] + + pcb_remove = 0; + 8007f9c: 2300 movs r3, #0 + 8007f9e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + pcb_reset = 0; + 8007fa2: 2300 movs r3, #0 + 8007fa4: f887 3026 strb.w r3, [r7, #38] ; 0x26 + + if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) { + 8007fa8: 6afb ldr r3, [r7, #44] ; 0x2c + 8007faa: 7d1b ldrb r3, [r3, #20] + 8007fac: 2b02 cmp r3, #2 + 8007fae: d10a bne.n 8007fc6 + 8007fb0: 6afb ldr r3, [r7, #44] ; 0x2c + 8007fb2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8007fb6: 2b05 cmp r3, #5 + 8007fb8: d905 bls.n 8007fc6 + ++pcb_remove; + 8007fba: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8007fbe: 3301 adds r3, #1 + 8007fc0: f887 3027 strb.w r3, [r7, #39] ; 0x27 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); + 8007fc4: e11e b.n 8008204 + } else if (pcb->nrtx >= TCP_MAXRTX) { + 8007fc6: 6afb ldr r3, [r7, #44] ; 0x2c + 8007fc8: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8007fcc: 2b0b cmp r3, #11 + 8007fce: d905 bls.n 8007fdc + ++pcb_remove; + 8007fd0: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8007fd4: 3301 adds r3, #1 + 8007fd6: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8007fda: e113 b.n 8008204 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); + } else { + if (pcb->persist_backoff > 0) { + 8007fdc: 6afb ldr r3, [r7, #44] ; 0x2c + 8007fde: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 8007fe2: 2b00 cmp r3, #0 + 8007fe4: d075 beq.n 80080d2 + LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL); + 8007fe6: 6afb ldr r3, [r7, #44] ; 0x2c + 8007fe8: 6f1b ldr r3, [r3, #112] ; 0x70 + 8007fea: 2b00 cmp r3, #0 + 8007fec: d006 beq.n 8007ffc + 8007fee: 4b62 ldr r3, [pc, #392] ; (8008178 ) + 8007ff0: f240 42d4 movw r2, #1236 ; 0x4d4 + 8007ff4: 4965 ldr r1, [pc, #404] ; (800818c ) + 8007ff6: 4862 ldr r0, [pc, #392] ; (8008180 ) + 8007ff8: f008 fde6 bl 8010bc8 + LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL); + 8007ffc: 6afb ldr r3, [r7, #44] ; 0x2c + 8007ffe: 6edb ldr r3, [r3, #108] ; 0x6c + 8008000: 2b00 cmp r3, #0 + 8008002: d106 bne.n 8008012 + 8008004: 4b5c ldr r3, [pc, #368] ; (8008178 ) + 8008006: f240 42d5 movw r2, #1237 ; 0x4d5 + 800800a: 4961 ldr r1, [pc, #388] ; (8008190 ) + 800800c: 485c ldr r0, [pc, #368] ; (8008180 ) + 800800e: f008 fddb bl 8010bc8 + if (pcb->persist_probe >= TCP_MAXRTX) { + 8008012: 6afb ldr r3, [r7, #44] ; 0x2c + 8008014: f893 309a ldrb.w r3, [r3, #154] ; 0x9a + 8008018: 2b0b cmp r3, #11 + 800801a: d905 bls.n 8008028 + ++pcb_remove; /* max probes reached */ + 800801c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008020: 3301 adds r3, #1 + 8008022: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8008026: e0ed b.n 8008204 + } else { + u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1]; + 8008028: 6afb ldr r3, [r7, #44] ; 0x2c + 800802a: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 800802e: 3b01 subs r3, #1 + 8008030: 4a58 ldr r2, [pc, #352] ; (8008194 ) + 8008032: 5cd3 ldrb r3, [r2, r3] + 8008034: 747b strb r3, [r7, #17] + if (pcb->persist_cnt < backoff_cnt) { + 8008036: 6afb ldr r3, [r7, #44] ; 0x2c + 8008038: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 + 800803c: 7c7a ldrb r2, [r7, #17] + 800803e: 429a cmp r2, r3 + 8008040: d907 bls.n 8008052 + pcb->persist_cnt++; + 8008042: 6afb ldr r3, [r7, #44] ; 0x2c + 8008044: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 + 8008048: 3301 adds r3, #1 + 800804a: b2da uxtb r2, r3 + 800804c: 6afb ldr r3, [r7, #44] ; 0x2c + 800804e: f883 2098 strb.w r2, [r3, #152] ; 0x98 + } + if (pcb->persist_cnt >= backoff_cnt) { + 8008052: 6afb ldr r3, [r7, #44] ; 0x2c + 8008054: f893 3098 ldrb.w r3, [r3, #152] ; 0x98 + 8008058: 7c7a ldrb r2, [r7, #17] + 800805a: 429a cmp r2, r3 + 800805c: f200 80d2 bhi.w 8008204 + int next_slot = 1; /* increment timer to next slot */ + 8008060: 2301 movs r3, #1 + 8008062: 623b str r3, [r7, #32] + /* If snd_wnd is zero, send 1 byte probes */ + if (pcb->snd_wnd == 0) { + 8008064: 6afb ldr r3, [r7, #44] ; 0x2c + 8008066: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800806a: 2b00 cmp r3, #0 + 800806c: d108 bne.n 8008080 + if (tcp_zero_window_probe(pcb) != ERR_OK) { + 800806e: 6af8 ldr r0, [r7, #44] ; 0x2c + 8008070: f005 f974 bl 800d35c + 8008074: 4603 mov r3, r0 + 8008076: 2b00 cmp r3, #0 + 8008078: d014 beq.n 80080a4 + next_slot = 0; /* try probe again with current slot */ + 800807a: 2300 movs r3, #0 + 800807c: 623b str r3, [r7, #32] + 800807e: e011 b.n 80080a4 + } + /* snd_wnd not fully closed, split unsent head and fill window */ + } else { + if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) { + 8008080: 6afb ldr r3, [r7, #44] ; 0x2c + 8008082: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8008086: 4619 mov r1, r3 + 8008088: 6af8 ldr r0, [r7, #44] ; 0x2c + 800808a: f004 f829 bl 800c0e0 + 800808e: 4603 mov r3, r0 + 8008090: 2b00 cmp r3, #0 + 8008092: d107 bne.n 80080a4 + if (tcp_output(pcb) == ERR_OK) { + 8008094: 6af8 ldr r0, [r7, #44] ; 0x2c + 8008096: f004 faad bl 800c5f4 + 800809a: 4603 mov r3, r0 + 800809c: 2b00 cmp r3, #0 + 800809e: d101 bne.n 80080a4 + /* sending will cancel persist timer, else retry with current slot */ + next_slot = 0; + 80080a0: 2300 movs r3, #0 + 80080a2: 623b str r3, [r7, #32] + } + } + } + if (next_slot) { + 80080a4: 6a3b ldr r3, [r7, #32] + 80080a6: 2b00 cmp r3, #0 + 80080a8: f000 80ac beq.w 8008204 + pcb->persist_cnt = 0; + 80080ac: 6afb ldr r3, [r7, #44] ; 0x2c + 80080ae: 2200 movs r2, #0 + 80080b0: f883 2098 strb.w r2, [r3, #152] ; 0x98 + if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { + 80080b4: 6afb ldr r3, [r7, #44] ; 0x2c + 80080b6: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 80080ba: 2b06 cmp r3, #6 + 80080bc: f200 80a2 bhi.w 8008204 + pcb->persist_backoff++; + 80080c0: 6afb ldr r3, [r7, #44] ; 0x2c + 80080c2: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 80080c6: 3301 adds r3, #1 + 80080c8: b2da uxtb r2, r3 + 80080ca: 6afb ldr r3, [r7, #44] ; 0x2c + 80080cc: f883 2099 strb.w r2, [r3, #153] ; 0x99 + 80080d0: e098 b.n 8008204 + } + } + } + } else { + /* Increase the retransmission timer if it is running */ + if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) { + 80080d2: 6afb ldr r3, [r7, #44] ; 0x2c + 80080d4: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 80080d8: 2b00 cmp r3, #0 + 80080da: db0f blt.n 80080fc + 80080dc: 6afb ldr r3, [r7, #44] ; 0x2c + 80080de: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 80080e2: f647 72ff movw r2, #32767 ; 0x7fff + 80080e6: 4293 cmp r3, r2 + 80080e8: d008 beq.n 80080fc + ++pcb->rtime; + 80080ea: 6afb ldr r3, [r7, #44] ; 0x2c + 80080ec: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 80080f0: b29b uxth r3, r3 + 80080f2: 3301 adds r3, #1 + 80080f4: b29b uxth r3, r3 + 80080f6: b21a sxth r2, r3 + 80080f8: 6afb ldr r3, [r7, #44] ; 0x2c + 80080fa: 861a strh r2, [r3, #48] ; 0x30 + } + + if (pcb->rtime >= pcb->rto) { + 80080fc: 6afb ldr r3, [r7, #44] ; 0x2c + 80080fe: f9b3 2030 ldrsh.w r2, [r3, #48] ; 0x30 + 8008102: 6afb ldr r3, [r7, #44] ; 0x2c + 8008104: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40 + 8008108: 429a cmp r2, r3 + 800810a: db7b blt.n 8008204 + " pcb->rto %"S16_F"\n", + pcb->rtime, pcb->rto)); + /* If prepare phase fails but we have unsent data but no unacked data, + still execute the backoff calculations below, as this means we somehow + failed to send segment. */ + if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) { + 800810c: 6af8 ldr r0, [r7, #44] ; 0x2c + 800810e: f004 fd67 bl 800cbe0 + 8008112: 4603 mov r3, r0 + 8008114: 2b00 cmp r3, #0 + 8008116: d007 beq.n 8008128 + 8008118: 6afb ldr r3, [r7, #44] ; 0x2c + 800811a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800811c: 2b00 cmp r3, #0 + 800811e: d171 bne.n 8008204 + 8008120: 6afb ldr r3, [r7, #44] ; 0x2c + 8008122: 6edb ldr r3, [r3, #108] ; 0x6c + 8008124: 2b00 cmp r3, #0 + 8008126: d06d beq.n 8008204 + /* Double retransmission time-out unless we are trying to + * connect to somebody (i.e., we are in SYN_SENT). */ + if (pcb->state != SYN_SENT) { + 8008128: 6afb ldr r3, [r7, #44] ; 0x2c + 800812a: 7d1b ldrb r3, [r3, #20] + 800812c: 2b02 cmp r3, #2 + 800812e: d03a beq.n 80081a6 + u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1); + 8008130: 6afb ldr r3, [r7, #44] ; 0x2c + 8008132: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8008136: 2b0c cmp r3, #12 + 8008138: bf28 it cs + 800813a: 230c movcs r3, #12 + 800813c: 76fb strb r3, [r7, #27] + int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx]; + 800813e: 6afb ldr r3, [r7, #44] ; 0x2c + 8008140: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 8008144: 10db asrs r3, r3, #3 + 8008146: b21b sxth r3, r3 + 8008148: 461a mov r2, r3 + 800814a: 6afb ldr r3, [r7, #44] ; 0x2c + 800814c: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 8008150: 4413 add r3, r2 + 8008152: 7efa ldrb r2, [r7, #27] + 8008154: 4910 ldr r1, [pc, #64] ; (8008198 ) + 8008156: 5c8a ldrb r2, [r1, r2] + 8008158: 4093 lsls r3, r2 + 800815a: 617b str r3, [r7, #20] + pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF); + 800815c: 697b ldr r3, [r7, #20] + 800815e: f647 72fe movw r2, #32766 ; 0x7ffe + 8008162: 4293 cmp r3, r2 + 8008164: dc1a bgt.n 800819c + 8008166: 697b ldr r3, [r7, #20] + 8008168: b21a sxth r2, r3 + 800816a: e019 b.n 80081a0 + 800816c: 24007b6c .word 0x24007b6c + 8008170: 24007b82 .word 0x24007b82 + 8008174: 24007b78 .word 0x24007b78 + 8008178: 08012a08 .word 0x08012a08 + 800817c: 08012d4c .word 0x08012d4c + 8008180: 08012a4c .word 0x08012a4c + 8008184: 08012d78 .word 0x08012d78 + 8008188: 08012da4 .word 0x08012da4 + 800818c: 08012dd4 .word 0x08012dd4 + 8008190: 08012e08 .word 0x08012e08 + 8008194: 08014d64 .word 0x08014d64 + 8008198: 08014d54 .word 0x08014d54 + 800819c: f647 72ff movw r2, #32767 ; 0x7fff + 80081a0: 6afb ldr r3, [r7, #44] ; 0x2c + 80081a2: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + } + + /* Reset the retransmission timer. */ + pcb->rtime = 0; + 80081a6: 6afb ldr r3, [r7, #44] ; 0x2c + 80081a8: 2200 movs r2, #0 + 80081aa: 861a strh r2, [r3, #48] ; 0x30 + + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + 80081ac: 6afb ldr r3, [r7, #44] ; 0x2c + 80081ae: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 80081b2: 6afb ldr r3, [r7, #44] ; 0x2c + 80081b4: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 80081b8: 4293 cmp r3, r2 + 80081ba: bf28 it cs + 80081bc: 4613 movcs r3, r2 + 80081be: 827b strh r3, [r7, #18] + pcb->ssthresh = eff_wnd >> 1; + 80081c0: 8a7b ldrh r3, [r7, #18] + 80081c2: 085b lsrs r3, r3, #1 + 80081c4: b29a uxth r2, r3 + 80081c6: 6afb ldr r3, [r7, #44] ; 0x2c + 80081c8: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) { + 80081cc: 6afb ldr r3, [r7, #44] ; 0x2c + 80081ce: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a + 80081d2: 6afb ldr r3, [r7, #44] ; 0x2c + 80081d4: 8e5b ldrh r3, [r3, #50] ; 0x32 + 80081d6: 005b lsls r3, r3, #1 + 80081d8: b29b uxth r3, r3 + 80081da: 429a cmp r2, r3 + 80081dc: d206 bcs.n 80081ec + pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1); + 80081de: 6afb ldr r3, [r7, #44] ; 0x2c + 80081e0: 8e5b ldrh r3, [r3, #50] ; 0x32 + 80081e2: 005b lsls r3, r3, #1 + 80081e4: b29a uxth r2, r3 + 80081e6: 6afb ldr r3, [r7, #44] ; 0x2c + 80081e8: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + } + pcb->cwnd = pcb->mss; + 80081ec: 6afb ldr r3, [r7, #44] ; 0x2c + 80081ee: 8e5a ldrh r2, [r3, #50] ; 0x32 + 80081f0: 6afb ldr r3, [r7, #44] ; 0x2c + 80081f2: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + pcb->bytes_acked = 0; + 80081f6: 6afb ldr r3, [r7, #44] ; 0x2c + 80081f8: 2200 movs r2, #0 + 80081fa: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + + /* The following needs to be called AFTER cwnd is set to one + mss - STJ */ + tcp_rexmit_rto_commit(pcb); + 80081fe: 6af8 ldr r0, [r7, #44] ; 0x2c + 8008200: f004 fd68 bl 800ccd4 + } + } + } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { + 8008204: 6afb ldr r3, [r7, #44] ; 0x2c + 8008206: 7d1b ldrb r3, [r3, #20] + 8008208: 2b06 cmp r3, #6 + 800820a: d111 bne.n 8008230 + /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */ + if (pcb->flags & TF_RXCLOSED) { + 800820c: 6afb ldr r3, [r7, #44] ; 0x2c + 800820e: 8b5b ldrh r3, [r3, #26] + 8008210: f003 0310 and.w r3, r3, #16 + 8008214: 2b00 cmp r3, #0 + 8008216: d00b beq.n 8008230 + /* PCB was fully closed (either through close() or SHUT_RDWR): + normal FIN-WAIT timeout handling. */ + if ((u32_t)(tcp_ticks - pcb->tmr) > + 8008218: 4b9c ldr r3, [pc, #624] ; (800848c ) + 800821a: 681a ldr r2, [r3, #0] + 800821c: 6afb ldr r3, [r7, #44] ; 0x2c + 800821e: 6a1b ldr r3, [r3, #32] + 8008220: 1ad3 subs r3, r2, r3 + 8008222: 2b28 cmp r3, #40 ; 0x28 + 8008224: d904 bls.n 8008230 + TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + 8008226: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800822a: 3301 adds r3, #1 + 800822c: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + } + } + + /* Check if KEEPALIVE should be sent */ + if (ip_get_option(pcb, SOF_KEEPALIVE) && + 8008230: 6afb ldr r3, [r7, #44] ; 0x2c + 8008232: 7a5b ldrb r3, [r3, #9] + 8008234: f003 0308 and.w r3, r3, #8 + 8008238: 2b00 cmp r3, #0 + 800823a: d04a beq.n 80082d2 + ((pcb->state == ESTABLISHED) || + 800823c: 6afb ldr r3, [r7, #44] ; 0x2c + 800823e: 7d1b ldrb r3, [r3, #20] + if (ip_get_option(pcb, SOF_KEEPALIVE) && + 8008240: 2b04 cmp r3, #4 + 8008242: d003 beq.n 800824c + (pcb->state == CLOSE_WAIT))) { + 8008244: 6afb ldr r3, [r7, #44] ; 0x2c + 8008246: 7d1b ldrb r3, [r3, #20] + ((pcb->state == ESTABLISHED) || + 8008248: 2b07 cmp r3, #7 + 800824a: d142 bne.n 80082d2 + if ((u32_t)(tcp_ticks - pcb->tmr) > + 800824c: 4b8f ldr r3, [pc, #572] ; (800848c ) + 800824e: 681a ldr r2, [r3, #0] + 8008250: 6afb ldr r3, [r7, #44] ; 0x2c + 8008252: 6a1b ldr r3, [r3, #32] + 8008254: 1ad2 subs r2, r2, r3 + (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) { + 8008256: 6afb ldr r3, [r7, #44] ; 0x2c + 8008258: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94 + 800825c: 4b8c ldr r3, [pc, #560] ; (8008490 ) + 800825e: 440b add r3, r1 + 8008260: 498c ldr r1, [pc, #560] ; (8008494 ) + 8008262: fba1 1303 umull r1, r3, r1, r3 + 8008266: 095b lsrs r3, r3, #5 + if ((u32_t)(tcp_ticks - pcb->tmr) > + 8008268: 429a cmp r2, r3 + 800826a: d90a bls.n 8008282 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to ")); + ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + + ++pcb_remove; + 800826c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008270: 3301 adds r3, #1 + 8008272: f887 3027 strb.w r3, [r7, #39] ; 0x27 + ++pcb_reset; + 8008276: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800827a: 3301 adds r3, #1 + 800827c: f887 3026 strb.w r3, [r7, #38] ; 0x26 + 8008280: e027 b.n 80082d2 + } else if ((u32_t)(tcp_ticks - pcb->tmr) > + 8008282: 4b82 ldr r3, [pc, #520] ; (800848c ) + 8008284: 681a ldr r2, [r3, #0] + 8008286: 6afb ldr r3, [r7, #44] ; 0x2c + 8008288: 6a1b ldr r3, [r3, #32] + 800828a: 1ad2 subs r2, r2, r3 + (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb)) + 800828c: 6afb ldr r3, [r7, #44] ; 0x2c + 800828e: f8d3 1094 ldr.w r1, [r3, #148] ; 0x94 + 8008292: 6afb ldr r3, [r7, #44] ; 0x2c + 8008294: f893 309b ldrb.w r3, [r3, #155] ; 0x9b + 8008298: 4618 mov r0, r3 + 800829a: 4b7f ldr r3, [pc, #508] ; (8008498 ) + 800829c: fb00 f303 mul.w r3, r0, r3 + 80082a0: 440b add r3, r1 + / TCP_SLOW_INTERVAL) { + 80082a2: 497c ldr r1, [pc, #496] ; (8008494 ) + 80082a4: fba1 1303 umull r1, r3, r1, r3 + 80082a8: 095b lsrs r3, r3, #5 + } else if ((u32_t)(tcp_ticks - pcb->tmr) > + 80082aa: 429a cmp r2, r3 + 80082ac: d911 bls.n 80082d2 + err = tcp_keepalive(pcb); + 80082ae: 6af8 ldr r0, [r7, #44] ; 0x2c + 80082b0: f005 f814 bl 800d2dc + 80082b4: 4603 mov r3, r0 + 80082b6: f887 3025 strb.w r3, [r7, #37] ; 0x25 + if (err == ERR_OK) { + 80082ba: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25 + 80082be: 2b00 cmp r3, #0 + 80082c0: d107 bne.n 80082d2 + pcb->keep_cnt_sent++; + 80082c2: 6afb ldr r3, [r7, #44] ; 0x2c + 80082c4: f893 309b ldrb.w r3, [r3, #155] ; 0x9b + 80082c8: 3301 adds r3, #1 + 80082ca: b2da uxtb r2, r3 + 80082cc: 6afb ldr r3, [r7, #44] ; 0x2c + 80082ce: f883 209b strb.w r2, [r3, #155] ; 0x9b + + /* If this PCB has queued out of sequence data, but has been + inactive for too long, will drop the data (it will eventually + be retransmitted). */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + 80082d2: 6afb ldr r3, [r7, #44] ; 0x2c + 80082d4: 6f5b ldr r3, [r3, #116] ; 0x74 + 80082d6: 2b00 cmp r3, #0 + 80082d8: d011 beq.n 80082fe + (tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) { + 80082da: 4b6c ldr r3, [pc, #432] ; (800848c ) + 80082dc: 681a ldr r2, [r3, #0] + 80082de: 6afb ldr r3, [r7, #44] ; 0x2c + 80082e0: 6a1b ldr r3, [r3, #32] + 80082e2: 1ad2 subs r2, r2, r3 + 80082e4: 6afb ldr r3, [r7, #44] ; 0x2c + 80082e6: f9b3 3040 ldrsh.w r3, [r3, #64] ; 0x40 + 80082ea: 4619 mov r1, r3 + 80082ec: 460b mov r3, r1 + 80082ee: 005b lsls r3, r3, #1 + 80082f0: 440b add r3, r1 + 80082f2: 005b lsls r3, r3, #1 + if (pcb->ooseq != NULL && + 80082f4: 429a cmp r2, r3 + 80082f6: d302 bcc.n 80082fe + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); + tcp_free_ooseq(pcb); + 80082f8: 6af8 ldr r0, [r7, #44] ; 0x2c + 80082fa: f000 fe63 bl 8008fc4 + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + 80082fe: 6afb ldr r3, [r7, #44] ; 0x2c + 8008300: 7d1b ldrb r3, [r3, #20] + 8008302: 2b03 cmp r3, #3 + 8008304: d10b bne.n 800831e + if ((u32_t)(tcp_ticks - pcb->tmr) > + 8008306: 4b61 ldr r3, [pc, #388] ; (800848c ) + 8008308: 681a ldr r2, [r3, #0] + 800830a: 6afb ldr r3, [r7, #44] ; 0x2c + 800830c: 6a1b ldr r3, [r3, #32] + 800830e: 1ad3 subs r3, r2, r3 + 8008310: 2b28 cmp r3, #40 ; 0x28 + 8008312: d904 bls.n 800831e + TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + 8008314: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008318: 3301 adds r3, #1 + 800831a: f887 3027 strb.w r3, [r7, #39] ; 0x27 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + + /* Check if this PCB has stayed too long in LAST-ACK */ + if (pcb->state == LAST_ACK) { + 800831e: 6afb ldr r3, [r7, #44] ; 0x2c + 8008320: 7d1b ldrb r3, [r3, #20] + 8008322: 2b09 cmp r3, #9 + 8008324: d10b bne.n 800833e + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + 8008326: 4b59 ldr r3, [pc, #356] ; (800848c ) + 8008328: 681a ldr r2, [r3, #0] + 800832a: 6afb ldr r3, [r7, #44] ; 0x2c + 800832c: 6a1b ldr r3, [r3, #32] + 800832e: 1ad3 subs r3, r2, r3 + 8008330: 2bf0 cmp r3, #240 ; 0xf0 + 8008332: d904 bls.n 800833e + ++pcb_remove; + 8008334: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008338: 3301 adds r3, #1 + 800833a: f887 3027 strb.w r3, [r7, #39] ; 0x27 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); + } + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + 800833e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008342: 2b00 cmp r3, #0 + 8008344: d060 beq.n 8008408 + struct tcp_pcb *pcb2; +#if LWIP_CALLBACK_API + tcp_err_fn err_fn = pcb->errf; + 8008346: 6afb ldr r3, [r7, #44] ; 0x2c + 8008348: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800834c: 60fb str r3, [r7, #12] +#endif /* LWIP_CALLBACK_API */ + void *err_arg; + enum tcp_state last_state; + tcp_pcb_purge(pcb); + 800834e: 6af8 ldr r0, [r7, #44] ; 0x2c + 8008350: f000 fc7e bl 8008c50 + /* Remove PCB from tcp_active_pcbs list. */ + if (prev != NULL) { + 8008354: 6abb ldr r3, [r7, #40] ; 0x28 + 8008356: 2b00 cmp r3, #0 + 8008358: d010 beq.n 800837c + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); + 800835a: 4b50 ldr r3, [pc, #320] ; (800849c ) + 800835c: 681b ldr r3, [r3, #0] + 800835e: 6afa ldr r2, [r7, #44] ; 0x2c + 8008360: 429a cmp r2, r3 + 8008362: d106 bne.n 8008372 + 8008364: 4b4e ldr r3, [pc, #312] ; (80084a0 ) + 8008366: f240 526d movw r2, #1389 ; 0x56d + 800836a: 494e ldr r1, [pc, #312] ; (80084a4 ) + 800836c: 484e ldr r0, [pc, #312] ; (80084a8 ) + 800836e: f008 fc2b bl 8010bc8 + prev->next = pcb->next; + 8008372: 6afb ldr r3, [r7, #44] ; 0x2c + 8008374: 68da ldr r2, [r3, #12] + 8008376: 6abb ldr r3, [r7, #40] ; 0x28 + 8008378: 60da str r2, [r3, #12] + 800837a: e00f b.n 800839c + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); + 800837c: 4b47 ldr r3, [pc, #284] ; (800849c ) + 800837e: 681b ldr r3, [r3, #0] + 8008380: 6afa ldr r2, [r7, #44] ; 0x2c + 8008382: 429a cmp r2, r3 + 8008384: d006 beq.n 8008394 + 8008386: 4b46 ldr r3, [pc, #280] ; (80084a0 ) + 8008388: f240 5271 movw r2, #1393 ; 0x571 + 800838c: 4947 ldr r1, [pc, #284] ; (80084ac ) + 800838e: 4846 ldr r0, [pc, #280] ; (80084a8 ) + 8008390: f008 fc1a bl 8010bc8 + tcp_active_pcbs = pcb->next; + 8008394: 6afb ldr r3, [r7, #44] ; 0x2c + 8008396: 68db ldr r3, [r3, #12] + 8008398: 4a40 ldr r2, [pc, #256] ; (800849c ) + 800839a: 6013 str r3, [r2, #0] + } + + if (pcb_reset) { + 800839c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 80083a0: 2b00 cmp r3, #0 + 80083a2: d013 beq.n 80083cc + tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + 80083a4: 6afb ldr r3, [r7, #44] ; 0x2c + 80083a6: 6d18 ldr r0, [r3, #80] ; 0x50 + 80083a8: 6afb ldr r3, [r7, #44] ; 0x2c + 80083aa: 6a5c ldr r4, [r3, #36] ; 0x24 + 80083ac: 6afd ldr r5, [r7, #44] ; 0x2c + 80083ae: 6afb ldr r3, [r7, #44] ; 0x2c + 80083b0: 3304 adds r3, #4 + 80083b2: 6afa ldr r2, [r7, #44] ; 0x2c + 80083b4: 8ad2 ldrh r2, [r2, #22] + 80083b6: 6af9 ldr r1, [r7, #44] ; 0x2c + 80083b8: 8b09 ldrh r1, [r1, #24] + 80083ba: 9102 str r1, [sp, #8] + 80083bc: 9201 str r2, [sp, #4] + 80083be: 9300 str r3, [sp, #0] + 80083c0: 462b mov r3, r5 + 80083c2: 4622 mov r2, r4 + 80083c4: 4601 mov r1, r0 + 80083c6: 6af8 ldr r0, [r7, #44] ; 0x2c + 80083c8: f004 fed4 bl 800d174 + pcb->local_port, pcb->remote_port); + } + + err_arg = pcb->callback_arg; + 80083cc: 6afb ldr r3, [r7, #44] ; 0x2c + 80083ce: 691b ldr r3, [r3, #16] + 80083d0: 60bb str r3, [r7, #8] + last_state = pcb->state; + 80083d2: 6afb ldr r3, [r7, #44] ; 0x2c + 80083d4: 7d1b ldrb r3, [r3, #20] + 80083d6: 71fb strb r3, [r7, #7] + pcb2 = pcb; + 80083d8: 6afb ldr r3, [r7, #44] ; 0x2c + 80083da: 603b str r3, [r7, #0] + pcb = pcb->next; + 80083dc: 6afb ldr r3, [r7, #44] ; 0x2c + 80083de: 68db ldr r3, [r3, #12] + 80083e0: 62fb str r3, [r7, #44] ; 0x2c + tcp_free(pcb2); + 80083e2: 6838 ldr r0, [r7, #0] + 80083e4: f7ff f896 bl 8007514 + + tcp_active_pcbs_changed = 0; + 80083e8: 4b31 ldr r3, [pc, #196] ; (80084b0 ) + 80083ea: 2200 movs r2, #0 + 80083ec: 701a strb r2, [r3, #0] + TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT); + 80083ee: 68fb ldr r3, [r7, #12] + 80083f0: 2b00 cmp r3, #0 + 80083f2: d004 beq.n 80083fe + 80083f4: 68fb ldr r3, [r7, #12] + 80083f6: f06f 010c mvn.w r1, #12 + 80083fa: 68b8 ldr r0, [r7, #8] + 80083fc: 4798 blx r3 + if (tcp_active_pcbs_changed) { + 80083fe: 4b2c ldr r3, [pc, #176] ; (80084b0 ) + 8008400: 781b ldrb r3, [r3, #0] + 8008402: 2b00 cmp r3, #0 + 8008404: d037 beq.n 8008476 + goto tcp_slowtmr_start; + 8008406: e592 b.n 8007f2e + } + } else { + /* get the 'next' element now and work with 'prev' below (in case of abort) */ + prev = pcb; + 8008408: 6afb ldr r3, [r7, #44] ; 0x2c + 800840a: 62bb str r3, [r7, #40] ; 0x28 + pcb = pcb->next; + 800840c: 6afb ldr r3, [r7, #44] ; 0x2c + 800840e: 68db ldr r3, [r3, #12] + 8008410: 62fb str r3, [r7, #44] ; 0x2c + + /* We check if we should poll the connection. */ + ++prev->polltmr; + 8008412: 6abb ldr r3, [r7, #40] ; 0x28 + 8008414: 7f1b ldrb r3, [r3, #28] + 8008416: 3301 adds r3, #1 + 8008418: b2da uxtb r2, r3 + 800841a: 6abb ldr r3, [r7, #40] ; 0x28 + 800841c: 771a strb r2, [r3, #28] + if (prev->polltmr >= prev->pollinterval) { + 800841e: 6abb ldr r3, [r7, #40] ; 0x28 + 8008420: 7f1a ldrb r2, [r3, #28] + 8008422: 6abb ldr r3, [r7, #40] ; 0x28 + 8008424: 7f5b ldrb r3, [r3, #29] + 8008426: 429a cmp r2, r3 + 8008428: d325 bcc.n 8008476 + prev->polltmr = 0; + 800842a: 6abb ldr r3, [r7, #40] ; 0x28 + 800842c: 2200 movs r2, #0 + 800842e: 771a strb r2, [r3, #28] + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); + tcp_active_pcbs_changed = 0; + 8008430: 4b1f ldr r3, [pc, #124] ; (80084b0 ) + 8008432: 2200 movs r2, #0 + 8008434: 701a strb r2, [r3, #0] + TCP_EVENT_POLL(prev, err); + 8008436: 6abb ldr r3, [r7, #40] ; 0x28 + 8008438: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800843c: 2b00 cmp r3, #0 + 800843e: d00b beq.n 8008458 + 8008440: 6abb ldr r3, [r7, #40] ; 0x28 + 8008442: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8008446: 6aba ldr r2, [r7, #40] ; 0x28 + 8008448: 6912 ldr r2, [r2, #16] + 800844a: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800844c: 4610 mov r0, r2 + 800844e: 4798 blx r3 + 8008450: 4603 mov r3, r0 + 8008452: f887 3025 strb.w r3, [r7, #37] ; 0x25 + 8008456: e002 b.n 800845e + 8008458: 2300 movs r3, #0 + 800845a: f887 3025 strb.w r3, [r7, #37] ; 0x25 + if (tcp_active_pcbs_changed) { + 800845e: 4b14 ldr r3, [pc, #80] ; (80084b0 ) + 8008460: 781b ldrb r3, [r3, #0] + 8008462: 2b00 cmp r3, #0 + 8008464: d000 beq.n 8008468 + goto tcp_slowtmr_start; + 8008466: e562 b.n 8007f2e + } + /* if err == ERR_ABRT, 'prev' is already deallocated */ + if (err == ERR_OK) { + 8008468: f997 3025 ldrsb.w r3, [r7, #37] ; 0x25 + 800846c: 2b00 cmp r3, #0 + 800846e: d102 bne.n 8008476 + tcp_output(prev); + 8008470: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8008472: f004 f8bf bl 800c5f4 + while (pcb != NULL) { + 8008476: 6afb ldr r3, [r7, #44] ; 0x2c + 8008478: 2b00 cmp r3, #0 + 800847a: f47f ad5e bne.w 8007f3a + } + } + + + /* Steps through all of the TIME-WAIT PCBs. */ + prev = NULL; + 800847e: 2300 movs r3, #0 + 8008480: 62bb str r3, [r7, #40] ; 0x28 + pcb = tcp_tw_pcbs; + 8008482: 4b0c ldr r3, [pc, #48] ; (80084b4 ) + 8008484: 681b ldr r3, [r3, #0] + 8008486: 62fb str r3, [r7, #44] ; 0x2c + while (pcb != NULL) { + 8008488: e069 b.n 800855e + 800848a: bf00 nop + 800848c: 24007b6c .word 0x24007b6c + 8008490: 000a4cb8 .word 0x000a4cb8 + 8008494: 10624dd3 .word 0x10624dd3 + 8008498: 000124f8 .word 0x000124f8 + 800849c: 24007b78 .word 0x24007b78 + 80084a0: 08012a08 .word 0x08012a08 + 80084a4: 08012e40 .word 0x08012e40 + 80084a8: 08012a4c .word 0x08012a4c + 80084ac: 08012e6c .word 0x08012e6c + 80084b0: 24007b80 .word 0x24007b80 + 80084b4: 24007b7c .word 0x24007b7c + LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + 80084b8: 6afb ldr r3, [r7, #44] ; 0x2c + 80084ba: 7d1b ldrb r3, [r3, #20] + 80084bc: 2b0a cmp r3, #10 + 80084be: d006 beq.n 80084ce + 80084c0: 4b2b ldr r3, [pc, #172] ; (8008570 ) + 80084c2: f240 52a1 movw r2, #1441 ; 0x5a1 + 80084c6: 492b ldr r1, [pc, #172] ; (8008574 ) + 80084c8: 482b ldr r0, [pc, #172] ; (8008578 ) + 80084ca: f008 fb7d bl 8010bc8 + pcb_remove = 0; + 80084ce: 2300 movs r3, #0 + 80084d0: f887 3027 strb.w r3, [r7, #39] ; 0x27 + + /* Check if this PCB has stayed long enough in TIME-WAIT */ + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + 80084d4: 4b29 ldr r3, [pc, #164] ; (800857c ) + 80084d6: 681a ldr r2, [r3, #0] + 80084d8: 6afb ldr r3, [r7, #44] ; 0x2c + 80084da: 6a1b ldr r3, [r3, #32] + 80084dc: 1ad3 subs r3, r2, r3 + 80084de: 2bf0 cmp r3, #240 ; 0xf0 + 80084e0: d904 bls.n 80084ec + ++pcb_remove; + 80084e2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80084e6: 3301 adds r3, #1 + 80084e8: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + 80084ec: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80084f0: 2b00 cmp r3, #0 + 80084f2: d02f beq.n 8008554 + struct tcp_pcb *pcb2; + tcp_pcb_purge(pcb); + 80084f4: 6af8 ldr r0, [r7, #44] ; 0x2c + 80084f6: f000 fbab bl 8008c50 + /* Remove PCB from tcp_tw_pcbs list. */ + if (prev != NULL) { + 80084fa: 6abb ldr r3, [r7, #40] ; 0x28 + 80084fc: 2b00 cmp r3, #0 + 80084fe: d010 beq.n 8008522 + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); + 8008500: 4b1f ldr r3, [pc, #124] ; (8008580 ) + 8008502: 681b ldr r3, [r3, #0] + 8008504: 6afa ldr r2, [r7, #44] ; 0x2c + 8008506: 429a cmp r2, r3 + 8008508: d106 bne.n 8008518 + 800850a: 4b19 ldr r3, [pc, #100] ; (8008570 ) + 800850c: f240 52af movw r2, #1455 ; 0x5af + 8008510: 491c ldr r1, [pc, #112] ; (8008584 ) + 8008512: 4819 ldr r0, [pc, #100] ; (8008578 ) + 8008514: f008 fb58 bl 8010bc8 + prev->next = pcb->next; + 8008518: 6afb ldr r3, [r7, #44] ; 0x2c + 800851a: 68da ldr r2, [r3, #12] + 800851c: 6abb ldr r3, [r7, #40] ; 0x28 + 800851e: 60da str r2, [r3, #12] + 8008520: e00f b.n 8008542 + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); + 8008522: 4b17 ldr r3, [pc, #92] ; (8008580 ) + 8008524: 681b ldr r3, [r3, #0] + 8008526: 6afa ldr r2, [r7, #44] ; 0x2c + 8008528: 429a cmp r2, r3 + 800852a: d006 beq.n 800853a + 800852c: 4b10 ldr r3, [pc, #64] ; (8008570 ) + 800852e: f240 52b3 movw r2, #1459 ; 0x5b3 + 8008532: 4915 ldr r1, [pc, #84] ; (8008588 ) + 8008534: 4810 ldr r0, [pc, #64] ; (8008578 ) + 8008536: f008 fb47 bl 8010bc8 + tcp_tw_pcbs = pcb->next; + 800853a: 6afb ldr r3, [r7, #44] ; 0x2c + 800853c: 68db ldr r3, [r3, #12] + 800853e: 4a10 ldr r2, [pc, #64] ; (8008580 ) + 8008540: 6013 str r3, [r2, #0] + } + pcb2 = pcb; + 8008542: 6afb ldr r3, [r7, #44] ; 0x2c + 8008544: 61fb str r3, [r7, #28] + pcb = pcb->next; + 8008546: 6afb ldr r3, [r7, #44] ; 0x2c + 8008548: 68db ldr r3, [r3, #12] + 800854a: 62fb str r3, [r7, #44] ; 0x2c + tcp_free(pcb2); + 800854c: 69f8 ldr r0, [r7, #28] + 800854e: f7fe ffe1 bl 8007514 + 8008552: e004 b.n 800855e + } else { + prev = pcb; + 8008554: 6afb ldr r3, [r7, #44] ; 0x2c + 8008556: 62bb str r3, [r7, #40] ; 0x28 + pcb = pcb->next; + 8008558: 6afb ldr r3, [r7, #44] ; 0x2c + 800855a: 68db ldr r3, [r3, #12] + 800855c: 62fb str r3, [r7, #44] ; 0x2c + while (pcb != NULL) { + 800855e: 6afb ldr r3, [r7, #44] ; 0x2c + 8008560: 2b00 cmp r3, #0 + 8008562: d1a9 bne.n 80084b8 + } + } +} + 8008564: bf00 nop + 8008566: bf00 nop + 8008568: 3730 adds r7, #48 ; 0x30 + 800856a: 46bd mov sp, r7 + 800856c: bdb0 pop {r4, r5, r7, pc} + 800856e: bf00 nop + 8008570: 08012a08 .word 0x08012a08 + 8008574: 08012e98 .word 0x08012e98 + 8008578: 08012a4c .word 0x08012a4c + 800857c: 24007b6c .word 0x24007b6c + 8008580: 24007b7c .word 0x24007b7c + 8008584: 08012ec8 .word 0x08012ec8 + 8008588: 08012ef0 .word 0x08012ef0 + +0800858c : + * + * Automatically called from tcp_tmr(). + */ +void +tcp_fasttmr(void) +{ + 800858c: b580 push {r7, lr} + 800858e: b082 sub sp, #8 + 8008590: af00 add r7, sp, #0 + struct tcp_pcb *pcb; + + ++tcp_timer_ctr; + 8008592: 4b2d ldr r3, [pc, #180] ; (8008648 ) + 8008594: 781b ldrb r3, [r3, #0] + 8008596: 3301 adds r3, #1 + 8008598: b2da uxtb r2, r3 + 800859a: 4b2b ldr r3, [pc, #172] ; (8008648 ) + 800859c: 701a strb r2, [r3, #0] + +tcp_fasttmr_start: + pcb = tcp_active_pcbs; + 800859e: 4b2b ldr r3, [pc, #172] ; (800864c ) + 80085a0: 681b ldr r3, [r3, #0] + 80085a2: 607b str r3, [r7, #4] + + while (pcb != NULL) { + 80085a4: e048 b.n 8008638 + if (pcb->last_timer != tcp_timer_ctr) { + 80085a6: 687b ldr r3, [r7, #4] + 80085a8: 7f9a ldrb r2, [r3, #30] + 80085aa: 4b27 ldr r3, [pc, #156] ; (8008648 ) + 80085ac: 781b ldrb r3, [r3, #0] + 80085ae: 429a cmp r2, r3 + 80085b0: d03f beq.n 8008632 + struct tcp_pcb *next; + pcb->last_timer = tcp_timer_ctr; + 80085b2: 4b25 ldr r3, [pc, #148] ; (8008648 ) + 80085b4: 781a ldrb r2, [r3, #0] + 80085b6: 687b ldr r3, [r7, #4] + 80085b8: 779a strb r2, [r3, #30] + /* send delayed ACKs */ + if (pcb->flags & TF_ACK_DELAY) { + 80085ba: 687b ldr r3, [r7, #4] + 80085bc: 8b5b ldrh r3, [r3, #26] + 80085be: f003 0301 and.w r3, r3, #1 + 80085c2: 2b00 cmp r3, #0 + 80085c4: d010 beq.n 80085e8 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); + tcp_ack_now(pcb); + 80085c6: 687b ldr r3, [r7, #4] + 80085c8: 8b5b ldrh r3, [r3, #26] + 80085ca: f043 0302 orr.w r3, r3, #2 + 80085ce: b29a uxth r2, r3 + 80085d0: 687b ldr r3, [r7, #4] + 80085d2: 835a strh r2, [r3, #26] + tcp_output(pcb); + 80085d4: 6878 ldr r0, [r7, #4] + 80085d6: f004 f80d bl 800c5f4 + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 80085da: 687b ldr r3, [r7, #4] + 80085dc: 8b5b ldrh r3, [r3, #26] + 80085de: f023 0303 bic.w r3, r3, #3 + 80085e2: b29a uxth r2, r3 + 80085e4: 687b ldr r3, [r7, #4] + 80085e6: 835a strh r2, [r3, #26] + } + /* send pending FIN */ + if (pcb->flags & TF_CLOSEPEND) { + 80085e8: 687b ldr r3, [r7, #4] + 80085ea: 8b5b ldrh r3, [r3, #26] + 80085ec: f003 0308 and.w r3, r3, #8 + 80085f0: 2b00 cmp r3, #0 + 80085f2: d009 beq.n 8008608 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n")); + tcp_clear_flags(pcb, TF_CLOSEPEND); + 80085f4: 687b ldr r3, [r7, #4] + 80085f6: 8b5b ldrh r3, [r3, #26] + 80085f8: f023 0308 bic.w r3, r3, #8 + 80085fc: b29a uxth r2, r3 + 80085fe: 687b ldr r3, [r7, #4] + 8008600: 835a strh r2, [r3, #26] + tcp_close_shutdown_fin(pcb); + 8008602: 6878 ldr r0, [r7, #4] + 8008604: f7ff f91a bl 800783c + } + + next = pcb->next; + 8008608: 687b ldr r3, [r7, #4] + 800860a: 68db ldr r3, [r3, #12] + 800860c: 603b str r3, [r7, #0] + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + 800860e: 687b ldr r3, [r7, #4] + 8008610: 6f9b ldr r3, [r3, #120] ; 0x78 + 8008612: 2b00 cmp r3, #0 + 8008614: d00a beq.n 800862c + tcp_active_pcbs_changed = 0; + 8008616: 4b0e ldr r3, [pc, #56] ; (8008650 ) + 8008618: 2200 movs r2, #0 + 800861a: 701a strb r2, [r3, #0] + tcp_process_refused_data(pcb); + 800861c: 6878 ldr r0, [r7, #4] + 800861e: f000 f819 bl 8008654 + if (tcp_active_pcbs_changed) { + 8008622: 4b0b ldr r3, [pc, #44] ; (8008650 ) + 8008624: 781b ldrb r3, [r3, #0] + 8008626: 2b00 cmp r3, #0 + 8008628: d000 beq.n 800862c + /* application callback has changed the pcb list: restart the loop */ + goto tcp_fasttmr_start; + 800862a: e7b8 b.n 800859e + } + } + pcb = next; + 800862c: 683b ldr r3, [r7, #0] + 800862e: 607b str r3, [r7, #4] + 8008630: e002 b.n 8008638 + } else { + pcb = pcb->next; + 8008632: 687b ldr r3, [r7, #4] + 8008634: 68db ldr r3, [r3, #12] + 8008636: 607b str r3, [r7, #4] + while (pcb != NULL) { + 8008638: 687b ldr r3, [r7, #4] + 800863a: 2b00 cmp r3, #0 + 800863c: d1b3 bne.n 80085a6 + } + } +} + 800863e: bf00 nop + 8008640: bf00 nop + 8008642: 3708 adds r7, #8 + 8008644: 46bd mov sp, r7 + 8008646: bd80 pop {r7, pc} + 8008648: 24007b82 .word 0x24007b82 + 800864c: 24007b78 .word 0x24007b78 + 8008650: 24007b80 .word 0x24007b80 + +08008654 : +} + +/** Pass pcb->refused_data to the recv callback */ +err_t +tcp_process_refused_data(struct tcp_pcb *pcb) +{ + 8008654: b590 push {r4, r7, lr} + 8008656: b085 sub sp, #20 + 8008658: af00 add r7, sp, #0 + 800865a: 6078 str r0, [r7, #4] +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + struct pbuf *rest; +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + + LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG); + 800865c: 687b ldr r3, [r7, #4] + 800865e: 2b00 cmp r3, #0 + 8008660: d109 bne.n 8008676 + 8008662: 4b37 ldr r3, [pc, #220] ; (8008740 ) + 8008664: f240 6209 movw r2, #1545 ; 0x609 + 8008668: 4936 ldr r1, [pc, #216] ; (8008744 ) + 800866a: 4837 ldr r0, [pc, #220] ; (8008748 ) + 800866c: f008 faac bl 8010bc8 + 8008670: f06f 030f mvn.w r3, #15 + 8008674: e060 b.n 8008738 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + while (pcb->refused_data != NULL) +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + { + err_t err; + u8_t refused_flags = pcb->refused_data->flags; + 8008676: 687b ldr r3, [r7, #4] + 8008678: 6f9b ldr r3, [r3, #120] ; 0x78 + 800867a: 7b5b ldrb r3, [r3, #13] + 800867c: 73bb strb r3, [r7, #14] + /* set pcb->refused_data to NULL in case the callback frees it and then + closes the pcb */ + struct pbuf *refused_data = pcb->refused_data; + 800867e: 687b ldr r3, [r7, #4] + 8008680: 6f9b ldr r3, [r3, #120] ; 0x78 + 8008682: 60bb str r3, [r7, #8] +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + pbuf_split_64k(refused_data, &rest); + pcb->refused_data = rest; +#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = NULL; + 8008684: 687b ldr r3, [r7, #4] + 8008686: 2200 movs r2, #0 + 8008688: 679a str r2, [r3, #120] ; 0x78 +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + /* Notify again application with data previously received. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); + TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err); + 800868a: 687b ldr r3, [r7, #4] + 800868c: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8008690: 2b00 cmp r3, #0 + 8008692: d00b beq.n 80086ac + 8008694: 687b ldr r3, [r7, #4] + 8008696: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 800869a: 687b ldr r3, [r7, #4] + 800869c: 6918 ldr r0, [r3, #16] + 800869e: 2300 movs r3, #0 + 80086a0: 68ba ldr r2, [r7, #8] + 80086a2: 6879 ldr r1, [r7, #4] + 80086a4: 47a0 blx r4 + 80086a6: 4603 mov r3, r0 + 80086a8: 73fb strb r3, [r7, #15] + 80086aa: e007 b.n 80086bc + 80086ac: 2300 movs r3, #0 + 80086ae: 68ba ldr r2, [r7, #8] + 80086b0: 6879 ldr r1, [r7, #4] + 80086b2: 2000 movs r0, #0 + 80086b4: f000 f8a4 bl 8008800 + 80086b8: 4603 mov r3, r0 + 80086ba: 73fb strb r3, [r7, #15] + if (err == ERR_OK) { + 80086bc: f997 300f ldrsb.w r3, [r7, #15] + 80086c0: 2b00 cmp r3, #0 + 80086c2: d12a bne.n 800871a + /* did refused_data include a FIN? */ + if ((refused_flags & PBUF_FLAG_TCP_FIN) + 80086c4: 7bbb ldrb r3, [r7, #14] + 80086c6: f003 0320 and.w r3, r3, #32 + 80086ca: 2b00 cmp r3, #0 + 80086cc: d033 beq.n 8008736 + && (rest == NULL) +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + ) { + /* correct rcv_wnd as the application won't call tcp_recved() + for the FIN's seqno */ + if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { + 80086ce: 687b ldr r3, [r7, #4] + 80086d0: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80086d2: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 80086d6: d005 beq.n 80086e4 + pcb->rcv_wnd++; + 80086d8: 687b ldr r3, [r7, #4] + 80086da: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80086dc: 3301 adds r3, #1 + 80086de: b29a uxth r2, r3 + 80086e0: 687b ldr r3, [r7, #4] + 80086e2: 851a strh r2, [r3, #40] ; 0x28 + } + TCP_EVENT_CLOSED(pcb, err); + 80086e4: 687b ldr r3, [r7, #4] + 80086e6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80086ea: 2b00 cmp r3, #0 + 80086ec: d00b beq.n 8008706 + 80086ee: 687b ldr r3, [r7, #4] + 80086f0: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 80086f4: 687b ldr r3, [r7, #4] + 80086f6: 6918 ldr r0, [r3, #16] + 80086f8: 2300 movs r3, #0 + 80086fa: 2200 movs r2, #0 + 80086fc: 6879 ldr r1, [r7, #4] + 80086fe: 47a0 blx r4 + 8008700: 4603 mov r3, r0 + 8008702: 73fb strb r3, [r7, #15] + 8008704: e001 b.n 800870a + 8008706: 2300 movs r3, #0 + 8008708: 73fb strb r3, [r7, #15] + if (err == ERR_ABRT) { + 800870a: f997 300f ldrsb.w r3, [r7, #15] + 800870e: f113 0f0d cmn.w r3, #13 + 8008712: d110 bne.n 8008736 + return ERR_ABRT; + 8008714: f06f 030c mvn.w r3, #12 + 8008718: e00e b.n 8008738 + } + } + } else if (err == ERR_ABRT) { + 800871a: f997 300f ldrsb.w r3, [r7, #15] + 800871e: f113 0f0d cmn.w r3, #13 + 8008722: d102 bne.n 800872a + /* if err == ERR_ABRT, 'pcb' is already deallocated */ + /* Drop incoming packets because pcb is "full" (only if the incoming + segment contains data). */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); + return ERR_ABRT; + 8008724: f06f 030c mvn.w r3, #12 + 8008728: e006 b.n 8008738 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_cat(refused_data, rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = refused_data; + 800872a: 687b ldr r3, [r7, #4] + 800872c: 68ba ldr r2, [r7, #8] + 800872e: 679a str r2, [r3, #120] ; 0x78 + return ERR_INPROGRESS; + 8008730: f06f 0304 mvn.w r3, #4 + 8008734: e000 b.n 8008738 + } + } + return ERR_OK; + 8008736: 2300 movs r3, #0 +} + 8008738: 4618 mov r0, r3 + 800873a: 3714 adds r7, #20 + 800873c: 46bd mov sp, r7 + 800873e: bd90 pop {r4, r7, pc} + 8008740: 08012a08 .word 0x08012a08 + 8008744: 08012f18 .word 0x08012f18 + 8008748: 08012a4c .word 0x08012a4c + +0800874c : + * + * @param seg tcp_seg list of TCP segments to free + */ +void +tcp_segs_free(struct tcp_seg *seg) +{ + 800874c: b580 push {r7, lr} + 800874e: b084 sub sp, #16 + 8008750: af00 add r7, sp, #0 + 8008752: 6078 str r0, [r7, #4] + while (seg != NULL) { + 8008754: e007 b.n 8008766 + struct tcp_seg *next = seg->next; + 8008756: 687b ldr r3, [r7, #4] + 8008758: 681b ldr r3, [r3, #0] + 800875a: 60fb str r3, [r7, #12] + tcp_seg_free(seg); + 800875c: 6878 ldr r0, [r7, #4] + 800875e: f000 f80a bl 8008776 + seg = next; + 8008762: 68fb ldr r3, [r7, #12] + 8008764: 607b str r3, [r7, #4] + while (seg != NULL) { + 8008766: 687b ldr r3, [r7, #4] + 8008768: 2b00 cmp r3, #0 + 800876a: d1f4 bne.n 8008756 + } +} + 800876c: bf00 nop + 800876e: bf00 nop + 8008770: 3710 adds r7, #16 + 8008772: 46bd mov sp, r7 + 8008774: bd80 pop {r7, pc} + +08008776 : + * + * @param seg single tcp_seg to free + */ +void +tcp_seg_free(struct tcp_seg *seg) +{ + 8008776: b580 push {r7, lr} + 8008778: b082 sub sp, #8 + 800877a: af00 add r7, sp, #0 + 800877c: 6078 str r0, [r7, #4] + if (seg != NULL) { + 800877e: 687b ldr r3, [r7, #4] + 8008780: 2b00 cmp r3, #0 + 8008782: d00c beq.n 800879e + if (seg->p != NULL) { + 8008784: 687b ldr r3, [r7, #4] + 8008786: 685b ldr r3, [r3, #4] + 8008788: 2b00 cmp r3, #0 + 800878a: d004 beq.n 8008796 + pbuf_free(seg->p); + 800878c: 687b ldr r3, [r7, #4] + 800878e: 685b ldr r3, [r3, #4] + 8008790: 4618 mov r0, r3 + 8008792: f7fe fc1f bl 8006fd4 +#if TCP_DEBUG + seg->p = NULL; +#endif /* TCP_DEBUG */ + } + memp_free(MEMP_TCP_SEG, seg); + 8008796: 6879 ldr r1, [r7, #4] + 8008798: 2003 movs r0, #3 + 800879a: f7fd fcaf bl 80060fc + } +} + 800879e: bf00 nop + 80087a0: 3708 adds r7, #8 + 80087a2: 46bd mov sp, r7 + 80087a4: bd80 pop {r7, pc} + ... + +080087a8 : + * @param seg the old tcp_seg + * @return a copy of seg + */ +struct tcp_seg * +tcp_seg_copy(struct tcp_seg *seg) +{ + 80087a8: b580 push {r7, lr} + 80087aa: b084 sub sp, #16 + 80087ac: af00 add r7, sp, #0 + 80087ae: 6078 str r0, [r7, #4] + struct tcp_seg *cseg; + + LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL); + 80087b0: 687b ldr r3, [r7, #4] + 80087b2: 2b00 cmp r3, #0 + 80087b4: d106 bne.n 80087c4 + 80087b6: 4b0f ldr r3, [pc, #60] ; (80087f4 ) + 80087b8: f240 6282 movw r2, #1666 ; 0x682 + 80087bc: 490e ldr r1, [pc, #56] ; (80087f8 ) + 80087be: 480f ldr r0, [pc, #60] ; (80087fc ) + 80087c0: f008 fa02 bl 8010bc8 + + cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG); + 80087c4: 2003 movs r0, #3 + 80087c6: f7fd fc29 bl 800601c + 80087ca: 60f8 str r0, [r7, #12] + if (cseg == NULL) { + 80087cc: 68fb ldr r3, [r7, #12] + 80087ce: 2b00 cmp r3, #0 + 80087d0: d101 bne.n 80087d6 + return NULL; + 80087d2: 2300 movs r3, #0 + 80087d4: e00a b.n 80087ec + } + SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); + 80087d6: 2214 movs r2, #20 + 80087d8: 6879 ldr r1, [r7, #4] + 80087da: 68f8 ldr r0, [r7, #12] + 80087dc: f008 fbd5 bl 8010f8a + pbuf_ref(cseg->p); + 80087e0: 68fb ldr r3, [r7, #12] + 80087e2: 685b ldr r3, [r3, #4] + 80087e4: 4618 mov r0, r3 + 80087e6: f7fe fc95 bl 8007114 + return cseg; + 80087ea: 68fb ldr r3, [r7, #12] +} + 80087ec: 4618 mov r0, r3 + 80087ee: 3710 adds r7, #16 + 80087f0: 46bd mov sp, r7 + 80087f2: bd80 pop {r7, pc} + 80087f4: 08012a08 .word 0x08012a08 + 80087f8: 08012f5c .word 0x08012f5c + 80087fc: 08012a4c .word 0x08012a4c + +08008800 : + * Default receive callback that is called if the user didn't register + * a recv callback for the pcb. + */ +err_t +tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + 8008800: b580 push {r7, lr} + 8008802: b084 sub sp, #16 + 8008804: af00 add r7, sp, #0 + 8008806: 60f8 str r0, [r7, #12] + 8008808: 60b9 str r1, [r7, #8] + 800880a: 607a str r2, [r7, #4] + 800880c: 70fb strb r3, [r7, #3] + LWIP_UNUSED_ARG(arg); + + LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG); + 800880e: 68bb ldr r3, [r7, #8] + 8008810: 2b00 cmp r3, #0 + 8008812: d109 bne.n 8008828 + 8008814: 4b12 ldr r3, [pc, #72] ; (8008860 ) + 8008816: f44f 62d3 mov.w r2, #1688 ; 0x698 + 800881a: 4912 ldr r1, [pc, #72] ; (8008864 ) + 800881c: 4812 ldr r0, [pc, #72] ; (8008868 ) + 800881e: f008 f9d3 bl 8010bc8 + 8008822: f06f 030f mvn.w r3, #15 + 8008826: e016 b.n 8008856 + + if (p != NULL) { + 8008828: 687b ldr r3, [r7, #4] + 800882a: 2b00 cmp r3, #0 + 800882c: d009 beq.n 8008842 + tcp_recved(pcb, p->tot_len); + 800882e: 687b ldr r3, [r7, #4] + 8008830: 891b ldrh r3, [r3, #8] + 8008832: 4619 mov r1, r3 + 8008834: 68b8 ldr r0, [r7, #8] + 8008836: f7ff f9bb bl 8007bb0 + pbuf_free(p); + 800883a: 6878 ldr r0, [r7, #4] + 800883c: f7fe fbca bl 8006fd4 + 8008840: e008 b.n 8008854 + } else if (err == ERR_OK) { + 8008842: f997 3003 ldrsb.w r3, [r7, #3] + 8008846: 2b00 cmp r3, #0 + 8008848: d104 bne.n 8008854 + return tcp_close(pcb); + 800884a: 68b8 ldr r0, [r7, #8] + 800884c: f7ff f860 bl 8007910 + 8008850: 4603 mov r3, r0 + 8008852: e000 b.n 8008856 + } + return ERR_OK; + 8008854: 2300 movs r3, #0 +} + 8008856: 4618 mov r0, r3 + 8008858: 3710 adds r7, #16 + 800885a: 46bd mov sp, r7 + 800885c: bd80 pop {r7, pc} + 800885e: bf00 nop + 8008860: 08012a08 .word 0x08012a08 + 8008864: 08012f78 .word 0x08012f78 + 8008868: 08012a4c .word 0x08012a4c + +0800886c : + * + * @param prio minimum priority + */ +static void +tcp_kill_prio(u8_t prio) +{ + 800886c: b580 push {r7, lr} + 800886e: b086 sub sp, #24 + 8008870: af00 add r7, sp, #0 + 8008872: 4603 mov r3, r0 + 8008874: 71fb strb r3, [r7, #7] + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + u8_t mprio; + + mprio = LWIP_MIN(TCP_PRIO_MAX, prio); + 8008876: f997 3007 ldrsb.w r3, [r7, #7] + 800887a: 2b00 cmp r3, #0 + 800887c: db01 blt.n 8008882 + 800887e: 79fb ldrb r3, [r7, #7] + 8008880: e000 b.n 8008884 + 8008882: 237f movs r3, #127 ; 0x7f + 8008884: 72fb strb r3, [r7, #11] + + /* We want to kill connections with a lower prio, so bail out if + * supplied prio is 0 - there can never be a lower prio + */ + if (mprio == 0) { + 8008886: 7afb ldrb r3, [r7, #11] + 8008888: 2b00 cmp r3, #0 + 800888a: d034 beq.n 80088f6 + /* We only want kill connections with a lower prio, so decrement prio by one + * and start searching for oldest connection with same or lower priority than mprio. + * We want to find the connections with the lowest possible prio, and among + * these the one with the longest inactivity time. + */ + mprio--; + 800888c: 7afb ldrb r3, [r7, #11] + 800888e: 3b01 subs r3, #1 + 8008890: 72fb strb r3, [r7, #11] + + inactivity = 0; + 8008892: 2300 movs r3, #0 + 8008894: 60fb str r3, [r7, #12] + inactive = NULL; + 8008896: 2300 movs r3, #0 + 8008898: 613b str r3, [r7, #16] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 800889a: 4b19 ldr r3, [pc, #100] ; (8008900 ) + 800889c: 681b ldr r3, [r3, #0] + 800889e: 617b str r3, [r7, #20] + 80088a0: e01f b.n 80088e2 + /* lower prio is always a kill candidate */ + if ((pcb->prio < mprio) || + 80088a2: 697b ldr r3, [r7, #20] + 80088a4: 7d5b ldrb r3, [r3, #21] + 80088a6: 7afa ldrb r2, [r7, #11] + 80088a8: 429a cmp r2, r3 + 80088aa: d80c bhi.n 80088c6 + /* longer inactivity is also a kill candidate */ + ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) { + 80088ac: 697b ldr r3, [r7, #20] + 80088ae: 7d5b ldrb r3, [r3, #21] + if ((pcb->prio < mprio) || + 80088b0: 7afa ldrb r2, [r7, #11] + 80088b2: 429a cmp r2, r3 + 80088b4: d112 bne.n 80088dc + ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) { + 80088b6: 4b13 ldr r3, [pc, #76] ; (8008904 ) + 80088b8: 681a ldr r2, [r3, #0] + 80088ba: 697b ldr r3, [r7, #20] + 80088bc: 6a1b ldr r3, [r3, #32] + 80088be: 1ad3 subs r3, r2, r3 + 80088c0: 68fa ldr r2, [r7, #12] + 80088c2: 429a cmp r2, r3 + 80088c4: d80a bhi.n 80088dc + inactivity = tcp_ticks - pcb->tmr; + 80088c6: 4b0f ldr r3, [pc, #60] ; (8008904 ) + 80088c8: 681a ldr r2, [r3, #0] + 80088ca: 697b ldr r3, [r7, #20] + 80088cc: 6a1b ldr r3, [r3, #32] + 80088ce: 1ad3 subs r3, r2, r3 + 80088d0: 60fb str r3, [r7, #12] + inactive = pcb; + 80088d2: 697b ldr r3, [r7, #20] + 80088d4: 613b str r3, [r7, #16] + mprio = pcb->prio; + 80088d6: 697b ldr r3, [r7, #20] + 80088d8: 7d5b ldrb r3, [r3, #21] + 80088da: 72fb strb r3, [r7, #11] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 80088dc: 697b ldr r3, [r7, #20] + 80088de: 68db ldr r3, [r3, #12] + 80088e0: 617b str r3, [r7, #20] + 80088e2: 697b ldr r3, [r7, #20] + 80088e4: 2b00 cmp r3, #0 + 80088e6: d1dc bne.n 80088a2 + } + } + if (inactive != NULL) { + 80088e8: 693b ldr r3, [r7, #16] + 80088ea: 2b00 cmp r3, #0 + 80088ec: d004 beq.n 80088f8 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + 80088ee: 6938 ldr r0, [r7, #16] + 80088f0: f7ff f8f8 bl 8007ae4 + 80088f4: e000 b.n 80088f8 + return; + 80088f6: bf00 nop + } +} + 80088f8: 3718 adds r7, #24 + 80088fa: 46bd mov sp, r7 + 80088fc: bd80 pop {r7, pc} + 80088fe: bf00 nop + 8008900: 24007b78 .word 0x24007b78 + 8008904: 24007b6c .word 0x24007b6c + +08008908 : + * Kills the oldest connection that is in specific state. + * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available. + */ +static void +tcp_kill_state(enum tcp_state state) +{ + 8008908: b580 push {r7, lr} + 800890a: b086 sub sp, #24 + 800890c: af00 add r7, sp, #0 + 800890e: 4603 mov r3, r0 + 8008910: 71fb strb r3, [r7, #7] + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK)); + 8008912: 79fb ldrb r3, [r7, #7] + 8008914: 2b08 cmp r3, #8 + 8008916: d009 beq.n 800892c + 8008918: 79fb ldrb r3, [r7, #7] + 800891a: 2b09 cmp r3, #9 + 800891c: d006 beq.n 800892c + 800891e: 4b1a ldr r3, [pc, #104] ; (8008988 ) + 8008920: f240 62dd movw r2, #1757 ; 0x6dd + 8008924: 4919 ldr r1, [pc, #100] ; (800898c ) + 8008926: 481a ldr r0, [pc, #104] ; (8008990 ) + 8008928: f008 f94e bl 8010bc8 + + inactivity = 0; + 800892c: 2300 movs r3, #0 + 800892e: 60fb str r3, [r7, #12] + inactive = NULL; + 8008930: 2300 movs r3, #0 + 8008932: 613b str r3, [r7, #16] + /* Go through the list of active pcbs and get the oldest pcb that is in state + CLOSING/LAST_ACK. */ + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 8008934: 4b17 ldr r3, [pc, #92] ; (8008994 ) + 8008936: 681b ldr r3, [r3, #0] + 8008938: 617b str r3, [r7, #20] + 800893a: e017 b.n 800896c + if (pcb->state == state) { + 800893c: 697b ldr r3, [r7, #20] + 800893e: 7d1b ldrb r3, [r3, #20] + 8008940: 79fa ldrb r2, [r7, #7] + 8008942: 429a cmp r2, r3 + 8008944: d10f bne.n 8008966 + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + 8008946: 4b14 ldr r3, [pc, #80] ; (8008998 ) + 8008948: 681a ldr r2, [r3, #0] + 800894a: 697b ldr r3, [r7, #20] + 800894c: 6a1b ldr r3, [r3, #32] + 800894e: 1ad3 subs r3, r2, r3 + 8008950: 68fa ldr r2, [r7, #12] + 8008952: 429a cmp r2, r3 + 8008954: d807 bhi.n 8008966 + inactivity = tcp_ticks - pcb->tmr; + 8008956: 4b10 ldr r3, [pc, #64] ; (8008998 ) + 8008958: 681a ldr r2, [r3, #0] + 800895a: 697b ldr r3, [r7, #20] + 800895c: 6a1b ldr r3, [r3, #32] + 800895e: 1ad3 subs r3, r2, r3 + 8008960: 60fb str r3, [r7, #12] + inactive = pcb; + 8008962: 697b ldr r3, [r7, #20] + 8008964: 613b str r3, [r7, #16] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 8008966: 697b ldr r3, [r7, #20] + 8008968: 68db ldr r3, [r3, #12] + 800896a: 617b str r3, [r7, #20] + 800896c: 697b ldr r3, [r7, #20] + 800896e: 2b00 cmp r3, #0 + 8008970: d1e4 bne.n 800893c + } + } + } + if (inactive != NULL) { + 8008972: 693b ldr r3, [r7, #16] + 8008974: 2b00 cmp r3, #0 + 8008976: d003 beq.n 8008980 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n", + tcp_state_str[state], (void *)inactive, inactivity)); + /* Don't send a RST, since no data is lost. */ + tcp_abandon(inactive, 0); + 8008978: 2100 movs r1, #0 + 800897a: 6938 ldr r0, [r7, #16] + 800897c: f7fe fff4 bl 8007968 + } +} + 8008980: bf00 nop + 8008982: 3718 adds r7, #24 + 8008984: 46bd mov sp, r7 + 8008986: bd80 pop {r7, pc} + 8008988: 08012a08 .word 0x08012a08 + 800898c: 08012f94 .word 0x08012f94 + 8008990: 08012a4c .word 0x08012a4c + 8008994: 24007b78 .word 0x24007b78 + 8008998: 24007b6c .word 0x24007b6c + +0800899c : + * Kills the oldest connection that is in TIME_WAIT state. + * Called from tcp_alloc() if no more connections are available. + */ +static void +tcp_kill_timewait(void) +{ + 800899c: b580 push {r7, lr} + 800899e: b084 sub sp, #16 + 80089a0: af00 add r7, sp, #0 + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + inactivity = 0; + 80089a2: 2300 movs r3, #0 + 80089a4: 607b str r3, [r7, #4] + inactive = NULL; + 80089a6: 2300 movs r3, #0 + 80089a8: 60bb str r3, [r7, #8] + /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 80089aa: 4b12 ldr r3, [pc, #72] ; (80089f4 ) + 80089ac: 681b ldr r3, [r3, #0] + 80089ae: 60fb str r3, [r7, #12] + 80089b0: e012 b.n 80089d8 + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + 80089b2: 4b11 ldr r3, [pc, #68] ; (80089f8 ) + 80089b4: 681a ldr r2, [r3, #0] + 80089b6: 68fb ldr r3, [r7, #12] + 80089b8: 6a1b ldr r3, [r3, #32] + 80089ba: 1ad3 subs r3, r2, r3 + 80089bc: 687a ldr r2, [r7, #4] + 80089be: 429a cmp r2, r3 + 80089c0: d807 bhi.n 80089d2 + inactivity = tcp_ticks - pcb->tmr; + 80089c2: 4b0d ldr r3, [pc, #52] ; (80089f8 ) + 80089c4: 681a ldr r2, [r3, #0] + 80089c6: 68fb ldr r3, [r7, #12] + 80089c8: 6a1b ldr r3, [r3, #32] + 80089ca: 1ad3 subs r3, r2, r3 + 80089cc: 607b str r3, [r7, #4] + inactive = pcb; + 80089ce: 68fb ldr r3, [r7, #12] + 80089d0: 60bb str r3, [r7, #8] + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 80089d2: 68fb ldr r3, [r7, #12] + 80089d4: 68db ldr r3, [r3, #12] + 80089d6: 60fb str r3, [r7, #12] + 80089d8: 68fb ldr r3, [r7, #12] + 80089da: 2b00 cmp r3, #0 + 80089dc: d1e9 bne.n 80089b2 + } + } + if (inactive != NULL) { + 80089de: 68bb ldr r3, [r7, #8] + 80089e0: 2b00 cmp r3, #0 + 80089e2: d002 beq.n 80089ea + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + 80089e4: 68b8 ldr r0, [r7, #8] + 80089e6: f7ff f87d bl 8007ae4 + } +} + 80089ea: bf00 nop + 80089ec: 3710 adds r7, #16 + 80089ee: 46bd mov sp, r7 + 80089f0: bd80 pop {r7, pc} + 80089f2: bf00 nop + 80089f4: 24007b7c .word 0x24007b7c + 80089f8: 24007b6c .word 0x24007b6c + +080089fc : + * now send the FIN (which failed before), the pcb might be in a state that is + * OK for us to now free it. + */ +static void +tcp_handle_closepend(void) +{ + 80089fc: b580 push {r7, lr} + 80089fe: b082 sub sp, #8 + 8008a00: af00 add r7, sp, #0 + struct tcp_pcb *pcb = tcp_active_pcbs; + 8008a02: 4b10 ldr r3, [pc, #64] ; (8008a44 ) + 8008a04: 681b ldr r3, [r3, #0] + 8008a06: 607b str r3, [r7, #4] + + while (pcb != NULL) { + 8008a08: e014 b.n 8008a34 + struct tcp_pcb *next = pcb->next; + 8008a0a: 687b ldr r3, [r7, #4] + 8008a0c: 68db ldr r3, [r3, #12] + 8008a0e: 603b str r3, [r7, #0] + /* send pending FIN */ + if (pcb->flags & TF_CLOSEPEND) { + 8008a10: 687b ldr r3, [r7, #4] + 8008a12: 8b5b ldrh r3, [r3, #26] + 8008a14: f003 0308 and.w r3, r3, #8 + 8008a18: 2b00 cmp r3, #0 + 8008a1a: d009 beq.n 8008a30 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n")); + tcp_clear_flags(pcb, TF_CLOSEPEND); + 8008a1c: 687b ldr r3, [r7, #4] + 8008a1e: 8b5b ldrh r3, [r3, #26] + 8008a20: f023 0308 bic.w r3, r3, #8 + 8008a24: b29a uxth r2, r3 + 8008a26: 687b ldr r3, [r7, #4] + 8008a28: 835a strh r2, [r3, #26] + tcp_close_shutdown_fin(pcb); + 8008a2a: 6878 ldr r0, [r7, #4] + 8008a2c: f7fe ff06 bl 800783c + } + pcb = next; + 8008a30: 683b ldr r3, [r7, #0] + 8008a32: 607b str r3, [r7, #4] + while (pcb != NULL) { + 8008a34: 687b ldr r3, [r7, #4] + 8008a36: 2b00 cmp r3, #0 + 8008a38: d1e7 bne.n 8008a0a + } +} + 8008a3a: bf00 nop + 8008a3c: bf00 nop + 8008a3e: 3708 adds r7, #8 + 8008a40: 46bd mov sp, r7 + 8008a42: bd80 pop {r7, pc} + 8008a44: 24007b78 .word 0x24007b78 + +08008a48 : + * @param prio priority for the new pcb + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_alloc(u8_t prio) +{ + 8008a48: b580 push {r7, lr} + 8008a4a: b084 sub sp, #16 + 8008a4c: af00 add r7, sp, #0 + 8008a4e: 4603 mov r3, r0 + 8008a50: 71fb strb r3, [r7, #7] + struct tcp_pcb *pcb; + + LWIP_ASSERT_CORE_LOCKED(); + + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8008a52: 2001 movs r0, #1 + 8008a54: f7fd fae2 bl 800601c + 8008a58: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 8008a5a: 68fb ldr r3, [r7, #12] + 8008a5c: 2b00 cmp r3, #0 + 8008a5e: d126 bne.n 8008aae + /* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */ + tcp_handle_closepend(); + 8008a60: f7ff ffcc bl 80089fc + + /* Try killing oldest connection in TIME-WAIT. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); + tcp_kill_timewait(); + 8008a64: f7ff ff9a bl 800899c + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8008a68: 2001 movs r0, #1 + 8008a6a: f7fd fad7 bl 800601c + 8008a6e: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 8008a70: 68fb ldr r3, [r7, #12] + 8008a72: 2b00 cmp r3, #0 + 8008a74: d11b bne.n 8008aae + /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n")); + tcp_kill_state(LAST_ACK); + 8008a76: 2009 movs r0, #9 + 8008a78: f7ff ff46 bl 8008908 + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8008a7c: 2001 movs r0, #1 + 8008a7e: f7fd facd bl 800601c + 8008a82: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 8008a84: 68fb ldr r3, [r7, #12] + 8008a86: 2b00 cmp r3, #0 + 8008a88: d111 bne.n 8008aae + /* Try killing oldest connection in CLOSING. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n")); + tcp_kill_state(CLOSING); + 8008a8a: 2008 movs r0, #8 + 8008a8c: f7ff ff3c bl 8008908 + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8008a90: 2001 movs r0, #1 + 8008a92: f7fd fac3 bl 800601c + 8008a96: 60f8 str r0, [r7, #12] + if (pcb == NULL) { + 8008a98: 68fb ldr r3, [r7, #12] + 8008a9a: 2b00 cmp r3, #0 + 8008a9c: d107 bne.n 8008aae + /* Try killing oldest active connection with lower priority than the new one. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio)); + tcp_kill_prio(prio); + 8008a9e: 79fb ldrb r3, [r7, #7] + 8008aa0: 4618 mov r0, r3 + 8008aa2: f7ff fee3 bl 800886c + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + 8008aa6: 2001 movs r0, #1 + 8008aa8: f7fd fab8 bl 800601c + 8008aac: 60f8 str r0, [r7, #12] + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed above */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + 8008aae: 68fb ldr r3, [r7, #12] + 8008ab0: 2b00 cmp r3, #0 + 8008ab2: d03f beq.n 8008b34 + /* zero out the whole pcb, so there is no need to initialize members to zero */ + memset(pcb, 0, sizeof(struct tcp_pcb)); + 8008ab4: 229c movs r2, #156 ; 0x9c + 8008ab6: 2100 movs r1, #0 + 8008ab8: 68f8 ldr r0, [r7, #12] + 8008aba: f008 f9e3 bl 8010e84 + pcb->prio = prio; + 8008abe: 68fb ldr r3, [r7, #12] + 8008ac0: 79fa ldrb r2, [r7, #7] + 8008ac2: 755a strb r2, [r3, #21] + pcb->snd_buf = TCP_SND_BUF; + 8008ac4: 68fb ldr r3, [r7, #12] + 8008ac6: f44f 6286 mov.w r2, #1072 ; 0x430 + 8008aca: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 + /* Start with a window that does not need scaling. When window scaling is + enabled and used, the window is enlarged when both sides agree on scaling. */ + pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); + 8008ace: 68fb ldr r3, [r7, #12] + 8008ad0: f44f 6206 mov.w r2, #2144 ; 0x860 + 8008ad4: 855a strh r2, [r3, #42] ; 0x2a + 8008ad6: 68fb ldr r3, [r7, #12] + 8008ad8: 8d5a ldrh r2, [r3, #42] ; 0x2a + 8008ada: 68fb ldr r3, [r7, #12] + 8008adc: 851a strh r2, [r3, #40] ; 0x28 + pcb->ttl = TCP_TTL; + 8008ade: 68fb ldr r3, [r7, #12] + 8008ae0: 22ff movs r2, #255 ; 0xff + 8008ae2: 72da strb r2, [r3, #11] + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = INITIAL_MSS; + 8008ae4: 68fb ldr r3, [r7, #12] + 8008ae6: f44f 7206 mov.w r2, #536 ; 0x218 + 8008aea: 865a strh r2, [r3, #50] ; 0x32 + pcb->rto = 3000 / TCP_SLOW_INTERVAL; + 8008aec: 68fb ldr r3, [r7, #12] + 8008aee: 2206 movs r2, #6 + 8008af0: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + pcb->sv = 3000 / TCP_SLOW_INTERVAL; + 8008af4: 68fb ldr r3, [r7, #12] + 8008af6: 2206 movs r2, #6 + 8008af8: 87da strh r2, [r3, #62] ; 0x3e + pcb->rtime = -1; + 8008afa: 68fb ldr r3, [r7, #12] + 8008afc: f64f 72ff movw r2, #65535 ; 0xffff + 8008b00: 861a strh r2, [r3, #48] ; 0x30 + pcb->cwnd = 1; + 8008b02: 68fb ldr r3, [r7, #12] + 8008b04: 2201 movs r2, #1 + 8008b06: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + pcb->tmr = tcp_ticks; + 8008b0a: 4b0d ldr r3, [pc, #52] ; (8008b40 ) + 8008b0c: 681a ldr r2, [r3, #0] + 8008b0e: 68fb ldr r3, [r7, #12] + 8008b10: 621a str r2, [r3, #32] + pcb->last_timer = tcp_timer_ctr; + 8008b12: 4b0c ldr r3, [pc, #48] ; (8008b44 ) + 8008b14: 781a ldrb r2, [r3, #0] + 8008b16: 68fb ldr r3, [r7, #12] + 8008b18: 779a strb r2, [r3, #30] + of using the largest advertised receive window. We've seen complications with + receiving TCPs that use window scaling and/or window auto-tuning where the + initial advertised window is very small and then grows rapidly once the + connection is established. To avoid these complications, we set ssthresh to the + largest effective cwnd (amount of in-flight data) that the sender can have. */ + pcb->ssthresh = TCP_SND_BUF; + 8008b1a: 68fb ldr r3, [r7, #12] + 8008b1c: f44f 6286 mov.w r2, #1072 ; 0x430 + 8008b20: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + +#if LWIP_CALLBACK_API + pcb->recv = tcp_recv_null; + 8008b24: 68fb ldr r3, [r7, #12] + 8008b26: 4a08 ldr r2, [pc, #32] ; (8008b48 ) + 8008b28: f8c3 2084 str.w r2, [r3, #132] ; 0x84 +#endif /* LWIP_CALLBACK_API */ + + /* Init KEEPALIVE timer */ + pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; + 8008b2c: 68fb ldr r3, [r7, #12] + 8008b2e: 4a07 ldr r2, [pc, #28] ; (8008b4c ) + 8008b30: f8c3 2094 str.w r2, [r3, #148] ; 0x94 +#if LWIP_TCP_KEEPALIVE + pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; + pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; +#endif /* LWIP_TCP_KEEPALIVE */ + } + return pcb; + 8008b34: 68fb ldr r3, [r7, #12] +} + 8008b36: 4618 mov r0, r3 + 8008b38: 3710 adds r7, #16 + 8008b3a: 46bd mov sp, r7 + 8008b3c: bd80 pop {r7, pc} + 8008b3e: bf00 nop + 8008b40: 24007b6c .word 0x24007b6c + 8008b44: 24007b82 .word 0x24007b82 + 8008b48: 08008801 .word 0x08008801 + 8008b4c: 006ddd00 .word 0x006ddd00 + +08008b50 : + * + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_new(void) +{ + 8008b50: b580 push {r7, lr} + 8008b52: af00 add r7, sp, #0 + return tcp_alloc(TCP_PRIO_NORMAL); + 8008b54: 2040 movs r0, #64 ; 0x40 + 8008b56: f7ff ff77 bl 8008a48 + 8008b5a: 4603 mov r3, r0 +} + 8008b5c: 4618 mov r0, r3 + 8008b5e: bd80 pop {r7, pc} + +08008b60 : + * @param pcb tcp_pcb to set the callback argument + * @param arg void pointer argument to pass to callback functions + */ +void +tcp_arg(struct tcp_pcb *pcb, void *arg) +{ + 8008b60: b480 push {r7} + 8008b62: b083 sub sp, #12 + 8008b64: af00 add r7, sp, #0 + 8008b66: 6078 str r0, [r7, #4] + 8008b68: 6039 str r1, [r7, #0] + LWIP_ASSERT_CORE_LOCKED(); + /* This function is allowed to be called for both listen pcbs and + connection pcbs. */ + if (pcb != NULL) { + 8008b6a: 687b ldr r3, [r7, #4] + 8008b6c: 2b00 cmp r3, #0 + 8008b6e: d002 beq.n 8008b76 + pcb->callback_arg = arg; + 8008b70: 687b ldr r3, [r7, #4] + 8008b72: 683a ldr r2, [r7, #0] + 8008b74: 611a str r2, [r3, #16] + } +} + 8008b76: bf00 nop + 8008b78: 370c adds r7, #12 + 8008b7a: 46bd mov sp, r7 + 8008b7c: f85d 7b04 ldr.w r7, [sp], #4 + 8008b80: 4770 bx lr + ... + +08008b84 : + * @param pcb tcp_pcb to set the recv callback + * @param recv callback function to call for this pcb when data is received + */ +void +tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv) +{ + 8008b84: b580 push {r7, lr} + 8008b86: b082 sub sp, #8 + 8008b88: af00 add r7, sp, #0 + 8008b8a: 6078 str r0, [r7, #4] + 8008b8c: 6039 str r1, [r7, #0] + LWIP_ASSERT_CORE_LOCKED(); + if (pcb != NULL) { + 8008b8e: 687b ldr r3, [r7, #4] + 8008b90: 2b00 cmp r3, #0 + 8008b92: d00e beq.n 8008bb2 + LWIP_ASSERT("invalid socket state for recv callback", pcb->state != LISTEN); + 8008b94: 687b ldr r3, [r7, #4] + 8008b96: 7d1b ldrb r3, [r3, #20] + 8008b98: 2b01 cmp r3, #1 + 8008b9a: d106 bne.n 8008baa + 8008b9c: 4b07 ldr r3, [pc, #28] ; (8008bbc ) + 8008b9e: f240 72df movw r2, #2015 ; 0x7df + 8008ba2: 4907 ldr r1, [pc, #28] ; (8008bc0 ) + 8008ba4: 4807 ldr r0, [pc, #28] ; (8008bc4 ) + 8008ba6: f008 f80f bl 8010bc8 + pcb->recv = recv; + 8008baa: 687b ldr r3, [r7, #4] + 8008bac: 683a ldr r2, [r7, #0] + 8008bae: f8c3 2084 str.w r2, [r3, #132] ; 0x84 + } +} + 8008bb2: bf00 nop + 8008bb4: 3708 adds r7, #8 + 8008bb6: 46bd mov sp, r7 + 8008bb8: bd80 pop {r7, pc} + 8008bba: bf00 nop + 8008bbc: 08012a08 .word 0x08012a08 + 8008bc0: 08012fa4 .word 0x08012fa4 + 8008bc4: 08012a4c .word 0x08012a4c + +08008bc8 : + * @param pcb tcp_pcb to set the sent callback + * @param sent callback function to call for this pcb when data is successfully sent + */ +void +tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent) +{ + 8008bc8: b580 push {r7, lr} + 8008bca: b082 sub sp, #8 + 8008bcc: af00 add r7, sp, #0 + 8008bce: 6078 str r0, [r7, #4] + 8008bd0: 6039 str r1, [r7, #0] + LWIP_ASSERT_CORE_LOCKED(); + if (pcb != NULL) { + 8008bd2: 687b ldr r3, [r7, #4] + 8008bd4: 2b00 cmp r3, #0 + 8008bd6: d00e beq.n 8008bf6 + LWIP_ASSERT("invalid socket state for sent callback", pcb->state != LISTEN); + 8008bd8: 687b ldr r3, [r7, #4] + 8008bda: 7d1b ldrb r3, [r3, #20] + 8008bdc: 2b01 cmp r3, #1 + 8008bde: d106 bne.n 8008bee + 8008be0: 4b07 ldr r3, [pc, #28] ; (8008c00 ) + 8008be2: f240 72f3 movw r2, #2035 ; 0x7f3 + 8008be6: 4907 ldr r1, [pc, #28] ; (8008c04 ) + 8008be8: 4807 ldr r0, [pc, #28] ; (8008c08 ) + 8008bea: f007 ffed bl 8010bc8 + pcb->sent = sent; + 8008bee: 687b ldr r3, [r7, #4] + 8008bf0: 683a ldr r2, [r7, #0] + 8008bf2: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + } +} + 8008bf6: bf00 nop + 8008bf8: 3708 adds r7, #8 + 8008bfa: 46bd mov sp, r7 + 8008bfc: bd80 pop {r7, pc} + 8008bfe: bf00 nop + 8008c00: 08012a08 .word 0x08012a08 + 8008c04: 08012fcc .word 0x08012fcc + 8008c08: 08012a4c .word 0x08012a4c + +08008c0c : + * @param err callback function to call for this pcb when a fatal error + * has occurred on the connection + */ +void +tcp_err(struct tcp_pcb *pcb, tcp_err_fn err) +{ + 8008c0c: b580 push {r7, lr} + 8008c0e: b082 sub sp, #8 + 8008c10: af00 add r7, sp, #0 + 8008c12: 6078 str r0, [r7, #4] + 8008c14: 6039 str r1, [r7, #0] + LWIP_ASSERT_CORE_LOCKED(); + if (pcb != NULL) { + 8008c16: 687b ldr r3, [r7, #4] + 8008c18: 2b00 cmp r3, #0 + 8008c1a: d00e beq.n 8008c3a + LWIP_ASSERT("invalid socket state for err callback", pcb->state != LISTEN); + 8008c1c: 687b ldr r3, [r7, #4] + 8008c1e: 7d1b ldrb r3, [r3, #20] + 8008c20: 2b01 cmp r3, #1 + 8008c22: d106 bne.n 8008c32 + 8008c24: 4b07 ldr r3, [pc, #28] ; (8008c44 ) + 8008c26: f640 020d movw r2, #2061 ; 0x80d + 8008c2a: 4907 ldr r1, [pc, #28] ; (8008c48 ) + 8008c2c: 4807 ldr r0, [pc, #28] ; (8008c4c ) + 8008c2e: f007 ffcb bl 8010bc8 + pcb->errf = err; + 8008c32: 687b ldr r3, [r7, #4] + 8008c34: 683a ldr r2, [r7, #0] + 8008c36: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } +} + 8008c3a: bf00 nop + 8008c3c: 3708 adds r7, #8 + 8008c3e: 46bd mov sp, r7 + 8008c40: bd80 pop {r7, pc} + 8008c42: bf00 nop + 8008c44: 08012a08 .word 0x08012a08 + 8008c48: 08012ff4 .word 0x08012ff4 + 8008c4c: 08012a4c .word 0x08012a4c + +08008c50 : + * + * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! + */ +void +tcp_pcb_purge(struct tcp_pcb *pcb) +{ + 8008c50: b580 push {r7, lr} + 8008c52: b082 sub sp, #8 + 8008c54: af00 add r7, sp, #0 + 8008c56: 6078 str r0, [r7, #4] + LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return); + 8008c58: 687b ldr r3, [r7, #4] + 8008c5a: 2b00 cmp r3, #0 + 8008c5c: d107 bne.n 8008c6e + 8008c5e: 4b21 ldr r3, [pc, #132] ; (8008ce4 ) + 8008c60: f640 0251 movw r2, #2129 ; 0x851 + 8008c64: 4920 ldr r1, [pc, #128] ; (8008ce8 ) + 8008c66: 4821 ldr r0, [pc, #132] ; (8008cec ) + 8008c68: f007 ffae bl 8010bc8 + 8008c6c: e037 b.n 8008cde + + if (pcb->state != CLOSED && + 8008c6e: 687b ldr r3, [r7, #4] + 8008c70: 7d1b ldrb r3, [r3, #20] + 8008c72: 2b00 cmp r3, #0 + 8008c74: d033 beq.n 8008cde + pcb->state != TIME_WAIT && + 8008c76: 687b ldr r3, [r7, #4] + 8008c78: 7d1b ldrb r3, [r3, #20] + if (pcb->state != CLOSED && + 8008c7a: 2b0a cmp r3, #10 + 8008c7c: d02f beq.n 8008cde + pcb->state != LISTEN) { + 8008c7e: 687b ldr r3, [r7, #4] + 8008c80: 7d1b ldrb r3, [r3, #20] + pcb->state != TIME_WAIT && + 8008c82: 2b01 cmp r3, #1 + 8008c84: d02b beq.n 8008cde + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); + + tcp_backlog_accepted(pcb); + + if (pcb->refused_data != NULL) { + 8008c86: 687b ldr r3, [r7, #4] + 8008c88: 6f9b ldr r3, [r3, #120] ; 0x78 + 8008c8a: 2b00 cmp r3, #0 + 8008c8c: d007 beq.n 8008c9e + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); + pbuf_free(pcb->refused_data); + 8008c8e: 687b ldr r3, [r7, #4] + 8008c90: 6f9b ldr r3, [r3, #120] ; 0x78 + 8008c92: 4618 mov r0, r3 + 8008c94: f7fe f99e bl 8006fd4 + pcb->refused_data = NULL; + 8008c98: 687b ldr r3, [r7, #4] + 8008c9a: 2200 movs r2, #0 + 8008c9c: 679a str r2, [r3, #120] ; 0x78 + } + if (pcb->unacked != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + 8008c9e: 687b ldr r3, [r7, #4] + 8008ca0: 6f5b ldr r3, [r3, #116] ; 0x74 + 8008ca2: 2b00 cmp r3, #0 + 8008ca4: d002 beq.n 8008cac + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); + tcp_free_ooseq(pcb); + 8008ca6: 6878 ldr r0, [r7, #4] + 8008ca8: f000 f98c bl 8008fc4 + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Stop the retransmission timer as it will expect data on unacked + queue if it fires */ + pcb->rtime = -1; + 8008cac: 687b ldr r3, [r7, #4] + 8008cae: f64f 72ff movw r2, #65535 ; 0xffff + 8008cb2: 861a strh r2, [r3, #48] ; 0x30 + + tcp_segs_free(pcb->unsent); + 8008cb4: 687b ldr r3, [r7, #4] + 8008cb6: 6edb ldr r3, [r3, #108] ; 0x6c + 8008cb8: 4618 mov r0, r3 + 8008cba: f7ff fd47 bl 800874c + tcp_segs_free(pcb->unacked); + 8008cbe: 687b ldr r3, [r7, #4] + 8008cc0: 6f1b ldr r3, [r3, #112] ; 0x70 + 8008cc2: 4618 mov r0, r3 + 8008cc4: f7ff fd42 bl 800874c + pcb->unacked = pcb->unsent = NULL; + 8008cc8: 687b ldr r3, [r7, #4] + 8008cca: 2200 movs r2, #0 + 8008ccc: 66da str r2, [r3, #108] ; 0x6c + 8008cce: 687b ldr r3, [r7, #4] + 8008cd0: 6eda ldr r2, [r3, #108] ; 0x6c + 8008cd2: 687b ldr r3, [r7, #4] + 8008cd4: 671a str r2, [r3, #112] ; 0x70 +#if TCP_OVERSIZE + pcb->unsent_oversize = 0; + 8008cd6: 687b ldr r3, [r7, #4] + 8008cd8: 2200 movs r2, #0 + 8008cda: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 +#endif /* TCP_OVERSIZE */ + } +} + 8008cde: 3708 adds r7, #8 + 8008ce0: 46bd mov sp, r7 + 8008ce2: bd80 pop {r7, pc} + 8008ce4: 08012a08 .word 0x08012a08 + 8008ce8: 08013054 .word 0x08013054 + 8008cec: 08012a4c .word 0x08012a4c + +08008cf0 : + * @param pcblist PCB list to purge. + * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! + */ +void +tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) +{ + 8008cf0: b580 push {r7, lr} + 8008cf2: b084 sub sp, #16 + 8008cf4: af00 add r7, sp, #0 + 8008cf6: 6078 str r0, [r7, #4] + 8008cf8: 6039 str r1, [r7, #0] + LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL); + 8008cfa: 683b ldr r3, [r7, #0] + 8008cfc: 2b00 cmp r3, #0 + 8008cfe: d106 bne.n 8008d0e + 8008d00: 4b3e ldr r3, [pc, #248] ; (8008dfc ) + 8008d02: f640 0283 movw r2, #2179 ; 0x883 + 8008d06: 493e ldr r1, [pc, #248] ; (8008e00 ) + 8008d08: 483e ldr r0, [pc, #248] ; (8008e04 ) + 8008d0a: f007 ff5d bl 8010bc8 + LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL); + 8008d0e: 687b ldr r3, [r7, #4] + 8008d10: 2b00 cmp r3, #0 + 8008d12: d106 bne.n 8008d22 + 8008d14: 4b39 ldr r3, [pc, #228] ; (8008dfc ) + 8008d16: f640 0284 movw r2, #2180 ; 0x884 + 8008d1a: 493b ldr r1, [pc, #236] ; (8008e08 ) + 8008d1c: 4839 ldr r0, [pc, #228] ; (8008e04 ) + 8008d1e: f007 ff53 bl 8010bc8 + + TCP_RMV(pcblist, pcb); + 8008d22: 687b ldr r3, [r7, #4] + 8008d24: 681b ldr r3, [r3, #0] + 8008d26: 683a ldr r2, [r7, #0] + 8008d28: 429a cmp r2, r3 + 8008d2a: d105 bne.n 8008d38 + 8008d2c: 687b ldr r3, [r7, #4] + 8008d2e: 681b ldr r3, [r3, #0] + 8008d30: 68da ldr r2, [r3, #12] + 8008d32: 687b ldr r3, [r7, #4] + 8008d34: 601a str r2, [r3, #0] + 8008d36: e013 b.n 8008d60 + 8008d38: 687b ldr r3, [r7, #4] + 8008d3a: 681b ldr r3, [r3, #0] + 8008d3c: 60fb str r3, [r7, #12] + 8008d3e: e00c b.n 8008d5a + 8008d40: 68fb ldr r3, [r7, #12] + 8008d42: 68db ldr r3, [r3, #12] + 8008d44: 683a ldr r2, [r7, #0] + 8008d46: 429a cmp r2, r3 + 8008d48: d104 bne.n 8008d54 + 8008d4a: 683b ldr r3, [r7, #0] + 8008d4c: 68da ldr r2, [r3, #12] + 8008d4e: 68fb ldr r3, [r7, #12] + 8008d50: 60da str r2, [r3, #12] + 8008d52: e005 b.n 8008d60 + 8008d54: 68fb ldr r3, [r7, #12] + 8008d56: 68db ldr r3, [r3, #12] + 8008d58: 60fb str r3, [r7, #12] + 8008d5a: 68fb ldr r3, [r7, #12] + 8008d5c: 2b00 cmp r3, #0 + 8008d5e: d1ef bne.n 8008d40 + 8008d60: 683b ldr r3, [r7, #0] + 8008d62: 2200 movs r2, #0 + 8008d64: 60da str r2, [r3, #12] + + tcp_pcb_purge(pcb); + 8008d66: 6838 ldr r0, [r7, #0] + 8008d68: f7ff ff72 bl 8008c50 + + /* if there is an outstanding delayed ACKs, send it */ + if ((pcb->state != TIME_WAIT) && + 8008d6c: 683b ldr r3, [r7, #0] + 8008d6e: 7d1b ldrb r3, [r3, #20] + 8008d70: 2b0a cmp r3, #10 + 8008d72: d013 beq.n 8008d9c + (pcb->state != LISTEN) && + 8008d74: 683b ldr r3, [r7, #0] + 8008d76: 7d1b ldrb r3, [r3, #20] + if ((pcb->state != TIME_WAIT) && + 8008d78: 2b01 cmp r3, #1 + 8008d7a: d00f beq.n 8008d9c + (pcb->flags & TF_ACK_DELAY)) { + 8008d7c: 683b ldr r3, [r7, #0] + 8008d7e: 8b5b ldrh r3, [r3, #26] + 8008d80: f003 0301 and.w r3, r3, #1 + (pcb->state != LISTEN) && + 8008d84: 2b00 cmp r3, #0 + 8008d86: d009 beq.n 8008d9c + tcp_ack_now(pcb); + 8008d88: 683b ldr r3, [r7, #0] + 8008d8a: 8b5b ldrh r3, [r3, #26] + 8008d8c: f043 0302 orr.w r3, r3, #2 + 8008d90: b29a uxth r2, r3 + 8008d92: 683b ldr r3, [r7, #0] + 8008d94: 835a strh r2, [r3, #26] + tcp_output(pcb); + 8008d96: 6838 ldr r0, [r7, #0] + 8008d98: f003 fc2c bl 800c5f4 + } + + if (pcb->state != LISTEN) { + 8008d9c: 683b ldr r3, [r7, #0] + 8008d9e: 7d1b ldrb r3, [r3, #20] + 8008da0: 2b01 cmp r3, #1 + 8008da2: d020 beq.n 8008de6 + LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); + 8008da4: 683b ldr r3, [r7, #0] + 8008da6: 6edb ldr r3, [r3, #108] ; 0x6c + 8008da8: 2b00 cmp r3, #0 + 8008daa: d006 beq.n 8008dba + 8008dac: 4b13 ldr r3, [pc, #76] ; (8008dfc ) + 8008dae: f640 0293 movw r2, #2195 ; 0x893 + 8008db2: 4916 ldr r1, [pc, #88] ; (8008e0c ) + 8008db4: 4813 ldr r0, [pc, #76] ; (8008e04 ) + 8008db6: f007 ff07 bl 8010bc8 + LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); + 8008dba: 683b ldr r3, [r7, #0] + 8008dbc: 6f1b ldr r3, [r3, #112] ; 0x70 + 8008dbe: 2b00 cmp r3, #0 + 8008dc0: d006 beq.n 8008dd0 + 8008dc2: 4b0e ldr r3, [pc, #56] ; (8008dfc ) + 8008dc4: f640 0294 movw r2, #2196 ; 0x894 + 8008dc8: 4911 ldr r1, [pc, #68] ; (8008e10 ) + 8008dca: 480e ldr r0, [pc, #56] ; (8008e04 ) + 8008dcc: f007 fefc bl 8010bc8 +#if TCP_QUEUE_OOSEQ + LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); + 8008dd0: 683b ldr r3, [r7, #0] + 8008dd2: 6f5b ldr r3, [r3, #116] ; 0x74 + 8008dd4: 2b00 cmp r3, #0 + 8008dd6: d006 beq.n 8008de6 + 8008dd8: 4b08 ldr r3, [pc, #32] ; (8008dfc ) + 8008dda: f640 0296 movw r2, #2198 ; 0x896 + 8008dde: 490d ldr r1, [pc, #52] ; (8008e14 ) + 8008de0: 4808 ldr r0, [pc, #32] ; (8008e04 ) + 8008de2: f007 fef1 bl 8010bc8 +#endif /* TCP_QUEUE_OOSEQ */ + } + + pcb->state = CLOSED; + 8008de6: 683b ldr r3, [r7, #0] + 8008de8: 2200 movs r2, #0 + 8008dea: 751a strb r2, [r3, #20] + /* reset the local port to prevent the pcb from being 'bound' */ + pcb->local_port = 0; + 8008dec: 683b ldr r3, [r7, #0] + 8008dee: 2200 movs r2, #0 + 8008df0: 82da strh r2, [r3, #22] + + LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); +} + 8008df2: bf00 nop + 8008df4: 3710 adds r7, #16 + 8008df6: 46bd mov sp, r7 + 8008df8: bd80 pop {r7, pc} + 8008dfa: bf00 nop + 8008dfc: 08012a08 .word 0x08012a08 + 8008e00: 08013070 .word 0x08013070 + 8008e04: 08012a4c .word 0x08012a4c + 8008e08: 0801308c .word 0x0801308c + 8008e0c: 080130ac .word 0x080130ac + 8008e10: 080130c4 .word 0x080130c4 + 8008e14: 080130e0 .word 0x080130e0 + +08008e18 : + * + * @return u32_t pseudo random sequence number + */ +u32_t +tcp_next_iss(struct tcp_pcb *pcb) +{ + 8008e18: b580 push {r7, lr} + 8008e1a: b082 sub sp, #8 + 8008e1c: af00 add r7, sp, #0 + 8008e1e: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); + return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port); +#else /* LWIP_HOOK_TCP_ISN */ + static u32_t iss = 6510; + + LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); + 8008e20: 687b ldr r3, [r7, #4] + 8008e22: 2b00 cmp r3, #0 + 8008e24: d106 bne.n 8008e34 + 8008e26: 4b0a ldr r3, [pc, #40] ; (8008e50 ) + 8008e28: f640 02af movw r2, #2223 ; 0x8af + 8008e2c: 4909 ldr r1, [pc, #36] ; (8008e54 ) + 8008e2e: 480a ldr r0, [pc, #40] ; (8008e58 ) + 8008e30: f007 feca bl 8010bc8 + LWIP_UNUSED_ARG(pcb); + + iss += tcp_ticks; /* XXX */ + 8008e34: 4b09 ldr r3, [pc, #36] ; (8008e5c ) + 8008e36: 681a ldr r2, [r3, #0] + 8008e38: 4b09 ldr r3, [pc, #36] ; (8008e60 ) + 8008e3a: 681b ldr r3, [r3, #0] + 8008e3c: 4413 add r3, r2 + 8008e3e: 4a07 ldr r2, [pc, #28] ; (8008e5c ) + 8008e40: 6013 str r3, [r2, #0] + return iss; + 8008e42: 4b06 ldr r3, [pc, #24] ; (8008e5c ) + 8008e44: 681b ldr r3, [r3, #0] +#endif /* LWIP_HOOK_TCP_ISN */ +} + 8008e46: 4618 mov r0, r3 + 8008e48: 3708 adds r7, #8 + 8008e4a: 46bd mov sp, r7 + 8008e4c: bd80 pop {r7, pc} + 8008e4e: bf00 nop + 8008e50: 08012a08 .word 0x08012a08 + 8008e54: 080130f8 .word 0x080130f8 + 8008e58: 08012a4c .word 0x08012a4c + 8008e5c: 2400006c .word 0x2400006c + 8008e60: 24007b6c .word 0x24007b6c + +08008e64 : + * by calculating the minimum of TCP_MSS and the mtu (if set) of the target + * netif (if not NULL). + */ +u16_t +tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest) +{ + 8008e64: b580 push {r7, lr} + 8008e66: b086 sub sp, #24 + 8008e68: af00 add r7, sp, #0 + 8008e6a: 4603 mov r3, r0 + 8008e6c: 60b9 str r1, [r7, #8] + 8008e6e: 607a str r2, [r7, #4] + 8008e70: 81fb strh r3, [r7, #14] + u16_t mss_s; + u16_t mtu; + + LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */ + + LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL); + 8008e72: 687b ldr r3, [r7, #4] + 8008e74: 2b00 cmp r3, #0 + 8008e76: d106 bne.n 8008e86 + 8008e78: 4b14 ldr r3, [pc, #80] ; (8008ecc ) + 8008e7a: f640 02c5 movw r2, #2245 ; 0x8c5 + 8008e7e: 4914 ldr r1, [pc, #80] ; (8008ed0 ) + 8008e80: 4814 ldr r0, [pc, #80] ; (8008ed4 ) + 8008e82: f007 fea1 bl 8010bc8 + else +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + { + if (outif == NULL) { + 8008e86: 68bb ldr r3, [r7, #8] + 8008e88: 2b00 cmp r3, #0 + 8008e8a: d101 bne.n 8008e90 + return sendmss; + 8008e8c: 89fb ldrh r3, [r7, #14] + 8008e8e: e019 b.n 8008ec4 + } + mtu = outif->mtu; + 8008e90: 68bb ldr r3, [r7, #8] + 8008e92: 8c9b ldrh r3, [r3, #36] ; 0x24 + 8008e94: 82fb strh r3, [r7, #22] + } +#endif /* LWIP_IPV4 */ + + if (mtu != 0) { + 8008e96: 8afb ldrh r3, [r7, #22] + 8008e98: 2b00 cmp r3, #0 + 8008e9a: d012 beq.n 8008ec2 + else +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + { + offset = IP_HLEN + TCP_HLEN; + 8008e9c: 2328 movs r3, #40 ; 0x28 + 8008e9e: 82bb strh r3, [r7, #20] + } +#endif /* LWIP_IPV4 */ + mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0; + 8008ea0: 8afa ldrh r2, [r7, #22] + 8008ea2: 8abb ldrh r3, [r7, #20] + 8008ea4: 429a cmp r2, r3 + 8008ea6: d904 bls.n 8008eb2 + 8008ea8: 8afa ldrh r2, [r7, #22] + 8008eaa: 8abb ldrh r3, [r7, #20] + 8008eac: 1ad3 subs r3, r2, r3 + 8008eae: b29b uxth r3, r3 + 8008eb0: e000 b.n 8008eb4 + 8008eb2: 2300 movs r3, #0 + 8008eb4: 827b strh r3, [r7, #18] + /* RFC 1122, chap 4.2.2.6: + * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize + * We correct for TCP options in tcp_write(), and don't support IP options. + */ + sendmss = LWIP_MIN(sendmss, mss_s); + 8008eb6: 8a7a ldrh r2, [r7, #18] + 8008eb8: 89fb ldrh r3, [r7, #14] + 8008eba: 4293 cmp r3, r2 + 8008ebc: bf28 it cs + 8008ebe: 4613 movcs r3, r2 + 8008ec0: 81fb strh r3, [r7, #14] + } + return sendmss; + 8008ec2: 89fb ldrh r3, [r7, #14] +} + 8008ec4: 4618 mov r0, r3 + 8008ec6: 3718 adds r7, #24 + 8008ec8: 46bd mov sp, r7 + 8008eca: bd80 pop {r7, pc} + 8008ecc: 08012a08 .word 0x08012a08 + 8008ed0: 08013114 .word 0x08013114 + 8008ed4: 08012a4c .word 0x08012a4c + +08008ed8 : +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */ +static void +tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list) +{ + 8008ed8: b580 push {r7, lr} + 8008eda: b084 sub sp, #16 + 8008edc: af00 add r7, sp, #0 + 8008ede: 6078 str r0, [r7, #4] + 8008ee0: 6039 str r1, [r7, #0] + struct tcp_pcb *pcb; + pcb = pcb_list; + 8008ee2: 683b ldr r3, [r7, #0] + 8008ee4: 60fb str r3, [r7, #12] + + LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL); + 8008ee6: 687b ldr r3, [r7, #4] + 8008ee8: 2b00 cmp r3, #0 + 8008eea: d11d bne.n 8008f28 + 8008eec: 4b12 ldr r3, [pc, #72] ; (8008f38 ) + 8008eee: f44f 6210 mov.w r2, #2304 ; 0x900 + 8008ef2: 4912 ldr r1, [pc, #72] ; (8008f3c ) + 8008ef4: 4812 ldr r0, [pc, #72] ; (8008f40 ) + 8008ef6: f007 fe67 bl 8010bc8 + + while (pcb != NULL) { + 8008efa: e015 b.n 8008f28 + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&pcb->local_ip, old_addr) + 8008efc: 68fb ldr r3, [r7, #12] + 8008efe: 681a ldr r2, [r3, #0] + 8008f00: 687b ldr r3, [r7, #4] + 8008f02: 681b ldr r3, [r3, #0] + 8008f04: 429a cmp r2, r3 + 8008f06: d10c bne.n 8008f22 + /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */ + && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip))) +#endif /* LWIP_AUTOIP */ + ) { + /* this connection must be aborted */ + struct tcp_pcb *next = pcb->next; + 8008f08: 68fb ldr r3, [r7, #12] + 8008f0a: 68db ldr r3, [r3, #12] + 8008f0c: 60bb str r3, [r7, #8] + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); + 8008f0e: 68f9 ldr r1, [r7, #12] + 8008f10: 480c ldr r0, [pc, #48] ; (8008f44 ) + 8008f12: f007 fe59 bl 8010bc8 + tcp_abort(pcb); + 8008f16: 68f8 ldr r0, [r7, #12] + 8008f18: f7fe fde4 bl 8007ae4 + pcb = next; + 8008f1c: 68bb ldr r3, [r7, #8] + 8008f1e: 60fb str r3, [r7, #12] + 8008f20: e002 b.n 8008f28 + } else { + pcb = pcb->next; + 8008f22: 68fb ldr r3, [r7, #12] + 8008f24: 68db ldr r3, [r3, #12] + 8008f26: 60fb str r3, [r7, #12] + while (pcb != NULL) { + 8008f28: 68fb ldr r3, [r7, #12] + 8008f2a: 2b00 cmp r3, #0 + 8008f2c: d1e6 bne.n 8008efc + } + } +} + 8008f2e: bf00 nop + 8008f30: bf00 nop + 8008f32: 3710 adds r7, #16 + 8008f34: 46bd mov sp, r7 + 8008f36: bd80 pop {r7, pc} + 8008f38: 08012a08 .word 0x08012a08 + 8008f3c: 0801313c .word 0x0801313c + 8008f40: 08012a4c .word 0x08012a4c + 8008f44: 08013170 .word 0x08013170 + +08008f48 : + * @param old_addr IP address of the netif before change + * @param new_addr IP address of the netif after change or NULL if netif has been removed + */ +void +tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + 8008f48: b580 push {r7, lr} + 8008f4a: b084 sub sp, #16 + 8008f4c: af00 add r7, sp, #0 + 8008f4e: 6078 str r0, [r7, #4] + 8008f50: 6039 str r1, [r7, #0] + struct tcp_pcb_listen *lpcb; + + if (!ip_addr_isany(old_addr)) { + 8008f52: 687b ldr r3, [r7, #4] + 8008f54: 2b00 cmp r3, #0 + 8008f56: d02a beq.n 8008fae + 8008f58: 687b ldr r3, [r7, #4] + 8008f5a: 681b ldr r3, [r3, #0] + 8008f5c: 2b00 cmp r3, #0 + 8008f5e: d026 beq.n 8008fae + tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs); + 8008f60: 4b15 ldr r3, [pc, #84] ; (8008fb8 ) + 8008f62: 681b ldr r3, [r3, #0] + 8008f64: 4619 mov r1, r3 + 8008f66: 6878 ldr r0, [r7, #4] + 8008f68: f7ff ffb6 bl 8008ed8 + tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs); + 8008f6c: 4b13 ldr r3, [pc, #76] ; (8008fbc ) + 8008f6e: 681b ldr r3, [r3, #0] + 8008f70: 4619 mov r1, r3 + 8008f72: 6878 ldr r0, [r7, #4] + 8008f74: f7ff ffb0 bl 8008ed8 + + if (!ip_addr_isany(new_addr)) { + 8008f78: 683b ldr r3, [r7, #0] + 8008f7a: 2b00 cmp r3, #0 + 8008f7c: d017 beq.n 8008fae + 8008f7e: 683b ldr r3, [r7, #0] + 8008f80: 681b ldr r3, [r3, #0] + 8008f82: 2b00 cmp r3, #0 + 8008f84: d013 beq.n 8008fae + /* PCB bound to current local interface address? */ + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 8008f86: 4b0e ldr r3, [pc, #56] ; (8008fc0 ) + 8008f88: 681b ldr r3, [r3, #0] + 8008f8a: 60fb str r3, [r7, #12] + 8008f8c: e00c b.n 8008fa8 + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&lpcb->local_ip, old_addr)) { + 8008f8e: 68fb ldr r3, [r7, #12] + 8008f90: 681a ldr r2, [r3, #0] + 8008f92: 687b ldr r3, [r7, #4] + 8008f94: 681b ldr r3, [r3, #0] + 8008f96: 429a cmp r2, r3 + 8008f98: d103 bne.n 8008fa2 + /* The PCB is listening to the old ipaddr and + * is set to listen to the new one instead */ + ip_addr_copy(lpcb->local_ip, *new_addr); + 8008f9a: 683b ldr r3, [r7, #0] + 8008f9c: 681a ldr r2, [r3, #0] + 8008f9e: 68fb ldr r3, [r7, #12] + 8008fa0: 601a str r2, [r3, #0] + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 8008fa2: 68fb ldr r3, [r7, #12] + 8008fa4: 68db ldr r3, [r3, #12] + 8008fa6: 60fb str r3, [r7, #12] + 8008fa8: 68fb ldr r3, [r7, #12] + 8008faa: 2b00 cmp r3, #0 + 8008fac: d1ef bne.n 8008f8e + } + } + } + } +} + 8008fae: bf00 nop + 8008fb0: 3710 adds r7, #16 + 8008fb2: 46bd mov sp, r7 + 8008fb4: bd80 pop {r7, pc} + 8008fb6: bf00 nop + 8008fb8: 24007b78 .word 0x24007b78 + 8008fbc: 24007b70 .word 0x24007b70 + 8008fc0: 24007b74 .word 0x24007b74 + +08008fc4 : + +#if TCP_QUEUE_OOSEQ +/* Free all ooseq pbufs (and possibly reset SACK state) */ +void +tcp_free_ooseq(struct tcp_pcb *pcb) +{ + 8008fc4: b580 push {r7, lr} + 8008fc6: b082 sub sp, #8 + 8008fc8: af00 add r7, sp, #0 + 8008fca: 6078 str r0, [r7, #4] + if (pcb->ooseq) { + 8008fcc: 687b ldr r3, [r7, #4] + 8008fce: 6f5b ldr r3, [r3, #116] ; 0x74 + 8008fd0: 2b00 cmp r3, #0 + 8008fd2: d007 beq.n 8008fe4 + tcp_segs_free(pcb->ooseq); + 8008fd4: 687b ldr r3, [r7, #4] + 8008fd6: 6f5b ldr r3, [r3, #116] ; 0x74 + 8008fd8: 4618 mov r0, r3 + 8008fda: f7ff fbb7 bl 800874c + pcb->ooseq = NULL; + 8008fde: 687b ldr r3, [r7, #4] + 8008fe0: 2200 movs r2, #0 + 8008fe2: 675a str r2, [r3, #116] ; 0x74 +#if LWIP_TCP_SACK_OUT + memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks)); +#endif /* LWIP_TCP_SACK_OUT */ + } +} + 8008fe4: bf00 nop + 8008fe6: 3708 adds r7, #8 + 8008fe8: 46bd mov sp, r7 + 8008fea: bd80 pop {r7, pc} + +08008fec : + * @param p received TCP segment to process (p->payload pointing to the TCP header) + * @param inp network interface on which this segment was received + */ +void +tcp_input(struct pbuf *p, struct netif *inp) +{ + 8008fec: b590 push {r4, r7, lr} + 8008fee: b08d sub sp, #52 ; 0x34 + 8008ff0: af04 add r7, sp, #16 + 8008ff2: 6078 str r0, [r7, #4] + 8008ff4: 6039 str r1, [r7, #0] + u8_t hdrlen_bytes; + err_t err; + + LWIP_UNUSED_ARG(inp); + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL); + 8008ff6: 687b ldr r3, [r7, #4] + 8008ff8: 2b00 cmp r3, #0 + 8008ffa: d105 bne.n 8009008 + 8008ffc: 4b9b ldr r3, [pc, #620] ; (800926c ) + 8008ffe: 2283 movs r2, #131 ; 0x83 + 8009000: 499b ldr r1, [pc, #620] ; (8009270 ) + 8009002: 489c ldr r0, [pc, #624] ; (8009274 ) + 8009004: f007 fde0 bl 8010bc8 + PERF_START; + + TCP_STATS_INC(tcp.recv); + MIB2_STATS_INC(mib2.tcpinsegs); + + tcphdr = (struct tcp_hdr *)p->payload; + 8009008: 687b ldr r3, [r7, #4] + 800900a: 685b ldr r3, [r3, #4] + 800900c: 4a9a ldr r2, [pc, #616] ; (8009278 ) + 800900e: 6013 str r3, [r2, #0] +#if TCP_INPUT_DEBUG + tcp_debug_print(tcphdr); +#endif + + /* Check that TCP header fits in payload */ + if (p->len < TCP_HLEN) { + 8009010: 687b ldr r3, [r7, #4] + 8009012: 895b ldrh r3, [r3, #10] + 8009014: 2b13 cmp r3, #19 + 8009016: f240 83d1 bls.w 80097bc + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + + /* Don't even process incoming broadcasts/multicasts. */ + if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || + 800901a: 4b98 ldr r3, [pc, #608] ; (800927c ) + 800901c: 695b ldr r3, [r3, #20] + 800901e: 4a97 ldr r2, [pc, #604] ; (800927c ) + 8009020: 6812 ldr r2, [r2, #0] + 8009022: 4611 mov r1, r2 + 8009024: 4618 mov r0, r3 + 8009026: f006 f9c5 bl 800f3b4 + 800902a: 4603 mov r3, r0 + 800902c: 2b00 cmp r3, #0 + 800902e: f040 83c7 bne.w 80097c0 + ip_addr_ismulticast(ip_current_dest_addr())) { + 8009032: 4b92 ldr r3, [pc, #584] ; (800927c ) + 8009034: 695b ldr r3, [r3, #20] + 8009036: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || + 800903a: 2be0 cmp r3, #224 ; 0xe0 + 800903c: f000 83c0 beq.w 80097c0 + } + } +#endif /* CHECKSUM_CHECK_TCP */ + + /* sanity-check header length */ + hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr); + 8009040: 4b8d ldr r3, [pc, #564] ; (8009278 ) + 8009042: 681b ldr r3, [r3, #0] + 8009044: 899b ldrh r3, [r3, #12] + 8009046: b29b uxth r3, r3 + 8009048: 4618 mov r0, r3 + 800904a: f7fc fa7f bl 800554c + 800904e: 4603 mov r3, r0 + 8009050: 0b1b lsrs r3, r3, #12 + 8009052: b29b uxth r3, r3 + 8009054: b2db uxtb r3, r3 + 8009056: 009b lsls r3, r3, #2 + 8009058: 74bb strb r3, [r7, #18] + if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) { + 800905a: 7cbb ldrb r3, [r7, #18] + 800905c: 2b13 cmp r3, #19 + 800905e: f240 83b1 bls.w 80097c4 + 8009062: 7cbb ldrb r3, [r7, #18] + 8009064: b29a uxth r2, r3 + 8009066: 687b ldr r3, [r7, #4] + 8009068: 891b ldrh r3, [r3, #8] + 800906a: 429a cmp r2, r3 + 800906c: f200 83aa bhi.w 80097c4 + goto dropped; + } + + /* Move the payload pointer in the pbuf so that it points to the + TCP data instead of the TCP header. */ + tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN); + 8009070: 7cbb ldrb r3, [r7, #18] + 8009072: b29b uxth r3, r3 + 8009074: 3b14 subs r3, #20 + 8009076: b29a uxth r2, r3 + 8009078: 4b81 ldr r3, [pc, #516] ; (8009280 ) + 800907a: 801a strh r2, [r3, #0] + tcphdr_opt2 = NULL; + 800907c: 4b81 ldr r3, [pc, #516] ; (8009284 ) + 800907e: 2200 movs r2, #0 + 8009080: 601a str r2, [r3, #0] + if (p->len >= hdrlen_bytes) { + 8009082: 687b ldr r3, [r7, #4] + 8009084: 895a ldrh r2, [r3, #10] + 8009086: 7cbb ldrb r3, [r7, #18] + 8009088: b29b uxth r3, r3 + 800908a: 429a cmp r2, r3 + 800908c: d309 bcc.n 80090a2 + /* all options are in the first pbuf */ + tcphdr_opt1len = tcphdr_optlen; + 800908e: 4b7c ldr r3, [pc, #496] ; (8009280 ) + 8009090: 881a ldrh r2, [r3, #0] + 8009092: 4b7d ldr r3, [pc, #500] ; (8009288 ) + 8009094: 801a strh r2, [r3, #0] + pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */ + 8009096: 7cbb ldrb r3, [r7, #18] + 8009098: 4619 mov r1, r3 + 800909a: 6878 ldr r0, [r7, #4] + 800909c: f7fd ff14 bl 8006ec8 + 80090a0: e04e b.n 8009140 + } else { + u16_t opt2len; + /* TCP header fits into first pbuf, options don't - data is in the next pbuf */ + /* there must be a next pbuf, due to hdrlen_bytes sanity check above */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + 80090a2: 687b ldr r3, [r7, #4] + 80090a4: 681b ldr r3, [r3, #0] + 80090a6: 2b00 cmp r3, #0 + 80090a8: d105 bne.n 80090b6 + 80090aa: 4b70 ldr r3, [pc, #448] ; (800926c ) + 80090ac: 22c2 movs r2, #194 ; 0xc2 + 80090ae: 4977 ldr r1, [pc, #476] ; (800928c ) + 80090b0: 4870 ldr r0, [pc, #448] ; (8009274 ) + 80090b2: f007 fd89 bl 8010bc8 + + /* advance over the TCP header (cannot fail) */ + pbuf_remove_header(p, TCP_HLEN); + 80090b6: 2114 movs r1, #20 + 80090b8: 6878 ldr r0, [r7, #4] + 80090ba: f7fd ff05 bl 8006ec8 + + /* determine how long the first and second parts of the options are */ + tcphdr_opt1len = p->len; + 80090be: 687b ldr r3, [r7, #4] + 80090c0: 895a ldrh r2, [r3, #10] + 80090c2: 4b71 ldr r3, [pc, #452] ; (8009288 ) + 80090c4: 801a strh r2, [r3, #0] + opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len); + 80090c6: 4b6e ldr r3, [pc, #440] ; (8009280 ) + 80090c8: 881a ldrh r2, [r3, #0] + 80090ca: 4b6f ldr r3, [pc, #444] ; (8009288 ) + 80090cc: 881b ldrh r3, [r3, #0] + 80090ce: 1ad3 subs r3, r2, r3 + 80090d0: 823b strh r3, [r7, #16] + + /* options continue in the next pbuf: set p to zero length and hide the + options in the next pbuf (adjusting p->tot_len) */ + pbuf_remove_header(p, tcphdr_opt1len); + 80090d2: 4b6d ldr r3, [pc, #436] ; (8009288 ) + 80090d4: 881b ldrh r3, [r3, #0] + 80090d6: 4619 mov r1, r3 + 80090d8: 6878 ldr r0, [r7, #4] + 80090da: f7fd fef5 bl 8006ec8 + + /* check that the options fit in the second pbuf */ + if (opt2len > p->next->len) { + 80090de: 687b ldr r3, [r7, #4] + 80090e0: 681b ldr r3, [r3, #0] + 80090e2: 895b ldrh r3, [r3, #10] + 80090e4: 8a3a ldrh r2, [r7, #16] + 80090e6: 429a cmp r2, r3 + 80090e8: f200 836e bhi.w 80097c8 + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + + /* remember the pointer to the second part of the options */ + tcphdr_opt2 = (u8_t *)p->next->payload; + 80090ec: 687b ldr r3, [r7, #4] + 80090ee: 681b ldr r3, [r3, #0] + 80090f0: 685b ldr r3, [r3, #4] + 80090f2: 4a64 ldr r2, [pc, #400] ; (8009284 ) + 80090f4: 6013 str r3, [r2, #0] + + /* advance p->next to point after the options, and manually + adjust p->tot_len to keep it consistent with the changed p->next */ + pbuf_remove_header(p->next, opt2len); + 80090f6: 687b ldr r3, [r7, #4] + 80090f8: 681b ldr r3, [r3, #0] + 80090fa: 8a3a ldrh r2, [r7, #16] + 80090fc: 4611 mov r1, r2 + 80090fe: 4618 mov r0, r3 + 8009100: f7fd fee2 bl 8006ec8 + p->tot_len = (u16_t)(p->tot_len - opt2len); + 8009104: 687b ldr r3, [r7, #4] + 8009106: 891a ldrh r2, [r3, #8] + 8009108: 8a3b ldrh r3, [r7, #16] + 800910a: 1ad3 subs r3, r2, r3 + 800910c: b29a uxth r2, r3 + 800910e: 687b ldr r3, [r7, #4] + 8009110: 811a strh r2, [r3, #8] + + LWIP_ASSERT("p->len == 0", p->len == 0); + 8009112: 687b ldr r3, [r7, #4] + 8009114: 895b ldrh r3, [r3, #10] + 8009116: 2b00 cmp r3, #0 + 8009118: d005 beq.n 8009126 + 800911a: 4b54 ldr r3, [pc, #336] ; (800926c ) + 800911c: 22df movs r2, #223 ; 0xdf + 800911e: 495c ldr r1, [pc, #368] ; (8009290 ) + 8009120: 4854 ldr r0, [pc, #336] ; (8009274 ) + 8009122: f007 fd51 bl 8010bc8 + LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len); + 8009126: 687b ldr r3, [r7, #4] + 8009128: 891a ldrh r2, [r3, #8] + 800912a: 687b ldr r3, [r7, #4] + 800912c: 681b ldr r3, [r3, #0] + 800912e: 891b ldrh r3, [r3, #8] + 8009130: 429a cmp r2, r3 + 8009132: d005 beq.n 8009140 + 8009134: 4b4d ldr r3, [pc, #308] ; (800926c ) + 8009136: 22e0 movs r2, #224 ; 0xe0 + 8009138: 4956 ldr r1, [pc, #344] ; (8009294 ) + 800913a: 484e ldr r0, [pc, #312] ; (8009274 ) + 800913c: f007 fd44 bl 8010bc8 + } + + /* Convert fields in TCP header to host byte order. */ + tcphdr->src = lwip_ntohs(tcphdr->src); + 8009140: 4b4d ldr r3, [pc, #308] ; (8009278 ) + 8009142: 681b ldr r3, [r3, #0] + 8009144: 881b ldrh r3, [r3, #0] + 8009146: b29b uxth r3, r3 + 8009148: 4a4b ldr r2, [pc, #300] ; (8009278 ) + 800914a: 6814 ldr r4, [r2, #0] + 800914c: 4618 mov r0, r3 + 800914e: f7fc f9fd bl 800554c + 8009152: 4603 mov r3, r0 + 8009154: 8023 strh r3, [r4, #0] + tcphdr->dest = lwip_ntohs(tcphdr->dest); + 8009156: 4b48 ldr r3, [pc, #288] ; (8009278 ) + 8009158: 681b ldr r3, [r3, #0] + 800915a: 885b ldrh r3, [r3, #2] + 800915c: b29b uxth r3, r3 + 800915e: 4a46 ldr r2, [pc, #280] ; (8009278 ) + 8009160: 6814 ldr r4, [r2, #0] + 8009162: 4618 mov r0, r3 + 8009164: f7fc f9f2 bl 800554c + 8009168: 4603 mov r3, r0 + 800916a: 8063 strh r3, [r4, #2] + seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno); + 800916c: 4b42 ldr r3, [pc, #264] ; (8009278 ) + 800916e: 681b ldr r3, [r3, #0] + 8009170: 685b ldr r3, [r3, #4] + 8009172: 4a41 ldr r2, [pc, #260] ; (8009278 ) + 8009174: 6814 ldr r4, [r2, #0] + 8009176: 4618 mov r0, r3 + 8009178: f7fc f9fd bl 8005576 + 800917c: 4603 mov r3, r0 + 800917e: 6063 str r3, [r4, #4] + 8009180: 6863 ldr r3, [r4, #4] + 8009182: 4a45 ldr r2, [pc, #276] ; (8009298 ) + 8009184: 6013 str r3, [r2, #0] + ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno); + 8009186: 4b3c ldr r3, [pc, #240] ; (8009278 ) + 8009188: 681b ldr r3, [r3, #0] + 800918a: 689b ldr r3, [r3, #8] + 800918c: 4a3a ldr r2, [pc, #232] ; (8009278 ) + 800918e: 6814 ldr r4, [r2, #0] + 8009190: 4618 mov r0, r3 + 8009192: f7fc f9f0 bl 8005576 + 8009196: 4603 mov r3, r0 + 8009198: 60a3 str r3, [r4, #8] + 800919a: 68a3 ldr r3, [r4, #8] + 800919c: 4a3f ldr r2, [pc, #252] ; (800929c ) + 800919e: 6013 str r3, [r2, #0] + tcphdr->wnd = lwip_ntohs(tcphdr->wnd); + 80091a0: 4b35 ldr r3, [pc, #212] ; (8009278 ) + 80091a2: 681b ldr r3, [r3, #0] + 80091a4: 89db ldrh r3, [r3, #14] + 80091a6: b29b uxth r3, r3 + 80091a8: 4a33 ldr r2, [pc, #204] ; (8009278 ) + 80091aa: 6814 ldr r4, [r2, #0] + 80091ac: 4618 mov r0, r3 + 80091ae: f7fc f9cd bl 800554c + 80091b2: 4603 mov r3, r0 + 80091b4: 81e3 strh r3, [r4, #14] + + flags = TCPH_FLAGS(tcphdr); + 80091b6: 4b30 ldr r3, [pc, #192] ; (8009278 ) + 80091b8: 681b ldr r3, [r3, #0] + 80091ba: 899b ldrh r3, [r3, #12] + 80091bc: b29b uxth r3, r3 + 80091be: 4618 mov r0, r3 + 80091c0: f7fc f9c4 bl 800554c + 80091c4: 4603 mov r3, r0 + 80091c6: b2db uxtb r3, r3 + 80091c8: f003 033f and.w r3, r3, #63 ; 0x3f + 80091cc: b2da uxtb r2, r3 + 80091ce: 4b34 ldr r3, [pc, #208] ; (80092a0 ) + 80091d0: 701a strb r2, [r3, #0] + tcplen = p->tot_len; + 80091d2: 687b ldr r3, [r7, #4] + 80091d4: 891a ldrh r2, [r3, #8] + 80091d6: 4b33 ldr r3, [pc, #204] ; (80092a4 ) + 80091d8: 801a strh r2, [r3, #0] + if (flags & (TCP_FIN | TCP_SYN)) { + 80091da: 4b31 ldr r3, [pc, #196] ; (80092a0 ) + 80091dc: 781b ldrb r3, [r3, #0] + 80091de: f003 0303 and.w r3, r3, #3 + 80091e2: 2b00 cmp r3, #0 + 80091e4: d00c beq.n 8009200 + tcplen++; + 80091e6: 4b2f ldr r3, [pc, #188] ; (80092a4 ) + 80091e8: 881b ldrh r3, [r3, #0] + 80091ea: 3301 adds r3, #1 + 80091ec: b29a uxth r2, r3 + 80091ee: 4b2d ldr r3, [pc, #180] ; (80092a4 ) + 80091f0: 801a strh r2, [r3, #0] + if (tcplen < p->tot_len) { + 80091f2: 687b ldr r3, [r7, #4] + 80091f4: 891a ldrh r2, [r3, #8] + 80091f6: 4b2b ldr r3, [pc, #172] ; (80092a4 ) + 80091f8: 881b ldrh r3, [r3, #0] + 80091fa: 429a cmp r2, r3 + 80091fc: f200 82e6 bhi.w 80097cc + } + } + + /* Demultiplex an incoming segment. First, we check if it is destined + for an active connection. */ + prev = NULL; + 8009200: 2300 movs r3, #0 + 8009202: 61fb str r3, [r7, #28] + + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 8009204: 4b28 ldr r3, [pc, #160] ; (80092a8 ) + 8009206: 681b ldr r3, [r3, #0] + 8009208: 61bb str r3, [r7, #24] + 800920a: e09d b.n 8009348 + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + 800920c: 69bb ldr r3, [r7, #24] + 800920e: 7d1b ldrb r3, [r3, #20] + 8009210: 2b00 cmp r3, #0 + 8009212: d105 bne.n 8009220 + 8009214: 4b15 ldr r3, [pc, #84] ; (800926c ) + 8009216: 22fb movs r2, #251 ; 0xfb + 8009218: 4924 ldr r1, [pc, #144] ; (80092ac ) + 800921a: 4816 ldr r0, [pc, #88] ; (8009274 ) + 800921c: f007 fcd4 bl 8010bc8 + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + 8009220: 69bb ldr r3, [r7, #24] + 8009222: 7d1b ldrb r3, [r3, #20] + 8009224: 2b0a cmp r3, #10 + 8009226: d105 bne.n 8009234 + 8009228: 4b10 ldr r3, [pc, #64] ; (800926c ) + 800922a: 22fc movs r2, #252 ; 0xfc + 800922c: 4920 ldr r1, [pc, #128] ; (80092b0 ) + 800922e: 4811 ldr r0, [pc, #68] ; (8009274 ) + 8009230: f007 fcca bl 8010bc8 + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); + 8009234: 69bb ldr r3, [r7, #24] + 8009236: 7d1b ldrb r3, [r3, #20] + 8009238: 2b01 cmp r3, #1 + 800923a: d105 bne.n 8009248 + 800923c: 4b0b ldr r3, [pc, #44] ; (800926c ) + 800923e: 22fd movs r2, #253 ; 0xfd + 8009240: 491c ldr r1, [pc, #112] ; (80092b4 ) + 8009242: 480c ldr r0, [pc, #48] ; (8009274 ) + 8009244: f007 fcc0 bl 8010bc8 + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 8009248: 69bb ldr r3, [r7, #24] + 800924a: 7a1b ldrb r3, [r3, #8] + 800924c: 2b00 cmp r3, #0 + 800924e: d033 beq.n 80092b8 + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 8009250: 69bb ldr r3, [r7, #24] + 8009252: 7a1a ldrb r2, [r3, #8] + 8009254: 4b09 ldr r3, [pc, #36] ; (800927c ) + 8009256: 685b ldr r3, [r3, #4] + 8009258: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 800925c: 3301 adds r3, #1 + 800925e: b2db uxtb r3, r3 + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 8009260: 429a cmp r2, r3 + 8009262: d029 beq.n 80092b8 + prev = pcb; + 8009264: 69bb ldr r3, [r7, #24] + 8009266: 61fb str r3, [r7, #28] + continue; + 8009268: e06b b.n 8009342 + 800926a: bf00 nop + 800926c: 08013198 .word 0x08013198 + 8009270: 080131cc .word 0x080131cc + 8009274: 080131e4 .word 0x080131e4 + 8009278: 24007b98 .word 0x24007b98 + 800927c: 24004c10 .word 0x24004c10 + 8009280: 24007b9c .word 0x24007b9c + 8009284: 24007ba0 .word 0x24007ba0 + 8009288: 24007b9e .word 0x24007b9e + 800928c: 0801320c .word 0x0801320c + 8009290: 0801321c .word 0x0801321c + 8009294: 08013228 .word 0x08013228 + 8009298: 24007ba8 .word 0x24007ba8 + 800929c: 24007bac .word 0x24007bac + 80092a0: 24007bb4 .word 0x24007bb4 + 80092a4: 24007bb2 .word 0x24007bb2 + 80092a8: 24007b78 .word 0x24007b78 + 80092ac: 08013248 .word 0x08013248 + 80092b0: 08013270 .word 0x08013270 + 80092b4: 0801329c .word 0x0801329c + } + + if (pcb->remote_port == tcphdr->src && + 80092b8: 69bb ldr r3, [r7, #24] + 80092ba: 8b1a ldrh r2, [r3, #24] + 80092bc: 4b72 ldr r3, [pc, #456] ; (8009488 ) + 80092be: 681b ldr r3, [r3, #0] + 80092c0: 881b ldrh r3, [r3, #0] + 80092c2: b29b uxth r3, r3 + 80092c4: 429a cmp r2, r3 + 80092c6: d13a bne.n 800933e + pcb->local_port == tcphdr->dest && + 80092c8: 69bb ldr r3, [r7, #24] + 80092ca: 8ada ldrh r2, [r3, #22] + 80092cc: 4b6e ldr r3, [pc, #440] ; (8009488 ) + 80092ce: 681b ldr r3, [r3, #0] + 80092d0: 885b ldrh r3, [r3, #2] + 80092d2: b29b uxth r3, r3 + if (pcb->remote_port == tcphdr->src && + 80092d4: 429a cmp r2, r3 + 80092d6: d132 bne.n 800933e + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 80092d8: 69bb ldr r3, [r7, #24] + 80092da: 685a ldr r2, [r3, #4] + 80092dc: 4b6b ldr r3, [pc, #428] ; (800948c ) + 80092de: 691b ldr r3, [r3, #16] + pcb->local_port == tcphdr->dest && + 80092e0: 429a cmp r2, r3 + 80092e2: d12c bne.n 800933e + ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + 80092e4: 69bb ldr r3, [r7, #24] + 80092e6: 681a ldr r2, [r3, #0] + 80092e8: 4b68 ldr r3, [pc, #416] ; (800948c ) + 80092ea: 695b ldr r3, [r3, #20] + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 80092ec: 429a cmp r2, r3 + 80092ee: d126 bne.n 800933e + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); + 80092f0: 69bb ldr r3, [r7, #24] + 80092f2: 68db ldr r3, [r3, #12] + 80092f4: 69ba ldr r2, [r7, #24] + 80092f6: 429a cmp r2, r3 + 80092f8: d106 bne.n 8009308 + 80092fa: 4b65 ldr r3, [pc, #404] ; (8009490 ) + 80092fc: f240 120d movw r2, #269 ; 0x10d + 8009300: 4964 ldr r1, [pc, #400] ; (8009494 ) + 8009302: 4865 ldr r0, [pc, #404] ; (8009498 ) + 8009304: f007 fc60 bl 8010bc8 + if (prev != NULL) { + 8009308: 69fb ldr r3, [r7, #28] + 800930a: 2b00 cmp r3, #0 + 800930c: d00a beq.n 8009324 + prev->next = pcb->next; + 800930e: 69bb ldr r3, [r7, #24] + 8009310: 68da ldr r2, [r3, #12] + 8009312: 69fb ldr r3, [r7, #28] + 8009314: 60da str r2, [r3, #12] + pcb->next = tcp_active_pcbs; + 8009316: 4b61 ldr r3, [pc, #388] ; (800949c ) + 8009318: 681a ldr r2, [r3, #0] + 800931a: 69bb ldr r3, [r7, #24] + 800931c: 60da str r2, [r3, #12] + tcp_active_pcbs = pcb; + 800931e: 4a5f ldr r2, [pc, #380] ; (800949c ) + 8009320: 69bb ldr r3, [r7, #24] + 8009322: 6013 str r3, [r2, #0] + } else { + TCP_STATS_INC(tcp.cachehit); + } + LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); + 8009324: 69bb ldr r3, [r7, #24] + 8009326: 68db ldr r3, [r3, #12] + 8009328: 69ba ldr r2, [r7, #24] + 800932a: 429a cmp r2, r3 + 800932c: d111 bne.n 8009352 + 800932e: 4b58 ldr r3, [pc, #352] ; (8009490 ) + 8009330: f240 1215 movw r2, #277 ; 0x115 + 8009334: 495a ldr r1, [pc, #360] ; (80094a0 ) + 8009336: 4858 ldr r0, [pc, #352] ; (8009498 ) + 8009338: f007 fc46 bl 8010bc8 + break; + 800933c: e009 b.n 8009352 + } + prev = pcb; + 800933e: 69bb ldr r3, [r7, #24] + 8009340: 61fb str r3, [r7, #28] + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + 8009342: 69bb ldr r3, [r7, #24] + 8009344: 68db ldr r3, [r3, #12] + 8009346: 61bb str r3, [r7, #24] + 8009348: 69bb ldr r3, [r7, #24] + 800934a: 2b00 cmp r3, #0 + 800934c: f47f af5e bne.w 800920c + 8009350: e000 b.n 8009354 + break; + 8009352: bf00 nop + } + + if (pcb == NULL) { + 8009354: 69bb ldr r3, [r7, #24] + 8009356: 2b00 cmp r3, #0 + 8009358: f040 80aa bne.w 80094b0 + /* If it did not go to an active connection, we check the connections + in the TIME-WAIT state. */ + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 800935c: 4b51 ldr r3, [pc, #324] ; (80094a4 ) + 800935e: 681b ldr r3, [r3, #0] + 8009360: 61bb str r3, [r7, #24] + 8009362: e03f b.n 80093e4 + LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + 8009364: 69bb ldr r3, [r7, #24] + 8009366: 7d1b ldrb r3, [r3, #20] + 8009368: 2b0a cmp r3, #10 + 800936a: d006 beq.n 800937a + 800936c: 4b48 ldr r3, [pc, #288] ; (8009490 ) + 800936e: f240 121f movw r2, #287 ; 0x11f + 8009372: 494d ldr r1, [pc, #308] ; (80094a8 ) + 8009374: 4848 ldr r0, [pc, #288] ; (8009498 ) + 8009376: f007 fc27 bl 8010bc8 + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 800937a: 69bb ldr r3, [r7, #24] + 800937c: 7a1b ldrb r3, [r3, #8] + 800937e: 2b00 cmp r3, #0 + 8009380: d009 beq.n 8009396 + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 8009382: 69bb ldr r3, [r7, #24] + 8009384: 7a1a ldrb r2, [r3, #8] + 8009386: 4b41 ldr r3, [pc, #260] ; (800948c ) + 8009388: 685b ldr r3, [r3, #4] + 800938a: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 800938e: 3301 adds r3, #1 + 8009390: b2db uxtb r3, r3 + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 8009392: 429a cmp r2, r3 + 8009394: d122 bne.n 80093dc + continue; + } + + if (pcb->remote_port == tcphdr->src && + 8009396: 69bb ldr r3, [r7, #24] + 8009398: 8b1a ldrh r2, [r3, #24] + 800939a: 4b3b ldr r3, [pc, #236] ; (8009488 ) + 800939c: 681b ldr r3, [r3, #0] + 800939e: 881b ldrh r3, [r3, #0] + 80093a0: b29b uxth r3, r3 + 80093a2: 429a cmp r2, r3 + 80093a4: d11b bne.n 80093de + pcb->local_port == tcphdr->dest && + 80093a6: 69bb ldr r3, [r7, #24] + 80093a8: 8ada ldrh r2, [r3, #22] + 80093aa: 4b37 ldr r3, [pc, #220] ; (8009488 ) + 80093ac: 681b ldr r3, [r3, #0] + 80093ae: 885b ldrh r3, [r3, #2] + 80093b0: b29b uxth r3, r3 + if (pcb->remote_port == tcphdr->src && + 80093b2: 429a cmp r2, r3 + 80093b4: d113 bne.n 80093de + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 80093b6: 69bb ldr r3, [r7, #24] + 80093b8: 685a ldr r2, [r3, #4] + 80093ba: 4b34 ldr r3, [pc, #208] ; (800948c ) + 80093bc: 691b ldr r3, [r3, #16] + pcb->local_port == tcphdr->dest && + 80093be: 429a cmp r2, r3 + 80093c0: d10d bne.n 80093de + ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + 80093c2: 69bb ldr r3, [r7, #24] + 80093c4: 681a ldr r2, [r3, #0] + 80093c6: 4b31 ldr r3, [pc, #196] ; (800948c ) + 80093c8: 695b ldr r3, [r3, #20] + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + 80093ca: 429a cmp r2, r3 + 80093cc: d107 bne.n 80093de +#ifdef LWIP_HOOK_TCP_INPACKET_PCB + if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len, + tcphdr_opt2, p) == ERR_OK) +#endif + { + tcp_timewait_input(pcb); + 80093ce: 69b8 ldr r0, [r7, #24] + 80093d0: f000 fb56 bl 8009a80 + } + pbuf_free(p); + 80093d4: 6878 ldr r0, [r7, #4] + 80093d6: f7fd fdfd bl 8006fd4 + return; + 80093da: e1fd b.n 80097d8 + continue; + 80093dc: bf00 nop + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + 80093de: 69bb ldr r3, [r7, #24] + 80093e0: 68db ldr r3, [r3, #12] + 80093e2: 61bb str r3, [r7, #24] + 80093e4: 69bb ldr r3, [r7, #24] + 80093e6: 2b00 cmp r3, #0 + 80093e8: d1bc bne.n 8009364 + } + } + + /* Finally, if we still did not get a match, we check all PCBs that + are LISTENing for incoming connections. */ + prev = NULL; + 80093ea: 2300 movs r3, #0 + 80093ec: 61fb str r3, [r7, #28] + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 80093ee: 4b2f ldr r3, [pc, #188] ; (80094ac ) + 80093f0: 681b ldr r3, [r3, #0] + 80093f2: 617b str r3, [r7, #20] + 80093f4: e02a b.n 800944c + /* check if PCB is bound to specific netif */ + if ((lpcb->netif_idx != NETIF_NO_INDEX) && + 80093f6: 697b ldr r3, [r7, #20] + 80093f8: 7a1b ldrb r3, [r3, #8] + 80093fa: 2b00 cmp r3, #0 + 80093fc: d00c beq.n 8009418 + (lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 80093fe: 697b ldr r3, [r7, #20] + 8009400: 7a1a ldrb r2, [r3, #8] + 8009402: 4b22 ldr r3, [pc, #136] ; (800948c ) + 8009404: 685b ldr r3, [r3, #4] + 8009406: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 800940a: 3301 adds r3, #1 + 800940c: b2db uxtb r3, r3 + if ((lpcb->netif_idx != NETIF_NO_INDEX) && + 800940e: 429a cmp r2, r3 + 8009410: d002 beq.n 8009418 + prev = (struct tcp_pcb *)lpcb; + 8009412: 697b ldr r3, [r7, #20] + 8009414: 61fb str r3, [r7, #28] + continue; + 8009416: e016 b.n 8009446 + } + + if (lpcb->local_port == tcphdr->dest) { + 8009418: 697b ldr r3, [r7, #20] + 800941a: 8ada ldrh r2, [r3, #22] + 800941c: 4b1a ldr r3, [pc, #104] ; (8009488 ) + 800941e: 681b ldr r3, [r3, #0] + 8009420: 885b ldrh r3, [r3, #2] + 8009422: b29b uxth r3, r3 + 8009424: 429a cmp r2, r3 + 8009426: d10c bne.n 8009442 + lpcb_prev = prev; +#else /* SO_REUSE */ + break; +#endif /* SO_REUSE */ + } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) { + if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) { + 8009428: 697b ldr r3, [r7, #20] + 800942a: 681a ldr r2, [r3, #0] + 800942c: 4b17 ldr r3, [pc, #92] ; (800948c ) + 800942e: 695b ldr r3, [r3, #20] + 8009430: 429a cmp r2, r3 + 8009432: d00f beq.n 8009454 + /* found an exact match */ + break; + } else if (ip_addr_isany(&lpcb->local_ip)) { + 8009434: 697b ldr r3, [r7, #20] + 8009436: 2b00 cmp r3, #0 + 8009438: d00d beq.n 8009456 + 800943a: 697b ldr r3, [r7, #20] + 800943c: 681b ldr r3, [r3, #0] + 800943e: 2b00 cmp r3, #0 + 8009440: d009 beq.n 8009456 + break; +#endif /* SO_REUSE */ + } + } + } + prev = (struct tcp_pcb *)lpcb; + 8009442: 697b ldr r3, [r7, #20] + 8009444: 61fb str r3, [r7, #28] + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + 8009446: 697b ldr r3, [r7, #20] + 8009448: 68db ldr r3, [r3, #12] + 800944a: 617b str r3, [r7, #20] + 800944c: 697b ldr r3, [r7, #20] + 800944e: 2b00 cmp r3, #0 + 8009450: d1d1 bne.n 80093f6 + 8009452: e000 b.n 8009456 + break; + 8009454: bf00 nop + /* only pass to ANY if no specific local IP has been found */ + lpcb = lpcb_any; + prev = lpcb_prev; + } +#endif /* SO_REUSE */ + if (lpcb != NULL) { + 8009456: 697b ldr r3, [r7, #20] + 8009458: 2b00 cmp r3, #0 + 800945a: d029 beq.n 80094b0 + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + if (prev != NULL) { + 800945c: 69fb ldr r3, [r7, #28] + 800945e: 2b00 cmp r3, #0 + 8009460: d00a beq.n 8009478 + ((struct tcp_pcb_listen *)prev)->next = lpcb->next; + 8009462: 697b ldr r3, [r7, #20] + 8009464: 68da ldr r2, [r3, #12] + 8009466: 69fb ldr r3, [r7, #28] + 8009468: 60da str r2, [r3, #12] + /* our successor is the remainder of the listening list */ + lpcb->next = tcp_listen_pcbs.listen_pcbs; + 800946a: 4b10 ldr r3, [pc, #64] ; (80094ac ) + 800946c: 681a ldr r2, [r3, #0] + 800946e: 697b ldr r3, [r7, #20] + 8009470: 60da str r2, [r3, #12] + /* put this listening pcb at the head of the listening list */ + tcp_listen_pcbs.listen_pcbs = lpcb; + 8009472: 4a0e ldr r2, [pc, #56] ; (80094ac ) + 8009474: 697b ldr r3, [r7, #20] + 8009476: 6013 str r3, [r2, #0] +#ifdef LWIP_HOOK_TCP_INPACKET_PCB + if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen, + tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK) +#endif + { + tcp_listen_input(lpcb); + 8009478: 6978 ldr r0, [r7, #20] + 800947a: f000 fa03 bl 8009884 + } + pbuf_free(p); + 800947e: 6878 ldr r0, [r7, #4] + 8009480: f7fd fda8 bl 8006fd4 + return; + 8009484: e1a8 b.n 80097d8 + 8009486: bf00 nop + 8009488: 24007b98 .word 0x24007b98 + 800948c: 24004c10 .word 0x24004c10 + 8009490: 08013198 .word 0x08013198 + 8009494: 080132c4 .word 0x080132c4 + 8009498: 080131e4 .word 0x080131e4 + 800949c: 24007b78 .word 0x24007b78 + 80094a0: 080132f0 .word 0x080132f0 + 80094a4: 24007b7c .word 0x24007b7c + 80094a8: 0801331c .word 0x0801331c + 80094ac: 24007b74 .word 0x24007b74 + tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) { + pbuf_free(p); + return; + } +#endif + if (pcb != NULL) { + 80094b0: 69bb ldr r3, [r7, #24] + 80094b2: 2b00 cmp r3, #0 + 80094b4: f000 8158 beq.w 8009768 +#if TCP_INPUT_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_INPUT_DEBUG */ + + /* Set up a tcp_seg structure. */ + inseg.next = NULL; + 80094b8: 4b95 ldr r3, [pc, #596] ; (8009710 ) + 80094ba: 2200 movs r2, #0 + 80094bc: 601a str r2, [r3, #0] + inseg.len = p->tot_len; + 80094be: 687b ldr r3, [r7, #4] + 80094c0: 891a ldrh r2, [r3, #8] + 80094c2: 4b93 ldr r3, [pc, #588] ; (8009710 ) + 80094c4: 811a strh r2, [r3, #8] + inseg.p = p; + 80094c6: 4a92 ldr r2, [pc, #584] ; (8009710 ) + 80094c8: 687b ldr r3, [r7, #4] + 80094ca: 6053 str r3, [r2, #4] + inseg.tcphdr = tcphdr; + 80094cc: 4b91 ldr r3, [pc, #580] ; (8009714 ) + 80094ce: 681b ldr r3, [r3, #0] + 80094d0: 4a8f ldr r2, [pc, #572] ; (8009710 ) + 80094d2: 6113 str r3, [r2, #16] + + recv_data = NULL; + 80094d4: 4b90 ldr r3, [pc, #576] ; (8009718 ) + 80094d6: 2200 movs r2, #0 + 80094d8: 601a str r2, [r3, #0] + recv_flags = 0; + 80094da: 4b90 ldr r3, [pc, #576] ; (800971c ) + 80094dc: 2200 movs r2, #0 + 80094de: 701a strb r2, [r3, #0] + recv_acked = 0; + 80094e0: 4b8f ldr r3, [pc, #572] ; (8009720 ) + 80094e2: 2200 movs r2, #0 + 80094e4: 801a strh r2, [r3, #0] + + if (flags & TCP_PSH) { + 80094e6: 4b8f ldr r3, [pc, #572] ; (8009724 ) + 80094e8: 781b ldrb r3, [r3, #0] + 80094ea: f003 0308 and.w r3, r3, #8 + 80094ee: 2b00 cmp r3, #0 + 80094f0: d006 beq.n 8009500 + p->flags |= PBUF_FLAG_PUSH; + 80094f2: 687b ldr r3, [r7, #4] + 80094f4: 7b5b ldrb r3, [r3, #13] + 80094f6: f043 0301 orr.w r3, r3, #1 + 80094fa: b2da uxtb r2, r3 + 80094fc: 687b ldr r3, [r7, #4] + 80094fe: 735a strb r2, [r3, #13] + } + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + 8009500: 69bb ldr r3, [r7, #24] + 8009502: 6f9b ldr r3, [r3, #120] ; 0x78 + 8009504: 2b00 cmp r3, #0 + 8009506: d017 beq.n 8009538 + if ((tcp_process_refused_data(pcb) == ERR_ABRT) || + 8009508: 69b8 ldr r0, [r7, #24] + 800950a: f7ff f8a3 bl 8008654 + 800950e: 4603 mov r3, r0 + 8009510: f113 0f0d cmn.w r3, #13 + 8009514: d007 beq.n 8009526 + ((pcb->refused_data != NULL) && (tcplen > 0))) { + 8009516: 69bb ldr r3, [r7, #24] + 8009518: 6f9b ldr r3, [r3, #120] ; 0x78 + if ((tcp_process_refused_data(pcb) == ERR_ABRT) || + 800951a: 2b00 cmp r3, #0 + 800951c: d00c beq.n 8009538 + ((pcb->refused_data != NULL) && (tcplen > 0))) { + 800951e: 4b82 ldr r3, [pc, #520] ; (8009728 ) + 8009520: 881b ldrh r3, [r3, #0] + 8009522: 2b00 cmp r3, #0 + 8009524: d008 beq.n 8009538 + /* pcb has been aborted or refused data is still refused and the new + segment contains data */ + if (pcb->rcv_ann_wnd == 0) { + 8009526: 69bb ldr r3, [r7, #24] + 8009528: 8d5b ldrh r3, [r3, #42] ; 0x2a + 800952a: 2b00 cmp r3, #0 + 800952c: f040 80e3 bne.w 80096f6 + /* this is a zero-window probe, we respond to it with current RCV.NXT + and drop the data segment */ + tcp_send_empty_ack(pcb); + 8009530: 69b8 ldr r0, [r7, #24] + 8009532: f003 fe71 bl 800d218 + } + TCP_STATS_INC(tcp.drop); + MIB2_STATS_INC(mib2.tcpinerrs); + goto aborted; + 8009536: e0de b.n 80096f6 + } + } + tcp_input_pcb = pcb; + 8009538: 4a7c ldr r2, [pc, #496] ; (800972c ) + 800953a: 69bb ldr r3, [r7, #24] + 800953c: 6013 str r3, [r2, #0] + err = tcp_process(pcb); + 800953e: 69b8 ldr r0, [r7, #24] + 8009540: f000 fb18 bl 8009b74 + 8009544: 4603 mov r3, r0 + 8009546: 74fb strb r3, [r7, #19] + /* A return value of ERR_ABRT means that tcp_abort() was called + and that the pcb has been freed. If so, we don't do anything. */ + if (err != ERR_ABRT) { + 8009548: f997 3013 ldrsb.w r3, [r7, #19] + 800954c: f113 0f0d cmn.w r3, #13 + 8009550: f000 80d3 beq.w 80096fa + if (recv_flags & TF_RESET) { + 8009554: 4b71 ldr r3, [pc, #452] ; (800971c ) + 8009556: 781b ldrb r3, [r3, #0] + 8009558: f003 0308 and.w r3, r3, #8 + 800955c: 2b00 cmp r3, #0 + 800955e: d015 beq.n 800958c + /* TF_RESET means that the connection was reset by the other + end. We then call the error callback to inform the + application that the connection is dead before we + deallocate the PCB. */ + TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST); + 8009560: 69bb ldr r3, [r7, #24] + 8009562: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009566: 2b00 cmp r3, #0 + 8009568: d008 beq.n 800957c + 800956a: 69bb ldr r3, [r7, #24] + 800956c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009570: 69ba ldr r2, [r7, #24] + 8009572: 6912 ldr r2, [r2, #16] + 8009574: f06f 010d mvn.w r1, #13 + 8009578: 4610 mov r0, r2 + 800957a: 4798 blx r3 + tcp_pcb_remove(&tcp_active_pcbs, pcb); + 800957c: 69b9 ldr r1, [r7, #24] + 800957e: 486c ldr r0, [pc, #432] ; (8009730 ) + 8009580: f7ff fbb6 bl 8008cf0 + tcp_free(pcb); + 8009584: 69b8 ldr r0, [r7, #24] + 8009586: f7fd ffc5 bl 8007514 + 800958a: e0da b.n 8009742 + } else { + err = ERR_OK; + 800958c: 2300 movs r3, #0 + 800958e: 74fb strb r3, [r7, #19] + /* If the application has registered a "sent" function to be + called when new send buffer space is available, we call it + now. */ + if (recv_acked > 0) { + 8009590: 4b63 ldr r3, [pc, #396] ; (8009720 ) + 8009592: 881b ldrh r3, [r3, #0] + 8009594: 2b00 cmp r3, #0 + 8009596: d01d beq.n 80095d4 + while (acked > 0) { + acked16 = (u16_t)LWIP_MIN(acked, 0xffffu); + acked -= acked16; +#else + { + acked16 = recv_acked; + 8009598: 4b61 ldr r3, [pc, #388] ; (8009720 ) + 800959a: 881b ldrh r3, [r3, #0] + 800959c: 81fb strh r3, [r7, #14] +#endif + TCP_EVENT_SENT(pcb, (u16_t)acked16, err); + 800959e: 69bb ldr r3, [r7, #24] + 80095a0: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80095a4: 2b00 cmp r3, #0 + 80095a6: d00a beq.n 80095be + 80095a8: 69bb ldr r3, [r7, #24] + 80095aa: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80095ae: 69ba ldr r2, [r7, #24] + 80095b0: 6910 ldr r0, [r2, #16] + 80095b2: 89fa ldrh r2, [r7, #14] + 80095b4: 69b9 ldr r1, [r7, #24] + 80095b6: 4798 blx r3 + 80095b8: 4603 mov r3, r0 + 80095ba: 74fb strb r3, [r7, #19] + 80095bc: e001 b.n 80095c2 + 80095be: 2300 movs r3, #0 + 80095c0: 74fb strb r3, [r7, #19] + if (err == ERR_ABRT) { + 80095c2: f997 3013 ldrsb.w r3, [r7, #19] + 80095c6: f113 0f0d cmn.w r3, #13 + 80095ca: f000 8098 beq.w 80096fe + goto aborted; + } + } + recv_acked = 0; + 80095ce: 4b54 ldr r3, [pc, #336] ; (8009720 ) + 80095d0: 2200 movs r2, #0 + 80095d2: 801a strh r2, [r3, #0] + } + if (tcp_input_delayed_close(pcb)) { + 80095d4: 69b8 ldr r0, [r7, #24] + 80095d6: f000 f915 bl 8009804 + 80095da: 4603 mov r3, r0 + 80095dc: 2b00 cmp r3, #0 + 80095de: f040 8090 bne.w 8009702 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + while (recv_data != NULL) { + struct pbuf *rest = NULL; + pbuf_split_64k(recv_data, &rest); +#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + if (recv_data != NULL) { + 80095e2: 4b4d ldr r3, [pc, #308] ; (8009718 ) + 80095e4: 681b ldr r3, [r3, #0] + 80095e6: 2b00 cmp r3, #0 + 80095e8: d041 beq.n 800966e +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + + LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL); + 80095ea: 69bb ldr r3, [r7, #24] + 80095ec: 6f9b ldr r3, [r3, #120] ; 0x78 + 80095ee: 2b00 cmp r3, #0 + 80095f0: d006 beq.n 8009600 + 80095f2: 4b50 ldr r3, [pc, #320] ; (8009734 ) + 80095f4: f44f 72f3 mov.w r2, #486 ; 0x1e6 + 80095f8: 494f ldr r1, [pc, #316] ; (8009738 ) + 80095fa: 4850 ldr r0, [pc, #320] ; (800973c ) + 80095fc: f007 fae4 bl 8010bc8 + if (pcb->flags & TF_RXCLOSED) { + 8009600: 69bb ldr r3, [r7, #24] + 8009602: 8b5b ldrh r3, [r3, #26] + 8009604: f003 0310 and.w r3, r3, #16 + 8009608: 2b00 cmp r3, #0 + 800960a: d008 beq.n 800961e + /* received data although already closed -> abort (send RST) to + notify the remote host that not all data has been processed */ + pbuf_free(recv_data); + 800960c: 4b42 ldr r3, [pc, #264] ; (8009718 ) + 800960e: 681b ldr r3, [r3, #0] + 8009610: 4618 mov r0, r3 + 8009612: f7fd fcdf bl 8006fd4 +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_free(rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + tcp_abort(pcb); + 8009616: 69b8 ldr r0, [r7, #24] + 8009618: f7fe fa64 bl 8007ae4 + goto aborted; + 800961c: e091 b.n 8009742 + } + + /* Notify application that data has been received. */ + TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); + 800961e: 69bb ldr r3, [r7, #24] + 8009620: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8009624: 2b00 cmp r3, #0 + 8009626: d00c beq.n 8009642 + 8009628: 69bb ldr r3, [r7, #24] + 800962a: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 800962e: 69bb ldr r3, [r7, #24] + 8009630: 6918 ldr r0, [r3, #16] + 8009632: 4b39 ldr r3, [pc, #228] ; (8009718 ) + 8009634: 681a ldr r2, [r3, #0] + 8009636: 2300 movs r3, #0 + 8009638: 69b9 ldr r1, [r7, #24] + 800963a: 47a0 blx r4 + 800963c: 4603 mov r3, r0 + 800963e: 74fb strb r3, [r7, #19] + 8009640: e008 b.n 8009654 + 8009642: 4b35 ldr r3, [pc, #212] ; (8009718 ) + 8009644: 681a ldr r2, [r3, #0] + 8009646: 2300 movs r3, #0 + 8009648: 69b9 ldr r1, [r7, #24] + 800964a: 2000 movs r0, #0 + 800964c: f7ff f8d8 bl 8008800 + 8009650: 4603 mov r3, r0 + 8009652: 74fb strb r3, [r7, #19] + if (err == ERR_ABRT) { + 8009654: f997 3013 ldrsb.w r3, [r7, #19] + 8009658: f113 0f0d cmn.w r3, #13 + 800965c: d053 beq.n 8009706 +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + goto aborted; + } + + /* If the upper layer can't receive this data, store it */ + if (err != ERR_OK) { + 800965e: f997 3013 ldrsb.w r3, [r7, #19] + 8009662: 2b00 cmp r3, #0 + 8009664: d003 beq.n 800966e +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_cat(recv_data, rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = recv_data; + 8009666: 4b2c ldr r3, [pc, #176] ; (8009718 ) + 8009668: 681a ldr r2, [r3, #0] + 800966a: 69bb ldr r3, [r7, #24] + 800966c: 679a str r2, [r3, #120] ; 0x78 + } + } + + /* If a FIN segment was received, we call the callback + function with a NULL buffer to indicate EOF. */ + if (recv_flags & TF_GOT_FIN) { + 800966e: 4b2b ldr r3, [pc, #172] ; (800971c ) + 8009670: 781b ldrb r3, [r3, #0] + 8009672: f003 0320 and.w r3, r3, #32 + 8009676: 2b00 cmp r3, #0 + 8009678: d030 beq.n 80096dc + if (pcb->refused_data != NULL) { + 800967a: 69bb ldr r3, [r7, #24] + 800967c: 6f9b ldr r3, [r3, #120] ; 0x78 + 800967e: 2b00 cmp r3, #0 + 8009680: d009 beq.n 8009696 + /* Delay this if we have refused data. */ + pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN; + 8009682: 69bb ldr r3, [r7, #24] + 8009684: 6f9b ldr r3, [r3, #120] ; 0x78 + 8009686: 7b5a ldrb r2, [r3, #13] + 8009688: 69bb ldr r3, [r7, #24] + 800968a: 6f9b ldr r3, [r3, #120] ; 0x78 + 800968c: f042 0220 orr.w r2, r2, #32 + 8009690: b2d2 uxtb r2, r2 + 8009692: 735a strb r2, [r3, #13] + 8009694: e022 b.n 80096dc + } else { + /* correct rcv_wnd as the application won't call tcp_recved() + for the FIN's seqno */ + if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { + 8009696: 69bb ldr r3, [r7, #24] + 8009698: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800969a: f5b3 6f06 cmp.w r3, #2144 ; 0x860 + 800969e: d005 beq.n 80096ac + pcb->rcv_wnd++; + 80096a0: 69bb ldr r3, [r7, #24] + 80096a2: 8d1b ldrh r3, [r3, #40] ; 0x28 + 80096a4: 3301 adds r3, #1 + 80096a6: b29a uxth r2, r3 + 80096a8: 69bb ldr r3, [r7, #24] + 80096aa: 851a strh r2, [r3, #40] ; 0x28 + } + TCP_EVENT_CLOSED(pcb, err); + 80096ac: 69bb ldr r3, [r7, #24] + 80096ae: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80096b2: 2b00 cmp r3, #0 + 80096b4: d00b beq.n 80096ce + 80096b6: 69bb ldr r3, [r7, #24] + 80096b8: f8d3 4084 ldr.w r4, [r3, #132] ; 0x84 + 80096bc: 69bb ldr r3, [r7, #24] + 80096be: 6918 ldr r0, [r3, #16] + 80096c0: 2300 movs r3, #0 + 80096c2: 2200 movs r2, #0 + 80096c4: 69b9 ldr r1, [r7, #24] + 80096c6: 47a0 blx r4 + 80096c8: 4603 mov r3, r0 + 80096ca: 74fb strb r3, [r7, #19] + 80096cc: e001 b.n 80096d2 + 80096ce: 2300 movs r3, #0 + 80096d0: 74fb strb r3, [r7, #19] + if (err == ERR_ABRT) { + 80096d2: f997 3013 ldrsb.w r3, [r7, #19] + 80096d6: f113 0f0d cmn.w r3, #13 + 80096da: d016 beq.n 800970a + goto aborted; + } + } + } + + tcp_input_pcb = NULL; + 80096dc: 4b13 ldr r3, [pc, #76] ; (800972c ) + 80096de: 2200 movs r2, #0 + 80096e0: 601a str r2, [r3, #0] + if (tcp_input_delayed_close(pcb)) { + 80096e2: 69b8 ldr r0, [r7, #24] + 80096e4: f000 f88e bl 8009804 + 80096e8: 4603 mov r3, r0 + 80096ea: 2b00 cmp r3, #0 + 80096ec: d128 bne.n 8009740 + goto aborted; + } + /* Try to send something out. */ + tcp_output(pcb); + 80096ee: 69b8 ldr r0, [r7, #24] + 80096f0: f002 ff80 bl 800c5f4 + 80096f4: e025 b.n 8009742 + goto aborted; + 80096f6: bf00 nop + 80096f8: e023 b.n 8009742 +#endif /* TCP_INPUT_DEBUG */ + } + } + /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()). + Below this line, 'pcb' may not be dereferenced! */ +aborted: + 80096fa: bf00 nop + 80096fc: e021 b.n 8009742 + goto aborted; + 80096fe: bf00 nop + 8009700: e01f b.n 8009742 + goto aborted; + 8009702: bf00 nop + 8009704: e01d b.n 8009742 + goto aborted; + 8009706: bf00 nop + 8009708: e01b b.n 8009742 + goto aborted; + 800970a: bf00 nop + 800970c: e019 b.n 8009742 + 800970e: bf00 nop + 8009710: 24007b84 .word 0x24007b84 + 8009714: 24007b98 .word 0x24007b98 + 8009718: 24007bb8 .word 0x24007bb8 + 800971c: 24007bb5 .word 0x24007bb5 + 8009720: 24007bb0 .word 0x24007bb0 + 8009724: 24007bb4 .word 0x24007bb4 + 8009728: 24007bb2 .word 0x24007bb2 + 800972c: 24007bbc .word 0x24007bbc + 8009730: 24007b78 .word 0x24007b78 + 8009734: 08013198 .word 0x08013198 + 8009738: 0801334c .word 0x0801334c + 800973c: 080131e4 .word 0x080131e4 + goto aborted; + 8009740: bf00 nop + tcp_input_pcb = NULL; + 8009742: 4b27 ldr r3, [pc, #156] ; (80097e0 ) + 8009744: 2200 movs r2, #0 + 8009746: 601a str r2, [r3, #0] + recv_data = NULL; + 8009748: 4b26 ldr r3, [pc, #152] ; (80097e4 ) + 800974a: 2200 movs r2, #0 + 800974c: 601a str r2, [r3, #0] + + /* give up our reference to inseg.p */ + if (inseg.p != NULL) { + 800974e: 4b26 ldr r3, [pc, #152] ; (80097e8 ) + 8009750: 685b ldr r3, [r3, #4] + 8009752: 2b00 cmp r3, #0 + 8009754: d03f beq.n 80097d6 + pbuf_free(inseg.p); + 8009756: 4b24 ldr r3, [pc, #144] ; (80097e8 ) + 8009758: 685b ldr r3, [r3, #4] + 800975a: 4618 mov r0, r3 + 800975c: f7fd fc3a bl 8006fd4 + inseg.p = NULL; + 8009760: 4b21 ldr r3, [pc, #132] ; (80097e8 ) + 8009762: 2200 movs r2, #0 + 8009764: 605a str r2, [r3, #4] + pbuf_free(p); + } + + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); + return; + 8009766: e036 b.n 80097d6 + if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { + 8009768: 4b20 ldr r3, [pc, #128] ; (80097ec ) + 800976a: 681b ldr r3, [r3, #0] + 800976c: 899b ldrh r3, [r3, #12] + 800976e: b29b uxth r3, r3 + 8009770: 4618 mov r0, r3 + 8009772: f7fb feeb bl 800554c + 8009776: 4603 mov r3, r0 + 8009778: b2db uxtb r3, r3 + 800977a: f003 0304 and.w r3, r3, #4 + 800977e: 2b00 cmp r3, #0 + 8009780: d118 bne.n 80097b4 + tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009782: 4b1b ldr r3, [pc, #108] ; (80097f0 ) + 8009784: 6819 ldr r1, [r3, #0] + 8009786: 4b1b ldr r3, [pc, #108] ; (80097f4 ) + 8009788: 881b ldrh r3, [r3, #0] + 800978a: 461a mov r2, r3 + 800978c: 4b1a ldr r3, [pc, #104] ; (80097f8 ) + 800978e: 681b ldr r3, [r3, #0] + 8009790: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8009792: 4b16 ldr r3, [pc, #88] ; (80097ec ) + 8009794: 681b ldr r3, [r3, #0] + tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009796: 885b ldrh r3, [r3, #2] + 8009798: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 800979a: 4a14 ldr r2, [pc, #80] ; (80097ec ) + 800979c: 6812 ldr r2, [r2, #0] + tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), + 800979e: 8812 ldrh r2, [r2, #0] + 80097a0: b292 uxth r2, r2 + 80097a2: 9202 str r2, [sp, #8] + 80097a4: 9301 str r3, [sp, #4] + 80097a6: 4b15 ldr r3, [pc, #84] ; (80097fc ) + 80097a8: 9300 str r3, [sp, #0] + 80097aa: 4b15 ldr r3, [pc, #84] ; (8009800 ) + 80097ac: 4602 mov r2, r0 + 80097ae: 2000 movs r0, #0 + 80097b0: f003 fce0 bl 800d174 + pbuf_free(p); + 80097b4: 6878 ldr r0, [r7, #4] + 80097b6: f7fd fc0d bl 8006fd4 + return; + 80097ba: e00c b.n 80097d6 + goto dropped; + 80097bc: bf00 nop + 80097be: e006 b.n 80097ce + goto dropped; + 80097c0: bf00 nop + 80097c2: e004 b.n 80097ce + goto dropped; + 80097c4: bf00 nop + 80097c6: e002 b.n 80097ce + goto dropped; + 80097c8: bf00 nop + 80097ca: e000 b.n 80097ce + goto dropped; + 80097cc: bf00 nop +dropped: + TCP_STATS_INC(tcp.drop); + MIB2_STATS_INC(mib2.tcpinerrs); + pbuf_free(p); + 80097ce: 6878 ldr r0, [r7, #4] + 80097d0: f7fd fc00 bl 8006fd4 + 80097d4: e000 b.n 80097d8 + return; + 80097d6: bf00 nop +} + 80097d8: 3724 adds r7, #36 ; 0x24 + 80097da: 46bd mov sp, r7 + 80097dc: bd90 pop {r4, r7, pc} + 80097de: bf00 nop + 80097e0: 24007bbc .word 0x24007bbc + 80097e4: 24007bb8 .word 0x24007bb8 + 80097e8: 24007b84 .word 0x24007b84 + 80097ec: 24007b98 .word 0x24007b98 + 80097f0: 24007bac .word 0x24007bac + 80097f4: 24007bb2 .word 0x24007bb2 + 80097f8: 24007ba8 .word 0x24007ba8 + 80097fc: 24004c20 .word 0x24004c20 + 8009800: 24004c24 .word 0x24004c24 + +08009804 : + * any more. + * @returns 1 if the pcb has been closed and deallocated, 0 otherwise + */ +static int +tcp_input_delayed_close(struct tcp_pcb *pcb) +{ + 8009804: b580 push {r7, lr} + 8009806: b082 sub sp, #8 + 8009808: af00 add r7, sp, #0 + 800980a: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL); + 800980c: 687b ldr r3, [r7, #4] + 800980e: 2b00 cmp r3, #0 + 8009810: d106 bne.n 8009820 + 8009812: 4b17 ldr r3, [pc, #92] ; (8009870 ) + 8009814: f240 225a movw r2, #602 ; 0x25a + 8009818: 4916 ldr r1, [pc, #88] ; (8009874 ) + 800981a: 4817 ldr r0, [pc, #92] ; (8009878 ) + 800981c: f007 f9d4 bl 8010bc8 + + if (recv_flags & TF_CLOSED) { + 8009820: 4b16 ldr r3, [pc, #88] ; (800987c ) + 8009822: 781b ldrb r3, [r3, #0] + 8009824: f003 0310 and.w r3, r3, #16 + 8009828: 2b00 cmp r3, #0 + 800982a: d01c beq.n 8009866 + /* The connection has been closed and we will deallocate the + PCB. */ + if (!(pcb->flags & TF_RXCLOSED)) { + 800982c: 687b ldr r3, [r7, #4] + 800982e: 8b5b ldrh r3, [r3, #26] + 8009830: f003 0310 and.w r3, r3, #16 + 8009834: 2b00 cmp r3, #0 + 8009836: d10d bne.n 8009854 + /* Connection closed although the application has only shut down the + tx side: call the PCB's err callback and indicate the closure to + ensure the application doesn't continue using the PCB. */ + TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD); + 8009838: 687b ldr r3, [r7, #4] + 800983a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800983e: 2b00 cmp r3, #0 + 8009840: d008 beq.n 8009854 + 8009842: 687b ldr r3, [r7, #4] + 8009844: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8009848: 687a ldr r2, [r7, #4] + 800984a: 6912 ldr r2, [r2, #16] + 800984c: f06f 010e mvn.w r1, #14 + 8009850: 4610 mov r0, r2 + 8009852: 4798 blx r3 + } + tcp_pcb_remove(&tcp_active_pcbs, pcb); + 8009854: 6879 ldr r1, [r7, #4] + 8009856: 480a ldr r0, [pc, #40] ; (8009880 ) + 8009858: f7ff fa4a bl 8008cf0 + tcp_free(pcb); + 800985c: 6878 ldr r0, [r7, #4] + 800985e: f7fd fe59 bl 8007514 + return 1; + 8009862: 2301 movs r3, #1 + 8009864: e000 b.n 8009868 + } + return 0; + 8009866: 2300 movs r3, #0 +} + 8009868: 4618 mov r0, r3 + 800986a: 3708 adds r7, #8 + 800986c: 46bd mov sp, r7 + 800986e: bd80 pop {r7, pc} + 8009870: 08013198 .word 0x08013198 + 8009874: 08013368 .word 0x08013368 + 8009878: 080131e4 .word 0x080131e4 + 800987c: 24007bb5 .word 0x24007bb5 + 8009880: 24007b78 .word 0x24007b78 + +08009884 : + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static void +tcp_listen_input(struct tcp_pcb_listen *pcb) +{ + 8009884: b590 push {r4, r7, lr} + 8009886: b08b sub sp, #44 ; 0x2c + 8009888: af04 add r7, sp, #16 + 800988a: 6078 str r0, [r7, #4] + struct tcp_pcb *npcb; + u32_t iss; + err_t rc; + + if (flags & TCP_RST) { + 800988c: 4b6f ldr r3, [pc, #444] ; (8009a4c ) + 800988e: 781b ldrb r3, [r3, #0] + 8009890: f003 0304 and.w r3, r3, #4 + 8009894: 2b00 cmp r3, #0 + 8009896: f040 80d2 bne.w 8009a3e + /* An incoming RST should be ignored. Return. */ + return; + } + + LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL); + 800989a: 687b ldr r3, [r7, #4] + 800989c: 2b00 cmp r3, #0 + 800989e: d106 bne.n 80098ae + 80098a0: 4b6b ldr r3, [pc, #428] ; (8009a50 ) + 80098a2: f240 2281 movw r2, #641 ; 0x281 + 80098a6: 496b ldr r1, [pc, #428] ; (8009a54 ) + 80098a8: 486b ldr r0, [pc, #428] ; (8009a58 ) + 80098aa: f007 f98d bl 8010bc8 + + /* In the LISTEN state, we check for incoming SYN segments, + creates a new PCB, and responds with a SYN|ACK. */ + if (flags & TCP_ACK) { + 80098ae: 4b67 ldr r3, [pc, #412] ; (8009a4c ) + 80098b0: 781b ldrb r3, [r3, #0] + 80098b2: f003 0310 and.w r3, r3, #16 + 80098b6: 2b00 cmp r3, #0 + 80098b8: d019 beq.n 80098ee + /* For incoming segments with the ACK flag set, respond with a + RST. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); + tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 80098ba: 4b68 ldr r3, [pc, #416] ; (8009a5c ) + 80098bc: 6819 ldr r1, [r3, #0] + 80098be: 4b68 ldr r3, [pc, #416] ; (8009a60 ) + 80098c0: 881b ldrh r3, [r3, #0] + 80098c2: 461a mov r2, r3 + 80098c4: 4b67 ldr r3, [pc, #412] ; (8009a64 ) + 80098c6: 681b ldr r3, [r3, #0] + 80098c8: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 80098ca: 4b67 ldr r3, [pc, #412] ; (8009a68 ) + 80098cc: 681b ldr r3, [r3, #0] + tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 80098ce: 885b ldrh r3, [r3, #2] + 80098d0: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 80098d2: 4a65 ldr r2, [pc, #404] ; (8009a68 ) + 80098d4: 6812 ldr r2, [r2, #0] + tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 80098d6: 8812 ldrh r2, [r2, #0] + 80098d8: b292 uxth r2, r2 + 80098da: 9202 str r2, [sp, #8] + 80098dc: 9301 str r3, [sp, #4] + 80098de: 4b63 ldr r3, [pc, #396] ; (8009a6c ) + 80098e0: 9300 str r3, [sp, #0] + 80098e2: 4b63 ldr r3, [pc, #396] ; (8009a70 ) + 80098e4: 4602 mov r2, r0 + 80098e6: 6878 ldr r0, [r7, #4] + 80098e8: f003 fc44 bl 800d174 + tcp_abandon(npcb, 0); + return; + } + tcp_output(npcb); + } + return; + 80098ec: e0a9 b.n 8009a42 + } else if (flags & TCP_SYN) { + 80098ee: 4b57 ldr r3, [pc, #348] ; (8009a4c ) + 80098f0: 781b ldrb r3, [r3, #0] + 80098f2: f003 0302 and.w r3, r3, #2 + 80098f6: 2b00 cmp r3, #0 + 80098f8: f000 80a3 beq.w 8009a42 + npcb = tcp_alloc(pcb->prio); + 80098fc: 687b ldr r3, [r7, #4] + 80098fe: 7d5b ldrb r3, [r3, #21] + 8009900: 4618 mov r0, r3 + 8009902: f7ff f8a1 bl 8008a48 + 8009906: 6178 str r0, [r7, #20] + if (npcb == NULL) { + 8009908: 697b ldr r3, [r7, #20] + 800990a: 2b00 cmp r3, #0 + 800990c: d111 bne.n 8009932 + TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); + 800990e: 687b ldr r3, [r7, #4] + 8009910: 699b ldr r3, [r3, #24] + 8009912: 2b00 cmp r3, #0 + 8009914: d00a beq.n 800992c + 8009916: 687b ldr r3, [r7, #4] + 8009918: 699b ldr r3, [r3, #24] + 800991a: 687a ldr r2, [r7, #4] + 800991c: 6910 ldr r0, [r2, #16] + 800991e: f04f 32ff mov.w r2, #4294967295 + 8009922: 2100 movs r1, #0 + 8009924: 4798 blx r3 + 8009926: 4603 mov r3, r0 + 8009928: 73bb strb r3, [r7, #14] + return; + 800992a: e08b b.n 8009a44 + TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); + 800992c: 23f0 movs r3, #240 ; 0xf0 + 800992e: 73bb strb r3, [r7, #14] + return; + 8009930: e088 b.n 8009a44 + ip_addr_copy(npcb->local_ip, *ip_current_dest_addr()); + 8009932: 4b50 ldr r3, [pc, #320] ; (8009a74 ) + 8009934: 695a ldr r2, [r3, #20] + 8009936: 697b ldr r3, [r7, #20] + 8009938: 601a str r2, [r3, #0] + ip_addr_copy(npcb->remote_ip, *ip_current_src_addr()); + 800993a: 4b4e ldr r3, [pc, #312] ; (8009a74 ) + 800993c: 691a ldr r2, [r3, #16] + 800993e: 697b ldr r3, [r7, #20] + 8009940: 605a str r2, [r3, #4] + npcb->local_port = pcb->local_port; + 8009942: 687b ldr r3, [r7, #4] + 8009944: 8ada ldrh r2, [r3, #22] + 8009946: 697b ldr r3, [r7, #20] + 8009948: 82da strh r2, [r3, #22] + npcb->remote_port = tcphdr->src; + 800994a: 4b47 ldr r3, [pc, #284] ; (8009a68 ) + 800994c: 681b ldr r3, [r3, #0] + 800994e: 881b ldrh r3, [r3, #0] + 8009950: b29a uxth r2, r3 + 8009952: 697b ldr r3, [r7, #20] + 8009954: 831a strh r2, [r3, #24] + npcb->state = SYN_RCVD; + 8009956: 697b ldr r3, [r7, #20] + 8009958: 2203 movs r2, #3 + 800995a: 751a strb r2, [r3, #20] + npcb->rcv_nxt = seqno + 1; + 800995c: 4b41 ldr r3, [pc, #260] ; (8009a64 ) + 800995e: 681b ldr r3, [r3, #0] + 8009960: 1c5a adds r2, r3, #1 + 8009962: 697b ldr r3, [r7, #20] + 8009964: 625a str r2, [r3, #36] ; 0x24 + npcb->rcv_ann_right_edge = npcb->rcv_nxt; + 8009966: 697b ldr r3, [r7, #20] + 8009968: 6a5a ldr r2, [r3, #36] ; 0x24 + 800996a: 697b ldr r3, [r7, #20] + 800996c: 62da str r2, [r3, #44] ; 0x2c + iss = tcp_next_iss(npcb); + 800996e: 6978 ldr r0, [r7, #20] + 8009970: f7ff fa52 bl 8008e18 + 8009974: 6138 str r0, [r7, #16] + npcb->snd_wl2 = iss; + 8009976: 697b ldr r3, [r7, #20] + 8009978: 693a ldr r2, [r7, #16] + 800997a: 659a str r2, [r3, #88] ; 0x58 + npcb->snd_nxt = iss; + 800997c: 697b ldr r3, [r7, #20] + 800997e: 693a ldr r2, [r7, #16] + 8009980: 651a str r2, [r3, #80] ; 0x50 + npcb->lastack = iss; + 8009982: 697b ldr r3, [r7, #20] + 8009984: 693a ldr r2, [r7, #16] + 8009986: 645a str r2, [r3, #68] ; 0x44 + npcb->snd_lbb = iss; + 8009988: 697b ldr r3, [r7, #20] + 800998a: 693a ldr r2, [r7, #16] + 800998c: 65da str r2, [r3, #92] ; 0x5c + npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ + 800998e: 4b35 ldr r3, [pc, #212] ; (8009a64 ) + 8009990: 681b ldr r3, [r3, #0] + 8009992: 1e5a subs r2, r3, #1 + 8009994: 697b ldr r3, [r7, #20] + 8009996: 655a str r2, [r3, #84] ; 0x54 + npcb->callback_arg = pcb->callback_arg; + 8009998: 687b ldr r3, [r7, #4] + 800999a: 691a ldr r2, [r3, #16] + 800999c: 697b ldr r3, [r7, #20] + 800999e: 611a str r2, [r3, #16] + npcb->listener = pcb; + 80099a0: 697b ldr r3, [r7, #20] + 80099a2: 687a ldr r2, [r7, #4] + 80099a4: 67da str r2, [r3, #124] ; 0x7c + npcb->so_options = pcb->so_options & SOF_INHERITED; + 80099a6: 687b ldr r3, [r7, #4] + 80099a8: 7a5b ldrb r3, [r3, #9] + 80099aa: f003 030c and.w r3, r3, #12 + 80099ae: b2da uxtb r2, r3 + 80099b0: 697b ldr r3, [r7, #20] + 80099b2: 725a strb r2, [r3, #9] + npcb->netif_idx = pcb->netif_idx; + 80099b4: 687b ldr r3, [r7, #4] + 80099b6: 7a1a ldrb r2, [r3, #8] + 80099b8: 697b ldr r3, [r7, #20] + 80099ba: 721a strb r2, [r3, #8] + TCP_REG_ACTIVE(npcb); + 80099bc: 4b2e ldr r3, [pc, #184] ; (8009a78 ) + 80099be: 681a ldr r2, [r3, #0] + 80099c0: 697b ldr r3, [r7, #20] + 80099c2: 60da str r2, [r3, #12] + 80099c4: 4a2c ldr r2, [pc, #176] ; (8009a78 ) + 80099c6: 697b ldr r3, [r7, #20] + 80099c8: 6013 str r3, [r2, #0] + 80099ca: f003 fd95 bl 800d4f8 + 80099ce: 4b2b ldr r3, [pc, #172] ; (8009a7c ) + 80099d0: 2201 movs r2, #1 + 80099d2: 701a strb r2, [r3, #0] + tcp_parseopt(npcb); + 80099d4: 6978 ldr r0, [r7, #20] + 80099d6: f001 fd8f bl 800b4f8 + npcb->snd_wnd = tcphdr->wnd; + 80099da: 4b23 ldr r3, [pc, #140] ; (8009a68 ) + 80099dc: 681b ldr r3, [r3, #0] + 80099de: 89db ldrh r3, [r3, #14] + 80099e0: b29a uxth r2, r3 + 80099e2: 697b ldr r3, [r7, #20] + 80099e4: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + npcb->snd_wnd_max = npcb->snd_wnd; + 80099e8: 697b ldr r3, [r7, #20] + 80099ea: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 80099ee: 697b ldr r3, [r7, #20] + 80099f0: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 + npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip); + 80099f4: 697b ldr r3, [r7, #20] + 80099f6: 8e5c ldrh r4, [r3, #50] ; 0x32 + 80099f8: 697b ldr r3, [r7, #20] + 80099fa: 3304 adds r3, #4 + 80099fc: 4618 mov r0, r3 + 80099fe: f005 fa43 bl 800ee88 + 8009a02: 4601 mov r1, r0 + 8009a04: 697b ldr r3, [r7, #20] + 8009a06: 3304 adds r3, #4 + 8009a08: 461a mov r2, r3 + 8009a0a: 4620 mov r0, r4 + 8009a0c: f7ff fa2a bl 8008e64 + 8009a10: 4603 mov r3, r0 + 8009a12: 461a mov r2, r3 + 8009a14: 697b ldr r3, [r7, #20] + 8009a16: 865a strh r2, [r3, #50] ; 0x32 + rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK); + 8009a18: 2112 movs r1, #18 + 8009a1a: 6978 ldr r0, [r7, #20] + 8009a1c: f002 fcfc bl 800c418 + 8009a20: 4603 mov r3, r0 + 8009a22: 73fb strb r3, [r7, #15] + if (rc != ERR_OK) { + 8009a24: f997 300f ldrsb.w r3, [r7, #15] + 8009a28: 2b00 cmp r3, #0 + 8009a2a: d004 beq.n 8009a36 + tcp_abandon(npcb, 0); + 8009a2c: 2100 movs r1, #0 + 8009a2e: 6978 ldr r0, [r7, #20] + 8009a30: f7fd ff9a bl 8007968 + return; + 8009a34: e006 b.n 8009a44 + tcp_output(npcb); + 8009a36: 6978 ldr r0, [r7, #20] + 8009a38: f002 fddc bl 800c5f4 + return; + 8009a3c: e001 b.n 8009a42 + return; + 8009a3e: bf00 nop + 8009a40: e000 b.n 8009a44 + return; + 8009a42: bf00 nop +} + 8009a44: 371c adds r7, #28 + 8009a46: 46bd mov sp, r7 + 8009a48: bd90 pop {r4, r7, pc} + 8009a4a: bf00 nop + 8009a4c: 24007bb4 .word 0x24007bb4 + 8009a50: 08013198 .word 0x08013198 + 8009a54: 08013390 .word 0x08013390 + 8009a58: 080131e4 .word 0x080131e4 + 8009a5c: 24007bac .word 0x24007bac + 8009a60: 24007bb2 .word 0x24007bb2 + 8009a64: 24007ba8 .word 0x24007ba8 + 8009a68: 24007b98 .word 0x24007b98 + 8009a6c: 24004c20 .word 0x24004c20 + 8009a70: 24004c24 .word 0x24004c24 + 8009a74: 24004c10 .word 0x24004c10 + 8009a78: 24007b78 .word 0x24007b78 + 8009a7c: 24007b80 .word 0x24007b80 + +08009a80 : + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static void +tcp_timewait_input(struct tcp_pcb *pcb) +{ + 8009a80: b580 push {r7, lr} + 8009a82: b086 sub sp, #24 + 8009a84: af04 add r7, sp, #16 + 8009a86: 6078 str r0, [r7, #4] + /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ + /* RFC 793 3.9 Event Processing - Segment Arrives: + * - first check sequence number - we skip that one in TIME_WAIT (always + * acceptable since we only send ACKs) + * - second check the RST bit (... return) */ + if (flags & TCP_RST) { + 8009a88: 4b2f ldr r3, [pc, #188] ; (8009b48 ) + 8009a8a: 781b ldrb r3, [r3, #0] + 8009a8c: f003 0304 and.w r3, r3, #4 + 8009a90: 2b00 cmp r3, #0 + 8009a92: d153 bne.n 8009b3c + return; + } + + LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL); + 8009a94: 687b ldr r3, [r7, #4] + 8009a96: 2b00 cmp r3, #0 + 8009a98: d106 bne.n 8009aa8 + 8009a9a: 4b2c ldr r3, [pc, #176] ; (8009b4c ) + 8009a9c: f240 22ee movw r2, #750 ; 0x2ee + 8009aa0: 492b ldr r1, [pc, #172] ; (8009b50 ) + 8009aa2: 482c ldr r0, [pc, #176] ; (8009b54 ) + 8009aa4: f007 f890 bl 8010bc8 + + /* - fourth, check the SYN bit, */ + if (flags & TCP_SYN) { + 8009aa8: 4b27 ldr r3, [pc, #156] ; (8009b48 ) + 8009aaa: 781b ldrb r3, [r3, #0] + 8009aac: f003 0302 and.w r3, r3, #2 + 8009ab0: 2b00 cmp r3, #0 + 8009ab2: d02a beq.n 8009b0a + /* If an incoming segment is not acceptable, an acknowledgment + should be sent in reply */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) { + 8009ab4: 4b28 ldr r3, [pc, #160] ; (8009b58 ) + 8009ab6: 681a ldr r2, [r3, #0] + 8009ab8: 687b ldr r3, [r7, #4] + 8009aba: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009abc: 1ad3 subs r3, r2, r3 + 8009abe: 2b00 cmp r3, #0 + 8009ac0: db2d blt.n 8009b1e + 8009ac2: 4b25 ldr r3, [pc, #148] ; (8009b58 ) + 8009ac4: 681a ldr r2, [r3, #0] + 8009ac6: 687b ldr r3, [r7, #4] + 8009ac8: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009aca: 6879 ldr r1, [r7, #4] + 8009acc: 8d09 ldrh r1, [r1, #40] ; 0x28 + 8009ace: 440b add r3, r1 + 8009ad0: 1ad3 subs r3, r2, r3 + 8009ad2: 2b00 cmp r3, #0 + 8009ad4: dc23 bgt.n 8009b1e + /* If the SYN is in the window it is an error, send a reset */ + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009ad6: 4b21 ldr r3, [pc, #132] ; (8009b5c ) + 8009ad8: 6819 ldr r1, [r3, #0] + 8009ada: 4b21 ldr r3, [pc, #132] ; (8009b60 ) + 8009adc: 881b ldrh r3, [r3, #0] + 8009ade: 461a mov r2, r3 + 8009ae0: 4b1d ldr r3, [pc, #116] ; (8009b58 ) + 8009ae2: 681b ldr r3, [r3, #0] + 8009ae4: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8009ae6: 4b1f ldr r3, [pc, #124] ; (8009b64 ) + 8009ae8: 681b ldr r3, [r3, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009aea: 885b ldrh r3, [r3, #2] + 8009aec: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8009aee: 4a1d ldr r2, [pc, #116] ; (8009b64 ) + 8009af0: 6812 ldr r2, [r2, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009af2: 8812 ldrh r2, [r2, #0] + 8009af4: b292 uxth r2, r2 + 8009af6: 9202 str r2, [sp, #8] + 8009af8: 9301 str r3, [sp, #4] + 8009afa: 4b1b ldr r3, [pc, #108] ; (8009b68 ) + 8009afc: 9300 str r3, [sp, #0] + 8009afe: 4b1b ldr r3, [pc, #108] ; (8009b6c ) + 8009b00: 4602 mov r2, r0 + 8009b02: 6878 ldr r0, [r7, #4] + 8009b04: f003 fb36 bl 800d174 + return; + 8009b08: e01b b.n 8009b42 + } + } else if (flags & TCP_FIN) { + 8009b0a: 4b0f ldr r3, [pc, #60] ; (8009b48 ) + 8009b0c: 781b ldrb r3, [r3, #0] + 8009b0e: f003 0301 and.w r3, r3, #1 + 8009b12: 2b00 cmp r3, #0 + 8009b14: d003 beq.n 8009b1e + /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. + Restart the 2 MSL time-wait timeout.*/ + pcb->tmr = tcp_ticks; + 8009b16: 4b16 ldr r3, [pc, #88] ; (8009b70 ) + 8009b18: 681a ldr r2, [r3, #0] + 8009b1a: 687b ldr r3, [r7, #4] + 8009b1c: 621a str r2, [r3, #32] + } + + if ((tcplen > 0)) { + 8009b1e: 4b10 ldr r3, [pc, #64] ; (8009b60 ) + 8009b20: 881b ldrh r3, [r3, #0] + 8009b22: 2b00 cmp r3, #0 + 8009b24: d00c beq.n 8009b40 + /* Acknowledge data, FIN or out-of-window SYN */ + tcp_ack_now(pcb); + 8009b26: 687b ldr r3, [r7, #4] + 8009b28: 8b5b ldrh r3, [r3, #26] + 8009b2a: f043 0302 orr.w r3, r3, #2 + 8009b2e: b29a uxth r2, r3 + 8009b30: 687b ldr r3, [r7, #4] + 8009b32: 835a strh r2, [r3, #26] + tcp_output(pcb); + 8009b34: 6878 ldr r0, [r7, #4] + 8009b36: f002 fd5d bl 800c5f4 + } + return; + 8009b3a: e001 b.n 8009b40 + return; + 8009b3c: bf00 nop + 8009b3e: e000 b.n 8009b42 + return; + 8009b40: bf00 nop +} + 8009b42: 3708 adds r7, #8 + 8009b44: 46bd mov sp, r7 + 8009b46: bd80 pop {r7, pc} + 8009b48: 24007bb4 .word 0x24007bb4 + 8009b4c: 08013198 .word 0x08013198 + 8009b50: 080133b0 .word 0x080133b0 + 8009b54: 080131e4 .word 0x080131e4 + 8009b58: 24007ba8 .word 0x24007ba8 + 8009b5c: 24007bac .word 0x24007bac + 8009b60: 24007bb2 .word 0x24007bb2 + 8009b64: 24007b98 .word 0x24007b98 + 8009b68: 24004c20 .word 0x24004c20 + 8009b6c: 24004c24 .word 0x24004c24 + 8009b70: 24007b6c .word 0x24007b6c + +08009b74 : + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_process(struct tcp_pcb *pcb) +{ + 8009b74: b590 push {r4, r7, lr} + 8009b76: b08d sub sp, #52 ; 0x34 + 8009b78: af04 add r7, sp, #16 + 8009b7a: 6078 str r0, [r7, #4] + struct tcp_seg *rseg; + u8_t acceptable = 0; + 8009b7c: 2300 movs r3, #0 + 8009b7e: 77fb strb r3, [r7, #31] + err_t err; + + err = ERR_OK; + 8009b80: 2300 movs r3, #0 + 8009b82: 77bb strb r3, [r7, #30] + + LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL); + 8009b84: 687b ldr r3, [r7, #4] + 8009b86: 2b00 cmp r3, #0 + 8009b88: d106 bne.n 8009b98 + 8009b8a: 4b9d ldr r3, [pc, #628] ; (8009e00 ) + 8009b8c: f44f 7247 mov.w r2, #796 ; 0x31c + 8009b90: 499c ldr r1, [pc, #624] ; (8009e04 ) + 8009b92: 489d ldr r0, [pc, #628] ; (8009e08 ) + 8009b94: f007 f818 bl 8010bc8 + + /* Process incoming RST segments. */ + if (flags & TCP_RST) { + 8009b98: 4b9c ldr r3, [pc, #624] ; (8009e0c ) + 8009b9a: 781b ldrb r3, [r3, #0] + 8009b9c: f003 0304 and.w r3, r3, #4 + 8009ba0: 2b00 cmp r3, #0 + 8009ba2: d04e beq.n 8009c42 + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + 8009ba4: 687b ldr r3, [r7, #4] + 8009ba6: 7d1b ldrb r3, [r3, #20] + 8009ba8: 2b02 cmp r3, #2 + 8009baa: d108 bne.n 8009bbe + /* "In the SYN-SENT state (a RST received in response to an initial SYN), + the RST is acceptable if the ACK field acknowledges the SYN." */ + if (ackno == pcb->snd_nxt) { + 8009bac: 687b ldr r3, [r7, #4] + 8009bae: 6d1a ldr r2, [r3, #80] ; 0x50 + 8009bb0: 4b97 ldr r3, [pc, #604] ; (8009e10 ) + 8009bb2: 681b ldr r3, [r3, #0] + 8009bb4: 429a cmp r2, r3 + 8009bb6: d123 bne.n 8009c00 + acceptable = 1; + 8009bb8: 2301 movs r3, #1 + 8009bba: 77fb strb r3, [r7, #31] + 8009bbc: e020 b.n 8009c00 + } + } else { + /* "In all states except SYN-SENT, all reset (RST) segments are validated + by checking their SEQ-fields." */ + if (seqno == pcb->rcv_nxt) { + 8009bbe: 687b ldr r3, [r7, #4] + 8009bc0: 6a5a ldr r2, [r3, #36] ; 0x24 + 8009bc2: 4b94 ldr r3, [pc, #592] ; (8009e14 ) + 8009bc4: 681b ldr r3, [r3, #0] + 8009bc6: 429a cmp r2, r3 + 8009bc8: d102 bne.n 8009bd0 + acceptable = 1; + 8009bca: 2301 movs r3, #1 + 8009bcc: 77fb strb r3, [r7, #31] + 8009bce: e017 b.n 8009c00 + } else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + 8009bd0: 4b90 ldr r3, [pc, #576] ; (8009e14 ) + 8009bd2: 681a ldr r2, [r3, #0] + 8009bd4: 687b ldr r3, [r7, #4] + 8009bd6: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009bd8: 1ad3 subs r3, r2, r3 + 8009bda: 2b00 cmp r3, #0 + 8009bdc: db10 blt.n 8009c00 + 8009bde: 4b8d ldr r3, [pc, #564] ; (8009e14 ) + 8009be0: 681a ldr r2, [r3, #0] + 8009be2: 687b ldr r3, [r7, #4] + 8009be4: 6a5b ldr r3, [r3, #36] ; 0x24 + 8009be6: 6879 ldr r1, [r7, #4] + 8009be8: 8d09 ldrh r1, [r1, #40] ; 0x28 + 8009bea: 440b add r3, r1 + 8009bec: 1ad3 subs r3, r2, r3 + 8009bee: 2b00 cmp r3, #0 + 8009bf0: dc06 bgt.n 8009c00 + pcb->rcv_nxt + pcb->rcv_wnd)) { + /* If the sequence number is inside the window, we send a challenge ACK + and wait for a re-send with matching sequence number. + This follows RFC 5961 section 3.2 and addresses CVE-2004-0230 + (RST spoofing attack), which is present in RFC 793 RST handling. */ + tcp_ack_now(pcb); + 8009bf2: 687b ldr r3, [r7, #4] + 8009bf4: 8b5b ldrh r3, [r3, #26] + 8009bf6: f043 0302 orr.w r3, r3, #2 + 8009bfa: b29a uxth r2, r3 + 8009bfc: 687b ldr r3, [r7, #4] + 8009bfe: 835a strh r2, [r3, #26] + } + } + + if (acceptable) { + 8009c00: 7ffb ldrb r3, [r7, #31] + 8009c02: 2b00 cmp r3, #0 + 8009c04: d01b beq.n 8009c3e + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); + LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); + 8009c06: 687b ldr r3, [r7, #4] + 8009c08: 7d1b ldrb r3, [r3, #20] + 8009c0a: 2b00 cmp r3, #0 + 8009c0c: d106 bne.n 8009c1c + 8009c0e: 4b7c ldr r3, [pc, #496] ; (8009e00 ) + 8009c10: f44f 724e mov.w r2, #824 ; 0x338 + 8009c14: 4980 ldr r1, [pc, #512] ; (8009e18 ) + 8009c16: 487c ldr r0, [pc, #496] ; (8009e08 ) + 8009c18: f006 ffd6 bl 8010bc8 + recv_flags |= TF_RESET; + 8009c1c: 4b7f ldr r3, [pc, #508] ; (8009e1c ) + 8009c1e: 781b ldrb r3, [r3, #0] + 8009c20: f043 0308 orr.w r3, r3, #8 + 8009c24: b2da uxtb r2, r3 + 8009c26: 4b7d ldr r3, [pc, #500] ; (8009e1c ) + 8009c28: 701a strb r2, [r3, #0] + tcp_clear_flags(pcb, TF_ACK_DELAY); + 8009c2a: 687b ldr r3, [r7, #4] + 8009c2c: 8b5b ldrh r3, [r3, #26] + 8009c2e: f023 0301 bic.w r3, r3, #1 + 8009c32: b29a uxth r2, r3 + 8009c34: 687b ldr r3, [r7, #4] + 8009c36: 835a strh r2, [r3, #26] + return ERR_RST; + 8009c38: f06f 030d mvn.w r3, #13 + 8009c3c: e37a b.n 800a334 + } else { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + 8009c3e: 2300 movs r3, #0 + 8009c40: e378 b.n 800a334 + } + } + + if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { + 8009c42: 4b72 ldr r3, [pc, #456] ; (8009e0c ) + 8009c44: 781b ldrb r3, [r3, #0] + 8009c46: f003 0302 and.w r3, r3, #2 + 8009c4a: 2b00 cmp r3, #0 + 8009c4c: d010 beq.n 8009c70 + 8009c4e: 687b ldr r3, [r7, #4] + 8009c50: 7d1b ldrb r3, [r3, #20] + 8009c52: 2b02 cmp r3, #2 + 8009c54: d00c beq.n 8009c70 + 8009c56: 687b ldr r3, [r7, #4] + 8009c58: 7d1b ldrb r3, [r3, #20] + 8009c5a: 2b03 cmp r3, #3 + 8009c5c: d008 beq.n 8009c70 + /* Cope with new connection attempt after remote end crashed */ + tcp_ack_now(pcb); + 8009c5e: 687b ldr r3, [r7, #4] + 8009c60: 8b5b ldrh r3, [r3, #26] + 8009c62: f043 0302 orr.w r3, r3, #2 + 8009c66: b29a uxth r2, r3 + 8009c68: 687b ldr r3, [r7, #4] + 8009c6a: 835a strh r2, [r3, #26] + return ERR_OK; + 8009c6c: 2300 movs r3, #0 + 8009c6e: e361 b.n 800a334 + } + + if ((pcb->flags & TF_RXCLOSED) == 0) { + 8009c70: 687b ldr r3, [r7, #4] + 8009c72: 8b5b ldrh r3, [r3, #26] + 8009c74: f003 0310 and.w r3, r3, #16 + 8009c78: 2b00 cmp r3, #0 + 8009c7a: d103 bne.n 8009c84 + /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */ + pcb->tmr = tcp_ticks; + 8009c7c: 4b68 ldr r3, [pc, #416] ; (8009e20 ) + 8009c7e: 681a ldr r2, [r3, #0] + 8009c80: 687b ldr r3, [r7, #4] + 8009c82: 621a str r2, [r3, #32] + } + pcb->keep_cnt_sent = 0; + 8009c84: 687b ldr r3, [r7, #4] + 8009c86: 2200 movs r2, #0 + 8009c88: f883 209b strb.w r2, [r3, #155] ; 0x9b + pcb->persist_probe = 0; + 8009c8c: 687b ldr r3, [r7, #4] + 8009c8e: 2200 movs r2, #0 + 8009c90: f883 209a strb.w r2, [r3, #154] ; 0x9a + + tcp_parseopt(pcb); + 8009c94: 6878 ldr r0, [r7, #4] + 8009c96: f001 fc2f bl 800b4f8 + + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + 8009c9a: 687b ldr r3, [r7, #4] + 8009c9c: 7d1b ldrb r3, [r3, #20] + 8009c9e: 3b02 subs r3, #2 + 8009ca0: 2b07 cmp r3, #7 + 8009ca2: f200 8337 bhi.w 800a314 + 8009ca6: a201 add r2, pc, #4 ; (adr r2, 8009cac ) + 8009ca8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009cac: 08009ccd .word 0x08009ccd + 8009cb0: 08009efd .word 0x08009efd + 8009cb4: 0800a075 .word 0x0800a075 + 8009cb8: 0800a09f .word 0x0800a09f + 8009cbc: 0800a1c3 .word 0x0800a1c3 + 8009cc0: 0800a075 .word 0x0800a075 + 8009cc4: 0800a24f .word 0x0800a24f + 8009cc8: 0800a2df .word 0x0800a2df + case SYN_SENT: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, + pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno))); + /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + 8009ccc: 4b4f ldr r3, [pc, #316] ; (8009e0c ) + 8009cce: 781b ldrb r3, [r3, #0] + 8009cd0: f003 0310 and.w r3, r3, #16 + 8009cd4: 2b00 cmp r3, #0 + 8009cd6: f000 80e4 beq.w 8009ea2 + 8009cda: 4b4c ldr r3, [pc, #304] ; (8009e0c ) + 8009cdc: 781b ldrb r3, [r3, #0] + 8009cde: f003 0302 and.w r3, r3, #2 + 8009ce2: 2b00 cmp r3, #0 + 8009ce4: f000 80dd beq.w 8009ea2 + && (ackno == pcb->lastack + 1)) { + 8009ce8: 687b ldr r3, [r7, #4] + 8009cea: 6c5b ldr r3, [r3, #68] ; 0x44 + 8009cec: 1c5a adds r2, r3, #1 + 8009cee: 4b48 ldr r3, [pc, #288] ; (8009e10 ) + 8009cf0: 681b ldr r3, [r3, #0] + 8009cf2: 429a cmp r2, r3 + 8009cf4: f040 80d5 bne.w 8009ea2 + pcb->rcv_nxt = seqno + 1; + 8009cf8: 4b46 ldr r3, [pc, #280] ; (8009e14 ) + 8009cfa: 681b ldr r3, [r3, #0] + 8009cfc: 1c5a adds r2, r3, #1 + 8009cfe: 687b ldr r3, [r7, #4] + 8009d00: 625a str r2, [r3, #36] ; 0x24 + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + 8009d02: 687b ldr r3, [r7, #4] + 8009d04: 6a5a ldr r2, [r3, #36] ; 0x24 + 8009d06: 687b ldr r3, [r7, #4] + 8009d08: 62da str r2, [r3, #44] ; 0x2c + pcb->lastack = ackno; + 8009d0a: 4b41 ldr r3, [pc, #260] ; (8009e10 ) + 8009d0c: 681a ldr r2, [r3, #0] + 8009d0e: 687b ldr r3, [r7, #4] + 8009d10: 645a str r2, [r3, #68] ; 0x44 + pcb->snd_wnd = tcphdr->wnd; + 8009d12: 4b44 ldr r3, [pc, #272] ; (8009e24 ) + 8009d14: 681b ldr r3, [r3, #0] + 8009d16: 89db ldrh r3, [r3, #14] + 8009d18: b29a uxth r2, r3 + 8009d1a: 687b ldr r3, [r7, #4] + 8009d1c: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + pcb->snd_wnd_max = pcb->snd_wnd; + 8009d20: 687b ldr r3, [r7, #4] + 8009d22: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 8009d26: 687b ldr r3, [r7, #4] + 8009d28: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 + pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ + 8009d2c: 4b39 ldr r3, [pc, #228] ; (8009e14 ) + 8009d2e: 681b ldr r3, [r3, #0] + 8009d30: 1e5a subs r2, r3, #1 + 8009d32: 687b ldr r3, [r7, #4] + 8009d34: 655a str r2, [r3, #84] ; 0x54 + pcb->state = ESTABLISHED; + 8009d36: 687b ldr r3, [r7, #4] + 8009d38: 2204 movs r2, #4 + 8009d3a: 751a strb r2, [r3, #20] + +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip); + 8009d3c: 687b ldr r3, [r7, #4] + 8009d3e: 8e5c ldrh r4, [r3, #50] ; 0x32 + 8009d40: 687b ldr r3, [r7, #4] + 8009d42: 3304 adds r3, #4 + 8009d44: 4618 mov r0, r3 + 8009d46: f005 f89f bl 800ee88 + 8009d4a: 4601 mov r1, r0 + 8009d4c: 687b ldr r3, [r7, #4] + 8009d4e: 3304 adds r3, #4 + 8009d50: 461a mov r2, r3 + 8009d52: 4620 mov r0, r4 + 8009d54: f7ff f886 bl 8008e64 + 8009d58: 4603 mov r3, r0 + 8009d5a: 461a mov r2, r3 + 8009d5c: 687b ldr r3, [r7, #4] + 8009d5e: 865a strh r2, [r3, #50] ; 0x32 +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); + 8009d60: 687b ldr r3, [r7, #4] + 8009d62: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009d64: 009a lsls r2, r3, #2 + 8009d66: 687b ldr r3, [r7, #4] + 8009d68: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009d6a: 005b lsls r3, r3, #1 + 8009d6c: f241 111c movw r1, #4380 ; 0x111c + 8009d70: 428b cmp r3, r1 + 8009d72: bf38 it cc + 8009d74: 460b movcc r3, r1 + 8009d76: 429a cmp r2, r3 + 8009d78: d204 bcs.n 8009d84 + 8009d7a: 687b ldr r3, [r7, #4] + 8009d7c: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009d7e: 009b lsls r3, r3, #2 + 8009d80: b29b uxth r3, r3 + 8009d82: e00d b.n 8009da0 + 8009d84: 687b ldr r3, [r7, #4] + 8009d86: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009d88: 005b lsls r3, r3, #1 + 8009d8a: f241 121c movw r2, #4380 ; 0x111c + 8009d8e: 4293 cmp r3, r2 + 8009d90: d904 bls.n 8009d9c + 8009d92: 687b ldr r3, [r7, #4] + 8009d94: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009d96: 005b lsls r3, r3, #1 + 8009d98: b29b uxth r3, r3 + 8009d9a: e001 b.n 8009da0 + 8009d9c: f241 131c movw r3, #4380 ; 0x111c + 8009da0: 687a ldr r2, [r7, #4] + 8009da2: f8a2 3048 strh.w r3, [r2, #72] ; 0x48 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); + 8009da6: 687b ldr r3, [r7, #4] + 8009da8: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 8009dac: 2b00 cmp r3, #0 + 8009dae: d106 bne.n 8009dbe + 8009db0: 4b13 ldr r3, [pc, #76] ; (8009e00 ) + 8009db2: f44f 725b mov.w r2, #876 ; 0x36c + 8009db6: 491c ldr r1, [pc, #112] ; (8009e28 ) + 8009db8: 4813 ldr r0, [pc, #76] ; (8009e08 ) + 8009dba: f006 ff05 bl 8010bc8 + --pcb->snd_queuelen; + 8009dbe: 687b ldr r3, [r7, #4] + 8009dc0: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 8009dc4: 3b01 subs r3, #1 + 8009dc6: b29a uxth r2, r3 + 8009dc8: 687b ldr r3, [r7, #4] + 8009dca: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); + rseg = pcb->unacked; + 8009dce: 687b ldr r3, [r7, #4] + 8009dd0: 6f1b ldr r3, [r3, #112] ; 0x70 + 8009dd2: 617b str r3, [r7, #20] + if (rseg == NULL) { + 8009dd4: 697b ldr r3, [r7, #20] + 8009dd6: 2b00 cmp r3, #0 + 8009dd8: d12a bne.n 8009e30 + /* might happen if tcp_output fails in tcp_rexmit_rto() + in which case the segment is on the unsent list */ + rseg = pcb->unsent; + 8009dda: 687b ldr r3, [r7, #4] + 8009ddc: 6edb ldr r3, [r3, #108] ; 0x6c + 8009dde: 617b str r3, [r7, #20] + LWIP_ASSERT("no segment to free", rseg != NULL); + 8009de0: 697b ldr r3, [r7, #20] + 8009de2: 2b00 cmp r3, #0 + 8009de4: d106 bne.n 8009df4 + 8009de6: 4b06 ldr r3, [pc, #24] ; (8009e00 ) + 8009de8: f44f 725d mov.w r2, #884 ; 0x374 + 8009dec: 490f ldr r1, [pc, #60] ; (8009e2c ) + 8009dee: 4806 ldr r0, [pc, #24] ; (8009e08 ) + 8009df0: f006 feea bl 8010bc8 + pcb->unsent = rseg->next; + 8009df4: 697b ldr r3, [r7, #20] + 8009df6: 681a ldr r2, [r3, #0] + 8009df8: 687b ldr r3, [r7, #4] + 8009dfa: 66da str r2, [r3, #108] ; 0x6c + 8009dfc: e01c b.n 8009e38 + 8009dfe: bf00 nop + 8009e00: 08013198 .word 0x08013198 + 8009e04: 080133d0 .word 0x080133d0 + 8009e08: 080131e4 .word 0x080131e4 + 8009e0c: 24007bb4 .word 0x24007bb4 + 8009e10: 24007bac .word 0x24007bac + 8009e14: 24007ba8 .word 0x24007ba8 + 8009e18: 080133ec .word 0x080133ec + 8009e1c: 24007bb5 .word 0x24007bb5 + 8009e20: 24007b6c .word 0x24007b6c + 8009e24: 24007b98 .word 0x24007b98 + 8009e28: 0801340c .word 0x0801340c + 8009e2c: 08013424 .word 0x08013424 + } else { + pcb->unacked = rseg->next; + 8009e30: 697b ldr r3, [r7, #20] + 8009e32: 681a ldr r2, [r3, #0] + 8009e34: 687b ldr r3, [r7, #4] + 8009e36: 671a str r2, [r3, #112] ; 0x70 + } + tcp_seg_free(rseg); + 8009e38: 6978 ldr r0, [r7, #20] + 8009e3a: f7fe fc9c bl 8008776 + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if (pcb->unacked == NULL) { + 8009e3e: 687b ldr r3, [r7, #4] + 8009e40: 6f1b ldr r3, [r3, #112] ; 0x70 + 8009e42: 2b00 cmp r3, #0 + 8009e44: d104 bne.n 8009e50 + pcb->rtime = -1; + 8009e46: 687b ldr r3, [r7, #4] + 8009e48: f64f 72ff movw r2, #65535 ; 0xffff + 8009e4c: 861a strh r2, [r3, #48] ; 0x30 + 8009e4e: e006 b.n 8009e5e + } else { + pcb->rtime = 0; + 8009e50: 687b ldr r3, [r7, #4] + 8009e52: 2200 movs r2, #0 + 8009e54: 861a strh r2, [r3, #48] ; 0x30 + pcb->nrtx = 0; + 8009e56: 687b ldr r3, [r7, #4] + 8009e58: 2200 movs r2, #0 + 8009e5a: f883 2042 strb.w r2, [r3, #66] ; 0x42 + } + + /* Call the user specified function to call when successfully + * connected. */ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + 8009e5e: 687b ldr r3, [r7, #4] + 8009e60: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8009e64: 2b00 cmp r3, #0 + 8009e66: d00a beq.n 8009e7e + 8009e68: 687b ldr r3, [r7, #4] + 8009e6a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8009e6e: 687a ldr r2, [r7, #4] + 8009e70: 6910 ldr r0, [r2, #16] + 8009e72: 2200 movs r2, #0 + 8009e74: 6879 ldr r1, [r7, #4] + 8009e76: 4798 blx r3 + 8009e78: 4603 mov r3, r0 + 8009e7a: 77bb strb r3, [r7, #30] + 8009e7c: e001 b.n 8009e82 + 8009e7e: 2300 movs r3, #0 + 8009e80: 77bb strb r3, [r7, #30] + if (err == ERR_ABRT) { + 8009e82: f997 301e ldrsb.w r3, [r7, #30] + 8009e86: f113 0f0d cmn.w r3, #13 + 8009e8a: d102 bne.n 8009e92 + return ERR_ABRT; + 8009e8c: f06f 030c mvn.w r3, #12 + 8009e90: e250 b.n 800a334 + } + tcp_ack_now(pcb); + 8009e92: 687b ldr r3, [r7, #4] + 8009e94: 8b5b ldrh r3, [r3, #26] + 8009e96: f043 0302 orr.w r3, r3, #2 + 8009e9a: b29a uxth r2, r3 + 8009e9c: 687b ldr r3, [r7, #4] + 8009e9e: 835a strh r2, [r3, #26] + if (pcb->nrtx < TCP_SYNMAXRTX) { + pcb->rtime = 0; + tcp_rexmit_rto(pcb); + } + } + break; + 8009ea0: e23a b.n 800a318 + else if (flags & TCP_ACK) { + 8009ea2: 4b98 ldr r3, [pc, #608] ; (800a104 ) + 8009ea4: 781b ldrb r3, [r3, #0] + 8009ea6: f003 0310 and.w r3, r3, #16 + 8009eaa: 2b00 cmp r3, #0 + 8009eac: f000 8234 beq.w 800a318 + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009eb0: 4b95 ldr r3, [pc, #596] ; (800a108 ) + 8009eb2: 6819 ldr r1, [r3, #0] + 8009eb4: 4b95 ldr r3, [pc, #596] ; (800a10c ) + 8009eb6: 881b ldrh r3, [r3, #0] + 8009eb8: 461a mov r2, r3 + 8009eba: 4b95 ldr r3, [pc, #596] ; (800a110 ) + 8009ebc: 681b ldr r3, [r3, #0] + 8009ebe: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8009ec0: 4b94 ldr r3, [pc, #592] ; (800a114 ) + 8009ec2: 681b ldr r3, [r3, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009ec4: 885b ldrh r3, [r3, #2] + 8009ec6: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 8009ec8: 4a92 ldr r2, [pc, #584] ; (800a114 ) + 8009eca: 6812 ldr r2, [r2, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 8009ecc: 8812 ldrh r2, [r2, #0] + 8009ece: b292 uxth r2, r2 + 8009ed0: 9202 str r2, [sp, #8] + 8009ed2: 9301 str r3, [sp, #4] + 8009ed4: 4b90 ldr r3, [pc, #576] ; (800a118 ) + 8009ed6: 9300 str r3, [sp, #0] + 8009ed8: 4b90 ldr r3, [pc, #576] ; (800a11c ) + 8009eda: 4602 mov r2, r0 + 8009edc: 6878 ldr r0, [r7, #4] + 8009ede: f003 f949 bl 800d174 + if (pcb->nrtx < TCP_SYNMAXRTX) { + 8009ee2: 687b ldr r3, [r7, #4] + 8009ee4: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 8009ee8: 2b05 cmp r3, #5 + 8009eea: f200 8215 bhi.w 800a318 + pcb->rtime = 0; + 8009eee: 687b ldr r3, [r7, #4] + 8009ef0: 2200 movs r2, #0 + 8009ef2: 861a strh r2, [r3, #48] ; 0x30 + tcp_rexmit_rto(pcb); + 8009ef4: 6878 ldr r0, [r7, #4] + 8009ef6: f002 ff15 bl 800cd24 + break; + 8009efa: e20d b.n 800a318 + case SYN_RCVD: + if (flags & TCP_ACK) { + 8009efc: 4b81 ldr r3, [pc, #516] ; (800a104 ) + 8009efe: 781b ldrb r3, [r3, #0] + 8009f00: f003 0310 and.w r3, r3, #16 + 8009f04: 2b00 cmp r3, #0 + 8009f06: f000 80a1 beq.w 800a04c + /* expected ACK number? */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 8009f0a: 4b7f ldr r3, [pc, #508] ; (800a108 ) + 8009f0c: 681a ldr r2, [r3, #0] + 8009f0e: 687b ldr r3, [r7, #4] + 8009f10: 6c5b ldr r3, [r3, #68] ; 0x44 + 8009f12: 1ad3 subs r3, r2, r3 + 8009f14: 3b01 subs r3, #1 + 8009f16: 2b00 cmp r3, #0 + 8009f18: db7e blt.n 800a018 + 8009f1a: 4b7b ldr r3, [pc, #492] ; (800a108 ) + 8009f1c: 681a ldr r2, [r3, #0] + 8009f1e: 687b ldr r3, [r7, #4] + 8009f20: 6d1b ldr r3, [r3, #80] ; 0x50 + 8009f22: 1ad3 subs r3, r2, r3 + 8009f24: 2b00 cmp r3, #0 + 8009f26: dc77 bgt.n 800a018 + pcb->state = ESTABLISHED; + 8009f28: 687b ldr r3, [r7, #4] + 8009f2a: 2204 movs r2, #4 + 8009f2c: 751a strb r2, [r3, #20] + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + if (pcb->listener == NULL) { + 8009f2e: 687b ldr r3, [r7, #4] + 8009f30: 6fdb ldr r3, [r3, #124] ; 0x7c + 8009f32: 2b00 cmp r3, #0 + 8009f34: d102 bne.n 8009f3c + /* listen pcb might be closed by now */ + err = ERR_VAL; + 8009f36: 23fa movs r3, #250 ; 0xfa + 8009f38: 77bb strb r3, [r7, #30] + 8009f3a: e01d b.n 8009f78 + } else +#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ + { +#if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL); + 8009f3c: 687b ldr r3, [r7, #4] + 8009f3e: 6fdb ldr r3, [r3, #124] ; 0x7c + 8009f40: 699b ldr r3, [r3, #24] + 8009f42: 2b00 cmp r3, #0 + 8009f44: d106 bne.n 8009f54 + 8009f46: 4b76 ldr r3, [pc, #472] ; (800a120 ) + 8009f48: f44f 726a mov.w r2, #936 ; 0x3a8 + 8009f4c: 4975 ldr r1, [pc, #468] ; (800a124 ) + 8009f4e: 4876 ldr r0, [pc, #472] ; (800a128 ) + 8009f50: f006 fe3a bl 8010bc8 +#endif + tcp_backlog_accepted(pcb); + /* Call the accept function. */ + TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err); + 8009f54: 687b ldr r3, [r7, #4] + 8009f56: 6fdb ldr r3, [r3, #124] ; 0x7c + 8009f58: 699b ldr r3, [r3, #24] + 8009f5a: 2b00 cmp r3, #0 + 8009f5c: d00a beq.n 8009f74 + 8009f5e: 687b ldr r3, [r7, #4] + 8009f60: 6fdb ldr r3, [r3, #124] ; 0x7c + 8009f62: 699b ldr r3, [r3, #24] + 8009f64: 687a ldr r2, [r7, #4] + 8009f66: 6910 ldr r0, [r2, #16] + 8009f68: 2200 movs r2, #0 + 8009f6a: 6879 ldr r1, [r7, #4] + 8009f6c: 4798 blx r3 + 8009f6e: 4603 mov r3, r0 + 8009f70: 77bb strb r3, [r7, #30] + 8009f72: e001 b.n 8009f78 + 8009f74: 23f0 movs r3, #240 ; 0xf0 + 8009f76: 77bb strb r3, [r7, #30] + } + if (err != ERR_OK) { + 8009f78: f997 301e ldrsb.w r3, [r7, #30] + 8009f7c: 2b00 cmp r3, #0 + 8009f7e: d00a beq.n 8009f96 + /* If the accept function returns with an error, we abort + * the connection. */ + /* Already aborted? */ + if (err != ERR_ABRT) { + 8009f80: f997 301e ldrsb.w r3, [r7, #30] + 8009f84: f113 0f0d cmn.w r3, #13 + 8009f88: d002 beq.n 8009f90 + tcp_abort(pcb); + 8009f8a: 6878 ldr r0, [r7, #4] + 8009f8c: f7fd fdaa bl 8007ae4 + } + return ERR_ABRT; + 8009f90: f06f 030c mvn.w r3, #12 + 8009f94: e1ce b.n 800a334 + } + /* If there was any data contained within this ACK, + * we'd better pass it on to the application as well. */ + tcp_receive(pcb); + 8009f96: 6878 ldr r0, [r7, #4] + 8009f98: f000 fae0 bl 800a55c + + /* Prevent ACK for SYN to generate a sent event */ + if (recv_acked != 0) { + 8009f9c: 4b63 ldr r3, [pc, #396] ; (800a12c ) + 8009f9e: 881b ldrh r3, [r3, #0] + 8009fa0: 2b00 cmp r3, #0 + 8009fa2: d005 beq.n 8009fb0 + recv_acked--; + 8009fa4: 4b61 ldr r3, [pc, #388] ; (800a12c ) + 8009fa6: 881b ldrh r3, [r3, #0] + 8009fa8: 3b01 subs r3, #1 + 8009faa: b29a uxth r2, r3 + 8009fac: 4b5f ldr r3, [pc, #380] ; (800a12c ) + 8009fae: 801a strh r2, [r3, #0] + } + + pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); + 8009fb0: 687b ldr r3, [r7, #4] + 8009fb2: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009fb4: 009a lsls r2, r3, #2 + 8009fb6: 687b ldr r3, [r7, #4] + 8009fb8: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009fba: 005b lsls r3, r3, #1 + 8009fbc: f241 111c movw r1, #4380 ; 0x111c + 8009fc0: 428b cmp r3, r1 + 8009fc2: bf38 it cc + 8009fc4: 460b movcc r3, r1 + 8009fc6: 429a cmp r2, r3 + 8009fc8: d204 bcs.n 8009fd4 + 8009fca: 687b ldr r3, [r7, #4] + 8009fcc: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009fce: 009b lsls r3, r3, #2 + 8009fd0: b29b uxth r3, r3 + 8009fd2: e00d b.n 8009ff0 + 8009fd4: 687b ldr r3, [r7, #4] + 8009fd6: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009fd8: 005b lsls r3, r3, #1 + 8009fda: f241 121c movw r2, #4380 ; 0x111c + 8009fde: 4293 cmp r3, r2 + 8009fe0: d904 bls.n 8009fec + 8009fe2: 687b ldr r3, [r7, #4] + 8009fe4: 8e5b ldrh r3, [r3, #50] ; 0x32 + 8009fe6: 005b lsls r3, r3, #1 + 8009fe8: b29b uxth r3, r3 + 8009fea: e001 b.n 8009ff0 + 8009fec: f241 131c movw r3, #4380 ; 0x111c + 8009ff0: 687a ldr r2, [r7, #4] + 8009ff2: f8a2 3048 strh.w r3, [r2, #72] ; 0x48 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + + if (recv_flags & TF_GOT_FIN) { + 8009ff6: 4b4e ldr r3, [pc, #312] ; (800a130 ) + 8009ff8: 781b ldrb r3, [r3, #0] + 8009ffa: f003 0320 and.w r3, r3, #32 + 8009ffe: 2b00 cmp r3, #0 + 800a000: d037 beq.n 800a072 + tcp_ack_now(pcb); + 800a002: 687b ldr r3, [r7, #4] + 800a004: 8b5b ldrh r3, [r3, #26] + 800a006: f043 0302 orr.w r3, r3, #2 + 800a00a: b29a uxth r2, r3 + 800a00c: 687b ldr r3, [r7, #4] + 800a00e: 835a strh r2, [r3, #26] + pcb->state = CLOSE_WAIT; + 800a010: 687b ldr r3, [r7, #4] + 800a012: 2207 movs r2, #7 + 800a014: 751a strb r2, [r3, #20] + if (recv_flags & TF_GOT_FIN) { + 800a016: e02c b.n 800a072 + } + } else { + /* incorrect ACK number, send RST */ + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 800a018: 4b3b ldr r3, [pc, #236] ; (800a108 ) + 800a01a: 6819 ldr r1, [r3, #0] + 800a01c: 4b3b ldr r3, [pc, #236] ; (800a10c ) + 800a01e: 881b ldrh r3, [r3, #0] + 800a020: 461a mov r2, r3 + 800a022: 4b3b ldr r3, [pc, #236] ; (800a110 ) + 800a024: 681b ldr r3, [r3, #0] + 800a026: 18d0 adds r0, r2, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 800a028: 4b3a ldr r3, [pc, #232] ; (800a114 ) + 800a02a: 681b ldr r3, [r3, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 800a02c: 885b ldrh r3, [r3, #2] + 800a02e: b29b uxth r3, r3 + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + 800a030: 4a38 ldr r2, [pc, #224] ; (800a114 ) + 800a032: 6812 ldr r2, [r2, #0] + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + 800a034: 8812 ldrh r2, [r2, #0] + 800a036: b292 uxth r2, r2 + 800a038: 9202 str r2, [sp, #8] + 800a03a: 9301 str r3, [sp, #4] + 800a03c: 4b36 ldr r3, [pc, #216] ; (800a118 ) + 800a03e: 9300 str r3, [sp, #0] + 800a040: 4b36 ldr r3, [pc, #216] ; (800a11c ) + 800a042: 4602 mov r2, r0 + 800a044: 6878 ldr r0, [r7, #4] + 800a046: f003 f895 bl 800d174 + } + } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { + /* Looks like another copy of the SYN - retransmit our SYN-ACK */ + tcp_rexmit(pcb); + } + break; + 800a04a: e167 b.n 800a31c + } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { + 800a04c: 4b2d ldr r3, [pc, #180] ; (800a104 ) + 800a04e: 781b ldrb r3, [r3, #0] + 800a050: f003 0302 and.w r3, r3, #2 + 800a054: 2b00 cmp r3, #0 + 800a056: f000 8161 beq.w 800a31c + 800a05a: 687b ldr r3, [r7, #4] + 800a05c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800a05e: 1e5a subs r2, r3, #1 + 800a060: 4b2b ldr r3, [pc, #172] ; (800a110 ) + 800a062: 681b ldr r3, [r3, #0] + 800a064: 429a cmp r2, r3 + 800a066: f040 8159 bne.w 800a31c + tcp_rexmit(pcb); + 800a06a: 6878 ldr r0, [r7, #4] + 800a06c: f002 fe7c bl 800cd68 + break; + 800a070: e154 b.n 800a31c + 800a072: e153 b.n 800a31c + case CLOSE_WAIT: + /* FALLTHROUGH */ + case ESTABLISHED: + tcp_receive(pcb); + 800a074: 6878 ldr r0, [r7, #4] + 800a076: f000 fa71 bl 800a55c + if (recv_flags & TF_GOT_FIN) { /* passive close */ + 800a07a: 4b2d ldr r3, [pc, #180] ; (800a130 ) + 800a07c: 781b ldrb r3, [r3, #0] + 800a07e: f003 0320 and.w r3, r3, #32 + 800a082: 2b00 cmp r3, #0 + 800a084: f000 814c beq.w 800a320 + tcp_ack_now(pcb); + 800a088: 687b ldr r3, [r7, #4] + 800a08a: 8b5b ldrh r3, [r3, #26] + 800a08c: f043 0302 orr.w r3, r3, #2 + 800a090: b29a uxth r2, r3 + 800a092: 687b ldr r3, [r7, #4] + 800a094: 835a strh r2, [r3, #26] + pcb->state = CLOSE_WAIT; + 800a096: 687b ldr r3, [r7, #4] + 800a098: 2207 movs r2, #7 + 800a09a: 751a strb r2, [r3, #20] + } + break; + 800a09c: e140 b.n 800a320 + case FIN_WAIT_1: + tcp_receive(pcb); + 800a09e: 6878 ldr r0, [r7, #4] + 800a0a0: f000 fa5c bl 800a55c + if (recv_flags & TF_GOT_FIN) { + 800a0a4: 4b22 ldr r3, [pc, #136] ; (800a130 ) + 800a0a6: 781b ldrb r3, [r3, #0] + 800a0a8: f003 0320 and.w r3, r3, #32 + 800a0ac: 2b00 cmp r3, #0 + 800a0ae: d071 beq.n 800a194 + if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 800a0b0: 4b14 ldr r3, [pc, #80] ; (800a104 ) + 800a0b2: 781b ldrb r3, [r3, #0] + 800a0b4: f003 0310 and.w r3, r3, #16 + 800a0b8: 2b00 cmp r3, #0 + 800a0ba: d060 beq.n 800a17e + 800a0bc: 687b ldr r3, [r7, #4] + 800a0be: 6d1a ldr r2, [r3, #80] ; 0x50 + 800a0c0: 4b11 ldr r3, [pc, #68] ; (800a108 ) + 800a0c2: 681b ldr r3, [r3, #0] + 800a0c4: 429a cmp r2, r3 + 800a0c6: d15a bne.n 800a17e + pcb->unsent == NULL) { + 800a0c8: 687b ldr r3, [r7, #4] + 800a0ca: 6edb ldr r3, [r3, #108] ; 0x6c + if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 800a0cc: 2b00 cmp r3, #0 + 800a0ce: d156 bne.n 800a17e + LWIP_DEBUGF(TCP_DEBUG, + ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + 800a0d0: 687b ldr r3, [r7, #4] + 800a0d2: 8b5b ldrh r3, [r3, #26] + 800a0d4: f043 0302 orr.w r3, r3, #2 + 800a0d8: b29a uxth r2, r3 + 800a0da: 687b ldr r3, [r7, #4] + 800a0dc: 835a strh r2, [r3, #26] + tcp_pcb_purge(pcb); + 800a0de: 6878 ldr r0, [r7, #4] + 800a0e0: f7fe fdb6 bl 8008c50 + TCP_RMV_ACTIVE(pcb); + 800a0e4: 4b13 ldr r3, [pc, #76] ; (800a134 ) + 800a0e6: 681b ldr r3, [r3, #0] + 800a0e8: 687a ldr r2, [r7, #4] + 800a0ea: 429a cmp r2, r3 + 800a0ec: d105 bne.n 800a0fa + 800a0ee: 4b11 ldr r3, [pc, #68] ; (800a134 ) + 800a0f0: 681b ldr r3, [r3, #0] + 800a0f2: 68db ldr r3, [r3, #12] + 800a0f4: 4a0f ldr r2, [pc, #60] ; (800a134 ) + 800a0f6: 6013 str r3, [r2, #0] + 800a0f8: e02e b.n 800a158 + 800a0fa: 4b0e ldr r3, [pc, #56] ; (800a134 ) + 800a0fc: 681b ldr r3, [r3, #0] + 800a0fe: 613b str r3, [r7, #16] + 800a100: e027 b.n 800a152 + 800a102: bf00 nop + 800a104: 24007bb4 .word 0x24007bb4 + 800a108: 24007bac .word 0x24007bac + 800a10c: 24007bb2 .word 0x24007bb2 + 800a110: 24007ba8 .word 0x24007ba8 + 800a114: 24007b98 .word 0x24007b98 + 800a118: 24004c20 .word 0x24004c20 + 800a11c: 24004c24 .word 0x24004c24 + 800a120: 08013198 .word 0x08013198 + 800a124: 08013438 .word 0x08013438 + 800a128: 080131e4 .word 0x080131e4 + 800a12c: 24007bb0 .word 0x24007bb0 + 800a130: 24007bb5 .word 0x24007bb5 + 800a134: 24007b78 .word 0x24007b78 + 800a138: 693b ldr r3, [r7, #16] + 800a13a: 68db ldr r3, [r3, #12] + 800a13c: 687a ldr r2, [r7, #4] + 800a13e: 429a cmp r2, r3 + 800a140: d104 bne.n 800a14c + 800a142: 687b ldr r3, [r7, #4] + 800a144: 68da ldr r2, [r3, #12] + 800a146: 693b ldr r3, [r7, #16] + 800a148: 60da str r2, [r3, #12] + 800a14a: e005 b.n 800a158 + 800a14c: 693b ldr r3, [r7, #16] + 800a14e: 68db ldr r3, [r3, #12] + 800a150: 613b str r3, [r7, #16] + 800a152: 693b ldr r3, [r7, #16] + 800a154: 2b00 cmp r3, #0 + 800a156: d1ef bne.n 800a138 + 800a158: 687b ldr r3, [r7, #4] + 800a15a: 2200 movs r2, #0 + 800a15c: 60da str r2, [r3, #12] + 800a15e: 4b77 ldr r3, [pc, #476] ; (800a33c ) + 800a160: 2201 movs r2, #1 + 800a162: 701a strb r2, [r3, #0] + pcb->state = TIME_WAIT; + 800a164: 687b ldr r3, [r7, #4] + 800a166: 220a movs r2, #10 + 800a168: 751a strb r2, [r3, #20] + TCP_REG(&tcp_tw_pcbs, pcb); + 800a16a: 4b75 ldr r3, [pc, #468] ; (800a340 ) + 800a16c: 681a ldr r2, [r3, #0] + 800a16e: 687b ldr r3, [r7, #4] + 800a170: 60da str r2, [r3, #12] + 800a172: 4a73 ldr r2, [pc, #460] ; (800a340 ) + 800a174: 687b ldr r3, [r7, #4] + 800a176: 6013 str r3, [r2, #0] + 800a178: f003 f9be bl 800d4f8 + } + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + pcb->unsent == NULL) { + pcb->state = FIN_WAIT_2; + } + break; + 800a17c: e0d2 b.n 800a324 + tcp_ack_now(pcb); + 800a17e: 687b ldr r3, [r7, #4] + 800a180: 8b5b ldrh r3, [r3, #26] + 800a182: f043 0302 orr.w r3, r3, #2 + 800a186: b29a uxth r2, r3 + 800a188: 687b ldr r3, [r7, #4] + 800a18a: 835a strh r2, [r3, #26] + pcb->state = CLOSING; + 800a18c: 687b ldr r3, [r7, #4] + 800a18e: 2208 movs r2, #8 + 800a190: 751a strb r2, [r3, #20] + break; + 800a192: e0c7 b.n 800a324 + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 800a194: 4b6b ldr r3, [pc, #428] ; (800a344 ) + 800a196: 781b ldrb r3, [r3, #0] + 800a198: f003 0310 and.w r3, r3, #16 + 800a19c: 2b00 cmp r3, #0 + 800a19e: f000 80c1 beq.w 800a324 + 800a1a2: 687b ldr r3, [r7, #4] + 800a1a4: 6d1a ldr r2, [r3, #80] ; 0x50 + 800a1a6: 4b68 ldr r3, [pc, #416] ; (800a348 ) + 800a1a8: 681b ldr r3, [r3, #0] + 800a1aa: 429a cmp r2, r3 + 800a1ac: f040 80ba bne.w 800a324 + pcb->unsent == NULL) { + 800a1b0: 687b ldr r3, [r7, #4] + 800a1b2: 6edb ldr r3, [r3, #108] ; 0x6c + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + 800a1b4: 2b00 cmp r3, #0 + 800a1b6: f040 80b5 bne.w 800a324 + pcb->state = FIN_WAIT_2; + 800a1ba: 687b ldr r3, [r7, #4] + 800a1bc: 2206 movs r2, #6 + 800a1be: 751a strb r2, [r3, #20] + break; + 800a1c0: e0b0 b.n 800a324 + case FIN_WAIT_2: + tcp_receive(pcb); + 800a1c2: 6878 ldr r0, [r7, #4] + 800a1c4: f000 f9ca bl 800a55c + if (recv_flags & TF_GOT_FIN) { + 800a1c8: 4b60 ldr r3, [pc, #384] ; (800a34c ) + 800a1ca: 781b ldrb r3, [r3, #0] + 800a1cc: f003 0320 and.w r3, r3, #32 + 800a1d0: 2b00 cmp r3, #0 + 800a1d2: f000 80a9 beq.w 800a328 + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + 800a1d6: 687b ldr r3, [r7, #4] + 800a1d8: 8b5b ldrh r3, [r3, #26] + 800a1da: f043 0302 orr.w r3, r3, #2 + 800a1de: b29a uxth r2, r3 + 800a1e0: 687b ldr r3, [r7, #4] + 800a1e2: 835a strh r2, [r3, #26] + tcp_pcb_purge(pcb); + 800a1e4: 6878 ldr r0, [r7, #4] + 800a1e6: f7fe fd33 bl 8008c50 + TCP_RMV_ACTIVE(pcb); + 800a1ea: 4b59 ldr r3, [pc, #356] ; (800a350 ) + 800a1ec: 681b ldr r3, [r3, #0] + 800a1ee: 687a ldr r2, [r7, #4] + 800a1f0: 429a cmp r2, r3 + 800a1f2: d105 bne.n 800a200 + 800a1f4: 4b56 ldr r3, [pc, #344] ; (800a350 ) + 800a1f6: 681b ldr r3, [r3, #0] + 800a1f8: 68db ldr r3, [r3, #12] + 800a1fa: 4a55 ldr r2, [pc, #340] ; (800a350 ) + 800a1fc: 6013 str r3, [r2, #0] + 800a1fe: e013 b.n 800a228 + 800a200: 4b53 ldr r3, [pc, #332] ; (800a350 ) + 800a202: 681b ldr r3, [r3, #0] + 800a204: 60fb str r3, [r7, #12] + 800a206: e00c b.n 800a222 + 800a208: 68fb ldr r3, [r7, #12] + 800a20a: 68db ldr r3, [r3, #12] + 800a20c: 687a ldr r2, [r7, #4] + 800a20e: 429a cmp r2, r3 + 800a210: d104 bne.n 800a21c + 800a212: 687b ldr r3, [r7, #4] + 800a214: 68da ldr r2, [r3, #12] + 800a216: 68fb ldr r3, [r7, #12] + 800a218: 60da str r2, [r3, #12] + 800a21a: e005 b.n 800a228 + 800a21c: 68fb ldr r3, [r7, #12] + 800a21e: 68db ldr r3, [r3, #12] + 800a220: 60fb str r3, [r7, #12] + 800a222: 68fb ldr r3, [r7, #12] + 800a224: 2b00 cmp r3, #0 + 800a226: d1ef bne.n 800a208 + 800a228: 687b ldr r3, [r7, #4] + 800a22a: 2200 movs r2, #0 + 800a22c: 60da str r2, [r3, #12] + 800a22e: 4b43 ldr r3, [pc, #268] ; (800a33c ) + 800a230: 2201 movs r2, #1 + 800a232: 701a strb r2, [r3, #0] + pcb->state = TIME_WAIT; + 800a234: 687b ldr r3, [r7, #4] + 800a236: 220a movs r2, #10 + 800a238: 751a strb r2, [r3, #20] + TCP_REG(&tcp_tw_pcbs, pcb); + 800a23a: 4b41 ldr r3, [pc, #260] ; (800a340 ) + 800a23c: 681a ldr r2, [r3, #0] + 800a23e: 687b ldr r3, [r7, #4] + 800a240: 60da str r2, [r3, #12] + 800a242: 4a3f ldr r2, [pc, #252] ; (800a340 ) + 800a244: 687b ldr r3, [r7, #4] + 800a246: 6013 str r3, [r2, #0] + 800a248: f003 f956 bl 800d4f8 + } + break; + 800a24c: e06c b.n 800a328 + case CLOSING: + tcp_receive(pcb); + 800a24e: 6878 ldr r0, [r7, #4] + 800a250: f000 f984 bl 800a55c + if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { + 800a254: 4b3b ldr r3, [pc, #236] ; (800a344 ) + 800a256: 781b ldrb r3, [r3, #0] + 800a258: f003 0310 and.w r3, r3, #16 + 800a25c: 2b00 cmp r3, #0 + 800a25e: d065 beq.n 800a32c + 800a260: 687b ldr r3, [r7, #4] + 800a262: 6d1a ldr r2, [r3, #80] ; 0x50 + 800a264: 4b38 ldr r3, [pc, #224] ; (800a348 ) + 800a266: 681b ldr r3, [r3, #0] + 800a268: 429a cmp r2, r3 + 800a26a: d15f bne.n 800a32c + 800a26c: 687b ldr r3, [r7, #4] + 800a26e: 6edb ldr r3, [r3, #108] ; 0x6c + 800a270: 2b00 cmp r3, #0 + 800a272: d15b bne.n 800a32c + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_pcb_purge(pcb); + 800a274: 6878 ldr r0, [r7, #4] + 800a276: f7fe fceb bl 8008c50 + TCP_RMV_ACTIVE(pcb); + 800a27a: 4b35 ldr r3, [pc, #212] ; (800a350 ) + 800a27c: 681b ldr r3, [r3, #0] + 800a27e: 687a ldr r2, [r7, #4] + 800a280: 429a cmp r2, r3 + 800a282: d105 bne.n 800a290 + 800a284: 4b32 ldr r3, [pc, #200] ; (800a350 ) + 800a286: 681b ldr r3, [r3, #0] + 800a288: 68db ldr r3, [r3, #12] + 800a28a: 4a31 ldr r2, [pc, #196] ; (800a350 ) + 800a28c: 6013 str r3, [r2, #0] + 800a28e: e013 b.n 800a2b8 + 800a290: 4b2f ldr r3, [pc, #188] ; (800a350 ) + 800a292: 681b ldr r3, [r3, #0] + 800a294: 61bb str r3, [r7, #24] + 800a296: e00c b.n 800a2b2 + 800a298: 69bb ldr r3, [r7, #24] + 800a29a: 68db ldr r3, [r3, #12] + 800a29c: 687a ldr r2, [r7, #4] + 800a29e: 429a cmp r2, r3 + 800a2a0: d104 bne.n 800a2ac + 800a2a2: 687b ldr r3, [r7, #4] + 800a2a4: 68da ldr r2, [r3, #12] + 800a2a6: 69bb ldr r3, [r7, #24] + 800a2a8: 60da str r2, [r3, #12] + 800a2aa: e005 b.n 800a2b8 + 800a2ac: 69bb ldr r3, [r7, #24] + 800a2ae: 68db ldr r3, [r3, #12] + 800a2b0: 61bb str r3, [r7, #24] + 800a2b2: 69bb ldr r3, [r7, #24] + 800a2b4: 2b00 cmp r3, #0 + 800a2b6: d1ef bne.n 800a298 + 800a2b8: 687b ldr r3, [r7, #4] + 800a2ba: 2200 movs r2, #0 + 800a2bc: 60da str r2, [r3, #12] + 800a2be: 4b1f ldr r3, [pc, #124] ; (800a33c ) + 800a2c0: 2201 movs r2, #1 + 800a2c2: 701a strb r2, [r3, #0] + pcb->state = TIME_WAIT; + 800a2c4: 687b ldr r3, [r7, #4] + 800a2c6: 220a movs r2, #10 + 800a2c8: 751a strb r2, [r3, #20] + TCP_REG(&tcp_tw_pcbs, pcb); + 800a2ca: 4b1d ldr r3, [pc, #116] ; (800a340 ) + 800a2cc: 681a ldr r2, [r3, #0] + 800a2ce: 687b ldr r3, [r7, #4] + 800a2d0: 60da str r2, [r3, #12] + 800a2d2: 4a1b ldr r2, [pc, #108] ; (800a340 ) + 800a2d4: 687b ldr r3, [r7, #4] + 800a2d6: 6013 str r3, [r2, #0] + 800a2d8: f003 f90e bl 800d4f8 + } + break; + 800a2dc: e026 b.n 800a32c + case LAST_ACK: + tcp_receive(pcb); + 800a2de: 6878 ldr r0, [r7, #4] + 800a2e0: f000 f93c bl 800a55c + if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { + 800a2e4: 4b17 ldr r3, [pc, #92] ; (800a344 ) + 800a2e6: 781b ldrb r3, [r3, #0] + 800a2e8: f003 0310 and.w r3, r3, #16 + 800a2ec: 2b00 cmp r3, #0 + 800a2ee: d01f beq.n 800a330 + 800a2f0: 687b ldr r3, [r7, #4] + 800a2f2: 6d1a ldr r2, [r3, #80] ; 0x50 + 800a2f4: 4b14 ldr r3, [pc, #80] ; (800a348 ) + 800a2f6: 681b ldr r3, [r3, #0] + 800a2f8: 429a cmp r2, r3 + 800a2fa: d119 bne.n 800a330 + 800a2fc: 687b ldr r3, [r7, #4] + 800a2fe: 6edb ldr r3, [r3, #108] ; 0x6c + 800a300: 2b00 cmp r3, #0 + 800a302: d115 bne.n 800a330 + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ + recv_flags |= TF_CLOSED; + 800a304: 4b11 ldr r3, [pc, #68] ; (800a34c ) + 800a306: 781b ldrb r3, [r3, #0] + 800a308: f043 0310 orr.w r3, r3, #16 + 800a30c: b2da uxtb r2, r3 + 800a30e: 4b0f ldr r3, [pc, #60] ; (800a34c ) + 800a310: 701a strb r2, [r3, #0] + } + break; + 800a312: e00d b.n 800a330 + default: + break; + 800a314: bf00 nop + 800a316: e00c b.n 800a332 + break; + 800a318: bf00 nop + 800a31a: e00a b.n 800a332 + break; + 800a31c: bf00 nop + 800a31e: e008 b.n 800a332 + break; + 800a320: bf00 nop + 800a322: e006 b.n 800a332 + break; + 800a324: bf00 nop + 800a326: e004 b.n 800a332 + break; + 800a328: bf00 nop + 800a32a: e002 b.n 800a332 + break; + 800a32c: bf00 nop + 800a32e: e000 b.n 800a332 + break; + 800a330: bf00 nop + } + return ERR_OK; + 800a332: 2300 movs r3, #0 +} + 800a334: 4618 mov r0, r3 + 800a336: 3724 adds r7, #36 ; 0x24 + 800a338: 46bd mov sp, r7 + 800a33a: bd90 pop {r4, r7, pc} + 800a33c: 24007b80 .word 0x24007b80 + 800a340: 24007b7c .word 0x24007b7c + 800a344: 24007bb4 .word 0x24007bb4 + 800a348: 24007bac .word 0x24007bac + 800a34c: 24007bb5 .word 0x24007bb5 + 800a350: 24007b78 .word 0x24007b78 + +0800a354 : + * + * Called from tcp_receive() + */ +static void +tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) +{ + 800a354: b590 push {r4, r7, lr} + 800a356: b085 sub sp, #20 + 800a358: af00 add r7, sp, #0 + 800a35a: 6078 str r0, [r7, #4] + 800a35c: 6039 str r1, [r7, #0] + struct tcp_seg *old_seg; + + LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL); + 800a35e: 687b ldr r3, [r7, #4] + 800a360: 2b00 cmp r3, #0 + 800a362: d106 bne.n 800a372 + 800a364: 4b3b ldr r3, [pc, #236] ; (800a454 ) + 800a366: f240 421f movw r2, #1055 ; 0x41f + 800a36a: 493b ldr r1, [pc, #236] ; (800a458 ) + 800a36c: 483b ldr r0, [pc, #236] ; (800a45c ) + 800a36e: f006 fc2b bl 8010bc8 + + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + 800a372: 687b ldr r3, [r7, #4] + 800a374: 691b ldr r3, [r3, #16] + 800a376: 899b ldrh r3, [r3, #12] + 800a378: b29b uxth r3, r3 + 800a37a: 4618 mov r0, r3 + 800a37c: f7fb f8e6 bl 800554c + 800a380: 4603 mov r3, r0 + 800a382: b2db uxtb r3, r3 + 800a384: f003 0301 and.w r3, r3, #1 + 800a388: 2b00 cmp r3, #0 + 800a38a: d028 beq.n 800a3de + /* received segment overlaps all following segments */ + tcp_segs_free(next); + 800a38c: 6838 ldr r0, [r7, #0] + 800a38e: f7fe f9dd bl 800874c + next = NULL; + 800a392: 2300 movs r3, #0 + 800a394: 603b str r3, [r7, #0] + 800a396: e056 b.n 800a446 + oos queue may have segments with FIN flag */ + while (next && + TCP_SEQ_GEQ((seqno + cseg->len), + (next->tcphdr->seqno + next->len))) { + /* cseg with FIN already processed */ + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + 800a398: 683b ldr r3, [r7, #0] + 800a39a: 691b ldr r3, [r3, #16] + 800a39c: 899b ldrh r3, [r3, #12] + 800a39e: b29b uxth r3, r3 + 800a3a0: 4618 mov r0, r3 + 800a3a2: f7fb f8d3 bl 800554c + 800a3a6: 4603 mov r3, r0 + 800a3a8: b2db uxtb r3, r3 + 800a3aa: f003 0301 and.w r3, r3, #1 + 800a3ae: 2b00 cmp r3, #0 + 800a3b0: d00d beq.n 800a3ce + TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN); + 800a3b2: 687b ldr r3, [r7, #4] + 800a3b4: 691b ldr r3, [r3, #16] + 800a3b6: 899b ldrh r3, [r3, #12] + 800a3b8: b29c uxth r4, r3 + 800a3ba: 2001 movs r0, #1 + 800a3bc: f7fb f8c6 bl 800554c + 800a3c0: 4603 mov r3, r0 + 800a3c2: 461a mov r2, r3 + 800a3c4: 687b ldr r3, [r7, #4] + 800a3c6: 691b ldr r3, [r3, #16] + 800a3c8: 4322 orrs r2, r4 + 800a3ca: b292 uxth r2, r2 + 800a3cc: 819a strh r2, [r3, #12] + } + old_seg = next; + 800a3ce: 683b ldr r3, [r7, #0] + 800a3d0: 60fb str r3, [r7, #12] + next = next->next; + 800a3d2: 683b ldr r3, [r7, #0] + 800a3d4: 681b ldr r3, [r3, #0] + 800a3d6: 603b str r3, [r7, #0] + tcp_seg_free(old_seg); + 800a3d8: 68f8 ldr r0, [r7, #12] + 800a3da: f7fe f9cc bl 8008776 + while (next && + 800a3de: 683b ldr r3, [r7, #0] + 800a3e0: 2b00 cmp r3, #0 + 800a3e2: d00e beq.n 800a402 + TCP_SEQ_GEQ((seqno + cseg->len), + 800a3e4: 687b ldr r3, [r7, #4] + 800a3e6: 891b ldrh r3, [r3, #8] + 800a3e8: 461a mov r2, r3 + 800a3ea: 4b1d ldr r3, [pc, #116] ; (800a460 ) + 800a3ec: 681b ldr r3, [r3, #0] + 800a3ee: 441a add r2, r3 + 800a3f0: 683b ldr r3, [r7, #0] + 800a3f2: 691b ldr r3, [r3, #16] + 800a3f4: 685b ldr r3, [r3, #4] + 800a3f6: 6839 ldr r1, [r7, #0] + 800a3f8: 8909 ldrh r1, [r1, #8] + 800a3fa: 440b add r3, r1 + 800a3fc: 1ad3 subs r3, r2, r3 + while (next && + 800a3fe: 2b00 cmp r3, #0 + 800a400: daca bge.n 800a398 + } + if (next && + 800a402: 683b ldr r3, [r7, #0] + 800a404: 2b00 cmp r3, #0 + 800a406: d01e beq.n 800a446 + TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { + 800a408: 687b ldr r3, [r7, #4] + 800a40a: 891b ldrh r3, [r3, #8] + 800a40c: 461a mov r2, r3 + 800a40e: 4b14 ldr r3, [pc, #80] ; (800a460 ) + 800a410: 681b ldr r3, [r3, #0] + 800a412: 441a add r2, r3 + 800a414: 683b ldr r3, [r7, #0] + 800a416: 691b ldr r3, [r3, #16] + 800a418: 685b ldr r3, [r3, #4] + 800a41a: 1ad3 subs r3, r2, r3 + if (next && + 800a41c: 2b00 cmp r3, #0 + 800a41e: dd12 ble.n 800a446 + /* We need to trim the incoming segment. */ + cseg->len = (u16_t)(next->tcphdr->seqno - seqno); + 800a420: 683b ldr r3, [r7, #0] + 800a422: 691b ldr r3, [r3, #16] + 800a424: 685b ldr r3, [r3, #4] + 800a426: b29a uxth r2, r3 + 800a428: 4b0d ldr r3, [pc, #52] ; (800a460 ) + 800a42a: 681b ldr r3, [r3, #0] + 800a42c: b29b uxth r3, r3 + 800a42e: 1ad3 subs r3, r2, r3 + 800a430: b29a uxth r2, r3 + 800a432: 687b ldr r3, [r7, #4] + 800a434: 811a strh r2, [r3, #8] + pbuf_realloc(cseg->p, cseg->len); + 800a436: 687b ldr r3, [r7, #4] + 800a438: 685a ldr r2, [r3, #4] + 800a43a: 687b ldr r3, [r7, #4] + 800a43c: 891b ldrh r3, [r3, #8] + 800a43e: 4619 mov r1, r3 + 800a440: 4610 mov r0, r2 + 800a442: f7fc fc41 bl 8006cc8 + } + } + cseg->next = next; + 800a446: 687b ldr r3, [r7, #4] + 800a448: 683a ldr r2, [r7, #0] + 800a44a: 601a str r2, [r3, #0] +} + 800a44c: bf00 nop + 800a44e: 3714 adds r7, #20 + 800a450: 46bd mov sp, r7 + 800a452: bd90 pop {r4, r7, pc} + 800a454: 08013198 .word 0x08013198 + 800a458: 08013458 .word 0x08013458 + 800a45c: 080131e4 .word 0x080131e4 + 800a460: 24007ba8 .word 0x24007ba8 + +0800a464 : + +/** Remove segments from a list if the incoming ACK acknowledges them */ +static struct tcp_seg * +tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name, + struct tcp_seg *dbg_other_seg_list) +{ + 800a464: b5b0 push {r4, r5, r7, lr} + 800a466: b086 sub sp, #24 + 800a468: af00 add r7, sp, #0 + 800a46a: 60f8 str r0, [r7, #12] + 800a46c: 60b9 str r1, [r7, #8] + 800a46e: 607a str r2, [r7, #4] + 800a470: 603b str r3, [r7, #0] + u16_t clen; + + LWIP_UNUSED_ARG(dbg_list_name); + LWIP_UNUSED_ARG(dbg_other_seg_list); + + while (seg_list != NULL && + 800a472: e03e b.n 800a4f2 + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n", + lwip_ntohl(seg_list->tcphdr->seqno), + lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list), + dbg_list_name)); + + next = seg_list; + 800a474: 68bb ldr r3, [r7, #8] + 800a476: 617b str r3, [r7, #20] + seg_list = seg_list->next; + 800a478: 68bb ldr r3, [r7, #8] + 800a47a: 681b ldr r3, [r3, #0] + 800a47c: 60bb str r3, [r7, #8] + + clen = pbuf_clen(next->p); + 800a47e: 697b ldr r3, [r7, #20] + 800a480: 685b ldr r3, [r3, #4] + 800a482: 4618 mov r0, r3 + 800a484: f7fc fe2e bl 80070e4 + 800a488: 4603 mov r3, r0 + 800a48a: 827b strh r3, [r7, #18] + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ", + (tcpwnd_size_t)pcb->snd_queuelen)); + LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen)); + 800a48c: 68fb ldr r3, [r7, #12] + 800a48e: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800a492: 8a7a ldrh r2, [r7, #18] + 800a494: 429a cmp r2, r3 + 800a496: d906 bls.n 800a4a6 + 800a498: 4b2a ldr r3, [pc, #168] ; (800a544 ) + 800a49a: f240 4257 movw r2, #1111 ; 0x457 + 800a49e: 492a ldr r1, [pc, #168] ; (800a548 ) + 800a4a0: 482a ldr r0, [pc, #168] ; (800a54c ) + 800a4a2: f006 fb91 bl 8010bc8 + + pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen); + 800a4a6: 68fb ldr r3, [r7, #12] + 800a4a8: f8b3 2066 ldrh.w r2, [r3, #102] ; 0x66 + 800a4ac: 8a7b ldrh r3, [r7, #18] + 800a4ae: 1ad3 subs r3, r2, r3 + 800a4b0: b29a uxth r2, r3 + 800a4b2: 68fb ldr r3, [r7, #12] + 800a4b4: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + recv_acked = (tcpwnd_size_t)(recv_acked + next->len); + 800a4b8: 697b ldr r3, [r7, #20] + 800a4ba: 891a ldrh r2, [r3, #8] + 800a4bc: 4b24 ldr r3, [pc, #144] ; (800a550 ) + 800a4be: 881b ldrh r3, [r3, #0] + 800a4c0: 4413 add r3, r2 + 800a4c2: b29a uxth r2, r3 + 800a4c4: 4b22 ldr r3, [pc, #136] ; (800a550 ) + 800a4c6: 801a strh r2, [r3, #0] + tcp_seg_free(next); + 800a4c8: 6978 ldr r0, [r7, #20] + 800a4ca: f7fe f954 bl 8008776 + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n", + (tcpwnd_size_t)pcb->snd_queuelen, + dbg_list_name)); + if (pcb->snd_queuelen != 0) { + 800a4ce: 68fb ldr r3, [r7, #12] + 800a4d0: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800a4d4: 2b00 cmp r3, #0 + 800a4d6: d00c beq.n 800a4f2 + LWIP_ASSERT("tcp_receive: valid queue length", + 800a4d8: 68bb ldr r3, [r7, #8] + 800a4da: 2b00 cmp r3, #0 + 800a4dc: d109 bne.n 800a4f2 + 800a4de: 683b ldr r3, [r7, #0] + 800a4e0: 2b00 cmp r3, #0 + 800a4e2: d106 bne.n 800a4f2 + 800a4e4: 4b17 ldr r3, [pc, #92] ; (800a544 ) + 800a4e6: f240 4261 movw r2, #1121 ; 0x461 + 800a4ea: 491a ldr r1, [pc, #104] ; (800a554 ) + 800a4ec: 4817 ldr r0, [pc, #92] ; (800a54c ) + 800a4ee: f006 fb6b bl 8010bc8 + while (seg_list != NULL && + 800a4f2: 68bb ldr r3, [r7, #8] + 800a4f4: 2b00 cmp r3, #0 + 800a4f6: d020 beq.n 800a53a + TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) + + 800a4f8: 68bb ldr r3, [r7, #8] + 800a4fa: 691b ldr r3, [r3, #16] + 800a4fc: 685b ldr r3, [r3, #4] + 800a4fe: 4618 mov r0, r3 + 800a500: f7fb f839 bl 8005576 + 800a504: 4604 mov r4, r0 + 800a506: 68bb ldr r3, [r7, #8] + 800a508: 891b ldrh r3, [r3, #8] + 800a50a: 461d mov r5, r3 + 800a50c: 68bb ldr r3, [r7, #8] + 800a50e: 691b ldr r3, [r3, #16] + 800a510: 899b ldrh r3, [r3, #12] + 800a512: b29b uxth r3, r3 + 800a514: 4618 mov r0, r3 + 800a516: f7fb f819 bl 800554c + 800a51a: 4603 mov r3, r0 + 800a51c: b2db uxtb r3, r3 + 800a51e: f003 0303 and.w r3, r3, #3 + 800a522: 2b00 cmp r3, #0 + 800a524: d001 beq.n 800a52a + 800a526: 2301 movs r3, #1 + 800a528: e000 b.n 800a52c + 800a52a: 2300 movs r3, #0 + 800a52c: 442b add r3, r5 + 800a52e: 18e2 adds r2, r4, r3 + 800a530: 4b09 ldr r3, [pc, #36] ; (800a558 ) + 800a532: 681b ldr r3, [r3, #0] + 800a534: 1ad3 subs r3, r2, r3 + while (seg_list != NULL && + 800a536: 2b00 cmp r3, #0 + 800a538: dd9c ble.n 800a474 + seg_list != NULL || dbg_other_seg_list != NULL); + } + } + return seg_list; + 800a53a: 68bb ldr r3, [r7, #8] +} + 800a53c: 4618 mov r0, r3 + 800a53e: 3718 adds r7, #24 + 800a540: 46bd mov sp, r7 + 800a542: bdb0 pop {r4, r5, r7, pc} + 800a544: 08013198 .word 0x08013198 + 800a548: 08013480 .word 0x08013480 + 800a54c: 080131e4 .word 0x080131e4 + 800a550: 24007bb0 .word 0x24007bb0 + 800a554: 080134a8 .word 0x080134a8 + 800a558: 24007bac .word 0x24007bac + +0800a55c : + * + * Called from tcp_process(). + */ +static void +tcp_receive(struct tcp_pcb *pcb) +{ + 800a55c: b5b0 push {r4, r5, r7, lr} + 800a55e: b094 sub sp, #80 ; 0x50 + 800a560: af00 add r7, sp, #0 + 800a562: 6078 str r0, [r7, #4] + s16_t m; + u32_t right_wnd_edge; + int found_dupack = 0; + 800a564: 2300 movs r3, #0 + 800a566: 64bb str r3, [r7, #72] ; 0x48 + + LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL); + 800a568: 687b ldr r3, [r7, #4] + 800a56a: 2b00 cmp r3, #0 + 800a56c: d106 bne.n 800a57c + 800a56e: 4b91 ldr r3, [pc, #580] ; (800a7b4 ) + 800a570: f240 427b movw r2, #1147 ; 0x47b + 800a574: 4990 ldr r1, [pc, #576] ; (800a7b8 ) + 800a576: 4891 ldr r0, [pc, #580] ; (800a7bc ) + 800a578: f006 fb26 bl 8010bc8 + LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED); + 800a57c: 687b ldr r3, [r7, #4] + 800a57e: 7d1b ldrb r3, [r3, #20] + 800a580: 2b03 cmp r3, #3 + 800a582: d806 bhi.n 800a592 + 800a584: 4b8b ldr r3, [pc, #556] ; (800a7b4 ) + 800a586: f240 427c movw r2, #1148 ; 0x47c + 800a58a: 498d ldr r1, [pc, #564] ; (800a7c0 ) + 800a58c: 488b ldr r0, [pc, #556] ; (800a7bc ) + 800a58e: f006 fb1b bl 8010bc8 + + if (flags & TCP_ACK) { + 800a592: 4b8c ldr r3, [pc, #560] ; (800a7c4 ) + 800a594: 781b ldrb r3, [r3, #0] + 800a596: f003 0310 and.w r3, r3, #16 + 800a59a: 2b00 cmp r3, #0 + 800a59c: f000 8264 beq.w 800aa68 + right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; + 800a5a0: 687b ldr r3, [r7, #4] + 800a5a2: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800a5a6: 461a mov r2, r3 + 800a5a8: 687b ldr r3, [r7, #4] + 800a5aa: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a5ac: 4413 add r3, r2 + 800a5ae: 633b str r3, [r7, #48] ; 0x30 + + /* Update window. */ + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + 800a5b0: 687b ldr r3, [r7, #4] + 800a5b2: 6d5a ldr r2, [r3, #84] ; 0x54 + 800a5b4: 4b84 ldr r3, [pc, #528] ; (800a7c8 ) + 800a5b6: 681b ldr r3, [r3, #0] + 800a5b8: 1ad3 subs r3, r2, r3 + 800a5ba: 2b00 cmp r3, #0 + 800a5bc: db1b blt.n 800a5f6 + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + 800a5be: 687b ldr r3, [r7, #4] + 800a5c0: 6d5a ldr r2, [r3, #84] ; 0x54 + 800a5c2: 4b81 ldr r3, [pc, #516] ; (800a7c8 ) + 800a5c4: 681b ldr r3, [r3, #0] + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + 800a5c6: 429a cmp r2, r3 + 800a5c8: d106 bne.n 800a5d8 + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + 800a5ca: 687b ldr r3, [r7, #4] + 800a5cc: 6d9a ldr r2, [r3, #88] ; 0x58 + 800a5ce: 4b7f ldr r3, [pc, #508] ; (800a7cc ) + 800a5d0: 681b ldr r3, [r3, #0] + 800a5d2: 1ad3 subs r3, r2, r3 + 800a5d4: 2b00 cmp r3, #0 + 800a5d6: db0e blt.n 800a5f6 + (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { + 800a5d8: 687b ldr r3, [r7, #4] + 800a5da: 6d9a ldr r2, [r3, #88] ; 0x58 + 800a5dc: 4b7b ldr r3, [pc, #492] ; (800a7cc ) + 800a5de: 681b ldr r3, [r3, #0] + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + 800a5e0: 429a cmp r2, r3 + 800a5e2: d125 bne.n 800a630 + (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { + 800a5e4: 4b7a ldr r3, [pc, #488] ; (800a7d0 ) + 800a5e6: 681b ldr r3, [r3, #0] + 800a5e8: 89db ldrh r3, [r3, #14] + 800a5ea: b29a uxth r2, r3 + 800a5ec: 687b ldr r3, [r7, #4] + 800a5ee: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800a5f2: 429a cmp r2, r3 + 800a5f4: d91c bls.n 800a630 + pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd); + 800a5f6: 4b76 ldr r3, [pc, #472] ; (800a7d0 ) + 800a5f8: 681b ldr r3, [r3, #0] + 800a5fa: 89db ldrh r3, [r3, #14] + 800a5fc: b29a uxth r2, r3 + 800a5fe: 687b ldr r3, [r7, #4] + 800a600: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + /* keep track of the biggest window announced by the remote host to calculate + the maximum segment size */ + if (pcb->snd_wnd_max < pcb->snd_wnd) { + 800a604: 687b ldr r3, [r7, #4] + 800a606: f8b3 2062 ldrh.w r2, [r3, #98] ; 0x62 + 800a60a: 687b ldr r3, [r7, #4] + 800a60c: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800a610: 429a cmp r2, r3 + 800a612: d205 bcs.n 800a620 + pcb->snd_wnd_max = pcb->snd_wnd; + 800a614: 687b ldr r3, [r7, #4] + 800a616: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 800a61a: 687b ldr r3, [r7, #4] + 800a61c: f8a3 2062 strh.w r2, [r3, #98] ; 0x62 + } + pcb->snd_wl1 = seqno; + 800a620: 4b69 ldr r3, [pc, #420] ; (800a7c8 ) + 800a622: 681a ldr r2, [r3, #0] + 800a624: 687b ldr r3, [r7, #4] + 800a626: 655a str r2, [r3, #84] ; 0x54 + pcb->snd_wl2 = ackno; + 800a628: 4b68 ldr r3, [pc, #416] ; (800a7cc ) + 800a62a: 681a ldr r2, [r3, #0] + 800a62c: 687b ldr r3, [r7, #4] + 800a62e: 659a str r2, [r3, #88] ; 0x58 + * If it only passes 1, should reset dupack counter + * + */ + + /* Clause 1 */ + if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { + 800a630: 4b66 ldr r3, [pc, #408] ; (800a7cc ) + 800a632: 681a ldr r2, [r3, #0] + 800a634: 687b ldr r3, [r7, #4] + 800a636: 6c5b ldr r3, [r3, #68] ; 0x44 + 800a638: 1ad3 subs r3, r2, r3 + 800a63a: 2b00 cmp r3, #0 + 800a63c: dc58 bgt.n 800a6f0 + /* Clause 2 */ + if (tcplen == 0) { + 800a63e: 4b65 ldr r3, [pc, #404] ; (800a7d4 ) + 800a640: 881b ldrh r3, [r3, #0] + 800a642: 2b00 cmp r3, #0 + 800a644: d14b bne.n 800a6de + /* Clause 3 */ + if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) { + 800a646: 687b ldr r3, [r7, #4] + 800a648: 6d9b ldr r3, [r3, #88] ; 0x58 + 800a64a: 687a ldr r2, [r7, #4] + 800a64c: f8b2 2060 ldrh.w r2, [r2, #96] ; 0x60 + 800a650: 4413 add r3, r2 + 800a652: 6b3a ldr r2, [r7, #48] ; 0x30 + 800a654: 429a cmp r2, r3 + 800a656: d142 bne.n 800a6de + /* Clause 4 */ + if (pcb->rtime >= 0) { + 800a658: 687b ldr r3, [r7, #4] + 800a65a: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 800a65e: 2b00 cmp r3, #0 + 800a660: db3d blt.n 800a6de + /* Clause 5 */ + if (pcb->lastack == ackno) { + 800a662: 687b ldr r3, [r7, #4] + 800a664: 6c5a ldr r2, [r3, #68] ; 0x44 + 800a666: 4b59 ldr r3, [pc, #356] ; (800a7cc ) + 800a668: 681b ldr r3, [r3, #0] + 800a66a: 429a cmp r2, r3 + 800a66c: d137 bne.n 800a6de + found_dupack = 1; + 800a66e: 2301 movs r3, #1 + 800a670: 64bb str r3, [r7, #72] ; 0x48 + if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) { + 800a672: 687b ldr r3, [r7, #4] + 800a674: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 800a678: 2bff cmp r3, #255 ; 0xff + 800a67a: d007 beq.n 800a68c + ++pcb->dupacks; + 800a67c: 687b ldr r3, [r7, #4] + 800a67e: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 800a682: 3301 adds r3, #1 + 800a684: b2da uxtb r2, r3 + 800a686: 687b ldr r3, [r7, #4] + 800a688: f883 2043 strb.w r2, [r3, #67] ; 0x43 + } + if (pcb->dupacks > 3) { + 800a68c: 687b ldr r3, [r7, #4] + 800a68e: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 800a692: 2b03 cmp r3, #3 + 800a694: d91b bls.n 800a6ce + /* Inflate the congestion window */ + TCP_WND_INC(pcb->cwnd, pcb->mss); + 800a696: 687b ldr r3, [r7, #4] + 800a698: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800a69c: 687b ldr r3, [r7, #4] + 800a69e: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800a6a0: 4413 add r3, r2 + 800a6a2: b29a uxth r2, r3 + 800a6a4: 687b ldr r3, [r7, #4] + 800a6a6: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 800a6aa: 429a cmp r2, r3 + 800a6ac: d30a bcc.n 800a6c4 + 800a6ae: 687b ldr r3, [r7, #4] + 800a6b0: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800a6b4: 687b ldr r3, [r7, #4] + 800a6b6: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800a6b8: 4413 add r3, r2 + 800a6ba: b29a uxth r2, r3 + 800a6bc: 687b ldr r3, [r7, #4] + 800a6be: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 800a6c2: e004 b.n 800a6ce + 800a6c4: 687b ldr r3, [r7, #4] + 800a6c6: f64f 72ff movw r2, #65535 ; 0xffff + 800a6ca: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + } + if (pcb->dupacks >= 3) { + 800a6ce: 687b ldr r3, [r7, #4] + 800a6d0: f893 3043 ldrb.w r3, [r3, #67] ; 0x43 + 800a6d4: 2b02 cmp r3, #2 + 800a6d6: d902 bls.n 800a6de + /* Do fast retransmit (checked via TF_INFR, not via dupacks count) */ + tcp_rexmit_fast(pcb); + 800a6d8: 6878 ldr r0, [r7, #4] + 800a6da: f002 fbb1 bl 800ce40 + } + } + } + /* If Clause (1) or more is true, but not a duplicate ack, reset + * count of consecutive duplicate acks */ + if (!found_dupack) { + 800a6de: 6cbb ldr r3, [r7, #72] ; 0x48 + 800a6e0: 2b00 cmp r3, #0 + 800a6e2: f040 8161 bne.w 800a9a8 + pcb->dupacks = 0; + 800a6e6: 687b ldr r3, [r7, #4] + 800a6e8: 2200 movs r2, #0 + 800a6ea: f883 2043 strb.w r2, [r3, #67] ; 0x43 + 800a6ee: e15b b.n 800a9a8 + } + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 800a6f0: 4b36 ldr r3, [pc, #216] ; (800a7cc ) + 800a6f2: 681a ldr r2, [r3, #0] + 800a6f4: 687b ldr r3, [r7, #4] + 800a6f6: 6c5b ldr r3, [r3, #68] ; 0x44 + 800a6f8: 1ad3 subs r3, r2, r3 + 800a6fa: 3b01 subs r3, #1 + 800a6fc: 2b00 cmp r3, #0 + 800a6fe: f2c0 814e blt.w 800a99e + 800a702: 4b32 ldr r3, [pc, #200] ; (800a7cc ) + 800a704: 681a ldr r2, [r3, #0] + 800a706: 687b ldr r3, [r7, #4] + 800a708: 6d1b ldr r3, [r3, #80] ; 0x50 + 800a70a: 1ad3 subs r3, r2, r3 + 800a70c: 2b00 cmp r3, #0 + 800a70e: f300 8146 bgt.w 800a99e + tcpwnd_size_t acked; + + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { + 800a712: 687b ldr r3, [r7, #4] + 800a714: 8b5b ldrh r3, [r3, #26] + 800a716: f003 0304 and.w r3, r3, #4 + 800a71a: 2b00 cmp r3, #0 + 800a71c: d010 beq.n 800a740 + tcp_clear_flags(pcb, TF_INFR); + 800a71e: 687b ldr r3, [r7, #4] + 800a720: 8b5b ldrh r3, [r3, #26] + 800a722: f023 0304 bic.w r3, r3, #4 + 800a726: b29a uxth r2, r3 + 800a728: 687b ldr r3, [r7, #4] + 800a72a: 835a strh r2, [r3, #26] + pcb->cwnd = pcb->ssthresh; + 800a72c: 687b ldr r3, [r7, #4] + 800a72e: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a + 800a732: 687b ldr r3, [r7, #4] + 800a734: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + pcb->bytes_acked = 0; + 800a738: 687b ldr r3, [r7, #4] + 800a73a: 2200 movs r2, #0 + 800a73c: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + } + + /* Reset the number of retransmissions. */ + pcb->nrtx = 0; + 800a740: 687b ldr r3, [r7, #4] + 800a742: 2200 movs r2, #0 + 800a744: f883 2042 strb.w r2, [r3, #66] ; 0x42 + + /* Reset the retransmission time-out. */ + pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); + 800a748: 687b ldr r3, [r7, #4] + 800a74a: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 800a74e: 10db asrs r3, r3, #3 + 800a750: b21b sxth r3, r3 + 800a752: b29a uxth r2, r3 + 800a754: 687b ldr r3, [r7, #4] + 800a756: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 800a75a: b29b uxth r3, r3 + 800a75c: 4413 add r3, r2 + 800a75e: b29b uxth r3, r3 + 800a760: b21a sxth r2, r3 + 800a762: 687b ldr r3, [r7, #4] + 800a764: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + /* Record how much data this ACK acks */ + acked = (tcpwnd_size_t)(ackno - pcb->lastack); + 800a768: 4b18 ldr r3, [pc, #96] ; (800a7cc ) + 800a76a: 681b ldr r3, [r3, #0] + 800a76c: b29a uxth r2, r3 + 800a76e: 687b ldr r3, [r7, #4] + 800a770: 6c5b ldr r3, [r3, #68] ; 0x44 + 800a772: b29b uxth r3, r3 + 800a774: 1ad3 subs r3, r2, r3 + 800a776: 85fb strh r3, [r7, #46] ; 0x2e + + /* Reset the fast retransmit variables. */ + pcb->dupacks = 0; + 800a778: 687b ldr r3, [r7, #4] + 800a77a: 2200 movs r2, #0 + 800a77c: f883 2043 strb.w r2, [r3, #67] ; 0x43 + pcb->lastack = ackno; + 800a780: 4b12 ldr r3, [pc, #72] ; (800a7cc ) + 800a782: 681a ldr r2, [r3, #0] + 800a784: 687b ldr r3, [r7, #4] + 800a786: 645a str r2, [r3, #68] ; 0x44 + + /* Update the congestion control variables (cwnd and + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + 800a788: 687b ldr r3, [r7, #4] + 800a78a: 7d1b ldrb r3, [r3, #20] + 800a78c: 2b03 cmp r3, #3 + 800a78e: f240 8097 bls.w 800a8c0 + if (pcb->cwnd < pcb->ssthresh) { + 800a792: 687b ldr r3, [r7, #4] + 800a794: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800a798: 687b ldr r3, [r7, #4] + 800a79a: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a + 800a79e: 429a cmp r2, r3 + 800a7a0: d245 bcs.n 800a82e + tcpwnd_size_t increase; + /* limit to 1 SMSS segment during period following RTO */ + u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2; + 800a7a2: 687b ldr r3, [r7, #4] + 800a7a4: 8b5b ldrh r3, [r3, #26] + 800a7a6: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800a7aa: 2b00 cmp r3, #0 + 800a7ac: d014 beq.n 800a7d8 + 800a7ae: 2301 movs r3, #1 + 800a7b0: e013 b.n 800a7da + 800a7b2: bf00 nop + 800a7b4: 08013198 .word 0x08013198 + 800a7b8: 080134c8 .word 0x080134c8 + 800a7bc: 080131e4 .word 0x080131e4 + 800a7c0: 080134e4 .word 0x080134e4 + 800a7c4: 24007bb4 .word 0x24007bb4 + 800a7c8: 24007ba8 .word 0x24007ba8 + 800a7cc: 24007bac .word 0x24007bac + 800a7d0: 24007b98 .word 0x24007b98 + 800a7d4: 24007bb2 .word 0x24007bb2 + 800a7d8: 2302 movs r3, #2 + 800a7da: f887 302d strb.w r3, [r7, #45] ; 0x2d + /* RFC 3465, section 2.2 Slow Start */ + increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss)); + 800a7de: f897 302d ldrb.w r3, [r7, #45] ; 0x2d + 800a7e2: b29a uxth r2, r3 + 800a7e4: 687b ldr r3, [r7, #4] + 800a7e6: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800a7e8: fb12 f303 smulbb r3, r2, r3 + 800a7ec: b29b uxth r3, r3 + 800a7ee: 8dfa ldrh r2, [r7, #46] ; 0x2e + 800a7f0: 4293 cmp r3, r2 + 800a7f2: bf28 it cs + 800a7f4: 4613 movcs r3, r2 + 800a7f6: 857b strh r3, [r7, #42] ; 0x2a + TCP_WND_INC(pcb->cwnd, increase); + 800a7f8: 687b ldr r3, [r7, #4] + 800a7fa: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800a7fe: 8d7b ldrh r3, [r7, #42] ; 0x2a + 800a800: 4413 add r3, r2 + 800a802: b29a uxth r2, r3 + 800a804: 687b ldr r3, [r7, #4] + 800a806: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 800a80a: 429a cmp r2, r3 + 800a80c: d309 bcc.n 800a822 + 800a80e: 687b ldr r3, [r7, #4] + 800a810: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800a814: 8d7b ldrh r3, [r7, #42] ; 0x2a + 800a816: 4413 add r3, r2 + 800a818: b29a uxth r2, r3 + 800a81a: 687b ldr r3, [r7, #4] + 800a81c: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 800a820: e04e b.n 800a8c0 + 800a822: 687b ldr r3, [r7, #4] + 800a824: f64f 72ff movw r2, #65535 ; 0xffff + 800a828: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 800a82c: e048 b.n 800a8c0 + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd)); + } else { + /* RFC 3465, section 2.1 Congestion Avoidance */ + TCP_WND_INC(pcb->bytes_acked, acked); + 800a82e: 687b ldr r3, [r7, #4] + 800a830: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 800a834: 8dfb ldrh r3, [r7, #46] ; 0x2e + 800a836: 4413 add r3, r2 + 800a838: b29a uxth r2, r3 + 800a83a: 687b ldr r3, [r7, #4] + 800a83c: f8b3 306a ldrh.w r3, [r3, #106] ; 0x6a + 800a840: 429a cmp r2, r3 + 800a842: d309 bcc.n 800a858 + 800a844: 687b ldr r3, [r7, #4] + 800a846: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 800a84a: 8dfb ldrh r3, [r7, #46] ; 0x2e + 800a84c: 4413 add r3, r2 + 800a84e: b29a uxth r2, r3 + 800a850: 687b ldr r3, [r7, #4] + 800a852: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + 800a856: e004 b.n 800a862 + 800a858: 687b ldr r3, [r7, #4] + 800a85a: f64f 72ff movw r2, #65535 ; 0xffff + 800a85e: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + if (pcb->bytes_acked >= pcb->cwnd) { + 800a862: 687b ldr r3, [r7, #4] + 800a864: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 800a868: 687b ldr r3, [r7, #4] + 800a86a: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 800a86e: 429a cmp r2, r3 + 800a870: d326 bcc.n 800a8c0 + pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd); + 800a872: 687b ldr r3, [r7, #4] + 800a874: f8b3 206a ldrh.w r2, [r3, #106] ; 0x6a + 800a878: 687b ldr r3, [r7, #4] + 800a87a: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 800a87e: 1ad3 subs r3, r2, r3 + 800a880: b29a uxth r2, r3 + 800a882: 687b ldr r3, [r7, #4] + 800a884: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + TCP_WND_INC(pcb->cwnd, pcb->mss); + 800a888: 687b ldr r3, [r7, #4] + 800a88a: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800a88e: 687b ldr r3, [r7, #4] + 800a890: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800a892: 4413 add r3, r2 + 800a894: b29a uxth r2, r3 + 800a896: 687b ldr r3, [r7, #4] + 800a898: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 800a89c: 429a cmp r2, r3 + 800a89e: d30a bcc.n 800a8b6 + 800a8a0: 687b ldr r3, [r7, #4] + 800a8a2: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800a8a6: 687b ldr r3, [r7, #4] + 800a8a8: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800a8aa: 4413 add r3, r2 + 800a8ac: b29a uxth r2, r3 + 800a8ae: 687b ldr r3, [r7, #4] + 800a8b0: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + 800a8b4: e004 b.n 800a8c0 + 800a8b6: 687b ldr r3, [r7, #4] + 800a8b8: f64f 72ff movw r2, #65535 ; 0xffff + 800a8bc: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + pcb->unacked != NULL ? + lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0)); + + /* Remove segment from the unacknowledged list if the incoming + ACK acknowledges them. */ + pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent); + 800a8c0: 687b ldr r3, [r7, #4] + 800a8c2: 6f19 ldr r1, [r3, #112] ; 0x70 + 800a8c4: 687b ldr r3, [r7, #4] + 800a8c6: 6edb ldr r3, [r3, #108] ; 0x6c + 800a8c8: 4a98 ldr r2, [pc, #608] ; (800ab2c ) + 800a8ca: 6878 ldr r0, [r7, #4] + 800a8cc: f7ff fdca bl 800a464 + 800a8d0: 4602 mov r2, r0 + 800a8d2: 687b ldr r3, [r7, #4] + 800a8d4: 671a str r2, [r3, #112] ; 0x70 + on the list are acknowledged by the ACK. This may seem + strange since an "unsent" segment shouldn't be acked. The + rationale is that lwIP puts all outstanding segments on the + ->unsent list after a retransmission, so these segments may + in fact have been sent once. */ + pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked); + 800a8d6: 687b ldr r3, [r7, #4] + 800a8d8: 6ed9 ldr r1, [r3, #108] ; 0x6c + 800a8da: 687b ldr r3, [r7, #4] + 800a8dc: 6f1b ldr r3, [r3, #112] ; 0x70 + 800a8de: 4a94 ldr r2, [pc, #592] ; (800ab30 ) + 800a8e0: 6878 ldr r0, [r7, #4] + 800a8e2: f7ff fdbf bl 800a464 + 800a8e6: 4602 mov r2, r0 + 800a8e8: 687b ldr r3, [r7, #4] + 800a8ea: 66da str r2, [r3, #108] ; 0x6c + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if (pcb->unacked == NULL) { + 800a8ec: 687b ldr r3, [r7, #4] + 800a8ee: 6f1b ldr r3, [r3, #112] ; 0x70 + 800a8f0: 2b00 cmp r3, #0 + 800a8f2: d104 bne.n 800a8fe + pcb->rtime = -1; + 800a8f4: 687b ldr r3, [r7, #4] + 800a8f6: f64f 72ff movw r2, #65535 ; 0xffff + 800a8fa: 861a strh r2, [r3, #48] ; 0x30 + 800a8fc: e002 b.n 800a904 + } else { + pcb->rtime = 0; + 800a8fe: 687b ldr r3, [r7, #4] + 800a900: 2200 movs r2, #0 + 800a902: 861a strh r2, [r3, #48] ; 0x30 + } + + pcb->polltmr = 0; + 800a904: 687b ldr r3, [r7, #4] + 800a906: 2200 movs r2, #0 + 800a908: 771a strb r2, [r3, #28] + +#if TCP_OVERSIZE + if (pcb->unsent == NULL) { + 800a90a: 687b ldr r3, [r7, #4] + 800a90c: 6edb ldr r3, [r3, #108] ; 0x6c + 800a90e: 2b00 cmp r3, #0 + 800a910: d103 bne.n 800a91a + pcb->unsent_oversize = 0; + 800a912: 687b ldr r3, [r7, #4] + 800a914: 2200 movs r2, #0 + 800a916: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + /* Inform neighbor reachability of forward progress. */ + nd6_reachability_hint(ip6_current_src_addr()); + } +#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/ + + pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked); + 800a91a: 687b ldr r3, [r7, #4] + 800a91c: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64 + 800a920: 4b84 ldr r3, [pc, #528] ; (800ab34 ) + 800a922: 881b ldrh r3, [r3, #0] + 800a924: 4413 add r3, r2 + 800a926: b29a uxth r2, r3 + 800a928: 687b ldr r3, [r7, #4] + 800a92a: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 + /* check if this ACK ends our retransmission of in-flight data */ + if (pcb->flags & TF_RTO) { + 800a92e: 687b ldr r3, [r7, #4] + 800a930: 8b5b ldrh r3, [r3, #26] + 800a932: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800a936: 2b00 cmp r3, #0 + 800a938: d035 beq.n 800a9a6 + /* RTO is done if + 1) both queues are empty or + 2) unacked is empty and unsent head contains data not part of RTO or + 3) unacked head contains data not part of RTO */ + if (pcb->unacked == NULL) { + 800a93a: 687b ldr r3, [r7, #4] + 800a93c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800a93e: 2b00 cmp r3, #0 + 800a940: d118 bne.n 800a974 + if ((pcb->unsent == NULL) || + 800a942: 687b ldr r3, [r7, #4] + 800a944: 6edb ldr r3, [r3, #108] ; 0x6c + 800a946: 2b00 cmp r3, #0 + 800a948: d00c beq.n 800a964 + (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) { + 800a94a: 687b ldr r3, [r7, #4] + 800a94c: 6cdc ldr r4, [r3, #76] ; 0x4c + 800a94e: 687b ldr r3, [r7, #4] + 800a950: 6edb ldr r3, [r3, #108] ; 0x6c + 800a952: 691b ldr r3, [r3, #16] + 800a954: 685b ldr r3, [r3, #4] + 800a956: 4618 mov r0, r3 + 800a958: f7fa fe0d bl 8005576 + 800a95c: 4603 mov r3, r0 + 800a95e: 1ae3 subs r3, r4, r3 + if ((pcb->unsent == NULL) || + 800a960: 2b00 cmp r3, #0 + 800a962: dc20 bgt.n 800a9a6 + tcp_clear_flags(pcb, TF_RTO); + 800a964: 687b ldr r3, [r7, #4] + 800a966: 8b5b ldrh r3, [r3, #26] + 800a968: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 800a96c: b29a uxth r2, r3 + 800a96e: 687b ldr r3, [r7, #4] + 800a970: 835a strh r2, [r3, #26] + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 800a972: e018 b.n 800a9a6 + } + } else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) { + 800a974: 687b ldr r3, [r7, #4] + 800a976: 6cdc ldr r4, [r3, #76] ; 0x4c + 800a978: 687b ldr r3, [r7, #4] + 800a97a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800a97c: 691b ldr r3, [r3, #16] + 800a97e: 685b ldr r3, [r3, #4] + 800a980: 4618 mov r0, r3 + 800a982: f7fa fdf8 bl 8005576 + 800a986: 4603 mov r3, r0 + 800a988: 1ae3 subs r3, r4, r3 + 800a98a: 2b00 cmp r3, #0 + 800a98c: dc0b bgt.n 800a9a6 + tcp_clear_flags(pcb, TF_RTO); + 800a98e: 687b ldr r3, [r7, #4] + 800a990: 8b5b ldrh r3, [r3, #26] + 800a992: f423 6300 bic.w r3, r3, #2048 ; 0x800 + 800a996: b29a uxth r2, r3 + 800a998: 687b ldr r3, [r7, #4] + 800a99a: 835a strh r2, [r3, #26] + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 800a99c: e003 b.n 800a9a6 + } + } + /* End of ACK for new data processing. */ + } else { + /* Out of sequence ACK, didn't really ack anything */ + tcp_send_empty_ack(pcb); + 800a99e: 6878 ldr r0, [r7, #4] + 800a9a0: f002 fc3a bl 800d218 + 800a9a4: e000 b.n 800a9a8 + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + 800a9a6: bf00 nop + pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a + round-trip time measurement. */ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + 800a9a8: 687b ldr r3, [r7, #4] + 800a9aa: 6b5b ldr r3, [r3, #52] ; 0x34 + 800a9ac: 2b00 cmp r3, #0 + 800a9ae: d05b beq.n 800aa68 + 800a9b0: 687b ldr r3, [r7, #4] + 800a9b2: 6b9a ldr r2, [r3, #56] ; 0x38 + 800a9b4: 4b60 ldr r3, [pc, #384] ; (800ab38 ) + 800a9b6: 681b ldr r3, [r3, #0] + 800a9b8: 1ad3 subs r3, r2, r3 + 800a9ba: 2b00 cmp r3, #0 + 800a9bc: da54 bge.n 800aa68 + /* diff between this shouldn't exceed 32K since this are tcp timer ticks + and a round-trip shouldn't be that long... */ + m = (s16_t)(tcp_ticks - pcb->rttest); + 800a9be: 4b5f ldr r3, [pc, #380] ; (800ab3c ) + 800a9c0: 681b ldr r3, [r3, #0] + 800a9c2: b29a uxth r2, r3 + 800a9c4: 687b ldr r3, [r7, #4] + 800a9c6: 6b5b ldr r3, [r3, #52] ; 0x34 + 800a9c8: b29b uxth r3, r3 + 800a9ca: 1ad3 subs r3, r2, r3 + 800a9cc: b29b uxth r3, r3 + 800a9ce: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", + m, (u16_t)(m * TCP_SLOW_INTERVAL))); + + /* This is taken directly from VJs original code in his paper */ + m = (s16_t)(m - (pcb->sa >> 3)); + 800a9d2: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e + 800a9d6: 687b ldr r3, [r7, #4] + 800a9d8: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 800a9dc: 10db asrs r3, r3, #3 + 800a9de: b21b sxth r3, r3 + 800a9e0: b29b uxth r3, r3 + 800a9e2: 1ad3 subs r3, r2, r3 + 800a9e4: b29b uxth r3, r3 + 800a9e6: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + pcb->sa = (s16_t)(pcb->sa + m); + 800a9ea: 687b ldr r3, [r7, #4] + 800a9ec: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 800a9f0: b29a uxth r2, r3 + 800a9f2: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 800a9f6: 4413 add r3, r2 + 800a9f8: b29b uxth r3, r3 + 800a9fa: b21a sxth r2, r3 + 800a9fc: 687b ldr r3, [r7, #4] + 800a9fe: 879a strh r2, [r3, #60] ; 0x3c + if (m < 0) { + 800aa00: f9b7 304e ldrsh.w r3, [r7, #78] ; 0x4e + 800aa04: 2b00 cmp r3, #0 + 800aa06: da05 bge.n 800aa14 + m = (s16_t) - m; + 800aa08: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 800aa0c: 425b negs r3, r3 + 800aa0e: b29b uxth r3, r3 + 800aa10: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + } + m = (s16_t)(m - (pcb->sv >> 2)); + 800aa14: f8b7 204e ldrh.w r2, [r7, #78] ; 0x4e + 800aa18: 687b ldr r3, [r7, #4] + 800aa1a: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 800aa1e: 109b asrs r3, r3, #2 + 800aa20: b21b sxth r3, r3 + 800aa22: b29b uxth r3, r3 + 800aa24: 1ad3 subs r3, r2, r3 + 800aa26: b29b uxth r3, r3 + 800aa28: f8a7 304e strh.w r3, [r7, #78] ; 0x4e + pcb->sv = (s16_t)(pcb->sv + m); + 800aa2c: 687b ldr r3, [r7, #4] + 800aa2e: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 800aa32: b29a uxth r2, r3 + 800aa34: f8b7 304e ldrh.w r3, [r7, #78] ; 0x4e + 800aa38: 4413 add r3, r2 + 800aa3a: b29b uxth r3, r3 + 800aa3c: b21a sxth r2, r3 + 800aa3e: 687b ldr r3, [r7, #4] + 800aa40: 87da strh r2, [r3, #62] ; 0x3e + pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); + 800aa42: 687b ldr r3, [r7, #4] + 800aa44: f9b3 303c ldrsh.w r3, [r3, #60] ; 0x3c + 800aa48: 10db asrs r3, r3, #3 + 800aa4a: b21b sxth r3, r3 + 800aa4c: b29a uxth r2, r3 + 800aa4e: 687b ldr r3, [r7, #4] + 800aa50: f9b3 303e ldrsh.w r3, [r3, #62] ; 0x3e + 800aa54: b29b uxth r3, r3 + 800aa56: 4413 add r3, r2 + 800aa58: b29b uxth r3, r3 + 800aa5a: b21a sxth r2, r3 + 800aa5c: 687b ldr r3, [r7, #4] + 800aa5e: f8a3 2040 strh.w r2, [r3, #64] ; 0x40 + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", + pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL))); + + pcb->rttest = 0; + 800aa62: 687b ldr r3, [r7, #4] + 800aa64: 2200 movs r2, #0 + 800aa66: 635a str r2, [r3, #52] ; 0x34 + + /* If the incoming segment contains data, we must process it + further unless the pcb already received a FIN. + (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING, + LAST-ACK and TIME-WAIT: "Ignore the segment text.") */ + if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) { + 800aa68: 4b35 ldr r3, [pc, #212] ; (800ab40 ) + 800aa6a: 881b ldrh r3, [r3, #0] + 800aa6c: 2b00 cmp r3, #0 + 800aa6e: f000 84e2 beq.w 800b436 + 800aa72: 687b ldr r3, [r7, #4] + 800aa74: 7d1b ldrb r3, [r3, #20] + 800aa76: 2b06 cmp r3, #6 + 800aa78: f200 84dd bhi.w 800b436 + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ + /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { + if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { + 800aa7c: 687b ldr r3, [r7, #4] + 800aa7e: 6a5a ldr r2, [r3, #36] ; 0x24 + 800aa80: 4b30 ldr r3, [pc, #192] ; (800ab44 ) + 800aa82: 681b ldr r3, [r3, #0] + 800aa84: 1ad3 subs r3, r2, r3 + 800aa86: 3b01 subs r3, #1 + 800aa88: 2b00 cmp r3, #0 + 800aa8a: f2c0 808f blt.w 800abac + 800aa8e: 687b ldr r3, [r7, #4] + 800aa90: 6a5a ldr r2, [r3, #36] ; 0x24 + 800aa92: 4b2b ldr r3, [pc, #172] ; (800ab40 ) + 800aa94: 881b ldrh r3, [r3, #0] + 800aa96: 4619 mov r1, r3 + 800aa98: 4b2a ldr r3, [pc, #168] ; (800ab44 ) + 800aa9a: 681b ldr r3, [r3, #0] + 800aa9c: 440b add r3, r1 + 800aa9e: 1ad3 subs r3, r2, r3 + 800aaa0: 3301 adds r3, #1 + 800aaa2: 2b00 cmp r3, #0 + 800aaa4: f300 8082 bgt.w 800abac + + After we are done with adjusting the pbuf pointers we must + adjust the ->data pointer in the seg and the segment + length.*/ + + struct pbuf *p = inseg.p; + 800aaa8: 4b27 ldr r3, [pc, #156] ; (800ab48 ) + 800aaaa: 685b ldr r3, [r3, #4] + 800aaac: 647b str r3, [r7, #68] ; 0x44 + u32_t off32 = pcb->rcv_nxt - seqno; + 800aaae: 687b ldr r3, [r7, #4] + 800aab0: 6a5a ldr r2, [r3, #36] ; 0x24 + 800aab2: 4b24 ldr r3, [pc, #144] ; (800ab44 ) + 800aab4: 681b ldr r3, [r3, #0] + 800aab6: 1ad3 subs r3, r2, r3 + 800aab8: 627b str r3, [r7, #36] ; 0x24 + u16_t new_tot_len, off; + LWIP_ASSERT("inseg.p != NULL", inseg.p); + 800aaba: 4b23 ldr r3, [pc, #140] ; (800ab48 ) + 800aabc: 685b ldr r3, [r3, #4] + 800aabe: 2b00 cmp r3, #0 + 800aac0: d106 bne.n 800aad0 + 800aac2: 4b22 ldr r3, [pc, #136] ; (800ab4c ) + 800aac4: f240 5294 movw r2, #1428 ; 0x594 + 800aac8: 4921 ldr r1, [pc, #132] ; (800ab50 ) + 800aaca: 4822 ldr r0, [pc, #136] ; (800ab54 ) + 800aacc: f006 f87c bl 8010bc8 + LWIP_ASSERT("insane offset!", (off32 < 0xffff)); + 800aad0: 6a7b ldr r3, [r7, #36] ; 0x24 + 800aad2: f64f 72fe movw r2, #65534 ; 0xfffe + 800aad6: 4293 cmp r3, r2 + 800aad8: d906 bls.n 800aae8 + 800aada: 4b1c ldr r3, [pc, #112] ; (800ab4c ) + 800aadc: f240 5295 movw r2, #1429 ; 0x595 + 800aae0: 491d ldr r1, [pc, #116] ; (800ab58 ) + 800aae2: 481c ldr r0, [pc, #112] ; (800ab54 ) + 800aae4: f006 f870 bl 8010bc8 + off = (u16_t)off32; + 800aae8: 6a7b ldr r3, [r7, #36] ; 0x24 + 800aaea: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); + 800aaee: 4b16 ldr r3, [pc, #88] ; (800ab48 ) + 800aaf0: 685b ldr r3, [r3, #4] + 800aaf2: 891b ldrh r3, [r3, #8] + 800aaf4: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 800aaf8: 429a cmp r2, r3 + 800aafa: d906 bls.n 800ab0a + 800aafc: 4b13 ldr r3, [pc, #76] ; (800ab4c ) + 800aafe: f240 5297 movw r2, #1431 ; 0x597 + 800ab02: 4916 ldr r1, [pc, #88] ; (800ab5c ) + 800ab04: 4813 ldr r0, [pc, #76] ; (800ab54 ) + 800ab06: f006 f85f bl 8010bc8 + inseg.len -= off; + 800ab0a: 4b0f ldr r3, [pc, #60] ; (800ab48 ) + 800ab0c: 891a ldrh r2, [r3, #8] + 800ab0e: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 800ab12: 1ad3 subs r3, r2, r3 + 800ab14: b29a uxth r2, r3 + 800ab16: 4b0c ldr r3, [pc, #48] ; (800ab48 ) + 800ab18: 811a strh r2, [r3, #8] + new_tot_len = (u16_t)(inseg.p->tot_len - off); + 800ab1a: 4b0b ldr r3, [pc, #44] ; (800ab48 ) + 800ab1c: 685b ldr r3, [r3, #4] + 800ab1e: 891a ldrh r2, [r3, #8] + 800ab20: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 800ab24: 1ad3 subs r3, r2, r3 + 800ab26: 847b strh r3, [r7, #34] ; 0x22 + while (p->len < off) { + 800ab28: e02a b.n 800ab80 + 800ab2a: bf00 nop + 800ab2c: 08013500 .word 0x08013500 + 800ab30: 08013508 .word 0x08013508 + 800ab34: 24007bb0 .word 0x24007bb0 + 800ab38: 24007bac .word 0x24007bac + 800ab3c: 24007b6c .word 0x24007b6c + 800ab40: 24007bb2 .word 0x24007bb2 + 800ab44: 24007ba8 .word 0x24007ba8 + 800ab48: 24007b84 .word 0x24007b84 + 800ab4c: 08013198 .word 0x08013198 + 800ab50: 08013510 .word 0x08013510 + 800ab54: 080131e4 .word 0x080131e4 + 800ab58: 08013520 .word 0x08013520 + 800ab5c: 08013530 .word 0x08013530 + off -= p->len; + 800ab60: 6c7b ldr r3, [r7, #68] ; 0x44 + 800ab62: 895b ldrh r3, [r3, #10] + 800ab64: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 800ab68: 1ad3 subs r3, r2, r3 + 800ab6a: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + /* all pbufs up to and including this one have len==0, so tot_len is equal */ + p->tot_len = new_tot_len; + 800ab6e: 6c7b ldr r3, [r7, #68] ; 0x44 + 800ab70: 8c7a ldrh r2, [r7, #34] ; 0x22 + 800ab72: 811a strh r2, [r3, #8] + p->len = 0; + 800ab74: 6c7b ldr r3, [r7, #68] ; 0x44 + 800ab76: 2200 movs r2, #0 + 800ab78: 815a strh r2, [r3, #10] + p = p->next; + 800ab7a: 6c7b ldr r3, [r7, #68] ; 0x44 + 800ab7c: 681b ldr r3, [r3, #0] + 800ab7e: 647b str r3, [r7, #68] ; 0x44 + while (p->len < off) { + 800ab80: 6c7b ldr r3, [r7, #68] ; 0x44 + 800ab82: 895b ldrh r3, [r3, #10] + 800ab84: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 800ab88: 429a cmp r2, r3 + 800ab8a: d8e9 bhi.n 800ab60 + } + /* cannot fail... */ + pbuf_remove_header(p, off); + 800ab8c: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 800ab90: 4619 mov r1, r3 + 800ab92: 6c78 ldr r0, [r7, #68] ; 0x44 + 800ab94: f7fc f998 bl 8006ec8 + inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; + 800ab98: 687b ldr r3, [r7, #4] + 800ab9a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800ab9c: 4a91 ldr r2, [pc, #580] ; (800ade4 ) + 800ab9e: 6013 str r3, [r2, #0] + 800aba0: 4b91 ldr r3, [pc, #580] ; (800ade8 ) + 800aba2: 691b ldr r3, [r3, #16] + 800aba4: 4a8f ldr r2, [pc, #572] ; (800ade4 ) + 800aba6: 6812 ldr r2, [r2, #0] + 800aba8: 605a str r2, [r3, #4] + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { + 800abaa: e00d b.n 800abc8 + } else { + if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { + 800abac: 4b8d ldr r3, [pc, #564] ; (800ade4 ) + 800abae: 681a ldr r2, [r3, #0] + 800abb0: 687b ldr r3, [r7, #4] + 800abb2: 6a5b ldr r3, [r3, #36] ; 0x24 + 800abb4: 1ad3 subs r3, r2, r3 + 800abb6: 2b00 cmp r3, #0 + 800abb8: da06 bge.n 800abc8 + /* the whole segment is < rcv_nxt */ + /* must be a duplicate of a packet that has already been correctly handled */ + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); + tcp_ack_now(pcb); + 800abba: 687b ldr r3, [r7, #4] + 800abbc: 8b5b ldrh r3, [r3, #26] + 800abbe: f043 0302 orr.w r3, r3, #2 + 800abc2: b29a uxth r2, r3 + 800abc4: 687b ldr r3, [r7, #4] + 800abc6: 835a strh r2, [r3, #26] + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + 800abc8: 4b86 ldr r3, [pc, #536] ; (800ade4 ) + 800abca: 681a ldr r2, [r3, #0] + 800abcc: 687b ldr r3, [r7, #4] + 800abce: 6a5b ldr r3, [r3, #36] ; 0x24 + 800abd0: 1ad3 subs r3, r2, r3 + 800abd2: 2b00 cmp r3, #0 + 800abd4: f2c0 842a blt.w 800b42c + 800abd8: 4b82 ldr r3, [pc, #520] ; (800ade4 ) + 800abda: 681a ldr r2, [r3, #0] + 800abdc: 687b ldr r3, [r7, #4] + 800abde: 6a5b ldr r3, [r3, #36] ; 0x24 + 800abe0: 6879 ldr r1, [r7, #4] + 800abe2: 8d09 ldrh r1, [r1, #40] ; 0x28 + 800abe4: 440b add r3, r1 + 800abe6: 1ad3 subs r3, r2, r3 + 800abe8: 3301 adds r3, #1 + 800abea: 2b00 cmp r3, #0 + 800abec: f300 841e bgt.w 800b42c + pcb->rcv_nxt + pcb->rcv_wnd - 1)) { + if (pcb->rcv_nxt == seqno) { + 800abf0: 687b ldr r3, [r7, #4] + 800abf2: 6a5a ldr r2, [r3, #36] ; 0x24 + 800abf4: 4b7b ldr r3, [pc, #492] ; (800ade4 ) + 800abf6: 681b ldr r3, [r3, #0] + 800abf8: 429a cmp r2, r3 + 800abfa: f040 829a bne.w 800b132 + /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ + tcplen = TCP_TCPLEN(&inseg); + 800abfe: 4b7a ldr r3, [pc, #488] ; (800ade8 ) + 800ac00: 891c ldrh r4, [r3, #8] + 800ac02: 4b79 ldr r3, [pc, #484] ; (800ade8 ) + 800ac04: 691b ldr r3, [r3, #16] + 800ac06: 899b ldrh r3, [r3, #12] + 800ac08: b29b uxth r3, r3 + 800ac0a: 4618 mov r0, r3 + 800ac0c: f7fa fc9e bl 800554c + 800ac10: 4603 mov r3, r0 + 800ac12: b2db uxtb r3, r3 + 800ac14: f003 0303 and.w r3, r3, #3 + 800ac18: 2b00 cmp r3, #0 + 800ac1a: d001 beq.n 800ac20 + 800ac1c: 2301 movs r3, #1 + 800ac1e: e000 b.n 800ac22 + 800ac20: 2300 movs r3, #0 + 800ac22: 4423 add r3, r4 + 800ac24: b29a uxth r2, r3 + 800ac26: 4b71 ldr r3, [pc, #452] ; (800adec ) + 800ac28: 801a strh r2, [r3, #0] + + if (tcplen > pcb->rcv_wnd) { + 800ac2a: 687b ldr r3, [r7, #4] + 800ac2c: 8d1a ldrh r2, [r3, #40] ; 0x28 + 800ac2e: 4b6f ldr r3, [pc, #444] ; (800adec ) + 800ac30: 881b ldrh r3, [r3, #0] + 800ac32: 429a cmp r2, r3 + 800ac34: d275 bcs.n 800ad22 + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + 800ac36: 4b6c ldr r3, [pc, #432] ; (800ade8 ) + 800ac38: 691b ldr r3, [r3, #16] + 800ac3a: 899b ldrh r3, [r3, #12] + 800ac3c: b29b uxth r3, r3 + 800ac3e: 4618 mov r0, r3 + 800ac40: f7fa fc84 bl 800554c + 800ac44: 4603 mov r3, r0 + 800ac46: b2db uxtb r3, r3 + 800ac48: f003 0301 and.w r3, r3, #1 + 800ac4c: 2b00 cmp r3, #0 + 800ac4e: d01f beq.n 800ac90 + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN); + 800ac50: 4b65 ldr r3, [pc, #404] ; (800ade8 ) + 800ac52: 691b ldr r3, [r3, #16] + 800ac54: 899b ldrh r3, [r3, #12] + 800ac56: b29b uxth r3, r3 + 800ac58: b21b sxth r3, r3 + 800ac5a: f423 537c bic.w r3, r3, #16128 ; 0x3f00 + 800ac5e: b21c sxth r4, r3 + 800ac60: 4b61 ldr r3, [pc, #388] ; (800ade8 ) + 800ac62: 691b ldr r3, [r3, #16] + 800ac64: 899b ldrh r3, [r3, #12] + 800ac66: b29b uxth r3, r3 + 800ac68: 4618 mov r0, r3 + 800ac6a: f7fa fc6f bl 800554c + 800ac6e: 4603 mov r3, r0 + 800ac70: b2db uxtb r3, r3 + 800ac72: b29b uxth r3, r3 + 800ac74: f003 033e and.w r3, r3, #62 ; 0x3e + 800ac78: b29b uxth r3, r3 + 800ac7a: 4618 mov r0, r3 + 800ac7c: f7fa fc66 bl 800554c + 800ac80: 4603 mov r3, r0 + 800ac82: b21b sxth r3, r3 + 800ac84: 4323 orrs r3, r4 + 800ac86: b21a sxth r2, r3 + 800ac88: 4b57 ldr r3, [pc, #348] ; (800ade8 ) + 800ac8a: 691b ldr r3, [r3, #16] + 800ac8c: b292 uxth r2, r2 + 800ac8e: 819a strh r2, [r3, #12] + } + /* Adjust length of segment to fit in the window. */ + TCPWND_CHECK16(pcb->rcv_wnd); + inseg.len = (u16_t)pcb->rcv_wnd; + 800ac90: 687b ldr r3, [r7, #4] + 800ac92: 8d1a ldrh r2, [r3, #40] ; 0x28 + 800ac94: 4b54 ldr r3, [pc, #336] ; (800ade8 ) + 800ac96: 811a strh r2, [r3, #8] + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + 800ac98: 4b53 ldr r3, [pc, #332] ; (800ade8 ) + 800ac9a: 691b ldr r3, [r3, #16] + 800ac9c: 899b ldrh r3, [r3, #12] + 800ac9e: b29b uxth r3, r3 + 800aca0: 4618 mov r0, r3 + 800aca2: f7fa fc53 bl 800554c + 800aca6: 4603 mov r3, r0 + 800aca8: b2db uxtb r3, r3 + 800acaa: f003 0302 and.w r3, r3, #2 + 800acae: 2b00 cmp r3, #0 + 800acb0: d005 beq.n 800acbe + inseg.len -= 1; + 800acb2: 4b4d ldr r3, [pc, #308] ; (800ade8 ) + 800acb4: 891b ldrh r3, [r3, #8] + 800acb6: 3b01 subs r3, #1 + 800acb8: b29a uxth r2, r3 + 800acba: 4b4b ldr r3, [pc, #300] ; (800ade8 ) + 800acbc: 811a strh r2, [r3, #8] + } + pbuf_realloc(inseg.p, inseg.len); + 800acbe: 4b4a ldr r3, [pc, #296] ; (800ade8 ) + 800acc0: 685b ldr r3, [r3, #4] + 800acc2: 4a49 ldr r2, [pc, #292] ; (800ade8 ) + 800acc4: 8912 ldrh r2, [r2, #8] + 800acc6: 4611 mov r1, r2 + 800acc8: 4618 mov r0, r3 + 800acca: f7fb fffd bl 8006cc8 + tcplen = TCP_TCPLEN(&inseg); + 800acce: 4b46 ldr r3, [pc, #280] ; (800ade8 ) + 800acd0: 891c ldrh r4, [r3, #8] + 800acd2: 4b45 ldr r3, [pc, #276] ; (800ade8 ) + 800acd4: 691b ldr r3, [r3, #16] + 800acd6: 899b ldrh r3, [r3, #12] + 800acd8: b29b uxth r3, r3 + 800acda: 4618 mov r0, r3 + 800acdc: f7fa fc36 bl 800554c + 800ace0: 4603 mov r3, r0 + 800ace2: b2db uxtb r3, r3 + 800ace4: f003 0303 and.w r3, r3, #3 + 800ace8: 2b00 cmp r3, #0 + 800acea: d001 beq.n 800acf0 + 800acec: 2301 movs r3, #1 + 800acee: e000 b.n 800acf2 + 800acf0: 2300 movs r3, #0 + 800acf2: 4423 add r3, r4 + 800acf4: b29a uxth r2, r3 + 800acf6: 4b3d ldr r3, [pc, #244] ; (800adec ) + 800acf8: 801a strh r2, [r3, #0] + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + 800acfa: 4b3c ldr r3, [pc, #240] ; (800adec ) + 800acfc: 881b ldrh r3, [r3, #0] + 800acfe: 461a mov r2, r3 + 800ad00: 4b38 ldr r3, [pc, #224] ; (800ade4 ) + 800ad02: 681b ldr r3, [r3, #0] + 800ad04: 441a add r2, r3 + 800ad06: 687b ldr r3, [r7, #4] + 800ad08: 6a5b ldr r3, [r3, #36] ; 0x24 + 800ad0a: 6879 ldr r1, [r7, #4] + 800ad0c: 8d09 ldrh r1, [r1, #40] ; 0x28 + 800ad0e: 440b add r3, r1 + 800ad10: 429a cmp r2, r3 + 800ad12: d006 beq.n 800ad22 + 800ad14: 4b36 ldr r3, [pc, #216] ; (800adf0 ) + 800ad16: f240 52cb movw r2, #1483 ; 0x5cb + 800ad1a: 4936 ldr r1, [pc, #216] ; (800adf4 ) + 800ad1c: 4836 ldr r0, [pc, #216] ; (800adf8 ) + 800ad1e: f005 ff53 bl 8010bc8 + } +#if TCP_QUEUE_OOSEQ + /* Received in-sequence data, adjust ooseq data if: + - FIN has been received or + - inseq overlaps with ooseq */ + if (pcb->ooseq != NULL) { + 800ad22: 687b ldr r3, [r7, #4] + 800ad24: 6f5b ldr r3, [r3, #116] ; 0x74 + 800ad26: 2b00 cmp r3, #0 + 800ad28: f000 80e7 beq.w 800aefa + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + 800ad2c: 4b2e ldr r3, [pc, #184] ; (800ade8 ) + 800ad2e: 691b ldr r3, [r3, #16] + 800ad30: 899b ldrh r3, [r3, #12] + 800ad32: b29b uxth r3, r3 + 800ad34: 4618 mov r0, r3 + 800ad36: f7fa fc09 bl 800554c + 800ad3a: 4603 mov r3, r0 + 800ad3c: b2db uxtb r3, r3 + 800ad3e: f003 0301 and.w r3, r3, #1 + 800ad42: 2b00 cmp r3, #0 + 800ad44: d010 beq.n 800ad68 + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: received in-order FIN, binning ooseq queue\n")); + /* Received in-order FIN means anything that was received + * out of order must now have been received in-order, so + * bin the ooseq queue */ + while (pcb->ooseq != NULL) { + 800ad46: e00a b.n 800ad5e + struct tcp_seg *old_ooseq = pcb->ooseq; + 800ad48: 687b ldr r3, [r7, #4] + 800ad4a: 6f5b ldr r3, [r3, #116] ; 0x74 + 800ad4c: 60fb str r3, [r7, #12] + pcb->ooseq = pcb->ooseq->next; + 800ad4e: 687b ldr r3, [r7, #4] + 800ad50: 6f5b ldr r3, [r3, #116] ; 0x74 + 800ad52: 681a ldr r2, [r3, #0] + 800ad54: 687b ldr r3, [r7, #4] + 800ad56: 675a str r2, [r3, #116] ; 0x74 + tcp_seg_free(old_ooseq); + 800ad58: 68f8 ldr r0, [r7, #12] + 800ad5a: f7fd fd0c bl 8008776 + while (pcb->ooseq != NULL) { + 800ad5e: 687b ldr r3, [r7, #4] + 800ad60: 6f5b ldr r3, [r3, #116] ; 0x74 + 800ad62: 2b00 cmp r3, #0 + 800ad64: d1f0 bne.n 800ad48 + 800ad66: e0c8 b.n 800aefa + } + } else { + struct tcp_seg *next = pcb->ooseq; + 800ad68: 687b ldr r3, [r7, #4] + 800ad6a: 6f5b ldr r3, [r3, #116] ; 0x74 + 800ad6c: 63fb str r3, [r7, #60] ; 0x3c + /* Remove all segments on ooseq that are covered by inseg already. + * FIN is copied from ooseq to inseg if present. */ + while (next && + 800ad6e: e052 b.n 800ae16 + TCP_SEQ_GEQ(seqno + tcplen, + next->tcphdr->seqno + next->len)) { + struct tcp_seg *tmp; + /* inseg cannot have FIN here (already processed above) */ + if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && + 800ad70: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ad72: 691b ldr r3, [r3, #16] + 800ad74: 899b ldrh r3, [r3, #12] + 800ad76: b29b uxth r3, r3 + 800ad78: 4618 mov r0, r3 + 800ad7a: f7fa fbe7 bl 800554c + 800ad7e: 4603 mov r3, r0 + 800ad80: b2db uxtb r3, r3 + 800ad82: f003 0301 and.w r3, r3, #1 + 800ad86: 2b00 cmp r3, #0 + 800ad88: d03d beq.n 800ae06 + (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { + 800ad8a: 4b17 ldr r3, [pc, #92] ; (800ade8 ) + 800ad8c: 691b ldr r3, [r3, #16] + 800ad8e: 899b ldrh r3, [r3, #12] + 800ad90: b29b uxth r3, r3 + 800ad92: 4618 mov r0, r3 + 800ad94: f7fa fbda bl 800554c + 800ad98: 4603 mov r3, r0 + 800ad9a: b2db uxtb r3, r3 + 800ad9c: f003 0302 and.w r3, r3, #2 + if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && + 800ada0: 2b00 cmp r3, #0 + 800ada2: d130 bne.n 800ae06 + TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN); + 800ada4: 4b10 ldr r3, [pc, #64] ; (800ade8 ) + 800ada6: 691b ldr r3, [r3, #16] + 800ada8: 899b ldrh r3, [r3, #12] + 800adaa: b29c uxth r4, r3 + 800adac: 2001 movs r0, #1 + 800adae: f7fa fbcd bl 800554c + 800adb2: 4603 mov r3, r0 + 800adb4: 461a mov r2, r3 + 800adb6: 4b0c ldr r3, [pc, #48] ; (800ade8 ) + 800adb8: 691b ldr r3, [r3, #16] + 800adba: 4322 orrs r2, r4 + 800adbc: b292 uxth r2, r2 + 800adbe: 819a strh r2, [r3, #12] + tcplen = TCP_TCPLEN(&inseg); + 800adc0: 4b09 ldr r3, [pc, #36] ; (800ade8 ) + 800adc2: 891c ldrh r4, [r3, #8] + 800adc4: 4b08 ldr r3, [pc, #32] ; (800ade8 ) + 800adc6: 691b ldr r3, [r3, #16] + 800adc8: 899b ldrh r3, [r3, #12] + 800adca: b29b uxth r3, r3 + 800adcc: 4618 mov r0, r3 + 800adce: f7fa fbbd bl 800554c + 800add2: 4603 mov r3, r0 + 800add4: b2db uxtb r3, r3 + 800add6: f003 0303 and.w r3, r3, #3 + 800adda: 2b00 cmp r3, #0 + 800addc: d00e beq.n 800adfc + 800adde: 2301 movs r3, #1 + 800ade0: e00d b.n 800adfe + 800ade2: bf00 nop + 800ade4: 24007ba8 .word 0x24007ba8 + 800ade8: 24007b84 .word 0x24007b84 + 800adec: 24007bb2 .word 0x24007bb2 + 800adf0: 08013198 .word 0x08013198 + 800adf4: 08013540 .word 0x08013540 + 800adf8: 080131e4 .word 0x080131e4 + 800adfc: 2300 movs r3, #0 + 800adfe: 4423 add r3, r4 + 800ae00: b29a uxth r2, r3 + 800ae02: 4b98 ldr r3, [pc, #608] ; (800b064 ) + 800ae04: 801a strh r2, [r3, #0] + } + tmp = next; + 800ae06: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ae08: 613b str r3, [r7, #16] + next = next->next; + 800ae0a: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ae0c: 681b ldr r3, [r3, #0] + 800ae0e: 63fb str r3, [r7, #60] ; 0x3c + tcp_seg_free(tmp); + 800ae10: 6938 ldr r0, [r7, #16] + 800ae12: f7fd fcb0 bl 8008776 + while (next && + 800ae16: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ae18: 2b00 cmp r3, #0 + 800ae1a: d00e beq.n 800ae3a + TCP_SEQ_GEQ(seqno + tcplen, + 800ae1c: 4b91 ldr r3, [pc, #580] ; (800b064 ) + 800ae1e: 881b ldrh r3, [r3, #0] + 800ae20: 461a mov r2, r3 + 800ae22: 4b91 ldr r3, [pc, #580] ; (800b068 ) + 800ae24: 681b ldr r3, [r3, #0] + 800ae26: 441a add r2, r3 + 800ae28: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ae2a: 691b ldr r3, [r3, #16] + 800ae2c: 685b ldr r3, [r3, #4] + 800ae2e: 6bf9 ldr r1, [r7, #60] ; 0x3c + 800ae30: 8909 ldrh r1, [r1, #8] + 800ae32: 440b add r3, r1 + 800ae34: 1ad3 subs r3, r2, r3 + while (next && + 800ae36: 2b00 cmp r3, #0 + 800ae38: da9a bge.n 800ad70 + } + /* Now trim right side of inseg if it overlaps with the first + * segment on ooseq */ + if (next && + 800ae3a: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ae3c: 2b00 cmp r3, #0 + 800ae3e: d059 beq.n 800aef4 + TCP_SEQ_GT(seqno + tcplen, + 800ae40: 4b88 ldr r3, [pc, #544] ; (800b064 ) + 800ae42: 881b ldrh r3, [r3, #0] + 800ae44: 461a mov r2, r3 + 800ae46: 4b88 ldr r3, [pc, #544] ; (800b068 ) + 800ae48: 681b ldr r3, [r3, #0] + 800ae4a: 441a add r2, r3 + 800ae4c: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ae4e: 691b ldr r3, [r3, #16] + 800ae50: 685b ldr r3, [r3, #4] + 800ae52: 1ad3 subs r3, r2, r3 + if (next && + 800ae54: 2b00 cmp r3, #0 + 800ae56: dd4d ble.n 800aef4 + next->tcphdr->seqno)) { + /* inseg cannot have FIN here (already processed above) */ + inseg.len = (u16_t)(next->tcphdr->seqno - seqno); + 800ae58: 6bfb ldr r3, [r7, #60] ; 0x3c + 800ae5a: 691b ldr r3, [r3, #16] + 800ae5c: 685b ldr r3, [r3, #4] + 800ae5e: b29a uxth r2, r3 + 800ae60: 4b81 ldr r3, [pc, #516] ; (800b068 ) + 800ae62: 681b ldr r3, [r3, #0] + 800ae64: b29b uxth r3, r3 + 800ae66: 1ad3 subs r3, r2, r3 + 800ae68: b29a uxth r2, r3 + 800ae6a: 4b80 ldr r3, [pc, #512] ; (800b06c ) + 800ae6c: 811a strh r2, [r3, #8] + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + 800ae6e: 4b7f ldr r3, [pc, #508] ; (800b06c ) + 800ae70: 691b ldr r3, [r3, #16] + 800ae72: 899b ldrh r3, [r3, #12] + 800ae74: b29b uxth r3, r3 + 800ae76: 4618 mov r0, r3 + 800ae78: f7fa fb68 bl 800554c + 800ae7c: 4603 mov r3, r0 + 800ae7e: b2db uxtb r3, r3 + 800ae80: f003 0302 and.w r3, r3, #2 + 800ae84: 2b00 cmp r3, #0 + 800ae86: d005 beq.n 800ae94 + inseg.len -= 1; + 800ae88: 4b78 ldr r3, [pc, #480] ; (800b06c ) + 800ae8a: 891b ldrh r3, [r3, #8] + 800ae8c: 3b01 subs r3, #1 + 800ae8e: b29a uxth r2, r3 + 800ae90: 4b76 ldr r3, [pc, #472] ; (800b06c ) + 800ae92: 811a strh r2, [r3, #8] + } + pbuf_realloc(inseg.p, inseg.len); + 800ae94: 4b75 ldr r3, [pc, #468] ; (800b06c ) + 800ae96: 685b ldr r3, [r3, #4] + 800ae98: 4a74 ldr r2, [pc, #464] ; (800b06c ) + 800ae9a: 8912 ldrh r2, [r2, #8] + 800ae9c: 4611 mov r1, r2 + 800ae9e: 4618 mov r0, r3 + 800aea0: f7fb ff12 bl 8006cc8 + tcplen = TCP_TCPLEN(&inseg); + 800aea4: 4b71 ldr r3, [pc, #452] ; (800b06c ) + 800aea6: 891c ldrh r4, [r3, #8] + 800aea8: 4b70 ldr r3, [pc, #448] ; (800b06c ) + 800aeaa: 691b ldr r3, [r3, #16] + 800aeac: 899b ldrh r3, [r3, #12] + 800aeae: b29b uxth r3, r3 + 800aeb0: 4618 mov r0, r3 + 800aeb2: f7fa fb4b bl 800554c + 800aeb6: 4603 mov r3, r0 + 800aeb8: b2db uxtb r3, r3 + 800aeba: f003 0303 and.w r3, r3, #3 + 800aebe: 2b00 cmp r3, #0 + 800aec0: d001 beq.n 800aec6 + 800aec2: 2301 movs r3, #1 + 800aec4: e000 b.n 800aec8 + 800aec6: 2300 movs r3, #0 + 800aec8: 4423 add r3, r4 + 800aeca: b29a uxth r2, r3 + 800aecc: 4b65 ldr r3, [pc, #404] ; (800b064 ) + 800aece: 801a strh r2, [r3, #0] + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", + 800aed0: 4b64 ldr r3, [pc, #400] ; (800b064 ) + 800aed2: 881b ldrh r3, [r3, #0] + 800aed4: 461a mov r2, r3 + 800aed6: 4b64 ldr r3, [pc, #400] ; (800b068 ) + 800aed8: 681b ldr r3, [r3, #0] + 800aeda: 441a add r2, r3 + 800aedc: 6bfb ldr r3, [r7, #60] ; 0x3c + 800aede: 691b ldr r3, [r3, #16] + 800aee0: 685b ldr r3, [r3, #4] + 800aee2: 429a cmp r2, r3 + 800aee4: d006 beq.n 800aef4 + 800aee6: 4b62 ldr r3, [pc, #392] ; (800b070 ) + 800aee8: f240 52fc movw r2, #1532 ; 0x5fc + 800aeec: 4961 ldr r1, [pc, #388] ; (800b074 ) + 800aeee: 4862 ldr r0, [pc, #392] ; (800b078 ) + 800aef0: f005 fe6a bl 8010bc8 + (seqno + tcplen) == next->tcphdr->seqno); + } + pcb->ooseq = next; + 800aef4: 687b ldr r3, [r7, #4] + 800aef6: 6bfa ldr r2, [r7, #60] ; 0x3c + 800aef8: 675a str r2, [r3, #116] ; 0x74 + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + pcb->rcv_nxt = seqno + tcplen; + 800aefa: 4b5a ldr r3, [pc, #360] ; (800b064 ) + 800aefc: 881b ldrh r3, [r3, #0] + 800aefe: 461a mov r2, r3 + 800af00: 4b59 ldr r3, [pc, #356] ; (800b068 ) + 800af02: 681b ldr r3, [r3, #0] + 800af04: 441a add r2, r3 + 800af06: 687b ldr r3, [r7, #4] + 800af08: 625a str r2, [r3, #36] ; 0x24 + + /* Update the receiver's (our) window. */ + LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); + 800af0a: 687b ldr r3, [r7, #4] + 800af0c: 8d1a ldrh r2, [r3, #40] ; 0x28 + 800af0e: 4b55 ldr r3, [pc, #340] ; (800b064 ) + 800af10: 881b ldrh r3, [r3, #0] + 800af12: 429a cmp r2, r3 + 800af14: d206 bcs.n 800af24 + 800af16: 4b56 ldr r3, [pc, #344] ; (800b070 ) + 800af18: f240 6207 movw r2, #1543 ; 0x607 + 800af1c: 4957 ldr r1, [pc, #348] ; (800b07c ) + 800af1e: 4856 ldr r0, [pc, #344] ; (800b078 ) + 800af20: f005 fe52 bl 8010bc8 + pcb->rcv_wnd -= tcplen; + 800af24: 687b ldr r3, [r7, #4] + 800af26: 8d1a ldrh r2, [r3, #40] ; 0x28 + 800af28: 4b4e ldr r3, [pc, #312] ; (800b064 ) + 800af2a: 881b ldrh r3, [r3, #0] + 800af2c: 1ad3 subs r3, r2, r3 + 800af2e: b29a uxth r2, r3 + 800af30: 687b ldr r3, [r7, #4] + 800af32: 851a strh r2, [r3, #40] ; 0x28 + + tcp_update_rcv_ann_wnd(pcb); + 800af34: 6878 ldr r0, [r7, #4] + 800af36: f7fc fde1 bl 8007afc + chains its data on this pbuf as well. + + If the segment was a FIN, we set the TF_GOT_FIN flag that will + be used to indicate to the application that the remote side has + closed its end of the connection. */ + if (inseg.p->tot_len > 0) { + 800af3a: 4b4c ldr r3, [pc, #304] ; (800b06c ) + 800af3c: 685b ldr r3, [r3, #4] + 800af3e: 891b ldrh r3, [r3, #8] + 800af40: 2b00 cmp r3, #0 + 800af42: d006 beq.n 800af52 + recv_data = inseg.p; + 800af44: 4b49 ldr r3, [pc, #292] ; (800b06c ) + 800af46: 685b ldr r3, [r3, #4] + 800af48: 4a4d ldr r2, [pc, #308] ; (800b080 ) + 800af4a: 6013 str r3, [r2, #0] + /* Since this pbuf now is the responsibility of the + application, we delete our reference to it so that we won't + (mistakingly) deallocate it. */ + inseg.p = NULL; + 800af4c: 4b47 ldr r3, [pc, #284] ; (800b06c ) + 800af4e: 2200 movs r2, #0 + 800af50: 605a str r2, [r3, #4] + } + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + 800af52: 4b46 ldr r3, [pc, #280] ; (800b06c ) + 800af54: 691b ldr r3, [r3, #16] + 800af56: 899b ldrh r3, [r3, #12] + 800af58: b29b uxth r3, r3 + 800af5a: 4618 mov r0, r3 + 800af5c: f7fa faf6 bl 800554c + 800af60: 4603 mov r3, r0 + 800af62: b2db uxtb r3, r3 + 800af64: f003 0301 and.w r3, r3, #1 + 800af68: 2b00 cmp r3, #0 + 800af6a: f000 80b8 beq.w 800b0de + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); + recv_flags |= TF_GOT_FIN; + 800af6e: 4b45 ldr r3, [pc, #276] ; (800b084 ) + 800af70: 781b ldrb r3, [r3, #0] + 800af72: f043 0320 orr.w r3, r3, #32 + 800af76: b2da uxtb r2, r3 + 800af78: 4b42 ldr r3, [pc, #264] ; (800b084 ) + 800af7a: 701a strb r2, [r3, #0] + } + +#if TCP_QUEUE_OOSEQ + /* We now check if we have segments on the ->ooseq queue that + are now in sequence. */ + while (pcb->ooseq != NULL && + 800af7c: e0af b.n 800b0de + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + + struct tcp_seg *cseg = pcb->ooseq; + 800af7e: 687b ldr r3, [r7, #4] + 800af80: 6f5b ldr r3, [r3, #116] ; 0x74 + 800af82: 60bb str r3, [r7, #8] + seqno = pcb->ooseq->tcphdr->seqno; + 800af84: 687b ldr r3, [r7, #4] + 800af86: 6f5b ldr r3, [r3, #116] ; 0x74 + 800af88: 691b ldr r3, [r3, #16] + 800af8a: 685b ldr r3, [r3, #4] + 800af8c: 4a36 ldr r2, [pc, #216] ; (800b068 ) + 800af8e: 6013 str r3, [r2, #0] + + pcb->rcv_nxt += TCP_TCPLEN(cseg); + 800af90: 68bb ldr r3, [r7, #8] + 800af92: 891b ldrh r3, [r3, #8] + 800af94: 461c mov r4, r3 + 800af96: 68bb ldr r3, [r7, #8] + 800af98: 691b ldr r3, [r3, #16] + 800af9a: 899b ldrh r3, [r3, #12] + 800af9c: b29b uxth r3, r3 + 800af9e: 4618 mov r0, r3 + 800afa0: f7fa fad4 bl 800554c + 800afa4: 4603 mov r3, r0 + 800afa6: b2db uxtb r3, r3 + 800afa8: f003 0303 and.w r3, r3, #3 + 800afac: 2b00 cmp r3, #0 + 800afae: d001 beq.n 800afb4 + 800afb0: 2301 movs r3, #1 + 800afb2: e000 b.n 800afb6 + 800afb4: 2300 movs r3, #0 + 800afb6: 191a adds r2, r3, r4 + 800afb8: 687b ldr r3, [r7, #4] + 800afba: 6a5b ldr r3, [r3, #36] ; 0x24 + 800afbc: 441a add r2, r3 + 800afbe: 687b ldr r3, [r7, #4] + 800afc0: 625a str r2, [r3, #36] ; 0x24 + LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", + 800afc2: 687b ldr r3, [r7, #4] + 800afc4: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800afc6: 461c mov r4, r3 + 800afc8: 68bb ldr r3, [r7, #8] + 800afca: 891b ldrh r3, [r3, #8] + 800afcc: 461d mov r5, r3 + 800afce: 68bb ldr r3, [r7, #8] + 800afd0: 691b ldr r3, [r3, #16] + 800afd2: 899b ldrh r3, [r3, #12] + 800afd4: b29b uxth r3, r3 + 800afd6: 4618 mov r0, r3 + 800afd8: f7fa fab8 bl 800554c + 800afdc: 4603 mov r3, r0 + 800afde: b2db uxtb r3, r3 + 800afe0: f003 0303 and.w r3, r3, #3 + 800afe4: 2b00 cmp r3, #0 + 800afe6: d001 beq.n 800afec + 800afe8: 2301 movs r3, #1 + 800afea: e000 b.n 800afee + 800afec: 2300 movs r3, #0 + 800afee: 442b add r3, r5 + 800aff0: 429c cmp r4, r3 + 800aff2: d206 bcs.n 800b002 + 800aff4: 4b1e ldr r3, [pc, #120] ; (800b070 ) + 800aff6: f240 622b movw r2, #1579 ; 0x62b + 800affa: 4923 ldr r1, [pc, #140] ; (800b088 ) + 800affc: 481e ldr r0, [pc, #120] ; (800b078 ) + 800affe: f005 fde3 bl 8010bc8 + pcb->rcv_wnd >= TCP_TCPLEN(cseg)); + pcb->rcv_wnd -= TCP_TCPLEN(cseg); + 800b002: 68bb ldr r3, [r7, #8] + 800b004: 891b ldrh r3, [r3, #8] + 800b006: 461c mov r4, r3 + 800b008: 68bb ldr r3, [r7, #8] + 800b00a: 691b ldr r3, [r3, #16] + 800b00c: 899b ldrh r3, [r3, #12] + 800b00e: b29b uxth r3, r3 + 800b010: 4618 mov r0, r3 + 800b012: f7fa fa9b bl 800554c + 800b016: 4603 mov r3, r0 + 800b018: b2db uxtb r3, r3 + 800b01a: f003 0303 and.w r3, r3, #3 + 800b01e: 2b00 cmp r3, #0 + 800b020: d001 beq.n 800b026 + 800b022: 2301 movs r3, #1 + 800b024: e000 b.n 800b028 + 800b026: 2300 movs r3, #0 + 800b028: 1919 adds r1, r3, r4 + 800b02a: 687b ldr r3, [r7, #4] + 800b02c: 8d1a ldrh r2, [r3, #40] ; 0x28 + 800b02e: b28b uxth r3, r1 + 800b030: 1ad3 subs r3, r2, r3 + 800b032: b29a uxth r2, r3 + 800b034: 687b ldr r3, [r7, #4] + 800b036: 851a strh r2, [r3, #40] ; 0x28 + + tcp_update_rcv_ann_wnd(pcb); + 800b038: 6878 ldr r0, [r7, #4] + 800b03a: f7fc fd5f bl 8007afc + + if (cseg->p->tot_len > 0) { + 800b03e: 68bb ldr r3, [r7, #8] + 800b040: 685b ldr r3, [r3, #4] + 800b042: 891b ldrh r3, [r3, #8] + 800b044: 2b00 cmp r3, #0 + 800b046: d028 beq.n 800b09a + /* Chain this pbuf onto the pbuf that we will pass to + the application. */ + /* With window scaling, this can overflow recv_data->tot_len, but + that's not a problem since we explicitly fix that before passing + recv_data to the application. */ + if (recv_data) { + 800b048: 4b0d ldr r3, [pc, #52] ; (800b080 ) + 800b04a: 681b ldr r3, [r3, #0] + 800b04c: 2b00 cmp r3, #0 + 800b04e: d01d beq.n 800b08c + pbuf_cat(recv_data, cseg->p); + 800b050: 4b0b ldr r3, [pc, #44] ; (800b080 ) + 800b052: 681a ldr r2, [r3, #0] + 800b054: 68bb ldr r3, [r7, #8] + 800b056: 685b ldr r3, [r3, #4] + 800b058: 4619 mov r1, r3 + 800b05a: 4610 mov r0, r2 + 800b05c: f7fc f87c bl 8007158 + 800b060: e018 b.n 800b094 + 800b062: bf00 nop + 800b064: 24007bb2 .word 0x24007bb2 + 800b068: 24007ba8 .word 0x24007ba8 + 800b06c: 24007b84 .word 0x24007b84 + 800b070: 08013198 .word 0x08013198 + 800b074: 08013578 .word 0x08013578 + 800b078: 080131e4 .word 0x080131e4 + 800b07c: 080135b4 .word 0x080135b4 + 800b080: 24007bb8 .word 0x24007bb8 + 800b084: 24007bb5 .word 0x24007bb5 + 800b088: 080135d4 .word 0x080135d4 + } else { + recv_data = cseg->p; + 800b08c: 68bb ldr r3, [r7, #8] + 800b08e: 685b ldr r3, [r3, #4] + 800b090: 4a70 ldr r2, [pc, #448] ; (800b254 ) + 800b092: 6013 str r3, [r2, #0] + } + cseg->p = NULL; + 800b094: 68bb ldr r3, [r7, #8] + 800b096: 2200 movs r2, #0 + 800b098: 605a str r2, [r3, #4] + } + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + 800b09a: 68bb ldr r3, [r7, #8] + 800b09c: 691b ldr r3, [r3, #16] + 800b09e: 899b ldrh r3, [r3, #12] + 800b0a0: b29b uxth r3, r3 + 800b0a2: 4618 mov r0, r3 + 800b0a4: f7fa fa52 bl 800554c + 800b0a8: 4603 mov r3, r0 + 800b0aa: b2db uxtb r3, r3 + 800b0ac: f003 0301 and.w r3, r3, #1 + 800b0b0: 2b00 cmp r3, #0 + 800b0b2: d00d beq.n 800b0d0 + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); + recv_flags |= TF_GOT_FIN; + 800b0b4: 4b68 ldr r3, [pc, #416] ; (800b258 ) + 800b0b6: 781b ldrb r3, [r3, #0] + 800b0b8: f043 0320 orr.w r3, r3, #32 + 800b0bc: b2da uxtb r2, r3 + 800b0be: 4b66 ldr r3, [pc, #408] ; (800b258 ) + 800b0c0: 701a strb r2, [r3, #0] + if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ + 800b0c2: 687b ldr r3, [r7, #4] + 800b0c4: 7d1b ldrb r3, [r3, #20] + 800b0c6: 2b04 cmp r3, #4 + 800b0c8: d102 bne.n 800b0d0 + pcb->state = CLOSE_WAIT; + 800b0ca: 687b ldr r3, [r7, #4] + 800b0cc: 2207 movs r2, #7 + 800b0ce: 751a strb r2, [r3, #20] + } + } + + pcb->ooseq = cseg->next; + 800b0d0: 68bb ldr r3, [r7, #8] + 800b0d2: 681a ldr r2, [r3, #0] + 800b0d4: 687b ldr r3, [r7, #4] + 800b0d6: 675a str r2, [r3, #116] ; 0x74 + tcp_seg_free(cseg); + 800b0d8: 68b8 ldr r0, [r7, #8] + 800b0da: f7fd fb4c bl 8008776 + while (pcb->ooseq != NULL && + 800b0de: 687b ldr r3, [r7, #4] + 800b0e0: 6f5b ldr r3, [r3, #116] ; 0x74 + 800b0e2: 2b00 cmp r3, #0 + 800b0e4: d008 beq.n 800b0f8 + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + 800b0e6: 687b ldr r3, [r7, #4] + 800b0e8: 6f5b ldr r3, [r3, #116] ; 0x74 + 800b0ea: 691b ldr r3, [r3, #16] + 800b0ec: 685a ldr r2, [r3, #4] + 800b0ee: 687b ldr r3, [r7, #4] + 800b0f0: 6a5b ldr r3, [r3, #36] ; 0x24 + while (pcb->ooseq != NULL && + 800b0f2: 429a cmp r2, r3 + 800b0f4: f43f af43 beq.w 800af7e +#endif /* LWIP_TCP_SACK_OUT */ +#endif /* TCP_QUEUE_OOSEQ */ + + + /* Acknowledge the segment(s). */ + tcp_ack(pcb); + 800b0f8: 687b ldr r3, [r7, #4] + 800b0fa: 8b5b ldrh r3, [r3, #26] + 800b0fc: f003 0301 and.w r3, r3, #1 + 800b100: 2b00 cmp r3, #0 + 800b102: d00e beq.n 800b122 + 800b104: 687b ldr r3, [r7, #4] + 800b106: 8b5b ldrh r3, [r3, #26] + 800b108: f023 0301 bic.w r3, r3, #1 + 800b10c: b29a uxth r2, r3 + 800b10e: 687b ldr r3, [r7, #4] + 800b110: 835a strh r2, [r3, #26] + 800b112: 687b ldr r3, [r7, #4] + 800b114: 8b5b ldrh r3, [r3, #26] + 800b116: f043 0302 orr.w r3, r3, #2 + 800b11a: b29a uxth r2, r3 + 800b11c: 687b ldr r3, [r7, #4] + 800b11e: 835a strh r2, [r3, #26] + if (pcb->rcv_nxt == seqno) { + 800b120: e188 b.n 800b434 + tcp_ack(pcb); + 800b122: 687b ldr r3, [r7, #4] + 800b124: 8b5b ldrh r3, [r3, #26] + 800b126: f043 0301 orr.w r3, r3, #1 + 800b12a: b29a uxth r2, r3 + 800b12c: 687b ldr r3, [r7, #4] + 800b12e: 835a strh r2, [r3, #26] + if (pcb->rcv_nxt == seqno) { + 800b130: e180 b.n 800b434 + } else { + /* We get here if the incoming segment is out-of-sequence. */ + +#if TCP_QUEUE_OOSEQ + /* We queue the segment on the ->ooseq queue. */ + if (pcb->ooseq == NULL) { + 800b132: 687b ldr r3, [r7, #4] + 800b134: 6f5b ldr r3, [r3, #116] ; 0x74 + 800b136: 2b00 cmp r3, #0 + 800b138: d106 bne.n 800b148 + pcb->ooseq = tcp_seg_copy(&inseg); + 800b13a: 4848 ldr r0, [pc, #288] ; (800b25c ) + 800b13c: f7fd fb34 bl 80087a8 + 800b140: 4602 mov r2, r0 + 800b142: 687b ldr r3, [r7, #4] + 800b144: 675a str r2, [r3, #116] ; 0x74 + 800b146: e16d b.n 800b424 +#if LWIP_TCP_SACK_OUT + /* This is the left edge of the lowest possible SACK range. + It may start before the newly received segment (possibly adjusted below). */ + u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno; +#endif /* LWIP_TCP_SACK_OUT */ + struct tcp_seg *next, *prev = NULL; + 800b148: 2300 movs r3, #0 + 800b14a: 637b str r3, [r7, #52] ; 0x34 + for (next = pcb->ooseq; next != NULL; next = next->next) { + 800b14c: 687b ldr r3, [r7, #4] + 800b14e: 6f5b ldr r3, [r3, #116] ; 0x74 + 800b150: 63bb str r3, [r7, #56] ; 0x38 + 800b152: e157 b.n 800b404 + if (seqno == next->tcphdr->seqno) { + 800b154: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b156: 691b ldr r3, [r3, #16] + 800b158: 685a ldr r2, [r3, #4] + 800b15a: 4b41 ldr r3, [pc, #260] ; (800b260 ) + 800b15c: 681b ldr r3, [r3, #0] + 800b15e: 429a cmp r2, r3 + 800b160: d11d bne.n 800b19e + /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ + if (inseg.len > next->len) { + 800b162: 4b3e ldr r3, [pc, #248] ; (800b25c ) + 800b164: 891a ldrh r2, [r3, #8] + 800b166: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b168: 891b ldrh r3, [r3, #8] + 800b16a: 429a cmp r2, r3 + 800b16c: f240 814f bls.w 800b40e + /* The incoming segment is larger than the old + segment. We replace some segments with the new + one. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + 800b170: 483a ldr r0, [pc, #232] ; (800b25c ) + 800b172: f7fd fb19 bl 80087a8 + 800b176: 6178 str r0, [r7, #20] + if (cseg != NULL) { + 800b178: 697b ldr r3, [r7, #20] + 800b17a: 2b00 cmp r3, #0 + 800b17c: f000 8149 beq.w 800b412 + if (prev != NULL) { + 800b180: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b182: 2b00 cmp r3, #0 + 800b184: d003 beq.n 800b18e + prev->next = cseg; + 800b186: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b188: 697a ldr r2, [r7, #20] + 800b18a: 601a str r2, [r3, #0] + 800b18c: e002 b.n 800b194 + } else { + pcb->ooseq = cseg; + 800b18e: 687b ldr r3, [r7, #4] + 800b190: 697a ldr r2, [r7, #20] + 800b192: 675a str r2, [r3, #116] ; 0x74 + } + tcp_oos_insert_segment(cseg, next); + 800b194: 6bb9 ldr r1, [r7, #56] ; 0x38 + 800b196: 6978 ldr r0, [r7, #20] + 800b198: f7ff f8dc bl 800a354 + } + break; + 800b19c: e139 b.n 800b412 + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ + break; + } + } else { + if (prev == NULL) { + 800b19e: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b1a0: 2b00 cmp r3, #0 + 800b1a2: d117 bne.n 800b1d4 + if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { + 800b1a4: 4b2e ldr r3, [pc, #184] ; (800b260 ) + 800b1a6: 681a ldr r2, [r3, #0] + 800b1a8: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b1aa: 691b ldr r3, [r3, #16] + 800b1ac: 685b ldr r3, [r3, #4] + 800b1ae: 1ad3 subs r3, r2, r3 + 800b1b0: 2b00 cmp r3, #0 + 800b1b2: da57 bge.n 800b264 + /* The sequence number of the incoming segment is lower + than the sequence number of the first segment on the + queue. We put the incoming segment first on the + queue. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + 800b1b4: 4829 ldr r0, [pc, #164] ; (800b25c ) + 800b1b6: f7fd faf7 bl 80087a8 + 800b1ba: 61b8 str r0, [r7, #24] + if (cseg != NULL) { + 800b1bc: 69bb ldr r3, [r7, #24] + 800b1be: 2b00 cmp r3, #0 + 800b1c0: f000 8129 beq.w 800b416 + pcb->ooseq = cseg; + 800b1c4: 687b ldr r3, [r7, #4] + 800b1c6: 69ba ldr r2, [r7, #24] + 800b1c8: 675a str r2, [r3, #116] ; 0x74 + tcp_oos_insert_segment(cseg, next); + 800b1ca: 6bb9 ldr r1, [r7, #56] ; 0x38 + 800b1cc: 69b8 ldr r0, [r7, #24] + 800b1ce: f7ff f8c1 bl 800a354 + } + break; + 800b1d2: e120 b.n 800b416 + } + } else { + /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && + TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ + if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) { + 800b1d4: 4b22 ldr r3, [pc, #136] ; (800b260 ) + 800b1d6: 681a ldr r2, [r3, #0] + 800b1d8: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b1da: 691b ldr r3, [r3, #16] + 800b1dc: 685b ldr r3, [r3, #4] + 800b1de: 1ad3 subs r3, r2, r3 + 800b1e0: 3b01 subs r3, #1 + 800b1e2: 2b00 cmp r3, #0 + 800b1e4: db3e blt.n 800b264 + 800b1e6: 4b1e ldr r3, [pc, #120] ; (800b260 ) + 800b1e8: 681a ldr r2, [r3, #0] + 800b1ea: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b1ec: 691b ldr r3, [r3, #16] + 800b1ee: 685b ldr r3, [r3, #4] + 800b1f0: 1ad3 subs r3, r2, r3 + 800b1f2: 3301 adds r3, #1 + 800b1f4: 2b00 cmp r3, #0 + 800b1f6: dc35 bgt.n 800b264 + /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim trim the previous + segment, delete next segments that included in received segment + and trim received, if needed. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + 800b1f8: 4818 ldr r0, [pc, #96] ; (800b25c ) + 800b1fa: f7fd fad5 bl 80087a8 + 800b1fe: 61f8 str r0, [r7, #28] + if (cseg != NULL) { + 800b200: 69fb ldr r3, [r7, #28] + 800b202: 2b00 cmp r3, #0 + 800b204: f000 8109 beq.w 800b41a + if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { + 800b208: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b20a: 691b ldr r3, [r3, #16] + 800b20c: 685b ldr r3, [r3, #4] + 800b20e: 6b7a ldr r2, [r7, #52] ; 0x34 + 800b210: 8912 ldrh r2, [r2, #8] + 800b212: 441a add r2, r3 + 800b214: 4b12 ldr r3, [pc, #72] ; (800b260 ) + 800b216: 681b ldr r3, [r3, #0] + 800b218: 1ad3 subs r3, r2, r3 + 800b21a: 2b00 cmp r3, #0 + 800b21c: dd12 ble.n 800b244 + /* We need to trim the prev segment. */ + prev->len = (u16_t)(seqno - prev->tcphdr->seqno); + 800b21e: 4b10 ldr r3, [pc, #64] ; (800b260 ) + 800b220: 681b ldr r3, [r3, #0] + 800b222: b29a uxth r2, r3 + 800b224: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b226: 691b ldr r3, [r3, #16] + 800b228: 685b ldr r3, [r3, #4] + 800b22a: b29b uxth r3, r3 + 800b22c: 1ad3 subs r3, r2, r3 + 800b22e: b29a uxth r2, r3 + 800b230: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b232: 811a strh r2, [r3, #8] + pbuf_realloc(prev->p, prev->len); + 800b234: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b236: 685a ldr r2, [r3, #4] + 800b238: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b23a: 891b ldrh r3, [r3, #8] + 800b23c: 4619 mov r1, r3 + 800b23e: 4610 mov r0, r2 + 800b240: f7fb fd42 bl 8006cc8 + } + prev->next = cseg; + 800b244: 6b7b ldr r3, [r7, #52] ; 0x34 + 800b246: 69fa ldr r2, [r7, #28] + 800b248: 601a str r2, [r3, #0] + tcp_oos_insert_segment(cseg, next); + 800b24a: 6bb9 ldr r1, [r7, #56] ; 0x38 + 800b24c: 69f8 ldr r0, [r7, #28] + 800b24e: f7ff f881 bl 800a354 + } + break; + 800b252: e0e2 b.n 800b41a + 800b254: 24007bb8 .word 0x24007bb8 + 800b258: 24007bb5 .word 0x24007bb5 + 800b25c: 24007b84 .word 0x24007b84 + 800b260: 24007ba8 .word 0x24007ba8 +#endif /* LWIP_TCP_SACK_OUT */ + + /* We don't use 'prev' below, so let's set it to current 'next'. + This way even if we break the loop below, 'prev' will be pointing + at the segment right in front of the newly added one. */ + prev = next; + 800b264: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b266: 637b str r3, [r7, #52] ; 0x34 + + /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ + if (next->next == NULL && + 800b268: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b26a: 681b ldr r3, [r3, #0] + 800b26c: 2b00 cmp r3, #0 + 800b26e: f040 80c6 bne.w 800b3fe + TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { + 800b272: 4b80 ldr r3, [pc, #512] ; (800b474 ) + 800b274: 681a ldr r2, [r3, #0] + 800b276: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b278: 691b ldr r3, [r3, #16] + 800b27a: 685b ldr r3, [r3, #4] + 800b27c: 1ad3 subs r3, r2, r3 + if (next->next == NULL && + 800b27e: 2b00 cmp r3, #0 + 800b280: f340 80bd ble.w 800b3fe + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + 800b284: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b286: 691b ldr r3, [r3, #16] + 800b288: 899b ldrh r3, [r3, #12] + 800b28a: b29b uxth r3, r3 + 800b28c: 4618 mov r0, r3 + 800b28e: f7fa f95d bl 800554c + 800b292: 4603 mov r3, r0 + 800b294: b2db uxtb r3, r3 + 800b296: f003 0301 and.w r3, r3, #1 + 800b29a: 2b00 cmp r3, #0 + 800b29c: f040 80bf bne.w 800b41e + /* segment "next" already contains all data */ + break; + } + next->next = tcp_seg_copy(&inseg); + 800b2a0: 4875 ldr r0, [pc, #468] ; (800b478 ) + 800b2a2: f7fd fa81 bl 80087a8 + 800b2a6: 4602 mov r2, r0 + 800b2a8: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b2aa: 601a str r2, [r3, #0] + if (next->next != NULL) { + 800b2ac: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b2ae: 681b ldr r3, [r3, #0] + 800b2b0: 2b00 cmp r3, #0 + 800b2b2: f000 80b6 beq.w 800b422 + if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { + 800b2b6: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b2b8: 691b ldr r3, [r3, #16] + 800b2ba: 685b ldr r3, [r3, #4] + 800b2bc: 6bba ldr r2, [r7, #56] ; 0x38 + 800b2be: 8912 ldrh r2, [r2, #8] + 800b2c0: 441a add r2, r3 + 800b2c2: 4b6c ldr r3, [pc, #432] ; (800b474 ) + 800b2c4: 681b ldr r3, [r3, #0] + 800b2c6: 1ad3 subs r3, r2, r3 + 800b2c8: 2b00 cmp r3, #0 + 800b2ca: dd12 ble.n 800b2f2 + /* We need to trim the last segment. */ + next->len = (u16_t)(seqno - next->tcphdr->seqno); + 800b2cc: 4b69 ldr r3, [pc, #420] ; (800b474 ) + 800b2ce: 681b ldr r3, [r3, #0] + 800b2d0: b29a uxth r2, r3 + 800b2d2: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b2d4: 691b ldr r3, [r3, #16] + 800b2d6: 685b ldr r3, [r3, #4] + 800b2d8: b29b uxth r3, r3 + 800b2da: 1ad3 subs r3, r2, r3 + 800b2dc: b29a uxth r2, r3 + 800b2de: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b2e0: 811a strh r2, [r3, #8] + pbuf_realloc(next->p, next->len); + 800b2e2: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b2e4: 685a ldr r2, [r3, #4] + 800b2e6: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b2e8: 891b ldrh r3, [r3, #8] + 800b2ea: 4619 mov r1, r3 + 800b2ec: 4610 mov r0, r2 + 800b2ee: f7fb fceb bl 8006cc8 + } + /* check if the remote side overruns our receive window */ + if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) { + 800b2f2: 4b62 ldr r3, [pc, #392] ; (800b47c ) + 800b2f4: 881b ldrh r3, [r3, #0] + 800b2f6: 461a mov r2, r3 + 800b2f8: 4b5e ldr r3, [pc, #376] ; (800b474 ) + 800b2fa: 681b ldr r3, [r3, #0] + 800b2fc: 441a add r2, r3 + 800b2fe: 687b ldr r3, [r7, #4] + 800b300: 6a5b ldr r3, [r3, #36] ; 0x24 + 800b302: 6879 ldr r1, [r7, #4] + 800b304: 8d09 ldrh r1, [r1, #40] ; 0x28 + 800b306: 440b add r3, r1 + 800b308: 1ad3 subs r3, r2, r3 + 800b30a: 2b00 cmp r3, #0 + 800b30c: f340 8089 ble.w 800b422 + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) { + 800b310: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b312: 681b ldr r3, [r3, #0] + 800b314: 691b ldr r3, [r3, #16] + 800b316: 899b ldrh r3, [r3, #12] + 800b318: b29b uxth r3, r3 + 800b31a: 4618 mov r0, r3 + 800b31c: f7fa f916 bl 800554c + 800b320: 4603 mov r3, r0 + 800b322: b2db uxtb r3, r3 + 800b324: f003 0301 and.w r3, r3, #1 + 800b328: 2b00 cmp r3, #0 + 800b32a: d022 beq.n 800b372 + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN); + 800b32c: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b32e: 681b ldr r3, [r3, #0] + 800b330: 691b ldr r3, [r3, #16] + 800b332: 899b ldrh r3, [r3, #12] + 800b334: b29b uxth r3, r3 + 800b336: b21b sxth r3, r3 + 800b338: f423 537c bic.w r3, r3, #16128 ; 0x3f00 + 800b33c: b21c sxth r4, r3 + 800b33e: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b340: 681b ldr r3, [r3, #0] + 800b342: 691b ldr r3, [r3, #16] + 800b344: 899b ldrh r3, [r3, #12] + 800b346: b29b uxth r3, r3 + 800b348: 4618 mov r0, r3 + 800b34a: f7fa f8ff bl 800554c + 800b34e: 4603 mov r3, r0 + 800b350: b2db uxtb r3, r3 + 800b352: b29b uxth r3, r3 + 800b354: f003 033e and.w r3, r3, #62 ; 0x3e + 800b358: b29b uxth r3, r3 + 800b35a: 4618 mov r0, r3 + 800b35c: f7fa f8f6 bl 800554c + 800b360: 4603 mov r3, r0 + 800b362: b21b sxth r3, r3 + 800b364: 4323 orrs r3, r4 + 800b366: b21a sxth r2, r3 + 800b368: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b36a: 681b ldr r3, [r3, #0] + 800b36c: 691b ldr r3, [r3, #16] + 800b36e: b292 uxth r2, r2 + 800b370: 819a strh r2, [r3, #12] + } + /* Adjust length of segment to fit in the window. */ + next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno); + 800b372: 687b ldr r3, [r7, #4] + 800b374: 6a5b ldr r3, [r3, #36] ; 0x24 + 800b376: b29a uxth r2, r3 + 800b378: 687b ldr r3, [r7, #4] + 800b37a: 8d1b ldrh r3, [r3, #40] ; 0x28 + 800b37c: 4413 add r3, r2 + 800b37e: b299 uxth r1, r3 + 800b380: 4b3c ldr r3, [pc, #240] ; (800b474 ) + 800b382: 681b ldr r3, [r3, #0] + 800b384: b29a uxth r2, r3 + 800b386: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b388: 681b ldr r3, [r3, #0] + 800b38a: 1a8a subs r2, r1, r2 + 800b38c: b292 uxth r2, r2 + 800b38e: 811a strh r2, [r3, #8] + pbuf_realloc(next->next->p, next->next->len); + 800b390: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b392: 681b ldr r3, [r3, #0] + 800b394: 685a ldr r2, [r3, #4] + 800b396: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b398: 681b ldr r3, [r3, #0] + 800b39a: 891b ldrh r3, [r3, #8] + 800b39c: 4619 mov r1, r3 + 800b39e: 4610 mov r0, r2 + 800b3a0: f7fb fc92 bl 8006cc8 + tcplen = TCP_TCPLEN(next->next); + 800b3a4: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b3a6: 681b ldr r3, [r3, #0] + 800b3a8: 891c ldrh r4, [r3, #8] + 800b3aa: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b3ac: 681b ldr r3, [r3, #0] + 800b3ae: 691b ldr r3, [r3, #16] + 800b3b0: 899b ldrh r3, [r3, #12] + 800b3b2: b29b uxth r3, r3 + 800b3b4: 4618 mov r0, r3 + 800b3b6: f7fa f8c9 bl 800554c + 800b3ba: 4603 mov r3, r0 + 800b3bc: b2db uxtb r3, r3 + 800b3be: f003 0303 and.w r3, r3, #3 + 800b3c2: 2b00 cmp r3, #0 + 800b3c4: d001 beq.n 800b3ca + 800b3c6: 2301 movs r3, #1 + 800b3c8: e000 b.n 800b3cc + 800b3ca: 2300 movs r3, #0 + 800b3cc: 4423 add r3, r4 + 800b3ce: b29a uxth r2, r3 + 800b3d0: 4b2a ldr r3, [pc, #168] ; (800b47c ) + 800b3d2: 801a strh r2, [r3, #0] + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + 800b3d4: 4b29 ldr r3, [pc, #164] ; (800b47c ) + 800b3d6: 881b ldrh r3, [r3, #0] + 800b3d8: 461a mov r2, r3 + 800b3da: 4b26 ldr r3, [pc, #152] ; (800b474 ) + 800b3dc: 681b ldr r3, [r3, #0] + 800b3de: 441a add r2, r3 + 800b3e0: 687b ldr r3, [r7, #4] + 800b3e2: 6a5b ldr r3, [r3, #36] ; 0x24 + 800b3e4: 6879 ldr r1, [r7, #4] + 800b3e6: 8d09 ldrh r1, [r1, #40] ; 0x28 + 800b3e8: 440b add r3, r1 + 800b3ea: 429a cmp r2, r3 + 800b3ec: d019 beq.n 800b422 + 800b3ee: 4b24 ldr r3, [pc, #144] ; (800b480 ) + 800b3f0: f44f 62df mov.w r2, #1784 ; 0x6f8 + 800b3f4: 4923 ldr r1, [pc, #140] ; (800b484 ) + 800b3f6: 4824 ldr r0, [pc, #144] ; (800b488 ) + 800b3f8: f005 fbe6 bl 8010bc8 + (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); + } + } + break; + 800b3fc: e011 b.n 800b422 + for (next = pcb->ooseq; next != NULL; next = next->next) { + 800b3fe: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b400: 681b ldr r3, [r3, #0] + 800b402: 63bb str r3, [r7, #56] ; 0x38 + 800b404: 6bbb ldr r3, [r7, #56] ; 0x38 + 800b406: 2b00 cmp r3, #0 + 800b408: f47f aea4 bne.w 800b154 + 800b40c: e00a b.n 800b424 + break; + 800b40e: bf00 nop + 800b410: e008 b.n 800b424 + break; + 800b412: bf00 nop + 800b414: e006 b.n 800b424 + break; + 800b416: bf00 nop + 800b418: e004 b.n 800b424 + break; + 800b41a: bf00 nop + 800b41c: e002 b.n 800b424 + break; + 800b41e: bf00 nop + 800b420: e000 b.n 800b424 + break; + 800b422: bf00 nop +#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */ +#endif /* TCP_QUEUE_OOSEQ */ + + /* We send the ACK packet after we've (potentially) dealt with SACKs, + so they can be included in the acknowledgment. */ + tcp_send_empty_ack(pcb); + 800b424: 6878 ldr r0, [r7, #4] + 800b426: f001 fef7 bl 800d218 + if (pcb->rcv_nxt == seqno) { + 800b42a: e003 b.n 800b434 + } + } else { + /* The incoming segment is not within the window. */ + tcp_send_empty_ack(pcb); + 800b42c: 6878 ldr r0, [r7, #4] + 800b42e: f001 fef3 bl 800d218 + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + 800b432: e01a b.n 800b46a + 800b434: e019 b.n 800b46a + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ + if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) { + 800b436: 4b0f ldr r3, [pc, #60] ; (800b474 ) + 800b438: 681a ldr r2, [r3, #0] + 800b43a: 687b ldr r3, [r7, #4] + 800b43c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800b43e: 1ad3 subs r3, r2, r3 + 800b440: 2b00 cmp r3, #0 + 800b442: db0a blt.n 800b45a + 800b444: 4b0b ldr r3, [pc, #44] ; (800b474 ) + 800b446: 681a ldr r2, [r3, #0] + 800b448: 687b ldr r3, [r7, #4] + 800b44a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800b44c: 6879 ldr r1, [r7, #4] + 800b44e: 8d09 ldrh r1, [r1, #40] ; 0x28 + 800b450: 440b add r3, r1 + 800b452: 1ad3 subs r3, r2, r3 + 800b454: 3301 adds r3, #1 + 800b456: 2b00 cmp r3, #0 + 800b458: dd07 ble.n 800b46a + tcp_ack_now(pcb); + 800b45a: 687b ldr r3, [r7, #4] + 800b45c: 8b5b ldrh r3, [r3, #26] + 800b45e: f043 0302 orr.w r3, r3, #2 + 800b462: b29a uxth r2, r3 + 800b464: 687b ldr r3, [r7, #4] + 800b466: 835a strh r2, [r3, #26] + } + } +} + 800b468: e7ff b.n 800b46a + 800b46a: bf00 nop + 800b46c: 3750 adds r7, #80 ; 0x50 + 800b46e: 46bd mov sp, r7 + 800b470: bdb0 pop {r4, r5, r7, pc} + 800b472: bf00 nop + 800b474: 24007ba8 .word 0x24007ba8 + 800b478: 24007b84 .word 0x24007b84 + 800b47c: 24007bb2 .word 0x24007bb2 + 800b480: 08013198 .word 0x08013198 + 800b484: 08013540 .word 0x08013540 + 800b488: 080131e4 .word 0x080131e4 + +0800b48c : + +static u8_t +tcp_get_next_optbyte(void) +{ + 800b48c: b480 push {r7} + 800b48e: b083 sub sp, #12 + 800b490: af00 add r7, sp, #0 + u16_t optidx = tcp_optidx++; + 800b492: 4b15 ldr r3, [pc, #84] ; (800b4e8 ) + 800b494: 881b ldrh r3, [r3, #0] + 800b496: 1c5a adds r2, r3, #1 + 800b498: b291 uxth r1, r2 + 800b49a: 4a13 ldr r2, [pc, #76] ; (800b4e8 ) + 800b49c: 8011 strh r1, [r2, #0] + 800b49e: 80fb strh r3, [r7, #6] + if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) { + 800b4a0: 4b12 ldr r3, [pc, #72] ; (800b4ec ) + 800b4a2: 681b ldr r3, [r3, #0] + 800b4a4: 2b00 cmp r3, #0 + 800b4a6: d004 beq.n 800b4b2 + 800b4a8: 4b11 ldr r3, [pc, #68] ; (800b4f0 ) + 800b4aa: 881b ldrh r3, [r3, #0] + 800b4ac: 88fa ldrh r2, [r7, #6] + 800b4ae: 429a cmp r2, r3 + 800b4b0: d208 bcs.n 800b4c4 + u8_t *opts = (u8_t *)tcphdr + TCP_HLEN; + 800b4b2: 4b10 ldr r3, [pc, #64] ; (800b4f4 ) + 800b4b4: 681b ldr r3, [r3, #0] + 800b4b6: 3314 adds r3, #20 + 800b4b8: 603b str r3, [r7, #0] + return opts[optidx]; + 800b4ba: 88fb ldrh r3, [r7, #6] + 800b4bc: 683a ldr r2, [r7, #0] + 800b4be: 4413 add r3, r2 + 800b4c0: 781b ldrb r3, [r3, #0] + 800b4c2: e00b b.n 800b4dc + } else { + u8_t idx = (u8_t)(optidx - tcphdr_opt1len); + 800b4c4: 88fb ldrh r3, [r7, #6] + 800b4c6: b2da uxtb r2, r3 + 800b4c8: 4b09 ldr r3, [pc, #36] ; (800b4f0 ) + 800b4ca: 881b ldrh r3, [r3, #0] + 800b4cc: b2db uxtb r3, r3 + 800b4ce: 1ad3 subs r3, r2, r3 + 800b4d0: 717b strb r3, [r7, #5] + return tcphdr_opt2[idx]; + 800b4d2: 4b06 ldr r3, [pc, #24] ; (800b4ec ) + 800b4d4: 681a ldr r2, [r3, #0] + 800b4d6: 797b ldrb r3, [r7, #5] + 800b4d8: 4413 add r3, r2 + 800b4da: 781b ldrb r3, [r3, #0] + } +} + 800b4dc: 4618 mov r0, r3 + 800b4de: 370c adds r7, #12 + 800b4e0: 46bd mov sp, r7 + 800b4e2: f85d 7b04 ldr.w r7, [sp], #4 + 800b4e6: 4770 bx lr + 800b4e8: 24007ba4 .word 0x24007ba4 + 800b4ec: 24007ba0 .word 0x24007ba0 + 800b4f0: 24007b9e .word 0x24007b9e + 800b4f4: 24007b98 .word 0x24007b98 + +0800b4f8 : + * + * @param pcb the tcp_pcb for which a segment arrived + */ +static void +tcp_parseopt(struct tcp_pcb *pcb) +{ + 800b4f8: b580 push {r7, lr} + 800b4fa: b084 sub sp, #16 + 800b4fc: af00 add r7, sp, #0 + 800b4fe: 6078 str r0, [r7, #4] + u16_t mss; +#if LWIP_TCP_TIMESTAMPS + u32_t tsval; +#endif + + LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL); + 800b500: 687b ldr r3, [r7, #4] + 800b502: 2b00 cmp r3, #0 + 800b504: d106 bne.n 800b514 + 800b506: 4b32 ldr r3, [pc, #200] ; (800b5d0 ) + 800b508: f240 727d movw r2, #1917 ; 0x77d + 800b50c: 4931 ldr r1, [pc, #196] ; (800b5d4 ) + 800b50e: 4832 ldr r0, [pc, #200] ; (800b5d8 ) + 800b510: f005 fb5a bl 8010bc8 + + /* Parse the TCP MSS option, if present. */ + if (tcphdr_optlen != 0) { + 800b514: 4b31 ldr r3, [pc, #196] ; (800b5dc ) + 800b516: 881b ldrh r3, [r3, #0] + 800b518: 2b00 cmp r3, #0 + 800b51a: d055 beq.n 800b5c8 + for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { + 800b51c: 4b30 ldr r3, [pc, #192] ; (800b5e0 ) + 800b51e: 2200 movs r2, #0 + 800b520: 801a strh r2, [r3, #0] + 800b522: e045 b.n 800b5b0 + u8_t opt = tcp_get_next_optbyte(); + 800b524: f7ff ffb2 bl 800b48c + 800b528: 4603 mov r3, r0 + 800b52a: 73fb strb r3, [r7, #15] + switch (opt) { + 800b52c: 7bfb ldrb r3, [r7, #15] + 800b52e: 2b02 cmp r3, #2 + 800b530: d006 beq.n 800b540 + 800b532: 2b02 cmp r3, #2 + 800b534: dc2b bgt.n 800b58e + 800b536: 2b00 cmp r3, #0 + 800b538: d041 beq.n 800b5be + 800b53a: 2b01 cmp r3, #1 + 800b53c: d127 bne.n 800b58e + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); + return; + case LWIP_TCP_OPT_NOP: + /* NOP option. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); + break; + 800b53e: e037 b.n 800b5b0 + case LWIP_TCP_OPT_MSS: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); + if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) { + 800b540: f7ff ffa4 bl 800b48c + 800b544: 4603 mov r3, r0 + 800b546: 2b04 cmp r3, #4 + 800b548: d13b bne.n 800b5c2 + 800b54a: 4b25 ldr r3, [pc, #148] ; (800b5e0 ) + 800b54c: 881b ldrh r3, [r3, #0] + 800b54e: 3301 adds r3, #1 + 800b550: 4a22 ldr r2, [pc, #136] ; (800b5dc ) + 800b552: 8812 ldrh r2, [r2, #0] + 800b554: 4293 cmp r3, r2 + 800b556: da34 bge.n 800b5c2 + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* An MSS option with the right option length. */ + mss = (u16_t)(tcp_get_next_optbyte() << 8); + 800b558: f7ff ff98 bl 800b48c + 800b55c: 4603 mov r3, r0 + 800b55e: b29b uxth r3, r3 + 800b560: 021b lsls r3, r3, #8 + 800b562: 81bb strh r3, [r7, #12] + mss |= tcp_get_next_optbyte(); + 800b564: f7ff ff92 bl 800b48c + 800b568: 4603 mov r3, r0 + 800b56a: b29a uxth r2, r3 + 800b56c: 89bb ldrh r3, [r7, #12] + 800b56e: 4313 orrs r3, r2 + 800b570: 81bb strh r3, [r7, #12] + /* Limit the mss to the configured TCP_MSS and prevent division by zero */ + pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; + 800b572: 89bb ldrh r3, [r7, #12] + 800b574: f5b3 7f06 cmp.w r3, #536 ; 0x218 + 800b578: d804 bhi.n 800b584 + 800b57a: 89bb ldrh r3, [r7, #12] + 800b57c: 2b00 cmp r3, #0 + 800b57e: d001 beq.n 800b584 + 800b580: 89ba ldrh r2, [r7, #12] + 800b582: e001 b.n 800b588 + 800b584: f44f 7206 mov.w r2, #536 ; 0x218 + 800b588: 687b ldr r3, [r7, #4] + 800b58a: 865a strh r2, [r3, #50] ; 0x32 + break; + 800b58c: e010 b.n 800b5b0 + } + break; +#endif /* LWIP_TCP_SACK_OUT */ + default: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); + data = tcp_get_next_optbyte(); + 800b58e: f7ff ff7d bl 800b48c + 800b592: 4603 mov r3, r0 + 800b594: 72fb strb r3, [r7, #11] + if (data < 2) { + 800b596: 7afb ldrb r3, [r7, #11] + 800b598: 2b01 cmp r3, #1 + 800b59a: d914 bls.n 800b5c6 + and we don't process them further. */ + return; + } + /* All other options have a length field, so that we easily + can skip past them. */ + tcp_optidx += data - 2; + 800b59c: 7afb ldrb r3, [r7, #11] + 800b59e: b29a uxth r2, r3 + 800b5a0: 4b0f ldr r3, [pc, #60] ; (800b5e0 ) + 800b5a2: 881b ldrh r3, [r3, #0] + 800b5a4: 4413 add r3, r2 + 800b5a6: b29b uxth r3, r3 + 800b5a8: 3b02 subs r3, #2 + 800b5aa: b29a uxth r2, r3 + 800b5ac: 4b0c ldr r3, [pc, #48] ; (800b5e0 ) + 800b5ae: 801a strh r2, [r3, #0] + for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { + 800b5b0: 4b0b ldr r3, [pc, #44] ; (800b5e0 ) + 800b5b2: 881a ldrh r2, [r3, #0] + 800b5b4: 4b09 ldr r3, [pc, #36] ; (800b5dc ) + 800b5b6: 881b ldrh r3, [r3, #0] + 800b5b8: 429a cmp r2, r3 + 800b5ba: d3b3 bcc.n 800b524 + 800b5bc: e004 b.n 800b5c8 + return; + 800b5be: bf00 nop + 800b5c0: e002 b.n 800b5c8 + return; + 800b5c2: bf00 nop + 800b5c4: e000 b.n 800b5c8 + return; + 800b5c6: bf00 nop + } + } + } +} + 800b5c8: 3710 adds r7, #16 + 800b5ca: 46bd mov sp, r7 + 800b5cc: bd80 pop {r7, pc} + 800b5ce: bf00 nop + 800b5d0: 08013198 .word 0x08013198 + 800b5d4: 080135fc .word 0x080135fc + 800b5d8: 080131e4 .word 0x080131e4 + 800b5dc: 24007b9c .word 0x24007b9c + 800b5e0: 24007ba4 .word 0x24007ba4 + +0800b5e4 : + +void +tcp_trigger_input_pcb_close(void) +{ + 800b5e4: b480 push {r7} + 800b5e6: af00 add r7, sp, #0 + recv_flags |= TF_CLOSED; + 800b5e8: 4b05 ldr r3, [pc, #20] ; (800b600 ) + 800b5ea: 781b ldrb r3, [r3, #0] + 800b5ec: f043 0310 orr.w r3, r3, #16 + 800b5f0: b2da uxtb r2, r3 + 800b5f2: 4b03 ldr r3, [pc, #12] ; (800b600 ) + 800b5f4: 701a strb r2, [r3, #0] +} + 800b5f6: bf00 nop + 800b5f8: 46bd mov sp, r7 + 800b5fa: f85d 7b04 ldr.w r7, [sp], #4 + 800b5fe: 4770 bx lr + 800b600: 24007bb5 .word 0x24007bb5 + +0800b604 : +static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif); + +/* tcp_route: common code that returns a fixed bound netif or calls ip_route */ +static struct netif * +tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst) +{ + 800b604: b580 push {r7, lr} + 800b606: b084 sub sp, #16 + 800b608: af00 add r7, sp, #0 + 800b60a: 60f8 str r0, [r7, #12] + 800b60c: 60b9 str r1, [r7, #8] + 800b60e: 607a str r2, [r7, #4] + LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */ + + if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) { + 800b610: 68fb ldr r3, [r7, #12] + 800b612: 2b00 cmp r3, #0 + 800b614: d00a beq.n 800b62c + 800b616: 68fb ldr r3, [r7, #12] + 800b618: 7a1b ldrb r3, [r3, #8] + 800b61a: 2b00 cmp r3, #0 + 800b61c: d006 beq.n 800b62c + return netif_get_by_index(pcb->netif_idx); + 800b61e: 68fb ldr r3, [r7, #12] + 800b620: 7a1b ldrb r3, [r3, #8] + 800b622: 4618 mov r0, r3 + 800b624: f7fb f976 bl 8006914 + 800b628: 4603 mov r3, r0 + 800b62a: e003 b.n 800b634 + } else { + return ip_route(src, dst); + 800b62c: 6878 ldr r0, [r7, #4] + 800b62e: f003 fc2b bl 800ee88 + 800b632: 4603 mov r3, r0 + } +} + 800b634: 4618 mov r0, r3 + 800b636: 3710 adds r7, #16 + 800b638: 46bd mov sp, r7 + 800b63a: bd80 pop {r7, pc} + +0800b63c : + * The TCP header is filled in except ackno and wnd. + * p is freed on failure. + */ +static struct tcp_seg * +tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags) +{ + 800b63c: b590 push {r4, r7, lr} + 800b63e: b087 sub sp, #28 + 800b640: af00 add r7, sp, #0 + 800b642: 60f8 str r0, [r7, #12] + 800b644: 60b9 str r1, [r7, #8] + 800b646: 603b str r3, [r7, #0] + 800b648: 4613 mov r3, r2 + 800b64a: 71fb strb r3, [r7, #7] + struct tcp_seg *seg; + u8_t optlen; + + LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL); + 800b64c: 68fb ldr r3, [r7, #12] + 800b64e: 2b00 cmp r3, #0 + 800b650: d105 bne.n 800b65e + 800b652: 4b45 ldr r3, [pc, #276] ; (800b768 ) + 800b654: 22a3 movs r2, #163 ; 0xa3 + 800b656: 4945 ldr r1, [pc, #276] ; (800b76c ) + 800b658: 4845 ldr r0, [pc, #276] ; (800b770 ) + 800b65a: f005 fab5 bl 8010bc8 + LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL); + 800b65e: 68bb ldr r3, [r7, #8] + 800b660: 2b00 cmp r3, #0 + 800b662: d105 bne.n 800b670 + 800b664: 4b40 ldr r3, [pc, #256] ; (800b768 ) + 800b666: 22a4 movs r2, #164 ; 0xa4 + 800b668: 4942 ldr r1, [pc, #264] ; (800b774 ) + 800b66a: 4841 ldr r0, [pc, #260] ; (800b770 ) + 800b66c: f005 faac bl 8010bc8 + + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + 800b670: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 800b674: 009b lsls r3, r3, #2 + 800b676: b2db uxtb r3, r3 + 800b678: f003 0304 and.w r3, r3, #4 + 800b67c: 75fb strb r3, [r7, #23] + + if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) { + 800b67e: 2003 movs r0, #3 + 800b680: f7fa fccc bl 800601c + 800b684: 6138 str r0, [r7, #16] + 800b686: 693b ldr r3, [r7, #16] + 800b688: 2b00 cmp r3, #0 + 800b68a: d104 bne.n 800b696 + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n")); + pbuf_free(p); + 800b68c: 68b8 ldr r0, [r7, #8] + 800b68e: f7fb fca1 bl 8006fd4 + return NULL; + 800b692: 2300 movs r3, #0 + 800b694: e064 b.n 800b760 + } + seg->flags = optflags; + 800b696: 693b ldr r3, [r7, #16] + 800b698: f897 2028 ldrb.w r2, [r7, #40] ; 0x28 + 800b69c: 731a strb r2, [r3, #12] + seg->next = NULL; + 800b69e: 693b ldr r3, [r7, #16] + 800b6a0: 2200 movs r2, #0 + 800b6a2: 601a str r2, [r3, #0] + seg->p = p; + 800b6a4: 693b ldr r3, [r7, #16] + 800b6a6: 68ba ldr r2, [r7, #8] + 800b6a8: 605a str r2, [r3, #4] + LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen); + 800b6aa: 68bb ldr r3, [r7, #8] + 800b6ac: 891a ldrh r2, [r3, #8] + 800b6ae: 7dfb ldrb r3, [r7, #23] + 800b6b0: b29b uxth r3, r3 + 800b6b2: 429a cmp r2, r3 + 800b6b4: d205 bcs.n 800b6c2 + 800b6b6: 4b2c ldr r3, [pc, #176] ; (800b768 ) + 800b6b8: 22b0 movs r2, #176 ; 0xb0 + 800b6ba: 492f ldr r1, [pc, #188] ; (800b778 ) + 800b6bc: 482c ldr r0, [pc, #176] ; (800b770 ) + 800b6be: f005 fa83 bl 8010bc8 + seg->len = p->tot_len - optlen; + 800b6c2: 68bb ldr r3, [r7, #8] + 800b6c4: 891a ldrh r2, [r3, #8] + 800b6c6: 7dfb ldrb r3, [r7, #23] + 800b6c8: b29b uxth r3, r3 + 800b6ca: 1ad3 subs r3, r2, r3 + 800b6cc: b29a uxth r2, r3 + 800b6ce: 693b ldr r3, [r7, #16] + 800b6d0: 811a strh r2, [r3, #8] +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = 0; + 800b6d2: 693b ldr r3, [r7, #16] + 800b6d4: 2200 movs r2, #0 + 800b6d6: 815a strh r2, [r3, #10] + LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED", + (optflags & TF_SEG_DATA_CHECKSUMMED) == 0); +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* build TCP header */ + if (pbuf_add_header(p, TCP_HLEN)) { + 800b6d8: 2114 movs r1, #20 + 800b6da: 68b8 ldr r0, [r7, #8] + 800b6dc: f7fb fbe4 bl 8006ea8 + 800b6e0: 4603 mov r3, r0 + 800b6e2: 2b00 cmp r3, #0 + 800b6e4: d004 beq.n 800b6f0 + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n")); + TCP_STATS_INC(tcp.err); + tcp_seg_free(seg); + 800b6e6: 6938 ldr r0, [r7, #16] + 800b6e8: f7fd f845 bl 8008776 + return NULL; + 800b6ec: 2300 movs r3, #0 + 800b6ee: e037 b.n 800b760 + } + seg->tcphdr = (struct tcp_hdr *)seg->p->payload; + 800b6f0: 693b ldr r3, [r7, #16] + 800b6f2: 685b ldr r3, [r3, #4] + 800b6f4: 685a ldr r2, [r3, #4] + 800b6f6: 693b ldr r3, [r7, #16] + 800b6f8: 611a str r2, [r3, #16] + seg->tcphdr->src = lwip_htons(pcb->local_port); + 800b6fa: 68fb ldr r3, [r7, #12] + 800b6fc: 8ada ldrh r2, [r3, #22] + 800b6fe: 693b ldr r3, [r7, #16] + 800b700: 691c ldr r4, [r3, #16] + 800b702: 4610 mov r0, r2 + 800b704: f7f9 ff22 bl 800554c + 800b708: 4603 mov r3, r0 + 800b70a: 8023 strh r3, [r4, #0] + seg->tcphdr->dest = lwip_htons(pcb->remote_port); + 800b70c: 68fb ldr r3, [r7, #12] + 800b70e: 8b1a ldrh r2, [r3, #24] + 800b710: 693b ldr r3, [r7, #16] + 800b712: 691c ldr r4, [r3, #16] + 800b714: 4610 mov r0, r2 + 800b716: f7f9 ff19 bl 800554c + 800b71a: 4603 mov r3, r0 + 800b71c: 8063 strh r3, [r4, #2] + seg->tcphdr->seqno = lwip_htonl(seqno); + 800b71e: 693b ldr r3, [r7, #16] + 800b720: 691c ldr r4, [r3, #16] + 800b722: 6838 ldr r0, [r7, #0] + 800b724: f7f9 ff27 bl 8005576 + 800b728: 4603 mov r3, r0 + 800b72a: 6063 str r3, [r4, #4] + /* ackno is set in tcp_output */ + TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags); + 800b72c: 7dfb ldrb r3, [r7, #23] + 800b72e: 089b lsrs r3, r3, #2 + 800b730: b2db uxtb r3, r3 + 800b732: b29b uxth r3, r3 + 800b734: 3305 adds r3, #5 + 800b736: b29b uxth r3, r3 + 800b738: 031b lsls r3, r3, #12 + 800b73a: b29a uxth r2, r3 + 800b73c: 79fb ldrb r3, [r7, #7] + 800b73e: b29b uxth r3, r3 + 800b740: 4313 orrs r3, r2 + 800b742: b29a uxth r2, r3 + 800b744: 693b ldr r3, [r7, #16] + 800b746: 691c ldr r4, [r3, #16] + 800b748: 4610 mov r0, r2 + 800b74a: f7f9 feff bl 800554c + 800b74e: 4603 mov r3, r0 + 800b750: 81a3 strh r3, [r4, #12] + /* wnd and chksum are set in tcp_output */ + seg->tcphdr->urgp = 0; + 800b752: 693b ldr r3, [r7, #16] + 800b754: 691b ldr r3, [r3, #16] + 800b756: 2200 movs r2, #0 + 800b758: 749a strb r2, [r3, #18] + 800b75a: 2200 movs r2, #0 + 800b75c: 74da strb r2, [r3, #19] + return seg; + 800b75e: 693b ldr r3, [r7, #16] +} + 800b760: 4618 mov r0, r3 + 800b762: 371c adds r7, #28 + 800b764: 46bd mov sp, r7 + 800b766: bd90 pop {r4, r7, pc} + 800b768: 08013618 .word 0x08013618 + 800b76c: 0801364c .word 0x0801364c + 800b770: 0801366c .word 0x0801366c + 800b774: 08013694 .word 0x08013694 + 800b778: 080136b8 .word 0x080136b8 + +0800b77c : +#if TCP_OVERSIZE +static struct pbuf * +tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length, + u16_t *oversize, const struct tcp_pcb *pcb, u8_t apiflags, + u8_t first_seg) +{ + 800b77c: b580 push {r7, lr} + 800b77e: b086 sub sp, #24 + 800b780: af00 add r7, sp, #0 + 800b782: 607b str r3, [r7, #4] + 800b784: 4603 mov r3, r0 + 800b786: 73fb strb r3, [r7, #15] + 800b788: 460b mov r3, r1 + 800b78a: 81bb strh r3, [r7, #12] + 800b78c: 4613 mov r3, r2 + 800b78e: 817b strh r3, [r7, #10] + struct pbuf *p; + u16_t alloc = length; + 800b790: 89bb ldrh r3, [r7, #12] + 800b792: 82fb strh r3, [r7, #22] + + LWIP_ASSERT("tcp_pbuf_prealloc: invalid oversize", oversize != NULL); + 800b794: 687b ldr r3, [r7, #4] + 800b796: 2b00 cmp r3, #0 + 800b798: d105 bne.n 800b7a6 + 800b79a: 4b30 ldr r3, [pc, #192] ; (800b85c ) + 800b79c: 22e8 movs r2, #232 ; 0xe8 + 800b79e: 4930 ldr r1, [pc, #192] ; (800b860 ) + 800b7a0: 4830 ldr r0, [pc, #192] ; (800b864 ) + 800b7a2: f005 fa11 bl 8010bc8 + LWIP_ASSERT("tcp_pbuf_prealloc: invalid pcb", pcb != NULL); + 800b7a6: 6a3b ldr r3, [r7, #32] + 800b7a8: 2b00 cmp r3, #0 + 800b7aa: d105 bne.n 800b7b8 + 800b7ac: 4b2b ldr r3, [pc, #172] ; (800b85c ) + 800b7ae: 22e9 movs r2, #233 ; 0xe9 + 800b7b0: 492d ldr r1, [pc, #180] ; (800b868 ) + 800b7b2: 482c ldr r0, [pc, #176] ; (800b864 ) + 800b7b4: f005 fa08 bl 8010bc8 + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(apiflags); + LWIP_UNUSED_ARG(first_seg); + alloc = max_length; +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + if (length < max_length) { + 800b7b8: 89ba ldrh r2, [r7, #12] + 800b7ba: 897b ldrh r3, [r7, #10] + 800b7bc: 429a cmp r2, r3 + 800b7be: d221 bcs.n 800b804 + * + * Did the user set TCP_WRITE_FLAG_MORE? + * + * Will the Nagle algorithm defer transmission of this segment? + */ + if ((apiflags & TCP_WRITE_FLAG_MORE) || + 800b7c0: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 800b7c4: f003 0302 and.w r3, r3, #2 + 800b7c8: 2b00 cmp r3, #0 + 800b7ca: d111 bne.n 800b7f0 + (!(pcb->flags & TF_NODELAY) && + 800b7cc: 6a3b ldr r3, [r7, #32] + 800b7ce: 8b5b ldrh r3, [r3, #26] + 800b7d0: f003 0340 and.w r3, r3, #64 ; 0x40 + if ((apiflags & TCP_WRITE_FLAG_MORE) || + 800b7d4: 2b00 cmp r3, #0 + 800b7d6: d115 bne.n 800b804 + (!(pcb->flags & TF_NODELAY) && + 800b7d8: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 800b7dc: 2b00 cmp r3, #0 + 800b7de: d007 beq.n 800b7f0 + (!first_seg || + pcb->unsent != NULL || + 800b7e0: 6a3b ldr r3, [r7, #32] + 800b7e2: 6edb ldr r3, [r3, #108] ; 0x6c + (!first_seg || + 800b7e4: 2b00 cmp r3, #0 + 800b7e6: d103 bne.n 800b7f0 + pcb->unacked != NULL))) { + 800b7e8: 6a3b ldr r3, [r7, #32] + 800b7ea: 6f1b ldr r3, [r3, #112] ; 0x70 + pcb->unsent != NULL || + 800b7ec: 2b00 cmp r3, #0 + 800b7ee: d009 beq.n 800b804 + alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(TCP_OVERSIZE_CALC_LENGTH(length))); + 800b7f0: 89bb ldrh r3, [r7, #12] + 800b7f2: f203 231b addw r3, r3, #539 ; 0x21b + 800b7f6: f023 0203 bic.w r2, r3, #3 + 800b7fa: 897b ldrh r3, [r7, #10] + 800b7fc: 4293 cmp r3, r2 + 800b7fe: bf28 it cs + 800b800: 4613 movcs r3, r2 + 800b802: 82fb strh r3, [r7, #22] + } + } +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + p = pbuf_alloc(layer, alloc, PBUF_RAM); + 800b804: 8af9 ldrh r1, [r7, #22] + 800b806: 7bfb ldrb r3, [r7, #15] + 800b808: f44f 7220 mov.w r2, #640 ; 0x280 + 800b80c: 4618 mov r0, r3 + 800b80e: f7fb f8fd bl 8006a0c + 800b812: 6138 str r0, [r7, #16] + if (p == NULL) { + 800b814: 693b ldr r3, [r7, #16] + 800b816: 2b00 cmp r3, #0 + 800b818: d101 bne.n 800b81e + return NULL; + 800b81a: 2300 movs r3, #0 + 800b81c: e019 b.n 800b852 + } + LWIP_ASSERT("need unchained pbuf", p->next == NULL); + 800b81e: 693b ldr r3, [r7, #16] + 800b820: 681b ldr r3, [r3, #0] + 800b822: 2b00 cmp r3, #0 + 800b824: d006 beq.n 800b834 + 800b826: 4b0d ldr r3, [pc, #52] ; (800b85c ) + 800b828: f240 120b movw r2, #267 ; 0x10b + 800b82c: 490f ldr r1, [pc, #60] ; (800b86c ) + 800b82e: 480d ldr r0, [pc, #52] ; (800b864 ) + 800b830: f005 f9ca bl 8010bc8 + *oversize = p->len - length; + 800b834: 693b ldr r3, [r7, #16] + 800b836: 895a ldrh r2, [r3, #10] + 800b838: 89bb ldrh r3, [r7, #12] + 800b83a: 1ad3 subs r3, r2, r3 + 800b83c: b29a uxth r2, r3 + 800b83e: 687b ldr r3, [r7, #4] + 800b840: 801a strh r2, [r3, #0] + /* trim p->len to the currently used size */ + p->len = p->tot_len = length; + 800b842: 693b ldr r3, [r7, #16] + 800b844: 89ba ldrh r2, [r7, #12] + 800b846: 811a strh r2, [r3, #8] + 800b848: 693b ldr r3, [r7, #16] + 800b84a: 891a ldrh r2, [r3, #8] + 800b84c: 693b ldr r3, [r7, #16] + 800b84e: 815a strh r2, [r3, #10] + return p; + 800b850: 693b ldr r3, [r7, #16] +} + 800b852: 4618 mov r0, r3 + 800b854: 3718 adds r7, #24 + 800b856: 46bd mov sp, r7 + 800b858: bd80 pop {r7, pc} + 800b85a: bf00 nop + 800b85c: 08013618 .word 0x08013618 + 800b860: 080136d0 .word 0x080136d0 + 800b864: 0801366c .word 0x0801366c + 800b868: 080136f4 .word 0x080136f4 + 800b86c: 08013714 .word 0x08013714 + +0800b870 : + * @param len length of data to send (checked agains snd_buf) + * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise + */ +static err_t +tcp_write_checks(struct tcp_pcb *pcb, u16_t len) +{ + 800b870: b580 push {r7, lr} + 800b872: b082 sub sp, #8 + 800b874: af00 add r7, sp, #0 + 800b876: 6078 str r0, [r7, #4] + 800b878: 460b mov r3, r1 + 800b87a: 807b strh r3, [r7, #2] + LWIP_ASSERT("tcp_write_checks: invalid pcb", pcb != NULL); + 800b87c: 687b ldr r3, [r7, #4] + 800b87e: 2b00 cmp r3, #0 + 800b880: d106 bne.n 800b890 + 800b882: 4b33 ldr r3, [pc, #204] ; (800b950 ) + 800b884: f240 1233 movw r2, #307 ; 0x133 + 800b888: 4932 ldr r1, [pc, #200] ; (800b954 ) + 800b88a: 4833 ldr r0, [pc, #204] ; (800b958 ) + 800b88c: f005 f99c bl 8010bc8 + + /* connection is in invalid state for data transmission? */ + if ((pcb->state != ESTABLISHED) && + 800b890: 687b ldr r3, [r7, #4] + 800b892: 7d1b ldrb r3, [r3, #20] + 800b894: 2b04 cmp r3, #4 + 800b896: d00e beq.n 800b8b6 + (pcb->state != CLOSE_WAIT) && + 800b898: 687b ldr r3, [r7, #4] + 800b89a: 7d1b ldrb r3, [r3, #20] + if ((pcb->state != ESTABLISHED) && + 800b89c: 2b07 cmp r3, #7 + 800b89e: d00a beq.n 800b8b6 + (pcb->state != SYN_SENT) && + 800b8a0: 687b ldr r3, [r7, #4] + 800b8a2: 7d1b ldrb r3, [r3, #20] + (pcb->state != CLOSE_WAIT) && + 800b8a4: 2b02 cmp r3, #2 + 800b8a6: d006 beq.n 800b8b6 + (pcb->state != SYN_RCVD)) { + 800b8a8: 687b ldr r3, [r7, #4] + 800b8aa: 7d1b ldrb r3, [r3, #20] + (pcb->state != SYN_SENT) && + 800b8ac: 2b03 cmp r3, #3 + 800b8ae: d002 beq.n 800b8b6 + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n")); + return ERR_CONN; + 800b8b0: f06f 030a mvn.w r3, #10 + 800b8b4: e048 b.n 800b948 + } else if (len == 0) { + 800b8b6: 887b ldrh r3, [r7, #2] + 800b8b8: 2b00 cmp r3, #0 + 800b8ba: d101 bne.n 800b8c0 + return ERR_OK; + 800b8bc: 2300 movs r3, #0 + 800b8be: e043 b.n 800b948 + } + + /* fail on too much data */ + if (len > pcb->snd_buf) { + 800b8c0: 687b ldr r3, [r7, #4] + 800b8c2: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 + 800b8c6: 887a ldrh r2, [r7, #2] + 800b8c8: 429a cmp r2, r3 + 800b8ca: d909 bls.n 800b8e0 + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"TCPWNDSIZE_F")\n", + len, pcb->snd_buf)); + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 800b8cc: 687b ldr r3, [r7, #4] + 800b8ce: 8b5b ldrh r3, [r3, #26] + 800b8d0: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800b8d4: b29a uxth r2, r3 + 800b8d6: 687b ldr r3, [r7, #4] + 800b8d8: 835a strh r2, [r3, #26] + return ERR_MEM; + 800b8da: f04f 33ff mov.w r3, #4294967295 + 800b8de: e033 b.n 800b948 + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); + + /* If total number of pbufs on the unsent/unacked queues exceeds the + * configured maximum, return an error */ + /* check for configured max queuelen and possible overflow */ + if (pcb->snd_queuelen >= LWIP_MIN(TCP_SND_QUEUELEN, (TCP_SNDQUEUELEN_OVERFLOW + 1))) { + 800b8e0: 687b ldr r3, [r7, #4] + 800b8e2: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800b8e6: 2b08 cmp r3, #8 + 800b8e8: d909 bls.n 800b8fe + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n", + pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN)); + TCP_STATS_INC(tcp.memerr); + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 800b8ea: 687b ldr r3, [r7, #4] + 800b8ec: 8b5b ldrh r3, [r3, #26] + 800b8ee: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800b8f2: b29a uxth r2, r3 + 800b8f4: 687b ldr r3, [r7, #4] + 800b8f6: 835a strh r2, [r3, #26] + return ERR_MEM; + 800b8f8: f04f 33ff mov.w r3, #4294967295 + 800b8fc: e024 b.n 800b948 + } + if (pcb->snd_queuelen != 0) { + 800b8fe: 687b ldr r3, [r7, #4] + 800b900: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800b904: 2b00 cmp r3, #0 + 800b906: d00f beq.n 800b928 + LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty", + 800b908: 687b ldr r3, [r7, #4] + 800b90a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800b90c: 2b00 cmp r3, #0 + 800b90e: d11a bne.n 800b946 + 800b910: 687b ldr r3, [r7, #4] + 800b912: 6edb ldr r3, [r3, #108] ; 0x6c + 800b914: 2b00 cmp r3, #0 + 800b916: d116 bne.n 800b946 + 800b918: 4b0d ldr r3, [pc, #52] ; (800b950 ) + 800b91a: f240 1255 movw r2, #341 ; 0x155 + 800b91e: 490f ldr r1, [pc, #60] ; (800b95c ) + 800b920: 480d ldr r0, [pc, #52] ; (800b958 ) + 800b922: f005 f951 bl 8010bc8 + 800b926: e00e b.n 800b946 + pcb->unacked != NULL || pcb->unsent != NULL); + } else { + LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty", + 800b928: 687b ldr r3, [r7, #4] + 800b92a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800b92c: 2b00 cmp r3, #0 + 800b92e: d103 bne.n 800b938 + 800b930: 687b ldr r3, [r7, #4] + 800b932: 6edb ldr r3, [r3, #108] ; 0x6c + 800b934: 2b00 cmp r3, #0 + 800b936: d006 beq.n 800b946 + 800b938: 4b05 ldr r3, [pc, #20] ; (800b950 ) + 800b93a: f44f 72ac mov.w r2, #344 ; 0x158 + 800b93e: 4908 ldr r1, [pc, #32] ; (800b960 ) + 800b940: 4805 ldr r0, [pc, #20] ; (800b958 ) + 800b942: f005 f941 bl 8010bc8 + pcb->unacked == NULL && pcb->unsent == NULL); + } + return ERR_OK; + 800b946: 2300 movs r3, #0 +} + 800b948: 4618 mov r0, r3 + 800b94a: 3708 adds r7, #8 + 800b94c: 46bd mov sp, r7 + 800b94e: bd80 pop {r7, pc} + 800b950: 08013618 .word 0x08013618 + 800b954: 08013728 .word 0x08013728 + 800b958: 0801366c .word 0x0801366c + 800b95c: 08013748 .word 0x08013748 + 800b960: 08013784 .word 0x08013784 + +0800b964 : + * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will not be set on last segment sent, + * @return ERR_OK if enqueued, another err_t on error + */ +err_t +tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags) +{ + 800b964: b590 push {r4, r7, lr} + 800b966: b09d sub sp, #116 ; 0x74 + 800b968: af04 add r7, sp, #16 + 800b96a: 60f8 str r0, [r7, #12] + 800b96c: 60b9 str r1, [r7, #8] + 800b96e: 4611 mov r1, r2 + 800b970: 461a mov r2, r3 + 800b972: 460b mov r3, r1 + 800b974: 80fb strh r3, [r7, #6] + 800b976: 4613 mov r3, r2 + 800b978: 717b strb r3, [r7, #5] + struct pbuf *concat_p = NULL; + 800b97a: 2300 movs r3, #0 + 800b97c: 63fb str r3, [r7, #60] ; 0x3c + struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL; + 800b97e: 2300 movs r3, #0 + 800b980: 643b str r3, [r7, #64] ; 0x40 + 800b982: 2300 movs r3, #0 + 800b984: 657b str r3, [r7, #84] ; 0x54 + 800b986: 2300 movs r3, #0 + 800b988: 653b str r3, [r7, #80] ; 0x50 + 800b98a: 2300 movs r3, #0 + 800b98c: 64fb str r3, [r7, #76] ; 0x4c + u16_t pos = 0; /* position in 'arg' data */ + 800b98e: 2300 movs r3, #0 + 800b990: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + u16_t queuelen; + u8_t optlen; + u8_t optflags = 0; + 800b994: 2300 movs r3, #0 + 800b996: f887 302b strb.w r3, [r7, #43] ; 0x2b +#if TCP_OVERSIZE + u16_t oversize = 0; + 800b99a: 2300 movs r3, #0 + 800b99c: 82fb strh r3, [r7, #22] + u16_t oversize_used = 0; + 800b99e: 2300 movs r3, #0 + 800b9a0: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 +#if TCP_OVERSIZE_DBGCHECK + u16_t oversize_add = 0; + 800b9a4: 2300 movs r3, #0 + 800b9a6: f8a7 305a strh.w r3, [r7, #90] ; 0x5a +#endif /* TCP_OVERSIZE_DBGCHECK*/ +#endif /* TCP_OVERSIZE */ + u16_t extendlen = 0; + 800b9aa: 2300 movs r3, #0 + 800b9ac: f8a7 305e strh.w r3, [r7, #94] ; 0x5e + u16_t concat_chksummed = 0; +#endif /* TCP_CHECKSUM_ON_COPY */ + err_t err; + u16_t mss_local; + + LWIP_ERROR("tcp_write: invalid pcb", pcb != NULL, return ERR_ARG); + 800b9b0: 68fb ldr r3, [r7, #12] + 800b9b2: 2b00 cmp r3, #0 + 800b9b4: d109 bne.n 800b9ca + 800b9b6: 4b9c ldr r3, [pc, #624] ; (800bc28 ) + 800b9b8: f44f 72cf mov.w r2, #414 ; 0x19e + 800b9bc: 499b ldr r1, [pc, #620] ; (800bc2c ) + 800b9be: 489c ldr r0, [pc, #624] ; (800bc30 ) + 800b9c0: f005 f902 bl 8010bc8 + 800b9c4: f06f 030f mvn.w r3, #15 + 800b9c8: e379 b.n 800c0be + + /* don't allocate segments bigger than half the maximum window we ever received */ + mss_local = LWIP_MIN(pcb->mss, TCPWND_MIN16(pcb->snd_wnd_max / 2)); + 800b9ca: 68fb ldr r3, [r7, #12] + 800b9cc: f8b3 3062 ldrh.w r3, [r3, #98] ; 0x62 + 800b9d0: 085b lsrs r3, r3, #1 + 800b9d2: b29a uxth r2, r3 + 800b9d4: 68fb ldr r3, [r7, #12] + 800b9d6: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800b9d8: 4293 cmp r3, r2 + 800b9da: bf28 it cs + 800b9dc: 4613 movcs r3, r2 + 800b9de: 853b strh r3, [r7, #40] ; 0x28 + mss_local = mss_local ? mss_local : pcb->mss; + 800b9e0: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800b9e2: 2b00 cmp r3, #0 + 800b9e4: d102 bne.n 800b9ec + 800b9e6: 68fb ldr r3, [r7, #12] + 800b9e8: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800b9ea: e000 b.n 800b9ee + 800b9ec: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800b9ee: 853b strh r3, [r7, #40] ; 0x28 + apiflags |= TCP_WRITE_FLAG_COPY; +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", + (void *)pcb, arg, len, (u16_t)apiflags)); + LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)", + 800b9f0: 68bb ldr r3, [r7, #8] + 800b9f2: 2b00 cmp r3, #0 + 800b9f4: d109 bne.n 800ba0a + 800b9f6: 4b8c ldr r3, [pc, #560] ; (800bc28 ) + 800b9f8: f240 12ad movw r2, #429 ; 0x1ad + 800b9fc: 498d ldr r1, [pc, #564] ; (800bc34 ) + 800b9fe: 488c ldr r0, [pc, #560] ; (800bc30 ) + 800ba00: f005 f8e2 bl 8010bc8 + 800ba04: f06f 030f mvn.w r3, #15 + 800ba08: e359 b.n 800c0be + arg != NULL, return ERR_ARG;); + + err = tcp_write_checks(pcb, len); + 800ba0a: 88fb ldrh r3, [r7, #6] + 800ba0c: 4619 mov r1, r3 + 800ba0e: 68f8 ldr r0, [r7, #12] + 800ba10: f7ff ff2e bl 800b870 + 800ba14: 4603 mov r3, r0 + 800ba16: f887 3027 strb.w r3, [r7, #39] ; 0x27 + if (err != ERR_OK) { + 800ba1a: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 + 800ba1e: 2b00 cmp r3, #0 + 800ba20: d002 beq.n 800ba28 + return err; + 800ba22: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 + 800ba26: e34a b.n 800c0be + } + queuelen = pcb->snd_queuelen; + 800ba28: 68fb ldr r3, [r7, #12] + 800ba2a: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800ba2e: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 + /* ensure that segments can hold at least one data byte... */ + mss_local = LWIP_MAX(mss_local, LWIP_TCP_OPT_LEN_TS + 1); + } else +#endif /* LWIP_TCP_TIMESTAMPS */ + { + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + 800ba32: 2300 movs r3, #0 + 800ba34: f887 3026 strb.w r3, [r7, #38] ; 0x26 + * + * pos records progress as data is segmented. + */ + + /* Find the tail of the unsent queue. */ + if (pcb->unsent != NULL) { + 800ba38: 68fb ldr r3, [r7, #12] + 800ba3a: 6edb ldr r3, [r3, #108] ; 0x6c + 800ba3c: 2b00 cmp r3, #0 + 800ba3e: f000 8127 beq.w 800bc90 + u16_t space; + u16_t unsent_optlen; + + /* @todo: this could be sped up by keeping last_unsent in the pcb */ + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + 800ba42: 68fb ldr r3, [r7, #12] + 800ba44: 6edb ldr r3, [r3, #108] ; 0x6c + 800ba46: 643b str r3, [r7, #64] ; 0x40 + 800ba48: e002 b.n 800ba50 + last_unsent = last_unsent->next); + 800ba4a: 6c3b ldr r3, [r7, #64] ; 0x40 + 800ba4c: 681b ldr r3, [r3, #0] + 800ba4e: 643b str r3, [r7, #64] ; 0x40 + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + 800ba50: 6c3b ldr r3, [r7, #64] ; 0x40 + 800ba52: 681b ldr r3, [r3, #0] + 800ba54: 2b00 cmp r3, #0 + 800ba56: d1f8 bne.n 800ba4a + + /* Usable space at the end of the last unsent segment */ + unsent_optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(last_unsent->flags, pcb); + 800ba58: 6c3b ldr r3, [r7, #64] ; 0x40 + 800ba5a: 7b1b ldrb r3, [r3, #12] + 800ba5c: 009b lsls r3, r3, #2 + 800ba5e: b29b uxth r3, r3 + 800ba60: f003 0304 and.w r3, r3, #4 + 800ba64: 84bb strh r3, [r7, #36] ; 0x24 + LWIP_ASSERT("mss_local is too small", mss_local >= last_unsent->len + unsent_optlen); + 800ba66: 8d3a ldrh r2, [r7, #40] ; 0x28 + 800ba68: 6c3b ldr r3, [r7, #64] ; 0x40 + 800ba6a: 891b ldrh r3, [r3, #8] + 800ba6c: 4619 mov r1, r3 + 800ba6e: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800ba70: 440b add r3, r1 + 800ba72: 429a cmp r2, r3 + 800ba74: da06 bge.n 800ba84 + 800ba76: 4b6c ldr r3, [pc, #432] ; (800bc28 ) + 800ba78: f44f 72f3 mov.w r2, #486 ; 0x1e6 + 800ba7c: 496e ldr r1, [pc, #440] ; (800bc38 ) + 800ba7e: 486c ldr r0, [pc, #432] ; (800bc30 ) + 800ba80: f005 f8a2 bl 8010bc8 + space = mss_local - (last_unsent->len + unsent_optlen); + 800ba84: 6c3b ldr r3, [r7, #64] ; 0x40 + 800ba86: 891a ldrh r2, [r3, #8] + 800ba88: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800ba8a: 4413 add r3, r2 + 800ba8c: b29b uxth r3, r3 + 800ba8e: 8d3a ldrh r2, [r7, #40] ; 0x28 + 800ba90: 1ad3 subs r3, r2, r3 + 800ba92: f8a7 305c strh.w r3, [r7, #92] ; 0x5c + * function. + */ +#if TCP_OVERSIZE +#if TCP_OVERSIZE_DBGCHECK + /* check that pcb->unsent_oversize matches last_unsent->oversize_left */ + LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)", + 800ba96: 68fb ldr r3, [r7, #12] + 800ba98: f8b3 2068 ldrh.w r2, [r3, #104] ; 0x68 + 800ba9c: 6c3b ldr r3, [r7, #64] ; 0x40 + 800ba9e: 895b ldrh r3, [r3, #10] + 800baa0: 429a cmp r2, r3 + 800baa2: d006 beq.n 800bab2 + 800baa4: 4b60 ldr r3, [pc, #384] ; (800bc28 ) + 800baa6: f240 12f3 movw r2, #499 ; 0x1f3 + 800baaa: 4964 ldr r1, [pc, #400] ; (800bc3c ) + 800baac: 4860 ldr r0, [pc, #384] ; (800bc30 ) + 800baae: f005 f88b bl 8010bc8 + pcb->unsent_oversize == last_unsent->oversize_left); +#endif /* TCP_OVERSIZE_DBGCHECK */ + oversize = pcb->unsent_oversize; + 800bab2: 68fb ldr r3, [r7, #12] + 800bab4: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 + 800bab8: 82fb strh r3, [r7, #22] + if (oversize > 0) { + 800baba: 8afb ldrh r3, [r7, #22] + 800babc: 2b00 cmp r3, #0 + 800babe: d02e beq.n 800bb1e + LWIP_ASSERT("inconsistent oversize vs. space", oversize <= space); + 800bac0: 8afb ldrh r3, [r7, #22] + 800bac2: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c + 800bac6: 429a cmp r2, r3 + 800bac8: d206 bcs.n 800bad8 + 800baca: 4b57 ldr r3, [pc, #348] ; (800bc28 ) + 800bacc: f44f 72fc mov.w r2, #504 ; 0x1f8 + 800bad0: 495b ldr r1, [pc, #364] ; (800bc40 ) + 800bad2: 4857 ldr r0, [pc, #348] ; (800bc30 ) + 800bad4: f005 f878 bl 8010bc8 + seg = last_unsent; + 800bad8: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bada: 657b str r3, [r7, #84] ; 0x54 + oversize_used = LWIP_MIN(space, LWIP_MIN(oversize, len)); + 800badc: 8afb ldrh r3, [r7, #22] + 800bade: 88fa ldrh r2, [r7, #6] + 800bae0: 4293 cmp r3, r2 + 800bae2: bf28 it cs + 800bae4: 4613 movcs r3, r2 + 800bae6: b29b uxth r3, r3 + 800bae8: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c + 800baec: 4293 cmp r3, r2 + 800baee: bf28 it cs + 800baf0: 4613 movcs r3, r2 + 800baf2: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 + pos += oversize_used; + 800baf6: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a + 800bafa: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800bafe: 4413 add r3, r2 + 800bb00: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + oversize -= oversize_used; + 800bb04: 8afa ldrh r2, [r7, #22] + 800bb06: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800bb0a: 1ad3 subs r3, r2, r3 + 800bb0c: b29b uxth r3, r3 + 800bb0e: 82fb strh r3, [r7, #22] + space -= oversize_used; + 800bb10: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c + 800bb14: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800bb18: 1ad3 subs r3, r2, r3 + 800bb1a: f8a7 305c strh.w r3, [r7, #92] ; 0x5c + } + /* now we are either finished or oversize is zero */ + LWIP_ASSERT("inconsistent oversize vs. len", (oversize == 0) || (pos == len)); + 800bb1e: 8afb ldrh r3, [r7, #22] + 800bb20: 2b00 cmp r3, #0 + 800bb22: d00b beq.n 800bb3c + 800bb24: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a + 800bb28: 88fb ldrh r3, [r7, #6] + 800bb2a: 429a cmp r2, r3 + 800bb2c: d006 beq.n 800bb3c + 800bb2e: 4b3e ldr r3, [pc, #248] ; (800bc28 ) + 800bb30: f44f 7200 mov.w r2, #512 ; 0x200 + 800bb34: 4943 ldr r1, [pc, #268] ; (800bc44 ) + 800bb36: 483e ldr r0, [pc, #248] ; (800bc30 ) + 800bb38: f005 f846 bl 8010bc8 + * + * This phase is skipped for LWIP_NETIF_TX_SINGLE_PBUF as we could only execute + * it after rexmit puts a segment from unacked to unsent and at this point, + * oversize info is lost. + */ + if ((pos < len) && (space > 0) && (last_unsent->len > 0)) { + 800bb3c: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a + 800bb40: 88fb ldrh r3, [r7, #6] + 800bb42: 429a cmp r2, r3 + 800bb44: f080 8172 bcs.w 800be2c + 800bb48: f8b7 305c ldrh.w r3, [r7, #92] ; 0x5c + 800bb4c: 2b00 cmp r3, #0 + 800bb4e: f000 816d beq.w 800be2c + 800bb52: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bb54: 891b ldrh r3, [r3, #8] + 800bb56: 2b00 cmp r3, #0 + 800bb58: f000 8168 beq.w 800be2c + u16_t seglen = LWIP_MIN(space, len - pos); + 800bb5c: 88fa ldrh r2, [r7, #6] + 800bb5e: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bb62: 1ad2 subs r2, r2, r3 + 800bb64: f8b7 305c ldrh.w r3, [r7, #92] ; 0x5c + 800bb68: 4293 cmp r3, r2 + 800bb6a: bfa8 it ge + 800bb6c: 4613 movge r3, r2 + 800bb6e: 847b strh r3, [r7, #34] ; 0x22 + seg = last_unsent; + 800bb70: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bb72: 657b str r3, [r7, #84] ; 0x54 + + /* Create a pbuf with a copy or reference to seglen bytes. We + * can use PBUF_RAW here since the data appears in the middle of + * a segment. A header will never be prepended. */ + if (apiflags & TCP_WRITE_FLAG_COPY) { + 800bb74: 797b ldrb r3, [r7, #5] + 800bb76: f003 0301 and.w r3, r3, #1 + 800bb7a: 2b00 cmp r3, #0 + 800bb7c: d02b beq.n 800bbd6 + /* Data is copied */ + if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) { + 800bb7e: f107 0016 add.w r0, r7, #22 + 800bb82: f8b7 205c ldrh.w r2, [r7, #92] ; 0x5c + 800bb86: 8c79 ldrh r1, [r7, #34] ; 0x22 + 800bb88: 2301 movs r3, #1 + 800bb8a: 9302 str r3, [sp, #8] + 800bb8c: 797b ldrb r3, [r7, #5] + 800bb8e: 9301 str r3, [sp, #4] + 800bb90: 68fb ldr r3, [r7, #12] + 800bb92: 9300 str r3, [sp, #0] + 800bb94: 4603 mov r3, r0 + 800bb96: 2000 movs r0, #0 + 800bb98: f7ff fdf0 bl 800b77c + 800bb9c: 63f8 str r0, [r7, #60] ; 0x3c + 800bb9e: 6bfb ldr r3, [r7, #60] ; 0x3c + 800bba0: 2b00 cmp r3, #0 + 800bba2: f000 825a beq.w 800c05a + ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", + seglen)); + goto memerr; + } +#if TCP_OVERSIZE_DBGCHECK + oversize_add = oversize; + 800bba6: 8afb ldrh r3, [r7, #22] + 800bba8: f8a7 305a strh.w r3, [r7, #90] ; 0x5a +#endif /* TCP_OVERSIZE_DBGCHECK */ + TCP_DATA_COPY2(concat_p->payload, (const u8_t *)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped); + 800bbac: 6bfb ldr r3, [r7, #60] ; 0x3c + 800bbae: 6858 ldr r0, [r3, #4] + 800bbb0: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bbb4: 68ba ldr r2, [r7, #8] + 800bbb6: 4413 add r3, r2 + 800bbb8: 8c7a ldrh r2, [r7, #34] ; 0x22 + 800bbba: 4619 mov r1, r3 + 800bbbc: f005 f9e5 bl 8010f8a +#if TCP_CHECKSUM_ON_COPY + concat_chksummed += seglen; +#endif /* TCP_CHECKSUM_ON_COPY */ + queuelen += pbuf_clen(concat_p); + 800bbc0: 6bf8 ldr r0, [r7, #60] ; 0x3c + 800bbc2: f7fb fa8f bl 80070e4 + 800bbc6: 4603 mov r3, r0 + 800bbc8: 461a mov r2, r3 + 800bbca: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 + 800bbce: 4413 add r3, r2 + 800bbd0: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 + 800bbd4: e055 b.n 800bc82 + } else { + /* Data is not copied */ + /* If the last unsent pbuf is of type PBUF_ROM, try to extend it. */ + struct pbuf *p; + for (p = last_unsent->p; p->next != NULL; p = p->next); + 800bbd6: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bbd8: 685b ldr r3, [r3, #4] + 800bbda: 63bb str r3, [r7, #56] ; 0x38 + 800bbdc: e002 b.n 800bbe4 + 800bbde: 6bbb ldr r3, [r7, #56] ; 0x38 + 800bbe0: 681b ldr r3, [r3, #0] + 800bbe2: 63bb str r3, [r7, #56] ; 0x38 + 800bbe4: 6bbb ldr r3, [r7, #56] ; 0x38 + 800bbe6: 681b ldr r3, [r3, #0] + 800bbe8: 2b00 cmp r3, #0 + 800bbea: d1f8 bne.n 800bbde + if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) && + 800bbec: 6bbb ldr r3, [r7, #56] ; 0x38 + 800bbee: 7b1b ldrb r3, [r3, #12] + 800bbf0: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 800bbf4: 2b00 cmp r3, #0 + 800bbf6: d129 bne.n 800bc4c + (const u8_t *)p->payload + p->len == (const u8_t *)arg) { + 800bbf8: 6bbb ldr r3, [r7, #56] ; 0x38 + 800bbfa: 685b ldr r3, [r3, #4] + 800bbfc: 6bba ldr r2, [r7, #56] ; 0x38 + 800bbfe: 8952 ldrh r2, [r2, #10] + 800bc00: 4413 add r3, r2 + if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) && + 800bc02: 68ba ldr r2, [r7, #8] + 800bc04: 429a cmp r2, r3 + 800bc06: d121 bne.n 800bc4c + LWIP_ASSERT("tcp_write: ROM pbufs cannot be oversized", pos == 0); + 800bc08: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bc0c: 2b00 cmp r3, #0 + 800bc0e: d006 beq.n 800bc1e + 800bc10: 4b05 ldr r3, [pc, #20] ; (800bc28 ) + 800bc12: f240 2231 movw r2, #561 ; 0x231 + 800bc16: 490c ldr r1, [pc, #48] ; (800bc48 ) + 800bc18: 4805 ldr r0, [pc, #20] ; (800bc30 ) + 800bc1a: f004 ffd5 bl 8010bc8 + extendlen = seglen; + 800bc1e: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800bc20: f8a7 305e strh.w r3, [r7, #94] ; 0x5e + 800bc24: e02d b.n 800bc82 + 800bc26: bf00 nop + 800bc28: 08013618 .word 0x08013618 + 800bc2c: 080137b8 .word 0x080137b8 + 800bc30: 0801366c .word 0x0801366c + 800bc34: 080137d0 .word 0x080137d0 + 800bc38: 08013804 .word 0x08013804 + 800bc3c: 0801381c .word 0x0801381c + 800bc40: 0801384c .word 0x0801384c + 800bc44: 0801386c .word 0x0801386c + 800bc48: 0801388c .word 0x0801388c + } else { + if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) { + 800bc4c: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800bc4e: 2201 movs r2, #1 + 800bc50: 4619 mov r1, r3 + 800bc52: 2000 movs r0, #0 + 800bc54: f7fa feda bl 8006a0c + 800bc58: 63f8 str r0, [r7, #60] ; 0x3c + 800bc5a: 6bfb ldr r3, [r7, #60] ; 0x3c + 800bc5c: 2b00 cmp r3, #0 + 800bc5e: f000 81fe beq.w 800c05e + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_write: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } + /* reference the non-volatile payload data */ + ((struct pbuf_rom *)concat_p)->payload = (const u8_t *)arg + pos; + 800bc62: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bc66: 68ba ldr r2, [r7, #8] + 800bc68: 441a add r2, r3 + 800bc6a: 6bfb ldr r3, [r7, #60] ; 0x3c + 800bc6c: 605a str r2, [r3, #4] + queuelen += pbuf_clen(concat_p); + 800bc6e: 6bf8 ldr r0, [r7, #60] ; 0x3c + 800bc70: f7fb fa38 bl 80070e4 + 800bc74: 4603 mov r3, r0 + 800bc76: 461a mov r2, r3 + 800bc78: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 + 800bc7c: 4413 add r3, r2 + 800bc7e: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 + &concat_chksum, &concat_chksum_swapped); + concat_chksummed += seglen; +#endif /* TCP_CHECKSUM_ON_COPY */ + } + + pos += seglen; + 800bc82: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a + 800bc86: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800bc88: 4413 add r3, r2 + 800bc8a: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + 800bc8e: e0cd b.n 800be2c + } +#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ + } else { +#if TCP_OVERSIZE + LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)", + 800bc90: 68fb ldr r3, [r7, #12] + 800bc92: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 + 800bc96: 2b00 cmp r3, #0 + 800bc98: f000 80c8 beq.w 800be2c + 800bc9c: 4b72 ldr r3, [pc, #456] ; (800be68 ) + 800bc9e: f240 224a movw r2, #586 ; 0x24a + 800bca2: 4972 ldr r1, [pc, #456] ; (800be6c ) + 800bca4: 4872 ldr r0, [pc, #456] ; (800be70 ) + 800bca6: f004 ff8f bl 8010bc8 + * Phase 3: Create new segments. + * + * The new segments are chained together in the local 'queue' + * variable, ready to be appended to pcb->unsent. + */ + while (pos < len) { + 800bcaa: e0bf b.n 800be2c + struct pbuf *p; + u16_t left = len - pos; + 800bcac: 88fa ldrh r2, [r7, #6] + 800bcae: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bcb2: 1ad3 subs r3, r2, r3 + 800bcb4: 843b strh r3, [r7, #32] + u16_t max_len = mss_local - optlen; + 800bcb6: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800bcba: b29b uxth r3, r3 + 800bcbc: 8d3a ldrh r2, [r7, #40] ; 0x28 + 800bcbe: 1ad3 subs r3, r2, r3 + 800bcc0: 83fb strh r3, [r7, #30] + u16_t seglen = LWIP_MIN(left, max_len); + 800bcc2: 8bfa ldrh r2, [r7, #30] + 800bcc4: 8c3b ldrh r3, [r7, #32] + 800bcc6: 4293 cmp r3, r2 + 800bcc8: bf28 it cs + 800bcca: 4613 movcs r3, r2 + 800bccc: 83bb strh r3, [r7, #28] +#if TCP_CHECKSUM_ON_COPY + u16_t chksum = 0; + u8_t chksum_swapped = 0; +#endif /* TCP_CHECKSUM_ON_COPY */ + + if (apiflags & TCP_WRITE_FLAG_COPY) { + 800bcce: 797b ldrb r3, [r7, #5] + 800bcd0: f003 0301 and.w r3, r3, #1 + 800bcd4: 2b00 cmp r3, #0 + 800bcd6: d036 beq.n 800bd46 + /* If copy is set, memory should be allocated and data copied + * into pbuf */ + if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, mss_local, &oversize, pcb, apiflags, queue == NULL)) == NULL) { + 800bcd8: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800bcdc: b29a uxth r2, r3 + 800bcde: 8bbb ldrh r3, [r7, #28] + 800bce0: 4413 add r3, r2 + 800bce2: b299 uxth r1, r3 + 800bce4: 6cfb ldr r3, [r7, #76] ; 0x4c + 800bce6: 2b00 cmp r3, #0 + 800bce8: bf0c ite eq + 800bcea: 2301 moveq r3, #1 + 800bcec: 2300 movne r3, #0 + 800bcee: b2db uxtb r3, r3 + 800bcf0: f107 0016 add.w r0, r7, #22 + 800bcf4: 8d3a ldrh r2, [r7, #40] ; 0x28 + 800bcf6: 9302 str r3, [sp, #8] + 800bcf8: 797b ldrb r3, [r7, #5] + 800bcfa: 9301 str r3, [sp, #4] + 800bcfc: 68fb ldr r3, [r7, #12] + 800bcfe: 9300 str r3, [sp, #0] + 800bd00: 4603 mov r3, r0 + 800bd02: 2036 movs r0, #54 ; 0x36 + 800bd04: f7ff fd3a bl 800b77c + 800bd08: 6378 str r0, [r7, #52] ; 0x34 + 800bd0a: 6b7b ldr r3, [r7, #52] ; 0x34 + 800bd0c: 2b00 cmp r3, #0 + 800bd0e: f000 81a8 beq.w 800c062 + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); + goto memerr; + } + LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen", + 800bd12: 6b7b ldr r3, [r7, #52] ; 0x34 + 800bd14: 895b ldrh r3, [r3, #10] + 800bd16: 8bba ldrh r2, [r7, #28] + 800bd18: 429a cmp r2, r3 + 800bd1a: d906 bls.n 800bd2a + 800bd1c: 4b52 ldr r3, [pc, #328] ; (800be68 ) + 800bd1e: f240 2266 movw r2, #614 ; 0x266 + 800bd22: 4954 ldr r1, [pc, #336] ; (800be74 ) + 800bd24: 4852 ldr r0, [pc, #328] ; (800be70 ) + 800bd26: f004 ff4f bl 8010bc8 + (p->len >= seglen)); + TCP_DATA_COPY2((char *)p->payload + optlen, (const u8_t *)arg + pos, seglen, &chksum, &chksum_swapped); + 800bd2a: 6b7b ldr r3, [r7, #52] ; 0x34 + 800bd2c: 685a ldr r2, [r3, #4] + 800bd2e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800bd32: 18d0 adds r0, r2, r3 + 800bd34: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bd38: 68ba ldr r2, [r7, #8] + 800bd3a: 4413 add r3, r2 + 800bd3c: 8bba ldrh r2, [r7, #28] + 800bd3e: 4619 mov r1, r3 + 800bd40: f005 f923 bl 8010f8a + 800bd44: e02f b.n 800bda6 + * sent out on the link (as it has to be ACKed by the remote + * party) we can safely use PBUF_ROM instead of PBUF_REF here. + */ + struct pbuf *p2; +#if TCP_OVERSIZE + LWIP_ASSERT("oversize == 0", oversize == 0); + 800bd46: 8afb ldrh r3, [r7, #22] + 800bd48: 2b00 cmp r3, #0 + 800bd4a: d006 beq.n 800bd5a + 800bd4c: 4b46 ldr r3, [pc, #280] ; (800be68 ) + 800bd4e: f240 2271 movw r2, #625 ; 0x271 + 800bd52: 4949 ldr r1, [pc, #292] ; (800be78 ) + 800bd54: 4846 ldr r0, [pc, #280] ; (800be70 ) + 800bd56: f004 ff37 bl 8010bc8 +#endif /* TCP_OVERSIZE */ + if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { + 800bd5a: 8bbb ldrh r3, [r7, #28] + 800bd5c: 2201 movs r2, #1 + 800bd5e: 4619 mov r1, r3 + 800bd60: 2036 movs r0, #54 ; 0x36 + 800bd62: f7fa fe53 bl 8006a0c + 800bd66: 61b8 str r0, [r7, #24] + 800bd68: 69bb ldr r3, [r7, #24] + 800bd6a: 2b00 cmp r3, #0 + 800bd6c: f000 817b beq.w 800c066 + chksum_swapped = 1; + chksum = SWAP_BYTES_IN_WORD(chksum); + } +#endif /* TCP_CHECKSUM_ON_COPY */ + /* reference the non-volatile payload data */ + ((struct pbuf_rom *)p2)->payload = (const u8_t *)arg + pos; + 800bd70: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bd74: 68ba ldr r2, [r7, #8] + 800bd76: 441a add r2, r3 + 800bd78: 69bb ldr r3, [r7, #24] + 800bd7a: 605a str r2, [r3, #4] + + /* Second, allocate a pbuf for the headers. */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + 800bd7c: f897 3026 ldrb.w r3, [r7, #38] ; 0x26 + 800bd80: b29b uxth r3, r3 + 800bd82: f44f 7220 mov.w r2, #640 ; 0x280 + 800bd86: 4619 mov r1, r3 + 800bd88: 2036 movs r0, #54 ; 0x36 + 800bd8a: f7fa fe3f bl 8006a0c + 800bd8e: 6378 str r0, [r7, #52] ; 0x34 + 800bd90: 6b7b ldr r3, [r7, #52] ; 0x34 + 800bd92: 2b00 cmp r3, #0 + 800bd94: d103 bne.n 800bd9e + /* If allocation fails, we have to deallocate the data pbuf as + * well. */ + pbuf_free(p2); + 800bd96: 69b8 ldr r0, [r7, #24] + 800bd98: f7fb f91c bl 8006fd4 + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for header pbuf\n")); + goto memerr; + 800bd9c: e166 b.n 800c06c + } + /* Concatenate the headers and data pbufs together. */ + pbuf_cat(p/*header*/, p2/*data*/); + 800bd9e: 69b9 ldr r1, [r7, #24] + 800bda0: 6b78 ldr r0, [r7, #52] ; 0x34 + 800bda2: f7fb f9d9 bl 8007158 + } + + queuelen += pbuf_clen(p); + 800bda6: 6b78 ldr r0, [r7, #52] ; 0x34 + 800bda8: f7fb f99c bl 80070e4 + 800bdac: 4603 mov r3, r0 + 800bdae: 461a mov r2, r3 + 800bdb0: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 + 800bdb4: 4413 add r3, r2 + 800bdb6: f8a7 3048 strh.w r3, [r7, #72] ; 0x48 + + /* Now that there are more segments queued, we check again if the + * length of the queue exceeds the configured maximum or + * overflows. */ + if (queuelen > LWIP_MIN(TCP_SND_QUEUELEN, TCP_SNDQUEUELEN_OVERFLOW)) { + 800bdba: f8b7 3048 ldrh.w r3, [r7, #72] ; 0x48 + 800bdbe: 2b09 cmp r3, #9 + 800bdc0: d903 bls.n 800bdca + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: queue too long %"U16_F" (%d)\n", + queuelen, (int)TCP_SND_QUEUELEN)); + pbuf_free(p); + 800bdc2: 6b78 ldr r0, [r7, #52] ; 0x34 + 800bdc4: f7fb f906 bl 8006fd4 + goto memerr; + 800bdc8: e150 b.n 800c06c + } + + if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) { + 800bdca: 68fb ldr r3, [r7, #12] + 800bdcc: 6dda ldr r2, [r3, #92] ; 0x5c + 800bdce: f8b7 304a ldrh.w r3, [r7, #74] ; 0x4a + 800bdd2: 441a add r2, r3 + 800bdd4: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 800bdd8: 9300 str r3, [sp, #0] + 800bdda: 4613 mov r3, r2 + 800bddc: 2200 movs r2, #0 + 800bdde: 6b79 ldr r1, [r7, #52] ; 0x34 + 800bde0: 68f8 ldr r0, [r7, #12] + 800bde2: f7ff fc2b bl 800b63c + 800bde6: 6578 str r0, [r7, #84] ; 0x54 + 800bde8: 6d7b ldr r3, [r7, #84] ; 0x54 + 800bdea: 2b00 cmp r3, #0 + 800bdec: f000 813d beq.w 800c06a + goto memerr; + } +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = oversize; + 800bdf0: 8afa ldrh r2, [r7, #22] + 800bdf2: 6d7b ldr r3, [r7, #84] ; 0x54 + 800bdf4: 815a strh r2, [r3, #10] + seg->chksum_swapped = chksum_swapped; + seg->flags |= TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* first segment of to-be-queued data? */ + if (queue == NULL) { + 800bdf6: 6cfb ldr r3, [r7, #76] ; 0x4c + 800bdf8: 2b00 cmp r3, #0 + 800bdfa: d102 bne.n 800be02 + queue = seg; + 800bdfc: 6d7b ldr r3, [r7, #84] ; 0x54 + 800bdfe: 64fb str r3, [r7, #76] ; 0x4c + 800be00: e00c b.n 800be1c + } else { + /* Attach the segment to the end of the queued segments */ + LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL); + 800be02: 6d3b ldr r3, [r7, #80] ; 0x50 + 800be04: 2b00 cmp r3, #0 + 800be06: d106 bne.n 800be16 + 800be08: 4b17 ldr r3, [pc, #92] ; (800be68 ) + 800be0a: f240 22ab movw r2, #683 ; 0x2ab + 800be0e: 491b ldr r1, [pc, #108] ; (800be7c ) + 800be10: 4817 ldr r0, [pc, #92] ; (800be70 ) + 800be12: f004 fed9 bl 8010bc8 + prev_seg->next = seg; + 800be16: 6d3b ldr r3, [r7, #80] ; 0x50 + 800be18: 6d7a ldr r2, [r7, #84] ; 0x54 + 800be1a: 601a str r2, [r3, #0] + } + /* remember last segment of to-be-queued data for next iteration */ + prev_seg = seg; + 800be1c: 6d7b ldr r3, [r7, #84] ; 0x54 + 800be1e: 653b str r3, [r7, #80] ; 0x50 + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n", + lwip_ntohl(seg->tcphdr->seqno), + lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg))); + + pos += seglen; + 800be20: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a + 800be24: 8bbb ldrh r3, [r7, #28] + 800be26: 4413 add r3, r2 + 800be28: f8a7 304a strh.w r3, [r7, #74] ; 0x4a + while (pos < len) { + 800be2c: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a + 800be30: 88fb ldrh r3, [r7, #6] + 800be32: 429a cmp r2, r3 + 800be34: f4ff af3a bcc.w 800bcac + /* + * All three segmentation phases were successful. We can commit the + * transaction. + */ +#if TCP_OVERSIZE_DBGCHECK + if ((last_unsent != NULL) && (oversize_add != 0)) { + 800be38: 6c3b ldr r3, [r7, #64] ; 0x40 + 800be3a: 2b00 cmp r3, #0 + 800be3c: d00b beq.n 800be56 + 800be3e: f8b7 305a ldrh.w r3, [r7, #90] ; 0x5a + 800be42: 2b00 cmp r3, #0 + 800be44: d007 beq.n 800be56 + last_unsent->oversize_left += oversize_add; + 800be46: 6c3b ldr r3, [r7, #64] ; 0x40 + 800be48: 895a ldrh r2, [r3, #10] + 800be4a: f8b7 305a ldrh.w r3, [r7, #90] ; 0x5a + 800be4e: 4413 add r3, r2 + 800be50: b29a uxth r2, r3 + 800be52: 6c3b ldr r3, [r7, #64] ; 0x40 + 800be54: 815a strh r2, [r3, #10] + /* + * Phase 1: If data has been added to the preallocated tail of + * last_unsent, we update the length fields of the pbuf chain. + */ +#if TCP_OVERSIZE + if (oversize_used > 0) { + 800be56: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800be5a: 2b00 cmp r3, #0 + 800be5c: d052 beq.n 800bf04 + struct pbuf *p; + /* Bump tot_len of whole chain, len of tail */ + for (p = last_unsent->p; p; p = p->next) { + 800be5e: 6c3b ldr r3, [r7, #64] ; 0x40 + 800be60: 685b ldr r3, [r3, #4] + 800be62: 633b str r3, [r7, #48] ; 0x30 + 800be64: e02e b.n 800bec4 + 800be66: bf00 nop + 800be68: 08013618 .word 0x08013618 + 800be6c: 080138b8 .word 0x080138b8 + 800be70: 0801366c .word 0x0801366c + 800be74: 080138e8 .word 0x080138e8 + 800be78: 08013928 .word 0x08013928 + 800be7c: 08013938 .word 0x08013938 + p->tot_len += oversize_used; + 800be80: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be82: 891a ldrh r2, [r3, #8] + 800be84: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800be88: 4413 add r3, r2 + 800be8a: b29a uxth r2, r3 + 800be8c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be8e: 811a strh r2, [r3, #8] + if (p->next == NULL) { + 800be90: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be92: 681b ldr r3, [r3, #0] + 800be94: 2b00 cmp r3, #0 + 800be96: d112 bne.n 800bebe + TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent); + 800be98: 6b3b ldr r3, [r7, #48] ; 0x30 + 800be9a: 685b ldr r3, [r3, #4] + 800be9c: 6b3a ldr r2, [r7, #48] ; 0x30 + 800be9e: 8952 ldrh r2, [r2, #10] + 800bea0: 4413 add r3, r2 + 800bea2: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 + 800bea6: 68b9 ldr r1, [r7, #8] + 800bea8: 4618 mov r0, r3 + 800beaa: f005 f86e bl 8010f8a + p->len += oversize_used; + 800beae: 6b3b ldr r3, [r7, #48] ; 0x30 + 800beb0: 895a ldrh r2, [r3, #10] + 800beb2: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800beb6: 4413 add r3, r2 + 800beb8: b29a uxth r2, r3 + 800beba: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bebc: 815a strh r2, [r3, #10] + for (p = last_unsent->p; p; p = p->next) { + 800bebe: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bec0: 681b ldr r3, [r3, #0] + 800bec2: 633b str r3, [r7, #48] ; 0x30 + 800bec4: 6b3b ldr r3, [r7, #48] ; 0x30 + 800bec6: 2b00 cmp r3, #0 + 800bec8: d1da bne.n 800be80 + } + } + last_unsent->len += oversize_used; + 800beca: 6c3b ldr r3, [r7, #64] ; 0x40 + 800becc: 891a ldrh r2, [r3, #8] + 800bece: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800bed2: 4413 add r3, r2 + 800bed4: b29a uxth r2, r3 + 800bed6: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bed8: 811a strh r2, [r3, #8] +#if TCP_OVERSIZE_DBGCHECK + LWIP_ASSERT("last_unsent->oversize_left >= oversize_used", + 800beda: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bedc: 895b ldrh r3, [r3, #10] + 800bede: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 + 800bee2: 429a cmp r2, r3 + 800bee4: d906 bls.n 800bef4 + 800bee6: 4b78 ldr r3, [pc, #480] ; (800c0c8 ) + 800bee8: f240 22d3 movw r2, #723 ; 0x2d3 + 800beec: 4977 ldr r1, [pc, #476] ; (800c0cc ) + 800beee: 4878 ldr r0, [pc, #480] ; (800c0d0 ) + 800bef0: f004 fe6a bl 8010bc8 + last_unsent->oversize_left >= oversize_used); + last_unsent->oversize_left -= oversize_used; + 800bef4: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bef6: 895a ldrh r2, [r3, #10] + 800bef8: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800befc: 1ad3 subs r3, r2, r3 + 800befe: b29a uxth r2, r3 + 800bf00: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf02: 815a strh r2, [r3, #10] +#endif /* TCP_OVERSIZE_DBGCHECK */ + } + pcb->unsent_oversize = oversize; + 800bf04: 8afa ldrh r2, [r7, #22] + 800bf06: 68fb ldr r3, [r7, #12] + 800bf08: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + + /* + * Phase 2: concat_p can be concatenated onto last_unsent->p, unless we + * determined that the last ROM pbuf can be extended to include the new data. + */ + if (concat_p != NULL) { + 800bf0c: 6bfb ldr r3, [r7, #60] ; 0x3c + 800bf0e: 2b00 cmp r3, #0 + 800bf10: d018 beq.n 800bf44 + LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty", + 800bf12: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf14: 2b00 cmp r3, #0 + 800bf16: d106 bne.n 800bf26 + 800bf18: 4b6b ldr r3, [pc, #428] ; (800c0c8 ) + 800bf1a: f44f 7238 mov.w r2, #736 ; 0x2e0 + 800bf1e: 496d ldr r1, [pc, #436] ; (800c0d4 ) + 800bf20: 486b ldr r0, [pc, #428] ; (800c0d0 ) + 800bf22: f004 fe51 bl 8010bc8 + (last_unsent != NULL)); + pbuf_cat(last_unsent->p, concat_p); + 800bf26: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf28: 685b ldr r3, [r3, #4] + 800bf2a: 6bf9 ldr r1, [r7, #60] ; 0x3c + 800bf2c: 4618 mov r0, r3 + 800bf2e: f7fb f913 bl 8007158 + last_unsent->len += concat_p->tot_len; + 800bf32: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf34: 891a ldrh r2, [r3, #8] + 800bf36: 6bfb ldr r3, [r7, #60] ; 0x3c + 800bf38: 891b ldrh r3, [r3, #8] + 800bf3a: 4413 add r3, r2 + 800bf3c: b29a uxth r2, r3 + 800bf3e: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf40: 811a strh r2, [r3, #8] + 800bf42: e03c b.n 800bfbe + } else if (extendlen > 0) { + 800bf44: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 800bf48: 2b00 cmp r3, #0 + 800bf4a: d038 beq.n 800bfbe + struct pbuf *p; + LWIP_ASSERT("tcp_write: extension of reference requires reference", + 800bf4c: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf4e: 2b00 cmp r3, #0 + 800bf50: d003 beq.n 800bf5a + 800bf52: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf54: 685b ldr r3, [r3, #4] + 800bf56: 2b00 cmp r3, #0 + 800bf58: d106 bne.n 800bf68 + 800bf5a: 4b5b ldr r3, [pc, #364] ; (800c0c8 ) + 800bf5c: f240 22e6 movw r2, #742 ; 0x2e6 + 800bf60: 495d ldr r1, [pc, #372] ; (800c0d8 ) + 800bf62: 485b ldr r0, [pc, #364] ; (800c0d0 ) + 800bf64: f004 fe30 bl 8010bc8 + last_unsent != NULL && last_unsent->p != NULL); + for (p = last_unsent->p; p->next != NULL; p = p->next) { + 800bf68: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bf6a: 685b ldr r3, [r3, #4] + 800bf6c: 62fb str r3, [r7, #44] ; 0x2c + 800bf6e: e00a b.n 800bf86 + p->tot_len += extendlen; + 800bf70: 6afb ldr r3, [r7, #44] ; 0x2c + 800bf72: 891a ldrh r2, [r3, #8] + 800bf74: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 800bf78: 4413 add r3, r2 + 800bf7a: b29a uxth r2, r3 + 800bf7c: 6afb ldr r3, [r7, #44] ; 0x2c + 800bf7e: 811a strh r2, [r3, #8] + for (p = last_unsent->p; p->next != NULL; p = p->next) { + 800bf80: 6afb ldr r3, [r7, #44] ; 0x2c + 800bf82: 681b ldr r3, [r3, #0] + 800bf84: 62fb str r3, [r7, #44] ; 0x2c + 800bf86: 6afb ldr r3, [r7, #44] ; 0x2c + 800bf88: 681b ldr r3, [r3, #0] + 800bf8a: 2b00 cmp r3, #0 + 800bf8c: d1f0 bne.n 800bf70 + } + p->tot_len += extendlen; + 800bf8e: 6afb ldr r3, [r7, #44] ; 0x2c + 800bf90: 891a ldrh r2, [r3, #8] + 800bf92: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 800bf96: 4413 add r3, r2 + 800bf98: b29a uxth r2, r3 + 800bf9a: 6afb ldr r3, [r7, #44] ; 0x2c + 800bf9c: 811a strh r2, [r3, #8] + p->len += extendlen; + 800bf9e: 6afb ldr r3, [r7, #44] ; 0x2c + 800bfa0: 895a ldrh r2, [r3, #10] + 800bfa2: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 800bfa6: 4413 add r3, r2 + 800bfa8: b29a uxth r2, r3 + 800bfaa: 6afb ldr r3, [r7, #44] ; 0x2c + 800bfac: 815a strh r2, [r3, #10] + last_unsent->len += extendlen; + 800bfae: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bfb0: 891a ldrh r2, [r3, #8] + 800bfb2: f8b7 305e ldrh.w r3, [r7, #94] ; 0x5e + 800bfb6: 4413 add r3, r2 + 800bfb8: b29a uxth r2, r3 + 800bfba: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bfbc: 811a strh r2, [r3, #8] + + /* + * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that + * is harmless + */ + if (last_unsent == NULL) { + 800bfbe: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bfc0: 2b00 cmp r3, #0 + 800bfc2: d103 bne.n 800bfcc + pcb->unsent = queue; + 800bfc4: 68fb ldr r3, [r7, #12] + 800bfc6: 6cfa ldr r2, [r7, #76] ; 0x4c + 800bfc8: 66da str r2, [r3, #108] ; 0x6c + 800bfca: e002 b.n 800bfd2 + } else { + last_unsent->next = queue; + 800bfcc: 6c3b ldr r3, [r7, #64] ; 0x40 + 800bfce: 6cfa ldr r2, [r7, #76] ; 0x4c + 800bfd0: 601a str r2, [r3, #0] + } + + /* + * Finally update the pcb state. + */ + pcb->snd_lbb += len; + 800bfd2: 68fb ldr r3, [r7, #12] + 800bfd4: 6dda ldr r2, [r3, #92] ; 0x5c + 800bfd6: 88fb ldrh r3, [r7, #6] + 800bfd8: 441a add r2, r3 + 800bfda: 68fb ldr r3, [r7, #12] + 800bfdc: 65da str r2, [r3, #92] ; 0x5c + pcb->snd_buf -= len; + 800bfde: 68fb ldr r3, [r7, #12] + 800bfe0: f8b3 2064 ldrh.w r2, [r3, #100] ; 0x64 + 800bfe4: 88fb ldrh r3, [r7, #6] + 800bfe6: 1ad3 subs r3, r2, r3 + 800bfe8: b29a uxth r2, r3 + 800bfea: 68fb ldr r3, [r7, #12] + 800bfec: f8a3 2064 strh.w r2, [r3, #100] ; 0x64 + pcb->snd_queuelen = queuelen; + 800bff0: 68fb ldr r3, [r7, #12] + 800bff2: f8b7 2048 ldrh.w r2, [r7, #72] ; 0x48 + 800bff6: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n", + pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + 800bffa: 68fb ldr r3, [r7, #12] + 800bffc: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c000: 2b00 cmp r3, #0 + 800c002: d00e beq.n 800c022 + LWIP_ASSERT("tcp_write: valid queue length", + 800c004: 68fb ldr r3, [r7, #12] + 800c006: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c008: 2b00 cmp r3, #0 + 800c00a: d10a bne.n 800c022 + 800c00c: 68fb ldr r3, [r7, #12] + 800c00e: 6edb ldr r3, [r3, #108] ; 0x6c + 800c010: 2b00 cmp r3, #0 + 800c012: d106 bne.n 800c022 + 800c014: 4b2c ldr r3, [pc, #176] ; (800c0c8 ) + 800c016: f240 3212 movw r2, #786 ; 0x312 + 800c01a: 4930 ldr r1, [pc, #192] ; (800c0dc ) + 800c01c: 482c ldr r0, [pc, #176] ; (800c0d0 ) + 800c01e: f004 fdd3 bl 8010bc8 + pcb->unacked != NULL || pcb->unsent != NULL); + } + + /* Set the PSH flag in the last segment that we enqueued. */ + if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE) == 0)) { + 800c022: 6d7b ldr r3, [r7, #84] ; 0x54 + 800c024: 2b00 cmp r3, #0 + 800c026: d016 beq.n 800c056 + 800c028: 6d7b ldr r3, [r7, #84] ; 0x54 + 800c02a: 691b ldr r3, [r3, #16] + 800c02c: 2b00 cmp r3, #0 + 800c02e: d012 beq.n 800c056 + 800c030: 797b ldrb r3, [r7, #5] + 800c032: f003 0302 and.w r3, r3, #2 + 800c036: 2b00 cmp r3, #0 + 800c038: d10d bne.n 800c056 + TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); + 800c03a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800c03c: 691b ldr r3, [r3, #16] + 800c03e: 899b ldrh r3, [r3, #12] + 800c040: b29c uxth r4, r3 + 800c042: 2008 movs r0, #8 + 800c044: f7f9 fa82 bl 800554c + 800c048: 4603 mov r3, r0 + 800c04a: 461a mov r2, r3 + 800c04c: 6d7b ldr r3, [r7, #84] ; 0x54 + 800c04e: 691b ldr r3, [r3, #16] + 800c050: 4322 orrs r2, r4 + 800c052: b292 uxth r2, r2 + 800c054: 819a strh r2, [r3, #12] + } + + return ERR_OK; + 800c056: 2300 movs r3, #0 + 800c058: e031 b.n 800c0be + goto memerr; + 800c05a: bf00 nop + 800c05c: e006 b.n 800c06c + goto memerr; + 800c05e: bf00 nop + 800c060: e004 b.n 800c06c + goto memerr; + 800c062: bf00 nop + 800c064: e002 b.n 800c06c + goto memerr; + 800c066: bf00 nop + 800c068: e000 b.n 800c06c + goto memerr; + 800c06a: bf00 nop +memerr: + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 800c06c: 68fb ldr r3, [r7, #12] + 800c06e: 8b5b ldrh r3, [r3, #26] + 800c070: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800c074: b29a uxth r2, r3 + 800c076: 68fb ldr r3, [r7, #12] + 800c078: 835a strh r2, [r3, #26] + TCP_STATS_INC(tcp.memerr); + + if (concat_p != NULL) { + 800c07a: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c07c: 2b00 cmp r3, #0 + 800c07e: d002 beq.n 800c086 + pbuf_free(concat_p); + 800c080: 6bf8 ldr r0, [r7, #60] ; 0x3c + 800c082: f7fa ffa7 bl 8006fd4 + } + if (queue != NULL) { + 800c086: 6cfb ldr r3, [r7, #76] ; 0x4c + 800c088: 2b00 cmp r3, #0 + 800c08a: d002 beq.n 800c092 + tcp_segs_free(queue); + 800c08c: 6cf8 ldr r0, [r7, #76] ; 0x4c + 800c08e: f7fc fb5d bl 800874c + } + if (pcb->snd_queuelen != 0) { + 800c092: 68fb ldr r3, [r7, #12] + 800c094: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c098: 2b00 cmp r3, #0 + 800c09a: d00e beq.n 800c0ba + LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL || + 800c09c: 68fb ldr r3, [r7, #12] + 800c09e: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c0a0: 2b00 cmp r3, #0 + 800c0a2: d10a bne.n 800c0ba + 800c0a4: 68fb ldr r3, [r7, #12] + 800c0a6: 6edb ldr r3, [r3, #108] ; 0x6c + 800c0a8: 2b00 cmp r3, #0 + 800c0aa: d106 bne.n 800c0ba + 800c0ac: 4b06 ldr r3, [pc, #24] ; (800c0c8 ) + 800c0ae: f240 3227 movw r2, #807 ; 0x327 + 800c0b2: 490a ldr r1, [pc, #40] ; (800c0dc ) + 800c0b4: 4806 ldr r0, [pc, #24] ; (800c0d0 ) + 800c0b6: f004 fd87 bl 8010bc8 + pcb->unsent != NULL); + } + LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); + return ERR_MEM; + 800c0ba: f04f 33ff mov.w r3, #4294967295 +} + 800c0be: 4618 mov r0, r3 + 800c0c0: 3764 adds r7, #100 ; 0x64 + 800c0c2: 46bd mov sp, r7 + 800c0c4: bd90 pop {r4, r7, pc} + 800c0c6: bf00 nop + 800c0c8: 08013618 .word 0x08013618 + 800c0cc: 0801394c .word 0x0801394c + 800c0d0: 0801366c .word 0x0801366c + 800c0d4: 08013978 .word 0x08013978 + 800c0d8: 080139b0 .word 0x080139b0 + 800c0dc: 080139e8 .word 0x080139e8 + +0800c0e0 : + * @param pcb the tcp_pcb for which to split the unsent head + * @param split the amount of payload to remain in the head + */ +err_t +tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split) +{ + 800c0e0: b590 push {r4, r7, lr} + 800c0e2: b08b sub sp, #44 ; 0x2c + 800c0e4: af02 add r7, sp, #8 + 800c0e6: 6078 str r0, [r7, #4] + 800c0e8: 460b mov r3, r1 + 800c0ea: 807b strh r3, [r7, #2] + struct tcp_seg *seg = NULL, *useg = NULL; + 800c0ec: 2300 movs r3, #0 + 800c0ee: 61bb str r3, [r7, #24] + 800c0f0: 2300 movs r3, #0 + 800c0f2: 617b str r3, [r7, #20] + struct pbuf *p = NULL; + 800c0f4: 2300 movs r3, #0 + 800c0f6: 613b str r3, [r7, #16] + u16_t chksum = 0; + u8_t chksum_swapped = 0; + struct pbuf *q; +#endif /* TCP_CHECKSUM_ON_COPY */ + + LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL); + 800c0f8: 687b ldr r3, [r7, #4] + 800c0fa: 2b00 cmp r3, #0 + 800c0fc: d106 bne.n 800c10c + 800c0fe: 4b97 ldr r3, [pc, #604] ; (800c35c ) + 800c100: f240 324b movw r2, #843 ; 0x34b + 800c104: 4996 ldr r1, [pc, #600] ; (800c360 ) + 800c106: 4897 ldr r0, [pc, #604] ; (800c364 ) + 800c108: f004 fd5e bl 8010bc8 + + useg = pcb->unsent; + 800c10c: 687b ldr r3, [r7, #4] + 800c10e: 6edb ldr r3, [r3, #108] ; 0x6c + 800c110: 617b str r3, [r7, #20] + if (useg == NULL) { + 800c112: 697b ldr r3, [r7, #20] + 800c114: 2b00 cmp r3, #0 + 800c116: d102 bne.n 800c11e + return ERR_MEM; + 800c118: f04f 33ff mov.w r3, #4294967295 + 800c11c: e119 b.n 800c352 + } + + if (split == 0) { + 800c11e: 887b ldrh r3, [r7, #2] + 800c120: 2b00 cmp r3, #0 + 800c122: d109 bne.n 800c138 + LWIP_ASSERT("Can't split segment into length 0", 0); + 800c124: 4b8d ldr r3, [pc, #564] ; (800c35c ) + 800c126: f240 3253 movw r2, #851 ; 0x353 + 800c12a: 498f ldr r1, [pc, #572] ; (800c368 ) + 800c12c: 488d ldr r0, [pc, #564] ; (800c364 ) + 800c12e: f004 fd4b bl 8010bc8 + return ERR_VAL; + 800c132: f06f 0305 mvn.w r3, #5 + 800c136: e10c b.n 800c352 + } + + if (useg->len <= split) { + 800c138: 697b ldr r3, [r7, #20] + 800c13a: 891b ldrh r3, [r3, #8] + 800c13c: 887a ldrh r2, [r7, #2] + 800c13e: 429a cmp r2, r3 + 800c140: d301 bcc.n 800c146 + return ERR_OK; + 800c142: 2300 movs r3, #0 + 800c144: e105 b.n 800c352 + } + + LWIP_ASSERT("split <= mss", split <= pcb->mss); + 800c146: 687b ldr r3, [r7, #4] + 800c148: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800c14a: 887a ldrh r2, [r7, #2] + 800c14c: 429a cmp r2, r3 + 800c14e: d906 bls.n 800c15e + 800c150: 4b82 ldr r3, [pc, #520] ; (800c35c ) + 800c152: f240 325b movw r2, #859 ; 0x35b + 800c156: 4985 ldr r1, [pc, #532] ; (800c36c ) + 800c158: 4882 ldr r0, [pc, #520] ; (800c364 ) + 800c15a: f004 fd35 bl 8010bc8 + LWIP_ASSERT("useg->len > 0", useg->len > 0); + 800c15e: 697b ldr r3, [r7, #20] + 800c160: 891b ldrh r3, [r3, #8] + 800c162: 2b00 cmp r3, #0 + 800c164: d106 bne.n 800c174 + 800c166: 4b7d ldr r3, [pc, #500] ; (800c35c ) + 800c168: f44f 7257 mov.w r2, #860 ; 0x35c + 800c16c: 4980 ldr r1, [pc, #512] ; (800c370 ) + 800c16e: 487d ldr r0, [pc, #500] ; (800c364 ) + 800c170: f004 fd2a bl 8010bc8 + * to split this packet so we may actually exceed the max value by + * one! + */ + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen)); + + optflags = useg->flags; + 800c174: 697b ldr r3, [r7, #20] + 800c176: 7b1b ldrb r3, [r3, #12] + 800c178: 73fb strb r3, [r7, #15] +#if TCP_CHECKSUM_ON_COPY + /* Remove since checksum is not stored until after tcp_create_segment() */ + optflags &= ~TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + optlen = LWIP_TCP_OPT_LENGTH(optflags); + 800c17a: 7bfb ldrb r3, [r7, #15] + 800c17c: 009b lsls r3, r3, #2 + 800c17e: b2db uxtb r3, r3 + 800c180: f003 0304 and.w r3, r3, #4 + 800c184: 73bb strb r3, [r7, #14] + remainder = useg->len - split; + 800c186: 697b ldr r3, [r7, #20] + 800c188: 891a ldrh r2, [r3, #8] + 800c18a: 887b ldrh r3, [r7, #2] + 800c18c: 1ad3 subs r3, r2, r3 + 800c18e: 81bb strh r3, [r7, #12] + + /* Create new pbuf for the remainder of the split */ + p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM); + 800c190: 7bbb ldrb r3, [r7, #14] + 800c192: b29a uxth r2, r3 + 800c194: 89bb ldrh r3, [r7, #12] + 800c196: 4413 add r3, r2 + 800c198: b29b uxth r3, r3 + 800c19a: f44f 7220 mov.w r2, #640 ; 0x280 + 800c19e: 4619 mov r1, r3 + 800c1a0: 2036 movs r0, #54 ; 0x36 + 800c1a2: f7fa fc33 bl 8006a0c + 800c1a6: 6138 str r0, [r7, #16] + if (p == NULL) { + 800c1a8: 693b ldr r3, [r7, #16] + 800c1aa: 2b00 cmp r3, #0 + 800c1ac: f000 80ba beq.w 800c324 + ("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder)); + goto memerr; + } + + /* Offset into the original pbuf is past TCP/IP headers, options, and split amount */ + offset = useg->p->tot_len - useg->len + split; + 800c1b0: 697b ldr r3, [r7, #20] + 800c1b2: 685b ldr r3, [r3, #4] + 800c1b4: 891a ldrh r2, [r3, #8] + 800c1b6: 697b ldr r3, [r7, #20] + 800c1b8: 891b ldrh r3, [r3, #8] + 800c1ba: 1ad3 subs r3, r2, r3 + 800c1bc: b29a uxth r2, r3 + 800c1be: 887b ldrh r3, [r7, #2] + 800c1c0: 4413 add r3, r2 + 800c1c2: 817b strh r3, [r7, #10] + /* Copy remainder into new pbuf, headers and options will not be filled out */ + if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) { + 800c1c4: 697b ldr r3, [r7, #20] + 800c1c6: 6858 ldr r0, [r3, #4] + 800c1c8: 693b ldr r3, [r7, #16] + 800c1ca: 685a ldr r2, [r3, #4] + 800c1cc: 7bbb ldrb r3, [r7, #14] + 800c1ce: 18d1 adds r1, r2, r3 + 800c1d0: 897b ldrh r3, [r7, #10] + 800c1d2: 89ba ldrh r2, [r7, #12] + 800c1d4: f7fb f8e8 bl 80073a8 + 800c1d8: 4603 mov r3, r0 + 800c1da: 461a mov r2, r3 + 800c1dc: 89bb ldrh r3, [r7, #12] + 800c1de: 4293 cmp r3, r2 + 800c1e0: f040 80a2 bne.w 800c328 +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Options are created when calling tcp_output() */ + + /* Migrate flags from original segment */ + split_flags = TCPH_FLAGS(useg->tcphdr); + 800c1e4: 697b ldr r3, [r7, #20] + 800c1e6: 691b ldr r3, [r3, #16] + 800c1e8: 899b ldrh r3, [r3, #12] + 800c1ea: b29b uxth r3, r3 + 800c1ec: 4618 mov r0, r3 + 800c1ee: f7f9 f9ad bl 800554c + 800c1f2: 4603 mov r3, r0 + 800c1f4: b2db uxtb r3, r3 + 800c1f6: f003 033f and.w r3, r3, #63 ; 0x3f + 800c1fa: 77fb strb r3, [r7, #31] + remainder_flags = 0; /* ACK added in tcp_output() */ + 800c1fc: 2300 movs r3, #0 + 800c1fe: 77bb strb r3, [r7, #30] + + if (split_flags & TCP_PSH) { + 800c200: 7ffb ldrb r3, [r7, #31] + 800c202: f003 0308 and.w r3, r3, #8 + 800c206: 2b00 cmp r3, #0 + 800c208: d007 beq.n 800c21a + split_flags &= ~TCP_PSH; + 800c20a: 7ffb ldrb r3, [r7, #31] + 800c20c: f023 0308 bic.w r3, r3, #8 + 800c210: 77fb strb r3, [r7, #31] + remainder_flags |= TCP_PSH; + 800c212: 7fbb ldrb r3, [r7, #30] + 800c214: f043 0308 orr.w r3, r3, #8 + 800c218: 77bb strb r3, [r7, #30] + } + if (split_flags & TCP_FIN) { + 800c21a: 7ffb ldrb r3, [r7, #31] + 800c21c: f003 0301 and.w r3, r3, #1 + 800c220: 2b00 cmp r3, #0 + 800c222: d007 beq.n 800c234 + split_flags &= ~TCP_FIN; + 800c224: 7ffb ldrb r3, [r7, #31] + 800c226: f023 0301 bic.w r3, r3, #1 + 800c22a: 77fb strb r3, [r7, #31] + remainder_flags |= TCP_FIN; + 800c22c: 7fbb ldrb r3, [r7, #30] + 800c22e: f043 0301 orr.w r3, r3, #1 + 800c232: 77bb strb r3, [r7, #30] + } + /* SYN should be left on split, RST should not be present with data */ + + seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags); + 800c234: 697b ldr r3, [r7, #20] + 800c236: 691b ldr r3, [r3, #16] + 800c238: 685b ldr r3, [r3, #4] + 800c23a: 4618 mov r0, r3 + 800c23c: f7f9 f99b bl 8005576 + 800c240: 4602 mov r2, r0 + 800c242: 887b ldrh r3, [r7, #2] + 800c244: 18d1 adds r1, r2, r3 + 800c246: 7fba ldrb r2, [r7, #30] + 800c248: 7bfb ldrb r3, [r7, #15] + 800c24a: 9300 str r3, [sp, #0] + 800c24c: 460b mov r3, r1 + 800c24e: 6939 ldr r1, [r7, #16] + 800c250: 6878 ldr r0, [r7, #4] + 800c252: f7ff f9f3 bl 800b63c + 800c256: 61b8 str r0, [r7, #24] + if (seg == NULL) { + 800c258: 69bb ldr r3, [r7, #24] + 800c25a: 2b00 cmp r3, #0 + 800c25c: d066 beq.n 800c32c + seg->chksum_swapped = chksum_swapped; + seg->flags |= TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Remove this segment from the queue since trimming it may free pbufs */ + pcb->snd_queuelen -= pbuf_clen(useg->p); + 800c25e: 697b ldr r3, [r7, #20] + 800c260: 685b ldr r3, [r3, #4] + 800c262: 4618 mov r0, r3 + 800c264: f7fa ff3e bl 80070e4 + 800c268: 4603 mov r3, r0 + 800c26a: 461a mov r2, r3 + 800c26c: 687b ldr r3, [r7, #4] + 800c26e: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c272: 1a9b subs r3, r3, r2 + 800c274: b29a uxth r2, r3 + 800c276: 687b ldr r3, [r7, #4] + 800c278: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + + /* Trim the original pbuf into our split size. At this point our remainder segment must be setup + successfully because we are modifying the original segment */ + pbuf_realloc(useg->p, useg->p->tot_len - remainder); + 800c27c: 697b ldr r3, [r7, #20] + 800c27e: 6858 ldr r0, [r3, #4] + 800c280: 697b ldr r3, [r7, #20] + 800c282: 685b ldr r3, [r3, #4] + 800c284: 891a ldrh r2, [r3, #8] + 800c286: 89bb ldrh r3, [r7, #12] + 800c288: 1ad3 subs r3, r2, r3 + 800c28a: b29b uxth r3, r3 + 800c28c: 4619 mov r1, r3 + 800c28e: f7fa fd1b bl 8006cc8 + useg->len -= remainder; + 800c292: 697b ldr r3, [r7, #20] + 800c294: 891a ldrh r2, [r3, #8] + 800c296: 89bb ldrh r3, [r7, #12] + 800c298: 1ad3 subs r3, r2, r3 + 800c29a: b29a uxth r2, r3 + 800c29c: 697b ldr r3, [r7, #20] + 800c29e: 811a strh r2, [r3, #8] + TCPH_SET_FLAG(useg->tcphdr, split_flags); + 800c2a0: 697b ldr r3, [r7, #20] + 800c2a2: 691b ldr r3, [r3, #16] + 800c2a4: 899b ldrh r3, [r3, #12] + 800c2a6: b29c uxth r4, r3 + 800c2a8: 7ffb ldrb r3, [r7, #31] + 800c2aa: b29b uxth r3, r3 + 800c2ac: 4618 mov r0, r3 + 800c2ae: f7f9 f94d bl 800554c + 800c2b2: 4603 mov r3, r0 + 800c2b4: 461a mov r2, r3 + 800c2b6: 697b ldr r3, [r7, #20] + 800c2b8: 691b ldr r3, [r3, #16] + 800c2ba: 4322 orrs r2, r4 + 800c2bc: b292 uxth r2, r2 + 800c2be: 819a strh r2, [r3, #12] +#if TCP_OVERSIZE_DBGCHECK + /* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */ + useg->oversize_left = 0; + 800c2c0: 697b ldr r3, [r7, #20] + 800c2c2: 2200 movs r2, #0 + 800c2c4: 815a strh r2, [r3, #10] +#endif /* TCP_OVERSIZE_DBGCHECK */ + + /* Add back to the queue with new trimmed pbuf */ + pcb->snd_queuelen += pbuf_clen(useg->p); + 800c2c6: 697b ldr r3, [r7, #20] + 800c2c8: 685b ldr r3, [r3, #4] + 800c2ca: 4618 mov r0, r3 + 800c2cc: f7fa ff0a bl 80070e4 + 800c2d0: 4603 mov r3, r0 + 800c2d2: 461a mov r2, r3 + 800c2d4: 687b ldr r3, [r7, #4] + 800c2d6: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c2da: 4413 add r3, r2 + 800c2dc: b29a uxth r2, r3 + 800c2de: 687b ldr r3, [r7, #4] + 800c2e0: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Update number of segments on the queues. Note that length now may + * exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf + * because the total amount of data is constant when packet is split */ + pcb->snd_queuelen += pbuf_clen(seg->p); + 800c2e4: 69bb ldr r3, [r7, #24] + 800c2e6: 685b ldr r3, [r3, #4] + 800c2e8: 4618 mov r0, r3 + 800c2ea: f7fa fefb bl 80070e4 + 800c2ee: 4603 mov r3, r0 + 800c2f0: 461a mov r2, r3 + 800c2f2: 687b ldr r3, [r7, #4] + 800c2f4: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c2f8: 4413 add r3, r2 + 800c2fa: b29a uxth r2, r3 + 800c2fc: 687b ldr r3, [r7, #4] + 800c2fe: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + + /* Finally insert remainder into queue after split (which stays head) */ + seg->next = useg->next; + 800c302: 697b ldr r3, [r7, #20] + 800c304: 681a ldr r2, [r3, #0] + 800c306: 69bb ldr r3, [r7, #24] + 800c308: 601a str r2, [r3, #0] + useg->next = seg; + 800c30a: 697b ldr r3, [r7, #20] + 800c30c: 69ba ldr r2, [r7, #24] + 800c30e: 601a str r2, [r3, #0] + +#if TCP_OVERSIZE + /* If remainder is last segment on the unsent, ensure we clear the oversize amount + * because the remainder is always sized to the exact remaining amount */ + if (seg->next == NULL) { + 800c310: 69bb ldr r3, [r7, #24] + 800c312: 681b ldr r3, [r3, #0] + 800c314: 2b00 cmp r3, #0 + 800c316: d103 bne.n 800c320 + pcb->unsent_oversize = 0; + 800c318: 687b ldr r3, [r7, #4] + 800c31a: 2200 movs r2, #0 + 800c31c: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + } +#endif /* TCP_OVERSIZE */ + + return ERR_OK; + 800c320: 2300 movs r3, #0 + 800c322: e016 b.n 800c352 + goto memerr; + 800c324: bf00 nop + 800c326: e002 b.n 800c32e + goto memerr; + 800c328: bf00 nop + 800c32a: e000 b.n 800c32e + goto memerr; + 800c32c: bf00 nop +memerr: + TCP_STATS_INC(tcp.memerr); + + LWIP_ASSERT("seg == NULL", seg == NULL); + 800c32e: 69bb ldr r3, [r7, #24] + 800c330: 2b00 cmp r3, #0 + 800c332: d006 beq.n 800c342 + 800c334: 4b09 ldr r3, [pc, #36] ; (800c35c ) + 800c336: f44f 7276 mov.w r2, #984 ; 0x3d8 + 800c33a: 490e ldr r1, [pc, #56] ; (800c374 ) + 800c33c: 4809 ldr r0, [pc, #36] ; (800c364 ) + 800c33e: f004 fc43 bl 8010bc8 + if (p != NULL) { + 800c342: 693b ldr r3, [r7, #16] + 800c344: 2b00 cmp r3, #0 + 800c346: d002 beq.n 800c34e + pbuf_free(p); + 800c348: 6938 ldr r0, [r7, #16] + 800c34a: f7fa fe43 bl 8006fd4 + } + + return ERR_MEM; + 800c34e: f04f 33ff mov.w r3, #4294967295 +} + 800c352: 4618 mov r0, r3 + 800c354: 3724 adds r7, #36 ; 0x24 + 800c356: 46bd mov sp, r7 + 800c358: bd90 pop {r4, r7, pc} + 800c35a: bf00 nop + 800c35c: 08013618 .word 0x08013618 + 800c360: 08013a08 .word 0x08013a08 + 800c364: 0801366c .word 0x0801366c + 800c368: 08013a2c .word 0x08013a2c + 800c36c: 08013a50 .word 0x08013a50 + 800c370: 08013a60 .word 0x08013a60 + 800c374: 08013a70 .word 0x08013a70 + +0800c378 : + * @param pcb the tcp_pcb over which to send a segment + * @return ERR_OK if sent, another err_t otherwise + */ +err_t +tcp_send_fin(struct tcp_pcb *pcb) +{ + 800c378: b590 push {r4, r7, lr} + 800c37a: b085 sub sp, #20 + 800c37c: af00 add r7, sp, #0 + 800c37e: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL); + 800c380: 687b ldr r3, [r7, #4] + 800c382: 2b00 cmp r3, #0 + 800c384: d106 bne.n 800c394 + 800c386: 4b21 ldr r3, [pc, #132] ; (800c40c ) + 800c388: f240 32eb movw r2, #1003 ; 0x3eb + 800c38c: 4920 ldr r1, [pc, #128] ; (800c410 ) + 800c38e: 4821 ldr r0, [pc, #132] ; (800c414 ) + 800c390: f004 fc1a bl 8010bc8 + + /* first, try to add the fin to the last unsent segment */ + if (pcb->unsent != NULL) { + 800c394: 687b ldr r3, [r7, #4] + 800c396: 6edb ldr r3, [r3, #108] ; 0x6c + 800c398: 2b00 cmp r3, #0 + 800c39a: d02e beq.n 800c3fa + struct tcp_seg *last_unsent; + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + 800c39c: 687b ldr r3, [r7, #4] + 800c39e: 6edb ldr r3, [r3, #108] ; 0x6c + 800c3a0: 60fb str r3, [r7, #12] + 800c3a2: e002 b.n 800c3aa + last_unsent = last_unsent->next); + 800c3a4: 68fb ldr r3, [r7, #12] + 800c3a6: 681b ldr r3, [r3, #0] + 800c3a8: 60fb str r3, [r7, #12] + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + 800c3aa: 68fb ldr r3, [r7, #12] + 800c3ac: 681b ldr r3, [r3, #0] + 800c3ae: 2b00 cmp r3, #0 + 800c3b0: d1f8 bne.n 800c3a4 + + if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) { + 800c3b2: 68fb ldr r3, [r7, #12] + 800c3b4: 691b ldr r3, [r3, #16] + 800c3b6: 899b ldrh r3, [r3, #12] + 800c3b8: b29b uxth r3, r3 + 800c3ba: 4618 mov r0, r3 + 800c3bc: f7f9 f8c6 bl 800554c + 800c3c0: 4603 mov r3, r0 + 800c3c2: b2db uxtb r3, r3 + 800c3c4: f003 0307 and.w r3, r3, #7 + 800c3c8: 2b00 cmp r3, #0 + 800c3ca: d116 bne.n 800c3fa + /* no SYN/FIN/RST flag in the header, we can add the FIN flag */ + TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN); + 800c3cc: 68fb ldr r3, [r7, #12] + 800c3ce: 691b ldr r3, [r3, #16] + 800c3d0: 899b ldrh r3, [r3, #12] + 800c3d2: b29c uxth r4, r3 + 800c3d4: 2001 movs r0, #1 + 800c3d6: f7f9 f8b9 bl 800554c + 800c3da: 4603 mov r3, r0 + 800c3dc: 461a mov r2, r3 + 800c3de: 68fb ldr r3, [r7, #12] + 800c3e0: 691b ldr r3, [r3, #16] + 800c3e2: 4322 orrs r2, r4 + 800c3e4: b292 uxth r2, r2 + 800c3e6: 819a strh r2, [r3, #12] + tcp_set_flags(pcb, TF_FIN); + 800c3e8: 687b ldr r3, [r7, #4] + 800c3ea: 8b5b ldrh r3, [r3, #26] + 800c3ec: f043 0320 orr.w r3, r3, #32 + 800c3f0: b29a uxth r2, r3 + 800c3f2: 687b ldr r3, [r7, #4] + 800c3f4: 835a strh r2, [r3, #26] + return ERR_OK; + 800c3f6: 2300 movs r3, #0 + 800c3f8: e004 b.n 800c404 + } + } + /* no data, no length, flags, copy=1, no optdata */ + return tcp_enqueue_flags(pcb, TCP_FIN); + 800c3fa: 2101 movs r1, #1 + 800c3fc: 6878 ldr r0, [r7, #4] + 800c3fe: f000 f80b bl 800c418 + 800c402: 4603 mov r3, r0 +} + 800c404: 4618 mov r0, r3 + 800c406: 3714 adds r7, #20 + 800c408: 46bd mov sp, r7 + 800c40a: bd90 pop {r4, r7, pc} + 800c40c: 08013618 .word 0x08013618 + 800c410: 08013a7c .word 0x08013a7c + 800c414: 0801366c .word 0x0801366c + +0800c418 : + * @param pcb Protocol control block for the TCP connection. + * @param flags TCP header flags to set in the outgoing segment. + */ +err_t +tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags) +{ + 800c418: b580 push {r7, lr} + 800c41a: b088 sub sp, #32 + 800c41c: af02 add r7, sp, #8 + 800c41e: 6078 str r0, [r7, #4] + 800c420: 460b mov r3, r1 + 800c422: 70fb strb r3, [r7, #3] + struct pbuf *p; + struct tcp_seg *seg; + u8_t optflags = 0; + 800c424: 2300 movs r3, #0 + 800c426: 75fb strb r3, [r7, #23] + u8_t optlen = 0; + 800c428: 2300 movs r3, #0 + 800c42a: 75bb strb r3, [r7, #22] + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)", + 800c42c: 78fb ldrb r3, [r7, #3] + 800c42e: f003 0303 and.w r3, r3, #3 + 800c432: 2b00 cmp r3, #0 + 800c434: d106 bne.n 800c444 + 800c436: 4b67 ldr r3, [pc, #412] ; (800c5d4 ) + 800c438: f240 4211 movw r2, #1041 ; 0x411 + 800c43c: 4966 ldr r1, [pc, #408] ; (800c5d8 ) + 800c43e: 4867 ldr r0, [pc, #412] ; (800c5dc ) + 800c440: f004 fbc2 bl 8010bc8 + (flags & (TCP_SYN | TCP_FIN)) != 0); + LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL); + 800c444: 687b ldr r3, [r7, #4] + 800c446: 2b00 cmp r3, #0 + 800c448: d106 bne.n 800c458 + 800c44a: 4b62 ldr r3, [pc, #392] ; (800c5d4 ) + 800c44c: f240 4213 movw r2, #1043 ; 0x413 + 800c450: 4963 ldr r1, [pc, #396] ; (800c5e0 ) + 800c452: 4862 ldr r0, [pc, #392] ; (800c5dc ) + 800c454: f004 fbb8 bl 8010bc8 + + /* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */ + + /* Get options for this segment. This is a special case since this is the + only place where a SYN can be sent. */ + if (flags & TCP_SYN) { + 800c458: 78fb ldrb r3, [r7, #3] + 800c45a: f003 0302 and.w r3, r3, #2 + 800c45e: 2b00 cmp r3, #0 + 800c460: d001 beq.n 800c466 + optflags = TF_SEG_OPTS_MSS; + 800c462: 2301 movs r3, #1 + 800c464: 75fb strb r3, [r7, #23] + /* Make sure the timestamp option is only included in data segments if we + agreed about it with the remote host (and in active open SYN segments). */ + optflags |= TF_SEG_OPTS_TS; + } +#endif /* LWIP_TCP_TIMESTAMPS */ + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + 800c466: 7dfb ldrb r3, [r7, #23] + 800c468: 009b lsls r3, r3, #2 + 800c46a: b2db uxtb r3, r3 + 800c46c: f003 0304 and.w r3, r3, #4 + 800c470: 75bb strb r3, [r7, #22] + + /* Allocate pbuf with room for TCP header + options */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + 800c472: 7dbb ldrb r3, [r7, #22] + 800c474: b29b uxth r3, r3 + 800c476: f44f 7220 mov.w r2, #640 ; 0x280 + 800c47a: 4619 mov r1, r3 + 800c47c: 2036 movs r0, #54 ; 0x36 + 800c47e: f7fa fac5 bl 8006a0c + 800c482: 60f8 str r0, [r7, #12] + 800c484: 68fb ldr r3, [r7, #12] + 800c486: 2b00 cmp r3, #0 + 800c488: d109 bne.n 800c49e + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 800c48a: 687b ldr r3, [r7, #4] + 800c48c: 8b5b ldrh r3, [r3, #26] + 800c48e: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800c492: b29a uxth r2, r3 + 800c494: 687b ldr r3, [r7, #4] + 800c496: 835a strh r2, [r3, #26] + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + 800c498: f04f 33ff mov.w r3, #4294967295 + 800c49c: e095 b.n 800c5ca + } + LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen", + 800c49e: 68fb ldr r3, [r7, #12] + 800c4a0: 895a ldrh r2, [r3, #10] + 800c4a2: 7dbb ldrb r3, [r7, #22] + 800c4a4: b29b uxth r3, r3 + 800c4a6: 429a cmp r2, r3 + 800c4a8: d206 bcs.n 800c4b8 + 800c4aa: 4b4a ldr r3, [pc, #296] ; (800c5d4 ) + 800c4ac: f240 4239 movw r2, #1081 ; 0x439 + 800c4b0: 494c ldr r1, [pc, #304] ; (800c5e4 ) + 800c4b2: 484a ldr r0, [pc, #296] ; (800c5dc ) + 800c4b4: f004 fb88 bl 8010bc8 + (p->len >= optlen)); + + /* Allocate memory for tcp_seg, and fill in fields. */ + if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) { + 800c4b8: 687b ldr r3, [r7, #4] + 800c4ba: 6dd9 ldr r1, [r3, #92] ; 0x5c + 800c4bc: 78fa ldrb r2, [r7, #3] + 800c4be: 7dfb ldrb r3, [r7, #23] + 800c4c0: 9300 str r3, [sp, #0] + 800c4c2: 460b mov r3, r1 + 800c4c4: 68f9 ldr r1, [r7, #12] + 800c4c6: 6878 ldr r0, [r7, #4] + 800c4c8: f7ff f8b8 bl 800b63c + 800c4cc: 60b8 str r0, [r7, #8] + 800c4ce: 68bb ldr r3, [r7, #8] + 800c4d0: 2b00 cmp r3, #0 + 800c4d2: d109 bne.n 800c4e8 + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 800c4d4: 687b ldr r3, [r7, #4] + 800c4d6: 8b5b ldrh r3, [r3, #26] + 800c4d8: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800c4dc: b29a uxth r2, r3 + 800c4de: 687b ldr r3, [r7, #4] + 800c4e0: 835a strh r2, [r3, #26] + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + 800c4e2: f04f 33ff mov.w r3, #4294967295 + 800c4e6: e070 b.n 800c5ca + } + LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0); + 800c4e8: 68bb ldr r3, [r7, #8] + 800c4ea: 691b ldr r3, [r3, #16] + 800c4ec: f003 0303 and.w r3, r3, #3 + 800c4f0: 2b00 cmp r3, #0 + 800c4f2: d006 beq.n 800c502 + 800c4f4: 4b37 ldr r3, [pc, #220] ; (800c5d4 ) + 800c4f6: f240 4242 movw r2, #1090 ; 0x442 + 800c4fa: 493b ldr r1, [pc, #236] ; (800c5e8 ) + 800c4fc: 4837 ldr r0, [pc, #220] ; (800c5dc ) + 800c4fe: f004 fb63 bl 8010bc8 + LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0); + 800c502: 68bb ldr r3, [r7, #8] + 800c504: 891b ldrh r3, [r3, #8] + 800c506: 2b00 cmp r3, #0 + 800c508: d006 beq.n 800c518 + 800c50a: 4b32 ldr r3, [pc, #200] ; (800c5d4 ) + 800c50c: f240 4243 movw r2, #1091 ; 0x443 + 800c510: 4936 ldr r1, [pc, #216] ; (800c5ec ) + 800c512: 4832 ldr r0, [pc, #200] ; (800c5dc ) + 800c514: f004 fb58 bl 8010bc8 + lwip_ntohl(seg->tcphdr->seqno), + lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), + (u16_t)flags)); + + /* Now append seg to pcb->unsent queue */ + if (pcb->unsent == NULL) { + 800c518: 687b ldr r3, [r7, #4] + 800c51a: 6edb ldr r3, [r3, #108] ; 0x6c + 800c51c: 2b00 cmp r3, #0 + 800c51e: d103 bne.n 800c528 + pcb->unsent = seg; + 800c520: 687b ldr r3, [r7, #4] + 800c522: 68ba ldr r2, [r7, #8] + 800c524: 66da str r2, [r3, #108] ; 0x6c + 800c526: e00d b.n 800c544 + } else { + struct tcp_seg *useg; + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + 800c528: 687b ldr r3, [r7, #4] + 800c52a: 6edb ldr r3, [r3, #108] ; 0x6c + 800c52c: 613b str r3, [r7, #16] + 800c52e: e002 b.n 800c536 + 800c530: 693b ldr r3, [r7, #16] + 800c532: 681b ldr r3, [r3, #0] + 800c534: 613b str r3, [r7, #16] + 800c536: 693b ldr r3, [r7, #16] + 800c538: 681b ldr r3, [r3, #0] + 800c53a: 2b00 cmp r3, #0 + 800c53c: d1f8 bne.n 800c530 + useg->next = seg; + 800c53e: 693b ldr r3, [r7, #16] + 800c540: 68ba ldr r2, [r7, #8] + 800c542: 601a str r2, [r3, #0] + } +#if TCP_OVERSIZE + /* The new unsent tail has no space */ + pcb->unsent_oversize = 0; + 800c544: 687b ldr r3, [r7, #4] + 800c546: 2200 movs r2, #0 + 800c548: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 +#endif /* TCP_OVERSIZE */ + + /* SYN and FIN bump the sequence number */ + if ((flags & TCP_SYN) || (flags & TCP_FIN)) { + 800c54c: 78fb ldrb r3, [r7, #3] + 800c54e: f003 0302 and.w r3, r3, #2 + 800c552: 2b00 cmp r3, #0 + 800c554: d104 bne.n 800c560 + 800c556: 78fb ldrb r3, [r7, #3] + 800c558: f003 0301 and.w r3, r3, #1 + 800c55c: 2b00 cmp r3, #0 + 800c55e: d004 beq.n 800c56a + pcb->snd_lbb++; + 800c560: 687b ldr r3, [r7, #4] + 800c562: 6ddb ldr r3, [r3, #92] ; 0x5c + 800c564: 1c5a adds r2, r3, #1 + 800c566: 687b ldr r3, [r7, #4] + 800c568: 65da str r2, [r3, #92] ; 0x5c + /* optlen does not influence snd_buf */ + } + if (flags & TCP_FIN) { + 800c56a: 78fb ldrb r3, [r7, #3] + 800c56c: f003 0301 and.w r3, r3, #1 + 800c570: 2b00 cmp r3, #0 + 800c572: d006 beq.n 800c582 + tcp_set_flags(pcb, TF_FIN); + 800c574: 687b ldr r3, [r7, #4] + 800c576: 8b5b ldrh r3, [r3, #26] + 800c578: f043 0320 orr.w r3, r3, #32 + 800c57c: b29a uxth r2, r3 + 800c57e: 687b ldr r3, [r7, #4] + 800c580: 835a strh r2, [r3, #26] + } + + /* update number of segments on the queues */ + pcb->snd_queuelen += pbuf_clen(seg->p); + 800c582: 68bb ldr r3, [r7, #8] + 800c584: 685b ldr r3, [r3, #4] + 800c586: 4618 mov r0, r3 + 800c588: f7fa fdac bl 80070e4 + 800c58c: 4603 mov r3, r0 + 800c58e: 461a mov r2, r3 + 800c590: 687b ldr r3, [r7, #4] + 800c592: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c596: 4413 add r3, r2 + 800c598: b29a uxth r2, r3 + 800c59a: 687b ldr r3, [r7, #4] + 800c59c: f8a3 2066 strh.w r2, [r3, #102] ; 0x66 + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + 800c5a0: 687b ldr r3, [r7, #4] + 800c5a2: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c5a6: 2b00 cmp r3, #0 + 800c5a8: d00e beq.n 800c5c8 + LWIP_ASSERT("tcp_enqueue_flags: invalid queue length", + 800c5aa: 687b ldr r3, [r7, #4] + 800c5ac: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c5ae: 2b00 cmp r3, #0 + 800c5b0: d10a bne.n 800c5c8 + 800c5b2: 687b ldr r3, [r7, #4] + 800c5b4: 6edb ldr r3, [r3, #108] ; 0x6c + 800c5b6: 2b00 cmp r3, #0 + 800c5b8: d106 bne.n 800c5c8 + 800c5ba: 4b06 ldr r3, [pc, #24] ; (800c5d4 ) + 800c5bc: f240 4265 movw r2, #1125 ; 0x465 + 800c5c0: 490b ldr r1, [pc, #44] ; (800c5f0 ) + 800c5c2: 4806 ldr r0, [pc, #24] ; (800c5dc ) + 800c5c4: f004 fb00 bl 8010bc8 + pcb->unacked != NULL || pcb->unsent != NULL); + } + + return ERR_OK; + 800c5c8: 2300 movs r3, #0 +} + 800c5ca: 4618 mov r0, r3 + 800c5cc: 3718 adds r7, #24 + 800c5ce: 46bd mov sp, r7 + 800c5d0: bd80 pop {r7, pc} + 800c5d2: bf00 nop + 800c5d4: 08013618 .word 0x08013618 + 800c5d8: 08013a98 .word 0x08013a98 + 800c5dc: 0801366c .word 0x0801366c + 800c5e0: 08013af0 .word 0x08013af0 + 800c5e4: 08013b10 .word 0x08013b10 + 800c5e8: 08013b4c .word 0x08013b4c + 800c5ec: 08013b64 .word 0x08013b64 + 800c5f0: 08013b90 .word 0x08013b90 + +0800c5f4 : + * @return ERR_OK if data has been sent or nothing to send + * another err_t on error + */ +err_t +tcp_output(struct tcp_pcb *pcb) +{ + 800c5f4: b5b0 push {r4, r5, r7, lr} + 800c5f6: b08a sub sp, #40 ; 0x28 + 800c5f8: af00 add r7, sp, #0 + 800c5fa: 6078 str r0, [r7, #4] + s16_t i = 0; +#endif /* TCP_CWND_DEBUG */ + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL); + 800c5fc: 687b ldr r3, [r7, #4] + 800c5fe: 2b00 cmp r3, #0 + 800c600: d106 bne.n 800c610 + 800c602: 4b8a ldr r3, [pc, #552] ; (800c82c ) + 800c604: f240 42e1 movw r2, #1249 ; 0x4e1 + 800c608: 4989 ldr r1, [pc, #548] ; (800c830 ) + 800c60a: 488a ldr r0, [pc, #552] ; (800c834 ) + 800c60c: f004 fadc bl 8010bc8 + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_output for listen-pcbs", + 800c610: 687b ldr r3, [r7, #4] + 800c612: 7d1b ldrb r3, [r3, #20] + 800c614: 2b01 cmp r3, #1 + 800c616: d106 bne.n 800c626 + 800c618: 4b84 ldr r3, [pc, #528] ; (800c82c ) + 800c61a: f240 42e3 movw r2, #1251 ; 0x4e3 + 800c61e: 4986 ldr r1, [pc, #536] ; (800c838 ) + 800c620: 4884 ldr r0, [pc, #528] ; (800c834 ) + 800c622: f004 fad1 bl 8010bc8 + + /* First, check if we are invoked by the TCP input processing + code. If so, we do not output anything. Instead, we rely on the + input processing code to call us when input processing is done + with. */ + if (tcp_input_pcb == pcb) { + 800c626: 4b85 ldr r3, [pc, #532] ; (800c83c ) + 800c628: 681b ldr r3, [r3, #0] + 800c62a: 687a ldr r2, [r7, #4] + 800c62c: 429a cmp r2, r3 + 800c62e: d101 bne.n 800c634 + return ERR_OK; + 800c630: 2300 movs r3, #0 + 800c632: e1d1 b.n 800c9d8 + } + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + 800c634: 687b ldr r3, [r7, #4] + 800c636: f8b3 2048 ldrh.w r2, [r3, #72] ; 0x48 + 800c63a: 687b ldr r3, [r7, #4] + 800c63c: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800c640: 4293 cmp r3, r2 + 800c642: bf28 it cs + 800c644: 4613 movcs r3, r2 + 800c646: b29b uxth r3, r3 + 800c648: 61bb str r3, [r7, #24] + + seg = pcb->unsent; + 800c64a: 687b ldr r3, [r7, #4] + 800c64c: 6edb ldr r3, [r3, #108] ; 0x6c + 800c64e: 627b str r3, [r7, #36] ; 0x24 + + if (seg == NULL) { + 800c650: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c652: 2b00 cmp r3, #0 + 800c654: d10b bne.n 800c66e + ", seg == NULL, ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); + + /* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct + * an empty ACK segment and send it. */ + if (pcb->flags & TF_ACK_NOW) { + 800c656: 687b ldr r3, [r7, #4] + 800c658: 8b5b ldrh r3, [r3, #26] + 800c65a: f003 0302 and.w r3, r3, #2 + 800c65e: 2b00 cmp r3, #0 + 800c660: f000 81ad beq.w 800c9be + return tcp_send_empty_ack(pcb); + 800c664: 6878 ldr r0, [r7, #4] + 800c666: f000 fdd7 bl 800d218 + 800c66a: 4603 mov r3, r0 + 800c66c: e1b4 b.n 800c9d8 + pcb->snd_wnd, pcb->cwnd, wnd, + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + lwip_ntohl(seg->tcphdr->seqno), pcb->lastack)); + } + + netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip); + 800c66e: 6879 ldr r1, [r7, #4] + 800c670: 687b ldr r3, [r7, #4] + 800c672: 3304 adds r3, #4 + 800c674: 461a mov r2, r3 + 800c676: 6878 ldr r0, [r7, #4] + 800c678: f7fe ffc4 bl 800b604 + 800c67c: 6178 str r0, [r7, #20] + if (netif == NULL) { + 800c67e: 697b ldr r3, [r7, #20] + 800c680: 2b00 cmp r3, #0 + 800c682: d102 bne.n 800c68a + return ERR_RTE; + 800c684: f06f 0303 mvn.w r3, #3 + 800c688: e1a6 b.n 800c9d8 + } + + /* If we don't have a local IP address, we get one from netif */ + if (ip_addr_isany(&pcb->local_ip)) { + 800c68a: 687b ldr r3, [r7, #4] + 800c68c: 2b00 cmp r3, #0 + 800c68e: d003 beq.n 800c698 + 800c690: 687b ldr r3, [r7, #4] + 800c692: 681b ldr r3, [r3, #0] + 800c694: 2b00 cmp r3, #0 + 800c696: d111 bne.n 800c6bc + const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip); + 800c698: 697b ldr r3, [r7, #20] + 800c69a: 2b00 cmp r3, #0 + 800c69c: d002 beq.n 800c6a4 + 800c69e: 697b ldr r3, [r7, #20] + 800c6a0: 3304 adds r3, #4 + 800c6a2: e000 b.n 800c6a6 + 800c6a4: 2300 movs r3, #0 + 800c6a6: 613b str r3, [r7, #16] + if (local_ip == NULL) { + 800c6a8: 693b ldr r3, [r7, #16] + 800c6aa: 2b00 cmp r3, #0 + 800c6ac: d102 bne.n 800c6b4 + return ERR_RTE; + 800c6ae: f06f 0303 mvn.w r3, #3 + 800c6b2: e191 b.n 800c9d8 + } + ip_addr_copy(pcb->local_ip, *local_ip); + 800c6b4: 693b ldr r3, [r7, #16] + 800c6b6: 681a ldr r2, [r3, #0] + 800c6b8: 687b ldr r3, [r7, #4] + 800c6ba: 601a str r2, [r3, #0] + } + + /* Handle the current segment not fitting within the window */ + if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) { + 800c6bc: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c6be: 691b ldr r3, [r3, #16] + 800c6c0: 685b ldr r3, [r3, #4] + 800c6c2: 4618 mov r0, r3 + 800c6c4: f7f8 ff57 bl 8005576 + 800c6c8: 4602 mov r2, r0 + 800c6ca: 687b ldr r3, [r7, #4] + 800c6cc: 6c5b ldr r3, [r3, #68] ; 0x44 + 800c6ce: 1ad3 subs r3, r2, r3 + 800c6d0: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c6d2: 8912 ldrh r2, [r2, #8] + 800c6d4: 4413 add r3, r2 + 800c6d6: 69ba ldr r2, [r7, #24] + 800c6d8: 429a cmp r2, r3 + 800c6da: d227 bcs.n 800c72c + * within the remaining (could be 0) send window and RTO timer is not running (we + * have no in-flight data). If window is still too small after persist timer fires, + * then we split the segment. We don't consider the congestion window since a cwnd + * smaller than 1 SMSS implies in-flight data + */ + if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) { + 800c6dc: 687b ldr r3, [r7, #4] + 800c6de: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800c6e2: 461a mov r2, r3 + 800c6e4: 69bb ldr r3, [r7, #24] + 800c6e6: 4293 cmp r3, r2 + 800c6e8: d114 bne.n 800c714 + 800c6ea: 687b ldr r3, [r7, #4] + 800c6ec: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c6ee: 2b00 cmp r3, #0 + 800c6f0: d110 bne.n 800c714 + 800c6f2: 687b ldr r3, [r7, #4] + 800c6f4: f893 3099 ldrb.w r3, [r3, #153] ; 0x99 + 800c6f8: 2b00 cmp r3, #0 + 800c6fa: d10b bne.n 800c714 + pcb->persist_cnt = 0; + 800c6fc: 687b ldr r3, [r7, #4] + 800c6fe: 2200 movs r2, #0 + 800c700: f883 2098 strb.w r2, [r3, #152] ; 0x98 + pcb->persist_backoff = 1; + 800c704: 687b ldr r3, [r7, #4] + 800c706: 2201 movs r2, #1 + 800c708: f883 2099 strb.w r2, [r3, #153] ; 0x99 + pcb->persist_probe = 0; + 800c70c: 687b ldr r3, [r7, #4] + 800c70e: 2200 movs r2, #0 + 800c710: f883 209a strb.w r2, [r3, #154] ; 0x9a + } + /* We need an ACK, but can't send data now, so send an empty ACK */ + if (pcb->flags & TF_ACK_NOW) { + 800c714: 687b ldr r3, [r7, #4] + 800c716: 8b5b ldrh r3, [r3, #26] + 800c718: f003 0302 and.w r3, r3, #2 + 800c71c: 2b00 cmp r3, #0 + 800c71e: f000 8150 beq.w 800c9c2 + return tcp_send_empty_ack(pcb); + 800c722: 6878 ldr r0, [r7, #4] + 800c724: f000 fd78 bl 800d218 + 800c728: 4603 mov r3, r0 + 800c72a: e155 b.n 800c9d8 + } + goto output_done; + } + /* Stop persist timer, above conditions are not active */ + pcb->persist_backoff = 0; + 800c72c: 687b ldr r3, [r7, #4] + 800c72e: 2200 movs r2, #0 + 800c730: f883 2099 strb.w r2, [r3, #153] ; 0x99 + + /* useg should point to last segment on unacked queue */ + useg = pcb->unacked; + 800c734: 687b ldr r3, [r7, #4] + 800c736: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c738: 623b str r3, [r7, #32] + if (useg != NULL) { + 800c73a: 6a3b ldr r3, [r7, #32] + 800c73c: 2b00 cmp r3, #0 + 800c73e: f000 811f beq.w 800c980 + for (; useg->next != NULL; useg = useg->next); + 800c742: e002 b.n 800c74a + 800c744: 6a3b ldr r3, [r7, #32] + 800c746: 681b ldr r3, [r3, #0] + 800c748: 623b str r3, [r7, #32] + 800c74a: 6a3b ldr r3, [r7, #32] + 800c74c: 681b ldr r3, [r3, #0] + 800c74e: 2b00 cmp r3, #0 + 800c750: d1f8 bne.n 800c744 + } + /* data available and window allows it to be sent? */ + while (seg != NULL && + 800c752: e115 b.n 800c980 + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + LWIP_ASSERT("RST not expected here!", + 800c754: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c756: 691b ldr r3, [r3, #16] + 800c758: 899b ldrh r3, [r3, #12] + 800c75a: b29b uxth r3, r3 + 800c75c: 4618 mov r0, r3 + 800c75e: f7f8 fef5 bl 800554c + 800c762: 4603 mov r3, r0 + 800c764: b2db uxtb r3, r3 + 800c766: f003 0304 and.w r3, r3, #4 + 800c76a: 2b00 cmp r3, #0 + 800c76c: d006 beq.n 800c77c + 800c76e: 4b2f ldr r3, [pc, #188] ; (800c82c ) + 800c770: f240 5236 movw r2, #1334 ; 0x536 + 800c774: 4932 ldr r1, [pc, #200] ; (800c840 ) + 800c776: 482f ldr r0, [pc, #188] ; (800c834 ) + 800c778: f004 fa26 bl 8010bc8 + * - if tcp_write had a memory error before (prevent delayed ACK timeout) or + * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - + * either seg->next != NULL or pcb->unacked == NULL; + * RST is no sent using tcp_write/tcp_output. + */ + if ((tcp_do_output_nagle(pcb) == 0) && + 800c77c: 687b ldr r3, [r7, #4] + 800c77e: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c780: 2b00 cmp r3, #0 + 800c782: d01f beq.n 800c7c4 + 800c784: 687b ldr r3, [r7, #4] + 800c786: 8b5b ldrh r3, [r3, #26] + 800c788: f003 0344 and.w r3, r3, #68 ; 0x44 + 800c78c: 2b00 cmp r3, #0 + 800c78e: d119 bne.n 800c7c4 + 800c790: 687b ldr r3, [r7, #4] + 800c792: 6edb ldr r3, [r3, #108] ; 0x6c + 800c794: 2b00 cmp r3, #0 + 800c796: d00b beq.n 800c7b0 + 800c798: 687b ldr r3, [r7, #4] + 800c79a: 6edb ldr r3, [r3, #108] ; 0x6c + 800c79c: 681b ldr r3, [r3, #0] + 800c79e: 2b00 cmp r3, #0 + 800c7a0: d110 bne.n 800c7c4 + 800c7a2: 687b ldr r3, [r7, #4] + 800c7a4: 6edb ldr r3, [r3, #108] ; 0x6c + 800c7a6: 891a ldrh r2, [r3, #8] + 800c7a8: 687b ldr r3, [r7, #4] + 800c7aa: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800c7ac: 429a cmp r2, r3 + 800c7ae: d209 bcs.n 800c7c4 + 800c7b0: 687b ldr r3, [r7, #4] + 800c7b2: f8b3 3064 ldrh.w r3, [r3, #100] ; 0x64 + 800c7b6: 2b00 cmp r3, #0 + 800c7b8: d004 beq.n 800c7c4 + 800c7ba: 687b ldr r3, [r7, #4] + 800c7bc: f8b3 3066 ldrh.w r3, [r3, #102] ; 0x66 + 800c7c0: 2b08 cmp r3, #8 + 800c7c2: d901 bls.n 800c7c8 + 800c7c4: 2301 movs r3, #1 + 800c7c6: e000 b.n 800c7ca + 800c7c8: 2300 movs r3, #0 + 800c7ca: 2b00 cmp r3, #0 + 800c7cc: d106 bne.n 800c7dc + ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) { + 800c7ce: 687b ldr r3, [r7, #4] + 800c7d0: 8b5b ldrh r3, [r3, #26] + 800c7d2: f003 03a0 and.w r3, r3, #160 ; 0xa0 + if ((tcp_do_output_nagle(pcb) == 0) && + 800c7d6: 2b00 cmp r3, #0 + 800c7d8: f000 80e7 beq.w 800c9aa + pcb->lastack, + lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i)); + ++i; +#endif /* TCP_CWND_DEBUG */ + + if (pcb->state != SYN_SENT) { + 800c7dc: 687b ldr r3, [r7, #4] + 800c7de: 7d1b ldrb r3, [r3, #20] + 800c7e0: 2b02 cmp r3, #2 + 800c7e2: d00d beq.n 800c800 + TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); + 800c7e4: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c7e6: 691b ldr r3, [r3, #16] + 800c7e8: 899b ldrh r3, [r3, #12] + 800c7ea: b29c uxth r4, r3 + 800c7ec: 2010 movs r0, #16 + 800c7ee: f7f8 fead bl 800554c + 800c7f2: 4603 mov r3, r0 + 800c7f4: 461a mov r2, r3 + 800c7f6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c7f8: 691b ldr r3, [r3, #16] + 800c7fa: 4322 orrs r2, r4 + 800c7fc: b292 uxth r2, r2 + 800c7fe: 819a strh r2, [r3, #12] + } + + err = tcp_output_segment(seg, pcb, netif); + 800c800: 697a ldr r2, [r7, #20] + 800c802: 6879 ldr r1, [r7, #4] + 800c804: 6a78 ldr r0, [r7, #36] ; 0x24 + 800c806: f000 f90b bl 800ca20 + 800c80a: 4603 mov r3, r0 + 800c80c: 73fb strb r3, [r7, #15] + if (err != ERR_OK) { + 800c80e: f997 300f ldrsb.w r3, [r7, #15] + 800c812: 2b00 cmp r3, #0 + 800c814: d016 beq.n 800c844 + /* segment could not be sent, for whatever reason */ + tcp_set_flags(pcb, TF_NAGLEMEMERR); + 800c816: 687b ldr r3, [r7, #4] + 800c818: 8b5b ldrh r3, [r3, #26] + 800c81a: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800c81e: b29a uxth r2, r3 + 800c820: 687b ldr r3, [r7, #4] + 800c822: 835a strh r2, [r3, #26] + return err; + 800c824: f997 300f ldrsb.w r3, [r7, #15] + 800c828: e0d6 b.n 800c9d8 + 800c82a: bf00 nop + 800c82c: 08013618 .word 0x08013618 + 800c830: 08013bb8 .word 0x08013bb8 + 800c834: 0801366c .word 0x0801366c + 800c838: 08013bd0 .word 0x08013bd0 + 800c83c: 24007bbc .word 0x24007bbc + 800c840: 08013bf8 .word 0x08013bf8 + } +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = 0; + 800c844: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c846: 2200 movs r2, #0 + 800c848: 815a strh r2, [r3, #10] +#endif /* TCP_OVERSIZE_DBGCHECK */ + pcb->unsent = seg->next; + 800c84a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c84c: 681a ldr r2, [r3, #0] + 800c84e: 687b ldr r3, [r7, #4] + 800c850: 66da str r2, [r3, #108] ; 0x6c + if (pcb->state != SYN_SENT) { + 800c852: 687b ldr r3, [r7, #4] + 800c854: 7d1b ldrb r3, [r3, #20] + 800c856: 2b02 cmp r3, #2 + 800c858: d006 beq.n 800c868 + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 800c85a: 687b ldr r3, [r7, #4] + 800c85c: 8b5b ldrh r3, [r3, #26] + 800c85e: f023 0303 bic.w r3, r3, #3 + 800c862: b29a uxth r2, r3 + 800c864: 687b ldr r3, [r7, #4] + 800c866: 835a strh r2, [r3, #26] + } + snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + 800c868: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c86a: 691b ldr r3, [r3, #16] + 800c86c: 685b ldr r3, [r3, #4] + 800c86e: 4618 mov r0, r3 + 800c870: f7f8 fe81 bl 8005576 + 800c874: 4604 mov r4, r0 + 800c876: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c878: 891b ldrh r3, [r3, #8] + 800c87a: 461d mov r5, r3 + 800c87c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c87e: 691b ldr r3, [r3, #16] + 800c880: 899b ldrh r3, [r3, #12] + 800c882: b29b uxth r3, r3 + 800c884: 4618 mov r0, r3 + 800c886: f7f8 fe61 bl 800554c + 800c88a: 4603 mov r3, r0 + 800c88c: b2db uxtb r3, r3 + 800c88e: f003 0303 and.w r3, r3, #3 + 800c892: 2b00 cmp r3, #0 + 800c894: d001 beq.n 800c89a + 800c896: 2301 movs r3, #1 + 800c898: e000 b.n 800c89c + 800c89a: 2300 movs r3, #0 + 800c89c: 442b add r3, r5 + 800c89e: 4423 add r3, r4 + 800c8a0: 60bb str r3, [r7, #8] + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + 800c8a2: 687b ldr r3, [r7, #4] + 800c8a4: 6d1a ldr r2, [r3, #80] ; 0x50 + 800c8a6: 68bb ldr r3, [r7, #8] + 800c8a8: 1ad3 subs r3, r2, r3 + 800c8aa: 2b00 cmp r3, #0 + 800c8ac: da02 bge.n 800c8b4 + pcb->snd_nxt = snd_nxt; + 800c8ae: 687b ldr r3, [r7, #4] + 800c8b0: 68ba ldr r2, [r7, #8] + 800c8b2: 651a str r2, [r3, #80] ; 0x50 + } + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + 800c8b4: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c8b6: 891b ldrh r3, [r3, #8] + 800c8b8: 461c mov r4, r3 + 800c8ba: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c8bc: 691b ldr r3, [r3, #16] + 800c8be: 899b ldrh r3, [r3, #12] + 800c8c0: b29b uxth r3, r3 + 800c8c2: 4618 mov r0, r3 + 800c8c4: f7f8 fe42 bl 800554c + 800c8c8: 4603 mov r3, r0 + 800c8ca: b2db uxtb r3, r3 + 800c8cc: f003 0303 and.w r3, r3, #3 + 800c8d0: 2b00 cmp r3, #0 + 800c8d2: d001 beq.n 800c8d8 + 800c8d4: 2301 movs r3, #1 + 800c8d6: e000 b.n 800c8da + 800c8d8: 2300 movs r3, #0 + 800c8da: 4423 add r3, r4 + 800c8dc: 2b00 cmp r3, #0 + 800c8de: d049 beq.n 800c974 + seg->next = NULL; + 800c8e0: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c8e2: 2200 movs r2, #0 + 800c8e4: 601a str r2, [r3, #0] + /* unacked list is empty? */ + if (pcb->unacked == NULL) { + 800c8e6: 687b ldr r3, [r7, #4] + 800c8e8: 6f1b ldr r3, [r3, #112] ; 0x70 + 800c8ea: 2b00 cmp r3, #0 + 800c8ec: d105 bne.n 800c8fa + pcb->unacked = seg; + 800c8ee: 687b ldr r3, [r7, #4] + 800c8f0: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c8f2: 671a str r2, [r3, #112] ; 0x70 + useg = seg; + 800c8f4: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c8f6: 623b str r3, [r7, #32] + 800c8f8: e03f b.n 800c97a + /* unacked list is not empty? */ + } else { + /* In the case of fast retransmit, the packet should not go to the tail + * of the unacked queue, but rather somewhere before it. We need to check for + * this case. -STJ Jul 27, 2004 */ + if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) { + 800c8fa: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c8fc: 691b ldr r3, [r3, #16] + 800c8fe: 685b ldr r3, [r3, #4] + 800c900: 4618 mov r0, r3 + 800c902: f7f8 fe38 bl 8005576 + 800c906: 4604 mov r4, r0 + 800c908: 6a3b ldr r3, [r7, #32] + 800c90a: 691b ldr r3, [r3, #16] + 800c90c: 685b ldr r3, [r3, #4] + 800c90e: 4618 mov r0, r3 + 800c910: f7f8 fe31 bl 8005576 + 800c914: 4603 mov r3, r0 + 800c916: 1ae3 subs r3, r4, r3 + 800c918: 2b00 cmp r3, #0 + 800c91a: da24 bge.n 800c966 + /* add segment to before tail of unacked list, keeping the list sorted */ + struct tcp_seg **cur_seg = &(pcb->unacked); + 800c91c: 687b ldr r3, [r7, #4] + 800c91e: 3370 adds r3, #112 ; 0x70 + 800c920: 61fb str r3, [r7, #28] + while (*cur_seg && + 800c922: e002 b.n 800c92a + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + 800c924: 69fb ldr r3, [r7, #28] + 800c926: 681b ldr r3, [r3, #0] + 800c928: 61fb str r3, [r7, #28] + while (*cur_seg && + 800c92a: 69fb ldr r3, [r7, #28] + 800c92c: 681b ldr r3, [r3, #0] + 800c92e: 2b00 cmp r3, #0 + 800c930: d011 beq.n 800c956 + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + 800c932: 69fb ldr r3, [r7, #28] + 800c934: 681b ldr r3, [r3, #0] + 800c936: 691b ldr r3, [r3, #16] + 800c938: 685b ldr r3, [r3, #4] + 800c93a: 4618 mov r0, r3 + 800c93c: f7f8 fe1b bl 8005576 + 800c940: 4604 mov r4, r0 + 800c942: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c944: 691b ldr r3, [r3, #16] + 800c946: 685b ldr r3, [r3, #4] + 800c948: 4618 mov r0, r3 + 800c94a: f7f8 fe14 bl 8005576 + 800c94e: 4603 mov r3, r0 + 800c950: 1ae3 subs r3, r4, r3 + while (*cur_seg && + 800c952: 2b00 cmp r3, #0 + 800c954: dbe6 blt.n 800c924 + } + seg->next = (*cur_seg); + 800c956: 69fb ldr r3, [r7, #28] + 800c958: 681a ldr r2, [r3, #0] + 800c95a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c95c: 601a str r2, [r3, #0] + (*cur_seg) = seg; + 800c95e: 69fb ldr r3, [r7, #28] + 800c960: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c962: 601a str r2, [r3, #0] + 800c964: e009 b.n 800c97a + } else { + /* add segment to tail of unacked list */ + useg->next = seg; + 800c966: 6a3b ldr r3, [r7, #32] + 800c968: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c96a: 601a str r2, [r3, #0] + useg = useg->next; + 800c96c: 6a3b ldr r3, [r7, #32] + 800c96e: 681b ldr r3, [r3, #0] + 800c970: 623b str r3, [r7, #32] + 800c972: e002 b.n 800c97a + } + } + /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + 800c974: 6a78 ldr r0, [r7, #36] ; 0x24 + 800c976: f7fb fefe bl 8008776 + } + seg = pcb->unsent; + 800c97a: 687b ldr r3, [r7, #4] + 800c97c: 6edb ldr r3, [r3, #108] ; 0x6c + 800c97e: 627b str r3, [r7, #36] ; 0x24 + while (seg != NULL && + 800c980: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c982: 2b00 cmp r3, #0 + 800c984: d012 beq.n 800c9ac + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + 800c986: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c988: 691b ldr r3, [r3, #16] + 800c98a: 685b ldr r3, [r3, #4] + 800c98c: 4618 mov r0, r3 + 800c98e: f7f8 fdf2 bl 8005576 + 800c992: 4602 mov r2, r0 + 800c994: 687b ldr r3, [r7, #4] + 800c996: 6c5b ldr r3, [r3, #68] ; 0x44 + 800c998: 1ad3 subs r3, r2, r3 + 800c99a: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c99c: 8912 ldrh r2, [r2, #8] + 800c99e: 4413 add r3, r2 + while (seg != NULL && + 800c9a0: 69ba ldr r2, [r7, #24] + 800c9a2: 429a cmp r2, r3 + 800c9a4: f4bf aed6 bcs.w 800c754 + 800c9a8: e000 b.n 800c9ac + break; + 800c9aa: bf00 nop + } +#if TCP_OVERSIZE + if (pcb->unsent == NULL) { + 800c9ac: 687b ldr r3, [r7, #4] + 800c9ae: 6edb ldr r3, [r3, #108] ; 0x6c + 800c9b0: 2b00 cmp r3, #0 + 800c9b2: d108 bne.n 800c9c6 + /* last unsent has been removed, reset unsent_oversize */ + pcb->unsent_oversize = 0; + 800c9b4: 687b ldr r3, [r7, #4] + 800c9b6: 2200 movs r2, #0 + 800c9b8: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + 800c9bc: e004 b.n 800c9c8 + goto output_done; + 800c9be: bf00 nop + 800c9c0: e002 b.n 800c9c8 + goto output_done; + 800c9c2: bf00 nop + 800c9c4: e000 b.n 800c9c8 + } +#endif /* TCP_OVERSIZE */ + +output_done: + 800c9c6: bf00 nop + tcp_clear_flags(pcb, TF_NAGLEMEMERR); + 800c9c8: 687b ldr r3, [r7, #4] + 800c9ca: 8b5b ldrh r3, [r3, #26] + 800c9cc: f023 0380 bic.w r3, r3, #128 ; 0x80 + 800c9d0: b29a uxth r2, r3 + 800c9d2: 687b ldr r3, [r7, #4] + 800c9d4: 835a strh r2, [r3, #26] + return ERR_OK; + 800c9d6: 2300 movs r3, #0 +} + 800c9d8: 4618 mov r0, r3 + 800c9da: 3728 adds r7, #40 ; 0x28 + 800c9dc: 46bd mov sp, r7 + 800c9de: bdb0 pop {r4, r5, r7, pc} + +0800c9e0 : + * @arg seg the tcp segment to check + * @return 1 if ref != 1, 0 if ref == 1 + */ +static int +tcp_output_segment_busy(const struct tcp_seg *seg) +{ + 800c9e0: b580 push {r7, lr} + 800c9e2: b082 sub sp, #8 + 800c9e4: af00 add r7, sp, #0 + 800c9e6: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL); + 800c9e8: 687b ldr r3, [r7, #4] + 800c9ea: 2b00 cmp r3, #0 + 800c9ec: d106 bne.n 800c9fc + 800c9ee: 4b09 ldr r3, [pc, #36] ; (800ca14 ) + 800c9f0: f240 529a movw r2, #1434 ; 0x59a + 800c9f4: 4908 ldr r1, [pc, #32] ; (800ca18 ) + 800c9f6: 4809 ldr r0, [pc, #36] ; (800ca1c ) + 800c9f8: f004 f8e6 bl 8010bc8 + + /* We only need to check the first pbuf here: + If a pbuf is queued for transmission, a driver calls pbuf_ref(), + which only changes the ref count of the first pbuf */ + if (seg->p->ref != 1) { + 800c9fc: 687b ldr r3, [r7, #4] + 800c9fe: 685b ldr r3, [r3, #4] + 800ca00: 7b9b ldrb r3, [r3, #14] + 800ca02: 2b01 cmp r3, #1 + 800ca04: d001 beq.n 800ca0a + /* other reference found */ + return 1; + 800ca06: 2301 movs r3, #1 + 800ca08: e000 b.n 800ca0c + } + /* no other references found */ + return 0; + 800ca0a: 2300 movs r3, #0 +} + 800ca0c: 4618 mov r0, r3 + 800ca0e: 3708 adds r7, #8 + 800ca10: 46bd mov sp, r7 + 800ca12: bd80 pop {r7, pc} + 800ca14: 08013618 .word 0x08013618 + 800ca18: 08013c10 .word 0x08013c10 + 800ca1c: 0801366c .word 0x0801366c + +0800ca20 : + * @param pcb the tcp_pcb for the TCP connection used to send the segment + * @param netif the netif used to send the segment + */ +static err_t +tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif) +{ + 800ca20: b5b0 push {r4, r5, r7, lr} + 800ca22: b08c sub sp, #48 ; 0x30 + 800ca24: af04 add r7, sp, #16 + 800ca26: 60f8 str r0, [r7, #12] + 800ca28: 60b9 str r1, [r7, #8] + 800ca2a: 607a str r2, [r7, #4] + u32_t *opts; +#if TCP_CHECKSUM_ON_COPY + int seg_chksum_was_swapped = 0; +#endif + + LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL); + 800ca2c: 68fb ldr r3, [r7, #12] + 800ca2e: 2b00 cmp r3, #0 + 800ca30: d106 bne.n 800ca40 + 800ca32: 4b64 ldr r3, [pc, #400] ; (800cbc4 ) + 800ca34: f44f 62b7 mov.w r2, #1464 ; 0x5b8 + 800ca38: 4963 ldr r1, [pc, #396] ; (800cbc8 ) + 800ca3a: 4864 ldr r0, [pc, #400] ; (800cbcc ) + 800ca3c: f004 f8c4 bl 8010bc8 + LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL); + 800ca40: 68bb ldr r3, [r7, #8] + 800ca42: 2b00 cmp r3, #0 + 800ca44: d106 bne.n 800ca54 + 800ca46: 4b5f ldr r3, [pc, #380] ; (800cbc4 ) + 800ca48: f240 52b9 movw r2, #1465 ; 0x5b9 + 800ca4c: 4960 ldr r1, [pc, #384] ; (800cbd0 ) + 800ca4e: 485f ldr r0, [pc, #380] ; (800cbcc ) + 800ca50: f004 f8ba bl 8010bc8 + LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL); + 800ca54: 687b ldr r3, [r7, #4] + 800ca56: 2b00 cmp r3, #0 + 800ca58: d106 bne.n 800ca68 + 800ca5a: 4b5a ldr r3, [pc, #360] ; (800cbc4 ) + 800ca5c: f240 52ba movw r2, #1466 ; 0x5ba + 800ca60: 495c ldr r1, [pc, #368] ; (800cbd4 ) + 800ca62: 485a ldr r0, [pc, #360] ; (800cbcc ) + 800ca64: f004 f8b0 bl 8010bc8 + + if (tcp_output_segment_busy(seg)) { + 800ca68: 68f8 ldr r0, [r7, #12] + 800ca6a: f7ff ffb9 bl 800c9e0 + 800ca6e: 4603 mov r3, r0 + 800ca70: 2b00 cmp r3, #0 + 800ca72: d001 beq.n 800ca78 + /* This should not happen: rexmit functions should have checked this. + However, since this function modifies p->len, we must not continue in this case. */ + LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n")); + return ERR_OK; + 800ca74: 2300 movs r3, #0 + 800ca76: e0a1 b.n 800cbbc + } + + /* The TCP header has already been constructed, but the ackno and + wnd fields remain. */ + seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt); + 800ca78: 68bb ldr r3, [r7, #8] + 800ca7a: 6a5a ldr r2, [r3, #36] ; 0x24 + 800ca7c: 68fb ldr r3, [r7, #12] + 800ca7e: 691c ldr r4, [r3, #16] + 800ca80: 4610 mov r0, r2 + 800ca82: f7f8 fd78 bl 8005576 + 800ca86: 4603 mov r3, r0 + 800ca88: 60a3 str r3, [r4, #8] + the window scale option) is never scaled. */ + seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd)); + } else +#endif /* LWIP_WND_SCALE */ + { + seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); + 800ca8a: 68bb ldr r3, [r7, #8] + 800ca8c: 8d5a ldrh r2, [r3, #42] ; 0x2a + 800ca8e: 68fb ldr r3, [r7, #12] + 800ca90: 691c ldr r4, [r3, #16] + 800ca92: 4610 mov r0, r2 + 800ca94: f7f8 fd5a bl 800554c + 800ca98: 4603 mov r3, r0 + 800ca9a: 81e3 strh r3, [r4, #14] + } + + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + 800ca9c: 68bb ldr r3, [r7, #8] + 800ca9e: 6a5b ldr r3, [r3, #36] ; 0x24 + 800caa0: 68ba ldr r2, [r7, #8] + 800caa2: 8d52 ldrh r2, [r2, #42] ; 0x2a + 800caa4: 441a add r2, r3 + 800caa6: 68bb ldr r3, [r7, #8] + 800caa8: 62da str r2, [r3, #44] ; 0x2c + + /* Add any requested options. NB MSS option is only set on SYN + packets, so ignore it here */ + /* cast through void* to get rid of alignment warnings */ + opts = (u32_t *)(void *)(seg->tcphdr + 1); + 800caaa: 68fb ldr r3, [r7, #12] + 800caac: 691b ldr r3, [r3, #16] + 800caae: 3314 adds r3, #20 + 800cab0: 61fb str r3, [r7, #28] + if (seg->flags & TF_SEG_OPTS_MSS) { + 800cab2: 68fb ldr r3, [r7, #12] + 800cab4: 7b1b ldrb r3, [r3, #12] + 800cab6: f003 0301 and.w r3, r3, #1 + 800caba: 2b00 cmp r3, #0 + 800cabc: d015 beq.n 800caea + u16_t mss; +#if TCP_CALCULATE_EFF_SEND_MSS + mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip); + 800cabe: 68bb ldr r3, [r7, #8] + 800cac0: 3304 adds r3, #4 + 800cac2: 461a mov r2, r3 + 800cac4: 6879 ldr r1, [r7, #4] + 800cac6: f44f 7006 mov.w r0, #536 ; 0x218 + 800caca: f7fc f9cb bl 8008e64 + 800cace: 4603 mov r3, r0 + 800cad0: 837b strh r3, [r7, #26] +#else /* TCP_CALCULATE_EFF_SEND_MSS */ + mss = TCP_MSS; +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + *opts = TCP_BUILD_MSS_OPTION(mss); + 800cad2: 8b7b ldrh r3, [r7, #26] + 800cad4: f043 7301 orr.w r3, r3, #33816576 ; 0x2040000 + 800cad8: 4618 mov r0, r3 + 800cada: f7f8 fd4c bl 8005576 + 800cade: 4602 mov r2, r0 + 800cae0: 69fb ldr r3, [r7, #28] + 800cae2: 601a str r2, [r3, #0] + opts += 1; + 800cae4: 69fb ldr r3, [r7, #28] + 800cae6: 3304 adds r3, #4 + 800cae8: 61fb str r3, [r7, #28] + } +#endif + + /* Set retransmission timer running if it is not currently enabled + This must be set before checking the route. */ + if (pcb->rtime < 0) { + 800caea: 68bb ldr r3, [r7, #8] + 800caec: f9b3 3030 ldrsh.w r3, [r3, #48] ; 0x30 + 800caf0: 2b00 cmp r3, #0 + 800caf2: da02 bge.n 800cafa + pcb->rtime = 0; + 800caf4: 68bb ldr r3, [r7, #8] + 800caf6: 2200 movs r2, #0 + 800caf8: 861a strh r2, [r3, #48] ; 0x30 + } + + if (pcb->rttest == 0) { + 800cafa: 68bb ldr r3, [r7, #8] + 800cafc: 6b5b ldr r3, [r3, #52] ; 0x34 + 800cafe: 2b00 cmp r3, #0 + 800cb00: d10c bne.n 800cb1c + pcb->rttest = tcp_ticks; + 800cb02: 4b35 ldr r3, [pc, #212] ; (800cbd8 ) + 800cb04: 681a ldr r2, [r3, #0] + 800cb06: 68bb ldr r3, [r7, #8] + 800cb08: 635a str r2, [r3, #52] ; 0x34 + pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno); + 800cb0a: 68fb ldr r3, [r7, #12] + 800cb0c: 691b ldr r3, [r3, #16] + 800cb0e: 685b ldr r3, [r3, #4] + 800cb10: 4618 mov r0, r3 + 800cb12: f7f8 fd30 bl 8005576 + 800cb16: 4602 mov r2, r0 + 800cb18: 68bb ldr r3, [r7, #8] + 800cb1a: 639a str r2, [r3, #56] ; 0x38 + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", + lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) + + seg->len)); + + len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); + 800cb1c: 68fb ldr r3, [r7, #12] + 800cb1e: 691a ldr r2, [r3, #16] + 800cb20: 68fb ldr r3, [r7, #12] + 800cb22: 685b ldr r3, [r3, #4] + 800cb24: 685b ldr r3, [r3, #4] + 800cb26: 1ad3 subs r3, r2, r3 + 800cb28: 833b strh r3, [r7, #24] + if (len == 0) { + /** Exclude retransmitted segments from this count. */ + MIB2_STATS_INC(mib2.tcpoutsegs); + } + + seg->p->len -= len; + 800cb2a: 68fb ldr r3, [r7, #12] + 800cb2c: 685b ldr r3, [r3, #4] + 800cb2e: 8959 ldrh r1, [r3, #10] + 800cb30: 68fb ldr r3, [r7, #12] + 800cb32: 685b ldr r3, [r3, #4] + 800cb34: 8b3a ldrh r2, [r7, #24] + 800cb36: 1a8a subs r2, r1, r2 + 800cb38: b292 uxth r2, r2 + 800cb3a: 815a strh r2, [r3, #10] + seg->p->tot_len -= len; + 800cb3c: 68fb ldr r3, [r7, #12] + 800cb3e: 685b ldr r3, [r3, #4] + 800cb40: 8919 ldrh r1, [r3, #8] + 800cb42: 68fb ldr r3, [r7, #12] + 800cb44: 685b ldr r3, [r3, #4] + 800cb46: 8b3a ldrh r2, [r7, #24] + 800cb48: 1a8a subs r2, r1, r2 + 800cb4a: b292 uxth r2, r2 + 800cb4c: 811a strh r2, [r3, #8] + + seg->p->payload = seg->tcphdr; + 800cb4e: 68fb ldr r3, [r7, #12] + 800cb50: 685b ldr r3, [r3, #4] + 800cb52: 68fa ldr r2, [r7, #12] + 800cb54: 6912 ldr r2, [r2, #16] + 800cb56: 605a str r2, [r3, #4] + + seg->tcphdr->chksum = 0; + 800cb58: 68fb ldr r3, [r7, #12] + 800cb5a: 691b ldr r3, [r3, #16] + 800cb5c: 2200 movs r2, #0 + 800cb5e: 741a strb r2, [r3, #16] + 800cb60: 2200 movs r2, #0 + 800cb62: 745a strb r2, [r3, #17] + +#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS + opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts); +#endif + LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb)); + 800cb64: 68fb ldr r3, [r7, #12] + 800cb66: 691a ldr r2, [r3, #16] + 800cb68: 68fb ldr r3, [r7, #12] + 800cb6a: 7b1b ldrb r3, [r3, #12] + 800cb6c: f003 0301 and.w r3, r3, #1 + 800cb70: 2b00 cmp r3, #0 + 800cb72: d001 beq.n 800cb78 + 800cb74: 2318 movs r3, #24 + 800cb76: e000 b.n 800cb7a + 800cb78: 2314 movs r3, #20 + 800cb7a: 4413 add r3, r2 + 800cb7c: 69fa ldr r2, [r7, #28] + 800cb7e: 429a cmp r2, r3 + 800cb80: d006 beq.n 800cb90 + 800cb82: 4b10 ldr r3, [pc, #64] ; (800cbc4 ) + 800cb84: f240 621c movw r2, #1564 ; 0x61c + 800cb88: 4914 ldr r1, [pc, #80] ; (800cbdc ) + 800cb8a: 4810 ldr r0, [pc, #64] ; (800cbcc ) + 800cb8c: f004 f81c bl 8010bc8 + } +#endif /* CHECKSUM_GEN_TCP */ + TCP_STATS_INC(tcp.xmit); + + NETIF_SET_HINTS(netif, &(pcb->netif_hints)); + err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, + 800cb90: 68fb ldr r3, [r7, #12] + 800cb92: 6858 ldr r0, [r3, #4] + 800cb94: 68b9 ldr r1, [r7, #8] + 800cb96: 68bb ldr r3, [r7, #8] + 800cb98: 1d1c adds r4, r3, #4 + 800cb9a: 68bb ldr r3, [r7, #8] + 800cb9c: 7add ldrb r5, [r3, #11] + 800cb9e: 68bb ldr r3, [r7, #8] + 800cba0: 7a9b ldrb r3, [r3, #10] + 800cba2: 687a ldr r2, [r7, #4] + 800cba4: 9202 str r2, [sp, #8] + 800cba6: 2206 movs r2, #6 + 800cba8: 9201 str r2, [sp, #4] + 800cbaa: 9300 str r3, [sp, #0] + 800cbac: 462b mov r3, r5 + 800cbae: 4622 mov r2, r4 + 800cbb0: f002 fb28 bl 800f204 + 800cbb4: 4603 mov r3, r0 + 800cbb6: 75fb strb r3, [r7, #23] + seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum); + seg->chksum_swapped = 1; + } +#endif + + return err; + 800cbb8: f997 3017 ldrsb.w r3, [r7, #23] +} + 800cbbc: 4618 mov r0, r3 + 800cbbe: 3720 adds r7, #32 + 800cbc0: 46bd mov sp, r7 + 800cbc2: bdb0 pop {r4, r5, r7, pc} + 800cbc4: 08013618 .word 0x08013618 + 800cbc8: 08013c38 .word 0x08013c38 + 800cbcc: 0801366c .word 0x0801366c + 800cbd0: 08013c58 .word 0x08013c58 + 800cbd4: 08013c78 .word 0x08013c78 + 800cbd8: 24007b6c .word 0x24007b6c + 800cbdc: 08013c9c .word 0x08013c9c + +0800cbe0 : + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +err_t +tcp_rexmit_rto_prepare(struct tcp_pcb *pcb) +{ + 800cbe0: b5b0 push {r4, r5, r7, lr} + 800cbe2: b084 sub sp, #16 + 800cbe4: af00 add r7, sp, #0 + 800cbe6: 6078 str r0, [r7, #4] + struct tcp_seg *seg; + + LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL); + 800cbe8: 687b ldr r3, [r7, #4] + 800cbea: 2b00 cmp r3, #0 + 800cbec: d106 bne.n 800cbfc + 800cbee: 4b36 ldr r3, [pc, #216] ; (800ccc8 ) + 800cbf0: f240 6263 movw r2, #1635 ; 0x663 + 800cbf4: 4935 ldr r1, [pc, #212] ; (800cccc ) + 800cbf6: 4836 ldr r0, [pc, #216] ; (800ccd0 ) + 800cbf8: f003 ffe6 bl 8010bc8 + + if (pcb->unacked == NULL) { + 800cbfc: 687b ldr r3, [r7, #4] + 800cbfe: 6f1b ldr r3, [r3, #112] ; 0x70 + 800cc00: 2b00 cmp r3, #0 + 800cc02: d102 bne.n 800cc0a + return ERR_VAL; + 800cc04: f06f 0305 mvn.w r3, #5 + 800cc08: e059 b.n 800ccbe + + /* Move all unacked segments to the head of the unsent queue. + However, give up if any of the unsent pbufs are still referenced by the + netif driver due to deferred transmission. No point loading the link further + if it is struggling to flush its buffered writes. */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { + 800cc0a: 687b ldr r3, [r7, #4] + 800cc0c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800cc0e: 60fb str r3, [r7, #12] + 800cc10: e00b b.n 800cc2a + if (tcp_output_segment_busy(seg)) { + 800cc12: 68f8 ldr r0, [r7, #12] + 800cc14: f7ff fee4 bl 800c9e0 + 800cc18: 4603 mov r3, r0 + 800cc1a: 2b00 cmp r3, #0 + 800cc1c: d002 beq.n 800cc24 + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); + return ERR_VAL; + 800cc1e: f06f 0305 mvn.w r3, #5 + 800cc22: e04c b.n 800ccbe + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { + 800cc24: 68fb ldr r3, [r7, #12] + 800cc26: 681b ldr r3, [r3, #0] + 800cc28: 60fb str r3, [r7, #12] + 800cc2a: 68fb ldr r3, [r7, #12] + 800cc2c: 681b ldr r3, [r3, #0] + 800cc2e: 2b00 cmp r3, #0 + 800cc30: d1ef bne.n 800cc12 + } + } + if (tcp_output_segment_busy(seg)) { + 800cc32: 68f8 ldr r0, [r7, #12] + 800cc34: f7ff fed4 bl 800c9e0 + 800cc38: 4603 mov r3, r0 + 800cc3a: 2b00 cmp r3, #0 + 800cc3c: d002 beq.n 800cc44 + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); + return ERR_VAL; + 800cc3e: f06f 0305 mvn.w r3, #5 + 800cc42: e03c b.n 800ccbe + } + /* concatenate unsent queue after unacked queue */ + seg->next = pcb->unsent; + 800cc44: 687b ldr r3, [r7, #4] + 800cc46: 6eda ldr r2, [r3, #108] ; 0x6c + 800cc48: 68fb ldr r3, [r7, #12] + 800cc4a: 601a str r2, [r3, #0] +#if TCP_OVERSIZE_DBGCHECK + /* if last unsent changed, we need to update unsent_oversize */ + if (pcb->unsent == NULL) { + 800cc4c: 687b ldr r3, [r7, #4] + 800cc4e: 6edb ldr r3, [r3, #108] ; 0x6c + 800cc50: 2b00 cmp r3, #0 + 800cc52: d104 bne.n 800cc5e + pcb->unsent_oversize = seg->oversize_left; + 800cc54: 68fb ldr r3, [r7, #12] + 800cc56: 895a ldrh r2, [r3, #10] + 800cc58: 687b ldr r3, [r7, #4] + 800cc5a: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + } +#endif /* TCP_OVERSIZE_DBGCHECK */ + /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; + 800cc5e: 687b ldr r3, [r7, #4] + 800cc60: 6f1a ldr r2, [r3, #112] ; 0x70 + 800cc62: 687b ldr r3, [r7, #4] + 800cc64: 66da str r2, [r3, #108] ; 0x6c + /* unacked queue is now empty */ + pcb->unacked = NULL; + 800cc66: 687b ldr r3, [r7, #4] + 800cc68: 2200 movs r2, #0 + 800cc6a: 671a str r2, [r3, #112] ; 0x70 + + /* Mark RTO in-progress */ + tcp_set_flags(pcb, TF_RTO); + 800cc6c: 687b ldr r3, [r7, #4] + 800cc6e: 8b5b ldrh r3, [r3, #26] + 800cc70: f443 6300 orr.w r3, r3, #2048 ; 0x800 + 800cc74: b29a uxth r2, r3 + 800cc76: 687b ldr r3, [r7, #4] + 800cc78: 835a strh r2, [r3, #26] + /* Record the next byte following retransmit */ + pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + 800cc7a: 68fb ldr r3, [r7, #12] + 800cc7c: 691b ldr r3, [r3, #16] + 800cc7e: 685b ldr r3, [r3, #4] + 800cc80: 4618 mov r0, r3 + 800cc82: f7f8 fc78 bl 8005576 + 800cc86: 4604 mov r4, r0 + 800cc88: 68fb ldr r3, [r7, #12] + 800cc8a: 891b ldrh r3, [r3, #8] + 800cc8c: 461d mov r5, r3 + 800cc8e: 68fb ldr r3, [r7, #12] + 800cc90: 691b ldr r3, [r3, #16] + 800cc92: 899b ldrh r3, [r3, #12] + 800cc94: b29b uxth r3, r3 + 800cc96: 4618 mov r0, r3 + 800cc98: f7f8 fc58 bl 800554c + 800cc9c: 4603 mov r3, r0 + 800cc9e: b2db uxtb r3, r3 + 800cca0: f003 0303 and.w r3, r3, #3 + 800cca4: 2b00 cmp r3, #0 + 800cca6: d001 beq.n 800ccac + 800cca8: 2301 movs r3, #1 + 800ccaa: e000 b.n 800ccae + 800ccac: 2300 movs r3, #0 + 800ccae: 442b add r3, r5 + 800ccb0: 18e2 adds r2, r4, r3 + 800ccb2: 687b ldr r3, [r7, #4] + 800ccb4: 64da str r2, [r3, #76] ; 0x4c + /* Don't take any RTT measurements after retransmitting. */ + pcb->rttest = 0; + 800ccb6: 687b ldr r3, [r7, #4] + 800ccb8: 2200 movs r2, #0 + 800ccba: 635a str r2, [r3, #52] ; 0x34 + + return ERR_OK; + 800ccbc: 2300 movs r3, #0 +} + 800ccbe: 4618 mov r0, r3 + 800ccc0: 3710 adds r7, #16 + 800ccc2: 46bd mov sp, r7 + 800ccc4: bdb0 pop {r4, r5, r7, pc} + 800ccc6: bf00 nop + 800ccc8: 08013618 .word 0x08013618 + 800cccc: 08013cb0 .word 0x08013cb0 + 800ccd0: 0801366c .word 0x0801366c + +0800ccd4 : + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto_commit(struct tcp_pcb *pcb) +{ + 800ccd4: b580 push {r7, lr} + 800ccd6: b082 sub sp, #8 + 800ccd8: af00 add r7, sp, #0 + 800ccda: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL); + 800ccdc: 687b ldr r3, [r7, #4] + 800ccde: 2b00 cmp r3, #0 + 800cce0: d106 bne.n 800ccf0 + 800cce2: 4b0d ldr r3, [pc, #52] ; (800cd18 ) + 800cce4: f44f 62d3 mov.w r2, #1688 ; 0x698 + 800cce8: 490c ldr r1, [pc, #48] ; (800cd1c ) + 800ccea: 480d ldr r0, [pc, #52] ; (800cd20 ) + 800ccec: f003 ff6c bl 8010bc8 + + /* increment number of retransmissions */ + if (pcb->nrtx < 0xFF) { + 800ccf0: 687b ldr r3, [r7, #4] + 800ccf2: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 800ccf6: 2bff cmp r3, #255 ; 0xff + 800ccf8: d007 beq.n 800cd0a + ++pcb->nrtx; + 800ccfa: 687b ldr r3, [r7, #4] + 800ccfc: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 800cd00: 3301 adds r3, #1 + 800cd02: b2da uxtb r2, r3 + 800cd04: 687b ldr r3, [r7, #4] + 800cd06: f883 2042 strb.w r2, [r3, #66] ; 0x42 + } + /* Do the actual retransmission */ + tcp_output(pcb); + 800cd0a: 6878 ldr r0, [r7, #4] + 800cd0c: f7ff fc72 bl 800c5f4 +} + 800cd10: bf00 nop + 800cd12: 3708 adds r7, #8 + 800cd14: 46bd mov sp, r7 + 800cd16: bd80 pop {r7, pc} + 800cd18: 08013618 .word 0x08013618 + 800cd1c: 08013cd4 .word 0x08013cd4 + 800cd20: 0801366c .word 0x0801366c + +0800cd24 : + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto(struct tcp_pcb *pcb) +{ + 800cd24: b580 push {r7, lr} + 800cd26: b082 sub sp, #8 + 800cd28: af00 add r7, sp, #0 + 800cd2a: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL); + 800cd2c: 687b ldr r3, [r7, #4] + 800cd2e: 2b00 cmp r3, #0 + 800cd30: d106 bne.n 800cd40 + 800cd32: 4b0a ldr r3, [pc, #40] ; (800cd5c ) + 800cd34: f240 62ad movw r2, #1709 ; 0x6ad + 800cd38: 4909 ldr r1, [pc, #36] ; (800cd60 ) + 800cd3a: 480a ldr r0, [pc, #40] ; (800cd64 ) + 800cd3c: f003 ff44 bl 8010bc8 + + if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) { + 800cd40: 6878 ldr r0, [r7, #4] + 800cd42: f7ff ff4d bl 800cbe0 + 800cd46: 4603 mov r3, r0 + 800cd48: 2b00 cmp r3, #0 + 800cd4a: d102 bne.n 800cd52 + tcp_rexmit_rto_commit(pcb); + 800cd4c: 6878 ldr r0, [r7, #4] + 800cd4e: f7ff ffc1 bl 800ccd4 + } +} + 800cd52: bf00 nop + 800cd54: 3708 adds r7, #8 + 800cd56: 46bd mov sp, r7 + 800cd58: bd80 pop {r7, pc} + 800cd5a: bf00 nop + 800cd5c: 08013618 .word 0x08013618 + 800cd60: 08013cf8 .word 0x08013cf8 + 800cd64: 0801366c .word 0x0801366c + +0800cd68 : + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +err_t +tcp_rexmit(struct tcp_pcb *pcb) +{ + 800cd68: b590 push {r4, r7, lr} + 800cd6a: b085 sub sp, #20 + 800cd6c: af00 add r7, sp, #0 + 800cd6e: 6078 str r0, [r7, #4] + struct tcp_seg *seg; + struct tcp_seg **cur_seg; + + LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL); + 800cd70: 687b ldr r3, [r7, #4] + 800cd72: 2b00 cmp r3, #0 + 800cd74: d106 bne.n 800cd84 + 800cd76: 4b2f ldr r3, [pc, #188] ; (800ce34 ) + 800cd78: f240 62c1 movw r2, #1729 ; 0x6c1 + 800cd7c: 492e ldr r1, [pc, #184] ; (800ce38 ) + 800cd7e: 482f ldr r0, [pc, #188] ; (800ce3c ) + 800cd80: f003 ff22 bl 8010bc8 + + if (pcb->unacked == NULL) { + 800cd84: 687b ldr r3, [r7, #4] + 800cd86: 6f1b ldr r3, [r3, #112] ; 0x70 + 800cd88: 2b00 cmp r3, #0 + 800cd8a: d102 bne.n 800cd92 + return ERR_VAL; + 800cd8c: f06f 0305 mvn.w r3, #5 + 800cd90: e04c b.n 800ce2c + } + + seg = pcb->unacked; + 800cd92: 687b ldr r3, [r7, #4] + 800cd94: 6f1b ldr r3, [r3, #112] ; 0x70 + 800cd96: 60bb str r3, [r7, #8] + + /* Give up if the segment is still referenced by the netif driver + due to deferred transmission. */ + if (tcp_output_segment_busy(seg)) { + 800cd98: 68b8 ldr r0, [r7, #8] + 800cd9a: f7ff fe21 bl 800c9e0 + 800cd9e: 4603 mov r3, r0 + 800cda0: 2b00 cmp r3, #0 + 800cda2: d002 beq.n 800cdaa + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n")); + return ERR_VAL; + 800cda4: f06f 0305 mvn.w r3, #5 + 800cda8: e040 b.n 800ce2c + } + + /* Move the first unacked segment to the unsent queue */ + /* Keep the unsent queue sorted. */ + pcb->unacked = seg->next; + 800cdaa: 68bb ldr r3, [r7, #8] + 800cdac: 681a ldr r2, [r3, #0] + 800cdae: 687b ldr r3, [r7, #4] + 800cdb0: 671a str r2, [r3, #112] ; 0x70 + + cur_seg = &(pcb->unsent); + 800cdb2: 687b ldr r3, [r7, #4] + 800cdb4: 336c adds r3, #108 ; 0x6c + 800cdb6: 60fb str r3, [r7, #12] + while (*cur_seg && + 800cdb8: e002 b.n 800cdc0 + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + 800cdba: 68fb ldr r3, [r7, #12] + 800cdbc: 681b ldr r3, [r3, #0] + 800cdbe: 60fb str r3, [r7, #12] + while (*cur_seg && + 800cdc0: 68fb ldr r3, [r7, #12] + 800cdc2: 681b ldr r3, [r3, #0] + 800cdc4: 2b00 cmp r3, #0 + 800cdc6: d011 beq.n 800cdec + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + 800cdc8: 68fb ldr r3, [r7, #12] + 800cdca: 681b ldr r3, [r3, #0] + 800cdcc: 691b ldr r3, [r3, #16] + 800cdce: 685b ldr r3, [r3, #4] + 800cdd0: 4618 mov r0, r3 + 800cdd2: f7f8 fbd0 bl 8005576 + 800cdd6: 4604 mov r4, r0 + 800cdd8: 68bb ldr r3, [r7, #8] + 800cdda: 691b ldr r3, [r3, #16] + 800cddc: 685b ldr r3, [r3, #4] + 800cdde: 4618 mov r0, r3 + 800cde0: f7f8 fbc9 bl 8005576 + 800cde4: 4603 mov r3, r0 + 800cde6: 1ae3 subs r3, r4, r3 + while (*cur_seg && + 800cde8: 2b00 cmp r3, #0 + 800cdea: dbe6 blt.n 800cdba + } + seg->next = *cur_seg; + 800cdec: 68fb ldr r3, [r7, #12] + 800cdee: 681a ldr r2, [r3, #0] + 800cdf0: 68bb ldr r3, [r7, #8] + 800cdf2: 601a str r2, [r3, #0] + *cur_seg = seg; + 800cdf4: 68fb ldr r3, [r7, #12] + 800cdf6: 68ba ldr r2, [r7, #8] + 800cdf8: 601a str r2, [r3, #0] +#if TCP_OVERSIZE + if (seg->next == NULL) { + 800cdfa: 68bb ldr r3, [r7, #8] + 800cdfc: 681b ldr r3, [r3, #0] + 800cdfe: 2b00 cmp r3, #0 + 800ce00: d103 bne.n 800ce0a + /* the retransmitted segment is last in unsent, so reset unsent_oversize */ + pcb->unsent_oversize = 0; + 800ce02: 687b ldr r3, [r7, #4] + 800ce04: 2200 movs r2, #0 + 800ce06: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + } +#endif /* TCP_OVERSIZE */ + + if (pcb->nrtx < 0xFF) { + 800ce0a: 687b ldr r3, [r7, #4] + 800ce0c: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 800ce10: 2bff cmp r3, #255 ; 0xff + 800ce12: d007 beq.n 800ce24 + ++pcb->nrtx; + 800ce14: 687b ldr r3, [r7, #4] + 800ce16: f893 3042 ldrb.w r3, [r3, #66] ; 0x42 + 800ce1a: 3301 adds r3, #1 + 800ce1c: b2da uxtb r2, r3 + 800ce1e: 687b ldr r3, [r7, #4] + 800ce20: f883 2042 strb.w r2, [r3, #66] ; 0x42 + } + + /* Don't take any rtt measurements after retransmitting. */ + pcb->rttest = 0; + 800ce24: 687b ldr r3, [r7, #4] + 800ce26: 2200 movs r2, #0 + 800ce28: 635a str r2, [r3, #52] ; 0x34 + + /* Do the actual retransmission. */ + MIB2_STATS_INC(mib2.tcpretranssegs); + /* No need to call tcp_output: we are always called from tcp_input() + and thus tcp_output directly returns. */ + return ERR_OK; + 800ce2a: 2300 movs r3, #0 +} + 800ce2c: 4618 mov r0, r3 + 800ce2e: 3714 adds r7, #20 + 800ce30: 46bd mov sp, r7 + 800ce32: bd90 pop {r4, r7, pc} + 800ce34: 08013618 .word 0x08013618 + 800ce38: 08013d14 .word 0x08013d14 + 800ce3c: 0801366c .word 0x0801366c + +0800ce40 : + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +void +tcp_rexmit_fast(struct tcp_pcb *pcb) +{ + 800ce40: b580 push {r7, lr} + 800ce42: b082 sub sp, #8 + 800ce44: af00 add r7, sp, #0 + 800ce46: 6078 str r0, [r7, #4] + LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL); + 800ce48: 687b ldr r3, [r7, #4] + 800ce4a: 2b00 cmp r3, #0 + 800ce4c: d106 bne.n 800ce5c + 800ce4e: 4b2a ldr r3, [pc, #168] ; (800cef8 ) + 800ce50: f240 62f9 movw r2, #1785 ; 0x6f9 + 800ce54: 4929 ldr r1, [pc, #164] ; (800cefc ) + 800ce56: 482a ldr r0, [pc, #168] ; (800cf00 ) + 800ce58: f003 feb6 bl 8010bc8 + + if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { + 800ce5c: 687b ldr r3, [r7, #4] + 800ce5e: 6f1b ldr r3, [r3, #112] ; 0x70 + 800ce60: 2b00 cmp r3, #0 + 800ce62: d045 beq.n 800cef0 + 800ce64: 687b ldr r3, [r7, #4] + 800ce66: 8b5b ldrh r3, [r3, #26] + 800ce68: f003 0304 and.w r3, r3, #4 + 800ce6c: 2b00 cmp r3, #0 + 800ce6e: d13f bne.n 800cef0 + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: dupacks %"U16_F" (%"U32_F + "), fast retransmit %"U32_F"\n", + (u16_t)pcb->dupacks, pcb->lastack, + lwip_ntohl(pcb->unacked->tcphdr->seqno))); + if (tcp_rexmit(pcb) == ERR_OK) { + 800ce70: 6878 ldr r0, [r7, #4] + 800ce72: f7ff ff79 bl 800cd68 + 800ce76: 4603 mov r3, r0 + 800ce78: 2b00 cmp r3, #0 + 800ce7a: d139 bne.n 800cef0 + /* Set ssthresh to half of the minimum of the current + * cwnd and the advertised window */ + pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2; + 800ce7c: 687b ldr r3, [r7, #4] + 800ce7e: f8b3 2060 ldrh.w r2, [r3, #96] ; 0x60 + 800ce82: 687b ldr r3, [r7, #4] + 800ce84: f8b3 3048 ldrh.w r3, [r3, #72] ; 0x48 + 800ce88: 4293 cmp r3, r2 + 800ce8a: bf28 it cs + 800ce8c: 4613 movcs r3, r2 + 800ce8e: b29b uxth r3, r3 + 800ce90: 2b00 cmp r3, #0 + 800ce92: da00 bge.n 800ce96 + 800ce94: 3301 adds r3, #1 + 800ce96: 105b asrs r3, r3, #1 + 800ce98: b29a uxth r2, r3 + 800ce9a: 687b ldr r3, [r7, #4] + 800ce9c: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + + /* The minimum value for ssthresh should be 2 MSS */ + if (pcb->ssthresh < (2U * pcb->mss)) { + 800cea0: 687b ldr r3, [r7, #4] + 800cea2: f8b3 304a ldrh.w r3, [r3, #74] ; 0x4a + 800cea6: 461a mov r2, r3 + 800cea8: 687b ldr r3, [r7, #4] + 800ceaa: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800ceac: 005b lsls r3, r3, #1 + 800ceae: 429a cmp r2, r3 + 800ceb0: d206 bcs.n 800cec0 + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F + " should be min 2 mss %"U16_F"...\n", + pcb->ssthresh, (u16_t)(2 * pcb->mss))); + pcb->ssthresh = 2 * pcb->mss; + 800ceb2: 687b ldr r3, [r7, #4] + 800ceb4: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800ceb6: 005b lsls r3, r3, #1 + 800ceb8: b29a uxth r2, r3 + 800ceba: 687b ldr r3, [r7, #4] + 800cebc: f8a3 204a strh.w r2, [r3, #74] ; 0x4a + } + + pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; + 800cec0: 687b ldr r3, [r7, #4] + 800cec2: f8b3 204a ldrh.w r2, [r3, #74] ; 0x4a + 800cec6: 687b ldr r3, [r7, #4] + 800cec8: 8e5b ldrh r3, [r3, #50] ; 0x32 + 800ceca: 4619 mov r1, r3 + 800cecc: 0049 lsls r1, r1, #1 + 800cece: 440b add r3, r1 + 800ced0: b29b uxth r3, r3 + 800ced2: 4413 add r3, r2 + 800ced4: b29a uxth r2, r3 + 800ced6: 687b ldr r3, [r7, #4] + 800ced8: f8a3 2048 strh.w r2, [r3, #72] ; 0x48 + tcp_set_flags(pcb, TF_INFR); + 800cedc: 687b ldr r3, [r7, #4] + 800cede: 8b5b ldrh r3, [r3, #26] + 800cee0: f043 0304 orr.w r3, r3, #4 + 800cee4: b29a uxth r2, r3 + 800cee6: 687b ldr r3, [r7, #4] + 800cee8: 835a strh r2, [r3, #26] + + /* Reset the retransmission timer to prevent immediate rto retransmissions */ + pcb->rtime = 0; + 800ceea: 687b ldr r3, [r7, #4] + 800ceec: 2200 movs r2, #0 + 800ceee: 861a strh r2, [r3, #48] ; 0x30 + } + } +} + 800cef0: bf00 nop + 800cef2: 3708 adds r7, #8 + 800cef4: 46bd mov sp, r7 + 800cef6: bd80 pop {r7, pc} + 800cef8: 08013618 .word 0x08013618 + 800cefc: 08013d2c .word 0x08013d2c + 800cf00: 0801366c .word 0x0801366c + +0800cf04 : + +static struct pbuf * +tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen, + u32_t seqno_be /* already in network byte order */, + u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd) +{ + 800cf04: b580 push {r7, lr} + 800cf06: b086 sub sp, #24 + 800cf08: af00 add r7, sp, #0 + 800cf0a: 60f8 str r0, [r7, #12] + 800cf0c: 607b str r3, [r7, #4] + 800cf0e: 460b mov r3, r1 + 800cf10: 817b strh r3, [r7, #10] + 800cf12: 4613 mov r3, r2 + 800cf14: 813b strh r3, [r7, #8] + struct tcp_hdr *tcphdr; + struct pbuf *p; + + p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM); + 800cf16: 897a ldrh r2, [r7, #10] + 800cf18: 893b ldrh r3, [r7, #8] + 800cf1a: 4413 add r3, r2 + 800cf1c: b29b uxth r3, r3 + 800cf1e: 3314 adds r3, #20 + 800cf20: b29b uxth r3, r3 + 800cf22: f44f 7220 mov.w r2, #640 ; 0x280 + 800cf26: 4619 mov r1, r3 + 800cf28: 2022 movs r0, #34 ; 0x22 + 800cf2a: f7f9 fd6f bl 8006a0c + 800cf2e: 6178 str r0, [r7, #20] + if (p != NULL) { + 800cf30: 697b ldr r3, [r7, #20] + 800cf32: 2b00 cmp r3, #0 + 800cf34: d04d beq.n 800cfd2 + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + 800cf36: 897b ldrh r3, [r7, #10] + 800cf38: 3313 adds r3, #19 + 800cf3a: 697a ldr r2, [r7, #20] + 800cf3c: 8952 ldrh r2, [r2, #10] + 800cf3e: 4293 cmp r3, r2 + 800cf40: db06 blt.n 800cf50 + 800cf42: 4b26 ldr r3, [pc, #152] ; (800cfdc ) + 800cf44: f240 7223 movw r2, #1827 ; 0x723 + 800cf48: 4925 ldr r1, [pc, #148] ; (800cfe0 ) + 800cf4a: 4826 ldr r0, [pc, #152] ; (800cfe4 ) + 800cf4c: f003 fe3c bl 8010bc8 + (p->len >= TCP_HLEN + optlen)); + tcphdr = (struct tcp_hdr *)p->payload; + 800cf50: 697b ldr r3, [r7, #20] + 800cf52: 685b ldr r3, [r3, #4] + 800cf54: 613b str r3, [r7, #16] + tcphdr->src = lwip_htons(src_port); + 800cf56: 8c3b ldrh r3, [r7, #32] + 800cf58: 4618 mov r0, r3 + 800cf5a: f7f8 faf7 bl 800554c + 800cf5e: 4603 mov r3, r0 + 800cf60: 461a mov r2, r3 + 800cf62: 693b ldr r3, [r7, #16] + 800cf64: 801a strh r2, [r3, #0] + tcphdr->dest = lwip_htons(dst_port); + 800cf66: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800cf68: 4618 mov r0, r3 + 800cf6a: f7f8 faef bl 800554c + 800cf6e: 4603 mov r3, r0 + 800cf70: 461a mov r2, r3 + 800cf72: 693b ldr r3, [r7, #16] + 800cf74: 805a strh r2, [r3, #2] + tcphdr->seqno = seqno_be; + 800cf76: 693b ldr r3, [r7, #16] + 800cf78: 687a ldr r2, [r7, #4] + 800cf7a: 605a str r2, [r3, #4] + tcphdr->ackno = lwip_htonl(ackno); + 800cf7c: 68f8 ldr r0, [r7, #12] + 800cf7e: f7f8 fafa bl 8005576 + 800cf82: 4602 mov r2, r0 + 800cf84: 693b ldr r3, [r7, #16] + 800cf86: 609a str r2, [r3, #8] + TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags); + 800cf88: 897b ldrh r3, [r7, #10] + 800cf8a: 089b lsrs r3, r3, #2 + 800cf8c: b29b uxth r3, r3 + 800cf8e: 3305 adds r3, #5 + 800cf90: b29b uxth r3, r3 + 800cf92: 031b lsls r3, r3, #12 + 800cf94: b29a uxth r2, r3 + 800cf96: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 800cf9a: b29b uxth r3, r3 + 800cf9c: 4313 orrs r3, r2 + 800cf9e: b29b uxth r3, r3 + 800cfa0: 4618 mov r0, r3 + 800cfa2: f7f8 fad3 bl 800554c + 800cfa6: 4603 mov r3, r0 + 800cfa8: 461a mov r2, r3 + 800cfaa: 693b ldr r3, [r7, #16] + 800cfac: 819a strh r2, [r3, #12] + tcphdr->wnd = lwip_htons(wnd); + 800cfae: 8dbb ldrh r3, [r7, #44] ; 0x2c + 800cfb0: 4618 mov r0, r3 + 800cfb2: f7f8 facb bl 800554c + 800cfb6: 4603 mov r3, r0 + 800cfb8: 461a mov r2, r3 + 800cfba: 693b ldr r3, [r7, #16] + 800cfbc: 81da strh r2, [r3, #14] + tcphdr->chksum = 0; + 800cfbe: 693b ldr r3, [r7, #16] + 800cfc0: 2200 movs r2, #0 + 800cfc2: 741a strb r2, [r3, #16] + 800cfc4: 2200 movs r2, #0 + 800cfc6: 745a strb r2, [r3, #17] + tcphdr->urgp = 0; + 800cfc8: 693b ldr r3, [r7, #16] + 800cfca: 2200 movs r2, #0 + 800cfcc: 749a strb r2, [r3, #18] + 800cfce: 2200 movs r2, #0 + 800cfd0: 74da strb r2, [r3, #19] + } + return p; + 800cfd2: 697b ldr r3, [r7, #20] +} + 800cfd4: 4618 mov r0, r3 + 800cfd6: 3718 adds r7, #24 + 800cfd8: 46bd mov sp, r7 + 800cfda: bd80 pop {r7, pc} + 800cfdc: 08013618 .word 0x08013618 + 800cfe0: 08013d4c .word 0x08013d4c + 800cfe4: 0801366c .word 0x0801366c + +0800cfe8 : + * @return pbuf with p->payload being the tcp_hdr + */ +static struct pbuf * +tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen, + u32_t seqno_be /* already in network byte order */) +{ + 800cfe8: b5b0 push {r4, r5, r7, lr} + 800cfea: b08a sub sp, #40 ; 0x28 + 800cfec: af04 add r7, sp, #16 + 800cfee: 60f8 str r0, [r7, #12] + 800cff0: 607b str r3, [r7, #4] + 800cff2: 460b mov r3, r1 + 800cff4: 817b strh r3, [r7, #10] + 800cff6: 4613 mov r3, r2 + 800cff8: 813b strh r3, [r7, #8] + struct pbuf *p; + + LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL); + 800cffa: 68fb ldr r3, [r7, #12] + 800cffc: 2b00 cmp r3, #0 + 800cffe: d106 bne.n 800d00e + 800d000: 4b15 ldr r3, [pc, #84] ; (800d058 ) + 800d002: f240 7242 movw r2, #1858 ; 0x742 + 800d006: 4915 ldr r1, [pc, #84] ; (800d05c ) + 800d008: 4815 ldr r0, [pc, #84] ; (800d060 ) + 800d00a: f003 fddd bl 8010bc8 + + p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen, + 800d00e: 68fb ldr r3, [r7, #12] + 800d010: 6a58 ldr r0, [r3, #36] ; 0x24 + 800d012: 68fb ldr r3, [r7, #12] + 800d014: 8adb ldrh r3, [r3, #22] + 800d016: 68fa ldr r2, [r7, #12] + 800d018: 8b12 ldrh r2, [r2, #24] + 800d01a: 68f9 ldr r1, [r7, #12] + 800d01c: 8d49 ldrh r1, [r1, #42] ; 0x2a + 800d01e: 893d ldrh r5, [r7, #8] + 800d020: 897c ldrh r4, [r7, #10] + 800d022: 9103 str r1, [sp, #12] + 800d024: 2110 movs r1, #16 + 800d026: 9102 str r1, [sp, #8] + 800d028: 9201 str r2, [sp, #4] + 800d02a: 9300 str r3, [sp, #0] + 800d02c: 687b ldr r3, [r7, #4] + 800d02e: 462a mov r2, r5 + 800d030: 4621 mov r1, r4 + 800d032: f7ff ff67 bl 800cf04 + 800d036: 6178 str r0, [r7, #20] + seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK, + TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); + if (p != NULL) { + 800d038: 697b ldr r3, [r7, #20] + 800d03a: 2b00 cmp r3, #0 + 800d03c: d006 beq.n 800d04c + /* If we're sending a packet, update the announced right window edge */ + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + 800d03e: 68fb ldr r3, [r7, #12] + 800d040: 6a5b ldr r3, [r3, #36] ; 0x24 + 800d042: 68fa ldr r2, [r7, #12] + 800d044: 8d52 ldrh r2, [r2, #42] ; 0x2a + 800d046: 441a add r2, r3 + 800d048: 68fb ldr r3, [r7, #12] + 800d04a: 62da str r2, [r3, #44] ; 0x2c + } + return p; + 800d04c: 697b ldr r3, [r7, #20] +} + 800d04e: 4618 mov r0, r3 + 800d050: 3718 adds r7, #24 + 800d052: 46bd mov sp, r7 + 800d054: bdb0 pop {r4, r5, r7, pc} + 800d056: bf00 nop + 800d058: 08013618 .word 0x08013618 + 800d05c: 08013d7c .word 0x08013d7c + 800d060: 0801366c .word 0x0801366c + +0800d064 : + +/* Fill in options for control segments */ +static void +tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks) +{ + 800d064: b580 push {r7, lr} + 800d066: b088 sub sp, #32 + 800d068: af00 add r7, sp, #0 + 800d06a: 60f8 str r0, [r7, #12] + 800d06c: 60b9 str r1, [r7, #8] + 800d06e: 4611 mov r1, r2 + 800d070: 461a mov r2, r3 + 800d072: 460b mov r3, r1 + 800d074: 71fb strb r3, [r7, #7] + 800d076: 4613 mov r3, r2 + 800d078: 71bb strb r3, [r7, #6] + struct tcp_hdr *tcphdr; + u32_t *opts; + u16_t sacks_len = 0; + 800d07a: 2300 movs r3, #0 + 800d07c: 83fb strh r3, [r7, #30] + + LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL); + 800d07e: 68bb ldr r3, [r7, #8] + 800d080: 2b00 cmp r3, #0 + 800d082: d106 bne.n 800d092 + 800d084: 4b12 ldr r3, [pc, #72] ; (800d0d0 ) + 800d086: f240 7256 movw r2, #1878 ; 0x756 + 800d08a: 4912 ldr r1, [pc, #72] ; (800d0d4 ) + 800d08c: 4812 ldr r0, [pc, #72] ; (800d0d8 ) + 800d08e: f003 fd9b bl 8010bc8 + + tcphdr = (struct tcp_hdr *)p->payload; + 800d092: 68bb ldr r3, [r7, #8] + 800d094: 685b ldr r3, [r3, #4] + 800d096: 61bb str r3, [r7, #24] + opts = (u32_t *)(void *)(tcphdr + 1); + 800d098: 69bb ldr r3, [r7, #24] + 800d09a: 3314 adds r3, #20 + 800d09c: 617b str r3, [r7, #20] + opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts); +#endif + + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(sacks_len); + LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb)); + 800d09e: 8bfb ldrh r3, [r7, #30] + 800d0a0: 009b lsls r3, r3, #2 + 800d0a2: 461a mov r2, r3 + 800d0a4: 79fb ldrb r3, [r7, #7] + 800d0a6: 009b lsls r3, r3, #2 + 800d0a8: f003 0304 and.w r3, r3, #4 + 800d0ac: 4413 add r3, r2 + 800d0ae: 3314 adds r3, #20 + 800d0b0: 69ba ldr r2, [r7, #24] + 800d0b2: 4413 add r3, r2 + 800d0b4: 697a ldr r2, [r7, #20] + 800d0b6: 429a cmp r2, r3 + 800d0b8: d006 beq.n 800d0c8 + 800d0ba: 4b05 ldr r3, [pc, #20] ; (800d0d0 ) + 800d0bc: f240 7275 movw r2, #1909 ; 0x775 + 800d0c0: 4906 ldr r1, [pc, #24] ; (800d0dc ) + 800d0c2: 4805 ldr r0, [pc, #20] ; (800d0d8 ) + 800d0c4: f003 fd80 bl 8010bc8 + LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */ + LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */ +} + 800d0c8: bf00 nop + 800d0ca: 3720 adds r7, #32 + 800d0cc: 46bd mov sp, r7 + 800d0ce: bd80 pop {r7, pc} + 800d0d0: 08013618 .word 0x08013618 + 800d0d4: 08013da4 .word 0x08013da4 + 800d0d8: 0801366c .word 0x0801366c + 800d0dc: 08013c9c .word 0x08013c9c + +0800d0e0 : + * header checksum and calling ip_output_if while handling netif hints and stats. + */ +static err_t +tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p, + const ip_addr_t *src, const ip_addr_t *dst) +{ + 800d0e0: b580 push {r7, lr} + 800d0e2: b08a sub sp, #40 ; 0x28 + 800d0e4: af04 add r7, sp, #16 + 800d0e6: 60f8 str r0, [r7, #12] + 800d0e8: 60b9 str r1, [r7, #8] + 800d0ea: 607a str r2, [r7, #4] + 800d0ec: 603b str r3, [r7, #0] + err_t err; + struct netif *netif; + + LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL); + 800d0ee: 68bb ldr r3, [r7, #8] + 800d0f0: 2b00 cmp r3, #0 + 800d0f2: d106 bne.n 800d102 + 800d0f4: 4b1c ldr r3, [pc, #112] ; (800d168 ) + 800d0f6: f240 7287 movw r2, #1927 ; 0x787 + 800d0fa: 491c ldr r1, [pc, #112] ; (800d16c ) + 800d0fc: 481c ldr r0, [pc, #112] ; (800d170 ) + 800d0fe: f003 fd63 bl 8010bc8 + + netif = tcp_route(pcb, src, dst); + 800d102: 683a ldr r2, [r7, #0] + 800d104: 6879 ldr r1, [r7, #4] + 800d106: 68f8 ldr r0, [r7, #12] + 800d108: f7fe fa7c bl 800b604 + 800d10c: 6138 str r0, [r7, #16] + if (netif == NULL) { + 800d10e: 693b ldr r3, [r7, #16] + 800d110: 2b00 cmp r3, #0 + 800d112: d102 bne.n 800d11a + err = ERR_RTE; + 800d114: 23fc movs r3, #252 ; 0xfc + 800d116: 75fb strb r3, [r7, #23] + 800d118: e01c b.n 800d154 + struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload; + tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, + src, dst); + } +#endif + if (pcb != NULL) { + 800d11a: 68fb ldr r3, [r7, #12] + 800d11c: 2b00 cmp r3, #0 + 800d11e: d006 beq.n 800d12e + NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints))); + ttl = pcb->ttl; + 800d120: 68fb ldr r3, [r7, #12] + 800d122: 7adb ldrb r3, [r3, #11] + 800d124: 75bb strb r3, [r7, #22] + tos = pcb->tos; + 800d126: 68fb ldr r3, [r7, #12] + 800d128: 7a9b ldrb r3, [r3, #10] + 800d12a: 757b strb r3, [r7, #21] + 800d12c: e003 b.n 800d136 + } else { + /* Send output with hardcoded TTL/HL since we have no access to the pcb */ + ttl = TCP_TTL; + 800d12e: 23ff movs r3, #255 ; 0xff + 800d130: 75bb strb r3, [r7, #22] + tos = 0; + 800d132: 2300 movs r3, #0 + 800d134: 757b strb r3, [r7, #21] + } + TCP_STATS_INC(tcp.xmit); + err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif); + 800d136: 7dba ldrb r2, [r7, #22] + 800d138: 693b ldr r3, [r7, #16] + 800d13a: 9302 str r3, [sp, #8] + 800d13c: 2306 movs r3, #6 + 800d13e: 9301 str r3, [sp, #4] + 800d140: 7d7b ldrb r3, [r7, #21] + 800d142: 9300 str r3, [sp, #0] + 800d144: 4613 mov r3, r2 + 800d146: 683a ldr r2, [r7, #0] + 800d148: 6879 ldr r1, [r7, #4] + 800d14a: 68b8 ldr r0, [r7, #8] + 800d14c: f002 f85a bl 800f204 + 800d150: 4603 mov r3, r0 + 800d152: 75fb strb r3, [r7, #23] + NETIF_RESET_HINTS(netif); + } + pbuf_free(p); + 800d154: 68b8 ldr r0, [r7, #8] + 800d156: f7f9 ff3d bl 8006fd4 + return err; + 800d15a: f997 3017 ldrsb.w r3, [r7, #23] +} + 800d15e: 4618 mov r0, r3 + 800d160: 3718 adds r7, #24 + 800d162: 46bd mov sp, r7 + 800d164: bd80 pop {r7, pc} + 800d166: bf00 nop + 800d168: 08013618 .word 0x08013618 + 800d16c: 08013dcc .word 0x08013dcc + 800d170: 0801366c .word 0x0801366c + +0800d174 : + */ +void +tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno, + const ip_addr_t *local_ip, const ip_addr_t *remote_ip, + u16_t local_port, u16_t remote_port) +{ + 800d174: b590 push {r4, r7, lr} + 800d176: b08b sub sp, #44 ; 0x2c + 800d178: af04 add r7, sp, #16 + 800d17a: 60f8 str r0, [r7, #12] + 800d17c: 60b9 str r1, [r7, #8] + 800d17e: 607a str r2, [r7, #4] + 800d180: 603b str r3, [r7, #0] + struct pbuf *p; + u16_t wnd; + u8_t optlen; + + LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL); + 800d182: 683b ldr r3, [r7, #0] + 800d184: 2b00 cmp r3, #0 + 800d186: d106 bne.n 800d196 + 800d188: 4b1f ldr r3, [pc, #124] ; (800d208 ) + 800d18a: f240 72c4 movw r2, #1988 ; 0x7c4 + 800d18e: 491f ldr r1, [pc, #124] ; (800d20c ) + 800d190: 481f ldr r0, [pc, #124] ; (800d210 ) + 800d192: f003 fd19 bl 8010bc8 + LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL); + 800d196: 6abb ldr r3, [r7, #40] ; 0x28 + 800d198: 2b00 cmp r3, #0 + 800d19a: d106 bne.n 800d1aa + 800d19c: 4b1a ldr r3, [pc, #104] ; (800d208 ) + 800d19e: f240 72c5 movw r2, #1989 ; 0x7c5 + 800d1a2: 491c ldr r1, [pc, #112] ; (800d214 ) + 800d1a4: 481a ldr r0, [pc, #104] ; (800d210 ) + 800d1a6: f003 fd0f bl 8010bc8 + + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + 800d1aa: 2300 movs r3, #0 + 800d1ac: 75fb strb r3, [r7, #23] + +#if LWIP_WND_SCALE + wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF)); +#else + wnd = PP_HTONS(TCP_WND); + 800d1ae: f246 0308 movw r3, #24584 ; 0x6008 + 800d1b2: 82bb strh r3, [r7, #20] +#endif + + p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port, + 800d1b4: 7dfb ldrb r3, [r7, #23] + 800d1b6: b29c uxth r4, r3 + 800d1b8: 68b8 ldr r0, [r7, #8] + 800d1ba: f7f8 f9dc bl 8005576 + 800d1be: 4602 mov r2, r0 + 800d1c0: 8abb ldrh r3, [r7, #20] + 800d1c2: 9303 str r3, [sp, #12] + 800d1c4: 2314 movs r3, #20 + 800d1c6: 9302 str r3, [sp, #8] + 800d1c8: 8e3b ldrh r3, [r7, #48] ; 0x30 + 800d1ca: 9301 str r3, [sp, #4] + 800d1cc: 8dbb ldrh r3, [r7, #44] ; 0x2c + 800d1ce: 9300 str r3, [sp, #0] + 800d1d0: 4613 mov r3, r2 + 800d1d2: 2200 movs r2, #0 + 800d1d4: 4621 mov r1, r4 + 800d1d6: 6878 ldr r0, [r7, #4] + 800d1d8: f7ff fe94 bl 800cf04 + 800d1dc: 6138 str r0, [r7, #16] + remote_port, TCP_RST | TCP_ACK, wnd); + if (p == NULL) { + 800d1de: 693b ldr r3, [r7, #16] + 800d1e0: 2b00 cmp r3, #0 + 800d1e2: d00c beq.n 800d1fe + LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); + return; + } + tcp_output_fill_options(pcb, p, 0, optlen); + 800d1e4: 7dfb ldrb r3, [r7, #23] + 800d1e6: 2200 movs r2, #0 + 800d1e8: 6939 ldr r1, [r7, #16] + 800d1ea: 68f8 ldr r0, [r7, #12] + 800d1ec: f7ff ff3a bl 800d064 + + MIB2_STATS_INC(mib2.tcpoutrsts); + + tcp_output_control_segment(pcb, p, local_ip, remote_ip); + 800d1f0: 6abb ldr r3, [r7, #40] ; 0x28 + 800d1f2: 683a ldr r2, [r7, #0] + 800d1f4: 6939 ldr r1, [r7, #16] + 800d1f6: 68f8 ldr r0, [r7, #12] + 800d1f8: f7ff ff72 bl 800d0e0 + 800d1fc: e000 b.n 800d200 + return; + 800d1fe: bf00 nop + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); +} + 800d200: 371c adds r7, #28 + 800d202: 46bd mov sp, r7 + 800d204: bd90 pop {r4, r7, pc} + 800d206: bf00 nop + 800d208: 08013618 .word 0x08013618 + 800d20c: 08013df8 .word 0x08013df8 + 800d210: 0801366c .word 0x0801366c + 800d214: 08013e14 .word 0x08013e14 + +0800d218 : + * + * @param pcb Protocol control block for the TCP connection to send the ACK + */ +err_t +tcp_send_empty_ack(struct tcp_pcb *pcb) +{ + 800d218: b590 push {r4, r7, lr} + 800d21a: b087 sub sp, #28 + 800d21c: af00 add r7, sp, #0 + 800d21e: 6078 str r0, [r7, #4] + err_t err; + struct pbuf *p; + u8_t optlen, optflags = 0; + 800d220: 2300 movs r3, #0 + 800d222: 75fb strb r3, [r7, #23] + u8_t num_sacks = 0; + 800d224: 2300 movs r3, #0 + 800d226: 75bb strb r3, [r7, #22] + + LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL); + 800d228: 687b ldr r3, [r7, #4] + 800d22a: 2b00 cmp r3, #0 + 800d22c: d106 bne.n 800d23c + 800d22e: 4b28 ldr r3, [pc, #160] ; (800d2d0 ) + 800d230: f240 72ea movw r2, #2026 ; 0x7ea + 800d234: 4927 ldr r1, [pc, #156] ; (800d2d4 ) + 800d236: 4828 ldr r0, [pc, #160] ; (800d2d8 ) + 800d238: f003 fcc6 bl 8010bc8 +#if LWIP_TCP_TIMESTAMPS + if (pcb->flags & TF_TIMESTAMP) { + optflags = TF_SEG_OPTS_TS; + } +#endif + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + 800d23c: 7dfb ldrb r3, [r7, #23] + 800d23e: 009b lsls r3, r3, #2 + 800d240: b2db uxtb r3, r3 + 800d242: f003 0304 and.w r3, r3, #4 + 800d246: 757b strb r3, [r7, #21] + if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) { + optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */ + } +#endif + + p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt)); + 800d248: 7d7b ldrb r3, [r7, #21] + 800d24a: b29c uxth r4, r3 + 800d24c: 687b ldr r3, [r7, #4] + 800d24e: 6d1b ldr r3, [r3, #80] ; 0x50 + 800d250: 4618 mov r0, r3 + 800d252: f7f8 f990 bl 8005576 + 800d256: 4603 mov r3, r0 + 800d258: 2200 movs r2, #0 + 800d25a: 4621 mov r1, r4 + 800d25c: 6878 ldr r0, [r7, #4] + 800d25e: f7ff fec3 bl 800cfe8 + 800d262: 6138 str r0, [r7, #16] + if (p == NULL) { + 800d264: 693b ldr r3, [r7, #16] + 800d266: 2b00 cmp r3, #0 + 800d268: d109 bne.n 800d27e + /* let tcp_fasttmr retry sending this ACK */ + tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 800d26a: 687b ldr r3, [r7, #4] + 800d26c: 8b5b ldrh r3, [r3, #26] + 800d26e: f043 0303 orr.w r3, r3, #3 + 800d272: b29a uxth r2, r3 + 800d274: 687b ldr r3, [r7, #4] + 800d276: 835a strh r2, [r3, #26] + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + 800d278: f06f 0301 mvn.w r3, #1 + 800d27c: e023 b.n 800d2c6 + } + tcp_output_fill_options(pcb, p, optflags, num_sacks); + 800d27e: 7dbb ldrb r3, [r7, #22] + 800d280: 7dfa ldrb r2, [r7, #23] + 800d282: 6939 ldr r1, [r7, #16] + 800d284: 6878 ldr r0, [r7, #4] + 800d286: f7ff feed bl 800d064 + pcb->ts_lastacksent = pcb->rcv_nxt; +#endif + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, + ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + 800d28a: 687a ldr r2, [r7, #4] + 800d28c: 687b ldr r3, [r7, #4] + 800d28e: 3304 adds r3, #4 + 800d290: 6939 ldr r1, [r7, #16] + 800d292: 6878 ldr r0, [r7, #4] + 800d294: f7ff ff24 bl 800d0e0 + 800d298: 4603 mov r3, r0 + 800d29a: 73fb strb r3, [r7, #15] + if (err != ERR_OK) { + 800d29c: f997 300f ldrsb.w r3, [r7, #15] + 800d2a0: 2b00 cmp r3, #0 + 800d2a2: d007 beq.n 800d2b4 + /* let tcp_fasttmr retry sending this ACK */ + tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 800d2a4: 687b ldr r3, [r7, #4] + 800d2a6: 8b5b ldrh r3, [r3, #26] + 800d2a8: f043 0303 orr.w r3, r3, #3 + 800d2ac: b29a uxth r2, r3 + 800d2ae: 687b ldr r3, [r7, #4] + 800d2b0: 835a strh r2, [r3, #26] + 800d2b2: e006 b.n 800d2c2 + } else { + /* remove ACK flags from the PCB, as we sent an empty ACK now */ + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + 800d2b4: 687b ldr r3, [r7, #4] + 800d2b6: 8b5b ldrh r3, [r3, #26] + 800d2b8: f023 0303 bic.w r3, r3, #3 + 800d2bc: b29a uxth r2, r3 + 800d2be: 687b ldr r3, [r7, #4] + 800d2c0: 835a strh r2, [r3, #26] + } + + return err; + 800d2c2: f997 300f ldrsb.w r3, [r7, #15] +} + 800d2c6: 4618 mov r0, r3 + 800d2c8: 371c adds r7, #28 + 800d2ca: 46bd mov sp, r7 + 800d2cc: bd90 pop {r4, r7, pc} + 800d2ce: bf00 nop + 800d2d0: 08013618 .word 0x08013618 + 800d2d4: 08013e30 .word 0x08013e30 + 800d2d8: 0801366c .word 0x0801366c + +0800d2dc : + * + * @param pcb the tcp_pcb for which to send a keepalive packet + */ +err_t +tcp_keepalive(struct tcp_pcb *pcb) +{ + 800d2dc: b590 push {r4, r7, lr} + 800d2de: b085 sub sp, #20 + 800d2e0: af00 add r7, sp, #0 + 800d2e2: 6078 str r0, [r7, #4] + err_t err; + struct pbuf *p; + u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + 800d2e4: 2300 movs r3, #0 + 800d2e6: 72bb strb r3, [r7, #10] + + LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL); + 800d2e8: 687b ldr r3, [r7, #4] + 800d2ea: 2b00 cmp r3, #0 + 800d2ec: d106 bne.n 800d2fc + 800d2ee: 4b18 ldr r3, [pc, #96] ; (800d350 ) + 800d2f0: f640 0224 movw r2, #2084 ; 0x824 + 800d2f4: 4917 ldr r1, [pc, #92] ; (800d354 ) + 800d2f6: 4818 ldr r0, [pc, #96] ; (800d358 ) + 800d2f8: f003 fc66 bl 8010bc8 + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); + + p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1)); + 800d2fc: 7abb ldrb r3, [r7, #10] + 800d2fe: b29c uxth r4, r3 + 800d300: 687b ldr r3, [r7, #4] + 800d302: 6d1b ldr r3, [r3, #80] ; 0x50 + 800d304: 3b01 subs r3, #1 + 800d306: 4618 mov r0, r3 + 800d308: f7f8 f935 bl 8005576 + 800d30c: 4603 mov r3, r0 + 800d30e: 2200 movs r2, #0 + 800d310: 4621 mov r1, r4 + 800d312: 6878 ldr r0, [r7, #4] + 800d314: f7ff fe68 bl 800cfe8 + 800d318: 60f8 str r0, [r7, #12] + if (p == NULL) { + 800d31a: 68fb ldr r3, [r7, #12] + 800d31c: 2b00 cmp r3, #0 + 800d31e: d102 bne.n 800d326 + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_keepalive: could not allocate memory for pbuf\n")); + return ERR_MEM; + 800d320: f04f 33ff mov.w r3, #4294967295 + 800d324: e010 b.n 800d348 + } + tcp_output_fill_options(pcb, p, 0, optlen); + 800d326: 7abb ldrb r3, [r7, #10] + 800d328: 2200 movs r2, #0 + 800d32a: 68f9 ldr r1, [r7, #12] + 800d32c: 6878 ldr r0, [r7, #4] + 800d32e: f7ff fe99 bl 800d064 + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + 800d332: 687a ldr r2, [r7, #4] + 800d334: 687b ldr r3, [r7, #4] + 800d336: 3304 adds r3, #4 + 800d338: 68f9 ldr r1, [r7, #12] + 800d33a: 6878 ldr r0, [r7, #4] + 800d33c: f7ff fed0 bl 800d0e0 + 800d340: 4603 mov r3, r0 + 800d342: 72fb strb r3, [r7, #11] + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n", + pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); + return err; + 800d344: f997 300b ldrsb.w r3, [r7, #11] +} + 800d348: 4618 mov r0, r3 + 800d34a: 3714 adds r7, #20 + 800d34c: 46bd mov sp, r7 + 800d34e: bd90 pop {r4, r7, pc} + 800d350: 08013618 .word 0x08013618 + 800d354: 08013e50 .word 0x08013e50 + 800d358: 0801366c .word 0x0801366c + +0800d35c : + * + * @param pcb the tcp_pcb for which to send a zero-window probe packet + */ +err_t +tcp_zero_window_probe(struct tcp_pcb *pcb) +{ + 800d35c: b590 push {r4, r7, lr} + 800d35e: b08b sub sp, #44 ; 0x2c + 800d360: af00 add r7, sp, #0 + 800d362: 6078 str r0, [r7, #4] + struct tcp_hdr *tcphdr; + struct tcp_seg *seg; + u16_t len; + u8_t is_fin; + u32_t snd_nxt; + u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + 800d364: 2300 movs r3, #0 + 800d366: 74fb strb r3, [r7, #19] + + LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL); + 800d368: 687b ldr r3, [r7, #4] + 800d36a: 2b00 cmp r3, #0 + 800d36c: d106 bne.n 800d37c + 800d36e: 4b4d ldr r3, [pc, #308] ; (800d4a4 ) + 800d370: f640 024f movw r2, #2127 ; 0x84f + 800d374: 494c ldr r1, [pc, #304] ; (800d4a8 ) + 800d376: 484d ldr r0, [pc, #308] ; (800d4ac ) + 800d378: f003 fc26 bl 8010bc8 + ("tcp_zero_window_probe: tcp_ticks %"U32_F + " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); + + /* Only consider unsent, persist timer should be off when there is data in-flight */ + seg = pcb->unsent; + 800d37c: 687b ldr r3, [r7, #4] + 800d37e: 6edb ldr r3, [r3, #108] ; 0x6c + 800d380: 627b str r3, [r7, #36] ; 0x24 + if (seg == NULL) { + 800d382: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d384: 2b00 cmp r3, #0 + 800d386: d101 bne.n 800d38c + /* Not expected, persist timer should be off when the send buffer is empty */ + return ERR_OK; + 800d388: 2300 movs r3, #0 + 800d38a: e087 b.n 800d49c + + /* increment probe count. NOTE: we record probe even if it fails + to actually transmit due to an error. This ensures memory exhaustion/ + routing problem doesn't leave a zero-window pcb as an indefinite zombie. + RTO mechanism has similar behavior, see pcb->nrtx */ + if (pcb->persist_probe < 0xFF) { + 800d38c: 687b ldr r3, [r7, #4] + 800d38e: f893 309a ldrb.w r3, [r3, #154] ; 0x9a + 800d392: 2bff cmp r3, #255 ; 0xff + 800d394: d007 beq.n 800d3a6 + ++pcb->persist_probe; + 800d396: 687b ldr r3, [r7, #4] + 800d398: f893 309a ldrb.w r3, [r3, #154] ; 0x9a + 800d39c: 3301 adds r3, #1 + 800d39e: b2da uxtb r2, r3 + 800d3a0: 687b ldr r3, [r7, #4] + 800d3a2: f883 209a strb.w r2, [r3, #154] ; 0x9a + } + + is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); + 800d3a6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d3a8: 691b ldr r3, [r3, #16] + 800d3aa: 899b ldrh r3, [r3, #12] + 800d3ac: b29b uxth r3, r3 + 800d3ae: 4618 mov r0, r3 + 800d3b0: f7f8 f8cc bl 800554c + 800d3b4: 4603 mov r3, r0 + 800d3b6: b2db uxtb r3, r3 + 800d3b8: f003 0301 and.w r3, r3, #1 + 800d3bc: 2b00 cmp r3, #0 + 800d3be: d005 beq.n 800d3cc + 800d3c0: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d3c2: 891b ldrh r3, [r3, #8] + 800d3c4: 2b00 cmp r3, #0 + 800d3c6: d101 bne.n 800d3cc + 800d3c8: 2301 movs r3, #1 + 800d3ca: e000 b.n 800d3ce + 800d3cc: 2300 movs r3, #0 + 800d3ce: f887 3023 strb.w r3, [r7, #35] ; 0x23 + /* we want to send one seqno: either FIN or data (no options) */ + len = is_fin ? 0 : 1; + 800d3d2: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800d3d6: 2b00 cmp r3, #0 + 800d3d8: bf0c ite eq + 800d3da: 2301 moveq r3, #1 + 800d3dc: 2300 movne r3, #0 + 800d3de: b2db uxtb r3, r3 + 800d3e0: 843b strh r3, [r7, #32] + + p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno); + 800d3e2: 7cfb ldrb r3, [r7, #19] + 800d3e4: b299 uxth r1, r3 + 800d3e6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d3e8: 691b ldr r3, [r3, #16] + 800d3ea: 685b ldr r3, [r3, #4] + 800d3ec: 8c3a ldrh r2, [r7, #32] + 800d3ee: 6878 ldr r0, [r7, #4] + 800d3f0: f7ff fdfa bl 800cfe8 + 800d3f4: 61f8 str r0, [r7, #28] + if (p == NULL) { + 800d3f6: 69fb ldr r3, [r7, #28] + 800d3f8: 2b00 cmp r3, #0 + 800d3fa: d102 bne.n 800d402 + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); + return ERR_MEM; + 800d3fc: f04f 33ff mov.w r3, #4294967295 + 800d400: e04c b.n 800d49c + } + tcphdr = (struct tcp_hdr *)p->payload; + 800d402: 69fb ldr r3, [r7, #28] + 800d404: 685b ldr r3, [r3, #4] + 800d406: 61bb str r3, [r7, #24] + + if (is_fin) { + 800d408: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800d40c: 2b00 cmp r3, #0 + 800d40e: d011 beq.n 800d434 + /* FIN segment, no data */ + TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); + 800d410: 69bb ldr r3, [r7, #24] + 800d412: 899b ldrh r3, [r3, #12] + 800d414: b29b uxth r3, r3 + 800d416: b21b sxth r3, r3 + 800d418: f423 537c bic.w r3, r3, #16128 ; 0x3f00 + 800d41c: b21c sxth r4, r3 + 800d41e: 2011 movs r0, #17 + 800d420: f7f8 f894 bl 800554c + 800d424: 4603 mov r3, r0 + 800d426: b21b sxth r3, r3 + 800d428: 4323 orrs r3, r4 + 800d42a: b21b sxth r3, r3 + 800d42c: b29a uxth r2, r3 + 800d42e: 69bb ldr r3, [r7, #24] + 800d430: 819a strh r2, [r3, #12] + 800d432: e010 b.n 800d456 + } else { + /* Data segment, copy in one byte from the head of the unacked queue */ + char *d = ((char *)p->payload + TCP_HLEN); + 800d434: 69fb ldr r3, [r7, #28] + 800d436: 685b ldr r3, [r3, #4] + 800d438: 3314 adds r3, #20 + 800d43a: 617b str r3, [r7, #20] + /* Depending on whether the segment has already been sent (unacked) or not + (unsent), seg->p->payload points to the IP header or TCP header. + Ensure we copy the first TCP data byte: */ + pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len); + 800d43c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d43e: 6858 ldr r0, [r3, #4] + 800d440: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d442: 685b ldr r3, [r3, #4] + 800d444: 891a ldrh r2, [r3, #8] + 800d446: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d448: 891b ldrh r3, [r3, #8] + 800d44a: 1ad3 subs r3, r2, r3 + 800d44c: b29b uxth r3, r3 + 800d44e: 2201 movs r2, #1 + 800d450: 6979 ldr r1, [r7, #20] + 800d452: f7f9 ffa9 bl 80073a8 + } + + /* The byte may be acknowledged without the window being opened. */ + snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1; + 800d456: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d458: 691b ldr r3, [r3, #16] + 800d45a: 685b ldr r3, [r3, #4] + 800d45c: 4618 mov r0, r3 + 800d45e: f7f8 f88a bl 8005576 + 800d462: 4603 mov r3, r0 + 800d464: 3301 adds r3, #1 + 800d466: 60fb str r3, [r7, #12] + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + 800d468: 687b ldr r3, [r7, #4] + 800d46a: 6d1a ldr r2, [r3, #80] ; 0x50 + 800d46c: 68fb ldr r3, [r7, #12] + 800d46e: 1ad3 subs r3, r2, r3 + 800d470: 2b00 cmp r3, #0 + 800d472: da02 bge.n 800d47a + pcb->snd_nxt = snd_nxt; + 800d474: 687b ldr r3, [r7, #4] + 800d476: 68fa ldr r2, [r7, #12] + 800d478: 651a str r2, [r3, #80] ; 0x50 + } + tcp_output_fill_options(pcb, p, 0, optlen); + 800d47a: 7cfb ldrb r3, [r7, #19] + 800d47c: 2200 movs r2, #0 + 800d47e: 69f9 ldr r1, [r7, #28] + 800d480: 6878 ldr r0, [r7, #4] + 800d482: f7ff fdef bl 800d064 + + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + 800d486: 687a ldr r2, [r7, #4] + 800d488: 687b ldr r3, [r7, #4] + 800d48a: 3304 adds r3, #4 + 800d48c: 69f9 ldr r1, [r7, #28] + 800d48e: 6878 ldr r0, [r7, #4] + 800d490: f7ff fe26 bl 800d0e0 + 800d494: 4603 mov r3, r0 + 800d496: 72fb strb r3, [r7, #11] + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F + " ackno %"U32_F" err %d.\n", + pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); + return err; + 800d498: f997 300b ldrsb.w r3, [r7, #11] +} + 800d49c: 4618 mov r0, r3 + 800d49e: 372c adds r7, #44 ; 0x2c + 800d4a0: 46bd mov sp, r7 + 800d4a2: bd90 pop {r4, r7, pc} + 800d4a4: 08013618 .word 0x08013618 + 800d4a8: 08013e6c .word 0x08013e6c + 800d4ac: 0801366c .word 0x0801366c + +0800d4b0 : + * + * @param arg unused argument + */ +static void +tcpip_tcp_timer(void *arg) +{ + 800d4b0: b580 push {r7, lr} + 800d4b2: b082 sub sp, #8 + 800d4b4: af00 add r7, sp, #0 + 800d4b6: 6078 str r0, [r7, #4] + LWIP_UNUSED_ARG(arg); + + /* call TCP timer handler */ + tcp_tmr(); + 800d4b8: f7fa f864 bl 8007584 + /* timer still needed? */ + if (tcp_active_pcbs || tcp_tw_pcbs) { + 800d4bc: 4b0a ldr r3, [pc, #40] ; (800d4e8 ) + 800d4be: 681b ldr r3, [r3, #0] + 800d4c0: 2b00 cmp r3, #0 + 800d4c2: d103 bne.n 800d4cc + 800d4c4: 4b09 ldr r3, [pc, #36] ; (800d4ec ) + 800d4c6: 681b ldr r3, [r3, #0] + 800d4c8: 2b00 cmp r3, #0 + 800d4ca: d005 beq.n 800d4d8 + /* restart timer */ + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + 800d4cc: 2200 movs r2, #0 + 800d4ce: 4908 ldr r1, [pc, #32] ; (800d4f0 ) + 800d4d0: 20fa movs r0, #250 ; 0xfa + 800d4d2: f000 f8f3 bl 800d6bc + 800d4d6: e003 b.n 800d4e0 + } else { + /* disable timer */ + tcpip_tcp_timer_active = 0; + 800d4d8: 4b06 ldr r3, [pc, #24] ; (800d4f4 ) + 800d4da: 2200 movs r2, #0 + 800d4dc: 601a str r2, [r3, #0] + } +} + 800d4de: bf00 nop + 800d4e0: bf00 nop + 800d4e2: 3708 adds r7, #8 + 800d4e4: 46bd mov sp, r7 + 800d4e6: bd80 pop {r7, pc} + 800d4e8: 24007b78 .word 0x24007b78 + 800d4ec: 24007b7c .word 0x24007b7c + 800d4f0: 0800d4b1 .word 0x0800d4b1 + 800d4f4: 24007bc8 .word 0x24007bc8 + +0800d4f8 : + * the reason is to have the TCP timer only running when + * there are active (or time-wait) PCBs. + */ +void +tcp_timer_needed(void) +{ + 800d4f8: b580 push {r7, lr} + 800d4fa: af00 add r7, sp, #0 + LWIP_ASSERT_CORE_LOCKED(); + + /* timer is off but needed again? */ + if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { + 800d4fc: 4b0a ldr r3, [pc, #40] ; (800d528 ) + 800d4fe: 681b ldr r3, [r3, #0] + 800d500: 2b00 cmp r3, #0 + 800d502: d10f bne.n 800d524 + 800d504: 4b09 ldr r3, [pc, #36] ; (800d52c ) + 800d506: 681b ldr r3, [r3, #0] + 800d508: 2b00 cmp r3, #0 + 800d50a: d103 bne.n 800d514 + 800d50c: 4b08 ldr r3, [pc, #32] ; (800d530 ) + 800d50e: 681b ldr r3, [r3, #0] + 800d510: 2b00 cmp r3, #0 + 800d512: d007 beq.n 800d524 + /* enable and start timer */ + tcpip_tcp_timer_active = 1; + 800d514: 4b04 ldr r3, [pc, #16] ; (800d528 ) + 800d516: 2201 movs r2, #1 + 800d518: 601a str r2, [r3, #0] + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + 800d51a: 2200 movs r2, #0 + 800d51c: 4905 ldr r1, [pc, #20] ; (800d534 ) + 800d51e: 20fa movs r0, #250 ; 0xfa + 800d520: f000 f8cc bl 800d6bc + } +} + 800d524: bf00 nop + 800d526: bd80 pop {r7, pc} + 800d528: 24007bc8 .word 0x24007bc8 + 800d52c: 24007b78 .word 0x24007b78 + 800d530: 24007b7c .word 0x24007b7c + 800d534: 0800d4b1 .word 0x0800d4b1 + +0800d538 : +#if LWIP_DEBUG_TIMERNAMES +sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg) +#endif +{ + 800d538: b580 push {r7, lr} + 800d53a: b086 sub sp, #24 + 800d53c: af00 add r7, sp, #0 + 800d53e: 60f8 str r0, [r7, #12] + 800d540: 60b9 str r1, [r7, #8] + 800d542: 607a str r2, [r7, #4] + struct sys_timeo *timeout, *t; + + timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT); + 800d544: 2006 movs r0, #6 + 800d546: f7f8 fd69 bl 800601c + 800d54a: 6138 str r0, [r7, #16] + if (timeout == NULL) { + 800d54c: 693b ldr r3, [r7, #16] + 800d54e: 2b00 cmp r3, #0 + 800d550: d109 bne.n 800d566 + LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); + 800d552: 693b ldr r3, [r7, #16] + 800d554: 2b00 cmp r3, #0 + 800d556: d151 bne.n 800d5fc + 800d558: 4b2a ldr r3, [pc, #168] ; (800d604 ) + 800d55a: 22be movs r2, #190 ; 0xbe + 800d55c: 492a ldr r1, [pc, #168] ; (800d608 ) + 800d55e: 482b ldr r0, [pc, #172] ; (800d60c ) + 800d560: f003 fb32 bl 8010bc8 + return; + 800d564: e04a b.n 800d5fc + } + + timeout->next = NULL; + 800d566: 693b ldr r3, [r7, #16] + 800d568: 2200 movs r2, #0 + 800d56a: 601a str r2, [r3, #0] + timeout->h = handler; + 800d56c: 693b ldr r3, [r7, #16] + 800d56e: 68ba ldr r2, [r7, #8] + 800d570: 609a str r2, [r3, #8] + timeout->arg = arg; + 800d572: 693b ldr r3, [r7, #16] + 800d574: 687a ldr r2, [r7, #4] + 800d576: 60da str r2, [r3, #12] + timeout->time = abs_time; + 800d578: 693b ldr r3, [r7, #16] + 800d57a: 68fa ldr r2, [r7, #12] + 800d57c: 605a str r2, [r3, #4] + timeout->handler_name = handler_name; + LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n", + (void *)timeout, abs_time, handler_name, (void *)arg)); +#endif /* LWIP_DEBUG_TIMERNAMES */ + + if (next_timeout == NULL) { + 800d57e: 4b24 ldr r3, [pc, #144] ; (800d610 ) + 800d580: 681b ldr r3, [r3, #0] + 800d582: 2b00 cmp r3, #0 + 800d584: d103 bne.n 800d58e + next_timeout = timeout; + 800d586: 4a22 ldr r2, [pc, #136] ; (800d610 ) + 800d588: 693b ldr r3, [r7, #16] + 800d58a: 6013 str r3, [r2, #0] + return; + 800d58c: e037 b.n 800d5fe + } + if (TIME_LESS_THAN(timeout->time, next_timeout->time)) { + 800d58e: 693b ldr r3, [r7, #16] + 800d590: 685a ldr r2, [r3, #4] + 800d592: 4b1f ldr r3, [pc, #124] ; (800d610 ) + 800d594: 681b ldr r3, [r3, #0] + 800d596: 685b ldr r3, [r3, #4] + 800d598: 1ad3 subs r3, r2, r3 + 800d59a: 0fdb lsrs r3, r3, #31 + 800d59c: f003 0301 and.w r3, r3, #1 + 800d5a0: b2db uxtb r3, r3 + 800d5a2: 2b00 cmp r3, #0 + 800d5a4: d007 beq.n 800d5b6 + timeout->next = next_timeout; + 800d5a6: 4b1a ldr r3, [pc, #104] ; (800d610 ) + 800d5a8: 681a ldr r2, [r3, #0] + 800d5aa: 693b ldr r3, [r7, #16] + 800d5ac: 601a str r2, [r3, #0] + next_timeout = timeout; + 800d5ae: 4a18 ldr r2, [pc, #96] ; (800d610 ) + 800d5b0: 693b ldr r3, [r7, #16] + 800d5b2: 6013 str r3, [r2, #0] + 800d5b4: e023 b.n 800d5fe + } else { + for (t = next_timeout; t != NULL; t = t->next) { + 800d5b6: 4b16 ldr r3, [pc, #88] ; (800d610 ) + 800d5b8: 681b ldr r3, [r3, #0] + 800d5ba: 617b str r3, [r7, #20] + 800d5bc: e01a b.n 800d5f4 + if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) { + 800d5be: 697b ldr r3, [r7, #20] + 800d5c0: 681b ldr r3, [r3, #0] + 800d5c2: 2b00 cmp r3, #0 + 800d5c4: d00b beq.n 800d5de + 800d5c6: 693b ldr r3, [r7, #16] + 800d5c8: 685a ldr r2, [r3, #4] + 800d5ca: 697b ldr r3, [r7, #20] + 800d5cc: 681b ldr r3, [r3, #0] + 800d5ce: 685b ldr r3, [r3, #4] + 800d5d0: 1ad3 subs r3, r2, r3 + 800d5d2: 0fdb lsrs r3, r3, #31 + 800d5d4: f003 0301 and.w r3, r3, #1 + 800d5d8: b2db uxtb r3, r3 + 800d5da: 2b00 cmp r3, #0 + 800d5dc: d007 beq.n 800d5ee + timeout->next = t->next; + 800d5de: 697b ldr r3, [r7, #20] + 800d5e0: 681a ldr r2, [r3, #0] + 800d5e2: 693b ldr r3, [r7, #16] + 800d5e4: 601a str r2, [r3, #0] + t->next = timeout; + 800d5e6: 697b ldr r3, [r7, #20] + 800d5e8: 693a ldr r2, [r7, #16] + 800d5ea: 601a str r2, [r3, #0] + break; + 800d5ec: e007 b.n 800d5fe + for (t = next_timeout; t != NULL; t = t->next) { + 800d5ee: 697b ldr r3, [r7, #20] + 800d5f0: 681b ldr r3, [r3, #0] + 800d5f2: 617b str r3, [r7, #20] + 800d5f4: 697b ldr r3, [r7, #20] + 800d5f6: 2b00 cmp r3, #0 + 800d5f8: d1e1 bne.n 800d5be + 800d5fa: e000 b.n 800d5fe + return; + 800d5fc: bf00 nop + } + } + } +} + 800d5fe: 3718 adds r7, #24 + 800d600: 46bd mov sp, r7 + 800d602: bd80 pop {r7, pc} + 800d604: 08013e90 .word 0x08013e90 + 800d608: 08013ec4 .word 0x08013ec4 + 800d60c: 08013f04 .word 0x08013f04 + 800d610: 24007bc0 .word 0x24007bc0 + +0800d614 : +#if !LWIP_TESTMODE +static +#endif +void +lwip_cyclic_timer(void *arg) +{ + 800d614: b580 push {r7, lr} + 800d616: b086 sub sp, #24 + 800d618: af00 add r7, sp, #0 + 800d61a: 6078 str r0, [r7, #4] + u32_t now; + u32_t next_timeout_time; + const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg; + 800d61c: 687b ldr r3, [r7, #4] + 800d61e: 617b str r3, [r7, #20] + +#if LWIP_DEBUG_TIMERNAMES + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name)); +#endif + cyclic->handler(); + 800d620: 697b ldr r3, [r7, #20] + 800d622: 685b ldr r3, [r3, #4] + 800d624: 4798 blx r3 + + now = sys_now(); + 800d626: f7f7 fd43 bl 80050b0 + 800d62a: 6138 str r0, [r7, #16] + next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */ + 800d62c: 697b ldr r3, [r7, #20] + 800d62e: 681a ldr r2, [r3, #0] + 800d630: 4b0f ldr r3, [pc, #60] ; (800d670 ) + 800d632: 681b ldr r3, [r3, #0] + 800d634: 4413 add r3, r2 + 800d636: 60fb str r3, [r7, #12] + if (TIME_LESS_THAN(next_timeout_time, now)) { + 800d638: 68fa ldr r2, [r7, #12] + 800d63a: 693b ldr r3, [r7, #16] + 800d63c: 1ad3 subs r3, r2, r3 + 800d63e: 0fdb lsrs r3, r3, #31 + 800d640: f003 0301 and.w r3, r3, #1 + 800d644: b2db uxtb r3, r3 + 800d646: 2b00 cmp r3, #0 + 800d648: d009 beq.n 800d65e + /* timer would immediately expire again -> "overload" -> restart without any correction */ +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg); + 800d64a: 697b ldr r3, [r7, #20] + 800d64c: 681a ldr r2, [r3, #0] + 800d64e: 693b ldr r3, [r7, #16] + 800d650: 4413 add r3, r2 + 800d652: 687a ldr r2, [r7, #4] + 800d654: 4907 ldr r1, [pc, #28] ; (800d674 ) + 800d656: 4618 mov r0, r3 + 800d658: f7ff ff6e bl 800d538 + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); +#endif + } +} + 800d65c: e004 b.n 800d668 + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); + 800d65e: 687a ldr r2, [r7, #4] + 800d660: 4904 ldr r1, [pc, #16] ; (800d674 ) + 800d662: 68f8 ldr r0, [r7, #12] + 800d664: f7ff ff68 bl 800d538 +} + 800d668: bf00 nop + 800d66a: 3718 adds r7, #24 + 800d66c: 46bd mov sp, r7 + 800d66e: bd80 pop {r7, pc} + 800d670: 24007bc4 .word 0x24007bc4 + 800d674: 0800d615 .word 0x0800d615 + +0800d678 : + +/** Initialize this module */ +void sys_timeouts_init(void) +{ + 800d678: b580 push {r7, lr} + 800d67a: b082 sub sp, #8 + 800d67c: af00 add r7, sp, #0 + size_t i; + /* tcp_tmr() at index 0 is started on demand */ + for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { + 800d67e: 2301 movs r3, #1 + 800d680: 607b str r3, [r7, #4] + 800d682: e00e b.n 800d6a2 + /* we have to cast via size_t to get rid of const warning + (this is OK as cyclic_timer() casts back to const* */ + sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i])); + 800d684: 4a0b ldr r2, [pc, #44] ; (800d6b4 ) + 800d686: 687b ldr r3, [r7, #4] + 800d688: f852 0033 ldr.w r0, [r2, r3, lsl #3] + 800d68c: 687b ldr r3, [r7, #4] + 800d68e: 00db lsls r3, r3, #3 + 800d690: 4a08 ldr r2, [pc, #32] ; (800d6b4 ) + 800d692: 4413 add r3, r2 + 800d694: 461a mov r2, r3 + 800d696: 4908 ldr r1, [pc, #32] ; (800d6b8 ) + 800d698: f000 f810 bl 800d6bc + for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { + 800d69c: 687b ldr r3, [r7, #4] + 800d69e: 3301 adds r3, #1 + 800d6a0: 607b str r3, [r7, #4] + 800d6a2: 687b ldr r3, [r7, #4] + 800d6a4: 2b02 cmp r3, #2 + 800d6a6: d9ed bls.n 800d684 + } +} + 800d6a8: bf00 nop + 800d6aa: bf00 nop + 800d6ac: 3708 adds r7, #8 + 800d6ae: 46bd mov sp, r7 + 800d6b0: bd80 pop {r7, pc} + 800d6b2: bf00 nop + 800d6b4: 08014d7c .word 0x08014d7c + 800d6b8: 0800d615 .word 0x0800d615 + +0800d6bc : +sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +void +sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg) +#endif /* LWIP_DEBUG_TIMERNAMES */ +{ + 800d6bc: b580 push {r7, lr} + 800d6be: b086 sub sp, #24 + 800d6c0: af00 add r7, sp, #0 + 800d6c2: 60f8 str r0, [r7, #12] + 800d6c4: 60b9 str r1, [r7, #8] + 800d6c6: 607a str r2, [r7, #4] + u32_t next_timeout_time; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4)); + 800d6c8: 68fb ldr r3, [r7, #12] + 800d6ca: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 800d6ce: d306 bcc.n 800d6de + 800d6d0: 4b0a ldr r3, [pc, #40] ; (800d6fc ) + 800d6d2: f240 1229 movw r2, #297 ; 0x129 + 800d6d6: 490a ldr r1, [pc, #40] ; (800d700 ) + 800d6d8: 480a ldr r0, [pc, #40] ; (800d704 ) + 800d6da: f003 fa75 bl 8010bc8 + + next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */ + 800d6de: f7f7 fce7 bl 80050b0 + 800d6e2: 4602 mov r2, r0 + 800d6e4: 68fb ldr r3, [r7, #12] + 800d6e6: 4413 add r3, r2 + 800d6e8: 617b str r3, [r7, #20] + +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs(next_timeout_time, handler, arg, handler_name); +#else + sys_timeout_abs(next_timeout_time, handler, arg); + 800d6ea: 687a ldr r2, [r7, #4] + 800d6ec: 68b9 ldr r1, [r7, #8] + 800d6ee: 6978 ldr r0, [r7, #20] + 800d6f0: f7ff ff22 bl 800d538 +#endif +} + 800d6f4: bf00 nop + 800d6f6: 3718 adds r7, #24 + 800d6f8: 46bd mov sp, r7 + 800d6fa: bd80 pop {r7, pc} + 800d6fc: 08013e90 .word 0x08013e90 + 800d700: 08013f2c .word 0x08013f2c + 800d704: 08013f04 .word 0x08013f04 + +0800d708 : + * + * Must be called periodically from your main loop. + */ +void +sys_check_timeouts(void) +{ + 800d708: b580 push {r7, lr} + 800d70a: b084 sub sp, #16 + 800d70c: af00 add r7, sp, #0 + u32_t now; + + LWIP_ASSERT_CORE_LOCKED(); + + /* Process only timers expired at the start of the function. */ + now = sys_now(); + 800d70e: f7f7 fccf bl 80050b0 + 800d712: 60f8 str r0, [r7, #12] + do { + struct sys_timeo *tmptimeout; + sys_timeout_handler handler; + void *arg; + + PBUF_CHECK_FREE_OOSEQ(); + 800d714: 4b1a ldr r3, [pc, #104] ; (800d780 ) + 800d716: 781b ldrb r3, [r3, #0] + 800d718: b2db uxtb r3, r3 + 800d71a: 2b00 cmp r3, #0 + 800d71c: d001 beq.n 800d722 + 800d71e: f7f9 f91f bl 8006960 + + tmptimeout = next_timeout; + 800d722: 4b18 ldr r3, [pc, #96] ; (800d784 ) + 800d724: 681b ldr r3, [r3, #0] + 800d726: 60bb str r3, [r7, #8] + if (tmptimeout == NULL) { + 800d728: 68bb ldr r3, [r7, #8] + 800d72a: 2b00 cmp r3, #0 + 800d72c: d022 beq.n 800d774 + return; + } + + if (TIME_LESS_THAN(now, tmptimeout->time)) { + 800d72e: 68bb ldr r3, [r7, #8] + 800d730: 685b ldr r3, [r3, #4] + 800d732: 68fa ldr r2, [r7, #12] + 800d734: 1ad3 subs r3, r2, r3 + 800d736: 0fdb lsrs r3, r3, #31 + 800d738: f003 0301 and.w r3, r3, #1 + 800d73c: b2db uxtb r3, r3 + 800d73e: 2b00 cmp r3, #0 + 800d740: d11a bne.n 800d778 + return; + } + + /* Timeout has expired */ + next_timeout = tmptimeout->next; + 800d742: 68bb ldr r3, [r7, #8] + 800d744: 681b ldr r3, [r3, #0] + 800d746: 4a0f ldr r2, [pc, #60] ; (800d784 ) + 800d748: 6013 str r3, [r2, #0] + handler = tmptimeout->h; + 800d74a: 68bb ldr r3, [r7, #8] + 800d74c: 689b ldr r3, [r3, #8] + 800d74e: 607b str r3, [r7, #4] + arg = tmptimeout->arg; + 800d750: 68bb ldr r3, [r7, #8] + 800d752: 68db ldr r3, [r3, #12] + 800d754: 603b str r3, [r7, #0] + current_timeout_due_time = tmptimeout->time; + 800d756: 68bb ldr r3, [r7, #8] + 800d758: 685b ldr r3, [r3, #4] + 800d75a: 4a0b ldr r2, [pc, #44] ; (800d788 ) + 800d75c: 6013 str r3, [r2, #0] + if (handler != NULL) { + LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n", + tmptimeout->handler_name, sys_now() - tmptimeout->time, arg)); + } +#endif /* LWIP_DEBUG_TIMERNAMES */ + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + 800d75e: 68b9 ldr r1, [r7, #8] + 800d760: 2006 movs r0, #6 + 800d762: f7f8 fccb bl 80060fc + if (handler != NULL) { + 800d766: 687b ldr r3, [r7, #4] + 800d768: 2b00 cmp r3, #0 + 800d76a: d0d3 beq.n 800d714 + handler(arg); + 800d76c: 687b ldr r3, [r7, #4] + 800d76e: 6838 ldr r0, [r7, #0] + 800d770: 4798 blx r3 + do { + 800d772: e7cf b.n 800d714 + return; + 800d774: bf00 nop + 800d776: e000 b.n 800d77a + return; + 800d778: bf00 nop + } + LWIP_TCPIP_THREAD_ALIVE(); + + /* Repeat until all expired timers have been called */ + } while (1); +} + 800d77a: 3710 adds r7, #16 + 800d77c: 46bd mov sp, r7 + 800d77e: bd80 pop {r7, pc} + 800d780: 24007b69 .word 0x24007b69 + 800d784: 24007bc0 .word 0x24007bc0 + 800d788: 24007bc4 .word 0x24007bc4 + +0800d78c : +/** + * Initialize this module. + */ +void +udp_init(void) +{ + 800d78c: b580 push {r7, lr} + 800d78e: af00 add r7, sp, #0 +#ifdef LWIP_RAND + udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); + 800d790: f002 fd66 bl 8010260 + 800d794: 4603 mov r3, r0 + 800d796: b29b uxth r3, r3 + 800d798: f3c3 030d ubfx r3, r3, #0, #14 + 800d79c: b29b uxth r3, r3 + 800d79e: f5a3 4380 sub.w r3, r3, #16384 ; 0x4000 + 800d7a2: b29a uxth r2, r3 + 800d7a4: 4b01 ldr r3, [pc, #4] ; (800d7ac ) + 800d7a6: 801a strh r2, [r3, #0] +#endif /* LWIP_RAND */ +} + 800d7a8: bf00 nop + 800d7aa: bd80 pop {r7, pc} + 800d7ac: 24000070 .word 0x24000070 + +0800d7b0 : + * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4) + * @return 1 on match, 0 otherwise + */ +static u8_t +udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast) +{ + 800d7b0: b580 push {r7, lr} + 800d7b2: b084 sub sp, #16 + 800d7b4: af00 add r7, sp, #0 + 800d7b6: 60f8 str r0, [r7, #12] + 800d7b8: 60b9 str r1, [r7, #8] + 800d7ba: 4613 mov r3, r2 + 800d7bc: 71fb strb r3, [r7, #7] + LWIP_UNUSED_ARG(inp); /* in IPv6 only case */ + LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */ + + LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL); + 800d7be: 68fb ldr r3, [r7, #12] + 800d7c0: 2b00 cmp r3, #0 + 800d7c2: d105 bne.n 800d7d0 + 800d7c4: 4b27 ldr r3, [pc, #156] ; (800d864 ) + 800d7c6: 2287 movs r2, #135 ; 0x87 + 800d7c8: 4927 ldr r1, [pc, #156] ; (800d868 ) + 800d7ca: 4828 ldr r0, [pc, #160] ; (800d86c ) + 800d7cc: f003 f9fc bl 8010bc8 + LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL); + 800d7d0: 68bb ldr r3, [r7, #8] + 800d7d2: 2b00 cmp r3, #0 + 800d7d4: d105 bne.n 800d7e2 + 800d7d6: 4b23 ldr r3, [pc, #140] ; (800d864 ) + 800d7d8: 2288 movs r2, #136 ; 0x88 + 800d7da: 4925 ldr r1, [pc, #148] ; (800d870 ) + 800d7dc: 4823 ldr r0, [pc, #140] ; (800d86c ) + 800d7de: f003 f9f3 bl 8010bc8 + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 800d7e2: 68fb ldr r3, [r7, #12] + 800d7e4: 7a1b ldrb r3, [r3, #8] + 800d7e6: 2b00 cmp r3, #0 + 800d7e8: d00b beq.n 800d802 + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + 800d7ea: 68fb ldr r3, [r7, #12] + 800d7ec: 7a1a ldrb r2, [r3, #8] + 800d7ee: 4b21 ldr r3, [pc, #132] ; (800d874 ) + 800d7f0: 685b ldr r3, [r3, #4] + 800d7f2: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 800d7f6: 3301 adds r3, #1 + 800d7f8: b2db uxtb r3, r3 + if ((pcb->netif_idx != NETIF_NO_INDEX) && + 800d7fa: 429a cmp r2, r3 + 800d7fc: d001 beq.n 800d802 + return 0; + 800d7fe: 2300 movs r3, #0 + 800d800: e02b b.n 800d85a + /* Only need to check PCB if incoming IP version matches PCB IP version */ + if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) { +#if LWIP_IPV4 + /* Special case: IPv4 broadcast: all or broadcasts in my subnet + * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */ + if (broadcast != 0) { + 800d802: 79fb ldrb r3, [r7, #7] + 800d804: 2b00 cmp r3, #0 + 800d806: d018 beq.n 800d83a +#if IP_SOF_BROADCAST_RECV + if (ip_get_option(pcb, SOF_BROADCAST)) +#endif /* IP_SOF_BROADCAST_RECV */ + { + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + 800d808: 68fb ldr r3, [r7, #12] + 800d80a: 2b00 cmp r3, #0 + 800d80c: d013 beq.n 800d836 + 800d80e: 68fb ldr r3, [r7, #12] + 800d810: 681b ldr r3, [r3, #0] + 800d812: 2b00 cmp r3, #0 + 800d814: d00f beq.n 800d836 + ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || + 800d816: 4b17 ldr r3, [pc, #92] ; (800d874 ) + 800d818: 695b ldr r3, [r3, #20] + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + 800d81a: f1b3 3fff cmp.w r3, #4294967295 + 800d81e: d00a beq.n 800d836 + ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) { + 800d820: 68fb ldr r3, [r7, #12] + 800d822: 681a ldr r2, [r3, #0] + 800d824: 4b13 ldr r3, [pc, #76] ; (800d874 ) + 800d826: 695b ldr r3, [r3, #20] + 800d828: 405a eors r2, r3 + 800d82a: 68bb ldr r3, [r7, #8] + 800d82c: 3308 adds r3, #8 + 800d82e: 681b ldr r3, [r3, #0] + 800d830: 4013 ands r3, r2 + ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || + 800d832: 2b00 cmp r3, #0 + 800d834: d110 bne.n 800d858 + return 1; + 800d836: 2301 movs r3, #1 + 800d838: e00f b.n 800d85a + } + } + } else +#endif /* LWIP_IPV4 */ + /* Handle IPv4 and IPv6: all or exact match */ + if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + 800d83a: 68fb ldr r3, [r7, #12] + 800d83c: 2b00 cmp r3, #0 + 800d83e: d009 beq.n 800d854 + 800d840: 68fb ldr r3, [r7, #12] + 800d842: 681b ldr r3, [r3, #0] + 800d844: 2b00 cmp r3, #0 + 800d846: d005 beq.n 800d854 + 800d848: 68fb ldr r3, [r7, #12] + 800d84a: 681a ldr r2, [r3, #0] + 800d84c: 4b09 ldr r3, [pc, #36] ; (800d874 ) + 800d84e: 695b ldr r3, [r3, #20] + 800d850: 429a cmp r2, r3 + 800d852: d101 bne.n 800d858 + return 1; + 800d854: 2301 movs r3, #1 + 800d856: e000 b.n 800d85a + } + } + + return 0; + 800d858: 2300 movs r3, #0 +} + 800d85a: 4618 mov r0, r3 + 800d85c: 3710 adds r7, #16 + 800d85e: 46bd mov sp, r7 + 800d860: bd80 pop {r7, pc} + 800d862: bf00 nop + 800d864: 08013f78 .word 0x08013f78 + 800d868: 08013fa8 .word 0x08013fa8 + 800d86c: 08013fcc .word 0x08013fcc + 800d870: 08013ff4 .word 0x08013ff4 + 800d874: 24004c10 .word 0x24004c10 + +0800d878 : + * @param inp network interface on which the datagram was received. + * + */ +void +udp_input(struct pbuf *p, struct netif *inp) +{ + 800d878: b590 push {r4, r7, lr} + 800d87a: b08d sub sp, #52 ; 0x34 + 800d87c: af02 add r7, sp, #8 + 800d87e: 6078 str r0, [r7, #4] + 800d880: 6039 str r1, [r7, #0] + struct udp_hdr *udphdr; + struct udp_pcb *pcb, *prev; + struct udp_pcb *uncon_pcb; + u16_t src, dest; + u8_t broadcast; + u8_t for_us = 0; + 800d882: 2300 movs r3, #0 + 800d884: 77fb strb r3, [r7, #31] + + LWIP_UNUSED_ARG(inp); + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("udp_input: invalid pbuf", p != NULL); + 800d886: 687b ldr r3, [r7, #4] + 800d888: 2b00 cmp r3, #0 + 800d88a: d105 bne.n 800d898 + 800d88c: 4b7c ldr r3, [pc, #496] ; (800da80 ) + 800d88e: 22cf movs r2, #207 ; 0xcf + 800d890: 497c ldr r1, [pc, #496] ; (800da84 ) + 800d892: 487d ldr r0, [pc, #500] ; (800da88 ) + 800d894: f003 f998 bl 8010bc8 + LWIP_ASSERT("udp_input: invalid netif", inp != NULL); + 800d898: 683b ldr r3, [r7, #0] + 800d89a: 2b00 cmp r3, #0 + 800d89c: d105 bne.n 800d8aa + 800d89e: 4b78 ldr r3, [pc, #480] ; (800da80 ) + 800d8a0: 22d0 movs r2, #208 ; 0xd0 + 800d8a2: 497a ldr r1, [pc, #488] ; (800da8c ) + 800d8a4: 4878 ldr r0, [pc, #480] ; (800da88 ) + 800d8a6: f003 f98f bl 8010bc8 + PERF_START; + + UDP_STATS_INC(udp.recv); + + /* Check minimum length (UDP header) */ + if (p->len < UDP_HLEN) { + 800d8aa: 687b ldr r3, [r7, #4] + 800d8ac: 895b ldrh r3, [r3, #10] + 800d8ae: 2b07 cmp r3, #7 + 800d8b0: d803 bhi.n 800d8ba + LWIP_DEBUGF(UDP_DEBUG, + ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + 800d8b2: 6878 ldr r0, [r7, #4] + 800d8b4: f7f9 fb8e bl 8006fd4 + goto end; + 800d8b8: e0de b.n 800da78 + } + + udphdr = (struct udp_hdr *)p->payload; + 800d8ba: 687b ldr r3, [r7, #4] + 800d8bc: 685b ldr r3, [r3, #4] + 800d8be: 617b str r3, [r7, #20] + + /* is broadcast packet ? */ + broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()); + 800d8c0: 4b73 ldr r3, [pc, #460] ; (800da90 ) + 800d8c2: 695b ldr r3, [r3, #20] + 800d8c4: 4a72 ldr r2, [pc, #456] ; (800da90 ) + 800d8c6: 6812 ldr r2, [r2, #0] + 800d8c8: 4611 mov r1, r2 + 800d8ca: 4618 mov r0, r3 + 800d8cc: f001 fd72 bl 800f3b4 + 800d8d0: 4603 mov r3, r0 + 800d8d2: 74fb strb r3, [r7, #19] + + LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); + + /* convert src and dest ports to host byte order */ + src = lwip_ntohs(udphdr->src); + 800d8d4: 697b ldr r3, [r7, #20] + 800d8d6: 881b ldrh r3, [r3, #0] + 800d8d8: b29b uxth r3, r3 + 800d8da: 4618 mov r0, r3 + 800d8dc: f7f7 fe36 bl 800554c + 800d8e0: 4603 mov r3, r0 + 800d8e2: 823b strh r3, [r7, #16] + dest = lwip_ntohs(udphdr->dest); + 800d8e4: 697b ldr r3, [r7, #20] + 800d8e6: 885b ldrh r3, [r3, #2] + 800d8e8: b29b uxth r3, r3 + 800d8ea: 4618 mov r0, r3 + 800d8ec: f7f7 fe2e bl 800554c + 800d8f0: 4603 mov r3, r0 + 800d8f2: 81fb strh r3, [r7, #14] + ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr()); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest))); + ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr()); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src))); + + pcb = NULL; + 800d8f4: 2300 movs r3, #0 + 800d8f6: 623b str r3, [r7, #32] + prev = NULL; + 800d8f8: 2300 movs r3, #0 + 800d8fa: 627b str r3, [r7, #36] ; 0x24 + uncon_pcb = NULL; + 800d8fc: 2300 movs r3, #0 + 800d8fe: 61bb str r3, [r7, #24] + /* Iterate through the UDP pcb list for a matching pcb. + * 'Perfect match' pcbs (connected to the remote port & ip address) are + * preferred. If no perfect match is found, the first unconnected pcb that + * matches the local port and ip address gets the datagram. */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + 800d900: 4b64 ldr r3, [pc, #400] ; (800da94 ) + 800d902: 681b ldr r3, [r3, #0] + 800d904: 623b str r3, [r7, #32] + 800d906: e054 b.n 800d9b2 + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port)); + ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port)); + + /* compare PCB local addr+port to UDP destination addr+port */ + if ((pcb->local_port == dest) && + 800d908: 6a3b ldr r3, [r7, #32] + 800d90a: 8a5b ldrh r3, [r3, #18] + 800d90c: 89fa ldrh r2, [r7, #14] + 800d90e: 429a cmp r2, r3 + 800d910: d14a bne.n 800d9a8 + (udp_input_local_match(pcb, inp, broadcast) != 0)) { + 800d912: 7cfb ldrb r3, [r7, #19] + 800d914: 461a mov r2, r3 + 800d916: 6839 ldr r1, [r7, #0] + 800d918: 6a38 ldr r0, [r7, #32] + 800d91a: f7ff ff49 bl 800d7b0 + 800d91e: 4603 mov r3, r0 + if ((pcb->local_port == dest) && + 800d920: 2b00 cmp r3, #0 + 800d922: d041 beq.n 800d9a8 + if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) { + 800d924: 6a3b ldr r3, [r7, #32] + 800d926: 7c1b ldrb r3, [r3, #16] + 800d928: f003 0304 and.w r3, r3, #4 + 800d92c: 2b00 cmp r3, #0 + 800d92e: d11d bne.n 800d96c + if (uncon_pcb == NULL) { + 800d930: 69bb ldr r3, [r7, #24] + 800d932: 2b00 cmp r3, #0 + 800d934: d102 bne.n 800d93c + /* the first unconnected matching PCB */ + uncon_pcb = pcb; + 800d936: 6a3b ldr r3, [r7, #32] + 800d938: 61bb str r3, [r7, #24] + 800d93a: e017 b.n 800d96c +#if LWIP_IPV4 + } else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) { + 800d93c: 7cfb ldrb r3, [r7, #19] + 800d93e: 2b00 cmp r3, #0 + 800d940: d014 beq.n 800d96c + 800d942: 4b53 ldr r3, [pc, #332] ; (800da90 ) + 800d944: 695b ldr r3, [r3, #20] + 800d946: f1b3 3fff cmp.w r3, #4294967295 + 800d94a: d10f bne.n 800d96c + /* global broadcast address (only valid for IPv4; match was checked before) */ + if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) { + 800d94c: 69bb ldr r3, [r7, #24] + 800d94e: 681a ldr r2, [r3, #0] + 800d950: 683b ldr r3, [r7, #0] + 800d952: 3304 adds r3, #4 + 800d954: 681b ldr r3, [r3, #0] + 800d956: 429a cmp r2, r3 + 800d958: d008 beq.n 800d96c + /* uncon_pcb does not match the input netif, check this pcb */ + if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) { + 800d95a: 6a3b ldr r3, [r7, #32] + 800d95c: 681a ldr r2, [r3, #0] + 800d95e: 683b ldr r3, [r7, #0] + 800d960: 3304 adds r3, #4 + 800d962: 681b ldr r3, [r3, #0] + 800d964: 429a cmp r2, r3 + 800d966: d101 bne.n 800d96c + /* better match */ + uncon_pcb = pcb; + 800d968: 6a3b ldr r3, [r7, #32] + 800d96a: 61bb str r3, [r7, #24] + } +#endif /* SO_REUSE */ + } + + /* compare PCB remote addr+port to UDP source addr+port */ + if ((pcb->remote_port == src) && + 800d96c: 6a3b ldr r3, [r7, #32] + 800d96e: 8a9b ldrh r3, [r3, #20] + 800d970: 8a3a ldrh r2, [r7, #16] + 800d972: 429a cmp r2, r3 + 800d974: d118 bne.n 800d9a8 + (ip_addr_isany_val(pcb->remote_ip) || + 800d976: 6a3b ldr r3, [r7, #32] + 800d978: 685b ldr r3, [r3, #4] + if ((pcb->remote_port == src) && + 800d97a: 2b00 cmp r3, #0 + 800d97c: d005 beq.n 800d98a + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) { + 800d97e: 6a3b ldr r3, [r7, #32] + 800d980: 685a ldr r2, [r3, #4] + 800d982: 4b43 ldr r3, [pc, #268] ; (800da90 ) + 800d984: 691b ldr r3, [r3, #16] + (ip_addr_isany_val(pcb->remote_ip) || + 800d986: 429a cmp r2, r3 + 800d988: d10e bne.n 800d9a8 + /* the first fully matching PCB */ + if (prev != NULL) { + 800d98a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d98c: 2b00 cmp r3, #0 + 800d98e: d014 beq.n 800d9ba + /* move the pcb to the front of udp_pcbs so that is + found faster next time */ + prev->next = pcb->next; + 800d990: 6a3b ldr r3, [r7, #32] + 800d992: 68da ldr r2, [r3, #12] + 800d994: 6a7b ldr r3, [r7, #36] ; 0x24 + 800d996: 60da str r2, [r3, #12] + pcb->next = udp_pcbs; + 800d998: 4b3e ldr r3, [pc, #248] ; (800da94 ) + 800d99a: 681a ldr r2, [r3, #0] + 800d99c: 6a3b ldr r3, [r7, #32] + 800d99e: 60da str r2, [r3, #12] + udp_pcbs = pcb; + 800d9a0: 4a3c ldr r2, [pc, #240] ; (800da94 ) + 800d9a2: 6a3b ldr r3, [r7, #32] + 800d9a4: 6013 str r3, [r2, #0] + } else { + UDP_STATS_INC(udp.cachehit); + } + break; + 800d9a6: e008 b.n 800d9ba + } + } + + prev = pcb; + 800d9a8: 6a3b ldr r3, [r7, #32] + 800d9aa: 627b str r3, [r7, #36] ; 0x24 + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + 800d9ac: 6a3b ldr r3, [r7, #32] + 800d9ae: 68db ldr r3, [r3, #12] + 800d9b0: 623b str r3, [r7, #32] + 800d9b2: 6a3b ldr r3, [r7, #32] + 800d9b4: 2b00 cmp r3, #0 + 800d9b6: d1a7 bne.n 800d908 + 800d9b8: e000 b.n 800d9bc + break; + 800d9ba: bf00 nop + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { + 800d9bc: 6a3b ldr r3, [r7, #32] + 800d9be: 2b00 cmp r3, #0 + 800d9c0: d101 bne.n 800d9c6 + pcb = uncon_pcb; + 800d9c2: 69bb ldr r3, [r7, #24] + 800d9c4: 623b str r3, [r7, #32] + } + + /* Check checksum if this is a match or if it was directed at us. */ + if (pcb != NULL) { + 800d9c6: 6a3b ldr r3, [r7, #32] + 800d9c8: 2b00 cmp r3, #0 + 800d9ca: d002 beq.n 800d9d2 + for_us = 1; + 800d9cc: 2301 movs r3, #1 + 800d9ce: 77fb strb r3, [r7, #31] + 800d9d0: e00a b.n 800d9e8 + for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0; + } +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + if (!ip_current_is_v6()) { + for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr()); + 800d9d2: 683b ldr r3, [r7, #0] + 800d9d4: 3304 adds r3, #4 + 800d9d6: 681a ldr r2, [r3, #0] + 800d9d8: 4b2d ldr r3, [pc, #180] ; (800da90 ) + 800d9da: 695b ldr r3, [r3, #20] + 800d9dc: 429a cmp r2, r3 + 800d9de: bf0c ite eq + 800d9e0: 2301 moveq r3, #1 + 800d9e2: 2300 movne r3, #0 + 800d9e4: b2db uxtb r3, r3 + 800d9e6: 77fb strb r3, [r7, #31] + } +#endif /* LWIP_IPV4 */ + } + + if (for_us) { + 800d9e8: 7ffb ldrb r3, [r7, #31] + 800d9ea: 2b00 cmp r3, #0 + 800d9ec: d041 beq.n 800da72 + } + } + } + } +#endif /* CHECKSUM_CHECK_UDP */ + if (pbuf_remove_header(p, UDP_HLEN)) { + 800d9ee: 2108 movs r1, #8 + 800d9f0: 6878 ldr r0, [r7, #4] + 800d9f2: f7f9 fa69 bl 8006ec8 + 800d9f6: 4603 mov r3, r0 + 800d9f8: 2b00 cmp r3, #0 + 800d9fa: d00a beq.n 800da12 + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + 800d9fc: 4b20 ldr r3, [pc, #128] ; (800da80 ) + 800d9fe: f44f 72b8 mov.w r2, #368 ; 0x170 + 800da02: 4925 ldr r1, [pc, #148] ; (800da98 ) + 800da04: 4820 ldr r0, [pc, #128] ; (800da88 ) + 800da06: f003 f8df bl 8010bc8 + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + 800da0a: 6878 ldr r0, [r7, #4] + 800da0c: f7f9 fae2 bl 8006fd4 + goto end; + 800da10: e032 b.n 800da78 + } + + if (pcb != NULL) { + 800da12: 6a3b ldr r3, [r7, #32] + 800da14: 2b00 cmp r3, #0 + 800da16: d012 beq.n 800da3e + } + } + } +#endif /* SO_REUSE && SO_REUSE_RXTOALL */ + /* callback */ + if (pcb->recv != NULL) { + 800da18: 6a3b ldr r3, [r7, #32] + 800da1a: 699b ldr r3, [r3, #24] + 800da1c: 2b00 cmp r3, #0 + 800da1e: d00a beq.n 800da36 + /* now the recv function is responsible for freeing p */ + pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src); + 800da20: 6a3b ldr r3, [r7, #32] + 800da22: 699c ldr r4, [r3, #24] + 800da24: 6a3b ldr r3, [r7, #32] + 800da26: 69d8 ldr r0, [r3, #28] + 800da28: 8a3b ldrh r3, [r7, #16] + 800da2a: 9300 str r3, [sp, #0] + 800da2c: 4b1b ldr r3, [pc, #108] ; (800da9c ) + 800da2e: 687a ldr r2, [r7, #4] + 800da30: 6a39 ldr r1, [r7, #32] + 800da32: 47a0 blx r4 + } else { + pbuf_free(p); + } +end: + PERF_STOP("udp_input"); + return; + 800da34: e021 b.n 800da7a + pbuf_free(p); + 800da36: 6878 ldr r0, [r7, #4] + 800da38: f7f9 facc bl 8006fd4 + goto end; + 800da3c: e01c b.n 800da78 + if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) { + 800da3e: 7cfb ldrb r3, [r7, #19] + 800da40: 2b00 cmp r3, #0 + 800da42: d112 bne.n 800da6a + 800da44: 4b12 ldr r3, [pc, #72] ; (800da90 ) + 800da46: 695b ldr r3, [r3, #20] + 800da48: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800da4c: 2be0 cmp r3, #224 ; 0xe0 + 800da4e: d00c beq.n 800da6a + pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN)); + 800da50: 4b0f ldr r3, [pc, #60] ; (800da90 ) + 800da52: 899b ldrh r3, [r3, #12] + 800da54: 3308 adds r3, #8 + 800da56: b29b uxth r3, r3 + 800da58: b21b sxth r3, r3 + 800da5a: 4619 mov r1, r3 + 800da5c: 6878 ldr r0, [r7, #4] + 800da5e: f7f9 faa6 bl 8006fae + icmp_port_unreach(ip_current_is_v6(), p); + 800da62: 2103 movs r1, #3 + 800da64: 6878 ldr r0, [r7, #4] + 800da66: f001 f93b bl 800ece0 + pbuf_free(p); + 800da6a: 6878 ldr r0, [r7, #4] + 800da6c: f7f9 fab2 bl 8006fd4 + return; + 800da70: e003 b.n 800da7a + pbuf_free(p); + 800da72: 6878 ldr r0, [r7, #4] + 800da74: f7f9 faae bl 8006fd4 + return; + 800da78: bf00 nop + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + PERF_STOP("udp_input"); +#endif /* CHECKSUM_CHECK_UDP */ +} + 800da7a: 372c adds r7, #44 ; 0x2c + 800da7c: 46bd mov sp, r7 + 800da7e: bd90 pop {r4, r7, pc} + 800da80: 08013f78 .word 0x08013f78 + 800da84: 0801401c .word 0x0801401c + 800da88: 08013fcc .word 0x08013fcc + 800da8c: 08014034 .word 0x08014034 + 800da90: 24004c10 .word 0x24004c10 + 800da94: 24007bcc .word 0x24007bcc + 800da98: 08014050 .word 0x08014050 + 800da9c: 24004c20 .word 0x24004c20 + +0800daa0 : + * + * @param old_addr IP address of the netif before change + * @param new_addr IP address of the netif after change + */ +void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + 800daa0: b480 push {r7} + 800daa2: b085 sub sp, #20 + 800daa4: af00 add r7, sp, #0 + 800daa6: 6078 str r0, [r7, #4] + 800daa8: 6039 str r1, [r7, #0] + struct udp_pcb *upcb; + + if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) { + 800daaa: 687b ldr r3, [r7, #4] + 800daac: 2b00 cmp r3, #0 + 800daae: d01e beq.n 800daee + 800dab0: 687b ldr r3, [r7, #4] + 800dab2: 681b ldr r3, [r3, #0] + 800dab4: 2b00 cmp r3, #0 + 800dab6: d01a beq.n 800daee + 800dab8: 683b ldr r3, [r7, #0] + 800daba: 2b00 cmp r3, #0 + 800dabc: d017 beq.n 800daee + 800dabe: 683b ldr r3, [r7, #0] + 800dac0: 681b ldr r3, [r3, #0] + 800dac2: 2b00 cmp r3, #0 + 800dac4: d013 beq.n 800daee + for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { + 800dac6: 4b0d ldr r3, [pc, #52] ; (800dafc ) + 800dac8: 681b ldr r3, [r3, #0] + 800daca: 60fb str r3, [r7, #12] + 800dacc: e00c b.n 800dae8 + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&upcb->local_ip, old_addr)) { + 800dace: 68fb ldr r3, [r7, #12] + 800dad0: 681a ldr r2, [r3, #0] + 800dad2: 687b ldr r3, [r7, #4] + 800dad4: 681b ldr r3, [r3, #0] + 800dad6: 429a cmp r2, r3 + 800dad8: d103 bne.n 800dae2 + /* The PCB is bound to the old ipaddr and + * is set to bound to the new one instead */ + ip_addr_copy(upcb->local_ip, *new_addr); + 800dada: 683b ldr r3, [r7, #0] + 800dadc: 681a ldr r2, [r3, #0] + 800dade: 68fb ldr r3, [r7, #12] + 800dae0: 601a str r2, [r3, #0] + for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { + 800dae2: 68fb ldr r3, [r7, #12] + 800dae4: 68db ldr r3, [r3, #12] + 800dae6: 60fb str r3, [r7, #12] + 800dae8: 68fb ldr r3, [r7, #12] + 800daea: 2b00 cmp r3, #0 + 800daec: d1ef bne.n 800dace + } + } + } +} + 800daee: bf00 nop + 800daf0: 3714 adds r7, #20 + 800daf2: 46bd mov sp, r7 + 800daf4: f85d 7b04 ldr.w r7, [sp], #4 + 800daf8: 4770 bx lr + 800dafa: bf00 nop + 800dafc: 24007bcc .word 0x24007bcc + +0800db00 : +#endif /* ARP_QUEUEING */ + +/** Clean up ARP table entries */ +static void +etharp_free_entry(int i) +{ + 800db00: b580 push {r7, lr} + 800db02: b082 sub sp, #8 + 800db04: af00 add r7, sp, #0 + 800db06: 6078 str r0, [r7, #4] + /* remove from SNMP ARP index tree */ + mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr); + /* and empty packet queue */ + if (arp_table[i].q != NULL) { + 800db08: 492b ldr r1, [pc, #172] ; (800dbb8 ) + 800db0a: 687a ldr r2, [r7, #4] + 800db0c: 4613 mov r3, r2 + 800db0e: 005b lsls r3, r3, #1 + 800db10: 4413 add r3, r2 + 800db12: 00db lsls r3, r3, #3 + 800db14: 440b add r3, r1 + 800db16: 681b ldr r3, [r3, #0] + 800db18: 2b00 cmp r3, #0 + 800db1a: d013 beq.n 800db44 + /* remove all queued packets */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); + free_etharp_q(arp_table[i].q); + 800db1c: 4926 ldr r1, [pc, #152] ; (800dbb8 ) + 800db1e: 687a ldr r2, [r7, #4] + 800db20: 4613 mov r3, r2 + 800db22: 005b lsls r3, r3, #1 + 800db24: 4413 add r3, r2 + 800db26: 00db lsls r3, r3, #3 + 800db28: 440b add r3, r1 + 800db2a: 681b ldr r3, [r3, #0] + 800db2c: 4618 mov r0, r3 + 800db2e: f7f9 fa51 bl 8006fd4 + arp_table[i].q = NULL; + 800db32: 4921 ldr r1, [pc, #132] ; (800dbb8 ) + 800db34: 687a ldr r2, [r7, #4] + 800db36: 4613 mov r3, r2 + 800db38: 005b lsls r3, r3, #1 + 800db3a: 4413 add r3, r2 + 800db3c: 00db lsls r3, r3, #3 + 800db3e: 440b add r3, r1 + 800db40: 2200 movs r2, #0 + 800db42: 601a str r2, [r3, #0] + } + /* recycle entry for re-use */ + arp_table[i].state = ETHARP_STATE_EMPTY; + 800db44: 491c ldr r1, [pc, #112] ; (800dbb8 ) + 800db46: 687a ldr r2, [r7, #4] + 800db48: 4613 mov r3, r2 + 800db4a: 005b lsls r3, r3, #1 + 800db4c: 4413 add r3, r2 + 800db4e: 00db lsls r3, r3, #3 + 800db50: 440b add r3, r1 + 800db52: 3314 adds r3, #20 + 800db54: 2200 movs r2, #0 + 800db56: 701a strb r2, [r3, #0] +#ifdef LWIP_DEBUG + /* for debugging, clean out the complete entry */ + arp_table[i].ctime = 0; + 800db58: 4917 ldr r1, [pc, #92] ; (800dbb8 ) + 800db5a: 687a ldr r2, [r7, #4] + 800db5c: 4613 mov r3, r2 + 800db5e: 005b lsls r3, r3, #1 + 800db60: 4413 add r3, r2 + 800db62: 00db lsls r3, r3, #3 + 800db64: 440b add r3, r1 + 800db66: 3312 adds r3, #18 + 800db68: 2200 movs r2, #0 + 800db6a: 801a strh r2, [r3, #0] + arp_table[i].netif = NULL; + 800db6c: 4912 ldr r1, [pc, #72] ; (800dbb8 ) + 800db6e: 687a ldr r2, [r7, #4] + 800db70: 4613 mov r3, r2 + 800db72: 005b lsls r3, r3, #1 + 800db74: 4413 add r3, r2 + 800db76: 00db lsls r3, r3, #3 + 800db78: 440b add r3, r1 + 800db7a: 3308 adds r3, #8 + 800db7c: 2200 movs r2, #0 + 800db7e: 601a str r2, [r3, #0] + ip4_addr_set_zero(&arp_table[i].ipaddr); + 800db80: 490d ldr r1, [pc, #52] ; (800dbb8 ) + 800db82: 687a ldr r2, [r7, #4] + 800db84: 4613 mov r3, r2 + 800db86: 005b lsls r3, r3, #1 + 800db88: 4413 add r3, r2 + 800db8a: 00db lsls r3, r3, #3 + 800db8c: 440b add r3, r1 + 800db8e: 3304 adds r3, #4 + 800db90: 2200 movs r2, #0 + 800db92: 601a str r2, [r3, #0] + arp_table[i].ethaddr = ethzero; + 800db94: 4908 ldr r1, [pc, #32] ; (800dbb8 ) + 800db96: 687a ldr r2, [r7, #4] + 800db98: 4613 mov r3, r2 + 800db9a: 005b lsls r3, r3, #1 + 800db9c: 4413 add r3, r2 + 800db9e: 00db lsls r3, r3, #3 + 800dba0: 440b add r3, r1 + 800dba2: 3308 adds r3, #8 + 800dba4: 4a05 ldr r2, [pc, #20] ; (800dbbc ) + 800dba6: 3304 adds r3, #4 + 800dba8: 6810 ldr r0, [r2, #0] + 800dbaa: 6018 str r0, [r3, #0] + 800dbac: 8892 ldrh r2, [r2, #4] + 800dbae: 809a strh r2, [r3, #4] +#endif /* LWIP_DEBUG */ +} + 800dbb0: bf00 nop + 800dbb2: 3708 adds r7, #8 + 800dbb4: 46bd mov sp, r7 + 800dbb6: bd80 pop {r7, pc} + 800dbb8: 24007bd0 .word 0x24007bd0 + 800dbbc: 08014da0 .word 0x08014da0 + +0800dbc0 : + * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second), + * in order to expire entries in the ARP table. + */ +void +etharp_tmr(void) +{ + 800dbc0: b580 push {r7, lr} + 800dbc2: b082 sub sp, #8 + 800dbc4: af00 add r7, sp, #0 + int i; + + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); + /* remove expired entries from the ARP table */ + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 800dbc6: 2300 movs r3, #0 + 800dbc8: 607b str r3, [r7, #4] + 800dbca: e096 b.n 800dcfa + u8_t state = arp_table[i].state; + 800dbcc: 494f ldr r1, [pc, #316] ; (800dd0c ) + 800dbce: 687a ldr r2, [r7, #4] + 800dbd0: 4613 mov r3, r2 + 800dbd2: 005b lsls r3, r3, #1 + 800dbd4: 4413 add r3, r2 + 800dbd6: 00db lsls r3, r3, #3 + 800dbd8: 440b add r3, r1 + 800dbda: 3314 adds r3, #20 + 800dbdc: 781b ldrb r3, [r3, #0] + 800dbde: 70fb strb r3, [r7, #3] + if (state != ETHARP_STATE_EMPTY + 800dbe0: 78fb ldrb r3, [r7, #3] + 800dbe2: 2b00 cmp r3, #0 + 800dbe4: f000 8086 beq.w 800dcf4 +#if ETHARP_SUPPORT_STATIC_ENTRIES + && (state != ETHARP_STATE_STATIC) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + ) { + arp_table[i].ctime++; + 800dbe8: 4948 ldr r1, [pc, #288] ; (800dd0c ) + 800dbea: 687a ldr r2, [r7, #4] + 800dbec: 4613 mov r3, r2 + 800dbee: 005b lsls r3, r3, #1 + 800dbf0: 4413 add r3, r2 + 800dbf2: 00db lsls r3, r3, #3 + 800dbf4: 440b add r3, r1 + 800dbf6: 3312 adds r3, #18 + 800dbf8: 881b ldrh r3, [r3, #0] + 800dbfa: 3301 adds r3, #1 + 800dbfc: b298 uxth r0, r3 + 800dbfe: 4943 ldr r1, [pc, #268] ; (800dd0c ) + 800dc00: 687a ldr r2, [r7, #4] + 800dc02: 4613 mov r3, r2 + 800dc04: 005b lsls r3, r3, #1 + 800dc06: 4413 add r3, r2 + 800dc08: 00db lsls r3, r3, #3 + 800dc0a: 440b add r3, r1 + 800dc0c: 3312 adds r3, #18 + 800dc0e: 4602 mov r2, r0 + 800dc10: 801a strh r2, [r3, #0] + if ((arp_table[i].ctime >= ARP_MAXAGE) || + 800dc12: 493e ldr r1, [pc, #248] ; (800dd0c ) + 800dc14: 687a ldr r2, [r7, #4] + 800dc16: 4613 mov r3, r2 + 800dc18: 005b lsls r3, r3, #1 + 800dc1a: 4413 add r3, r2 + 800dc1c: 00db lsls r3, r3, #3 + 800dc1e: 440b add r3, r1 + 800dc20: 3312 adds r3, #18 + 800dc22: 881b ldrh r3, [r3, #0] + 800dc24: f5b3 7f96 cmp.w r3, #300 ; 0x12c + 800dc28: d215 bcs.n 800dc56 + ((arp_table[i].state == ETHARP_STATE_PENDING) && + 800dc2a: 4938 ldr r1, [pc, #224] ; (800dd0c ) + 800dc2c: 687a ldr r2, [r7, #4] + 800dc2e: 4613 mov r3, r2 + 800dc30: 005b lsls r3, r3, #1 + 800dc32: 4413 add r3, r2 + 800dc34: 00db lsls r3, r3, #3 + 800dc36: 440b add r3, r1 + 800dc38: 3314 adds r3, #20 + 800dc3a: 781b ldrb r3, [r3, #0] + if ((arp_table[i].ctime >= ARP_MAXAGE) || + 800dc3c: 2b01 cmp r3, #1 + 800dc3e: d10e bne.n 800dc5e + (arp_table[i].ctime >= ARP_MAXPENDING))) { + 800dc40: 4932 ldr r1, [pc, #200] ; (800dd0c ) + 800dc42: 687a ldr r2, [r7, #4] + 800dc44: 4613 mov r3, r2 + 800dc46: 005b lsls r3, r3, #1 + 800dc48: 4413 add r3, r2 + 800dc4a: 00db lsls r3, r3, #3 + 800dc4c: 440b add r3, r1 + 800dc4e: 3312 adds r3, #18 + 800dc50: 881b ldrh r3, [r3, #0] + ((arp_table[i].state == ETHARP_STATE_PENDING) && + 800dc52: 2b04 cmp r3, #4 + 800dc54: d903 bls.n 800dc5e + /* pending or stable entry has become old! */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n", + arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i)); + /* clean up entries that have just been expired */ + etharp_free_entry(i); + 800dc56: 6878 ldr r0, [r7, #4] + 800dc58: f7ff ff52 bl 800db00 + 800dc5c: e04a b.n 800dcf4 + } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) { + 800dc5e: 492b ldr r1, [pc, #172] ; (800dd0c ) + 800dc60: 687a ldr r2, [r7, #4] + 800dc62: 4613 mov r3, r2 + 800dc64: 005b lsls r3, r3, #1 + 800dc66: 4413 add r3, r2 + 800dc68: 00db lsls r3, r3, #3 + 800dc6a: 440b add r3, r1 + 800dc6c: 3314 adds r3, #20 + 800dc6e: 781b ldrb r3, [r3, #0] + 800dc70: 2b03 cmp r3, #3 + 800dc72: d10a bne.n 800dc8a + /* Don't send more than one request every 2 seconds. */ + arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2; + 800dc74: 4925 ldr r1, [pc, #148] ; (800dd0c ) + 800dc76: 687a ldr r2, [r7, #4] + 800dc78: 4613 mov r3, r2 + 800dc7a: 005b lsls r3, r3, #1 + 800dc7c: 4413 add r3, r2 + 800dc7e: 00db lsls r3, r3, #3 + 800dc80: 440b add r3, r1 + 800dc82: 3314 adds r3, #20 + 800dc84: 2204 movs r2, #4 + 800dc86: 701a strb r2, [r3, #0] + 800dc88: e034 b.n 800dcf4 + } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) { + 800dc8a: 4920 ldr r1, [pc, #128] ; (800dd0c ) + 800dc8c: 687a ldr r2, [r7, #4] + 800dc8e: 4613 mov r3, r2 + 800dc90: 005b lsls r3, r3, #1 + 800dc92: 4413 add r3, r2 + 800dc94: 00db lsls r3, r3, #3 + 800dc96: 440b add r3, r1 + 800dc98: 3314 adds r3, #20 + 800dc9a: 781b ldrb r3, [r3, #0] + 800dc9c: 2b04 cmp r3, #4 + 800dc9e: d10a bne.n 800dcb6 + /* Reset state to stable, so that the next transmitted packet will + re-send an ARP request. */ + arp_table[i].state = ETHARP_STATE_STABLE; + 800dca0: 491a ldr r1, [pc, #104] ; (800dd0c ) + 800dca2: 687a ldr r2, [r7, #4] + 800dca4: 4613 mov r3, r2 + 800dca6: 005b lsls r3, r3, #1 + 800dca8: 4413 add r3, r2 + 800dcaa: 00db lsls r3, r3, #3 + 800dcac: 440b add r3, r1 + 800dcae: 3314 adds r3, #20 + 800dcb0: 2202 movs r2, #2 + 800dcb2: 701a strb r2, [r3, #0] + 800dcb4: e01e b.n 800dcf4 + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + 800dcb6: 4915 ldr r1, [pc, #84] ; (800dd0c ) + 800dcb8: 687a ldr r2, [r7, #4] + 800dcba: 4613 mov r3, r2 + 800dcbc: 005b lsls r3, r3, #1 + 800dcbe: 4413 add r3, r2 + 800dcc0: 00db lsls r3, r3, #3 + 800dcc2: 440b add r3, r1 + 800dcc4: 3314 adds r3, #20 + 800dcc6: 781b ldrb r3, [r3, #0] + 800dcc8: 2b01 cmp r3, #1 + 800dcca: d113 bne.n 800dcf4 + /* still pending, resend an ARP query */ + etharp_request(arp_table[i].netif, &arp_table[i].ipaddr); + 800dccc: 490f ldr r1, [pc, #60] ; (800dd0c ) + 800dcce: 687a ldr r2, [r7, #4] + 800dcd0: 4613 mov r3, r2 + 800dcd2: 005b lsls r3, r3, #1 + 800dcd4: 4413 add r3, r2 + 800dcd6: 00db lsls r3, r3, #3 + 800dcd8: 440b add r3, r1 + 800dcda: 3308 adds r3, #8 + 800dcdc: 6818 ldr r0, [r3, #0] + 800dcde: 687a ldr r2, [r7, #4] + 800dce0: 4613 mov r3, r2 + 800dce2: 005b lsls r3, r3, #1 + 800dce4: 4413 add r3, r2 + 800dce6: 00db lsls r3, r3, #3 + 800dce8: 4a08 ldr r2, [pc, #32] ; (800dd0c ) + 800dcea: 4413 add r3, r2 + 800dcec: 3304 adds r3, #4 + 800dcee: 4619 mov r1, r3 + 800dcf0: f000 fe6e bl 800e9d0 + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 800dcf4: 687b ldr r3, [r7, #4] + 800dcf6: 3301 adds r3, #1 + 800dcf8: 607b str r3, [r7, #4] + 800dcfa: 687b ldr r3, [r7, #4] + 800dcfc: 2b09 cmp r3, #9 + 800dcfe: f77f af65 ble.w 800dbcc + } + } + } +} + 800dd02: bf00 nop + 800dd04: bf00 nop + 800dd06: 3708 adds r7, #8 + 800dd08: 46bd mov sp, r7 + 800dd0a: bd80 pop {r7, pc} + 800dd0c: 24007bd0 .word 0x24007bd0 + +0800dd10 : + * @return The ARP entry index that matched or is created, ERR_MEM if no + * entry is found or could be recycled. + */ +static s16_t +etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif) +{ + 800dd10: b580 push {r7, lr} + 800dd12: b08a sub sp, #40 ; 0x28 + 800dd14: af00 add r7, sp, #0 + 800dd16: 60f8 str r0, [r7, #12] + 800dd18: 460b mov r3, r1 + 800dd1a: 607a str r2, [r7, #4] + 800dd1c: 72fb strb r3, [r7, #11] + s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; + 800dd1e: 230a movs r3, #10 + 800dd20: 843b strh r3, [r7, #32] + 800dd22: 230a movs r3, #10 + 800dd24: 847b strh r3, [r7, #34] ; 0x22 + s16_t empty = ARP_TABLE_SIZE; + 800dd26: 230a movs r3, #10 + 800dd28: 84bb strh r3, [r7, #36] ; 0x24 + s16_t i = 0; + 800dd2a: 2300 movs r3, #0 + 800dd2c: 84fb strh r3, [r7, #38] ; 0x26 + /* oldest entry with packets on queue */ + s16_t old_queue = ARP_TABLE_SIZE; + 800dd2e: 230a movs r3, #10 + 800dd30: 83fb strh r3, [r7, #30] + /* its age */ + u16_t age_queue = 0, age_pending = 0, age_stable = 0; + 800dd32: 2300 movs r3, #0 + 800dd34: 83bb strh r3, [r7, #28] + 800dd36: 2300 movs r3, #0 + 800dd38: 837b strh r3, [r7, #26] + 800dd3a: 2300 movs r3, #0 + 800dd3c: 833b strh r3, [r7, #24] + * 4) remember the oldest pending entry with queued packets (if any) + * 5) search for a matching IP entry, either pending or stable + * until 5 matches, or all entries are searched for. + */ + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 800dd3e: 2300 movs r3, #0 + 800dd40: 84fb strh r3, [r7, #38] ; 0x26 + 800dd42: e0ae b.n 800dea2 + u8_t state = arp_table[i].state; + 800dd44: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800dd48: 49a6 ldr r1, [pc, #664] ; (800dfe4 ) + 800dd4a: 4613 mov r3, r2 + 800dd4c: 005b lsls r3, r3, #1 + 800dd4e: 4413 add r3, r2 + 800dd50: 00db lsls r3, r3, #3 + 800dd52: 440b add r3, r1 + 800dd54: 3314 adds r3, #20 + 800dd56: 781b ldrb r3, [r3, #0] + 800dd58: 75fb strb r3, [r7, #23] + /* no empty entry found yet and now we do find one? */ + if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) { + 800dd5a: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24 + 800dd5e: 2b0a cmp r3, #10 + 800dd60: d105 bne.n 800dd6e + 800dd62: 7dfb ldrb r3, [r7, #23] + 800dd64: 2b00 cmp r3, #0 + 800dd66: d102 bne.n 800dd6e + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i)); + /* remember first empty entry */ + empty = i; + 800dd68: 8cfb ldrh r3, [r7, #38] ; 0x26 + 800dd6a: 84bb strh r3, [r7, #36] ; 0x24 + 800dd6c: e095 b.n 800de9a + } else if (state != ETHARP_STATE_EMPTY) { + 800dd6e: 7dfb ldrb r3, [r7, #23] + 800dd70: 2b00 cmp r3, #0 + 800dd72: f000 8092 beq.w 800de9a + LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE", + 800dd76: 7dfb ldrb r3, [r7, #23] + 800dd78: 2b01 cmp r3, #1 + 800dd7a: d009 beq.n 800dd90 + 800dd7c: 7dfb ldrb r3, [r7, #23] + 800dd7e: 2b01 cmp r3, #1 + 800dd80: d806 bhi.n 800dd90 + 800dd82: 4b99 ldr r3, [pc, #612] ; (800dfe8 ) + 800dd84: f240 1223 movw r2, #291 ; 0x123 + 800dd88: 4998 ldr r1, [pc, #608] ; (800dfec ) + 800dd8a: 4899 ldr r0, [pc, #612] ; (800dff0 ) + 800dd8c: f002 ff1c bl 8010bc8 + state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE); + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr) + 800dd90: 68fb ldr r3, [r7, #12] + 800dd92: 2b00 cmp r3, #0 + 800dd94: d020 beq.n 800ddd8 + 800dd96: 68fb ldr r3, [r7, #12] + 800dd98: 6819 ldr r1, [r3, #0] + 800dd9a: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800dd9e: 4891 ldr r0, [pc, #580] ; (800dfe4 ) + 800dda0: 4613 mov r3, r2 + 800dda2: 005b lsls r3, r3, #1 + 800dda4: 4413 add r3, r2 + 800dda6: 00db lsls r3, r3, #3 + 800dda8: 4403 add r3, r0 + 800ddaa: 3304 adds r3, #4 + 800ddac: 681b ldr r3, [r3, #0] + 800ddae: 4299 cmp r1, r3 + 800ddb0: d112 bne.n 800ddd8 +#if ETHARP_TABLE_MATCH_NETIF + && ((netif == NULL) || (netif == arp_table[i].netif)) + 800ddb2: 687b ldr r3, [r7, #4] + 800ddb4: 2b00 cmp r3, #0 + 800ddb6: d00c beq.n 800ddd2 + 800ddb8: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800ddbc: 4989 ldr r1, [pc, #548] ; (800dfe4 ) + 800ddbe: 4613 mov r3, r2 + 800ddc0: 005b lsls r3, r3, #1 + 800ddc2: 4413 add r3, r2 + 800ddc4: 00db lsls r3, r3, #3 + 800ddc6: 440b add r3, r1 + 800ddc8: 3308 adds r3, #8 + 800ddca: 681b ldr r3, [r3, #0] + 800ddcc: 687a ldr r2, [r7, #4] + 800ddce: 429a cmp r2, r3 + 800ddd0: d102 bne.n 800ddd8 +#endif /* ETHARP_TABLE_MATCH_NETIF */ + ) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i)); + /* found exact IP address match, simply bail out */ + return i; + 800ddd2: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 + 800ddd6: e100 b.n 800dfda + } + /* pending entry? */ + if (state == ETHARP_STATE_PENDING) { + 800ddd8: 7dfb ldrb r3, [r7, #23] + 800ddda: 2b01 cmp r3, #1 + 800dddc: d140 bne.n 800de60 + /* pending with queued packets? */ + if (arp_table[i].q != NULL) { + 800ddde: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800dde2: 4980 ldr r1, [pc, #512] ; (800dfe4 ) + 800dde4: 4613 mov r3, r2 + 800dde6: 005b lsls r3, r3, #1 + 800dde8: 4413 add r3, r2 + 800ddea: 00db lsls r3, r3, #3 + 800ddec: 440b add r3, r1 + 800ddee: 681b ldr r3, [r3, #0] + 800ddf0: 2b00 cmp r3, #0 + 800ddf2: d01a beq.n 800de2a + if (arp_table[i].ctime >= age_queue) { + 800ddf4: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800ddf8: 497a ldr r1, [pc, #488] ; (800dfe4 ) + 800ddfa: 4613 mov r3, r2 + 800ddfc: 005b lsls r3, r3, #1 + 800ddfe: 4413 add r3, r2 + 800de00: 00db lsls r3, r3, #3 + 800de02: 440b add r3, r1 + 800de04: 3312 adds r3, #18 + 800de06: 881b ldrh r3, [r3, #0] + 800de08: 8bba ldrh r2, [r7, #28] + 800de0a: 429a cmp r2, r3 + 800de0c: d845 bhi.n 800de9a + old_queue = i; + 800de0e: 8cfb ldrh r3, [r7, #38] ; 0x26 + 800de10: 83fb strh r3, [r7, #30] + age_queue = arp_table[i].ctime; + 800de12: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800de16: 4973 ldr r1, [pc, #460] ; (800dfe4 ) + 800de18: 4613 mov r3, r2 + 800de1a: 005b lsls r3, r3, #1 + 800de1c: 4413 add r3, r2 + 800de1e: 00db lsls r3, r3, #3 + 800de20: 440b add r3, r1 + 800de22: 3312 adds r3, #18 + 800de24: 881b ldrh r3, [r3, #0] + 800de26: 83bb strh r3, [r7, #28] + 800de28: e037 b.n 800de9a + } + } else + /* pending without queued packets? */ + { + if (arp_table[i].ctime >= age_pending) { + 800de2a: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800de2e: 496d ldr r1, [pc, #436] ; (800dfe4 ) + 800de30: 4613 mov r3, r2 + 800de32: 005b lsls r3, r3, #1 + 800de34: 4413 add r3, r2 + 800de36: 00db lsls r3, r3, #3 + 800de38: 440b add r3, r1 + 800de3a: 3312 adds r3, #18 + 800de3c: 881b ldrh r3, [r3, #0] + 800de3e: 8b7a ldrh r2, [r7, #26] + 800de40: 429a cmp r2, r3 + 800de42: d82a bhi.n 800de9a + old_pending = i; + 800de44: 8cfb ldrh r3, [r7, #38] ; 0x26 + 800de46: 843b strh r3, [r7, #32] + age_pending = arp_table[i].ctime; + 800de48: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800de4c: 4965 ldr r1, [pc, #404] ; (800dfe4 ) + 800de4e: 4613 mov r3, r2 + 800de50: 005b lsls r3, r3, #1 + 800de52: 4413 add r3, r2 + 800de54: 00db lsls r3, r3, #3 + 800de56: 440b add r3, r1 + 800de58: 3312 adds r3, #18 + 800de5a: 881b ldrh r3, [r3, #0] + 800de5c: 837b strh r3, [r7, #26] + 800de5e: e01c b.n 800de9a + } + } + /* stable entry? */ + } else if (state >= ETHARP_STATE_STABLE) { + 800de60: 7dfb ldrb r3, [r7, #23] + 800de62: 2b01 cmp r3, #1 + 800de64: d919 bls.n 800de9a + /* don't record old_stable for static entries since they never expire */ + if (state < ETHARP_STATE_STATIC) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + { + /* remember entry with oldest stable entry in oldest, its age in maxtime */ + if (arp_table[i].ctime >= age_stable) { + 800de66: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800de6a: 495e ldr r1, [pc, #376] ; (800dfe4 ) + 800de6c: 4613 mov r3, r2 + 800de6e: 005b lsls r3, r3, #1 + 800de70: 4413 add r3, r2 + 800de72: 00db lsls r3, r3, #3 + 800de74: 440b add r3, r1 + 800de76: 3312 adds r3, #18 + 800de78: 881b ldrh r3, [r3, #0] + 800de7a: 8b3a ldrh r2, [r7, #24] + 800de7c: 429a cmp r2, r3 + 800de7e: d80c bhi.n 800de9a + old_stable = i; + 800de80: 8cfb ldrh r3, [r7, #38] ; 0x26 + 800de82: 847b strh r3, [r7, #34] ; 0x22 + age_stable = arp_table[i].ctime; + 800de84: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800de88: 4956 ldr r1, [pc, #344] ; (800dfe4 ) + 800de8a: 4613 mov r3, r2 + 800de8c: 005b lsls r3, r3, #1 + 800de8e: 4413 add r3, r2 + 800de90: 00db lsls r3, r3, #3 + 800de92: 440b add r3, r1 + 800de94: 3312 adds r3, #18 + 800de96: 881b ldrh r3, [r3, #0] + 800de98: 833b strh r3, [r7, #24] + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 800de9a: 8cfb ldrh r3, [r7, #38] ; 0x26 + 800de9c: 3301 adds r3, #1 + 800de9e: b29b uxth r3, r3 + 800dea0: 84fb strh r3, [r7, #38] ; 0x26 + 800dea2: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 + 800dea6: 2b09 cmp r3, #9 + 800dea8: f77f af4c ble.w 800dd44 + } + } + /* { we have no match } => try to create a new entry */ + + /* don't create new entry, only search? */ + if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) || + 800deac: 7afb ldrb r3, [r7, #11] + 800deae: f003 0302 and.w r3, r3, #2 + 800deb2: 2b00 cmp r3, #0 + 800deb4: d108 bne.n 800dec8 + 800deb6: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24 + 800deba: 2b0a cmp r3, #10 + 800debc: d107 bne.n 800dece + /* or no empty entry found and not allowed to recycle? */ + ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) { + 800debe: 7afb ldrb r3, [r7, #11] + 800dec0: f003 0301 and.w r3, r3, #1 + 800dec4: 2b00 cmp r3, #0 + 800dec6: d102 bne.n 800dece + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n")); + return (s16_t)ERR_MEM; + 800dec8: f04f 33ff mov.w r3, #4294967295 + 800decc: e085 b.n 800dfda + * + * { ETHARP_FLAG_TRY_HARD is set at this point } + */ + + /* 1) empty entry available? */ + if (empty < ARP_TABLE_SIZE) { + 800dece: f9b7 3024 ldrsh.w r3, [r7, #36] ; 0x24 + 800ded2: 2b09 cmp r3, #9 + 800ded4: dc02 bgt.n 800dedc + i = empty; + 800ded6: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800ded8: 84fb strh r3, [r7, #38] ; 0x26 + 800deda: e039 b.n 800df50 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i)); + } else { + /* 2) found recyclable stable entry? */ + if (old_stable < ARP_TABLE_SIZE) { + 800dedc: f9b7 3022 ldrsh.w r3, [r7, #34] ; 0x22 + 800dee0: 2b09 cmp r3, #9 + 800dee2: dc14 bgt.n 800df0e + /* recycle oldest stable*/ + i = old_stable; + 800dee4: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800dee6: 84fb strh r3, [r7, #38] ; 0x26 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i)); + /* no queued packets should exist on stable entries */ + LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); + 800dee8: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800deec: 493d ldr r1, [pc, #244] ; (800dfe4 ) + 800deee: 4613 mov r3, r2 + 800def0: 005b lsls r3, r3, #1 + 800def2: 4413 add r3, r2 + 800def4: 00db lsls r3, r3, #3 + 800def6: 440b add r3, r1 + 800def8: 681b ldr r3, [r3, #0] + 800defa: 2b00 cmp r3, #0 + 800defc: d018 beq.n 800df30 + 800defe: 4b3a ldr r3, [pc, #232] ; (800dfe8 ) + 800df00: f240 126d movw r2, #365 ; 0x16d + 800df04: 493b ldr r1, [pc, #236] ; (800dff4 ) + 800df06: 483a ldr r0, [pc, #232] ; (800dff0 ) + 800df08: f002 fe5e bl 8010bc8 + 800df0c: e010 b.n 800df30 + /* 3) found recyclable pending entry without queued packets? */ + } else if (old_pending < ARP_TABLE_SIZE) { + 800df0e: f9b7 3020 ldrsh.w r3, [r7, #32] + 800df12: 2b09 cmp r3, #9 + 800df14: dc02 bgt.n 800df1c + /* recycle oldest pending */ + i = old_pending; + 800df16: 8c3b ldrh r3, [r7, #32] + 800df18: 84fb strh r3, [r7, #38] ; 0x26 + 800df1a: e009 b.n 800df30 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i)); + /* 4) found recyclable pending entry with queued packets? */ + } else if (old_queue < ARP_TABLE_SIZE) { + 800df1c: f9b7 301e ldrsh.w r3, [r7, #30] + 800df20: 2b09 cmp r3, #9 + 800df22: dc02 bgt.n 800df2a + /* recycle oldest pending (queued packets are free in etharp_free_entry) */ + i = old_queue; + 800df24: 8bfb ldrh r3, [r7, #30] + 800df26: 84fb strh r3, [r7, #38] ; 0x26 + 800df28: e002 b.n 800df30 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q))); + /* no empty or recyclable entries found */ + } else { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n")); + return (s16_t)ERR_MEM; + 800df2a: f04f 33ff mov.w r3, #4294967295 + 800df2e: e054 b.n 800dfda + } + + /* { empty or recyclable entry found } */ + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + 800df30: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 + 800df34: 2b09 cmp r3, #9 + 800df36: dd06 ble.n 800df46 + 800df38: 4b2b ldr r3, [pc, #172] ; (800dfe8 ) + 800df3a: f240 127f movw r2, #383 ; 0x17f + 800df3e: 492e ldr r1, [pc, #184] ; (800dff8 ) + 800df40: 482b ldr r0, [pc, #172] ; (800dff0 ) + 800df42: f002 fe41 bl 8010bc8 + etharp_free_entry(i); + 800df46: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 + 800df4a: 4618 mov r0, r3 + 800df4c: f7ff fdd8 bl 800db00 + } + + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + 800df50: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 + 800df54: 2b09 cmp r3, #9 + 800df56: dd06 ble.n 800df66 + 800df58: 4b23 ldr r3, [pc, #140] ; (800dfe8 ) + 800df5a: f240 1283 movw r2, #387 ; 0x183 + 800df5e: 4926 ldr r1, [pc, #152] ; (800dff8 ) + 800df60: 4823 ldr r0, [pc, #140] ; (800dff0 ) + 800df62: f002 fe31 bl 8010bc8 + LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY", + 800df66: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800df6a: 491e ldr r1, [pc, #120] ; (800dfe4 ) + 800df6c: 4613 mov r3, r2 + 800df6e: 005b lsls r3, r3, #1 + 800df70: 4413 add r3, r2 + 800df72: 00db lsls r3, r3, #3 + 800df74: 440b add r3, r1 + 800df76: 3314 adds r3, #20 + 800df78: 781b ldrb r3, [r3, #0] + 800df7a: 2b00 cmp r3, #0 + 800df7c: d006 beq.n 800df8c + 800df7e: 4b1a ldr r3, [pc, #104] ; (800dfe8 ) + 800df80: f44f 72c2 mov.w r2, #388 ; 0x184 + 800df84: 491d ldr r1, [pc, #116] ; (800dffc ) + 800df86: 481a ldr r0, [pc, #104] ; (800dff0 ) + 800df88: f002 fe1e bl 8010bc8 + arp_table[i].state == ETHARP_STATE_EMPTY); + + /* IP address given? */ + if (ipaddr != NULL) { + 800df8c: 68fb ldr r3, [r7, #12] + 800df8e: 2b00 cmp r3, #0 + 800df90: d00b beq.n 800dfaa + /* set IP address */ + ip4_addr_copy(arp_table[i].ipaddr, *ipaddr); + 800df92: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800df96: 68fb ldr r3, [r7, #12] + 800df98: 6819 ldr r1, [r3, #0] + 800df9a: 4812 ldr r0, [pc, #72] ; (800dfe4 ) + 800df9c: 4613 mov r3, r2 + 800df9e: 005b lsls r3, r3, #1 + 800dfa0: 4413 add r3, r2 + 800dfa2: 00db lsls r3, r3, #3 + 800dfa4: 4403 add r3, r0 + 800dfa6: 3304 adds r3, #4 + 800dfa8: 6019 str r1, [r3, #0] + } + arp_table[i].ctime = 0; + 800dfaa: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800dfae: 490d ldr r1, [pc, #52] ; (800dfe4 ) + 800dfb0: 4613 mov r3, r2 + 800dfb2: 005b lsls r3, r3, #1 + 800dfb4: 4413 add r3, r2 + 800dfb6: 00db lsls r3, r3, #3 + 800dfb8: 440b add r3, r1 + 800dfba: 3312 adds r3, #18 + 800dfbc: 2200 movs r2, #0 + 800dfbe: 801a strh r2, [r3, #0] +#if ETHARP_TABLE_MATCH_NETIF + arp_table[i].netif = netif; + 800dfc0: f9b7 2026 ldrsh.w r2, [r7, #38] ; 0x26 + 800dfc4: 4907 ldr r1, [pc, #28] ; (800dfe4 ) + 800dfc6: 4613 mov r3, r2 + 800dfc8: 005b lsls r3, r3, #1 + 800dfca: 4413 add r3, r2 + 800dfcc: 00db lsls r3, r3, #3 + 800dfce: 440b add r3, r1 + 800dfd0: 3308 adds r3, #8 + 800dfd2: 687a ldr r2, [r7, #4] + 800dfd4: 601a str r2, [r3, #0] +#endif /* ETHARP_TABLE_MATCH_NETIF */ + return (s16_t)i; + 800dfd6: f9b7 3026 ldrsh.w r3, [r7, #38] ; 0x26 +} + 800dfda: 4618 mov r0, r3 + 800dfdc: 3728 adds r7, #40 ; 0x28 + 800dfde: 46bd mov sp, r7 + 800dfe0: bd80 pop {r7, pc} + 800dfe2: bf00 nop + 800dfe4: 24007bd0 .word 0x24007bd0 + 800dfe8: 080142dc .word 0x080142dc + 800dfec: 08014314 .word 0x08014314 + 800dff0: 08014354 .word 0x08014354 + 800dff4: 0801437c .word 0x0801437c + 800dff8: 08014394 .word 0x08014394 + 800dffc: 080143a8 .word 0x080143a8 + +0800e000 : + * + * @see pbuf_free() + */ +static err_t +etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags) +{ + 800e000: b580 push {r7, lr} + 800e002: b088 sub sp, #32 + 800e004: af02 add r7, sp, #8 + 800e006: 60f8 str r0, [r7, #12] + 800e008: 60b9 str r1, [r7, #8] + 800e00a: 607a str r2, [r7, #4] + 800e00c: 70fb strb r3, [r7, #3] + s16_t i; + LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN); + 800e00e: 68fb ldr r3, [r7, #12] + 800e010: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 800e014: 2b06 cmp r3, #6 + 800e016: d006 beq.n 800e026 + 800e018: 4b48 ldr r3, [pc, #288] ; (800e13c ) + 800e01a: f240 12a9 movw r2, #425 ; 0x1a9 + 800e01e: 4948 ldr r1, [pc, #288] ; (800e140 ) + 800e020: 4848 ldr r0, [pc, #288] ; (800e144 ) + 800e022: f002 fdd1 bl 8010bc8 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), + (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2], + (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5])); + /* non-unicast address? */ + if (ip4_addr_isany(ipaddr) || + 800e026: 68bb ldr r3, [r7, #8] + 800e028: 2b00 cmp r3, #0 + 800e02a: d012 beq.n 800e052 + 800e02c: 68bb ldr r3, [r7, #8] + 800e02e: 681b ldr r3, [r3, #0] + 800e030: 2b00 cmp r3, #0 + 800e032: d00e beq.n 800e052 + ip4_addr_isbroadcast(ipaddr, netif) || + 800e034: 68bb ldr r3, [r7, #8] + 800e036: 681b ldr r3, [r3, #0] + 800e038: 68f9 ldr r1, [r7, #12] + 800e03a: 4618 mov r0, r3 + 800e03c: f001 f9ba bl 800f3b4 + 800e040: 4603 mov r3, r0 + if (ip4_addr_isany(ipaddr) || + 800e042: 2b00 cmp r3, #0 + 800e044: d105 bne.n 800e052 + ip4_addr_ismulticast(ipaddr)) { + 800e046: 68bb ldr r3, [r7, #8] + 800e048: 681b ldr r3, [r3, #0] + 800e04a: f003 03f0 and.w r3, r3, #240 ; 0xf0 + ip4_addr_isbroadcast(ipaddr, netif) || + 800e04e: 2be0 cmp r3, #224 ; 0xe0 + 800e050: d102 bne.n 800e058 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + 800e052: f06f 030f mvn.w r3, #15 + 800e056: e06c b.n 800e132 + } + /* find or create ARP entry */ + i = etharp_find_entry(ipaddr, flags, netif); + 800e058: 78fb ldrb r3, [r7, #3] + 800e05a: 68fa ldr r2, [r7, #12] + 800e05c: 4619 mov r1, r3 + 800e05e: 68b8 ldr r0, [r7, #8] + 800e060: f7ff fe56 bl 800dd10 + 800e064: 4603 mov r3, r0 + 800e066: 82fb strh r3, [r7, #22] + /* bail out if no entry could be found */ + if (i < 0) { + 800e068: f9b7 3016 ldrsh.w r3, [r7, #22] + 800e06c: 2b00 cmp r3, #0 + 800e06e: da02 bge.n 800e076 + return (err_t)i; + 800e070: 8afb ldrh r3, [r7, #22] + 800e072: b25b sxtb r3, r3 + 800e074: e05d b.n 800e132 + return ERR_VAL; + } else +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + { + /* mark it stable */ + arp_table[i].state = ETHARP_STATE_STABLE; + 800e076: f9b7 2016 ldrsh.w r2, [r7, #22] + 800e07a: 4933 ldr r1, [pc, #204] ; (800e148 ) + 800e07c: 4613 mov r3, r2 + 800e07e: 005b lsls r3, r3, #1 + 800e080: 4413 add r3, r2 + 800e082: 00db lsls r3, r3, #3 + 800e084: 440b add r3, r1 + 800e086: 3314 adds r3, #20 + 800e088: 2202 movs r2, #2 + 800e08a: 701a strb r2, [r3, #0] + } + + /* record network interface */ + arp_table[i].netif = netif; + 800e08c: f9b7 2016 ldrsh.w r2, [r7, #22] + 800e090: 492d ldr r1, [pc, #180] ; (800e148 ) + 800e092: 4613 mov r3, r2 + 800e094: 005b lsls r3, r3, #1 + 800e096: 4413 add r3, r2 + 800e098: 00db lsls r3, r3, #3 + 800e09a: 440b add r3, r1 + 800e09c: 3308 adds r3, #8 + 800e09e: 68fa ldr r2, [r7, #12] + 800e0a0: 601a str r2, [r3, #0] + /* insert in SNMP ARP index tree */ + mib2_add_arp_entry(netif, &arp_table[i].ipaddr); + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i)); + /* update address */ + SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN); + 800e0a2: f9b7 2016 ldrsh.w r2, [r7, #22] + 800e0a6: 4613 mov r3, r2 + 800e0a8: 005b lsls r3, r3, #1 + 800e0aa: 4413 add r3, r2 + 800e0ac: 00db lsls r3, r3, #3 + 800e0ae: 3308 adds r3, #8 + 800e0b0: 4a25 ldr r2, [pc, #148] ; (800e148 ) + 800e0b2: 4413 add r3, r2 + 800e0b4: 3304 adds r3, #4 + 800e0b6: 2206 movs r2, #6 + 800e0b8: 6879 ldr r1, [r7, #4] + 800e0ba: 4618 mov r0, r3 + 800e0bc: f002 ff65 bl 8010f8a + /* reset time stamp */ + arp_table[i].ctime = 0; + 800e0c0: f9b7 2016 ldrsh.w r2, [r7, #22] + 800e0c4: 4920 ldr r1, [pc, #128] ; (800e148 ) + 800e0c6: 4613 mov r3, r2 + 800e0c8: 005b lsls r3, r3, #1 + 800e0ca: 4413 add r3, r2 + 800e0cc: 00db lsls r3, r3, #3 + 800e0ce: 440b add r3, r1 + 800e0d0: 3312 adds r3, #18 + 800e0d2: 2200 movs r2, #0 + 800e0d4: 801a strh r2, [r3, #0] + /* get the packet pointer */ + p = q->p; + /* now queue entry can be freed */ + memp_free(MEMP_ARP_QUEUE, q); +#else /* ARP_QUEUEING */ + if (arp_table[i].q != NULL) { + 800e0d6: f9b7 2016 ldrsh.w r2, [r7, #22] + 800e0da: 491b ldr r1, [pc, #108] ; (800e148 ) + 800e0dc: 4613 mov r3, r2 + 800e0de: 005b lsls r3, r3, #1 + 800e0e0: 4413 add r3, r2 + 800e0e2: 00db lsls r3, r3, #3 + 800e0e4: 440b add r3, r1 + 800e0e6: 681b ldr r3, [r3, #0] + 800e0e8: 2b00 cmp r3, #0 + 800e0ea: d021 beq.n 800e130 + struct pbuf *p = arp_table[i].q; + 800e0ec: f9b7 2016 ldrsh.w r2, [r7, #22] + 800e0f0: 4915 ldr r1, [pc, #84] ; (800e148 ) + 800e0f2: 4613 mov r3, r2 + 800e0f4: 005b lsls r3, r3, #1 + 800e0f6: 4413 add r3, r2 + 800e0f8: 00db lsls r3, r3, #3 + 800e0fa: 440b add r3, r1 + 800e0fc: 681b ldr r3, [r3, #0] + 800e0fe: 613b str r3, [r7, #16] + arp_table[i].q = NULL; + 800e100: f9b7 2016 ldrsh.w r2, [r7, #22] + 800e104: 4910 ldr r1, [pc, #64] ; (800e148 ) + 800e106: 4613 mov r3, r2 + 800e108: 005b lsls r3, r3, #1 + 800e10a: 4413 add r3, r2 + 800e10c: 00db lsls r3, r3, #3 + 800e10e: 440b add r3, r1 + 800e110: 2200 movs r2, #0 + 800e112: 601a str r2, [r3, #0] +#endif /* ARP_QUEUEING */ + /* send the queued IP packet */ + ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP); + 800e114: 68fb ldr r3, [r7, #12] + 800e116: f103 0226 add.w r2, r3, #38 ; 0x26 + 800e11a: f44f 6300 mov.w r3, #2048 ; 0x800 + 800e11e: 9300 str r3, [sp, #0] + 800e120: 687b ldr r3, [r7, #4] + 800e122: 6939 ldr r1, [r7, #16] + 800e124: 68f8 ldr r0, [r7, #12] + 800e126: f002 f853 bl 80101d0 + /* free the queued IP packet */ + pbuf_free(p); + 800e12a: 6938 ldr r0, [r7, #16] + 800e12c: f7f8 ff52 bl 8006fd4 + } + return ERR_OK; + 800e130: 2300 movs r3, #0 +} + 800e132: 4618 mov r0, r3 + 800e134: 3718 adds r7, #24 + 800e136: 46bd mov sp, r7 + 800e138: bd80 pop {r7, pc} + 800e13a: bf00 nop + 800e13c: 080142dc .word 0x080142dc + 800e140: 080143d4 .word 0x080143d4 + 800e144: 08014354 .word 0x08014354 + 800e148: 24007bd0 .word 0x24007bd0 + +0800e14c : + * + * @param netif points to a network interface + */ +void +etharp_cleanup_netif(struct netif *netif) +{ + 800e14c: b580 push {r7, lr} + 800e14e: b084 sub sp, #16 + 800e150: af00 add r7, sp, #0 + 800e152: 6078 str r0, [r7, #4] + int i; + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 800e154: 2300 movs r3, #0 + 800e156: 60fb str r3, [r7, #12] + 800e158: e01e b.n 800e198 + u8_t state = arp_table[i].state; + 800e15a: 4913 ldr r1, [pc, #76] ; (800e1a8 ) + 800e15c: 68fa ldr r2, [r7, #12] + 800e15e: 4613 mov r3, r2 + 800e160: 005b lsls r3, r3, #1 + 800e162: 4413 add r3, r2 + 800e164: 00db lsls r3, r3, #3 + 800e166: 440b add r3, r1 + 800e168: 3314 adds r3, #20 + 800e16a: 781b ldrb r3, [r3, #0] + 800e16c: 72fb strb r3, [r7, #11] + if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) { + 800e16e: 7afb ldrb r3, [r7, #11] + 800e170: 2b00 cmp r3, #0 + 800e172: d00e beq.n 800e192 + 800e174: 490c ldr r1, [pc, #48] ; (800e1a8 ) + 800e176: 68fa ldr r2, [r7, #12] + 800e178: 4613 mov r3, r2 + 800e17a: 005b lsls r3, r3, #1 + 800e17c: 4413 add r3, r2 + 800e17e: 00db lsls r3, r3, #3 + 800e180: 440b add r3, r1 + 800e182: 3308 adds r3, #8 + 800e184: 681b ldr r3, [r3, #0] + 800e186: 687a ldr r2, [r7, #4] + 800e188: 429a cmp r2, r3 + 800e18a: d102 bne.n 800e192 + etharp_free_entry(i); + 800e18c: 68f8 ldr r0, [r7, #12] + 800e18e: f7ff fcb7 bl 800db00 + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + 800e192: 68fb ldr r3, [r7, #12] + 800e194: 3301 adds r3, #1 + 800e196: 60fb str r3, [r7, #12] + 800e198: 68fb ldr r3, [r7, #12] + 800e19a: 2b09 cmp r3, #9 + 800e19c: dddd ble.n 800e15a + } + } +} + 800e19e: bf00 nop + 800e1a0: bf00 nop + 800e1a2: 3710 adds r7, #16 + 800e1a4: 46bd mov sp, r7 + 800e1a6: bd80 pop {r7, pc} + 800e1a8: 24007bd0 .word 0x24007bd0 + +0800e1ac : + * + * @see pbuf_free() + */ +void +etharp_input(struct pbuf *p, struct netif *netif) +{ + 800e1ac: b5b0 push {r4, r5, r7, lr} + 800e1ae: b08a sub sp, #40 ; 0x28 + 800e1b0: af04 add r7, sp, #16 + 800e1b2: 6078 str r0, [r7, #4] + 800e1b4: 6039 str r1, [r7, #0] + ip4_addr_t sipaddr, dipaddr; + u8_t for_us; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + 800e1b6: 683b ldr r3, [r7, #0] + 800e1b8: 2b00 cmp r3, #0 + 800e1ba: d107 bne.n 800e1cc + 800e1bc: 4b3d ldr r3, [pc, #244] ; (800e2b4 ) + 800e1be: f240 228a movw r2, #650 ; 0x28a + 800e1c2: 493d ldr r1, [pc, #244] ; (800e2b8 ) + 800e1c4: 483d ldr r0, [pc, #244] ; (800e2bc ) + 800e1c6: f002 fcff bl 8010bc8 + 800e1ca: e06f b.n 800e2ac + + hdr = (struct etharp_hdr *)p->payload; + 800e1cc: 687b ldr r3, [r7, #4] + 800e1ce: 685b ldr r3, [r3, #4] + 800e1d0: 617b str r3, [r7, #20] + + /* RFC 826 "Packet Reception": */ + if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) || + 800e1d2: 697b ldr r3, [r7, #20] + 800e1d4: 881b ldrh r3, [r3, #0] + 800e1d6: b29b uxth r3, r3 + 800e1d8: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800e1dc: d10c bne.n 800e1f8 + (hdr->hwlen != ETH_HWADDR_LEN) || + 800e1de: 697b ldr r3, [r7, #20] + 800e1e0: 791b ldrb r3, [r3, #4] + if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) || + 800e1e2: 2b06 cmp r3, #6 + 800e1e4: d108 bne.n 800e1f8 + (hdr->protolen != sizeof(ip4_addr_t)) || + 800e1e6: 697b ldr r3, [r7, #20] + 800e1e8: 795b ldrb r3, [r3, #5] + (hdr->hwlen != ETH_HWADDR_LEN) || + 800e1ea: 2b04 cmp r3, #4 + 800e1ec: d104 bne.n 800e1f8 + (hdr->proto != PP_HTONS(ETHTYPE_IP))) { + 800e1ee: 697b ldr r3, [r7, #20] + 800e1f0: 885b ldrh r3, [r3, #2] + 800e1f2: b29b uxth r3, r3 + (hdr->protolen != sizeof(ip4_addr_t)) || + 800e1f4: 2b08 cmp r3, #8 + 800e1f6: d003 beq.n 800e200 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", + hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen)); + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + 800e1f8: 6878 ldr r0, [r7, #4] + 800e1fa: f7f8 feeb bl 8006fd4 + return; + 800e1fe: e055 b.n 800e2ac + autoip_arp_reply(netif, hdr); +#endif /* LWIP_AUTOIP */ + + /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). */ + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr); + 800e200: 697b ldr r3, [r7, #20] + 800e202: 330e adds r3, #14 + 800e204: 681b ldr r3, [r3, #0] + 800e206: 60fb str r3, [r7, #12] + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr); + 800e208: 697b ldr r3, [r7, #20] + 800e20a: 3318 adds r3, #24 + 800e20c: 681b ldr r3, [r3, #0] + 800e20e: 60bb str r3, [r7, #8] + + /* this interface is not configured? */ + if (ip4_addr_isany_val(*netif_ip4_addr(netif))) { + 800e210: 683b ldr r3, [r7, #0] + 800e212: 3304 adds r3, #4 + 800e214: 681b ldr r3, [r3, #0] + 800e216: 2b00 cmp r3, #0 + 800e218: d102 bne.n 800e220 + for_us = 0; + 800e21a: 2300 movs r3, #0 + 800e21c: 74fb strb r3, [r7, #19] + 800e21e: e009 b.n 800e234 + } else { + /* ARP packet directed to us? */ + for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif)); + 800e220: 68ba ldr r2, [r7, #8] + 800e222: 683b ldr r3, [r7, #0] + 800e224: 3304 adds r3, #4 + 800e226: 681b ldr r3, [r3, #0] + 800e228: 429a cmp r2, r3 + 800e22a: bf0c ite eq + 800e22c: 2301 moveq r3, #1 + 800e22e: 2300 movne r3, #0 + 800e230: b2db uxtb r3, r3 + 800e232: 74fb strb r3, [r7, #19] + /* ARP message directed to us? + -> add IP address in ARP cache; assume requester wants to talk to us, + can result in directly sending the queued packets for this host. + ARP message not directed to us? + -> update the source IP address in the cache, if present */ + etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), + 800e234: 697b ldr r3, [r7, #20] + 800e236: f103 0208 add.w r2, r3, #8 + 800e23a: 7cfb ldrb r3, [r7, #19] + 800e23c: 2b00 cmp r3, #0 + 800e23e: d001 beq.n 800e244 + 800e240: 2301 movs r3, #1 + 800e242: e000 b.n 800e246 + 800e244: 2302 movs r3, #2 + 800e246: f107 010c add.w r1, r7, #12 + 800e24a: 6838 ldr r0, [r7, #0] + 800e24c: f7ff fed8 bl 800e000 + for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY); + + /* now act on the message itself */ + switch (hdr->opcode) { + 800e250: 697b ldr r3, [r7, #20] + 800e252: 88db ldrh r3, [r3, #6] + 800e254: b29b uxth r3, r3 + 800e256: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800e25a: d003 beq.n 800e264 + 800e25c: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800e260: d01e beq.n 800e2a0 +#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */ + break; + default: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode))); + ETHARP_STATS_INC(etharp.err); + break; + 800e262: e020 b.n 800e2a6 + if (for_us) { + 800e264: 7cfb ldrb r3, [r7, #19] + 800e266: 2b00 cmp r3, #0 + 800e268: d01c beq.n 800e2a4 + (struct eth_addr *)netif->hwaddr, &hdr->shwaddr, + 800e26a: 683b ldr r3, [r7, #0] + 800e26c: f103 0026 add.w r0, r3, #38 ; 0x26 + 800e270: 697b ldr r3, [r7, #20] + 800e272: f103 0408 add.w r4, r3, #8 + (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), + 800e276: 683b ldr r3, [r7, #0] + 800e278: f103 0526 add.w r5, r3, #38 ; 0x26 + 800e27c: 683b ldr r3, [r7, #0] + 800e27e: 3304 adds r3, #4 + &hdr->shwaddr, &sipaddr, + 800e280: 697a ldr r2, [r7, #20] + 800e282: 3208 adds r2, #8 + etharp_raw(netif, + 800e284: 2102 movs r1, #2 + 800e286: 9103 str r1, [sp, #12] + 800e288: f107 010c add.w r1, r7, #12 + 800e28c: 9102 str r1, [sp, #8] + 800e28e: 9201 str r2, [sp, #4] + 800e290: 9300 str r3, [sp, #0] + 800e292: 462b mov r3, r5 + 800e294: 4622 mov r2, r4 + 800e296: 4601 mov r1, r0 + 800e298: 6838 ldr r0, [r7, #0] + 800e29a: f000 faeb bl 800e874 + break; + 800e29e: e001 b.n 800e2a4 + break; + 800e2a0: bf00 nop + 800e2a2: e000 b.n 800e2a6 + break; + 800e2a4: bf00 nop + } + /* free ARP packet */ + pbuf_free(p); + 800e2a6: 6878 ldr r0, [r7, #4] + 800e2a8: f7f8 fe94 bl 8006fd4 +} + 800e2ac: 3718 adds r7, #24 + 800e2ae: 46bd mov sp, r7 + 800e2b0: bdb0 pop {r4, r5, r7, pc} + 800e2b2: bf00 nop + 800e2b4: 080142dc .word 0x080142dc + 800e2b8: 0801442c .word 0x0801442c + 800e2bc: 08014354 .word 0x08014354 + +0800e2c0 : +/** Just a small helper function that sends a pbuf to an ethernet address + * in the arp_table specified by the index 'arp_idx'. + */ +static err_t +etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx) +{ + 800e2c0: b580 push {r7, lr} + 800e2c2: b086 sub sp, #24 + 800e2c4: af02 add r7, sp, #8 + 800e2c6: 60f8 str r0, [r7, #12] + 800e2c8: 60b9 str r1, [r7, #8] + 800e2ca: 4613 mov r3, r2 + 800e2cc: 71fb strb r3, [r7, #7] + LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE", + 800e2ce: 79fa ldrb r2, [r7, #7] + 800e2d0: 4944 ldr r1, [pc, #272] ; (800e3e4 ) + 800e2d2: 4613 mov r3, r2 + 800e2d4: 005b lsls r3, r3, #1 + 800e2d6: 4413 add r3, r2 + 800e2d8: 00db lsls r3, r3, #3 + 800e2da: 440b add r3, r1 + 800e2dc: 3314 adds r3, #20 + 800e2de: 781b ldrb r3, [r3, #0] + 800e2e0: 2b01 cmp r3, #1 + 800e2e2: d806 bhi.n 800e2f2 + 800e2e4: 4b40 ldr r3, [pc, #256] ; (800e3e8 ) + 800e2e6: f240 22ee movw r2, #750 ; 0x2ee + 800e2ea: 4940 ldr r1, [pc, #256] ; (800e3ec ) + 800e2ec: 4840 ldr r0, [pc, #256] ; (800e3f0 ) + 800e2ee: f002 fc6b bl 8010bc8 + arp_table[arp_idx].state >= ETHARP_STATE_STABLE); + /* if arp table entry is about to expire: re-request it, + but only if its state is ETHARP_STATE_STABLE to prevent flooding the + network with ARP requests if this address is used frequently. */ + if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) { + 800e2f2: 79fa ldrb r2, [r7, #7] + 800e2f4: 493b ldr r1, [pc, #236] ; (800e3e4 ) + 800e2f6: 4613 mov r3, r2 + 800e2f8: 005b lsls r3, r3, #1 + 800e2fa: 4413 add r3, r2 + 800e2fc: 00db lsls r3, r3, #3 + 800e2fe: 440b add r3, r1 + 800e300: 3314 adds r3, #20 + 800e302: 781b ldrb r3, [r3, #0] + 800e304: 2b02 cmp r3, #2 + 800e306: d153 bne.n 800e3b0 + if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) { + 800e308: 79fa ldrb r2, [r7, #7] + 800e30a: 4936 ldr r1, [pc, #216] ; (800e3e4 ) + 800e30c: 4613 mov r3, r2 + 800e30e: 005b lsls r3, r3, #1 + 800e310: 4413 add r3, r2 + 800e312: 00db lsls r3, r3, #3 + 800e314: 440b add r3, r1 + 800e316: 3312 adds r3, #18 + 800e318: 881b ldrh r3, [r3, #0] + 800e31a: f5b3 7f8e cmp.w r3, #284 ; 0x11c + 800e31e: d919 bls.n 800e354 + /* issue a standard request using broadcast */ + if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) { + 800e320: 79fa ldrb r2, [r7, #7] + 800e322: 4613 mov r3, r2 + 800e324: 005b lsls r3, r3, #1 + 800e326: 4413 add r3, r2 + 800e328: 00db lsls r3, r3, #3 + 800e32a: 4a2e ldr r2, [pc, #184] ; (800e3e4 ) + 800e32c: 4413 add r3, r2 + 800e32e: 3304 adds r3, #4 + 800e330: 4619 mov r1, r3 + 800e332: 68f8 ldr r0, [r7, #12] + 800e334: f000 fb4c bl 800e9d0 + 800e338: 4603 mov r3, r0 + 800e33a: 2b00 cmp r3, #0 + 800e33c: d138 bne.n 800e3b0 + arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; + 800e33e: 79fa ldrb r2, [r7, #7] + 800e340: 4928 ldr r1, [pc, #160] ; (800e3e4 ) + 800e342: 4613 mov r3, r2 + 800e344: 005b lsls r3, r3, #1 + 800e346: 4413 add r3, r2 + 800e348: 00db lsls r3, r3, #3 + 800e34a: 440b add r3, r1 + 800e34c: 3314 adds r3, #20 + 800e34e: 2203 movs r2, #3 + 800e350: 701a strb r2, [r3, #0] + 800e352: e02d b.n 800e3b0 + } + } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) { + 800e354: 79fa ldrb r2, [r7, #7] + 800e356: 4923 ldr r1, [pc, #140] ; (800e3e4 ) + 800e358: 4613 mov r3, r2 + 800e35a: 005b lsls r3, r3, #1 + 800e35c: 4413 add r3, r2 + 800e35e: 00db lsls r3, r3, #3 + 800e360: 440b add r3, r1 + 800e362: 3312 adds r3, #18 + 800e364: 881b ldrh r3, [r3, #0] + 800e366: f5b3 7f87 cmp.w r3, #270 ; 0x10e + 800e36a: d321 bcc.n 800e3b0 + /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */ + if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) { + 800e36c: 79fa ldrb r2, [r7, #7] + 800e36e: 4613 mov r3, r2 + 800e370: 005b lsls r3, r3, #1 + 800e372: 4413 add r3, r2 + 800e374: 00db lsls r3, r3, #3 + 800e376: 4a1b ldr r2, [pc, #108] ; (800e3e4 ) + 800e378: 4413 add r3, r2 + 800e37a: 1d19 adds r1, r3, #4 + 800e37c: 79fa ldrb r2, [r7, #7] + 800e37e: 4613 mov r3, r2 + 800e380: 005b lsls r3, r3, #1 + 800e382: 4413 add r3, r2 + 800e384: 00db lsls r3, r3, #3 + 800e386: 3308 adds r3, #8 + 800e388: 4a16 ldr r2, [pc, #88] ; (800e3e4 ) + 800e38a: 4413 add r3, r2 + 800e38c: 3304 adds r3, #4 + 800e38e: 461a mov r2, r3 + 800e390: 68f8 ldr r0, [r7, #12] + 800e392: f000 fafb bl 800e98c + 800e396: 4603 mov r3, r0 + 800e398: 2b00 cmp r3, #0 + 800e39a: d109 bne.n 800e3b0 + arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; + 800e39c: 79fa ldrb r2, [r7, #7] + 800e39e: 4911 ldr r1, [pc, #68] ; (800e3e4 ) + 800e3a0: 4613 mov r3, r2 + 800e3a2: 005b lsls r3, r3, #1 + 800e3a4: 4413 add r3, r2 + 800e3a6: 00db lsls r3, r3, #3 + 800e3a8: 440b add r3, r1 + 800e3aa: 3314 adds r3, #20 + 800e3ac: 2203 movs r2, #3 + 800e3ae: 701a strb r2, [r3, #0] + } + } + } + + return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP); + 800e3b0: 68fb ldr r3, [r7, #12] + 800e3b2: f103 0126 add.w r1, r3, #38 ; 0x26 + 800e3b6: 79fa ldrb r2, [r7, #7] + 800e3b8: 4613 mov r3, r2 + 800e3ba: 005b lsls r3, r3, #1 + 800e3bc: 4413 add r3, r2 + 800e3be: 00db lsls r3, r3, #3 + 800e3c0: 3308 adds r3, #8 + 800e3c2: 4a08 ldr r2, [pc, #32] ; (800e3e4 ) + 800e3c4: 4413 add r3, r2 + 800e3c6: 3304 adds r3, #4 + 800e3c8: f44f 6200 mov.w r2, #2048 ; 0x800 + 800e3cc: 9200 str r2, [sp, #0] + 800e3ce: 460a mov r2, r1 + 800e3d0: 68b9 ldr r1, [r7, #8] + 800e3d2: 68f8 ldr r0, [r7, #12] + 800e3d4: f001 fefc bl 80101d0 + 800e3d8: 4603 mov r3, r0 +} + 800e3da: 4618 mov r0, r3 + 800e3dc: 3710 adds r7, #16 + 800e3de: 46bd mov sp, r7 + 800e3e0: bd80 pop {r7, pc} + 800e3e2: bf00 nop + 800e3e4: 24007bd0 .word 0x24007bd0 + 800e3e8: 080142dc .word 0x080142dc + 800e3ec: 0801444c .word 0x0801444c + 800e3f0: 08014354 .word 0x08014354 + +0800e3f4 : + * - ERR_RTE No route to destination (no gateway to external networks), + * or the return type of either etharp_query() or ethernet_output(). + */ +err_t +etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) +{ + 800e3f4: b580 push {r7, lr} + 800e3f6: b08a sub sp, #40 ; 0x28 + 800e3f8: af02 add r7, sp, #8 + 800e3fa: 60f8 str r0, [r7, #12] + 800e3fc: 60b9 str r1, [r7, #8] + 800e3fe: 607a str r2, [r7, #4] + const struct eth_addr *dest; + struct eth_addr mcastaddr; + const ip4_addr_t *dst_addr = ipaddr; + 800e400: 687b ldr r3, [r7, #4] + 800e402: 61bb str r3, [r7, #24] + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + 800e404: 68fb ldr r3, [r7, #12] + 800e406: 2b00 cmp r3, #0 + 800e408: d106 bne.n 800e418 + 800e40a: 4b73 ldr r3, [pc, #460] ; (800e5d8 ) + 800e40c: f240 321e movw r2, #798 ; 0x31e + 800e410: 4972 ldr r1, [pc, #456] ; (800e5dc ) + 800e412: 4873 ldr r0, [pc, #460] ; (800e5e0 ) + 800e414: f002 fbd8 bl 8010bc8 + LWIP_ASSERT("q != NULL", q != NULL); + 800e418: 68bb ldr r3, [r7, #8] + 800e41a: 2b00 cmp r3, #0 + 800e41c: d106 bne.n 800e42c + 800e41e: 4b6e ldr r3, [pc, #440] ; (800e5d8 ) + 800e420: f240 321f movw r2, #799 ; 0x31f + 800e424: 496f ldr r1, [pc, #444] ; (800e5e4 ) + 800e426: 486e ldr r0, [pc, #440] ; (800e5e0 ) + 800e428: f002 fbce bl 8010bc8 + LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL); + 800e42c: 687b ldr r3, [r7, #4] + 800e42e: 2b00 cmp r3, #0 + 800e430: d106 bne.n 800e440 + 800e432: 4b69 ldr r3, [pc, #420] ; (800e5d8 ) + 800e434: f44f 7248 mov.w r2, #800 ; 0x320 + 800e438: 496b ldr r1, [pc, #428] ; (800e5e8 ) + 800e43a: 4869 ldr r0, [pc, #420] ; (800e5e0 ) + 800e43c: f002 fbc4 bl 8010bc8 + + /* Determine on destination hardware address. Broadcasts and multicasts + * are special, other IP addresses are looked up in the ARP table. */ + + /* broadcast destination IP address? */ + if (ip4_addr_isbroadcast(ipaddr, netif)) { + 800e440: 687b ldr r3, [r7, #4] + 800e442: 681b ldr r3, [r3, #0] + 800e444: 68f9 ldr r1, [r7, #12] + 800e446: 4618 mov r0, r3 + 800e448: f000 ffb4 bl 800f3b4 + 800e44c: 4603 mov r3, r0 + 800e44e: 2b00 cmp r3, #0 + 800e450: d002 beq.n 800e458 + /* broadcast on Ethernet also */ + dest = (const struct eth_addr *)ðbroadcast; + 800e452: 4b66 ldr r3, [pc, #408] ; (800e5ec ) + 800e454: 61fb str r3, [r7, #28] + 800e456: e0af b.n 800e5b8 + /* multicast destination IP address? */ + } else if (ip4_addr_ismulticast(ipaddr)) { + 800e458: 687b ldr r3, [r7, #4] + 800e45a: 681b ldr r3, [r3, #0] + 800e45c: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800e460: 2be0 cmp r3, #224 ; 0xe0 + 800e462: d118 bne.n 800e496 + /* Hash IP multicast address to MAC address.*/ + mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0; + 800e464: 2301 movs r3, #1 + 800e466: 743b strb r3, [r7, #16] + mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1; + 800e468: 2300 movs r3, #0 + 800e46a: 747b strb r3, [r7, #17] + mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2; + 800e46c: 235e movs r3, #94 ; 0x5e + 800e46e: 74bb strb r3, [r7, #18] + mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; + 800e470: 687b ldr r3, [r7, #4] + 800e472: 3301 adds r3, #1 + 800e474: 781b ldrb r3, [r3, #0] + 800e476: f003 037f and.w r3, r3, #127 ; 0x7f + 800e47a: b2db uxtb r3, r3 + 800e47c: 74fb strb r3, [r7, #19] + mcastaddr.addr[4] = ip4_addr3(ipaddr); + 800e47e: 687b ldr r3, [r7, #4] + 800e480: 3302 adds r3, #2 + 800e482: 781b ldrb r3, [r3, #0] + 800e484: 753b strb r3, [r7, #20] + mcastaddr.addr[5] = ip4_addr4(ipaddr); + 800e486: 687b ldr r3, [r7, #4] + 800e488: 3303 adds r3, #3 + 800e48a: 781b ldrb r3, [r3, #0] + 800e48c: 757b strb r3, [r7, #21] + /* destination Ethernet address is multicast */ + dest = &mcastaddr; + 800e48e: f107 0310 add.w r3, r7, #16 + 800e492: 61fb str r3, [r7, #28] + 800e494: e090 b.n 800e5b8 + /* unicast destination IP address? */ + } else { + netif_addr_idx_t i; + /* outside local network? if so, this can neither be a global broadcast nor + a subnet broadcast. */ + if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && + 800e496: 687b ldr r3, [r7, #4] + 800e498: 681a ldr r2, [r3, #0] + 800e49a: 68fb ldr r3, [r7, #12] + 800e49c: 3304 adds r3, #4 + 800e49e: 681b ldr r3, [r3, #0] + 800e4a0: 405a eors r2, r3 + 800e4a2: 68fb ldr r3, [r7, #12] + 800e4a4: 3308 adds r3, #8 + 800e4a6: 681b ldr r3, [r3, #0] + 800e4a8: 4013 ands r3, r2 + 800e4aa: 2b00 cmp r3, #0 + 800e4ac: d012 beq.n 800e4d4 + !ip4_addr_islinklocal(ipaddr)) { + 800e4ae: 687b ldr r3, [r7, #4] + 800e4b0: 681b ldr r3, [r3, #0] + 800e4b2: b29b uxth r3, r3 + if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && + 800e4b4: f64f 62a9 movw r2, #65193 ; 0xfea9 + 800e4b8: 4293 cmp r3, r2 + 800e4ba: d00b beq.n 800e4d4 + dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr); + if (dst_addr == NULL) +#endif /* LWIP_HOOK_ETHARP_GET_GW */ + { + /* interface has default gateway? */ + if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) { + 800e4bc: 68fb ldr r3, [r7, #12] + 800e4be: 330c adds r3, #12 + 800e4c0: 681b ldr r3, [r3, #0] + 800e4c2: 2b00 cmp r3, #0 + 800e4c4: d003 beq.n 800e4ce + /* send to hardware address of default gateway IP address */ + dst_addr = netif_ip4_gw(netif); + 800e4c6: 68fb ldr r3, [r7, #12] + 800e4c8: 330c adds r3, #12 + 800e4ca: 61bb str r3, [r7, #24] + 800e4cc: e002 b.n 800e4d4 + /* no default gateway available */ + } else { + /* no route to destination error (default gateway missing) */ + return ERR_RTE; + 800e4ce: f06f 0303 mvn.w r3, #3 + 800e4d2: e07d b.n 800e5d0 + if (netif->hints != NULL) { + /* per-pcb cached entry was given */ + netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint; + if (etharp_cached_entry < ARP_TABLE_SIZE) { +#endif /* LWIP_NETIF_HWADDRHINT */ + if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && + 800e4d4: 4b46 ldr r3, [pc, #280] ; (800e5f0 ) + 800e4d6: 781b ldrb r3, [r3, #0] + 800e4d8: 4619 mov r1, r3 + 800e4da: 4a46 ldr r2, [pc, #280] ; (800e5f4 ) + 800e4dc: 460b mov r3, r1 + 800e4de: 005b lsls r3, r3, #1 + 800e4e0: 440b add r3, r1 + 800e4e2: 00db lsls r3, r3, #3 + 800e4e4: 4413 add r3, r2 + 800e4e6: 3314 adds r3, #20 + 800e4e8: 781b ldrb r3, [r3, #0] + 800e4ea: 2b01 cmp r3, #1 + 800e4ec: d925 bls.n 800e53a +#if ETHARP_TABLE_MATCH_NETIF + (arp_table[etharp_cached_entry].netif == netif) && + 800e4ee: 4b40 ldr r3, [pc, #256] ; (800e5f0 ) + 800e4f0: 781b ldrb r3, [r3, #0] + 800e4f2: 4619 mov r1, r3 + 800e4f4: 4a3f ldr r2, [pc, #252] ; (800e5f4 ) + 800e4f6: 460b mov r3, r1 + 800e4f8: 005b lsls r3, r3, #1 + 800e4fa: 440b add r3, r1 + 800e4fc: 00db lsls r3, r3, #3 + 800e4fe: 4413 add r3, r2 + 800e500: 3308 adds r3, #8 + 800e502: 681b ldr r3, [r3, #0] + if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && + 800e504: 68fa ldr r2, [r7, #12] + 800e506: 429a cmp r2, r3 + 800e508: d117 bne.n 800e53a +#endif + (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) { + 800e50a: 69bb ldr r3, [r7, #24] + 800e50c: 681a ldr r2, [r3, #0] + 800e50e: 4b38 ldr r3, [pc, #224] ; (800e5f0 ) + 800e510: 781b ldrb r3, [r3, #0] + 800e512: 4618 mov r0, r3 + 800e514: 4937 ldr r1, [pc, #220] ; (800e5f4 ) + 800e516: 4603 mov r3, r0 + 800e518: 005b lsls r3, r3, #1 + 800e51a: 4403 add r3, r0 + 800e51c: 00db lsls r3, r3, #3 + 800e51e: 440b add r3, r1 + 800e520: 3304 adds r3, #4 + 800e522: 681b ldr r3, [r3, #0] + (arp_table[etharp_cached_entry].netif == netif) && + 800e524: 429a cmp r2, r3 + 800e526: d108 bne.n 800e53a + /* the per-pcb-cached entry is stable and the right one! */ + ETHARP_STATS_INC(etharp.cachehit); + return etharp_output_to_arp_index(netif, q, etharp_cached_entry); + 800e528: 4b31 ldr r3, [pc, #196] ; (800e5f0 ) + 800e52a: 781b ldrb r3, [r3, #0] + 800e52c: 461a mov r2, r3 + 800e52e: 68b9 ldr r1, [r7, #8] + 800e530: 68f8 ldr r0, [r7, #12] + 800e532: f7ff fec5 bl 800e2c0 + 800e536: 4603 mov r3, r0 + 800e538: e04a b.n 800e5d0 + } +#endif /* LWIP_NETIF_HWADDRHINT */ + + /* find stable entry: do this here since this is a critical path for + throughput and etharp_find_entry() is kind of slow */ + for (i = 0; i < ARP_TABLE_SIZE; i++) { + 800e53a: 2300 movs r3, #0 + 800e53c: 75fb strb r3, [r7, #23] + 800e53e: e031 b.n 800e5a4 + if ((arp_table[i].state >= ETHARP_STATE_STABLE) && + 800e540: 7dfa ldrb r2, [r7, #23] + 800e542: 492c ldr r1, [pc, #176] ; (800e5f4 ) + 800e544: 4613 mov r3, r2 + 800e546: 005b lsls r3, r3, #1 + 800e548: 4413 add r3, r2 + 800e54a: 00db lsls r3, r3, #3 + 800e54c: 440b add r3, r1 + 800e54e: 3314 adds r3, #20 + 800e550: 781b ldrb r3, [r3, #0] + 800e552: 2b01 cmp r3, #1 + 800e554: d923 bls.n 800e59e +#if ETHARP_TABLE_MATCH_NETIF + (arp_table[i].netif == netif) && + 800e556: 7dfa ldrb r2, [r7, #23] + 800e558: 4926 ldr r1, [pc, #152] ; (800e5f4 ) + 800e55a: 4613 mov r3, r2 + 800e55c: 005b lsls r3, r3, #1 + 800e55e: 4413 add r3, r2 + 800e560: 00db lsls r3, r3, #3 + 800e562: 440b add r3, r1 + 800e564: 3308 adds r3, #8 + 800e566: 681b ldr r3, [r3, #0] + if ((arp_table[i].state >= ETHARP_STATE_STABLE) && + 800e568: 68fa ldr r2, [r7, #12] + 800e56a: 429a cmp r2, r3 + 800e56c: d117 bne.n 800e59e +#endif + (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) { + 800e56e: 69bb ldr r3, [r7, #24] + 800e570: 6819 ldr r1, [r3, #0] + 800e572: 7dfa ldrb r2, [r7, #23] + 800e574: 481f ldr r0, [pc, #124] ; (800e5f4 ) + 800e576: 4613 mov r3, r2 + 800e578: 005b lsls r3, r3, #1 + 800e57a: 4413 add r3, r2 + 800e57c: 00db lsls r3, r3, #3 + 800e57e: 4403 add r3, r0 + 800e580: 3304 adds r3, #4 + 800e582: 681b ldr r3, [r3, #0] + (arp_table[i].netif == netif) && + 800e584: 4299 cmp r1, r3 + 800e586: d10a bne.n 800e59e + /* found an existing, stable entry */ + ETHARP_SET_ADDRHINT(netif, i); + 800e588: 4a19 ldr r2, [pc, #100] ; (800e5f0 ) + 800e58a: 7dfb ldrb r3, [r7, #23] + 800e58c: 7013 strb r3, [r2, #0] + return etharp_output_to_arp_index(netif, q, i); + 800e58e: 7dfb ldrb r3, [r7, #23] + 800e590: 461a mov r2, r3 + 800e592: 68b9 ldr r1, [r7, #8] + 800e594: 68f8 ldr r0, [r7, #12] + 800e596: f7ff fe93 bl 800e2c0 + 800e59a: 4603 mov r3, r0 + 800e59c: e018 b.n 800e5d0 + for (i = 0; i < ARP_TABLE_SIZE; i++) { + 800e59e: 7dfb ldrb r3, [r7, #23] + 800e5a0: 3301 adds r3, #1 + 800e5a2: 75fb strb r3, [r7, #23] + 800e5a4: 7dfb ldrb r3, [r7, #23] + 800e5a6: 2b09 cmp r3, #9 + 800e5a8: d9ca bls.n 800e540 + } + } + /* no stable entry found, use the (slower) query function: + queue on destination Ethernet address belonging to ipaddr */ + return etharp_query(netif, dst_addr, q); + 800e5aa: 68ba ldr r2, [r7, #8] + 800e5ac: 69b9 ldr r1, [r7, #24] + 800e5ae: 68f8 ldr r0, [r7, #12] + 800e5b0: f000 f822 bl 800e5f8 + 800e5b4: 4603 mov r3, r0 + 800e5b6: e00b b.n 800e5d0 + } + + /* continuation for multicast/broadcast destinations */ + /* obtain source Ethernet address of the given interface */ + /* send packet directly on the link */ + return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP); + 800e5b8: 68fb ldr r3, [r7, #12] + 800e5ba: f103 0226 add.w r2, r3, #38 ; 0x26 + 800e5be: f44f 6300 mov.w r3, #2048 ; 0x800 + 800e5c2: 9300 str r3, [sp, #0] + 800e5c4: 69fb ldr r3, [r7, #28] + 800e5c6: 68b9 ldr r1, [r7, #8] + 800e5c8: 68f8 ldr r0, [r7, #12] + 800e5ca: f001 fe01 bl 80101d0 + 800e5ce: 4603 mov r3, r0 +} + 800e5d0: 4618 mov r0, r3 + 800e5d2: 3720 adds r7, #32 + 800e5d4: 46bd mov sp, r7 + 800e5d6: bd80 pop {r7, pc} + 800e5d8: 080142dc .word 0x080142dc + 800e5dc: 0801442c .word 0x0801442c + 800e5e0: 08014354 .word 0x08014354 + 800e5e4: 0801447c .word 0x0801447c + 800e5e8: 0801441c .word 0x0801441c + 800e5ec: 08014d98 .word 0x08014d98 + 800e5f0: 24007cc0 .word 0x24007cc0 + 800e5f4: 24007bd0 .word 0x24007bd0 + +0800e5f8 : + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + */ +err_t +etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q) +{ + 800e5f8: b580 push {r7, lr} + 800e5fa: b08c sub sp, #48 ; 0x30 + 800e5fc: af02 add r7, sp, #8 + 800e5fe: 60f8 str r0, [r7, #12] + 800e600: 60b9 str r1, [r7, #8] + 800e602: 607a str r2, [r7, #4] + struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr; + 800e604: 68fb ldr r3, [r7, #12] + 800e606: 3326 adds r3, #38 ; 0x26 + 800e608: 617b str r3, [r7, #20] + err_t result = ERR_MEM; + 800e60a: 23ff movs r3, #255 ; 0xff + 800e60c: f887 3027 strb.w r3, [r7, #39] ; 0x27 + int is_new_entry = 0; + 800e610: 2300 movs r3, #0 + 800e612: 623b str r3, [r7, #32] + s16_t i_err; + netif_addr_idx_t i; + + /* non-unicast address? */ + if (ip4_addr_isbroadcast(ipaddr, netif) || + 800e614: 68bb ldr r3, [r7, #8] + 800e616: 681b ldr r3, [r3, #0] + 800e618: 68f9 ldr r1, [r7, #12] + 800e61a: 4618 mov r0, r3 + 800e61c: f000 feca bl 800f3b4 + 800e620: 4603 mov r3, r0 + 800e622: 2b00 cmp r3, #0 + 800e624: d10c bne.n 800e640 + ip4_addr_ismulticast(ipaddr) || + 800e626: 68bb ldr r3, [r7, #8] + 800e628: 681b ldr r3, [r3, #0] + 800e62a: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if (ip4_addr_isbroadcast(ipaddr, netif) || + 800e62e: 2be0 cmp r3, #224 ; 0xe0 + 800e630: d006 beq.n 800e640 + ip4_addr_ismulticast(ipaddr) || + 800e632: 68bb ldr r3, [r7, #8] + 800e634: 2b00 cmp r3, #0 + 800e636: d003 beq.n 800e640 + ip4_addr_isany(ipaddr)) { + 800e638: 68bb ldr r3, [r7, #8] + 800e63a: 681b ldr r3, [r3, #0] + 800e63c: 2b00 cmp r3, #0 + 800e63e: d102 bne.n 800e646 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + 800e640: f06f 030f mvn.w r3, #15 + 800e644: e101 b.n 800e84a + } + + /* find entry in ARP cache, ask to create entry if queueing packet */ + i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif); + 800e646: 68fa ldr r2, [r7, #12] + 800e648: 2101 movs r1, #1 + 800e64a: 68b8 ldr r0, [r7, #8] + 800e64c: f7ff fb60 bl 800dd10 + 800e650: 4603 mov r3, r0 + 800e652: 827b strh r3, [r7, #18] + + /* could not find or create entry? */ + if (i_err < 0) { + 800e654: f9b7 3012 ldrsh.w r3, [r7, #18] + 800e658: 2b00 cmp r3, #0 + 800e65a: da02 bge.n 800e662 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); + if (q) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); + ETHARP_STATS_INC(etharp.memerr); + } + return (err_t)i_err; + 800e65c: 8a7b ldrh r3, [r7, #18] + 800e65e: b25b sxtb r3, r3 + 800e660: e0f3 b.n 800e84a + } + LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX); + 800e662: 8a7b ldrh r3, [r7, #18] + 800e664: 2b7e cmp r3, #126 ; 0x7e + 800e666: d906 bls.n 800e676 + 800e668: 4b7a ldr r3, [pc, #488] ; (800e854 ) + 800e66a: f240 32c1 movw r2, #961 ; 0x3c1 + 800e66e: 497a ldr r1, [pc, #488] ; (800e858 ) + 800e670: 487a ldr r0, [pc, #488] ; (800e85c ) + 800e672: f002 faa9 bl 8010bc8 + i = (netif_addr_idx_t)i_err; + 800e676: 8a7b ldrh r3, [r7, #18] + 800e678: 747b strb r3, [r7, #17] + + /* mark a fresh entry as pending (we just sent a request) */ + if (arp_table[i].state == ETHARP_STATE_EMPTY) { + 800e67a: 7c7a ldrb r2, [r7, #17] + 800e67c: 4978 ldr r1, [pc, #480] ; (800e860 ) + 800e67e: 4613 mov r3, r2 + 800e680: 005b lsls r3, r3, #1 + 800e682: 4413 add r3, r2 + 800e684: 00db lsls r3, r3, #3 + 800e686: 440b add r3, r1 + 800e688: 3314 adds r3, #20 + 800e68a: 781b ldrb r3, [r3, #0] + 800e68c: 2b00 cmp r3, #0 + 800e68e: d115 bne.n 800e6bc + is_new_entry = 1; + 800e690: 2301 movs r3, #1 + 800e692: 623b str r3, [r7, #32] + arp_table[i].state = ETHARP_STATE_PENDING; + 800e694: 7c7a ldrb r2, [r7, #17] + 800e696: 4972 ldr r1, [pc, #456] ; (800e860 ) + 800e698: 4613 mov r3, r2 + 800e69a: 005b lsls r3, r3, #1 + 800e69c: 4413 add r3, r2 + 800e69e: 00db lsls r3, r3, #3 + 800e6a0: 440b add r3, r1 + 800e6a2: 3314 adds r3, #20 + 800e6a4: 2201 movs r2, #1 + 800e6a6: 701a strb r2, [r3, #0] + /* record network interface for re-sending arp request in etharp_tmr */ + arp_table[i].netif = netif; + 800e6a8: 7c7a ldrb r2, [r7, #17] + 800e6aa: 496d ldr r1, [pc, #436] ; (800e860 ) + 800e6ac: 4613 mov r3, r2 + 800e6ae: 005b lsls r3, r3, #1 + 800e6b0: 4413 add r3, r2 + 800e6b2: 00db lsls r3, r3, #3 + 800e6b4: 440b add r3, r1 + 800e6b6: 3308 adds r3, #8 + 800e6b8: 68fa ldr r2, [r7, #12] + 800e6ba: 601a str r2, [r3, #0] + } + + /* { i is either a STABLE or (new or existing) PENDING entry } */ + LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", + 800e6bc: 7c7a ldrb r2, [r7, #17] + 800e6be: 4968 ldr r1, [pc, #416] ; (800e860 ) + 800e6c0: 4613 mov r3, r2 + 800e6c2: 005b lsls r3, r3, #1 + 800e6c4: 4413 add r3, r2 + 800e6c6: 00db lsls r3, r3, #3 + 800e6c8: 440b add r3, r1 + 800e6ca: 3314 adds r3, #20 + 800e6cc: 781b ldrb r3, [r3, #0] + 800e6ce: 2b01 cmp r3, #1 + 800e6d0: d011 beq.n 800e6f6 + 800e6d2: 7c7a ldrb r2, [r7, #17] + 800e6d4: 4962 ldr r1, [pc, #392] ; (800e860 ) + 800e6d6: 4613 mov r3, r2 + 800e6d8: 005b lsls r3, r3, #1 + 800e6da: 4413 add r3, r2 + 800e6dc: 00db lsls r3, r3, #3 + 800e6de: 440b add r3, r1 + 800e6e0: 3314 adds r3, #20 + 800e6e2: 781b ldrb r3, [r3, #0] + 800e6e4: 2b01 cmp r3, #1 + 800e6e6: d806 bhi.n 800e6f6 + 800e6e8: 4b5a ldr r3, [pc, #360] ; (800e854 ) + 800e6ea: f240 32cd movw r2, #973 ; 0x3cd + 800e6ee: 495d ldr r1, [pc, #372] ; (800e864 ) + 800e6f0: 485a ldr r0, [pc, #360] ; (800e85c ) + 800e6f2: f002 fa69 bl 8010bc8 + ((arp_table[i].state == ETHARP_STATE_PENDING) || + (arp_table[i].state >= ETHARP_STATE_STABLE))); + + /* do we have a new entry? or an implicit query request? */ + if (is_new_entry || (q == NULL)) { + 800e6f6: 6a3b ldr r3, [r7, #32] + 800e6f8: 2b00 cmp r3, #0 + 800e6fa: d102 bne.n 800e702 + 800e6fc: 687b ldr r3, [r7, #4] + 800e6fe: 2b00 cmp r3, #0 + 800e700: d10c bne.n 800e71c + /* try to resolve it; send out ARP request */ + result = etharp_request(netif, ipaddr); + 800e702: 68b9 ldr r1, [r7, #8] + 800e704: 68f8 ldr r0, [r7, #12] + 800e706: f000 f963 bl 800e9d0 + 800e70a: 4603 mov r3, r0 + 800e70c: f887 3027 strb.w r3, [r7, #39] ; 0x27 + /* ARP request couldn't be sent */ + /* We don't re-send arp request in etharp_tmr, but we still queue packets, + since this failure could be temporary, and the next packet calling + etharp_query again could lead to sending the queued packets. */ + } + if (q == NULL) { + 800e710: 687b ldr r3, [r7, #4] + 800e712: 2b00 cmp r3, #0 + 800e714: d102 bne.n 800e71c + return result; + 800e716: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 + 800e71a: e096 b.n 800e84a + } + } + + /* packet given? */ + LWIP_ASSERT("q != NULL", q != NULL); + 800e71c: 687b ldr r3, [r7, #4] + 800e71e: 2b00 cmp r3, #0 + 800e720: d106 bne.n 800e730 + 800e722: 4b4c ldr r3, [pc, #304] ; (800e854 ) + 800e724: f240 32e1 movw r2, #993 ; 0x3e1 + 800e728: 494f ldr r1, [pc, #316] ; (800e868 ) + 800e72a: 484c ldr r0, [pc, #304] ; (800e85c ) + 800e72c: f002 fa4c bl 8010bc8 + /* stable entry? */ + if (arp_table[i].state >= ETHARP_STATE_STABLE) { + 800e730: 7c7a ldrb r2, [r7, #17] + 800e732: 494b ldr r1, [pc, #300] ; (800e860 ) + 800e734: 4613 mov r3, r2 + 800e736: 005b lsls r3, r3, #1 + 800e738: 4413 add r3, r2 + 800e73a: 00db lsls r3, r3, #3 + 800e73c: 440b add r3, r1 + 800e73e: 3314 adds r3, #20 + 800e740: 781b ldrb r3, [r3, #0] + 800e742: 2b01 cmp r3, #1 + 800e744: d917 bls.n 800e776 + /* we have a valid IP->Ethernet address mapping */ + ETHARP_SET_ADDRHINT(netif, i); + 800e746: 4a49 ldr r2, [pc, #292] ; (800e86c ) + 800e748: 7c7b ldrb r3, [r7, #17] + 800e74a: 7013 strb r3, [r2, #0] + /* send the packet */ + result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP); + 800e74c: 7c7a ldrb r2, [r7, #17] + 800e74e: 4613 mov r3, r2 + 800e750: 005b lsls r3, r3, #1 + 800e752: 4413 add r3, r2 + 800e754: 00db lsls r3, r3, #3 + 800e756: 3308 adds r3, #8 + 800e758: 4a41 ldr r2, [pc, #260] ; (800e860 ) + 800e75a: 4413 add r3, r2 + 800e75c: 3304 adds r3, #4 + 800e75e: f44f 6200 mov.w r2, #2048 ; 0x800 + 800e762: 9200 str r2, [sp, #0] + 800e764: 697a ldr r2, [r7, #20] + 800e766: 6879 ldr r1, [r7, #4] + 800e768: 68f8 ldr r0, [r7, #12] + 800e76a: f001 fd31 bl 80101d0 + 800e76e: 4603 mov r3, r0 + 800e770: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800e774: e067 b.n 800e846 + /* pending entry? (either just created or already pending */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + 800e776: 7c7a ldrb r2, [r7, #17] + 800e778: 4939 ldr r1, [pc, #228] ; (800e860 ) + 800e77a: 4613 mov r3, r2 + 800e77c: 005b lsls r3, r3, #1 + 800e77e: 4413 add r3, r2 + 800e780: 00db lsls r3, r3, #3 + 800e782: 440b add r3, r1 + 800e784: 3314 adds r3, #20 + 800e786: 781b ldrb r3, [r3, #0] + 800e788: 2b01 cmp r3, #1 + 800e78a: d15c bne.n 800e846 + /* entry is still pending, queue the given packet 'q' */ + struct pbuf *p; + int copy_needed = 0; + 800e78c: 2300 movs r3, #0 + 800e78e: 61bb str r3, [r7, #24] + /* IF q includes a pbuf that must be copied, copy the whole chain into a + * new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */ + p = q; + 800e790: 687b ldr r3, [r7, #4] + 800e792: 61fb str r3, [r7, #28] + while (p) { + 800e794: e01c b.n 800e7d0 + LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); + 800e796: 69fb ldr r3, [r7, #28] + 800e798: 895a ldrh r2, [r3, #10] + 800e79a: 69fb ldr r3, [r7, #28] + 800e79c: 891b ldrh r3, [r3, #8] + 800e79e: 429a cmp r2, r3 + 800e7a0: d10a bne.n 800e7b8 + 800e7a2: 69fb ldr r3, [r7, #28] + 800e7a4: 681b ldr r3, [r3, #0] + 800e7a6: 2b00 cmp r3, #0 + 800e7a8: d006 beq.n 800e7b8 + 800e7aa: 4b2a ldr r3, [pc, #168] ; (800e854 ) + 800e7ac: f240 32f1 movw r2, #1009 ; 0x3f1 + 800e7b0: 492f ldr r1, [pc, #188] ; (800e870 ) + 800e7b2: 482a ldr r0, [pc, #168] ; (800e85c ) + 800e7b4: f002 fa08 bl 8010bc8 + if (PBUF_NEEDS_COPY(p)) { + 800e7b8: 69fb ldr r3, [r7, #28] + 800e7ba: 7b1b ldrb r3, [r3, #12] + 800e7bc: f003 0340 and.w r3, r3, #64 ; 0x40 + 800e7c0: 2b00 cmp r3, #0 + 800e7c2: d002 beq.n 800e7ca + copy_needed = 1; + 800e7c4: 2301 movs r3, #1 + 800e7c6: 61bb str r3, [r7, #24] + break; + 800e7c8: e005 b.n 800e7d6 + } + p = p->next; + 800e7ca: 69fb ldr r3, [r7, #28] + 800e7cc: 681b ldr r3, [r3, #0] + 800e7ce: 61fb str r3, [r7, #28] + while (p) { + 800e7d0: 69fb ldr r3, [r7, #28] + 800e7d2: 2b00 cmp r3, #0 + 800e7d4: d1df bne.n 800e796 + } + if (copy_needed) { + 800e7d6: 69bb ldr r3, [r7, #24] + 800e7d8: 2b00 cmp r3, #0 + 800e7da: d007 beq.n 800e7ec + /* copy the whole packet into new pbufs */ + p = pbuf_clone(PBUF_LINK, PBUF_RAM, q); + 800e7dc: 687a ldr r2, [r7, #4] + 800e7de: f44f 7120 mov.w r1, #640 ; 0x280 + 800e7e2: 200e movs r0, #14 + 800e7e4: f7f8 fe52 bl 800748c + 800e7e8: 61f8 str r0, [r7, #28] + 800e7ea: e004 b.n 800e7f6 + } else { + /* referencing the old pbuf is enough */ + p = q; + 800e7ec: 687b ldr r3, [r7, #4] + 800e7ee: 61fb str r3, [r7, #28] + pbuf_ref(p); + 800e7f0: 69f8 ldr r0, [r7, #28] + 800e7f2: f7f8 fc8f bl 8007114 + } + /* packet could be taken over? */ + if (p != NULL) { + 800e7f6: 69fb ldr r3, [r7, #28] + 800e7f8: 2b00 cmp r3, #0 + 800e7fa: d021 beq.n 800e840 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + } +#else /* ARP_QUEUEING */ + /* always queue one packet per ARP request only, freeing a previously queued packet */ + if (arp_table[i].q != NULL) { + 800e7fc: 7c7a ldrb r2, [r7, #17] + 800e7fe: 4918 ldr r1, [pc, #96] ; (800e860 ) + 800e800: 4613 mov r3, r2 + 800e802: 005b lsls r3, r3, #1 + 800e804: 4413 add r3, r2 + 800e806: 00db lsls r3, r3, #3 + 800e808: 440b add r3, r1 + 800e80a: 681b ldr r3, [r3, #0] + 800e80c: 2b00 cmp r3, #0 + 800e80e: d00a beq.n 800e826 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); + pbuf_free(arp_table[i].q); + 800e810: 7c7a ldrb r2, [r7, #17] + 800e812: 4913 ldr r1, [pc, #76] ; (800e860 ) + 800e814: 4613 mov r3, r2 + 800e816: 005b lsls r3, r3, #1 + 800e818: 4413 add r3, r2 + 800e81a: 00db lsls r3, r3, #3 + 800e81c: 440b add r3, r1 + 800e81e: 681b ldr r3, [r3, #0] + 800e820: 4618 mov r0, r3 + 800e822: f7f8 fbd7 bl 8006fd4 + } + arp_table[i].q = p; + 800e826: 7c7a ldrb r2, [r7, #17] + 800e828: 490d ldr r1, [pc, #52] ; (800e860 ) + 800e82a: 4613 mov r3, r2 + 800e82c: 005b lsls r3, r3, #1 + 800e82e: 4413 add r3, r2 + 800e830: 00db lsls r3, r3, #3 + 800e832: 440b add r3, r1 + 800e834: 69fa ldr r2, [r7, #28] + 800e836: 601a str r2, [r3, #0] + result = ERR_OK; + 800e838: 2300 movs r3, #0 + 800e83a: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800e83e: e002 b.n 800e846 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); +#endif /* ARP_QUEUEING */ + } else { + ETHARP_STATS_INC(etharp.memerr); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + 800e840: 23ff movs r3, #255 ; 0xff + 800e842: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + } + return result; + 800e846: f997 3027 ldrsb.w r3, [r7, #39] ; 0x27 +} + 800e84a: 4618 mov r0, r3 + 800e84c: 3728 adds r7, #40 ; 0x28 + 800e84e: 46bd mov sp, r7 + 800e850: bd80 pop {r7, pc} + 800e852: bf00 nop + 800e854: 080142dc .word 0x080142dc + 800e858: 08014488 .word 0x08014488 + 800e85c: 08014354 .word 0x08014354 + 800e860: 24007bd0 .word 0x24007bd0 + 800e864: 08014498 .word 0x08014498 + 800e868: 0801447c .word 0x0801447c + 800e86c: 24007cc0 .word 0x24007cc0 + 800e870: 080144c0 .word 0x080144c0 + +0800e874 : +etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr, + const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr, + const u16_t opcode) +{ + 800e874: b580 push {r7, lr} + 800e876: b08a sub sp, #40 ; 0x28 + 800e878: af02 add r7, sp, #8 + 800e87a: 60f8 str r0, [r7, #12] + 800e87c: 60b9 str r1, [r7, #8] + 800e87e: 607a str r2, [r7, #4] + 800e880: 603b str r3, [r7, #0] + struct pbuf *p; + err_t result = ERR_OK; + 800e882: 2300 movs r3, #0 + 800e884: 77fb strb r3, [r7, #31] + struct etharp_hdr *hdr; + + LWIP_ASSERT("netif != NULL", netif != NULL); + 800e886: 68fb ldr r3, [r7, #12] + 800e888: 2b00 cmp r3, #0 + 800e88a: d106 bne.n 800e89a + 800e88c: 4b3a ldr r3, [pc, #232] ; (800e978 ) + 800e88e: f240 4257 movw r2, #1111 ; 0x457 + 800e892: 493a ldr r1, [pc, #232] ; (800e97c ) + 800e894: 483a ldr r0, [pc, #232] ; (800e980 ) + 800e896: f002 f997 bl 8010bc8 + + /* allocate a pbuf for the outgoing ARP request packet */ + p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM); + 800e89a: f44f 7220 mov.w r2, #640 ; 0x280 + 800e89e: 211c movs r1, #28 + 800e8a0: 200e movs r0, #14 + 800e8a2: f7f8 f8b3 bl 8006a0c + 800e8a6: 61b8 str r0, [r7, #24] + /* could allocate a pbuf for an ARP request? */ + if (p == NULL) { + 800e8a8: 69bb ldr r3, [r7, #24] + 800e8aa: 2b00 cmp r3, #0 + 800e8ac: d102 bne.n 800e8b4 + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("etharp_raw: could not allocate pbuf for ARP request.\n")); + ETHARP_STATS_INC(etharp.memerr); + return ERR_MEM; + 800e8ae: f04f 33ff mov.w r3, #4294967295 + 800e8b2: e05d b.n 800e970 + } + LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", + 800e8b4: 69bb ldr r3, [r7, #24] + 800e8b6: 895b ldrh r3, [r3, #10] + 800e8b8: 2b1b cmp r3, #27 + 800e8ba: d806 bhi.n 800e8ca + 800e8bc: 4b2e ldr r3, [pc, #184] ; (800e978 ) + 800e8be: f240 4262 movw r2, #1122 ; 0x462 + 800e8c2: 4930 ldr r1, [pc, #192] ; (800e984 ) + 800e8c4: 482e ldr r0, [pc, #184] ; (800e980 ) + 800e8c6: f002 f97f bl 8010bc8 + (p->len >= SIZEOF_ETHARP_HDR)); + + hdr = (struct etharp_hdr *)p->payload; + 800e8ca: 69bb ldr r3, [r7, #24] + 800e8cc: 685b ldr r3, [r3, #4] + 800e8ce: 617b str r3, [r7, #20] + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); + hdr->opcode = lwip_htons(opcode); + 800e8d0: 8ebb ldrh r3, [r7, #52] ; 0x34 + 800e8d2: 4618 mov r0, r3 + 800e8d4: f7f6 fe3a bl 800554c + 800e8d8: 4603 mov r3, r0 + 800e8da: 461a mov r2, r3 + 800e8dc: 697b ldr r3, [r7, #20] + 800e8de: 80da strh r2, [r3, #6] + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!", + 800e8e0: 68fb ldr r3, [r7, #12] + 800e8e2: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 800e8e6: 2b06 cmp r3, #6 + 800e8e8: d006 beq.n 800e8f8 + 800e8ea: 4b23 ldr r3, [pc, #140] ; (800e978 ) + 800e8ec: f240 4269 movw r2, #1129 ; 0x469 + 800e8f0: 4925 ldr r1, [pc, #148] ; (800e988 ) + 800e8f2: 4823 ldr r0, [pc, #140] ; (800e980 ) + 800e8f4: f002 f968 bl 8010bc8 + (netif->hwaddr_len == ETH_HWADDR_LEN)); + + /* Write the ARP MAC-Addresses */ + SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN); + 800e8f8: 697b ldr r3, [r7, #20] + 800e8fa: 3308 adds r3, #8 + 800e8fc: 2206 movs r2, #6 + 800e8fe: 6839 ldr r1, [r7, #0] + 800e900: 4618 mov r0, r3 + 800e902: f002 fb42 bl 8010f8a + SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN); + 800e906: 697b ldr r3, [r7, #20] + 800e908: 3312 adds r3, #18 + 800e90a: 2206 movs r2, #6 + 800e90c: 6af9 ldr r1, [r7, #44] ; 0x2c + 800e90e: 4618 mov r0, r3 + 800e910: f002 fb3b bl 8010f8a + /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without + * structure packing. */ + IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr); + 800e914: 697b ldr r3, [r7, #20] + 800e916: 330e adds r3, #14 + 800e918: 6aba ldr r2, [r7, #40] ; 0x28 + 800e91a: 6812 ldr r2, [r2, #0] + 800e91c: 601a str r2, [r3, #0] + IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr); + 800e91e: 697b ldr r3, [r7, #20] + 800e920: 3318 adds r3, #24 + 800e922: 6b3a ldr r2, [r7, #48] ; 0x30 + 800e924: 6812 ldr r2, [r2, #0] + 800e926: 601a str r2, [r3, #0] + + hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET); + 800e928: 697b ldr r3, [r7, #20] + 800e92a: 2200 movs r2, #0 + 800e92c: 701a strb r2, [r3, #0] + 800e92e: 2200 movs r2, #0 + 800e930: f042 0201 orr.w r2, r2, #1 + 800e934: 705a strb r2, [r3, #1] + hdr->proto = PP_HTONS(ETHTYPE_IP); + 800e936: 697b ldr r3, [r7, #20] + 800e938: 2200 movs r2, #0 + 800e93a: f042 0208 orr.w r2, r2, #8 + 800e93e: 709a strb r2, [r3, #2] + 800e940: 2200 movs r2, #0 + 800e942: 70da strb r2, [r3, #3] + /* set hwlen and protolen */ + hdr->hwlen = ETH_HWADDR_LEN; + 800e944: 697b ldr r3, [r7, #20] + 800e946: 2206 movs r2, #6 + 800e948: 711a strb r2, [r3, #4] + hdr->protolen = sizeof(ip4_addr_t); + 800e94a: 697b ldr r3, [r7, #20] + 800e94c: 2204 movs r2, #4 + 800e94e: 715a strb r2, [r3, #5] + if (ip4_addr_islinklocal(ipsrc_addr)) { + ethernet_output(netif, p, ethsrc_addr, ðbroadcast, ETHTYPE_ARP); + } else +#endif /* LWIP_AUTOIP */ + { + ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP); + 800e950: f640 0306 movw r3, #2054 ; 0x806 + 800e954: 9300 str r3, [sp, #0] + 800e956: 687b ldr r3, [r7, #4] + 800e958: 68ba ldr r2, [r7, #8] + 800e95a: 69b9 ldr r1, [r7, #24] + 800e95c: 68f8 ldr r0, [r7, #12] + 800e95e: f001 fc37 bl 80101d0 + } + + ETHARP_STATS_INC(etharp.xmit); + /* free ARP query packet */ + pbuf_free(p); + 800e962: 69b8 ldr r0, [r7, #24] + 800e964: f7f8 fb36 bl 8006fd4 + p = NULL; + 800e968: 2300 movs r3, #0 + 800e96a: 61bb str r3, [r7, #24] + /* could not allocate pbuf for ARP request */ + + return result; + 800e96c: f997 301f ldrsb.w r3, [r7, #31] +} + 800e970: 4618 mov r0, r3 + 800e972: 3720 adds r7, #32 + 800e974: 46bd mov sp, r7 + 800e976: bd80 pop {r7, pc} + 800e978: 080142dc .word 0x080142dc + 800e97c: 0801442c .word 0x0801442c + 800e980: 08014354 .word 0x08014354 + 800e984: 080144dc .word 0x080144dc + 800e988: 08014510 .word 0x08014510 + +0800e98c : + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +static err_t +etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr) +{ + 800e98c: b580 push {r7, lr} + 800e98e: b088 sub sp, #32 + 800e990: af04 add r7, sp, #16 + 800e992: 60f8 str r0, [r7, #12] + 800e994: 60b9 str r1, [r7, #8] + 800e996: 607a str r2, [r7, #4] + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, + 800e998: 68fb ldr r3, [r7, #12] + 800e99a: f103 0126 add.w r1, r3, #38 ; 0x26 + (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), ðzero, + 800e99e: 68fb ldr r3, [r7, #12] + 800e9a0: f103 0026 add.w r0, r3, #38 ; 0x26 + 800e9a4: 68fb ldr r3, [r7, #12] + 800e9a6: 3304 adds r3, #4 + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, + 800e9a8: 2201 movs r2, #1 + 800e9aa: 9203 str r2, [sp, #12] + 800e9ac: 68ba ldr r2, [r7, #8] + 800e9ae: 9202 str r2, [sp, #8] + 800e9b0: 4a06 ldr r2, [pc, #24] ; (800e9cc ) + 800e9b2: 9201 str r2, [sp, #4] + 800e9b4: 9300 str r3, [sp, #0] + 800e9b6: 4603 mov r3, r0 + 800e9b8: 687a ldr r2, [r7, #4] + 800e9ba: 68f8 ldr r0, [r7, #12] + 800e9bc: f7ff ff5a bl 800e874 + 800e9c0: 4603 mov r3, r0 + ipaddr, ARP_REQUEST); +} + 800e9c2: 4618 mov r0, r3 + 800e9c4: 3710 adds r7, #16 + 800e9c6: 46bd mov sp, r7 + 800e9c8: bd80 pop {r7, pc} + 800e9ca: bf00 nop + 800e9cc: 08014da0 .word 0x08014da0 + +0800e9d0 : + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +err_t +etharp_request(struct netif *netif, const ip4_addr_t *ipaddr) +{ + 800e9d0: b580 push {r7, lr} + 800e9d2: b082 sub sp, #8 + 800e9d4: af00 add r7, sp, #0 + 800e9d6: 6078 str r0, [r7, #4] + 800e9d8: 6039 str r1, [r7, #0] + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); + return etharp_request_dst(netif, ipaddr, ðbroadcast); + 800e9da: 4a05 ldr r2, [pc, #20] ; (800e9f0 ) + 800e9dc: 6839 ldr r1, [r7, #0] + 800e9de: 6878 ldr r0, [r7, #4] + 800e9e0: f7ff ffd4 bl 800e98c + 800e9e4: 4603 mov r3, r0 +} + 800e9e6: 4618 mov r0, r3 + 800e9e8: 3708 adds r7, #8 + 800e9ea: 46bd mov sp, r7 + 800e9ec: bd80 pop {r7, pc} + 800e9ee: bf00 nop + 800e9f0: 08014d98 .word 0x08014d98 + +0800e9f4 : + * @param p the icmp echo request packet, p->payload pointing to the icmp header + * @param inp the netif on which this packet was received + */ +void +icmp_input(struct pbuf *p, struct netif *inp) +{ + 800e9f4: b580 push {r7, lr} + 800e9f6: b08e sub sp, #56 ; 0x38 + 800e9f8: af04 add r7, sp, #16 + 800e9fa: 6078 str r0, [r7, #4] + 800e9fc: 6039 str r1, [r7, #0] + const ip4_addr_t *src; + + ICMP_STATS_INC(icmp.recv); + MIB2_STATS_INC(mib2.icmpinmsgs); + + iphdr_in = ip4_current_header(); + 800e9fe: 4ba4 ldr r3, [pc, #656] ; (800ec90 ) + 800ea00: 689b ldr r3, [r3, #8] + 800ea02: 627b str r3, [r7, #36] ; 0x24 + hlen = IPH_HL_BYTES(iphdr_in); + 800ea04: 6a7b ldr r3, [r7, #36] ; 0x24 + 800ea06: 781b ldrb r3, [r3, #0] + 800ea08: f003 030f and.w r3, r3, #15 + 800ea0c: b2db uxtb r3, r3 + 800ea0e: 009b lsls r3, r3, #2 + 800ea10: b2db uxtb r3, r3 + 800ea12: 847b strh r3, [r7, #34] ; 0x22 + if (hlen < IP_HLEN) { + 800ea14: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800ea16: 2b13 cmp r3, #19 + 800ea18: d805 bhi.n 800ea26 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen)); + 800ea1a: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800ea1c: 4619 mov r1, r3 + 800ea1e: 489d ldr r0, [pc, #628] ; (800ec94 ) + 800ea20: f002 f8d2 bl 8010bc8 + goto lenerr; + 800ea24: e128 b.n 800ec78 + } + if (p->len < sizeof(u16_t) * 2) { + 800ea26: 687b ldr r3, [r7, #4] + 800ea28: 895b ldrh r3, [r3, #10] + 800ea2a: 2b03 cmp r3, #3 + 800ea2c: d806 bhi.n 800ea3c + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); + 800ea2e: 687b ldr r3, [r7, #4] + 800ea30: 891b ldrh r3, [r3, #8] + 800ea32: 4619 mov r1, r3 + 800ea34: 4898 ldr r0, [pc, #608] ; (800ec98 ) + 800ea36: f002 f8c7 bl 8010bc8 + goto lenerr; + 800ea3a: e11d b.n 800ec78 + } + + type = *((u8_t *)p->payload); + 800ea3c: 687b ldr r3, [r7, #4] + 800ea3e: 685b ldr r3, [r3, #4] + 800ea40: 781b ldrb r3, [r3, #0] + 800ea42: f887 3021 strb.w r3, [r7, #33] ; 0x21 +#ifdef LWIP_DEBUG + code = *(((u8_t *)p->payload) + 1); + 800ea46: 687b ldr r3, [r7, #4] + 800ea48: 685b ldr r3, [r3, #4] + 800ea4a: 785b ldrb r3, [r3, #1] + 800ea4c: f887 3020 strb.w r3, [r7, #32] + /* if debug is enabled but debug statement below is somehow disabled: */ + LWIP_UNUSED_ARG(code); +#endif /* LWIP_DEBUG */ + switch (type) { + 800ea50: f897 3021 ldrb.w r3, [r7, #33] ; 0x21 + 800ea54: 2b00 cmp r3, #0 + 800ea56: f000 8108 beq.w 800ec6a + 800ea5a: 2b08 cmp r3, #8 + 800ea5c: f040 80fc bne.w 800ec58 + (as obviously, an echo request has been sent, too). */ + MIB2_STATS_INC(mib2.icmpinechoreps); + break; + case ICMP_ECHO: + MIB2_STATS_INC(mib2.icmpinechos); + src = ip4_current_dest_addr(); + 800ea60: 4b8e ldr r3, [pc, #568] ; (800ec9c ) + 800ea62: 61fb str r3, [r7, #28] + /* multicast destination address? */ + if (ip4_addr_ismulticast(ip4_current_dest_addr())) { + 800ea64: 4b8a ldr r3, [pc, #552] ; (800ec90 ) + 800ea66: 695b ldr r3, [r3, #20] + 800ea68: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800ea6c: 2be0 cmp r3, #224 ; 0xe0 + 800ea6e: d103 bne.n 800ea78 +#if LWIP_MULTICAST_PING + /* For multicast, use address of receiving interface as source address */ + src = netif_ip4_addr(inp); +#else /* LWIP_MULTICAST_PING */ + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n")); + 800ea70: 488b ldr r0, [pc, #556] ; (800eca0 ) + 800ea72: f002 f917 bl 8010ca4 + goto icmperr; + 800ea76: e103 b.n 800ec80 +#endif /* LWIP_MULTICAST_PING */ + } + /* broadcast destination address? */ + if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) { + 800ea78: 4b85 ldr r3, [pc, #532] ; (800ec90 ) + 800ea7a: 695b ldr r3, [r3, #20] + 800ea7c: 4a84 ldr r2, [pc, #528] ; (800ec90 ) + 800ea7e: 6812 ldr r2, [r2, #0] + 800ea80: 4611 mov r1, r2 + 800ea82: 4618 mov r0, r3 + 800ea84: f000 fc96 bl 800f3b4 + 800ea88: 4603 mov r3, r0 + 800ea8a: 2b00 cmp r3, #0 + 800ea8c: d003 beq.n 800ea96 +#if LWIP_BROADCAST_PING + /* For broadcast, use address of receiving interface as source address */ + src = netif_ip4_addr(inp); +#else /* LWIP_BROADCAST_PING */ + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n")); + 800ea8e: 4885 ldr r0, [pc, #532] ; (800eca4 ) + 800ea90: f002 f908 bl 8010ca4 + goto icmperr; + 800ea94: e0f4 b.n 800ec80 +#endif /* LWIP_BROADCAST_PING */ + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); + 800ea96: 4884 ldr r0, [pc, #528] ; (800eca8 ) + 800ea98: f002 f904 bl 8010ca4 + if (p->tot_len < sizeof(struct icmp_echo_hdr)) { + 800ea9c: 687b ldr r3, [r7, #4] + 800ea9e: 891b ldrh r3, [r3, #8] + 800eaa0: 2b07 cmp r3, #7 + 800eaa2: d803 bhi.n 800eaac + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); + 800eaa4: 4881 ldr r0, [pc, #516] ; (800ecac ) + 800eaa6: f002 f8fd bl 8010ca4 + goto lenerr; + 800eaaa: e0e5 b.n 800ec78 + } +#if CHECKSUM_CHECK_ICMP + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP) { + if (inet_chksum_pbuf(p) != 0) { + 800eaac: 6878 ldr r0, [r7, #4] + 800eaae: f7f6 fdea bl 8005686 + 800eab2: 4603 mov r3, r0 + 800eab4: 2b00 cmp r3, #0 + 800eab6: d006 beq.n 800eac6 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); + 800eab8: 487d ldr r0, [pc, #500] ; (800ecb0 ) + 800eaba: f002 f8f3 bl 8010ca4 + pbuf_free(p); + 800eabe: 6878 ldr r0, [r7, #4] + 800eac0: f7f8 fa88 bl 8006fd4 + ICMP_STATS_INC(icmp.chkerr); + MIB2_STATS_INC(mib2.icmpinerrors); + return; + 800eac4: e0e0 b.n 800ec88 + } + } +#endif +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN + if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { + 800eac6: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800eac8: 330e adds r3, #14 + 800eaca: 4619 mov r1, r3 + 800eacc: 6878 ldr r0, [r7, #4] + 800eace: f7f8 f9eb bl 8006ea8 + 800ead2: 4603 mov r3, r0 + 800ead4: 2b00 cmp r3, #0 + 800ead6: d057 beq.n 800eb88 + /* p is not big enough to contain link headers + * allocate a new one and copy p into it + */ + struct pbuf *r; + u16_t alloc_len = (u16_t)(p->tot_len + hlen); + 800ead8: 687b ldr r3, [r7, #4] + 800eada: 891a ldrh r2, [r3, #8] + 800eadc: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800eade: 4413 add r3, r2 + 800eae0: 837b strh r3, [r7, #26] + if (alloc_len < p->tot_len) { + 800eae2: 687b ldr r3, [r7, #4] + 800eae4: 891b ldrh r3, [r3, #8] + 800eae6: 8b7a ldrh r2, [r7, #26] + 800eae8: 429a cmp r2, r3 + 800eaea: d203 bcs.n 800eaf4 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n")); + 800eaec: 4871 ldr r0, [pc, #452] ; (800ecb4 ) + 800eaee: f002 f8d9 bl 8010ca4 + goto icmperr; + 800eaf2: e0c5 b.n 800ec80 + } + /* allocate new packet buffer with space for link headers */ + r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM); + 800eaf4: 8b7b ldrh r3, [r7, #26] + 800eaf6: f44f 7220 mov.w r2, #640 ; 0x280 + 800eafa: 4619 mov r1, r3 + 800eafc: 200e movs r0, #14 + 800eafe: f7f7 ff85 bl 8006a0c + 800eb02: 6178 str r0, [r7, #20] + if (r == NULL) { + 800eb04: 697b ldr r3, [r7, #20] + 800eb06: 2b00 cmp r3, #0 + 800eb08: d103 bne.n 800eb12 + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n")); + 800eb0a: 486b ldr r0, [pc, #428] ; (800ecb8 ) + 800eb0c: f002 f8ca bl 8010ca4 + goto icmperr; + 800eb10: e0b6 b.n 800ec80 + } + if (r->len < hlen + sizeof(struct icmp_echo_hdr)) { + 800eb12: 697b ldr r3, [r7, #20] + 800eb14: 895b ldrh r3, [r3, #10] + 800eb16: 461a mov r2, r3 + 800eb18: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800eb1a: 3308 adds r3, #8 + 800eb1c: 429a cmp r2, r3 + 800eb1e: d206 bcs.n 800eb2e + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header")); + 800eb20: 4866 ldr r0, [pc, #408] ; (800ecbc ) + 800eb22: f002 f851 bl 8010bc8 + pbuf_free(r); + 800eb26: 6978 ldr r0, [r7, #20] + 800eb28: f7f8 fa54 bl 8006fd4 + goto icmperr; + 800eb2c: e0a8 b.n 800ec80 + } + /* copy the ip header */ + MEMCPY(r->payload, iphdr_in, hlen); + 800eb2e: 697b ldr r3, [r7, #20] + 800eb30: 685b ldr r3, [r3, #4] + 800eb32: 8c7a ldrh r2, [r7, #34] ; 0x22 + 800eb34: 6a79 ldr r1, [r7, #36] ; 0x24 + 800eb36: 4618 mov r0, r3 + 800eb38: f002 fa27 bl 8010f8a + /* switch r->payload back to icmp header (cannot fail) */ + if (pbuf_remove_header(r, hlen)) { + 800eb3c: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800eb3e: 4619 mov r1, r3 + 800eb40: 6978 ldr r0, [r7, #20] + 800eb42: f7f8 f9c1 bl 8006ec8 + 800eb46: 4603 mov r3, r0 + 800eb48: 2b00 cmp r3, #0 + 800eb4a: d009 beq.n 800eb60 + LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0); + 800eb4c: 4b5c ldr r3, [pc, #368] ; (800ecc0 ) + 800eb4e: 22b6 movs r2, #182 ; 0xb6 + 800eb50: 495c ldr r1, [pc, #368] ; (800ecc4 ) + 800eb52: 485d ldr r0, [pc, #372] ; (800ecc8 ) + 800eb54: f002 f838 bl 8010bc8 + pbuf_free(r); + 800eb58: 6978 ldr r0, [r7, #20] + 800eb5a: f7f8 fa3b bl 8006fd4 + goto icmperr; + 800eb5e: e08f b.n 800ec80 + } + /* copy the rest of the packet without ip header */ + if (pbuf_copy(r, p) != ERR_OK) { + 800eb60: 6879 ldr r1, [r7, #4] + 800eb62: 6978 ldr r0, [r7, #20] + 800eb64: f7f8 fb4e bl 8007204 + 800eb68: 4603 mov r3, r0 + 800eb6a: 2b00 cmp r3, #0 + 800eb6c: d006 beq.n 800eb7c + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed")); + 800eb6e: 4857 ldr r0, [pc, #348] ; (800eccc ) + 800eb70: f002 f82a bl 8010bc8 + pbuf_free(r); + 800eb74: 6978 ldr r0, [r7, #20] + 800eb76: f7f8 fa2d bl 8006fd4 + goto icmperr; + 800eb7a: e081 b.n 800ec80 + } + /* free the original p */ + pbuf_free(p); + 800eb7c: 6878 ldr r0, [r7, #4] + 800eb7e: f7f8 fa29 bl 8006fd4 + /* we now have an identical copy of p that has room for link headers */ + p = r; + 800eb82: 697b ldr r3, [r7, #20] + 800eb84: 607b str r3, [r7, #4] + 800eb86: e00f b.n 800eba8 + } else { + /* restore p->payload to point to icmp header (cannot fail) */ + if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { + 800eb88: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800eb8a: 330e adds r3, #14 + 800eb8c: 4619 mov r1, r3 + 800eb8e: 6878 ldr r0, [r7, #4] + 800eb90: f7f8 f99a bl 8006ec8 + 800eb94: 4603 mov r3, r0 + 800eb96: 2b00 cmp r3, #0 + 800eb98: d006 beq.n 800eba8 + LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); + 800eb9a: 4b49 ldr r3, [pc, #292] ; (800ecc0 ) + 800eb9c: 22c7 movs r2, #199 ; 0xc7 + 800eb9e: 494c ldr r1, [pc, #304] ; (800ecd0 ) + 800eba0: 4849 ldr r0, [pc, #292] ; (800ecc8 ) + 800eba2: f002 f811 bl 8010bc8 + goto icmperr; + 800eba6: e06b b.n 800ec80 + } +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ + /* At this point, all checks are OK. */ + /* We generate an answer by switching the dest and src ip addresses, + * setting the icmp type to ECHO_RESPONSE and updating the checksum. */ + iecho = (struct icmp_echo_hdr *)p->payload; + 800eba8: 687b ldr r3, [r7, #4] + 800ebaa: 685b ldr r3, [r3, #4] + 800ebac: 613b str r3, [r7, #16] + if (pbuf_add_header(p, hlen)) { + 800ebae: 8c7b ldrh r3, [r7, #34] ; 0x22 + 800ebb0: 4619 mov r1, r3 + 800ebb2: 6878 ldr r0, [r7, #4] + 800ebb4: f7f8 f978 bl 8006ea8 + 800ebb8: 4603 mov r3, r0 + 800ebba: 2b00 cmp r3, #0 + 800ebbc: d003 beq.n 800ebc6 + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet")); + 800ebbe: 4845 ldr r0, [pc, #276] ; (800ecd4 ) + 800ebc0: f002 f802 bl 8010bc8 + ICMP_TTL, 0, IP_PROTO_ICMP, inp); + if (ret != ERR_OK) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret))); + } + } + break; + 800ebc4: e053 b.n 800ec6e + struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; + 800ebc6: 687b ldr r3, [r7, #4] + 800ebc8: 685b ldr r3, [r3, #4] + 800ebca: 60fb str r3, [r7, #12] + ip4_addr_copy(iphdr->src, *src); + 800ebcc: 69fb ldr r3, [r7, #28] + 800ebce: 681a ldr r2, [r3, #0] + 800ebd0: 68fb ldr r3, [r7, #12] + 800ebd2: 60da str r2, [r3, #12] + ip4_addr_copy(iphdr->dest, *ip4_current_src_addr()); + 800ebd4: 4b2e ldr r3, [pc, #184] ; (800ec90 ) + 800ebd6: 691a ldr r2, [r3, #16] + 800ebd8: 68fb ldr r3, [r7, #12] + 800ebda: 611a str r2, [r3, #16] + ICMPH_TYPE_SET(iecho, ICMP_ER); + 800ebdc: 693b ldr r3, [r7, #16] + 800ebde: 2200 movs r2, #0 + 800ebe0: 701a strb r2, [r3, #0] + if (iecho->chksum > PP_HTONS(0xffffU - (ICMP_ECHO << 8))) { + 800ebe2: 693b ldr r3, [r7, #16] + 800ebe4: 885b ldrh r3, [r3, #2] + 800ebe6: b29b uxth r3, r3 + 800ebe8: f64f 72f7 movw r2, #65527 ; 0xfff7 + 800ebec: 4293 cmp r3, r2 + 800ebee: d907 bls.n 800ec00 + iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS((u16_t)(ICMP_ECHO << 8)) + 1); + 800ebf0: 693b ldr r3, [r7, #16] + 800ebf2: 885b ldrh r3, [r3, #2] + 800ebf4: b29b uxth r3, r3 + 800ebf6: 3309 adds r3, #9 + 800ebf8: b29a uxth r2, r3 + 800ebfa: 693b ldr r3, [r7, #16] + 800ebfc: 805a strh r2, [r3, #2] + 800ebfe: e006 b.n 800ec0e + iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS(ICMP_ECHO << 8)); + 800ec00: 693b ldr r3, [r7, #16] + 800ec02: 885b ldrh r3, [r3, #2] + 800ec04: b29b uxth r3, r3 + 800ec06: 3308 adds r3, #8 + 800ec08: b29a uxth r2, r3 + 800ec0a: 693b ldr r3, [r7, #16] + 800ec0c: 805a strh r2, [r3, #2] + IPH_TTL_SET(iphdr, ICMP_TTL); + 800ec0e: 68fb ldr r3, [r7, #12] + 800ec10: 22ff movs r2, #255 ; 0xff + 800ec12: 721a strb r2, [r3, #8] + IPH_CHKSUM_SET(iphdr, 0); + 800ec14: 68fb ldr r3, [r7, #12] + 800ec16: 2200 movs r2, #0 + 800ec18: 729a strb r2, [r3, #10] + 800ec1a: 2200 movs r2, #0 + 800ec1c: 72da strb r2, [r3, #11] + ret = ip4_output_if(p, src, LWIP_IP_HDRINCL, + 800ec1e: 683b ldr r3, [r7, #0] + 800ec20: 9302 str r3, [sp, #8] + 800ec22: 2301 movs r3, #1 + 800ec24: 9301 str r3, [sp, #4] + 800ec26: 2300 movs r3, #0 + 800ec28: 9300 str r3, [sp, #0] + 800ec2a: 23ff movs r3, #255 ; 0xff + 800ec2c: 2200 movs r2, #0 + 800ec2e: 69f9 ldr r1, [r7, #28] + 800ec30: 6878 ldr r0, [r7, #4] + 800ec32: f000 fae7 bl 800f204 + 800ec36: 4603 mov r3, r0 + 800ec38: 72fb strb r3, [r7, #11] + if (ret != ERR_OK) { + 800ec3a: f997 300b ldrsb.w r3, [r7, #11] + 800ec3e: 2b00 cmp r3, #0 + 800ec40: d015 beq.n 800ec6e + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret))); + 800ec42: f997 300b ldrsb.w r3, [r7, #11] + 800ec46: 4618 mov r0, r3 + 800ec48: f7f6 fc60 bl 800550c + 800ec4c: 4603 mov r3, r0 + 800ec4e: 4619 mov r1, r3 + 800ec50: 4821 ldr r0, [pc, #132] ; (800ecd8 ) + 800ec52: f001 ffb9 bl 8010bc8 + break; + 800ec56: e00a b.n 800ec6e + } else if (type == ICMP_AM) { + MIB2_STATS_INC(mib2.icmpinaddrmasks); + } else if (type == ICMP_AMR) { + MIB2_STATS_INC(mib2.icmpinaddrmaskreps); + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", + 800ec58: f897 3021 ldrb.w r3, [r7, #33] ; 0x21 + 800ec5c: f897 2020 ldrb.w r2, [r7, #32] + 800ec60: 4619 mov r1, r3 + 800ec62: 481e ldr r0, [pc, #120] ; (800ecdc ) + 800ec64: f001 ffb0 bl 8010bc8 + 800ec68: e002 b.n 800ec70 + break; + 800ec6a: bf00 nop + 800ec6c: e000 b.n 800ec70 + break; + 800ec6e: bf00 nop + (s16_t)type, (s16_t)code)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } + pbuf_free(p); + 800ec70: 6878 ldr r0, [r7, #4] + 800ec72: f7f8 f9af bl 8006fd4 + return; + 800ec76: e007 b.n 800ec88 +lenerr: + pbuf_free(p); + 800ec78: 6878 ldr r0, [r7, #4] + 800ec7a: f7f8 f9ab bl 8006fd4 + ICMP_STATS_INC(icmp.lenerr); + MIB2_STATS_INC(mib2.icmpinerrors); + return; + 800ec7e: e003 b.n 800ec88 +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING +icmperr: + pbuf_free(p); + 800ec80: 6878 ldr r0, [r7, #4] + 800ec82: f7f8 f9a7 bl 8006fd4 + ICMP_STATS_INC(icmp.err); + MIB2_STATS_INC(mib2.icmpinerrors); + return; + 800ec86: bf00 nop +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */ +} + 800ec88: 3728 adds r7, #40 ; 0x28 + 800ec8a: 46bd mov sp, r7 + 800ec8c: bd80 pop {r7, pc} + 800ec8e: bf00 nop + 800ec90: 24004c10 .word 0x24004c10 + 800ec94: 08014554 .word 0x08014554 + 800ec98: 08014588 .word 0x08014588 + 800ec9c: 24004c24 .word 0x24004c24 + 800eca0: 080145b8 .word 0x080145b8 + 800eca4: 080145e4 .word 0x080145e4 + 800eca8: 08014610 .word 0x08014610 + 800ecac: 08014624 .word 0x08014624 + 800ecb0: 08014648 .word 0x08014648 + 800ecb4: 0801467c .word 0x0801467c + 800ecb8: 080146b8 .word 0x080146b8 + 800ecbc: 080146e0 .word 0x080146e0 + 800ecc0: 08014708 .word 0x08014708 + 800ecc4: 08014740 .word 0x08014740 + 800ecc8: 08014778 .word 0x08014778 + 800eccc: 080147a0 .word 0x080147a0 + 800ecd0: 080147c8 .word 0x080147c8 + 800ecd4: 080147fc .word 0x080147fc + 800ecd8: 08014820 .word 0x08014820 + 800ecdc: 08014850 .word 0x08014850 + +0800ece0 : + * p->payload pointing to the IP header + * @param t type of the 'unreachable' packet + */ +void +icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) +{ + 800ece0: b580 push {r7, lr} + 800ece2: b082 sub sp, #8 + 800ece4: af00 add r7, sp, #0 + 800ece6: 6078 str r0, [r7, #4] + 800ece8: 460b mov r3, r1 + 800ecea: 70fb strb r3, [r7, #3] + MIB2_STATS_INC(mib2.icmpoutdestunreachs); + icmp_send_response(p, ICMP_DUR, t); + 800ecec: 78fb ldrb r3, [r7, #3] + 800ecee: 461a mov r2, r3 + 800ecf0: 2103 movs r1, #3 + 800ecf2: 6878 ldr r0, [r7, #4] + 800ecf4: f000 f814 bl 800ed20 +} + 800ecf8: bf00 nop + 800ecfa: 3708 adds r7, #8 + 800ecfc: 46bd mov sp, r7 + 800ecfe: bd80 pop {r7, pc} + +0800ed00 : + * p->payload pointing to the IP header + * @param t type of the 'time exceeded' packet + */ +void +icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) +{ + 800ed00: b580 push {r7, lr} + 800ed02: b082 sub sp, #8 + 800ed04: af00 add r7, sp, #0 + 800ed06: 6078 str r0, [r7, #4] + 800ed08: 460b mov r3, r1 + 800ed0a: 70fb strb r3, [r7, #3] + MIB2_STATS_INC(mib2.icmpouttimeexcds); + icmp_send_response(p, ICMP_TE, t); + 800ed0c: 78fb ldrb r3, [r7, #3] + 800ed0e: 461a mov r2, r3 + 800ed10: 210b movs r1, #11 + 800ed12: 6878 ldr r0, [r7, #4] + 800ed14: f000 f804 bl 800ed20 +} + 800ed18: bf00 nop + 800ed1a: 3708 adds r7, #8 + 800ed1c: 46bd mov sp, r7 + 800ed1e: bd80 pop {r7, pc} + +0800ed20 : + * @param type Type of the ICMP header + * @param code Code of the ICMP header + */ +static void +icmp_send_response(struct pbuf *p, u8_t type, u8_t code) +{ + 800ed20: b580 push {r7, lr} + 800ed22: b08c sub sp, #48 ; 0x30 + 800ed24: af04 add r7, sp, #16 + 800ed26: 6078 str r0, [r7, #4] + 800ed28: 460b mov r3, r1 + 800ed2a: 70fb strb r3, [r7, #3] + 800ed2c: 4613 mov r3, r2 + 800ed2e: 70bb strb r3, [r7, #2] + + /* increase number of messages attempted to send */ + MIB2_STATS_INC(mib2.icmpoutmsgs); + + /* ICMP header + IP header + 8 bytes of data */ + q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE, + 800ed30: f44f 7220 mov.w r2, #640 ; 0x280 + 800ed34: 2124 movs r1, #36 ; 0x24 + 800ed36: 2022 movs r0, #34 ; 0x22 + 800ed38: f7f7 fe68 bl 8006a0c + 800ed3c: 61f8 str r0, [r7, #28] + PBUF_RAM); + if (q == NULL) { + 800ed3e: 69fb ldr r3, [r7, #28] + 800ed40: 2b00 cmp r3, #0 + 800ed42: d103 bne.n 800ed4c + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n")); + 800ed44: 4849 ldr r0, [pc, #292] ; (800ee6c ) + 800ed46: f001 ffad bl 8010ca4 + 800ed4a: e08c b.n 800ee66 + MIB2_STATS_INC(mib2.icmpouterrors); + return; + } + LWIP_ASSERT("check that first pbuf can hold icmp message", + 800ed4c: 69fb ldr r3, [r7, #28] + 800ed4e: 895b ldrh r3, [r3, #10] + 800ed50: 2b23 cmp r3, #35 ; 0x23 + 800ed52: d806 bhi.n 800ed62 + 800ed54: 4b46 ldr r3, [pc, #280] ; (800ee70 ) + 800ed56: f44f 72b4 mov.w r2, #360 ; 0x168 + 800ed5a: 4946 ldr r1, [pc, #280] ; (800ee74 ) + 800ed5c: 4846 ldr r0, [pc, #280] ; (800ee78 ) + 800ed5e: f001 ff33 bl 8010bc8 + (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE))); + + iphdr = (struct ip_hdr *)p->payload; + 800ed62: 687b ldr r3, [r7, #4] + 800ed64: 685b ldr r3, [r3, #4] + 800ed66: 61bb str r3, [r7, #24] + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); + 800ed68: 4844 ldr r0, [pc, #272] ; (800ee7c ) + 800ed6a: f001 ff2d bl 8010bc8 + ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src); + 800ed6e: 69bb ldr r3, [r7, #24] + 800ed70: 68db ldr r3, [r3, #12] + 800ed72: b2db uxtb r3, r3 + 800ed74: 4619 mov r1, r3 + 800ed76: 69bb ldr r3, [r7, #24] + 800ed78: 68db ldr r3, [r3, #12] + 800ed7a: 0a1b lsrs r3, r3, #8 + 800ed7c: b2db uxtb r3, r3 + 800ed7e: 461a mov r2, r3 + 800ed80: 69bb ldr r3, [r7, #24] + 800ed82: 68db ldr r3, [r3, #12] + 800ed84: 0c1b lsrs r3, r3, #16 + 800ed86: b2db uxtb r3, r3 + 800ed88: 4618 mov r0, r3 + 800ed8a: 69bb ldr r3, [r7, #24] + 800ed8c: 68db ldr r3, [r3, #12] + 800ed8e: 0e1b lsrs r3, r3, #24 + 800ed90: b2db uxtb r3, r3 + 800ed92: 9300 str r3, [sp, #0] + 800ed94: 4603 mov r3, r0 + 800ed96: 483a ldr r0, [pc, #232] ; (800ee80 ) + 800ed98: f001 ff16 bl 8010bc8 + LWIP_DEBUGF(ICMP_DEBUG, (" to ")); + 800ed9c: 4839 ldr r0, [pc, #228] ; (800ee84 ) + 800ed9e: f001 ff13 bl 8010bc8 + ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest); + 800eda2: 69bb ldr r3, [r7, #24] + 800eda4: 691b ldr r3, [r3, #16] + 800eda6: b2db uxtb r3, r3 + 800eda8: 4619 mov r1, r3 + 800edaa: 69bb ldr r3, [r7, #24] + 800edac: 691b ldr r3, [r3, #16] + 800edae: 0a1b lsrs r3, r3, #8 + 800edb0: b2db uxtb r3, r3 + 800edb2: 461a mov r2, r3 + 800edb4: 69bb ldr r3, [r7, #24] + 800edb6: 691b ldr r3, [r3, #16] + 800edb8: 0c1b lsrs r3, r3, #16 + 800edba: b2db uxtb r3, r3 + 800edbc: 4618 mov r0, r3 + 800edbe: 69bb ldr r3, [r7, #24] + 800edc0: 691b ldr r3, [r3, #16] + 800edc2: 0e1b lsrs r3, r3, #24 + 800edc4: b2db uxtb r3, r3 + 800edc6: 9300 str r3, [sp, #0] + 800edc8: 4603 mov r3, r0 + 800edca: 482d ldr r0, [pc, #180] ; (800ee80 ) + 800edcc: f001 fefc bl 8010bc8 + LWIP_DEBUGF(ICMP_DEBUG, ("\n")); + 800edd0: 200a movs r0, #10 + 800edd2: f001 ff0b bl 8010bec + + icmphdr = (struct icmp_echo_hdr *)q->payload; + 800edd6: 69fb ldr r3, [r7, #28] + 800edd8: 685b ldr r3, [r3, #4] + 800edda: 617b str r3, [r7, #20] + icmphdr->type = type; + 800eddc: 697b ldr r3, [r7, #20] + 800edde: 78fa ldrb r2, [r7, #3] + 800ede0: 701a strb r2, [r3, #0] + icmphdr->code = code; + 800ede2: 697b ldr r3, [r7, #20] + 800ede4: 78ba ldrb r2, [r7, #2] + 800ede6: 705a strb r2, [r3, #1] + icmphdr->id = 0; + 800ede8: 697b ldr r3, [r7, #20] + 800edea: 2200 movs r2, #0 + 800edec: 711a strb r2, [r3, #4] + 800edee: 2200 movs r2, #0 + 800edf0: 715a strb r2, [r3, #5] + icmphdr->seqno = 0; + 800edf2: 697b ldr r3, [r7, #20] + 800edf4: 2200 movs r2, #0 + 800edf6: 719a strb r2, [r3, #6] + 800edf8: 2200 movs r2, #0 + 800edfa: 71da strb r2, [r3, #7] + + /* copy fields from original packet */ + SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload, + 800edfc: 69fb ldr r3, [r7, #28] + 800edfe: 685b ldr r3, [r3, #4] + 800ee00: f103 0008 add.w r0, r3, #8 + 800ee04: 687b ldr r3, [r7, #4] + 800ee06: 685b ldr r3, [r3, #4] + 800ee08: 221c movs r2, #28 + 800ee0a: 4619 mov r1, r3 + 800ee0c: f002 f8bd bl 8010f8a + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE); + + ip4_addr_copy(iphdr_src, iphdr->src); + 800ee10: 69bb ldr r3, [r7, #24] + 800ee12: 68db ldr r3, [r3, #12] + 800ee14: 60fb str r3, [r7, #12] + ip4_addr_t iphdr_dst; + ip4_addr_copy(iphdr_dst, iphdr->dest); + netif = ip4_route_src(&iphdr_dst, &iphdr_src); + } +#else + netif = ip4_route(&iphdr_src); + 800ee16: f107 030c add.w r3, r7, #12 + 800ee1a: 4618 mov r0, r3 + 800ee1c: f000 f834 bl 800ee88 + 800ee20: 6138 str r0, [r7, #16] +#endif + if (netif != NULL) { + 800ee22: 693b ldr r3, [r7, #16] + 800ee24: 2b00 cmp r3, #0 + 800ee26: d01b beq.n 800ee60 + /* calculate checksum */ + icmphdr->chksum = 0; + 800ee28: 697b ldr r3, [r7, #20] + 800ee2a: 2200 movs r2, #0 + 800ee2c: 709a strb r2, [r3, #2] + 800ee2e: 2200 movs r2, #0 + 800ee30: 70da strb r2, [r3, #3] +#if CHECKSUM_GEN_ICMP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) { + icmphdr->chksum = inet_chksum(icmphdr, q->len); + 800ee32: 69fb ldr r3, [r7, #28] + 800ee34: 895b ldrh r3, [r3, #10] + 800ee36: 4619 mov r1, r3 + 800ee38: 6978 ldr r0, [r7, #20] + 800ee3a: f7f6 fc12 bl 8005662 + 800ee3e: 4603 mov r3, r0 + 800ee40: 461a mov r2, r3 + 800ee42: 697b ldr r3, [r7, #20] + 800ee44: 805a strh r2, [r3, #2] + } +#endif + ICMP_STATS_INC(icmp.xmit); + ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif); + 800ee46: f107 020c add.w r2, r7, #12 + 800ee4a: 693b ldr r3, [r7, #16] + 800ee4c: 9302 str r3, [sp, #8] + 800ee4e: 2301 movs r3, #1 + 800ee50: 9301 str r3, [sp, #4] + 800ee52: 2300 movs r3, #0 + 800ee54: 9300 str r3, [sp, #0] + 800ee56: 23ff movs r3, #255 ; 0xff + 800ee58: 2100 movs r1, #0 + 800ee5a: 69f8 ldr r0, [r7, #28] + 800ee5c: f000 f9d2 bl 800f204 + } + pbuf_free(q); + 800ee60: 69f8 ldr r0, [r7, #28] + 800ee62: f7f8 f8b7 bl 8006fd4 +} + 800ee66: 3720 adds r7, #32 + 800ee68: 46bd mov sp, r7 + 800ee6a: bd80 pop {r7, pc} + 800ee6c: 08014884 .word 0x08014884 + 800ee70: 08014708 .word 0x08014708 + 800ee74: 080148c4 .word 0x080148c4 + 800ee78: 08014778 .word 0x08014778 + 800ee7c: 080148f0 .word 0x080148f0 + 800ee80: 0801490c .word 0x0801490c + 800ee84: 0801491c .word 0x0801491c + +0800ee88 : + * @param dest the destination IP address for which to find the route + * @return the netif on which to send to reach dest + */ +struct netif * +ip4_route(const ip4_addr_t *dest) +{ + 800ee88: b480 push {r7} + 800ee8a: b085 sub sp, #20 + 800ee8c: af00 add r7, sp, #0 + 800ee8e: 6078 str r0, [r7, #4] + + /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */ + LWIP_UNUSED_ARG(dest); + + /* iterate through netifs */ + NETIF_FOREACH(netif) { + 800ee90: 4b33 ldr r3, [pc, #204] ; (800ef60 ) + 800ee92: 681b ldr r3, [r3, #0] + 800ee94: 60fb str r3, [r7, #12] + 800ee96: e036 b.n 800ef06 + /* is the netif up, does it have a link and a valid address? */ + if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) { + 800ee98: 68fb ldr r3, [r7, #12] + 800ee9a: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800ee9e: f003 0301 and.w r3, r3, #1 + 800eea2: b2db uxtb r3, r3 + 800eea4: 2b00 cmp r3, #0 + 800eea6: d02b beq.n 800ef00 + 800eea8: 68fb ldr r3, [r7, #12] + 800eeaa: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800eeae: 089b lsrs r3, r3, #2 + 800eeb0: f003 0301 and.w r3, r3, #1 + 800eeb4: b2db uxtb r3, r3 + 800eeb6: 2b00 cmp r3, #0 + 800eeb8: d022 beq.n 800ef00 + 800eeba: 68fb ldr r3, [r7, #12] + 800eebc: 3304 adds r3, #4 + 800eebe: 681b ldr r3, [r3, #0] + 800eec0: 2b00 cmp r3, #0 + 800eec2: d01d beq.n 800ef00 + /* network mask matches? */ + if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) { + 800eec4: 687b ldr r3, [r7, #4] + 800eec6: 681a ldr r2, [r3, #0] + 800eec8: 68fb ldr r3, [r7, #12] + 800eeca: 3304 adds r3, #4 + 800eecc: 681b ldr r3, [r3, #0] + 800eece: 405a eors r2, r3 + 800eed0: 68fb ldr r3, [r7, #12] + 800eed2: 3308 adds r3, #8 + 800eed4: 681b ldr r3, [r3, #0] + 800eed6: 4013 ands r3, r2 + 800eed8: 2b00 cmp r3, #0 + 800eeda: d101 bne.n 800eee0 + /* return netif on which to forward IP packet */ + return netif; + 800eedc: 68fb ldr r3, [r7, #12] + 800eede: e038 b.n 800ef52 + } + /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */ + if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) { + 800eee0: 68fb ldr r3, [r7, #12] + 800eee2: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800eee6: f003 0302 and.w r3, r3, #2 + 800eeea: 2b00 cmp r3, #0 + 800eeec: d108 bne.n 800ef00 + 800eeee: 687b ldr r3, [r7, #4] + 800eef0: 681a ldr r2, [r3, #0] + 800eef2: 68fb ldr r3, [r7, #12] + 800eef4: 330c adds r3, #12 + 800eef6: 681b ldr r3, [r3, #0] + 800eef8: 429a cmp r2, r3 + 800eefa: d101 bne.n 800ef00 + /* return netif on which to forward IP packet */ + return netif; + 800eefc: 68fb ldr r3, [r7, #12] + 800eefe: e028 b.n 800ef52 + NETIF_FOREACH(netif) { + 800ef00: 68fb ldr r3, [r7, #12] + 800ef02: 681b ldr r3, [r3, #0] + 800ef04: 60fb str r3, [r7, #12] + 800ef06: 68fb ldr r3, [r7, #12] + 800ef08: 2b00 cmp r3, #0 + 800ef0a: d1c5 bne.n 800ee98 + return netif; + } +#endif +#endif /* !LWIP_SINGLE_NETIF */ + + if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || + 800ef0c: 4b15 ldr r3, [pc, #84] ; (800ef64 ) + 800ef0e: 681b ldr r3, [r3, #0] + 800ef10: 2b00 cmp r3, #0 + 800ef12: d01a beq.n 800ef4a + 800ef14: 4b13 ldr r3, [pc, #76] ; (800ef64 ) + 800ef16: 681b ldr r3, [r3, #0] + 800ef18: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800ef1c: f003 0301 and.w r3, r3, #1 + 800ef20: 2b00 cmp r3, #0 + 800ef22: d012 beq.n 800ef4a + 800ef24: 4b0f ldr r3, [pc, #60] ; (800ef64 ) + 800ef26: 681b ldr r3, [r3, #0] + 800ef28: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800ef2c: f003 0304 and.w r3, r3, #4 + 800ef30: 2b00 cmp r3, #0 + 800ef32: d00a beq.n 800ef4a + ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) { + 800ef34: 4b0b ldr r3, [pc, #44] ; (800ef64 ) + 800ef36: 681b ldr r3, [r3, #0] + 800ef38: 3304 adds r3, #4 + 800ef3a: 681b ldr r3, [r3, #0] + if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || + 800ef3c: 2b00 cmp r3, #0 + 800ef3e: d004 beq.n 800ef4a + ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) { + 800ef40: 687b ldr r3, [r7, #4] + 800ef42: 681b ldr r3, [r3, #0] + 800ef44: b2db uxtb r3, r3 + 800ef46: 2b7f cmp r3, #127 ; 0x7f + 800ef48: d101 bne.n 800ef4e + If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + MIB2_STATS_INC(mib2.ipoutnoroutes); + return NULL; + 800ef4a: 2300 movs r3, #0 + 800ef4c: e001 b.n 800ef52 + } + + return netif_default; + 800ef4e: 4b05 ldr r3, [pc, #20] ; (800ef64 ) + 800ef50: 681b ldr r3, [r3, #0] +} + 800ef52: 4618 mov r0, r3 + 800ef54: 3714 adds r7, #20 + 800ef56: 46bd mov sp, r7 + 800ef58: f85d 7b04 ldr.w r7, [sp], #4 + 800ef5c: 4770 bx lr + 800ef5e: bf00 nop + 800ef60: 24007b60 .word 0x24007b60 + 800ef64: 24007b64 .word 0x24007b64 + +0800ef68 : +#endif /* IP_FORWARD */ + +/** Return true if the current input packet should be accepted on this netif */ +static int +ip4_input_accept(struct netif *netif) +{ + 800ef68: b580 push {r7, lr} + 800ef6a: b082 sub sp, #8 + 800ef6c: af00 add r7, sp, #0 + 800ef6e: 6078 str r0, [r7, #4] + ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)), + ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)), + ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif)))); + + /* interface is up and configured? */ + if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) { + 800ef70: 687b ldr r3, [r7, #4] + 800ef72: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800ef76: f003 0301 and.w r3, r3, #1 + 800ef7a: b2db uxtb r3, r3 + 800ef7c: 2b00 cmp r3, #0 + 800ef7e: d016 beq.n 800efae + 800ef80: 687b ldr r3, [r7, #4] + 800ef82: 3304 adds r3, #4 + 800ef84: 681b ldr r3, [r3, #0] + 800ef86: 2b00 cmp r3, #0 + 800ef88: d011 beq.n 800efae + /* unicast to this interface address? */ + if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || + 800ef8a: 4b0b ldr r3, [pc, #44] ; (800efb8 ) + 800ef8c: 695a ldr r2, [r3, #20] + 800ef8e: 687b ldr r3, [r7, #4] + 800ef90: 3304 adds r3, #4 + 800ef92: 681b ldr r3, [r3, #0] + 800ef94: 429a cmp r2, r3 + 800ef96: d008 beq.n 800efaa + /* or broadcast on this interface network address? */ + ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) + 800ef98: 4b07 ldr r3, [pc, #28] ; (800efb8 ) + 800ef9a: 695b ldr r3, [r3, #20] + 800ef9c: 6879 ldr r1, [r7, #4] + 800ef9e: 4618 mov r0, r3 + 800efa0: f000 fa08 bl 800f3b4 + 800efa4: 4603 mov r3, r0 + if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || + 800efa6: 2b00 cmp r3, #0 + 800efa8: d001 beq.n 800efae +#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ + ) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* accept on this netif */ + return 1; + 800efaa: 2301 movs r3, #1 + 800efac: e000 b.n 800efb0 + /* accept on this netif */ + return 1; + } +#endif /* LWIP_AUTOIP */ + } + return 0; + 800efae: 2300 movs r3, #0 +} + 800efb0: 4618 mov r0, r3 + 800efb2: 3708 adds r7, #8 + 800efb4: 46bd mov sp, r7 + 800efb6: bd80 pop {r7, pc} + 800efb8: 24004c10 .word 0x24004c10 + +0800efbc : + * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't + * processed, but currently always returns ERR_OK) + */ +err_t +ip4_input(struct pbuf *p, struct netif *inp) +{ + 800efbc: b580 push {r7, lr} + 800efbe: b086 sub sp, #24 + 800efc0: af00 add r7, sp, #0 + 800efc2: 6078 str r0, [r7, #4] + 800efc4: 6039 str r1, [r7, #0] + + IP_STATS_INC(ip.recv); + MIB2_STATS_INC(mib2.ipinreceives); + + /* identify the IP header */ + iphdr = (struct ip_hdr *)p->payload; + 800efc6: 687b ldr r3, [r7, #4] + 800efc8: 685b ldr r3, [r3, #4] + 800efca: 613b str r3, [r7, #16] + if (IPH_V(iphdr) != 4) { + 800efcc: 693b ldr r3, [r7, #16] + 800efce: 781b ldrb r3, [r3, #0] + 800efd0: 091b lsrs r3, r3, #4 + 800efd2: b2db uxtb r3, r3 + 800efd4: 2b04 cmp r3, #4 + 800efd6: d004 beq.n 800efe2 + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr))); + ip4_debug_print(p); + pbuf_free(p); + 800efd8: 6878 ldr r0, [r7, #4] + 800efda: f7f7 fffb bl 8006fd4 + IP_STATS_INC(ip.err); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinhdrerrors); + return ERR_OK; + 800efde: 2300 movs r3, #0 + 800efe0: e107 b.n 800f1f2 + return ERR_OK; + } +#endif + + /* obtain IP header length in bytes */ + iphdr_hlen = IPH_HL_BYTES(iphdr); + 800efe2: 693b ldr r3, [r7, #16] + 800efe4: 781b ldrb r3, [r3, #0] + 800efe6: f003 030f and.w r3, r3, #15 + 800efea: b2db uxtb r3, r3 + 800efec: 009b lsls r3, r3, #2 + 800efee: b2db uxtb r3, r3 + 800eff0: 81fb strh r3, [r7, #14] + /* obtain ip length in bytes */ + iphdr_len = lwip_ntohs(IPH_LEN(iphdr)); + 800eff2: 693b ldr r3, [r7, #16] + 800eff4: 885b ldrh r3, [r3, #2] + 800eff6: b29b uxth r3, r3 + 800eff8: 4618 mov r0, r3 + 800effa: f7f6 faa7 bl 800554c + 800effe: 4603 mov r3, r0 + 800f000: 81bb strh r3, [r7, #12] + + /* Trim pbuf. This is especially required for packets < 60 bytes. */ + if (iphdr_len < p->tot_len) { + 800f002: 687b ldr r3, [r7, #4] + 800f004: 891b ldrh r3, [r3, #8] + 800f006: 89ba ldrh r2, [r7, #12] + 800f008: 429a cmp r2, r3 + 800f00a: d204 bcs.n 800f016 + pbuf_realloc(p, iphdr_len); + 800f00c: 89bb ldrh r3, [r7, #12] + 800f00e: 4619 mov r1, r3 + 800f010: 6878 ldr r0, [r7, #4] + 800f012: f7f7 fe59 bl 8006cc8 + } + + /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ + if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) { + 800f016: 687b ldr r3, [r7, #4] + 800f018: 895b ldrh r3, [r3, #10] + 800f01a: 89fa ldrh r2, [r7, #14] + 800f01c: 429a cmp r2, r3 + 800f01e: d807 bhi.n 800f030 + 800f020: 687b ldr r3, [r7, #4] + 800f022: 891b ldrh r3, [r3, #8] + 800f024: 89ba ldrh r2, [r7, #12] + 800f026: 429a cmp r2, r3 + 800f028: d802 bhi.n 800f030 + 800f02a: 89fb ldrh r3, [r7, #14] + 800f02c: 2b13 cmp r3, #19 + 800f02e: d804 bhi.n 800f03a + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", + iphdr_len, p->tot_len)); + } + /* free (drop) packet pbufs */ + pbuf_free(p); + 800f030: 6878 ldr r0, [r7, #4] + 800f032: f7f7 ffcf bl 8006fd4 + IP_STATS_INC(ip.lenerr); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipindiscards); + return ERR_OK; + 800f036: 2300 movs r3, #0 + 800f038: e0db b.n 800f1f2 + } + } +#endif + + /* copy IP addresses to aligned ip_addr_t */ + ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest); + 800f03a: 693b ldr r3, [r7, #16] + 800f03c: 691b ldr r3, [r3, #16] + 800f03e: 4a6f ldr r2, [pc, #444] ; (800f1fc ) + 800f040: 6153 str r3, [r2, #20] + ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src); + 800f042: 693b ldr r3, [r7, #16] + 800f044: 68db ldr r3, [r3, #12] + 800f046: 4a6d ldr r2, [pc, #436] ; (800f1fc ) + 800f048: 6113 str r3, [r2, #16] + + /* match packet against an interface, i.e. is this packet for us? */ + if (ip4_addr_ismulticast(ip4_current_dest_addr())) { + 800f04a: 4b6c ldr r3, [pc, #432] ; (800f1fc ) + 800f04c: 695b ldr r3, [r3, #20] + 800f04e: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800f052: 2be0 cmp r3, #224 ; 0xe0 + 800f054: d112 bne.n 800f07c + netif = inp; + } else { + netif = NULL; + } +#else /* LWIP_IGMP */ + if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) { + 800f056: 683b ldr r3, [r7, #0] + 800f058: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800f05c: f003 0301 and.w r3, r3, #1 + 800f060: b2db uxtb r3, r3 + 800f062: 2b00 cmp r3, #0 + 800f064: d007 beq.n 800f076 + 800f066: 683b ldr r3, [r7, #0] + 800f068: 3304 adds r3, #4 + 800f06a: 681b ldr r3, [r3, #0] + 800f06c: 2b00 cmp r3, #0 + 800f06e: d002 beq.n 800f076 + netif = inp; + 800f070: 683b ldr r3, [r7, #0] + 800f072: 617b str r3, [r7, #20] + 800f074: e02a b.n 800f0cc + } else { + netif = NULL; + 800f076: 2300 movs r3, #0 + 800f078: 617b str r3, [r7, #20] + 800f07a: e027 b.n 800f0cc + } +#endif /* LWIP_IGMP */ + } else { + /* start trying with inp. if that's not acceptable, start walking the + list of configured netifs. */ + if (ip4_input_accept(inp)) { + 800f07c: 6838 ldr r0, [r7, #0] + 800f07e: f7ff ff73 bl 800ef68 + 800f082: 4603 mov r3, r0 + 800f084: 2b00 cmp r3, #0 + 800f086: d002 beq.n 800f08e + netif = inp; + 800f088: 683b ldr r3, [r7, #0] + 800f08a: 617b str r3, [r7, #20] + 800f08c: e01e b.n 800f0cc + } else { + netif = NULL; + 800f08e: 2300 movs r3, #0 + 800f090: 617b str r3, [r7, #20] +#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF + /* Packets sent to the loopback address must not be accepted on an + * interface that does not have the loopback address assigned to it, + * unless a non-loopback interface is used for loopback traffic. */ + if (!ip4_addr_isloopback(ip4_current_dest_addr())) + 800f092: 4b5a ldr r3, [pc, #360] ; (800f1fc ) + 800f094: 695b ldr r3, [r3, #20] + 800f096: b2db uxtb r3, r3 + 800f098: 2b7f cmp r3, #127 ; 0x7f + 800f09a: d017 beq.n 800f0cc +#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */ + { +#if !LWIP_SINGLE_NETIF + NETIF_FOREACH(netif) { + 800f09c: 4b58 ldr r3, [pc, #352] ; (800f200 ) + 800f09e: 681b ldr r3, [r3, #0] + 800f0a0: 617b str r3, [r7, #20] + 800f0a2: e00e b.n 800f0c2 + if (netif == inp) { + 800f0a4: 697a ldr r2, [r7, #20] + 800f0a6: 683b ldr r3, [r7, #0] + 800f0a8: 429a cmp r2, r3 + 800f0aa: d006 beq.n 800f0ba + /* we checked that before already */ + continue; + } + if (ip4_input_accept(netif)) { + 800f0ac: 6978 ldr r0, [r7, #20] + 800f0ae: f7ff ff5b bl 800ef68 + 800f0b2: 4603 mov r3, r0 + 800f0b4: 2b00 cmp r3, #0 + 800f0b6: d108 bne.n 800f0ca + 800f0b8: e000 b.n 800f0bc + continue; + 800f0ba: bf00 nop + NETIF_FOREACH(netif) { + 800f0bc: 697b ldr r3, [r7, #20] + 800f0be: 681b ldr r3, [r3, #0] + 800f0c0: 617b str r3, [r7, #20] + 800f0c2: 697b ldr r3, [r7, #20] + 800f0c4: 2b00 cmp r3, #0 + 800f0c6: d1ed bne.n 800f0a4 + 800f0c8: e000 b.n 800f0cc + break; + 800f0ca: bf00 nop + && !ip4_addr_isany_val(*ip4_current_src_addr()) +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + ) +#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */ + { + if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || + 800f0cc: 4b4b ldr r3, [pc, #300] ; (800f1fc ) + 800f0ce: 691b ldr r3, [r3, #16] + 800f0d0: 6839 ldr r1, [r7, #0] + 800f0d2: 4618 mov r0, r3 + 800f0d4: f000 f96e bl 800f3b4 + 800f0d8: 4603 mov r3, r0 + 800f0da: 2b00 cmp r3, #0 + 800f0dc: d105 bne.n 800f0ea + (ip4_addr_ismulticast(ip4_current_src_addr()))) { + 800f0de: 4b47 ldr r3, [pc, #284] ; (800f1fc ) + 800f0e0: 691b ldr r3, [r3, #16] + 800f0e2: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || + 800f0e6: 2be0 cmp r3, #224 ; 0xe0 + 800f0e8: d104 bne.n 800f0f4 + /* packet source is not valid */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n")); + /* free (drop) packet pbufs */ + pbuf_free(p); + 800f0ea: 6878 ldr r0, [r7, #4] + 800f0ec: f7f7 ff72 bl 8006fd4 + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinaddrerrors); + MIB2_STATS_INC(mib2.ipindiscards); + return ERR_OK; + 800f0f0: 2300 movs r3, #0 + 800f0f2: e07e b.n 800f1f2 + } + } + + /* packet not for us? */ + if (netif == NULL) { + 800f0f4: 697b ldr r3, [r7, #20] + 800f0f6: 2b00 cmp r3, #0 + 800f0f8: d104 bne.n 800f104 + { + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinaddrerrors); + MIB2_STATS_INC(mib2.ipindiscards); + } + pbuf_free(p); + 800f0fa: 6878 ldr r0, [r7, #4] + 800f0fc: f7f7 ff6a bl 8006fd4 + return ERR_OK; + 800f100: 2300 movs r3, #0 + 800f102: e076 b.n 800f1f2 + } + /* packet consists of multiple fragments? */ + if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) { + 800f104: 693b ldr r3, [r7, #16] + 800f106: 88db ldrh r3, [r3, #6] + 800f108: b29b uxth r3, r3 + 800f10a: 461a mov r2, r3 + 800f10c: f64f 733f movw r3, #65343 ; 0xff3f + 800f110: 4013 ands r3, r2 + 800f112: 2b00 cmp r3, #0 + 800f114: d00b beq.n 800f12e +#if IP_REASSEMBLY /* packet fragment reassembly code present? */ + LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n", + lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8))); + /* reassemble the packet*/ + p = ip4_reass(p); + 800f116: 6878 ldr r0, [r7, #4] + 800f118: f000 fc92 bl 800fa40 + 800f11c: 6078 str r0, [r7, #4] + /* packet not fully reassembled yet? */ + if (p == NULL) { + 800f11e: 687b ldr r3, [r7, #4] + 800f120: 2b00 cmp r3, #0 + 800f122: d101 bne.n 800f128 + return ERR_OK; + 800f124: 2300 movs r3, #0 + 800f126: e064 b.n 800f1f2 + } + iphdr = (const struct ip_hdr *)p->payload; + 800f128: 687b ldr r3, [r7, #4] + 800f12a: 685b ldr r3, [r3, #4] + 800f12c: 613b str r3, [r7, #16] + /* send to upper layers */ + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n")); + ip4_debug_print(p); + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); + + ip_data.current_netif = netif; + 800f12e: 4a33 ldr r2, [pc, #204] ; (800f1fc ) + 800f130: 697b ldr r3, [r7, #20] + 800f132: 6013 str r3, [r2, #0] + ip_data.current_input_netif = inp; + 800f134: 4a31 ldr r2, [pc, #196] ; (800f1fc ) + 800f136: 683b ldr r3, [r7, #0] + 800f138: 6053 str r3, [r2, #4] + ip_data.current_ip4_header = iphdr; + 800f13a: 4a30 ldr r2, [pc, #192] ; (800f1fc ) + 800f13c: 693b ldr r3, [r7, #16] + 800f13e: 6093 str r3, [r2, #8] + ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr); + 800f140: 693b ldr r3, [r7, #16] + 800f142: 781b ldrb r3, [r3, #0] + 800f144: f003 030f and.w r3, r3, #15 + 800f148: b2db uxtb r3, r3 + 800f14a: 009b lsls r3, r3, #2 + 800f14c: b2db uxtb r3, r3 + 800f14e: b29a uxth r2, r3 + 800f150: 4b2a ldr r3, [pc, #168] ; (800f1fc ) + 800f152: 819a strh r2, [r3, #12] + /* raw input did not eat the packet? */ + raw_status = raw_input(p, inp); + if (raw_status != RAW_INPUT_EATEN) +#endif /* LWIP_RAW */ + { + pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */ + 800f154: 89fb ldrh r3, [r7, #14] + 800f156: 4619 mov r1, r3 + 800f158: 6878 ldr r0, [r7, #4] + 800f15a: f7f7 feb5 bl 8006ec8 + + switch (IPH_PROTO(iphdr)) { + 800f15e: 693b ldr r3, [r7, #16] + 800f160: 7a5b ldrb r3, [r3, #9] + 800f162: 2b11 cmp r3, #17 + 800f164: d006 beq.n 800f174 + 800f166: 2b11 cmp r3, #17 + 800f168: dc13 bgt.n 800f192 + 800f16a: 2b01 cmp r3, #1 + 800f16c: d00c beq.n 800f188 + 800f16e: 2b06 cmp r3, #6 + 800f170: d005 beq.n 800f17e + 800f172: e00e b.n 800f192 + case IP_PROTO_UDP: +#if LWIP_UDPLITE + case IP_PROTO_UDPLITE: +#endif /* LWIP_UDPLITE */ + MIB2_STATS_INC(mib2.ipindelivers); + udp_input(p, inp); + 800f174: 6839 ldr r1, [r7, #0] + 800f176: 6878 ldr r0, [r7, #4] + 800f178: f7fe fb7e bl 800d878 + break; + 800f17c: e026 b.n 800f1cc +#endif /* LWIP_UDP */ +#if LWIP_TCP + case IP_PROTO_TCP: + MIB2_STATS_INC(mib2.ipindelivers); + tcp_input(p, inp); + 800f17e: 6839 ldr r1, [r7, #0] + 800f180: 6878 ldr r0, [r7, #4] + 800f182: f7f9 ff33 bl 8008fec + break; + 800f186: e021 b.n 800f1cc +#endif /* LWIP_TCP */ +#if LWIP_ICMP + case IP_PROTO_ICMP: + MIB2_STATS_INC(mib2.ipindelivers); + icmp_input(p, inp); + 800f188: 6839 ldr r1, [r7, #0] + 800f18a: 6878 ldr r0, [r7, #4] + 800f18c: f7ff fc32 bl 800e9f4 + break; + 800f190: e01c b.n 800f1cc + } else +#endif /* LWIP_RAW */ + { +#if LWIP_ICMP + /* send ICMP destination protocol unreachable unless is was a broadcast */ + if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && + 800f192: 4b1a ldr r3, [pc, #104] ; (800f1fc ) + 800f194: 695b ldr r3, [r3, #20] + 800f196: 6979 ldr r1, [r7, #20] + 800f198: 4618 mov r0, r3 + 800f19a: f000 f90b bl 800f3b4 + 800f19e: 4603 mov r3, r0 + 800f1a0: 2b00 cmp r3, #0 + 800f1a2: d10f bne.n 800f1c4 + !ip4_addr_ismulticast(ip4_current_dest_addr())) { + 800f1a4: 4b15 ldr r3, [pc, #84] ; (800f1fc ) + 800f1a6: 695b ldr r3, [r3, #20] + 800f1a8: f003 03f0 and.w r3, r3, #240 ; 0xf0 + if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && + 800f1ac: 2be0 cmp r3, #224 ; 0xe0 + 800f1ae: d009 beq.n 800f1c4 + pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */ + 800f1b0: f9b7 300e ldrsh.w r3, [r7, #14] + 800f1b4: 4619 mov r1, r3 + 800f1b6: 6878 ldr r0, [r7, #4] + 800f1b8: f7f7 fef9 bl 8006fae + icmp_dest_unreach(p, ICMP_DUR_PROTO); + 800f1bc: 2102 movs r1, #2 + 800f1be: 6878 ldr r0, [r7, #4] + 800f1c0: f7ff fd8e bl 800ece0 + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinunknownprotos); + } + pbuf_free(p); + 800f1c4: 6878 ldr r0, [r7, #4] + 800f1c6: f7f7 ff05 bl 8006fd4 + break; + 800f1ca: bf00 nop + } + } + + /* @todo: this is not really necessary... */ + ip_data.current_netif = NULL; + 800f1cc: 4b0b ldr r3, [pc, #44] ; (800f1fc ) + 800f1ce: 2200 movs r2, #0 + 800f1d0: 601a str r2, [r3, #0] + ip_data.current_input_netif = NULL; + 800f1d2: 4b0a ldr r3, [pc, #40] ; (800f1fc ) + 800f1d4: 2200 movs r2, #0 + 800f1d6: 605a str r2, [r3, #4] + ip_data.current_ip4_header = NULL; + 800f1d8: 4b08 ldr r3, [pc, #32] ; (800f1fc ) + 800f1da: 2200 movs r2, #0 + 800f1dc: 609a str r2, [r3, #8] + ip_data.current_ip_header_tot_len = 0; + 800f1de: 4b07 ldr r3, [pc, #28] ; (800f1fc ) + 800f1e0: 2200 movs r2, #0 + 800f1e2: 819a strh r2, [r3, #12] + ip4_addr_set_any(ip4_current_src_addr()); + 800f1e4: 4b05 ldr r3, [pc, #20] ; (800f1fc ) + 800f1e6: 2200 movs r2, #0 + 800f1e8: 611a str r2, [r3, #16] + ip4_addr_set_any(ip4_current_dest_addr()); + 800f1ea: 4b04 ldr r3, [pc, #16] ; (800f1fc ) + 800f1ec: 2200 movs r2, #0 + 800f1ee: 615a str r2, [r3, #20] + + return ERR_OK; + 800f1f0: 2300 movs r3, #0 +} + 800f1f2: 4618 mov r0, r3 + 800f1f4: 3718 adds r7, #24 + 800f1f6: 46bd mov sp, r7 + 800f1f8: bd80 pop {r7, pc} + 800f1fa: bf00 nop + 800f1fc: 24004c10 .word 0x24004c10 + 800f200: 24007b60 .word 0x24007b60 + +0800f204 : + */ +err_t +ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ + 800f204: b580 push {r7, lr} + 800f206: b08a sub sp, #40 ; 0x28 + 800f208: af04 add r7, sp, #16 + 800f20a: 60f8 str r0, [r7, #12] + 800f20c: 60b9 str r1, [r7, #8] + 800f20e: 607a str r2, [r7, #4] + 800f210: 70fb strb r3, [r7, #3] +ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen) +{ +#endif /* IP_OPTIONS_SEND */ + const ip4_addr_t *src_used = src; + 800f212: 68bb ldr r3, [r7, #8] + 800f214: 617b str r3, [r7, #20] + if (dest != LWIP_IP_HDRINCL) { + 800f216: 687b ldr r3, [r7, #4] + 800f218: 2b00 cmp r3, #0 + 800f21a: d009 beq.n 800f230 + if (ip4_addr_isany(src)) { + 800f21c: 68bb ldr r3, [r7, #8] + 800f21e: 2b00 cmp r3, #0 + 800f220: d003 beq.n 800f22a + 800f222: 68bb ldr r3, [r7, #8] + 800f224: 681b ldr r3, [r3, #0] + 800f226: 2b00 cmp r3, #0 + 800f228: d102 bne.n 800f230 + src_used = netif_ip4_addr(netif); + 800f22a: 6abb ldr r3, [r7, #40] ; 0x28 + 800f22c: 3304 adds r3, #4 + 800f22e: 617b str r3, [r7, #20] + +#if IP_OPTIONS_SEND + return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif, + ip_options, optlen); +#else /* IP_OPTIONS_SEND */ + return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif); + 800f230: 78fa ldrb r2, [r7, #3] + 800f232: 6abb ldr r3, [r7, #40] ; 0x28 + 800f234: 9302 str r3, [sp, #8] + 800f236: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 800f23a: 9301 str r3, [sp, #4] + 800f23c: f897 3020 ldrb.w r3, [r7, #32] + 800f240: 9300 str r3, [sp, #0] + 800f242: 4613 mov r3, r2 + 800f244: 687a ldr r2, [r7, #4] + 800f246: 6979 ldr r1, [r7, #20] + 800f248: 68f8 ldr r0, [r7, #12] + 800f24a: f000 f805 bl 800f258 + 800f24e: 4603 mov r3, r0 +#endif /* IP_OPTIONS_SEND */ +} + 800f250: 4618 mov r0, r3 + 800f252: 3718 adds r7, #24 + 800f254: 46bd mov sp, r7 + 800f256: bd80 pop {r7, pc} + +0800f258 : + */ +err_t +ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ + 800f258: b580 push {r7, lr} + 800f25a: b088 sub sp, #32 + 800f25c: af00 add r7, sp, #0 + 800f25e: 60f8 str r0, [r7, #12] + 800f260: 60b9 str r1, [r7, #8] + 800f262: 607a str r2, [r7, #4] + 800f264: 70fb strb r3, [r7, #3] +#if CHECKSUM_GEN_IP_INLINE + u32_t chk_sum = 0; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + 800f266: 68fb ldr r3, [r7, #12] + 800f268: 7b9b ldrb r3, [r3, #14] + 800f26a: 2b01 cmp r3, #1 + 800f26c: d006 beq.n 800f27c + 800f26e: 4b4b ldr r3, [pc, #300] ; (800f39c ) + 800f270: f44f 7255 mov.w r2, #852 ; 0x354 + 800f274: 494a ldr r1, [pc, #296] ; (800f3a0 ) + 800f276: 484b ldr r0, [pc, #300] ; (800f3a4 ) + 800f278: f001 fca6 bl 8010bc8 + + MIB2_STATS_INC(mib2.ipoutrequests); + + /* Should the IP header be generated or is it already included in p? */ + if (dest != LWIP_IP_HDRINCL) { + 800f27c: 687b ldr r3, [r7, #4] + 800f27e: 2b00 cmp r3, #0 + 800f280: d060 beq.n 800f344 + u16_t ip_hlen = IP_HLEN; + 800f282: 2314 movs r3, #20 + 800f284: 837b strh r3, [r7, #26] + } +#endif /* CHECKSUM_GEN_IP_INLINE */ + } +#endif /* IP_OPTIONS_SEND */ + /* generate IP header */ + if (pbuf_add_header(p, IP_HLEN)) { + 800f286: 2114 movs r1, #20 + 800f288: 68f8 ldr r0, [r7, #12] + 800f28a: f7f7 fe0d bl 8006ea8 + 800f28e: 4603 mov r3, r0 + 800f290: 2b00 cmp r3, #0 + 800f292: d002 beq.n 800f29a + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n")); + + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_BUF; + 800f294: f06f 0301 mvn.w r3, #1 + 800f298: e07c b.n 800f394 + } + + iphdr = (struct ip_hdr *)p->payload; + 800f29a: 68fb ldr r3, [r7, #12] + 800f29c: 685b ldr r3, [r3, #4] + 800f29e: 61fb str r3, [r7, #28] + LWIP_ASSERT("check that first pbuf can hold struct ip_hdr", + 800f2a0: 68fb ldr r3, [r7, #12] + 800f2a2: 895b ldrh r3, [r3, #10] + 800f2a4: 2b13 cmp r3, #19 + 800f2a6: d806 bhi.n 800f2b6 + 800f2a8: 4b3c ldr r3, [pc, #240] ; (800f39c ) + 800f2aa: f44f 7262 mov.w r2, #904 ; 0x388 + 800f2ae: 493e ldr r1, [pc, #248] ; (800f3a8 ) + 800f2b0: 483c ldr r0, [pc, #240] ; (800f3a4 ) + 800f2b2: f001 fc89 bl 8010bc8 + (p->len >= sizeof(struct ip_hdr))); + + IPH_TTL_SET(iphdr, ttl); + 800f2b6: 69fb ldr r3, [r7, #28] + 800f2b8: 78fa ldrb r2, [r7, #3] + 800f2ba: 721a strb r2, [r3, #8] + IPH_PROTO_SET(iphdr, proto); + 800f2bc: 69fb ldr r3, [r7, #28] + 800f2be: f897 202c ldrb.w r2, [r7, #44] ; 0x2c + 800f2c2: 725a strb r2, [r3, #9] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += PP_NTOHS(proto | (ttl << 8)); +#endif /* CHECKSUM_GEN_IP_INLINE */ + + /* dest cannot be NULL here */ + ip4_addr_copy(iphdr->dest, *dest); + 800f2c4: 687b ldr r3, [r7, #4] + 800f2c6: 681a ldr r2, [r3, #0] + 800f2c8: 69fb ldr r3, [r7, #28] + 800f2ca: 611a str r2, [r3, #16] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF; + chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + IPH_VHL_SET(iphdr, 4, ip_hlen / 4); + 800f2cc: 8b7b ldrh r3, [r7, #26] + 800f2ce: 089b lsrs r3, r3, #2 + 800f2d0: b29b uxth r3, r3 + 800f2d2: b2db uxtb r3, r3 + 800f2d4: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800f2d8: b2da uxtb r2, r3 + 800f2da: 69fb ldr r3, [r7, #28] + 800f2dc: 701a strb r2, [r3, #0] + IPH_TOS_SET(iphdr, tos); + 800f2de: 69fb ldr r3, [r7, #28] + 800f2e0: f897 2028 ldrb.w r2, [r7, #40] ; 0x28 + 800f2e4: 705a strb r2, [r3, #1] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8)); +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_LEN_SET(iphdr, lwip_htons(p->tot_len)); + 800f2e6: 68fb ldr r3, [r7, #12] + 800f2e8: 891b ldrh r3, [r3, #8] + 800f2ea: 4618 mov r0, r3 + 800f2ec: f7f6 f92e bl 800554c + 800f2f0: 4603 mov r3, r0 + 800f2f2: 461a mov r2, r3 + 800f2f4: 69fb ldr r3, [r7, #28] + 800f2f6: 805a strh r2, [r3, #2] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_len; +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_OFFSET_SET(iphdr, 0); + 800f2f8: 69fb ldr r3, [r7, #28] + 800f2fa: 2200 movs r2, #0 + 800f2fc: 719a strb r2, [r3, #6] + 800f2fe: 2200 movs r2, #0 + 800f300: 71da strb r2, [r3, #7] + IPH_ID_SET(iphdr, lwip_htons(ip_id)); + 800f302: 4b2a ldr r3, [pc, #168] ; (800f3ac ) + 800f304: 881b ldrh r3, [r3, #0] + 800f306: 4618 mov r0, r3 + 800f308: f7f6 f920 bl 800554c + 800f30c: 4603 mov r3, r0 + 800f30e: 461a mov r2, r3 + 800f310: 69fb ldr r3, [r7, #28] + 800f312: 809a strh r2, [r3, #4] +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_id; +#endif /* CHECKSUM_GEN_IP_INLINE */ + ++ip_id; + 800f314: 4b25 ldr r3, [pc, #148] ; (800f3ac ) + 800f316: 881b ldrh r3, [r3, #0] + 800f318: 3301 adds r3, #1 + 800f31a: b29a uxth r2, r3 + 800f31c: 4b23 ldr r3, [pc, #140] ; (800f3ac ) + 800f31e: 801a strh r2, [r3, #0] + + if (src == NULL) { + 800f320: 68bb ldr r3, [r7, #8] + 800f322: 2b00 cmp r3, #0 + 800f324: d104 bne.n 800f330 + ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4); + 800f326: 4b22 ldr r3, [pc, #136] ; (800f3b0 ) + 800f328: 681a ldr r2, [r3, #0] + 800f32a: 69fb ldr r3, [r7, #28] + 800f32c: 60da str r2, [r3, #12] + 800f32e: e003 b.n 800f338 + } else { + /* src cannot be NULL here */ + ip4_addr_copy(iphdr->src, *src); + 800f330: 68bb ldr r3, [r7, #8] + 800f332: 681a ldr r2, [r3, #0] + 800f334: 69fb ldr r3, [r7, #28] + 800f336: 60da str r2, [r3, #12] + else { + IPH_CHKSUM_SET(iphdr, 0); + } +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/ +#else /* CHECKSUM_GEN_IP_INLINE */ + IPH_CHKSUM_SET(iphdr, 0); + 800f338: 69fb ldr r3, [r7, #28] + 800f33a: 2200 movs r2, #0 + 800f33c: 729a strb r2, [r3, #10] + 800f33e: 2200 movs r2, #0 + 800f340: 72da strb r2, [r3, #11] + 800f342: e00f b.n 800f364 + } +#endif /* CHECKSUM_GEN_IP */ +#endif /* CHECKSUM_GEN_IP_INLINE */ + } else { + /* IP header already included in p */ + if (p->len < IP_HLEN) { + 800f344: 68fb ldr r3, [r7, #12] + 800f346: 895b ldrh r3, [r3, #10] + 800f348: 2b13 cmp r3, #19 + 800f34a: d802 bhi.n 800f352 + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n")); + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_BUF; + 800f34c: f06f 0301 mvn.w r3, #1 + 800f350: e020 b.n 800f394 + } + iphdr = (struct ip_hdr *)p->payload; + 800f352: 68fb ldr r3, [r7, #12] + 800f354: 685b ldr r3, [r3, #4] + 800f356: 61fb str r3, [r7, #28] + ip4_addr_copy(dest_addr, iphdr->dest); + 800f358: 69fb ldr r3, [r7, #28] + 800f35a: 691b ldr r3, [r3, #16] + 800f35c: 617b str r3, [r7, #20] + dest = &dest_addr; + 800f35e: f107 0314 add.w r3, r7, #20 + 800f362: 607b str r3, [r7, #4] + } +#endif /* LWIP_MULTICAST_TX_OPTIONS */ +#endif /* ENABLE_LOOPBACK */ +#if IP_FRAG + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif->mtu && (p->tot_len > netif->mtu)) { + 800f364: 6b3b ldr r3, [r7, #48] ; 0x30 + 800f366: 8c9b ldrh r3, [r3, #36] ; 0x24 + 800f368: 2b00 cmp r3, #0 + 800f36a: d00c beq.n 800f386 + 800f36c: 68fb ldr r3, [r7, #12] + 800f36e: 891a ldrh r2, [r3, #8] + 800f370: 6b3b ldr r3, [r7, #48] ; 0x30 + 800f372: 8c9b ldrh r3, [r3, #36] ; 0x24 + 800f374: 429a cmp r2, r3 + 800f376: d906 bls.n 800f386 + return ip4_frag(p, netif, dest); + 800f378: 687a ldr r2, [r7, #4] + 800f37a: 6b39 ldr r1, [r7, #48] ; 0x30 + 800f37c: 68f8 ldr r0, [r7, #12] + 800f37e: f000 fd53 bl 800fe28 + 800f382: 4603 mov r3, r0 + 800f384: e006 b.n 800f394 + } +#endif /* IP_FRAG */ + + LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n")); + return netif->output(netif, p, dest); + 800f386: 6b3b ldr r3, [r7, #48] ; 0x30 + 800f388: 695b ldr r3, [r3, #20] + 800f38a: 687a ldr r2, [r7, #4] + 800f38c: 68f9 ldr r1, [r7, #12] + 800f38e: 6b38 ldr r0, [r7, #48] ; 0x30 + 800f390: 4798 blx r3 + 800f392: 4603 mov r3, r0 +} + 800f394: 4618 mov r0, r3 + 800f396: 3720 adds r7, #32 + 800f398: 46bd mov sp, r7 + 800f39a: bd80 pop {r7, pc} + 800f39c: 08014924 .word 0x08014924 + 800f3a0: 08014958 .word 0x08014958 + 800f3a4: 08014964 .word 0x08014964 + 800f3a8: 0801498c .word 0x0801498c + 800f3ac: 24007cc2 .word 0x24007cc2 + 800f3b0: 08014d94 .word 0x08014d94 + +0800f3b4 : + * @param netif the network interface against which the address is checked + * @return returns non-zero if the address is a broadcast address + */ +u8_t +ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif) +{ + 800f3b4: b480 push {r7} + 800f3b6: b085 sub sp, #20 + 800f3b8: af00 add r7, sp, #0 + 800f3ba: 6078 str r0, [r7, #4] + 800f3bc: 6039 str r1, [r7, #0] + ip4_addr_t ipaddr; + ip4_addr_set_u32(&ipaddr, addr); + 800f3be: 687b ldr r3, [r7, #4] + 800f3c0: 60fb str r3, [r7, #12] + + /* all ones (broadcast) or all zeroes (old skool broadcast) */ + if ((~addr == IPADDR_ANY) || + 800f3c2: 687b ldr r3, [r7, #4] + 800f3c4: f1b3 3fff cmp.w r3, #4294967295 + 800f3c8: d002 beq.n 800f3d0 + 800f3ca: 687b ldr r3, [r7, #4] + 800f3cc: 2b00 cmp r3, #0 + 800f3ce: d101 bne.n 800f3d4 + (addr == IPADDR_ANY)) { + return 1; + 800f3d0: 2301 movs r3, #1 + 800f3d2: e02a b.n 800f42a + /* no broadcast support on this network interface? */ + } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) { + 800f3d4: 683b ldr r3, [r7, #0] + 800f3d6: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 800f3da: f003 0302 and.w r3, r3, #2 + 800f3de: 2b00 cmp r3, #0 + 800f3e0: d101 bne.n 800f3e6 + /* the given address cannot be a broadcast address + * nor can we check against any broadcast addresses */ + return 0; + 800f3e2: 2300 movs r3, #0 + 800f3e4: e021 b.n 800f42a + /* address matches network interface address exactly? => no broadcast */ + } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) { + 800f3e6: 683b ldr r3, [r7, #0] + 800f3e8: 3304 adds r3, #4 + 800f3ea: 681b ldr r3, [r3, #0] + 800f3ec: 687a ldr r2, [r7, #4] + 800f3ee: 429a cmp r2, r3 + 800f3f0: d101 bne.n 800f3f6 + return 0; + 800f3f2: 2300 movs r3, #0 + 800f3f4: e019 b.n 800f42a + /* on the same (sub) network... */ + } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) + 800f3f6: 68fa ldr r2, [r7, #12] + 800f3f8: 683b ldr r3, [r7, #0] + 800f3fa: 3304 adds r3, #4 + 800f3fc: 681b ldr r3, [r3, #0] + 800f3fe: 405a eors r2, r3 + 800f400: 683b ldr r3, [r7, #0] + 800f402: 3308 adds r3, #8 + 800f404: 681b ldr r3, [r3, #0] + 800f406: 4013 ands r3, r2 + 800f408: 2b00 cmp r3, #0 + 800f40a: d10d bne.n 800f428 + /* ...and host identifier bits are all ones? =>... */ + && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == + 800f40c: 683b ldr r3, [r7, #0] + 800f40e: 3308 adds r3, #8 + 800f410: 681b ldr r3, [r3, #0] + 800f412: 43da mvns r2, r3 + 800f414: 687b ldr r3, [r7, #4] + 800f416: 401a ands r2, r3 + (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) { + 800f418: 683b ldr r3, [r7, #0] + 800f41a: 3308 adds r3, #8 + 800f41c: 681b ldr r3, [r3, #0] + 800f41e: 43db mvns r3, r3 + && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == + 800f420: 429a cmp r2, r3 + 800f422: d101 bne.n 800f428 + /* => network broadcast address */ + return 1; + 800f424: 2301 movs r3, #1 + 800f426: e000 b.n 800f42a + } else { + return 0; + 800f428: 2300 movs r3, #0 + } +} + 800f42a: 4618 mov r0, r3 + 800f42c: 3714 adds r7, #20 + 800f42e: 46bd mov sp, r7 + 800f430: f85d 7b04 ldr.w r7, [sp], #4 + 800f434: 4770 bx lr + ... + +0800f438 : + * + * Should be called every 1000 msec (defined by IP_TMR_INTERVAL). + */ +void +ip_reass_tmr(void) +{ + 800f438: b580 push {r7, lr} + 800f43a: b084 sub sp, #16 + 800f43c: af00 add r7, sp, #0 + struct ip_reassdata *r, *prev = NULL; + 800f43e: 2300 movs r3, #0 + 800f440: 60bb str r3, [r7, #8] + + r = reassdatagrams; + 800f442: 4b12 ldr r3, [pc, #72] ; (800f48c ) + 800f444: 681b ldr r3, [r3, #0] + 800f446: 60fb str r3, [r7, #12] + while (r != NULL) { + 800f448: e018 b.n 800f47c + /* Decrement the timer. Once it reaches 0, + * clean up the incomplete fragment assembly */ + if (r->timer > 0) { + 800f44a: 68fb ldr r3, [r7, #12] + 800f44c: 7fdb ldrb r3, [r3, #31] + 800f44e: 2b00 cmp r3, #0 + 800f450: d00b beq.n 800f46a + r->timer--; + 800f452: 68fb ldr r3, [r7, #12] + 800f454: 7fdb ldrb r3, [r3, #31] + 800f456: 3b01 subs r3, #1 + 800f458: b2da uxtb r2, r3 + 800f45a: 68fb ldr r3, [r7, #12] + 800f45c: 77da strb r2, [r3, #31] + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer)); + prev = r; + 800f45e: 68fb ldr r3, [r7, #12] + 800f460: 60bb str r3, [r7, #8] + r = r->next; + 800f462: 68fb ldr r3, [r7, #12] + 800f464: 681b ldr r3, [r3, #0] + 800f466: 60fb str r3, [r7, #12] + 800f468: e008 b.n 800f47c + } else { + /* reassembly timed out */ + struct ip_reassdata *tmp; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n")); + tmp = r; + 800f46a: 68fb ldr r3, [r7, #12] + 800f46c: 607b str r3, [r7, #4] + /* get the next pointer before freeing */ + r = r->next; + 800f46e: 68fb ldr r3, [r7, #12] + 800f470: 681b ldr r3, [r3, #0] + 800f472: 60fb str r3, [r7, #12] + /* free the helper struct and all enqueued pbufs */ + ip_reass_free_complete_datagram(tmp, prev); + 800f474: 68b9 ldr r1, [r7, #8] + 800f476: 6878 ldr r0, [r7, #4] + 800f478: f000 f80a bl 800f490 + while (r != NULL) { + 800f47c: 68fb ldr r3, [r7, #12] + 800f47e: 2b00 cmp r3, #0 + 800f480: d1e3 bne.n 800f44a + } + } +} + 800f482: bf00 nop + 800f484: bf00 nop + 800f486: 3710 adds r7, #16 + 800f488: 46bd mov sp, r7 + 800f48a: bd80 pop {r7, pc} + 800f48c: 24007cc4 .word 0x24007cc4 + +0800f490 : + * @param prev the previous datagram in the linked list + * @return the number of pbufs freed + */ +static int +ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + 800f490: b580 push {r7, lr} + 800f492: b088 sub sp, #32 + 800f494: af00 add r7, sp, #0 + 800f496: 6078 str r0, [r7, #4] + 800f498: 6039 str r1, [r7, #0] + u16_t pbufs_freed = 0; + 800f49a: 2300 movs r3, #0 + 800f49c: 83fb strh r3, [r7, #30] + u16_t clen; + struct pbuf *p; + struct ip_reass_helper *iprh; + + LWIP_ASSERT("prev != ipr", prev != ipr); + 800f49e: 683a ldr r2, [r7, #0] + 800f4a0: 687b ldr r3, [r7, #4] + 800f4a2: 429a cmp r2, r3 + 800f4a4: d105 bne.n 800f4b2 + 800f4a6: 4b45 ldr r3, [pc, #276] ; (800f5bc ) + 800f4a8: 22ab movs r2, #171 ; 0xab + 800f4aa: 4945 ldr r1, [pc, #276] ; (800f5c0 ) + 800f4ac: 4845 ldr r0, [pc, #276] ; (800f5c4 ) + 800f4ae: f001 fb8b bl 8010bc8 + if (prev != NULL) { + 800f4b2: 683b ldr r3, [r7, #0] + 800f4b4: 2b00 cmp r3, #0 + 800f4b6: d00a beq.n 800f4ce + LWIP_ASSERT("prev->next == ipr", prev->next == ipr); + 800f4b8: 683b ldr r3, [r7, #0] + 800f4ba: 681b ldr r3, [r3, #0] + 800f4bc: 687a ldr r2, [r7, #4] + 800f4be: 429a cmp r2, r3 + 800f4c0: d005 beq.n 800f4ce + 800f4c2: 4b3e ldr r3, [pc, #248] ; (800f5bc ) + 800f4c4: 22ad movs r2, #173 ; 0xad + 800f4c6: 4940 ldr r1, [pc, #256] ; (800f5c8 ) + 800f4c8: 483e ldr r0, [pc, #248] ; (800f5c4 ) + 800f4ca: f001 fb7d bl 8010bc8 + } + + MIB2_STATS_INC(mib2.ipreasmfails); +#if LWIP_ICMP + iprh = (struct ip_reass_helper *)ipr->p->payload; + 800f4ce: 687b ldr r3, [r7, #4] + 800f4d0: 685b ldr r3, [r3, #4] + 800f4d2: 685b ldr r3, [r3, #4] + 800f4d4: 617b str r3, [r7, #20] + if (iprh->start == 0) { + 800f4d6: 697b ldr r3, [r7, #20] + 800f4d8: 889b ldrh r3, [r3, #4] + 800f4da: b29b uxth r3, r3 + 800f4dc: 2b00 cmp r3, #0 + 800f4de: d12a bne.n 800f536 + /* The first fragment was received, send ICMP time exceeded. */ + /* First, de-queue the first pbuf from r->p. */ + p = ipr->p; + 800f4e0: 687b ldr r3, [r7, #4] + 800f4e2: 685b ldr r3, [r3, #4] + 800f4e4: 61bb str r3, [r7, #24] + ipr->p = iprh->next_pbuf; + 800f4e6: 697b ldr r3, [r7, #20] + 800f4e8: 681a ldr r2, [r3, #0] + 800f4ea: 687b ldr r3, [r7, #4] + 800f4ec: 605a str r2, [r3, #4] + /* Then, copy the original header into it. */ + SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN); + 800f4ee: 69bb ldr r3, [r7, #24] + 800f4f0: 6858 ldr r0, [r3, #4] + 800f4f2: 687b ldr r3, [r7, #4] + 800f4f4: 3308 adds r3, #8 + 800f4f6: 2214 movs r2, #20 + 800f4f8: 4619 mov r1, r3 + 800f4fa: f001 fd46 bl 8010f8a + icmp_time_exceeded(p, ICMP_TE_FRAG); + 800f4fe: 2101 movs r1, #1 + 800f500: 69b8 ldr r0, [r7, #24] + 800f502: f7ff fbfd bl 800ed00 + clen = pbuf_clen(p); + 800f506: 69b8 ldr r0, [r7, #24] + 800f508: f7f7 fdec bl 80070e4 + 800f50c: 4603 mov r3, r0 + 800f50e: 827b strh r3, [r7, #18] + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + 800f510: 8bfa ldrh r2, [r7, #30] + 800f512: 8a7b ldrh r3, [r7, #18] + 800f514: 4413 add r3, r2 + 800f516: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800f51a: db05 blt.n 800f528 + 800f51c: 4b27 ldr r3, [pc, #156] ; (800f5bc ) + 800f51e: 22bc movs r2, #188 ; 0xbc + 800f520: 492a ldr r1, [pc, #168] ; (800f5cc ) + 800f522: 4828 ldr r0, [pc, #160] ; (800f5c4 ) + 800f524: f001 fb50 bl 8010bc8 + pbufs_freed = (u16_t)(pbufs_freed + clen); + 800f528: 8bfa ldrh r2, [r7, #30] + 800f52a: 8a7b ldrh r3, [r7, #18] + 800f52c: 4413 add r3, r2 + 800f52e: 83fb strh r3, [r7, #30] + pbuf_free(p); + 800f530: 69b8 ldr r0, [r7, #24] + 800f532: f7f7 fd4f bl 8006fd4 + } +#endif /* LWIP_ICMP */ + + /* First, free all received pbufs. The individual pbufs need to be released + separately as they have not yet been chained */ + p = ipr->p; + 800f536: 687b ldr r3, [r7, #4] + 800f538: 685b ldr r3, [r3, #4] + 800f53a: 61bb str r3, [r7, #24] + while (p != NULL) { + 800f53c: e01f b.n 800f57e + struct pbuf *pcur; + iprh = (struct ip_reass_helper *)p->payload; + 800f53e: 69bb ldr r3, [r7, #24] + 800f540: 685b ldr r3, [r3, #4] + 800f542: 617b str r3, [r7, #20] + pcur = p; + 800f544: 69bb ldr r3, [r7, #24] + 800f546: 60fb str r3, [r7, #12] + /* get the next pointer before freeing */ + p = iprh->next_pbuf; + 800f548: 697b ldr r3, [r7, #20] + 800f54a: 681b ldr r3, [r3, #0] + 800f54c: 61bb str r3, [r7, #24] + clen = pbuf_clen(pcur); + 800f54e: 68f8 ldr r0, [r7, #12] + 800f550: f7f7 fdc8 bl 80070e4 + 800f554: 4603 mov r3, r0 + 800f556: 827b strh r3, [r7, #18] + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + 800f558: 8bfa ldrh r2, [r7, #30] + 800f55a: 8a7b ldrh r3, [r7, #18] + 800f55c: 4413 add r3, r2 + 800f55e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800f562: db05 blt.n 800f570 + 800f564: 4b15 ldr r3, [pc, #84] ; (800f5bc ) + 800f566: 22cc movs r2, #204 ; 0xcc + 800f568: 4918 ldr r1, [pc, #96] ; (800f5cc ) + 800f56a: 4816 ldr r0, [pc, #88] ; (800f5c4 ) + 800f56c: f001 fb2c bl 8010bc8 + pbufs_freed = (u16_t)(pbufs_freed + clen); + 800f570: 8bfa ldrh r2, [r7, #30] + 800f572: 8a7b ldrh r3, [r7, #18] + 800f574: 4413 add r3, r2 + 800f576: 83fb strh r3, [r7, #30] + pbuf_free(pcur); + 800f578: 68f8 ldr r0, [r7, #12] + 800f57a: f7f7 fd2b bl 8006fd4 + while (p != NULL) { + 800f57e: 69bb ldr r3, [r7, #24] + 800f580: 2b00 cmp r3, #0 + 800f582: d1dc bne.n 800f53e + } + /* Then, unchain the struct ip_reassdata from the list and free it. */ + ip_reass_dequeue_datagram(ipr, prev); + 800f584: 6839 ldr r1, [r7, #0] + 800f586: 6878 ldr r0, [r7, #4] + 800f588: f000 f8c2 bl 800f710 + LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed); + 800f58c: 4b10 ldr r3, [pc, #64] ; (800f5d0 ) + 800f58e: 881b ldrh r3, [r3, #0] + 800f590: 8bfa ldrh r2, [r7, #30] + 800f592: 429a cmp r2, r3 + 800f594: d905 bls.n 800f5a2 + 800f596: 4b09 ldr r3, [pc, #36] ; (800f5bc ) + 800f598: 22d2 movs r2, #210 ; 0xd2 + 800f59a: 490e ldr r1, [pc, #56] ; (800f5d4 ) + 800f59c: 4809 ldr r0, [pc, #36] ; (800f5c4 ) + 800f59e: f001 fb13 bl 8010bc8 + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed); + 800f5a2: 4b0b ldr r3, [pc, #44] ; (800f5d0 ) + 800f5a4: 881a ldrh r2, [r3, #0] + 800f5a6: 8bfb ldrh r3, [r7, #30] + 800f5a8: 1ad3 subs r3, r2, r3 + 800f5aa: b29a uxth r2, r3 + 800f5ac: 4b08 ldr r3, [pc, #32] ; (800f5d0 ) + 800f5ae: 801a strh r2, [r3, #0] + + return pbufs_freed; + 800f5b0: 8bfb ldrh r3, [r7, #30] +} + 800f5b2: 4618 mov r0, r3 + 800f5b4: 3720 adds r7, #32 + 800f5b6: 46bd mov sp, r7 + 800f5b8: bd80 pop {r7, pc} + 800f5ba: bf00 nop + 800f5bc: 080149bc .word 0x080149bc + 800f5c0: 080149f8 .word 0x080149f8 + 800f5c4: 08014a04 .word 0x08014a04 + 800f5c8: 08014a2c .word 0x08014a2c + 800f5cc: 08014a40 .word 0x08014a40 + 800f5d0: 24007cc8 .word 0x24007cc8 + 800f5d4: 08014a60 .word 0x08014a60 + +0800f5d8 : + * (used for freeing other datagrams if not enough space) + * @return the number of pbufs freed + */ +static int +ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed) +{ + 800f5d8: b580 push {r7, lr} + 800f5da: b08a sub sp, #40 ; 0x28 + 800f5dc: af00 add r7, sp, #0 + 800f5de: 6078 str r0, [r7, #4] + 800f5e0: 6039 str r1, [r7, #0] + /* @todo Can't we simply remove the last datagram in the + * linked list behind reassdatagrams? + */ + struct ip_reassdata *r, *oldest, *prev, *oldest_prev; + int pbufs_freed = 0, pbufs_freed_current; + 800f5e2: 2300 movs r3, #0 + 800f5e4: 617b str r3, [r7, #20] + int other_datagrams; + + /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, + * but don't free the datagram that 'fraghdr' belongs to! */ + do { + oldest = NULL; + 800f5e6: 2300 movs r3, #0 + 800f5e8: 623b str r3, [r7, #32] + prev = NULL; + 800f5ea: 2300 movs r3, #0 + 800f5ec: 61fb str r3, [r7, #28] + oldest_prev = NULL; + 800f5ee: 2300 movs r3, #0 + 800f5f0: 61bb str r3, [r7, #24] + other_datagrams = 0; + 800f5f2: 2300 movs r3, #0 + 800f5f4: 613b str r3, [r7, #16] + r = reassdatagrams; + 800f5f6: 4b28 ldr r3, [pc, #160] ; (800f698 ) + 800f5f8: 681b ldr r3, [r3, #0] + 800f5fa: 627b str r3, [r7, #36] ; 0x24 + while (r != NULL) { + 800f5fc: e030 b.n 800f660 + if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) { + 800f5fe: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f600: 695a ldr r2, [r3, #20] + 800f602: 687b ldr r3, [r7, #4] + 800f604: 68db ldr r3, [r3, #12] + 800f606: 429a cmp r2, r3 + 800f608: d10c bne.n 800f624 + 800f60a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f60c: 699a ldr r2, [r3, #24] + 800f60e: 687b ldr r3, [r7, #4] + 800f610: 691b ldr r3, [r3, #16] + 800f612: 429a cmp r2, r3 + 800f614: d106 bne.n 800f624 + 800f616: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f618: 899a ldrh r2, [r3, #12] + 800f61a: 687b ldr r3, [r7, #4] + 800f61c: 889b ldrh r3, [r3, #4] + 800f61e: b29b uxth r3, r3 + 800f620: 429a cmp r2, r3 + 800f622: d014 beq.n 800f64e + /* Not the same datagram as fraghdr */ + other_datagrams++; + 800f624: 693b ldr r3, [r7, #16] + 800f626: 3301 adds r3, #1 + 800f628: 613b str r3, [r7, #16] + if (oldest == NULL) { + 800f62a: 6a3b ldr r3, [r7, #32] + 800f62c: 2b00 cmp r3, #0 + 800f62e: d104 bne.n 800f63a + oldest = r; + 800f630: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f632: 623b str r3, [r7, #32] + oldest_prev = prev; + 800f634: 69fb ldr r3, [r7, #28] + 800f636: 61bb str r3, [r7, #24] + 800f638: e009 b.n 800f64e + } else if (r->timer <= oldest->timer) { + 800f63a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f63c: 7fda ldrb r2, [r3, #31] + 800f63e: 6a3b ldr r3, [r7, #32] + 800f640: 7fdb ldrb r3, [r3, #31] + 800f642: 429a cmp r2, r3 + 800f644: d803 bhi.n 800f64e + /* older than the previous oldest */ + oldest = r; + 800f646: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f648: 623b str r3, [r7, #32] + oldest_prev = prev; + 800f64a: 69fb ldr r3, [r7, #28] + 800f64c: 61bb str r3, [r7, #24] + } + } + if (r->next != NULL) { + 800f64e: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f650: 681b ldr r3, [r3, #0] + 800f652: 2b00 cmp r3, #0 + 800f654: d001 beq.n 800f65a + prev = r; + 800f656: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f658: 61fb str r3, [r7, #28] + } + r = r->next; + 800f65a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f65c: 681b ldr r3, [r3, #0] + 800f65e: 627b str r3, [r7, #36] ; 0x24 + while (r != NULL) { + 800f660: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f662: 2b00 cmp r3, #0 + 800f664: d1cb bne.n 800f5fe + } + if (oldest != NULL) { + 800f666: 6a3b ldr r3, [r7, #32] + 800f668: 2b00 cmp r3, #0 + 800f66a: d008 beq.n 800f67e + pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev); + 800f66c: 69b9 ldr r1, [r7, #24] + 800f66e: 6a38 ldr r0, [r7, #32] + 800f670: f7ff ff0e bl 800f490 + 800f674: 60f8 str r0, [r7, #12] + pbufs_freed += pbufs_freed_current; + 800f676: 697a ldr r2, [r7, #20] + 800f678: 68fb ldr r3, [r7, #12] + 800f67a: 4413 add r3, r2 + 800f67c: 617b str r3, [r7, #20] + } + } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1)); + 800f67e: 697a ldr r2, [r7, #20] + 800f680: 683b ldr r3, [r7, #0] + 800f682: 429a cmp r2, r3 + 800f684: da02 bge.n 800f68c + 800f686: 693b ldr r3, [r7, #16] + 800f688: 2b01 cmp r3, #1 + 800f68a: dcac bgt.n 800f5e6 + return pbufs_freed; + 800f68c: 697b ldr r3, [r7, #20] +} + 800f68e: 4618 mov r0, r3 + 800f690: 3728 adds r7, #40 ; 0x28 + 800f692: 46bd mov sp, r7 + 800f694: bd80 pop {r7, pc} + 800f696: bf00 nop + 800f698: 24007cc4 .word 0x24007cc4 + +0800f69c : + * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space) + * @return A pointer to the queue location into which the fragment was enqueued + */ +static struct ip_reassdata * +ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen) +{ + 800f69c: b580 push {r7, lr} + 800f69e: b084 sub sp, #16 + 800f6a0: af00 add r7, sp, #0 + 800f6a2: 6078 str r0, [r7, #4] + 800f6a4: 6039 str r1, [r7, #0] +#if ! IP_REASS_FREE_OLDEST + LWIP_UNUSED_ARG(clen); +#endif + + /* No matching previous fragment found, allocate a new reassdata struct */ + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + 800f6a6: 2004 movs r0, #4 + 800f6a8: f7f6 fcb8 bl 800601c + 800f6ac: 60f8 str r0, [r7, #12] + if (ipr == NULL) { + 800f6ae: 68fb ldr r3, [r7, #12] + 800f6b0: 2b00 cmp r3, #0 + 800f6b2: d110 bne.n 800f6d6 +#if IP_REASS_FREE_OLDEST + if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) { + 800f6b4: 6839 ldr r1, [r7, #0] + 800f6b6: 6878 ldr r0, [r7, #4] + 800f6b8: f7ff ff8e bl 800f5d8 + 800f6bc: 4602 mov r2, r0 + 800f6be: 683b ldr r3, [r7, #0] + 800f6c0: 4293 cmp r3, r2 + 800f6c2: dc03 bgt.n 800f6cc + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + 800f6c4: 2004 movs r0, #4 + 800f6c6: f7f6 fca9 bl 800601c + 800f6ca: 60f8 str r0, [r7, #12] + } + if (ipr == NULL) + 800f6cc: 68fb ldr r3, [r7, #12] + 800f6ce: 2b00 cmp r3, #0 + 800f6d0: d101 bne.n 800f6d6 +#endif /* IP_REASS_FREE_OLDEST */ + { + IPFRAG_STATS_INC(ip_frag.memerr); + LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n")); + return NULL; + 800f6d2: 2300 movs r3, #0 + 800f6d4: e016 b.n 800f704 + } + } + memset(ipr, 0, sizeof(struct ip_reassdata)); + 800f6d6: 2220 movs r2, #32 + 800f6d8: 2100 movs r1, #0 + 800f6da: 68f8 ldr r0, [r7, #12] + 800f6dc: f001 fbd2 bl 8010e84 + ipr->timer = IP_REASS_MAXAGE; + 800f6e0: 68fb ldr r3, [r7, #12] + 800f6e2: 220f movs r2, #15 + 800f6e4: 77da strb r2, [r3, #31] + + /* enqueue the new structure to the front of the list */ + ipr->next = reassdatagrams; + 800f6e6: 4b09 ldr r3, [pc, #36] ; (800f70c ) + 800f6e8: 681a ldr r2, [r3, #0] + 800f6ea: 68fb ldr r3, [r7, #12] + 800f6ec: 601a str r2, [r3, #0] + reassdatagrams = ipr; + 800f6ee: 4a07 ldr r2, [pc, #28] ; (800f70c ) + 800f6f0: 68fb ldr r3, [r7, #12] + 800f6f2: 6013 str r3, [r2, #0] + /* copy the ip header for later tests and input */ + /* @todo: no ip options supported? */ + SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN); + 800f6f4: 68fb ldr r3, [r7, #12] + 800f6f6: 3308 adds r3, #8 + 800f6f8: 2214 movs r2, #20 + 800f6fa: 6879 ldr r1, [r7, #4] + 800f6fc: 4618 mov r0, r3 + 800f6fe: f001 fc44 bl 8010f8a + return ipr; + 800f702: 68fb ldr r3, [r7, #12] +} + 800f704: 4618 mov r0, r3 + 800f706: 3710 adds r7, #16 + 800f708: 46bd mov sp, r7 + 800f70a: bd80 pop {r7, pc} + 800f70c: 24007cc4 .word 0x24007cc4 + +0800f710 : + * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs. + * @param ipr points to the queue entry to dequeue + */ +static void +ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + 800f710: b580 push {r7, lr} + 800f712: b082 sub sp, #8 + 800f714: af00 add r7, sp, #0 + 800f716: 6078 str r0, [r7, #4] + 800f718: 6039 str r1, [r7, #0] + /* dequeue the reass struct */ + if (reassdatagrams == ipr) { + 800f71a: 4b10 ldr r3, [pc, #64] ; (800f75c ) + 800f71c: 681b ldr r3, [r3, #0] + 800f71e: 687a ldr r2, [r7, #4] + 800f720: 429a cmp r2, r3 + 800f722: d104 bne.n 800f72e + /* it was the first in the list */ + reassdatagrams = ipr->next; + 800f724: 687b ldr r3, [r7, #4] + 800f726: 681b ldr r3, [r3, #0] + 800f728: 4a0c ldr r2, [pc, #48] ; (800f75c ) + 800f72a: 6013 str r3, [r2, #0] + 800f72c: e00d b.n 800f74a + } else { + /* it wasn't the first, so it must have a valid 'prev' */ + LWIP_ASSERT("sanity check linked list", prev != NULL); + 800f72e: 683b ldr r3, [r7, #0] + 800f730: 2b00 cmp r3, #0 + 800f732: d106 bne.n 800f742 + 800f734: 4b0a ldr r3, [pc, #40] ; (800f760 ) + 800f736: f240 1245 movw r2, #325 ; 0x145 + 800f73a: 490a ldr r1, [pc, #40] ; (800f764 ) + 800f73c: 480a ldr r0, [pc, #40] ; (800f768 ) + 800f73e: f001 fa43 bl 8010bc8 + prev->next = ipr->next; + 800f742: 687b ldr r3, [r7, #4] + 800f744: 681a ldr r2, [r3, #0] + 800f746: 683b ldr r3, [r7, #0] + 800f748: 601a str r2, [r3, #0] + } + + /* now we can free the ip_reassdata struct */ + memp_free(MEMP_REASSDATA, ipr); + 800f74a: 6879 ldr r1, [r7, #4] + 800f74c: 2004 movs r0, #4 + 800f74e: f7f6 fcd5 bl 80060fc +} + 800f752: bf00 nop + 800f754: 3708 adds r7, #8 + 800f756: 46bd mov sp, r7 + 800f758: bd80 pop {r7, pc} + 800f75a: bf00 nop + 800f75c: 24007cc4 .word 0x24007cc4 + 800f760: 080149bc .word 0x080149bc + 800f764: 08014a84 .word 0x08014a84 + 800f768: 08014a04 .word 0x08014a04 + +0800f76c : + * @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet) + * @return see IP_REASS_VALIDATE_* defines + */ +static int +ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last) +{ + 800f76c: b580 push {r7, lr} + 800f76e: b08c sub sp, #48 ; 0x30 + 800f770: af00 add r7, sp, #0 + 800f772: 60f8 str r0, [r7, #12] + 800f774: 60b9 str r1, [r7, #8] + 800f776: 607a str r2, [r7, #4] + struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL; + 800f778: 2300 movs r3, #0 + 800f77a: 62bb str r3, [r7, #40] ; 0x28 + struct pbuf *q; + u16_t offset, len; + u8_t hlen; + struct ip_hdr *fraghdr; + int valid = 1; + 800f77c: 2301 movs r3, #1 + 800f77e: 623b str r3, [r7, #32] + + /* Extract length and fragment offset from current fragment */ + fraghdr = (struct ip_hdr *)new_p->payload; + 800f780: 68bb ldr r3, [r7, #8] + 800f782: 685b ldr r3, [r3, #4] + 800f784: 61fb str r3, [r7, #28] + len = lwip_ntohs(IPH_LEN(fraghdr)); + 800f786: 69fb ldr r3, [r7, #28] + 800f788: 885b ldrh r3, [r3, #2] + 800f78a: b29b uxth r3, r3 + 800f78c: 4618 mov r0, r3 + 800f78e: f7f5 fedd bl 800554c + 800f792: 4603 mov r3, r0 + 800f794: 837b strh r3, [r7, #26] + hlen = IPH_HL_BYTES(fraghdr); + 800f796: 69fb ldr r3, [r7, #28] + 800f798: 781b ldrb r3, [r3, #0] + 800f79a: f003 030f and.w r3, r3, #15 + 800f79e: b2db uxtb r3, r3 + 800f7a0: 009b lsls r3, r3, #2 + 800f7a2: 767b strb r3, [r7, #25] + if (hlen > len) { + 800f7a4: 7e7b ldrb r3, [r7, #25] + 800f7a6: b29b uxth r3, r3 + 800f7a8: 8b7a ldrh r2, [r7, #26] + 800f7aa: 429a cmp r2, r3 + 800f7ac: d202 bcs.n 800f7b4 + /* invalid datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 800f7ae: f04f 33ff mov.w r3, #4294967295 + 800f7b2: e135 b.n 800fa20 + } + len = (u16_t)(len - hlen); + 800f7b4: 7e7b ldrb r3, [r7, #25] + 800f7b6: b29b uxth r3, r3 + 800f7b8: 8b7a ldrh r2, [r7, #26] + 800f7ba: 1ad3 subs r3, r2, r3 + 800f7bc: 837b strh r3, [r7, #26] + offset = IPH_OFFSET_BYTES(fraghdr); + 800f7be: 69fb ldr r3, [r7, #28] + 800f7c0: 88db ldrh r3, [r3, #6] + 800f7c2: b29b uxth r3, r3 + 800f7c4: 4618 mov r0, r3 + 800f7c6: f7f5 fec1 bl 800554c + 800f7ca: 4603 mov r3, r0 + 800f7cc: f3c3 030c ubfx r3, r3, #0, #13 + 800f7d0: b29b uxth r3, r3 + 800f7d2: 00db lsls r3, r3, #3 + 800f7d4: 82fb strh r3, [r7, #22] + /* overwrite the fragment's ip header from the pbuf with our helper struct, + * and setup the embedded helper structure. */ + /* make sure the struct ip_reass_helper fits into the IP header */ + LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN", + sizeof(struct ip_reass_helper) <= IP_HLEN); + iprh = (struct ip_reass_helper *)new_p->payload; + 800f7d6: 68bb ldr r3, [r7, #8] + 800f7d8: 685b ldr r3, [r3, #4] + 800f7da: 62fb str r3, [r7, #44] ; 0x2c + iprh->next_pbuf = NULL; + 800f7dc: 6afb ldr r3, [r7, #44] ; 0x2c + 800f7de: 2200 movs r2, #0 + 800f7e0: 701a strb r2, [r3, #0] + 800f7e2: 2200 movs r2, #0 + 800f7e4: 705a strb r2, [r3, #1] + 800f7e6: 2200 movs r2, #0 + 800f7e8: 709a strb r2, [r3, #2] + 800f7ea: 2200 movs r2, #0 + 800f7ec: 70da strb r2, [r3, #3] + iprh->start = offset; + 800f7ee: 6afb ldr r3, [r7, #44] ; 0x2c + 800f7f0: 8afa ldrh r2, [r7, #22] + 800f7f2: 809a strh r2, [r3, #4] + iprh->end = (u16_t)(offset + len); + 800f7f4: 8afa ldrh r2, [r7, #22] + 800f7f6: 8b7b ldrh r3, [r7, #26] + 800f7f8: 4413 add r3, r2 + 800f7fa: b29a uxth r2, r3 + 800f7fc: 6afb ldr r3, [r7, #44] ; 0x2c + 800f7fe: 80da strh r2, [r3, #6] + if (iprh->end < offset) { + 800f800: 6afb ldr r3, [r7, #44] ; 0x2c + 800f802: 88db ldrh r3, [r3, #6] + 800f804: b29b uxth r3, r3 + 800f806: 8afa ldrh r2, [r7, #22] + 800f808: 429a cmp r2, r3 + 800f80a: d902 bls.n 800f812 + /* u16_t overflow, cannot handle this */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 800f80c: f04f 33ff mov.w r3, #4294967295 + 800f810: e106 b.n 800fa20 + } + + /* Iterate through until we either get to the end of the list (append), + * or we find one with a larger offset (insert). */ + for (q = ipr->p; q != NULL;) { + 800f812: 68fb ldr r3, [r7, #12] + 800f814: 685b ldr r3, [r3, #4] + 800f816: 627b str r3, [r7, #36] ; 0x24 + 800f818: e068 b.n 800f8ec + iprh_tmp = (struct ip_reass_helper *)q->payload; + 800f81a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f81c: 685b ldr r3, [r3, #4] + 800f81e: 613b str r3, [r7, #16] + if (iprh->start < iprh_tmp->start) { + 800f820: 6afb ldr r3, [r7, #44] ; 0x2c + 800f822: 889b ldrh r3, [r3, #4] + 800f824: b29a uxth r2, r3 + 800f826: 693b ldr r3, [r7, #16] + 800f828: 889b ldrh r3, [r3, #4] + 800f82a: b29b uxth r3, r3 + 800f82c: 429a cmp r2, r3 + 800f82e: d235 bcs.n 800f89c + /* the new pbuf should be inserted before this */ + iprh->next_pbuf = q; + 800f830: 6afb ldr r3, [r7, #44] ; 0x2c + 800f832: 6a7a ldr r2, [r7, #36] ; 0x24 + 800f834: 601a str r2, [r3, #0] + if (iprh_prev != NULL) { + 800f836: 6abb ldr r3, [r7, #40] ; 0x28 + 800f838: 2b00 cmp r3, #0 + 800f83a: d020 beq.n 800f87e + /* not the fragment with the lowest offset */ +#if IP_REASS_CHECK_OVERLAP + if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) { + 800f83c: 6afb ldr r3, [r7, #44] ; 0x2c + 800f83e: 889b ldrh r3, [r3, #4] + 800f840: b29a uxth r2, r3 + 800f842: 6abb ldr r3, [r7, #40] ; 0x28 + 800f844: 88db ldrh r3, [r3, #6] + 800f846: b29b uxth r3, r3 + 800f848: 429a cmp r2, r3 + 800f84a: d307 bcc.n 800f85c + 800f84c: 6afb ldr r3, [r7, #44] ; 0x2c + 800f84e: 88db ldrh r3, [r3, #6] + 800f850: b29a uxth r2, r3 + 800f852: 693b ldr r3, [r7, #16] + 800f854: 889b ldrh r3, [r3, #4] + 800f856: b29b uxth r3, r3 + 800f858: 429a cmp r2, r3 + 800f85a: d902 bls.n 800f862 + /* fragment overlaps with previous or following, throw away */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 800f85c: f04f 33ff mov.w r3, #4294967295 + 800f860: e0de b.n 800fa20 + } +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + 800f862: 6abb ldr r3, [r7, #40] ; 0x28 + 800f864: 68ba ldr r2, [r7, #8] + 800f866: 601a str r2, [r3, #0] + if (iprh_prev->end != iprh->start) { + 800f868: 6abb ldr r3, [r7, #40] ; 0x28 + 800f86a: 88db ldrh r3, [r3, #6] + 800f86c: b29a uxth r2, r3 + 800f86e: 6afb ldr r3, [r7, #44] ; 0x2c + 800f870: 889b ldrh r3, [r3, #4] + 800f872: b29b uxth r3, r3 + 800f874: 429a cmp r2, r3 + 800f876: d03d beq.n 800f8f4 + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + 800f878: 2300 movs r3, #0 + 800f87a: 623b str r3, [r7, #32] + } +#endif /* IP_REASS_CHECK_OVERLAP */ + /* fragment with the lowest offset */ + ipr->p = new_p; + } + break; + 800f87c: e03a b.n 800f8f4 + if (iprh->end > iprh_tmp->start) { + 800f87e: 6afb ldr r3, [r7, #44] ; 0x2c + 800f880: 88db ldrh r3, [r3, #6] + 800f882: b29a uxth r2, r3 + 800f884: 693b ldr r3, [r7, #16] + 800f886: 889b ldrh r3, [r3, #4] + 800f888: b29b uxth r3, r3 + 800f88a: 429a cmp r2, r3 + 800f88c: d902 bls.n 800f894 + return IP_REASS_VALIDATE_PBUF_DROPPED; + 800f88e: f04f 33ff mov.w r3, #4294967295 + 800f892: e0c5 b.n 800fa20 + ipr->p = new_p; + 800f894: 68fb ldr r3, [r7, #12] + 800f896: 68ba ldr r2, [r7, #8] + 800f898: 605a str r2, [r3, #4] + break; + 800f89a: e02b b.n 800f8f4 + } else if (iprh->start == iprh_tmp->start) { + 800f89c: 6afb ldr r3, [r7, #44] ; 0x2c + 800f89e: 889b ldrh r3, [r3, #4] + 800f8a0: b29a uxth r2, r3 + 800f8a2: 693b ldr r3, [r7, #16] + 800f8a4: 889b ldrh r3, [r3, #4] + 800f8a6: b29b uxth r3, r3 + 800f8a8: 429a cmp r2, r3 + 800f8aa: d102 bne.n 800f8b2 + /* received the same datagram twice: no need to keep the datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 800f8ac: f04f 33ff mov.w r3, #4294967295 + 800f8b0: e0b6 b.n 800fa20 +#if IP_REASS_CHECK_OVERLAP + } else if (iprh->start < iprh_tmp->end) { + 800f8b2: 6afb ldr r3, [r7, #44] ; 0x2c + 800f8b4: 889b ldrh r3, [r3, #4] + 800f8b6: b29a uxth r2, r3 + 800f8b8: 693b ldr r3, [r7, #16] + 800f8ba: 88db ldrh r3, [r3, #6] + 800f8bc: b29b uxth r3, r3 + 800f8be: 429a cmp r2, r3 + 800f8c0: d202 bcs.n 800f8c8 + /* overlap: no need to keep the new datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + 800f8c2: f04f 33ff mov.w r3, #4294967295 + 800f8c6: e0ab b.n 800fa20 +#endif /* IP_REASS_CHECK_OVERLAP */ + } else { + /* Check if the fragments received so far have no holes. */ + if (iprh_prev != NULL) { + 800f8c8: 6abb ldr r3, [r7, #40] ; 0x28 + 800f8ca: 2b00 cmp r3, #0 + 800f8cc: d009 beq.n 800f8e2 + if (iprh_prev->end != iprh_tmp->start) { + 800f8ce: 6abb ldr r3, [r7, #40] ; 0x28 + 800f8d0: 88db ldrh r3, [r3, #6] + 800f8d2: b29a uxth r2, r3 + 800f8d4: 693b ldr r3, [r7, #16] + 800f8d6: 889b ldrh r3, [r3, #4] + 800f8d8: b29b uxth r3, r3 + 800f8da: 429a cmp r2, r3 + 800f8dc: d001 beq.n 800f8e2 + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + 800f8de: 2300 movs r3, #0 + 800f8e0: 623b str r3, [r7, #32] + } + } + } + q = iprh_tmp->next_pbuf; + 800f8e2: 693b ldr r3, [r7, #16] + 800f8e4: 681b ldr r3, [r3, #0] + 800f8e6: 627b str r3, [r7, #36] ; 0x24 + iprh_prev = iprh_tmp; + 800f8e8: 693b ldr r3, [r7, #16] + 800f8ea: 62bb str r3, [r7, #40] ; 0x28 + for (q = ipr->p; q != NULL;) { + 800f8ec: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f8ee: 2b00 cmp r3, #0 + 800f8f0: d193 bne.n 800f81a + 800f8f2: e000 b.n 800f8f6 + break; + 800f8f4: bf00 nop + } + + /* If q is NULL, then we made it to the end of the list. Determine what to do now */ + if (q == NULL) { + 800f8f6: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f8f8: 2b00 cmp r3, #0 + 800f8fa: d12d bne.n 800f958 + if (iprh_prev != NULL) { + 800f8fc: 6abb ldr r3, [r7, #40] ; 0x28 + 800f8fe: 2b00 cmp r3, #0 + 800f900: d01c beq.n 800f93c + /* this is (for now), the fragment with the highest offset: + * chain it to the last fragment */ +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start); + 800f902: 6abb ldr r3, [r7, #40] ; 0x28 + 800f904: 88db ldrh r3, [r3, #6] + 800f906: b29a uxth r2, r3 + 800f908: 6afb ldr r3, [r7, #44] ; 0x2c + 800f90a: 889b ldrh r3, [r3, #4] + 800f90c: b29b uxth r3, r3 + 800f90e: 429a cmp r2, r3 + 800f910: d906 bls.n 800f920 + 800f912: 4b45 ldr r3, [pc, #276] ; (800fa28 ) + 800f914: f44f 72db mov.w r2, #438 ; 0x1b6 + 800f918: 4944 ldr r1, [pc, #272] ; (800fa2c ) + 800f91a: 4845 ldr r0, [pc, #276] ; (800fa30 ) + 800f91c: f001 f954 bl 8010bc8 +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + 800f920: 6abb ldr r3, [r7, #40] ; 0x28 + 800f922: 68ba ldr r2, [r7, #8] + 800f924: 601a str r2, [r3, #0] + if (iprh_prev->end != iprh->start) { + 800f926: 6abb ldr r3, [r7, #40] ; 0x28 + 800f928: 88db ldrh r3, [r3, #6] + 800f92a: b29a uxth r2, r3 + 800f92c: 6afb ldr r3, [r7, #44] ; 0x2c + 800f92e: 889b ldrh r3, [r3, #4] + 800f930: b29b uxth r3, r3 + 800f932: 429a cmp r2, r3 + 800f934: d010 beq.n 800f958 + valid = 0; + 800f936: 2300 movs r3, #0 + 800f938: 623b str r3, [r7, #32] + 800f93a: e00d b.n 800f958 + } + } else { +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("no previous fragment, this must be the first fragment!", + 800f93c: 68fb ldr r3, [r7, #12] + 800f93e: 685b ldr r3, [r3, #4] + 800f940: 2b00 cmp r3, #0 + 800f942: d006 beq.n 800f952 + 800f944: 4b38 ldr r3, [pc, #224] ; (800fa28 ) + 800f946: f44f 72df mov.w r2, #446 ; 0x1be + 800f94a: 493a ldr r1, [pc, #232] ; (800fa34 ) + 800f94c: 4838 ldr r0, [pc, #224] ; (800fa30 ) + 800f94e: f001 f93b bl 8010bc8 + ipr->p == NULL); +#endif /* IP_REASS_CHECK_OVERLAP */ + /* this is the first fragment we ever received for this ip datagram */ + ipr->p = new_p; + 800f952: 68fb ldr r3, [r7, #12] + 800f954: 68ba ldr r2, [r7, #8] + 800f956: 605a str r2, [r3, #4] + } + } + + /* At this point, the validation part begins: */ + /* If we already received the last fragment */ + if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) { + 800f958: 687b ldr r3, [r7, #4] + 800f95a: 2b00 cmp r3, #0 + 800f95c: d105 bne.n 800f96a + 800f95e: 68fb ldr r3, [r7, #12] + 800f960: 7f9b ldrb r3, [r3, #30] + 800f962: f003 0301 and.w r3, r3, #1 + 800f966: 2b00 cmp r3, #0 + 800f968: d059 beq.n 800fa1e + /* and had no holes so far */ + if (valid) { + 800f96a: 6a3b ldr r3, [r7, #32] + 800f96c: 2b00 cmp r3, #0 + 800f96e: d04f beq.n 800fa10 + /* then check if the rest of the fragments is here */ + /* Check if the queue starts with the first datagram */ + if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) { + 800f970: 68fb ldr r3, [r7, #12] + 800f972: 685b ldr r3, [r3, #4] + 800f974: 2b00 cmp r3, #0 + 800f976: d006 beq.n 800f986 + 800f978: 68fb ldr r3, [r7, #12] + 800f97a: 685b ldr r3, [r3, #4] + 800f97c: 685b ldr r3, [r3, #4] + 800f97e: 889b ldrh r3, [r3, #4] + 800f980: b29b uxth r3, r3 + 800f982: 2b00 cmp r3, #0 + 800f984: d002 beq.n 800f98c + valid = 0; + 800f986: 2300 movs r3, #0 + 800f988: 623b str r3, [r7, #32] + 800f98a: e041 b.n 800fa10 + } else { + /* and check that there are no holes after this datagram */ + iprh_prev = iprh; + 800f98c: 6afb ldr r3, [r7, #44] ; 0x2c + 800f98e: 62bb str r3, [r7, #40] ; 0x28 + q = iprh->next_pbuf; + 800f990: 6afb ldr r3, [r7, #44] ; 0x2c + 800f992: 681b ldr r3, [r3, #0] + 800f994: 627b str r3, [r7, #36] ; 0x24 + while (q != NULL) { + 800f996: e012 b.n 800f9be + iprh = (struct ip_reass_helper *)q->payload; + 800f998: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f99a: 685b ldr r3, [r3, #4] + 800f99c: 62fb str r3, [r7, #44] ; 0x2c + if (iprh_prev->end != iprh->start) { + 800f99e: 6abb ldr r3, [r7, #40] ; 0x28 + 800f9a0: 88db ldrh r3, [r3, #6] + 800f9a2: b29a uxth r2, r3 + 800f9a4: 6afb ldr r3, [r7, #44] ; 0x2c + 800f9a6: 889b ldrh r3, [r3, #4] + 800f9a8: b29b uxth r3, r3 + 800f9aa: 429a cmp r2, r3 + 800f9ac: d002 beq.n 800f9b4 + valid = 0; + 800f9ae: 2300 movs r3, #0 + 800f9b0: 623b str r3, [r7, #32] + break; + 800f9b2: e007 b.n 800f9c4 + } + iprh_prev = iprh; + 800f9b4: 6afb ldr r3, [r7, #44] ; 0x2c + 800f9b6: 62bb str r3, [r7, #40] ; 0x28 + q = iprh->next_pbuf; + 800f9b8: 6afb ldr r3, [r7, #44] ; 0x2c + 800f9ba: 681b ldr r3, [r3, #0] + 800f9bc: 627b str r3, [r7, #36] ; 0x24 + while (q != NULL) { + 800f9be: 6a7b ldr r3, [r7, #36] ; 0x24 + 800f9c0: 2b00 cmp r3, #0 + 800f9c2: d1e9 bne.n 800f998 + } + /* if still valid, all fragments are received + * (because to the MF==0 already arrived */ + if (valid) { + 800f9c4: 6a3b ldr r3, [r7, #32] + 800f9c6: 2b00 cmp r3, #0 + 800f9c8: d022 beq.n 800fa10 + LWIP_ASSERT("sanity check", ipr->p != NULL); + 800f9ca: 68fb ldr r3, [r7, #12] + 800f9cc: 685b ldr r3, [r3, #4] + 800f9ce: 2b00 cmp r3, #0 + 800f9d0: d106 bne.n 800f9e0 + 800f9d2: 4b15 ldr r3, [pc, #84] ; (800fa28 ) + 800f9d4: f240 12df movw r2, #479 ; 0x1df + 800f9d8: 4917 ldr r1, [pc, #92] ; (800fa38 ) + 800f9da: 4815 ldr r0, [pc, #84] ; (800fa30 ) + 800f9dc: f001 f8f4 bl 8010bc8 + LWIP_ASSERT("sanity check", + 800f9e0: 68fb ldr r3, [r7, #12] + 800f9e2: 685b ldr r3, [r3, #4] + 800f9e4: 685b ldr r3, [r3, #4] + 800f9e6: 6afa ldr r2, [r7, #44] ; 0x2c + 800f9e8: 429a cmp r2, r3 + 800f9ea: d106 bne.n 800f9fa + 800f9ec: 4b0e ldr r3, [pc, #56] ; (800fa28 ) + 800f9ee: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 800f9f2: 4911 ldr r1, [pc, #68] ; (800fa38 ) + 800f9f4: 480e ldr r0, [pc, #56] ; (800fa30 ) + 800f9f6: f001 f8e7 bl 8010bc8 + ((struct ip_reass_helper *)ipr->p->payload) != iprh); + LWIP_ASSERT("validate_datagram:next_pbuf!=NULL", + 800f9fa: 6afb ldr r3, [r7, #44] ; 0x2c + 800f9fc: 681b ldr r3, [r3, #0] + 800f9fe: 2b00 cmp r3, #0 + 800fa00: d006 beq.n 800fa10 + 800fa02: 4b09 ldr r3, [pc, #36] ; (800fa28 ) + 800fa04: f44f 72f1 mov.w r2, #482 ; 0x1e2 + 800fa08: 490c ldr r1, [pc, #48] ; (800fa3c ) + 800fa0a: 4809 ldr r0, [pc, #36] ; (800fa30 ) + 800fa0c: f001 f8dc bl 8010bc8 + } + } + /* If valid is 0 here, there are some fragments missing in the middle + * (since MF == 0 has already arrived). Such datagrams simply time out if + * no more fragments are received... */ + return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED; + 800fa10: 6a3b ldr r3, [r7, #32] + 800fa12: 2b00 cmp r3, #0 + 800fa14: bf14 ite ne + 800fa16: 2301 movne r3, #1 + 800fa18: 2300 moveq r3, #0 + 800fa1a: b2db uxtb r3, r3 + 800fa1c: e000 b.n 800fa20 + } + /* If we come here, not all fragments were received, yet! */ + return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */ + 800fa1e: 2300 movs r3, #0 +} + 800fa20: 4618 mov r0, r3 + 800fa22: 3730 adds r7, #48 ; 0x30 + 800fa24: 46bd mov sp, r7 + 800fa26: bd80 pop {r7, pc} + 800fa28: 080149bc .word 0x080149bc + 800fa2c: 08014aa0 .word 0x08014aa0 + 800fa30: 08014a04 .word 0x08014a04 + 800fa34: 08014ac0 .word 0x08014ac0 + 800fa38: 08014af8 .word 0x08014af8 + 800fa3c: 08014b08 .word 0x08014b08 + +0800fa40 : + * @param p points to a pbuf chain of the fragment + * @return NULL if reassembly is incomplete, ? otherwise + */ +struct pbuf * +ip4_reass(struct pbuf *p) +{ + 800fa40: b580 push {r7, lr} + 800fa42: b08e sub sp, #56 ; 0x38 + 800fa44: af00 add r7, sp, #0 + 800fa46: 6078 str r0, [r7, #4] + int is_last; + + IPFRAG_STATS_INC(ip_frag.recv); + MIB2_STATS_INC(mib2.ipreasmreqds); + + fraghdr = (struct ip_hdr *)p->payload; + 800fa48: 687b ldr r3, [r7, #4] + 800fa4a: 685b ldr r3, [r3, #4] + 800fa4c: 62bb str r3, [r7, #40] ; 0x28 + + if (IPH_HL_BYTES(fraghdr) != IP_HLEN) { + 800fa4e: 6abb ldr r3, [r7, #40] ; 0x28 + 800fa50: 781b ldrb r3, [r3, #0] + 800fa52: f003 030f and.w r3, r3, #15 + 800fa56: b2db uxtb r3, r3 + 800fa58: 009b lsls r3, r3, #2 + 800fa5a: b2db uxtb r3, r3 + 800fa5c: 2b14 cmp r3, #20 + 800fa5e: f040 8171 bne.w 800fd44 + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n")); + IPFRAG_STATS_INC(ip_frag.err); + goto nullreturn; + } + + offset = IPH_OFFSET_BYTES(fraghdr); + 800fa62: 6abb ldr r3, [r7, #40] ; 0x28 + 800fa64: 88db ldrh r3, [r3, #6] + 800fa66: b29b uxth r3, r3 + 800fa68: 4618 mov r0, r3 + 800fa6a: f7f5 fd6f bl 800554c + 800fa6e: 4603 mov r3, r0 + 800fa70: f3c3 030c ubfx r3, r3, #0, #13 + 800fa74: b29b uxth r3, r3 + 800fa76: 00db lsls r3, r3, #3 + 800fa78: 84fb strh r3, [r7, #38] ; 0x26 + len = lwip_ntohs(IPH_LEN(fraghdr)); + 800fa7a: 6abb ldr r3, [r7, #40] ; 0x28 + 800fa7c: 885b ldrh r3, [r3, #2] + 800fa7e: b29b uxth r3, r3 + 800fa80: 4618 mov r0, r3 + 800fa82: f7f5 fd63 bl 800554c + 800fa86: 4603 mov r3, r0 + 800fa88: 84bb strh r3, [r7, #36] ; 0x24 + hlen = IPH_HL_BYTES(fraghdr); + 800fa8a: 6abb ldr r3, [r7, #40] ; 0x28 + 800fa8c: 781b ldrb r3, [r3, #0] + 800fa8e: f003 030f and.w r3, r3, #15 + 800fa92: b2db uxtb r3, r3 + 800fa94: 009b lsls r3, r3, #2 + 800fa96: f887 3023 strb.w r3, [r7, #35] ; 0x23 + if (hlen > len) { + 800fa9a: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800fa9e: b29b uxth r3, r3 + 800faa0: 8cba ldrh r2, [r7, #36] ; 0x24 + 800faa2: 429a cmp r2, r3 + 800faa4: f0c0 8150 bcc.w 800fd48 + /* invalid datagram */ + goto nullreturn; + } + len = (u16_t)(len - hlen); + 800faa8: f897 3023 ldrb.w r3, [r7, #35] ; 0x23 + 800faac: b29b uxth r3, r3 + 800faae: 8cba ldrh r2, [r7, #36] ; 0x24 + 800fab0: 1ad3 subs r3, r2, r3 + 800fab2: 84bb strh r3, [r7, #36] ; 0x24 + + /* Check if we are allowed to enqueue more datagrams. */ + clen = pbuf_clen(p); + 800fab4: 6878 ldr r0, [r7, #4] + 800fab6: f7f7 fb15 bl 80070e4 + 800faba: 4603 mov r3, r0 + 800fabc: 843b strh r3, [r7, #32] + if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { + 800fabe: 4b8c ldr r3, [pc, #560] ; (800fcf0 ) + 800fac0: 881b ldrh r3, [r3, #0] + 800fac2: 461a mov r2, r3 + 800fac4: 8c3b ldrh r3, [r7, #32] + 800fac6: 4413 add r3, r2 + 800fac8: 2b0a cmp r3, #10 + 800faca: dd10 ble.n 800faee +#if IP_REASS_FREE_OLDEST + if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || + 800facc: 8c3b ldrh r3, [r7, #32] + 800face: 4619 mov r1, r3 + 800fad0: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800fad2: f7ff fd81 bl 800f5d8 + 800fad6: 4603 mov r3, r0 + 800fad8: 2b00 cmp r3, #0 + 800fada: f000 8137 beq.w 800fd4c + ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS)) + 800fade: 4b84 ldr r3, [pc, #528] ; (800fcf0 ) + 800fae0: 881b ldrh r3, [r3, #0] + 800fae2: 461a mov r2, r3 + 800fae4: 8c3b ldrh r3, [r7, #32] + 800fae6: 4413 add r3, r2 + if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || + 800fae8: 2b0a cmp r3, #10 + 800faea: f300 812f bgt.w 800fd4c + } + } + + /* Look for the datagram the fragment belongs to in the current datagram queue, + * remembering the previous in the queue for later dequeueing. */ + for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { + 800faee: 4b81 ldr r3, [pc, #516] ; (800fcf4 ) + 800faf0: 681b ldr r3, [r3, #0] + 800faf2: 633b str r3, [r7, #48] ; 0x30 + 800faf4: e015 b.n 800fb22 + /* Check if the incoming fragment matches the one currently present + in the reassembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) { + 800faf6: 6b3b ldr r3, [r7, #48] ; 0x30 + 800faf8: 695a ldr r2, [r3, #20] + 800fafa: 6abb ldr r3, [r7, #40] ; 0x28 + 800fafc: 68db ldr r3, [r3, #12] + 800fafe: 429a cmp r2, r3 + 800fb00: d10c bne.n 800fb1c + 800fb02: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb04: 699a ldr r2, [r3, #24] + 800fb06: 6abb ldr r3, [r7, #40] ; 0x28 + 800fb08: 691b ldr r3, [r3, #16] + 800fb0a: 429a cmp r2, r3 + 800fb0c: d106 bne.n 800fb1c + 800fb0e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb10: 899a ldrh r2, [r3, #12] + 800fb12: 6abb ldr r3, [r7, #40] ; 0x28 + 800fb14: 889b ldrh r3, [r3, #4] + 800fb16: b29b uxth r3, r3 + 800fb18: 429a cmp r2, r3 + 800fb1a: d006 beq.n 800fb2a + for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { + 800fb1c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb1e: 681b ldr r3, [r3, #0] + 800fb20: 633b str r3, [r7, #48] ; 0x30 + 800fb22: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb24: 2b00 cmp r3, #0 + 800fb26: d1e6 bne.n 800faf6 + 800fb28: e000 b.n 800fb2c + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n", + lwip_ntohs(IPH_ID(fraghdr)))); + IPFRAG_STATS_INC(ip_frag.cachehit); + break; + 800fb2a: bf00 nop + } + } + + if (ipr == NULL) { + 800fb2c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb2e: 2b00 cmp r3, #0 + 800fb30: d109 bne.n 800fb46 + /* Enqueue a new datagram into the datagram queue */ + ipr = ip_reass_enqueue_new_datagram(fraghdr, clen); + 800fb32: 8c3b ldrh r3, [r7, #32] + 800fb34: 4619 mov r1, r3 + 800fb36: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800fb38: f7ff fdb0 bl 800f69c + 800fb3c: 6338 str r0, [r7, #48] ; 0x30 + /* Bail if unable to enqueue */ + if (ipr == NULL) { + 800fb3e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb40: 2b00 cmp r3, #0 + 800fb42: d11c bne.n 800fb7e + goto nullreturn; + 800fb44: e105 b.n 800fd52 + } + } else { + if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && + 800fb46: 6abb ldr r3, [r7, #40] ; 0x28 + 800fb48: 88db ldrh r3, [r3, #6] + 800fb4a: b29b uxth r3, r3 + 800fb4c: 4618 mov r0, r3 + 800fb4e: f7f5 fcfd bl 800554c + 800fb52: 4603 mov r3, r0 + 800fb54: f3c3 030c ubfx r3, r3, #0, #13 + 800fb58: 2b00 cmp r3, #0 + 800fb5a: d110 bne.n 800fb7e + ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) { + 800fb5c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb5e: 89db ldrh r3, [r3, #14] + 800fb60: 4618 mov r0, r3 + 800fb62: f7f5 fcf3 bl 800554c + 800fb66: 4603 mov r3, r0 + 800fb68: f3c3 030c ubfx r3, r3, #0, #13 + if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && + 800fb6c: 2b00 cmp r3, #0 + 800fb6e: d006 beq.n 800fb7e + /* ipr->iphdr is not the header from the first fragment, but fraghdr is + * -> copy fraghdr into ipr->iphdr since we want to have the header + * of the first fragment (for ICMP time exceeded and later, for copying + * all options, if supported)*/ + SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN); + 800fb70: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fb72: 3308 adds r3, #8 + 800fb74: 2214 movs r2, #20 + 800fb76: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800fb78: 4618 mov r0, r3 + 800fb7a: f001 fa06 bl 8010f8a + + /* At this point, we have either created a new entry or pointing + * to an existing one */ + + /* check for 'no more fragments', and update queue entry*/ + is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0; + 800fb7e: 6abb ldr r3, [r7, #40] ; 0x28 + 800fb80: 88db ldrh r3, [r3, #6] + 800fb82: b29b uxth r3, r3 + 800fb84: f003 0320 and.w r3, r3, #32 + 800fb88: 2b00 cmp r3, #0 + 800fb8a: bf0c ite eq + 800fb8c: 2301 moveq r3, #1 + 800fb8e: 2300 movne r3, #0 + 800fb90: b2db uxtb r3, r3 + 800fb92: 61fb str r3, [r7, #28] + if (is_last) { + 800fb94: 69fb ldr r3, [r7, #28] + 800fb96: 2b00 cmp r3, #0 + 800fb98: d00e beq.n 800fbb8 + u16_t datagram_len = (u16_t)(offset + len); + 800fb9a: 8cfa ldrh r2, [r7, #38] ; 0x26 + 800fb9c: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800fb9e: 4413 add r3, r2 + 800fba0: 837b strh r3, [r7, #26] + if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) { + 800fba2: 8b7a ldrh r2, [r7, #26] + 800fba4: 8cfb ldrh r3, [r7, #38] ; 0x26 + 800fba6: 429a cmp r2, r3 + 800fba8: f0c0 80a0 bcc.w 800fcec + 800fbac: 8b7b ldrh r3, [r7, #26] + 800fbae: f64f 72eb movw r2, #65515 ; 0xffeb + 800fbb2: 4293 cmp r3, r2 + 800fbb4: f200 809a bhi.w 800fcec + goto nullreturn_ipr; + } + } + /* find the right place to insert this pbuf */ + /* @todo: trim pbufs if fragments are overlapping */ + valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last); + 800fbb8: 69fa ldr r2, [r7, #28] + 800fbba: 6879 ldr r1, [r7, #4] + 800fbbc: 6b38 ldr r0, [r7, #48] ; 0x30 + 800fbbe: f7ff fdd5 bl 800f76c + 800fbc2: 6178 str r0, [r7, #20] + if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) { + 800fbc4: 697b ldr r3, [r7, #20] + 800fbc6: f1b3 3fff cmp.w r3, #4294967295 + 800fbca: f000 809b beq.w 800fd04 + /* if we come here, the pbuf has been enqueued */ + + /* Track the current number of pbufs current 'in-flight', in order to limit + the number of fragments that may be enqueued at any one time + (overflow checked by testing against IP_REASS_MAX_PBUFS) */ + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen); + 800fbce: 4b48 ldr r3, [pc, #288] ; (800fcf0 ) + 800fbd0: 881a ldrh r2, [r3, #0] + 800fbd2: 8c3b ldrh r3, [r7, #32] + 800fbd4: 4413 add r3, r2 + 800fbd6: b29a uxth r2, r3 + 800fbd8: 4b45 ldr r3, [pc, #276] ; (800fcf0 ) + 800fbda: 801a strh r2, [r3, #0] + if (is_last) { + 800fbdc: 69fb ldr r3, [r7, #28] + 800fbde: 2b00 cmp r3, #0 + 800fbe0: d00d beq.n 800fbfe + u16_t datagram_len = (u16_t)(offset + len); + 800fbe2: 8cfa ldrh r2, [r7, #38] ; 0x26 + 800fbe4: 8cbb ldrh r3, [r7, #36] ; 0x24 + 800fbe6: 4413 add r3, r2 + 800fbe8: 827b strh r3, [r7, #18] + ipr->datagram_len = datagram_len; + 800fbea: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fbec: 8a7a ldrh r2, [r7, #18] + 800fbee: 839a strh r2, [r3, #28] + ipr->flags |= IP_REASS_FLAG_LASTFRAG; + 800fbf0: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fbf2: 7f9b ldrb r3, [r3, #30] + 800fbf4: f043 0301 orr.w r3, r3, #1 + 800fbf8: b2da uxtb r2, r3 + 800fbfa: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fbfc: 779a strb r2, [r3, #30] + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip4_reass: last fragment seen, total len %"S16_F"\n", + ipr->datagram_len)); + } + + if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) { + 800fbfe: 697b ldr r3, [r7, #20] + 800fc00: 2b01 cmp r3, #1 + 800fc02: d171 bne.n 800fce8 + struct ip_reassdata *ipr_prev; + /* the totally last fragment (flag more fragments = 0) was received at least + * once AND all fragments are received */ + u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN); + 800fc04: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fc06: 8b9b ldrh r3, [r3, #28] + 800fc08: 3314 adds r3, #20 + 800fc0a: 823b strh r3, [r7, #16] + + /* save the second pbuf before copying the header over the pointer */ + r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf; + 800fc0c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fc0e: 685b ldr r3, [r3, #4] + 800fc10: 685b ldr r3, [r3, #4] + 800fc12: 681b ldr r3, [r3, #0] + 800fc14: 62fb str r3, [r7, #44] ; 0x2c + + /* copy the original ip header back to the first pbuf */ + fraghdr = (struct ip_hdr *)(ipr->p->payload); + 800fc16: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fc18: 685b ldr r3, [r3, #4] + 800fc1a: 685b ldr r3, [r3, #4] + 800fc1c: 62bb str r3, [r7, #40] ; 0x28 + SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN); + 800fc1e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fc20: 3308 adds r3, #8 + 800fc22: 2214 movs r2, #20 + 800fc24: 4619 mov r1, r3 + 800fc26: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800fc28: f001 f9af bl 8010f8a + IPH_LEN_SET(fraghdr, lwip_htons(datagram_len)); + 800fc2c: 8a3b ldrh r3, [r7, #16] + 800fc2e: 4618 mov r0, r3 + 800fc30: f7f5 fc8c bl 800554c + 800fc34: 4603 mov r3, r0 + 800fc36: 461a mov r2, r3 + 800fc38: 6abb ldr r3, [r7, #40] ; 0x28 + 800fc3a: 805a strh r2, [r3, #2] + IPH_OFFSET_SET(fraghdr, 0); + 800fc3c: 6abb ldr r3, [r7, #40] ; 0x28 + 800fc3e: 2200 movs r2, #0 + 800fc40: 719a strb r2, [r3, #6] + 800fc42: 2200 movs r2, #0 + 800fc44: 71da strb r2, [r3, #7] + IPH_CHKSUM_SET(fraghdr, 0); + 800fc46: 6abb ldr r3, [r7, #40] ; 0x28 + 800fc48: 2200 movs r2, #0 + 800fc4a: 729a strb r2, [r3, #10] + 800fc4c: 2200 movs r2, #0 + 800fc4e: 72da strb r2, [r3, #11] + IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) { + IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN)); + } +#endif /* CHECKSUM_GEN_IP */ + + p = ipr->p; + 800fc50: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fc52: 685b ldr r3, [r3, #4] + 800fc54: 607b str r3, [r7, #4] + + /* chain together the pbufs contained within the reass_data list. */ + while (r != NULL) { + 800fc56: e00d b.n 800fc74 + iprh = (struct ip_reass_helper *)r->payload; + 800fc58: 6afb ldr r3, [r7, #44] ; 0x2c + 800fc5a: 685b ldr r3, [r3, #4] + 800fc5c: 60fb str r3, [r7, #12] + + /* hide the ip header for every succeeding fragment */ + pbuf_remove_header(r, IP_HLEN); + 800fc5e: 2114 movs r1, #20 + 800fc60: 6af8 ldr r0, [r7, #44] ; 0x2c + 800fc62: f7f7 f931 bl 8006ec8 + pbuf_cat(p, r); + 800fc66: 6af9 ldr r1, [r7, #44] ; 0x2c + 800fc68: 6878 ldr r0, [r7, #4] + 800fc6a: f7f7 fa75 bl 8007158 + r = iprh->next_pbuf; + 800fc6e: 68fb ldr r3, [r7, #12] + 800fc70: 681b ldr r3, [r3, #0] + 800fc72: 62fb str r3, [r7, #44] ; 0x2c + while (r != NULL) { + 800fc74: 6afb ldr r3, [r7, #44] ; 0x2c + 800fc76: 2b00 cmp r3, #0 + 800fc78: d1ee bne.n 800fc58 + } + + /* find the previous entry in the linked list */ + if (ipr == reassdatagrams) { + 800fc7a: 4b1e ldr r3, [pc, #120] ; (800fcf4 ) + 800fc7c: 681b ldr r3, [r3, #0] + 800fc7e: 6b3a ldr r2, [r7, #48] ; 0x30 + 800fc80: 429a cmp r2, r3 + 800fc82: d102 bne.n 800fc8a + ipr_prev = NULL; + 800fc84: 2300 movs r3, #0 + 800fc86: 637b str r3, [r7, #52] ; 0x34 + 800fc88: e010 b.n 800fcac + } else { + for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { + 800fc8a: 4b1a ldr r3, [pc, #104] ; (800fcf4 ) + 800fc8c: 681b ldr r3, [r3, #0] + 800fc8e: 637b str r3, [r7, #52] ; 0x34 + 800fc90: e007 b.n 800fca2 + if (ipr_prev->next == ipr) { + 800fc92: 6b7b ldr r3, [r7, #52] ; 0x34 + 800fc94: 681b ldr r3, [r3, #0] + 800fc96: 6b3a ldr r2, [r7, #48] ; 0x30 + 800fc98: 429a cmp r2, r3 + 800fc9a: d006 beq.n 800fcaa + for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { + 800fc9c: 6b7b ldr r3, [r7, #52] ; 0x34 + 800fc9e: 681b ldr r3, [r3, #0] + 800fca0: 637b str r3, [r7, #52] ; 0x34 + 800fca2: 6b7b ldr r3, [r7, #52] ; 0x34 + 800fca4: 2b00 cmp r3, #0 + 800fca6: d1f4 bne.n 800fc92 + 800fca8: e000 b.n 800fcac + break; + 800fcaa: bf00 nop + } + } + } + + /* release the sources allocate for the fragment queue entry */ + ip_reass_dequeue_datagram(ipr, ipr_prev); + 800fcac: 6b79 ldr r1, [r7, #52] ; 0x34 + 800fcae: 6b38 ldr r0, [r7, #48] ; 0x30 + 800fcb0: f7ff fd2e bl 800f710 + + /* and adjust the number of pbufs currently queued for reassembly. */ + clen = pbuf_clen(p); + 800fcb4: 6878 ldr r0, [r7, #4] + 800fcb6: f7f7 fa15 bl 80070e4 + 800fcba: 4603 mov r3, r0 + 800fcbc: 843b strh r3, [r7, #32] + LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen); + 800fcbe: 4b0c ldr r3, [pc, #48] ; (800fcf0 ) + 800fcc0: 881b ldrh r3, [r3, #0] + 800fcc2: 8c3a ldrh r2, [r7, #32] + 800fcc4: 429a cmp r2, r3 + 800fcc6: d906 bls.n 800fcd6 + 800fcc8: 4b0b ldr r3, [pc, #44] ; (800fcf8 ) + 800fcca: f240 229b movw r2, #667 ; 0x29b + 800fcce: 490b ldr r1, [pc, #44] ; (800fcfc ) + 800fcd0: 480b ldr r0, [pc, #44] ; (800fd00 ) + 800fcd2: f000 ff79 bl 8010bc8 + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen); + 800fcd6: 4b06 ldr r3, [pc, #24] ; (800fcf0 ) + 800fcd8: 881a ldrh r2, [r3, #0] + 800fcda: 8c3b ldrh r3, [r7, #32] + 800fcdc: 1ad3 subs r3, r2, r3 + 800fcde: b29a uxth r2, r3 + 800fce0: 4b03 ldr r3, [pc, #12] ; (800fcf0 ) + 800fce2: 801a strh r2, [r3, #0] + + MIB2_STATS_INC(mib2.ipreasmoks); + + /* Return the pbuf chain */ + return p; + 800fce4: 687b ldr r3, [r7, #4] + 800fce6: e038 b.n 800fd5a + } + /* the datagram is not (yet?) reassembled completely */ + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount)); + return NULL; + 800fce8: 2300 movs r3, #0 + 800fcea: e036 b.n 800fd5a + goto nullreturn_ipr; + 800fcec: bf00 nop + 800fcee: e00a b.n 800fd06 + 800fcf0: 24007cc8 .word 0x24007cc8 + 800fcf4: 24007cc4 .word 0x24007cc4 + 800fcf8: 080149bc .word 0x080149bc + 800fcfc: 08014b2c .word 0x08014b2c + 800fd00: 08014a04 .word 0x08014a04 + goto nullreturn_ipr; + 800fd04: bf00 nop + +nullreturn_ipr: + LWIP_ASSERT("ipr != NULL", ipr != NULL); + 800fd06: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fd08: 2b00 cmp r3, #0 + 800fd0a: d106 bne.n 800fd1a + 800fd0c: 4b15 ldr r3, [pc, #84] ; (800fd64 ) + 800fd0e: f44f 722a mov.w r2, #680 ; 0x2a8 + 800fd12: 4915 ldr r1, [pc, #84] ; (800fd68 ) + 800fd14: 4815 ldr r0, [pc, #84] ; (800fd6c ) + 800fd16: f000 ff57 bl 8010bc8 + if (ipr->p == NULL) { + 800fd1a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fd1c: 685b ldr r3, [r3, #4] + 800fd1e: 2b00 cmp r3, #0 + 800fd20: d116 bne.n 800fd50 + /* dropped pbuf after creating a new datagram entry: remove the entry, too */ + LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams); + 800fd22: 4b13 ldr r3, [pc, #76] ; (800fd70 ) + 800fd24: 681b ldr r3, [r3, #0] + 800fd26: 6b3a ldr r2, [r7, #48] ; 0x30 + 800fd28: 429a cmp r2, r3 + 800fd2a: d006 beq.n 800fd3a + 800fd2c: 4b0d ldr r3, [pc, #52] ; (800fd64 ) + 800fd2e: f240 22ab movw r2, #683 ; 0x2ab + 800fd32: 4910 ldr r1, [pc, #64] ; (800fd74 ) + 800fd34: 480d ldr r0, [pc, #52] ; (800fd6c ) + 800fd36: f000 ff47 bl 8010bc8 + ip_reass_dequeue_datagram(ipr, NULL); + 800fd3a: 2100 movs r1, #0 + 800fd3c: 6b38 ldr r0, [r7, #48] ; 0x30 + 800fd3e: f7ff fce7 bl 800f710 + 800fd42: e006 b.n 800fd52 + goto nullreturn; + 800fd44: bf00 nop + 800fd46: e004 b.n 800fd52 + goto nullreturn; + 800fd48: bf00 nop + 800fd4a: e002 b.n 800fd52 + goto nullreturn; + 800fd4c: bf00 nop + 800fd4e: e000 b.n 800fd52 + } + +nullreturn: + 800fd50: bf00 nop + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n")); + IPFRAG_STATS_INC(ip_frag.drop); + pbuf_free(p); + 800fd52: 6878 ldr r0, [r7, #4] + 800fd54: f7f7 f93e bl 8006fd4 + return NULL; + 800fd58: 2300 movs r3, #0 +} + 800fd5a: 4618 mov r0, r3 + 800fd5c: 3738 adds r7, #56 ; 0x38 + 800fd5e: 46bd mov sp, r7 + 800fd60: bd80 pop {r7, pc} + 800fd62: bf00 nop + 800fd64: 080149bc .word 0x080149bc + 800fd68: 08014b48 .word 0x08014b48 + 800fd6c: 08014a04 .word 0x08014a04 + 800fd70: 24007cc4 .word 0x24007cc4 + 800fd74: 08014b54 .word 0x08014b54 + +0800fd78 : +#if IP_FRAG +#if !LWIP_NETIF_TX_SINGLE_PBUF +/** Allocate a new struct pbuf_custom_ref */ +static struct pbuf_custom_ref * +ip_frag_alloc_pbuf_custom_ref(void) +{ + 800fd78: b580 push {r7, lr} + 800fd7a: af00 add r7, sp, #0 + return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF); + 800fd7c: 2005 movs r0, #5 + 800fd7e: f7f6 f94d bl 800601c + 800fd82: 4603 mov r3, r0 +} + 800fd84: 4618 mov r0, r3 + 800fd86: bd80 pop {r7, pc} + +0800fd88 : + +/** Free a struct pbuf_custom_ref */ +static void +ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p) +{ + 800fd88: b580 push {r7, lr} + 800fd8a: b082 sub sp, #8 + 800fd8c: af00 add r7, sp, #0 + 800fd8e: 6078 str r0, [r7, #4] + LWIP_ASSERT("p != NULL", p != NULL); + 800fd90: 687b ldr r3, [r7, #4] + 800fd92: 2b00 cmp r3, #0 + 800fd94: d106 bne.n 800fda4 + 800fd96: 4b07 ldr r3, [pc, #28] ; (800fdb4 ) + 800fd98: f44f 7231 mov.w r2, #708 ; 0x2c4 + 800fd9c: 4906 ldr r1, [pc, #24] ; (800fdb8 ) + 800fd9e: 4807 ldr r0, [pc, #28] ; (800fdbc ) + 800fda0: f000 ff12 bl 8010bc8 + memp_free(MEMP_FRAG_PBUF, p); + 800fda4: 6879 ldr r1, [r7, #4] + 800fda6: 2005 movs r0, #5 + 800fda8: f7f6 f9a8 bl 80060fc +} + 800fdac: bf00 nop + 800fdae: 3708 adds r7, #8 + 800fdb0: 46bd mov sp, r7 + 800fdb2: bd80 pop {r7, pc} + 800fdb4: 080149bc .word 0x080149bc + 800fdb8: 08014b74 .word 0x08014b74 + 800fdbc: 08014a04 .word 0x08014a04 + +0800fdc0 : + +/** Free-callback function to free a 'struct pbuf_custom_ref', called by + * pbuf_free. */ +static void +ipfrag_free_pbuf_custom(struct pbuf *p) +{ + 800fdc0: b580 push {r7, lr} + 800fdc2: b084 sub sp, #16 + 800fdc4: af00 add r7, sp, #0 + 800fdc6: 6078 str r0, [r7, #4] + struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p; + 800fdc8: 687b ldr r3, [r7, #4] + 800fdca: 60fb str r3, [r7, #12] + LWIP_ASSERT("pcr != NULL", pcr != NULL); + 800fdcc: 68fb ldr r3, [r7, #12] + 800fdce: 2b00 cmp r3, #0 + 800fdd0: d106 bne.n 800fde0 + 800fdd2: 4b11 ldr r3, [pc, #68] ; (800fe18 ) + 800fdd4: f240 22ce movw r2, #718 ; 0x2ce + 800fdd8: 4910 ldr r1, [pc, #64] ; (800fe1c ) + 800fdda: 4811 ldr r0, [pc, #68] ; (800fe20 ) + 800fddc: f000 fef4 bl 8010bc8 + LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p); + 800fde0: 68fa ldr r2, [r7, #12] + 800fde2: 687b ldr r3, [r7, #4] + 800fde4: 429a cmp r2, r3 + 800fde6: d006 beq.n 800fdf6 + 800fde8: 4b0b ldr r3, [pc, #44] ; (800fe18 ) + 800fdea: f240 22cf movw r2, #719 ; 0x2cf + 800fdee: 490d ldr r1, [pc, #52] ; (800fe24 ) + 800fdf0: 480b ldr r0, [pc, #44] ; (800fe20 ) + 800fdf2: f000 fee9 bl 8010bc8 + if (pcr->original != NULL) { + 800fdf6: 68fb ldr r3, [r7, #12] + 800fdf8: 695b ldr r3, [r3, #20] + 800fdfa: 2b00 cmp r3, #0 + 800fdfc: d004 beq.n 800fe08 + pbuf_free(pcr->original); + 800fdfe: 68fb ldr r3, [r7, #12] + 800fe00: 695b ldr r3, [r3, #20] + 800fe02: 4618 mov r0, r3 + 800fe04: f7f7 f8e6 bl 8006fd4 + } + ip_frag_free_pbuf_custom_ref(pcr); + 800fe08: 68f8 ldr r0, [r7, #12] + 800fe0a: f7ff ffbd bl 800fd88 +} + 800fe0e: bf00 nop + 800fe10: 3710 adds r7, #16 + 800fe12: 46bd mov sp, r7 + 800fe14: bd80 pop {r7, pc} + 800fe16: bf00 nop + 800fe18: 080149bc .word 0x080149bc + 800fe1c: 08014b80 .word 0x08014b80 + 800fe20: 08014a04 .word 0x08014a04 + 800fe24: 08014b8c .word 0x08014b8c + +0800fe28 : + * + * @return ERR_OK if sent successfully, err_t otherwise + */ +err_t +ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest) +{ + 800fe28: b580 push {r7, lr} + 800fe2a: b094 sub sp, #80 ; 0x50 + 800fe2c: af02 add r7, sp, #8 + 800fe2e: 60f8 str r0, [r7, #12] + 800fe30: 60b9 str r1, [r7, #8] + 800fe32: 607a str r2, [r7, #4] + struct pbuf *rambuf; +#if !LWIP_NETIF_TX_SINGLE_PBUF + struct pbuf *newpbuf; + u16_t newpbuflen = 0; + 800fe34: 2300 movs r3, #0 + 800fe36: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 + u16_t left_to_copy; +#endif + struct ip_hdr *original_iphdr; + struct ip_hdr *iphdr; + const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8); + 800fe3a: 68bb ldr r3, [r7, #8] + 800fe3c: 8c9b ldrh r3, [r3, #36] ; 0x24 + 800fe3e: 3b14 subs r3, #20 + 800fe40: 2b00 cmp r3, #0 + 800fe42: da00 bge.n 800fe46 + 800fe44: 3307 adds r3, #7 + 800fe46: 10db asrs r3, r3, #3 + 800fe48: 877b strh r3, [r7, #58] ; 0x3a + u16_t left, fragsize; + u16_t ofo; + int last; + u16_t poff = IP_HLEN; + 800fe4a: 2314 movs r3, #20 + 800fe4c: 87fb strh r3, [r7, #62] ; 0x3e + u16_t tmp; + int mf_set; + + original_iphdr = (struct ip_hdr *)p->payload; + 800fe4e: 68fb ldr r3, [r7, #12] + 800fe50: 685b ldr r3, [r3, #4] + 800fe52: 637b str r3, [r7, #52] ; 0x34 + iphdr = original_iphdr; + 800fe54: 6b7b ldr r3, [r7, #52] ; 0x34 + 800fe56: 633b str r3, [r7, #48] ; 0x30 + if (IPH_HL_BYTES(iphdr) != IP_HLEN) { + 800fe58: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fe5a: 781b ldrb r3, [r3, #0] + 800fe5c: f003 030f and.w r3, r3, #15 + 800fe60: b2db uxtb r3, r3 + 800fe62: 009b lsls r3, r3, #2 + 800fe64: b2db uxtb r3, r3 + 800fe66: 2b14 cmp r3, #20 + 800fe68: d002 beq.n 800fe70 + /* ip4_frag() does not support IP options */ + return ERR_VAL; + 800fe6a: f06f 0305 mvn.w r3, #5 + 800fe6e: e110 b.n 8010092 + } + LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL); + 800fe70: 68fb ldr r3, [r7, #12] + 800fe72: 895b ldrh r3, [r3, #10] + 800fe74: 2b13 cmp r3, #19 + 800fe76: d809 bhi.n 800fe8c + 800fe78: 4b88 ldr r3, [pc, #544] ; (801009c ) + 800fe7a: f44f 723f mov.w r2, #764 ; 0x2fc + 800fe7e: 4988 ldr r1, [pc, #544] ; (80100a0 ) + 800fe80: 4888 ldr r0, [pc, #544] ; (80100a4 ) + 800fe82: f000 fea1 bl 8010bc8 + 800fe86: f06f 0305 mvn.w r3, #5 + 800fe8a: e102 b.n 8010092 + + /* Save original offset */ + tmp = lwip_ntohs(IPH_OFFSET(iphdr)); + 800fe8c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800fe8e: 88db ldrh r3, [r3, #6] + 800fe90: b29b uxth r3, r3 + 800fe92: 4618 mov r0, r3 + 800fe94: f7f5 fb5a bl 800554c + 800fe98: 4603 mov r3, r0 + 800fe9a: 87bb strh r3, [r7, #60] ; 0x3c + ofo = tmp & IP_OFFMASK; + 800fe9c: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800fe9e: f3c3 030c ubfx r3, r3, #0, #13 + 800fea2: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 + /* already fragmented? if so, the last fragment we create must have MF, too */ + mf_set = tmp & IP_MF; + 800fea6: 8fbb ldrh r3, [r7, #60] ; 0x3c + 800fea8: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 800feac: 62fb str r3, [r7, #44] ; 0x2c + + left = (u16_t)(p->tot_len - IP_HLEN); + 800feae: 68fb ldr r3, [r7, #12] + 800feb0: 891b ldrh r3, [r3, #8] + 800feb2: 3b14 subs r3, #20 + 800feb4: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + + while (left) { + 800feb8: e0e1 b.n 801007e + /* Fill this fragment */ + fragsize = LWIP_MIN(left, (u16_t)(nfb * 8)); + 800feba: 8f7b ldrh r3, [r7, #58] ; 0x3a + 800febc: 00db lsls r3, r3, #3 + 800febe: b29b uxth r3, r3 + 800fec0: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 800fec4: 4293 cmp r3, r2 + 800fec6: bf28 it cs + 800fec8: 4613 movcs r3, r2 + 800feca: 857b strh r3, [r7, #42] ; 0x2a + /* When not using a static buffer, create a chain of pbufs. + * The first will be a PBUF_RAM holding the link and IP header. + * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, + * but limited to the size of an mtu. + */ + rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM); + 800fecc: f44f 7220 mov.w r2, #640 ; 0x280 + 800fed0: 2114 movs r1, #20 + 800fed2: 200e movs r0, #14 + 800fed4: f7f6 fd9a bl 8006a0c + 800fed8: 6278 str r0, [r7, #36] ; 0x24 + if (rambuf == NULL) { + 800feda: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fedc: 2b00 cmp r3, #0 + 800fede: f000 80d5 beq.w 801008c + goto memerr; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + 800fee2: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fee4: 895b ldrh r3, [r3, #10] + 800fee6: 2b13 cmp r3, #19 + 800fee8: d806 bhi.n 800fef8 + 800feea: 4b6c ldr r3, [pc, #432] ; (801009c ) + 800feec: f44f 7249 mov.w r2, #804 ; 0x324 + 800fef0: 496d ldr r1, [pc, #436] ; (80100a8 ) + 800fef2: 486c ldr r0, [pc, #432] ; (80100a4 ) + 800fef4: f000 fe68 bl 8010bc8 + (rambuf->len >= (IP_HLEN))); + SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); + 800fef8: 6a7b ldr r3, [r7, #36] ; 0x24 + 800fefa: 685b ldr r3, [r3, #4] + 800fefc: 2214 movs r2, #20 + 800fefe: 6b79 ldr r1, [r7, #52] ; 0x34 + 800ff00: 4618 mov r0, r3 + 800ff02: f001 f842 bl 8010f8a + iphdr = (struct ip_hdr *)rambuf->payload; + 800ff06: 6a7b ldr r3, [r7, #36] ; 0x24 + 800ff08: 685b ldr r3, [r3, #4] + 800ff0a: 633b str r3, [r7, #48] ; 0x30 + + left_to_copy = fragsize; + 800ff0c: 8d7b ldrh r3, [r7, #42] ; 0x2a + 800ff0e: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 + while (left_to_copy) { + 800ff12: e064 b.n 800ffde + struct pbuf_custom_ref *pcr; + u16_t plen = (u16_t)(p->len - poff); + 800ff14: 68fb ldr r3, [r7, #12] + 800ff16: 895a ldrh r2, [r3, #10] + 800ff18: 8ffb ldrh r3, [r7, #62] ; 0x3e + 800ff1a: 1ad3 subs r3, r2, r3 + 800ff1c: 83fb strh r3, [r7, #30] + LWIP_ASSERT("p->len >= poff", p->len >= poff); + 800ff1e: 68fb ldr r3, [r7, #12] + 800ff20: 895b ldrh r3, [r3, #10] + 800ff22: 8ffa ldrh r2, [r7, #62] ; 0x3e + 800ff24: 429a cmp r2, r3 + 800ff26: d906 bls.n 800ff36 + 800ff28: 4b5c ldr r3, [pc, #368] ; (801009c ) + 800ff2a: f240 322d movw r2, #813 ; 0x32d + 800ff2e: 495f ldr r1, [pc, #380] ; (80100ac ) + 800ff30: 485c ldr r0, [pc, #368] ; (80100a4 ) + 800ff32: f000 fe49 bl 8010bc8 + newpbuflen = LWIP_MIN(left_to_copy, plen); + 800ff36: 8bfa ldrh r2, [r7, #30] + 800ff38: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 800ff3c: 4293 cmp r3, r2 + 800ff3e: bf28 it cs + 800ff40: 4613 movcs r3, r2 + 800ff42: f8a7 3046 strh.w r3, [r7, #70] ; 0x46 + /* Is this pbuf already empty? */ + if (!newpbuflen) { + 800ff46: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800ff4a: 2b00 cmp r3, #0 + 800ff4c: d105 bne.n 800ff5a + poff = 0; + 800ff4e: 2300 movs r3, #0 + 800ff50: 87fb strh r3, [r7, #62] ; 0x3e + p = p->next; + 800ff52: 68fb ldr r3, [r7, #12] + 800ff54: 681b ldr r3, [r3, #0] + 800ff56: 60fb str r3, [r7, #12] + continue; + 800ff58: e041 b.n 800ffde + } + pcr = ip_frag_alloc_pbuf_custom_ref(); + 800ff5a: f7ff ff0d bl 800fd78 + 800ff5e: 61b8 str r0, [r7, #24] + if (pcr == NULL) { + 800ff60: 69bb ldr r3, [r7, #24] + 800ff62: 2b00 cmp r3, #0 + 800ff64: d103 bne.n 800ff6e + pbuf_free(rambuf); + 800ff66: 6a78 ldr r0, [r7, #36] ; 0x24 + 800ff68: f7f7 f834 bl 8006fd4 + goto memerr; + 800ff6c: e08f b.n 801008e + } + /* Mirror this pbuf, although we might not need all of it. */ + newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, + 800ff6e: 69b8 ldr r0, [r7, #24] + (u8_t *)p->payload + poff, newpbuflen); + 800ff70: 68fb ldr r3, [r7, #12] + 800ff72: 685a ldr r2, [r3, #4] + newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, + 800ff74: 8ffb ldrh r3, [r7, #62] ; 0x3e + 800ff76: 4413 add r3, r2 + 800ff78: f8b7 1046 ldrh.w r1, [r7, #70] ; 0x46 + 800ff7c: f8b7 2046 ldrh.w r2, [r7, #70] ; 0x46 + 800ff80: 9201 str r2, [sp, #4] + 800ff82: 9300 str r3, [sp, #0] + 800ff84: 4603 mov r3, r0 + 800ff86: 2241 movs r2, #65 ; 0x41 + 800ff88: 2000 movs r0, #0 + 800ff8a: f7f6 fe69 bl 8006c60 + 800ff8e: 6178 str r0, [r7, #20] + if (newpbuf == NULL) { + 800ff90: 697b ldr r3, [r7, #20] + 800ff92: 2b00 cmp r3, #0 + 800ff94: d106 bne.n 800ffa4 + ip_frag_free_pbuf_custom_ref(pcr); + 800ff96: 69b8 ldr r0, [r7, #24] + 800ff98: f7ff fef6 bl 800fd88 + pbuf_free(rambuf); + 800ff9c: 6a78 ldr r0, [r7, #36] ; 0x24 + 800ff9e: f7f7 f819 bl 8006fd4 + goto memerr; + 800ffa2: e074 b.n 801008e + } + pbuf_ref(p); + 800ffa4: 68f8 ldr r0, [r7, #12] + 800ffa6: f7f7 f8b5 bl 8007114 + pcr->original = p; + 800ffaa: 69bb ldr r3, [r7, #24] + 800ffac: 68fa ldr r2, [r7, #12] + 800ffae: 615a str r2, [r3, #20] + pcr->pc.custom_free_function = ipfrag_free_pbuf_custom; + 800ffb0: 69bb ldr r3, [r7, #24] + 800ffb2: 4a3f ldr r2, [pc, #252] ; (80100b0 ) + 800ffb4: 611a str r2, [r3, #16] + + /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain + * so that it is removed when pbuf_dechain is later called on rambuf. + */ + pbuf_cat(rambuf, newpbuf); + 800ffb6: 6979 ldr r1, [r7, #20] + 800ffb8: 6a78 ldr r0, [r7, #36] ; 0x24 + 800ffba: f7f7 f8cd bl 8007158 + left_to_copy = (u16_t)(left_to_copy - newpbuflen); + 800ffbe: f8b7 2044 ldrh.w r2, [r7, #68] ; 0x44 + 800ffc2: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800ffc6: 1ad3 subs r3, r2, r3 + 800ffc8: f8a7 3044 strh.w r3, [r7, #68] ; 0x44 + if (left_to_copy) { + 800ffcc: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 800ffd0: 2b00 cmp r3, #0 + 800ffd2: d004 beq.n 800ffde + poff = 0; + 800ffd4: 2300 movs r3, #0 + 800ffd6: 87fb strh r3, [r7, #62] ; 0x3e + p = p->next; + 800ffd8: 68fb ldr r3, [r7, #12] + 800ffda: 681b ldr r3, [r3, #0] + 800ffdc: 60fb str r3, [r7, #12] + while (left_to_copy) { + 800ffde: f8b7 3044 ldrh.w r3, [r7, #68] ; 0x44 + 800ffe2: 2b00 cmp r3, #0 + 800ffe4: d196 bne.n 800ff14 + } + } + poff = (u16_t)(poff + newpbuflen); + 800ffe6: 8ffa ldrh r2, [r7, #62] ; 0x3e + 800ffe8: f8b7 3046 ldrh.w r3, [r7, #70] ; 0x46 + 800ffec: 4413 add r3, r2 + 800ffee: 87fb strh r3, [r7, #62] ; 0x3e +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + /* Correct header */ + last = (left <= netif->mtu - IP_HLEN); + 800fff0: 68bb ldr r3, [r7, #8] + 800fff2: 8c9b ldrh r3, [r3, #36] ; 0x24 + 800fff4: f1a3 0213 sub.w r2, r3, #19 + 800fff8: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 800fffc: 429a cmp r2, r3 + 800fffe: bfcc ite gt + 8010000: 2301 movgt r3, #1 + 8010002: 2300 movle r3, #0 + 8010004: b2db uxtb r3, r3 + 8010006: 623b str r3, [r7, #32] + + /* Set new offset and MF flag */ + tmp = (IP_OFFMASK & (ofo)); + 8010008: f8b7 3040 ldrh.w r3, [r7, #64] ; 0x40 + 801000c: f3c3 030c ubfx r3, r3, #0, #13 + 8010010: 87bb strh r3, [r7, #60] ; 0x3c + if (!last || mf_set) { + 8010012: 6a3b ldr r3, [r7, #32] + 8010014: 2b00 cmp r3, #0 + 8010016: d002 beq.n 801001e + 8010018: 6afb ldr r3, [r7, #44] ; 0x2c + 801001a: 2b00 cmp r3, #0 + 801001c: d003 beq.n 8010026 + /* the last fragment has MF set if the input frame had it */ + tmp = tmp | IP_MF; + 801001e: 8fbb ldrh r3, [r7, #60] ; 0x3c + 8010020: f443 5300 orr.w r3, r3, #8192 ; 0x2000 + 8010024: 87bb strh r3, [r7, #60] ; 0x3c + } + IPH_OFFSET_SET(iphdr, lwip_htons(tmp)); + 8010026: 8fbb ldrh r3, [r7, #60] ; 0x3c + 8010028: 4618 mov r0, r3 + 801002a: f7f5 fa8f bl 800554c + 801002e: 4603 mov r3, r0 + 8010030: 461a mov r2, r3 + 8010032: 6b3b ldr r3, [r7, #48] ; 0x30 + 8010034: 80da strh r2, [r3, #6] + IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN))); + 8010036: 8d7b ldrh r3, [r7, #42] ; 0x2a + 8010038: 3314 adds r3, #20 + 801003a: b29b uxth r3, r3 + 801003c: 4618 mov r0, r3 + 801003e: f7f5 fa85 bl 800554c + 8010042: 4603 mov r3, r0 + 8010044: 461a mov r2, r3 + 8010046: 6b3b ldr r3, [r7, #48] ; 0x30 + 8010048: 805a strh r2, [r3, #2] + IPH_CHKSUM_SET(iphdr, 0); + 801004a: 6b3b ldr r3, [r7, #48] ; 0x30 + 801004c: 2200 movs r2, #0 + 801004e: 729a strb r2, [r3, #10] + 8010050: 2200 movs r2, #0 + 8010052: 72da strb r2, [r3, #11] +#endif /* CHECKSUM_GEN_IP */ + + /* No need for separate header pbuf - we allowed room for it in rambuf + * when allocated. + */ + netif->output(netif, rambuf, dest); + 8010054: 68bb ldr r3, [r7, #8] + 8010056: 695b ldr r3, [r3, #20] + 8010058: 687a ldr r2, [r7, #4] + 801005a: 6a79 ldr r1, [r7, #36] ; 0x24 + 801005c: 68b8 ldr r0, [r7, #8] + 801005e: 4798 blx r3 + * recreate it next time round the loop. If we're lucky the hardware + * will have already sent the packet, the free will really free, and + * there will be zero memory penalty. + */ + + pbuf_free(rambuf); + 8010060: 6a78 ldr r0, [r7, #36] ; 0x24 + 8010062: f7f6 ffb7 bl 8006fd4 + left = (u16_t)(left - fragsize); + 8010066: f8b7 2042 ldrh.w r2, [r7, #66] ; 0x42 + 801006a: 8d7b ldrh r3, [r7, #42] ; 0x2a + 801006c: 1ad3 subs r3, r2, r3 + 801006e: f8a7 3042 strh.w r3, [r7, #66] ; 0x42 + ofo = (u16_t)(ofo + nfb); + 8010072: f8b7 2040 ldrh.w r2, [r7, #64] ; 0x40 + 8010076: 8f7b ldrh r3, [r7, #58] ; 0x3a + 8010078: 4413 add r3, r2 + 801007a: f8a7 3040 strh.w r3, [r7, #64] ; 0x40 + while (left) { + 801007e: f8b7 3042 ldrh.w r3, [r7, #66] ; 0x42 + 8010082: 2b00 cmp r3, #0 + 8010084: f47f af19 bne.w 800feba + } + MIB2_STATS_INC(mib2.ipfragoks); + return ERR_OK; + 8010088: 2300 movs r3, #0 + 801008a: e002 b.n 8010092 + goto memerr; + 801008c: bf00 nop +memerr: + MIB2_STATS_INC(mib2.ipfragfails); + return ERR_MEM; + 801008e: f04f 33ff mov.w r3, #4294967295 +} + 8010092: 4618 mov r0, r3 + 8010094: 3748 adds r7, #72 ; 0x48 + 8010096: 46bd mov sp, r7 + 8010098: bd80 pop {r7, pc} + 801009a: bf00 nop + 801009c: 080149bc .word 0x080149bc + 80100a0: 08014b98 .word 0x08014b98 + 80100a4: 08014a04 .word 0x08014a04 + 80100a8: 08014bb4 .word 0x08014bb4 + 80100ac: 08014bd4 .word 0x08014bd4 + 80100b0: 0800fdc1 .word 0x0800fdc1 + +080100b4 : + * @see ETHARP_SUPPORT_VLAN + * @see LWIP_HOOK_VLAN_CHECK + */ +err_t +ethernet_input(struct pbuf *p, struct netif *netif) +{ + 80100b4: b580 push {r7, lr} + 80100b6: b086 sub sp, #24 + 80100b8: af00 add r7, sp, #0 + 80100ba: 6078 str r0, [r7, #4] + 80100bc: 6039 str r1, [r7, #0] + struct eth_hdr *ethhdr; + u16_t type; +#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6 + u16_t next_hdr_offset = SIZEOF_ETH_HDR; + 80100be: 230e movs r3, #14 + 80100c0: 82fb strh r3, [r7, #22] +#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */ + + LWIP_ASSERT_CORE_LOCKED(); + + if (p->len <= SIZEOF_ETH_HDR) { + 80100c2: 687b ldr r3, [r7, #4] + 80100c4: 895b ldrh r3, [r3, #10] + 80100c6: 2b0e cmp r3, #14 + 80100c8: d96e bls.n 80101a8 + ETHARP_STATS_INC(etharp.drop); + MIB2_STATS_NETIF_INC(netif, ifinerrors); + goto free_and_return; + } + + if (p->if_idx == NETIF_NO_INDEX) { + 80100ca: 687b ldr r3, [r7, #4] + 80100cc: 7bdb ldrb r3, [r3, #15] + 80100ce: 2b00 cmp r3, #0 + 80100d0: d106 bne.n 80100e0 + p->if_idx = netif_get_index(netif); + 80100d2: 683b ldr r3, [r7, #0] + 80100d4: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 80100d8: 3301 adds r3, #1 + 80100da: b2da uxtb r2, r3 + 80100dc: 687b ldr r3, [r7, #4] + 80100de: 73da strb r2, [r3, #15] + } + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = (struct eth_hdr *)p->payload; + 80100e0: 687b ldr r3, [r7, #4] + 80100e2: 685b ldr r3, [r3, #4] + 80100e4: 613b str r3, [r7, #16] + (unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5], + (unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2], + (unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5], + lwip_htons(ethhdr->type))); + + type = ethhdr->type; + 80100e6: 693b ldr r3, [r7, #16] + 80100e8: 7b1a ldrb r2, [r3, #12] + 80100ea: 7b5b ldrb r3, [r3, #13] + 80100ec: 021b lsls r3, r3, #8 + 80100ee: 4313 orrs r3, r2 + 80100f0: 81fb strh r3, [r7, #14] + +#if LWIP_ARP_FILTER_NETIF + netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type)); +#endif /* LWIP_ARP_FILTER_NETIF*/ + + if (ethhdr->dest.addr[0] & 1) { + 80100f2: 693b ldr r3, [r7, #16] + 80100f4: 781b ldrb r3, [r3, #0] + 80100f6: f003 0301 and.w r3, r3, #1 + 80100fa: 2b00 cmp r3, #0 + 80100fc: d023 beq.n 8010146 + /* this might be a multicast or broadcast packet */ + if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) { + 80100fe: 693b ldr r3, [r7, #16] + 8010100: 781b ldrb r3, [r3, #0] + 8010102: 2b01 cmp r3, #1 + 8010104: d10f bne.n 8010126 +#if LWIP_IPV4 + if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && + 8010106: 693b ldr r3, [r7, #16] + 8010108: 785b ldrb r3, [r3, #1] + 801010a: 2b00 cmp r3, #0 + 801010c: d11b bne.n 8010146 + (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) { + 801010e: 693b ldr r3, [r7, #16] + 8010110: 789b ldrb r3, [r3, #2] + if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && + 8010112: 2b5e cmp r3, #94 ; 0x5e + 8010114: d117 bne.n 8010146 + /* mark the pbuf as link-layer multicast */ + p->flags |= PBUF_FLAG_LLMCAST; + 8010116: 687b ldr r3, [r7, #4] + 8010118: 7b5b ldrb r3, [r3, #13] + 801011a: f043 0310 orr.w r3, r3, #16 + 801011e: b2da uxtb r2, r3 + 8010120: 687b ldr r3, [r7, #4] + 8010122: 735a strb r2, [r3, #13] + 8010124: e00f b.n 8010146 + (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) { + /* mark the pbuf as link-layer multicast */ + p->flags |= PBUF_FLAG_LLMCAST; + } +#endif /* LWIP_IPV6 */ + else if (eth_addr_cmp(ðhdr->dest, ðbroadcast)) { + 8010126: 693b ldr r3, [r7, #16] + 8010128: 2206 movs r2, #6 + 801012a: 4928 ldr r1, [pc, #160] ; (80101cc ) + 801012c: 4618 mov r0, r3 + 801012e: f000 fe99 bl 8010e64 + 8010132: 4603 mov r3, r0 + 8010134: 2b00 cmp r3, #0 + 8010136: d106 bne.n 8010146 + /* mark the pbuf as link-layer broadcast */ + p->flags |= PBUF_FLAG_LLBCAST; + 8010138: 687b ldr r3, [r7, #4] + 801013a: 7b5b ldrb r3, [r3, #13] + 801013c: f043 0308 orr.w r3, r3, #8 + 8010140: b2da uxtb r2, r3 + 8010142: 687b ldr r3, [r7, #4] + 8010144: 735a strb r2, [r3, #13] + } + } + + switch (type) { + 8010146: 89fb ldrh r3, [r7, #14] + 8010148: 2b08 cmp r3, #8 + 801014a: d003 beq.n 8010154 + 801014c: f5b3 6fc1 cmp.w r3, #1544 ; 0x608 + 8010150: d014 beq.n 801017c + } +#endif + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + MIB2_STATS_NETIF_INC(netif, ifinunknownprotos); + goto free_and_return; + 8010152: e032 b.n 80101ba + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + 8010154: 683b ldr r3, [r7, #0] + 8010156: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 801015a: f003 0308 and.w r3, r3, #8 + 801015e: 2b00 cmp r3, #0 + 8010160: d024 beq.n 80101ac + if (pbuf_remove_header(p, next_hdr_offset)) { + 8010162: 8afb ldrh r3, [r7, #22] + 8010164: 4619 mov r1, r3 + 8010166: 6878 ldr r0, [r7, #4] + 8010168: f7f6 feae bl 8006ec8 + 801016c: 4603 mov r3, r0 + 801016e: 2b00 cmp r3, #0 + 8010170: d11e bne.n 80101b0 + ip4_input(p, netif); + 8010172: 6839 ldr r1, [r7, #0] + 8010174: 6878 ldr r0, [r7, #4] + 8010176: f7fe ff21 bl 800efbc + break; + 801017a: e013 b.n 80101a4 + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + 801017c: 683b ldr r3, [r7, #0] + 801017e: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8010182: f003 0308 and.w r3, r3, #8 + 8010186: 2b00 cmp r3, #0 + 8010188: d014 beq.n 80101b4 + if (pbuf_remove_header(p, next_hdr_offset)) { + 801018a: 8afb ldrh r3, [r7, #22] + 801018c: 4619 mov r1, r3 + 801018e: 6878 ldr r0, [r7, #4] + 8010190: f7f6 fe9a bl 8006ec8 + 8010194: 4603 mov r3, r0 + 8010196: 2b00 cmp r3, #0 + 8010198: d10e bne.n 80101b8 + etharp_input(p, netif); + 801019a: 6839 ldr r1, [r7, #0] + 801019c: 6878 ldr r0, [r7, #4] + 801019e: f7fe f805 bl 800e1ac + break; + 80101a2: bf00 nop + } + + /* This means the pbuf is freed or consumed, + so the caller doesn't have to free it again */ + return ERR_OK; + 80101a4: 2300 movs r3, #0 + 80101a6: e00c b.n 80101c2 + goto free_and_return; + 80101a8: bf00 nop + 80101aa: e006 b.n 80101ba + goto free_and_return; + 80101ac: bf00 nop + 80101ae: e004 b.n 80101ba + goto free_and_return; + 80101b0: bf00 nop + 80101b2: e002 b.n 80101ba + goto free_and_return; + 80101b4: bf00 nop + 80101b6: e000 b.n 80101ba + goto free_and_return; + 80101b8: bf00 nop + +free_and_return: + pbuf_free(p); + 80101ba: 6878 ldr r0, [r7, #4] + 80101bc: f7f6 ff0a bl 8006fd4 + return ERR_OK; + 80101c0: 2300 movs r3, #0 +} + 80101c2: 4618 mov r0, r3 + 80101c4: 3718 adds r7, #24 + 80101c6: 46bd mov sp, r7 + 80101c8: bd80 pop {r7, pc} + 80101ca: bf00 nop + 80101cc: 08014d98 .word 0x08014d98 + +080101d0 : + * @return ERR_OK if the packet was sent, any other err_t on failure + */ +err_t +ethernet_output(struct netif * netif, struct pbuf * p, + const struct eth_addr * src, const struct eth_addr * dst, + u16_t eth_type) { + 80101d0: b580 push {r7, lr} + 80101d2: b086 sub sp, #24 + 80101d4: af00 add r7, sp, #0 + 80101d6: 60f8 str r0, [r7, #12] + 80101d8: 60b9 str r1, [r7, #8] + 80101da: 607a str r2, [r7, #4] + 80101dc: 603b str r3, [r7, #0] + struct eth_hdr *ethhdr; + u16_t eth_type_be = lwip_htons(eth_type); + 80101de: 8c3b ldrh r3, [r7, #32] + 80101e0: 4618 mov r0, r3 + 80101e2: f7f5 f9b3 bl 800554c + 80101e6: 4603 mov r3, r0 + 80101e8: 82fb strh r3, [r7, #22] + + eth_type_be = PP_HTONS(ETHTYPE_VLAN); + } else +#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */ + { + if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) { + 80101ea: 210e movs r1, #14 + 80101ec: 68b8 ldr r0, [r7, #8] + 80101ee: f7f6 fe5b bl 8006ea8 + 80101f2: 4603 mov r3, r0 + 80101f4: 2b00 cmp r3, #0 + 80101f6: d125 bne.n 8010244 + } + } + + LWIP_ASSERT_CORE_LOCKED(); + + ethhdr = (struct eth_hdr *)p->payload; + 80101f8: 68bb ldr r3, [r7, #8] + 80101fa: 685b ldr r3, [r3, #4] + 80101fc: 613b str r3, [r7, #16] + ethhdr->type = eth_type_be; + 80101fe: 693b ldr r3, [r7, #16] + 8010200: 8afa ldrh r2, [r7, #22] + 8010202: 819a strh r2, [r3, #12] + SMEMCPY(ðhdr->dest, dst, ETH_HWADDR_LEN); + 8010204: 693b ldr r3, [r7, #16] + 8010206: 2206 movs r2, #6 + 8010208: 6839 ldr r1, [r7, #0] + 801020a: 4618 mov r0, r3 + 801020c: f000 febd bl 8010f8a + SMEMCPY(ðhdr->src, src, ETH_HWADDR_LEN); + 8010210: 693b ldr r3, [r7, #16] + 8010212: 3306 adds r3, #6 + 8010214: 2206 movs r2, #6 + 8010216: 6879 ldr r1, [r7, #4] + 8010218: 4618 mov r0, r3 + 801021a: f000 feb6 bl 8010f8a + + LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!", + 801021e: 68fb ldr r3, [r7, #12] + 8010220: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8010224: 2b06 cmp r3, #6 + 8010226: d006 beq.n 8010236 + 8010228: 4b0a ldr r3, [pc, #40] ; (8010254 ) + 801022a: f44f 7299 mov.w r2, #306 ; 0x132 + 801022e: 490a ldr r1, [pc, #40] ; (8010258 ) + 8010230: 480a ldr r0, [pc, #40] ; (801025c ) + 8010232: f000 fcc9 bl 8010bc8 + (netif->hwaddr_len == ETH_HWADDR_LEN)); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, + ("ethernet_output: sending packet %p\n", (void *)p)); + + /* send the packet */ + return netif->linkoutput(netif, p); + 8010236: 68fb ldr r3, [r7, #12] + 8010238: 699b ldr r3, [r3, #24] + 801023a: 68b9 ldr r1, [r7, #8] + 801023c: 68f8 ldr r0, [r7, #12] + 801023e: 4798 blx r3 + 8010240: 4603 mov r3, r0 + 8010242: e002 b.n 801024a + goto pbuf_header_failed; + 8010244: bf00 nop + +pbuf_header_failed: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("ethernet_output: could not allocate room for header.\n")); + LINK_STATS_INC(link.lenerr); + return ERR_BUF; + 8010246: f06f 0301 mvn.w r3, #1 +} + 801024a: 4618 mov r0, r3 + 801024c: 3718 adds r7, #24 + 801024e: 46bd mov sp, r7 + 8010250: bd80 pop {r7, pc} + 8010252: bf00 nop + 8010254: 08014be4 .word 0x08014be4 + 8010258: 08014c1c .word 0x08014c1c + 801025c: 08014c50 .word 0x08014c50 + +08010260 : + 8010260: 4b16 ldr r3, [pc, #88] ; (80102bc ) + 8010262: b510 push {r4, lr} + 8010264: 681c ldr r4, [r3, #0] + 8010266: 6b23 ldr r3, [r4, #48] ; 0x30 + 8010268: b9b3 cbnz r3, 8010298 + 801026a: 2018 movs r0, #24 + 801026c: f000 ff06 bl 801107c + 8010270: 4602 mov r2, r0 + 8010272: 6320 str r0, [r4, #48] ; 0x30 + 8010274: b920 cbnz r0, 8010280 + 8010276: 4b12 ldr r3, [pc, #72] ; (80102c0 ) + 8010278: 4812 ldr r0, [pc, #72] ; (80102c4 ) + 801027a: 2152 movs r1, #82 ; 0x52 + 801027c: f000 fe94 bl 8010fa8 <__assert_func> + 8010280: 4911 ldr r1, [pc, #68] ; (80102c8 ) + 8010282: 4b12 ldr r3, [pc, #72] ; (80102cc ) + 8010284: e9c0 1300 strd r1, r3, [r0] + 8010288: 4b11 ldr r3, [pc, #68] ; (80102d0 ) + 801028a: 6083 str r3, [r0, #8] + 801028c: 230b movs r3, #11 + 801028e: 8183 strh r3, [r0, #12] + 8010290: 2100 movs r1, #0 + 8010292: 2001 movs r0, #1 + 8010294: e9c2 0104 strd r0, r1, [r2, #16] + 8010298: 6b21 ldr r1, [r4, #48] ; 0x30 + 801029a: 480e ldr r0, [pc, #56] ; (80102d4 ) + 801029c: 690b ldr r3, [r1, #16] + 801029e: 694c ldr r4, [r1, #20] + 80102a0: 4a0d ldr r2, [pc, #52] ; (80102d8 ) + 80102a2: 4358 muls r0, r3 + 80102a4: fb02 0004 mla r0, r2, r4, r0 + 80102a8: fba3 3202 umull r3, r2, r3, r2 + 80102ac: 3301 adds r3, #1 + 80102ae: eb40 0002 adc.w r0, r0, r2 + 80102b2: e9c1 3004 strd r3, r0, [r1, #16] + 80102b6: f020 4000 bic.w r0, r0, #2147483648 ; 0x80000000 + 80102ba: bd10 pop {r4, pc} + 80102bc: 240000cc .word 0x240000cc + 80102c0: 08014da6 .word 0x08014da6 + 80102c4: 08014dbd .word 0x08014dbd + 80102c8: abcd330e .word 0xabcd330e + 80102cc: e66d1234 .word 0xe66d1234 + 80102d0: 0005deec .word 0x0005deec + 80102d4: 5851f42d .word 0x5851f42d + 80102d8: 4c957f2d .word 0x4c957f2d + +080102dc <_strtoul_l.constprop.0>: + 80102dc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 80102e0: 4f36 ldr r7, [pc, #216] ; (80103bc <_strtoul_l.constprop.0+0xe0>) + 80102e2: 4686 mov lr, r0 + 80102e4: 460d mov r5, r1 + 80102e6: 4628 mov r0, r5 + 80102e8: f815 4b01 ldrb.w r4, [r5], #1 + 80102ec: 5d3e ldrb r6, [r7, r4] + 80102ee: f016 0608 ands.w r6, r6, #8 + 80102f2: d1f8 bne.n 80102e6 <_strtoul_l.constprop.0+0xa> + 80102f4: 2c2d cmp r4, #45 ; 0x2d + 80102f6: d130 bne.n 801035a <_strtoul_l.constprop.0+0x7e> + 80102f8: 782c ldrb r4, [r5, #0] + 80102fa: 2601 movs r6, #1 + 80102fc: 1c85 adds r5, r0, #2 + 80102fe: 2b00 cmp r3, #0 + 8010300: d057 beq.n 80103b2 <_strtoul_l.constprop.0+0xd6> + 8010302: 2b10 cmp r3, #16 + 8010304: d109 bne.n 801031a <_strtoul_l.constprop.0+0x3e> + 8010306: 2c30 cmp r4, #48 ; 0x30 + 8010308: d107 bne.n 801031a <_strtoul_l.constprop.0+0x3e> + 801030a: 7828 ldrb r0, [r5, #0] + 801030c: f000 00df and.w r0, r0, #223 ; 0xdf + 8010310: 2858 cmp r0, #88 ; 0x58 + 8010312: d149 bne.n 80103a8 <_strtoul_l.constprop.0+0xcc> + 8010314: 786c ldrb r4, [r5, #1] + 8010316: 2310 movs r3, #16 + 8010318: 3502 adds r5, #2 + 801031a: f04f 38ff mov.w r8, #4294967295 + 801031e: 2700 movs r7, #0 + 8010320: fbb8 f8f3 udiv r8, r8, r3 + 8010324: fb03 f908 mul.w r9, r3, r8 + 8010328: ea6f 0909 mvn.w r9, r9 + 801032c: 4638 mov r0, r7 + 801032e: f1a4 0c30 sub.w ip, r4, #48 ; 0x30 + 8010332: f1bc 0f09 cmp.w ip, #9 + 8010336: d815 bhi.n 8010364 <_strtoul_l.constprop.0+0x88> + 8010338: 4664 mov r4, ip + 801033a: 42a3 cmp r3, r4 + 801033c: dd23 ble.n 8010386 <_strtoul_l.constprop.0+0xaa> + 801033e: f1b7 3fff cmp.w r7, #4294967295 + 8010342: d007 beq.n 8010354 <_strtoul_l.constprop.0+0x78> + 8010344: 4580 cmp r8, r0 + 8010346: d31b bcc.n 8010380 <_strtoul_l.constprop.0+0xa4> + 8010348: d101 bne.n 801034e <_strtoul_l.constprop.0+0x72> + 801034a: 45a1 cmp r9, r4 + 801034c: db18 blt.n 8010380 <_strtoul_l.constprop.0+0xa4> + 801034e: fb00 4003 mla r0, r0, r3, r4 + 8010352: 2701 movs r7, #1 + 8010354: f815 4b01 ldrb.w r4, [r5], #1 + 8010358: e7e9 b.n 801032e <_strtoul_l.constprop.0+0x52> + 801035a: 2c2b cmp r4, #43 ; 0x2b + 801035c: bf04 itt eq + 801035e: 782c ldrbeq r4, [r5, #0] + 8010360: 1c85 addeq r5, r0, #2 + 8010362: e7cc b.n 80102fe <_strtoul_l.constprop.0+0x22> + 8010364: f1a4 0c41 sub.w ip, r4, #65 ; 0x41 + 8010368: f1bc 0f19 cmp.w ip, #25 + 801036c: d801 bhi.n 8010372 <_strtoul_l.constprop.0+0x96> + 801036e: 3c37 subs r4, #55 ; 0x37 + 8010370: e7e3 b.n 801033a <_strtoul_l.constprop.0+0x5e> + 8010372: f1a4 0c61 sub.w ip, r4, #97 ; 0x61 + 8010376: f1bc 0f19 cmp.w ip, #25 + 801037a: d804 bhi.n 8010386 <_strtoul_l.constprop.0+0xaa> + 801037c: 3c57 subs r4, #87 ; 0x57 + 801037e: e7dc b.n 801033a <_strtoul_l.constprop.0+0x5e> + 8010380: f04f 37ff mov.w r7, #4294967295 + 8010384: e7e6 b.n 8010354 <_strtoul_l.constprop.0+0x78> + 8010386: 1c7b adds r3, r7, #1 + 8010388: d106 bne.n 8010398 <_strtoul_l.constprop.0+0xbc> + 801038a: 2322 movs r3, #34 ; 0x22 + 801038c: f8ce 3000 str.w r3, [lr] + 8010390: 4638 mov r0, r7 + 8010392: b932 cbnz r2, 80103a2 <_strtoul_l.constprop.0+0xc6> + 8010394: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 8010398: b106 cbz r6, 801039c <_strtoul_l.constprop.0+0xc0> + 801039a: 4240 negs r0, r0 + 801039c: 2a00 cmp r2, #0 + 801039e: d0f9 beq.n 8010394 <_strtoul_l.constprop.0+0xb8> + 80103a0: b107 cbz r7, 80103a4 <_strtoul_l.constprop.0+0xc8> + 80103a2: 1e69 subs r1, r5, #1 + 80103a4: 6011 str r1, [r2, #0] + 80103a6: e7f5 b.n 8010394 <_strtoul_l.constprop.0+0xb8> + 80103a8: 2430 movs r4, #48 ; 0x30 + 80103aa: 2b00 cmp r3, #0 + 80103ac: d1b5 bne.n 801031a <_strtoul_l.constprop.0+0x3e> + 80103ae: 2308 movs r3, #8 + 80103b0: e7b3 b.n 801031a <_strtoul_l.constprop.0+0x3e> + 80103b2: 2c30 cmp r4, #48 ; 0x30 + 80103b4: d0a9 beq.n 801030a <_strtoul_l.constprop.0+0x2e> + 80103b6: 230a movs r3, #10 + 80103b8: e7af b.n 801031a <_strtoul_l.constprop.0+0x3e> + 80103ba: bf00 nop + 80103bc: 08014e16 .word 0x08014e16 + +080103c0 : + 80103c0: 4613 mov r3, r2 + 80103c2: 460a mov r2, r1 + 80103c4: 4601 mov r1, r0 + 80103c6: 4802 ldr r0, [pc, #8] ; (80103d0 ) + 80103c8: 6800 ldr r0, [r0, #0] + 80103ca: f7ff bf87 b.w 80102dc <_strtoul_l.constprop.0> + 80103ce: bf00 nop + 80103d0: 240000cc .word 0x240000cc + +080103d4 <__sfputc_r>: + 80103d4: 6893 ldr r3, [r2, #8] + 80103d6: 3b01 subs r3, #1 + 80103d8: 2b00 cmp r3, #0 + 80103da: b410 push {r4} + 80103dc: 6093 str r3, [r2, #8] + 80103de: da08 bge.n 80103f2 <__sfputc_r+0x1e> + 80103e0: 6994 ldr r4, [r2, #24] + 80103e2: 42a3 cmp r3, r4 + 80103e4: db01 blt.n 80103ea <__sfputc_r+0x16> + 80103e6: 290a cmp r1, #10 + 80103e8: d103 bne.n 80103f2 <__sfputc_r+0x1e> + 80103ea: f85d 4b04 ldr.w r4, [sp], #4 + 80103ee: f000 bca4 b.w 8010d3a <__swbuf_r> + 80103f2: 6813 ldr r3, [r2, #0] + 80103f4: 1c58 adds r0, r3, #1 + 80103f6: 6010 str r0, [r2, #0] + 80103f8: 7019 strb r1, [r3, #0] + 80103fa: 4608 mov r0, r1 + 80103fc: f85d 4b04 ldr.w r4, [sp], #4 + 8010400: 4770 bx lr + +08010402 <__sfputs_r>: + 8010402: b5f8 push {r3, r4, r5, r6, r7, lr} + 8010404: 4606 mov r6, r0 + 8010406: 460f mov r7, r1 + 8010408: 4614 mov r4, r2 + 801040a: 18d5 adds r5, r2, r3 + 801040c: 42ac cmp r4, r5 + 801040e: d101 bne.n 8010414 <__sfputs_r+0x12> + 8010410: 2000 movs r0, #0 + 8010412: e007 b.n 8010424 <__sfputs_r+0x22> + 8010414: f814 1b01 ldrb.w r1, [r4], #1 + 8010418: 463a mov r2, r7 + 801041a: 4630 mov r0, r6 + 801041c: f7ff ffda bl 80103d4 <__sfputc_r> + 8010420: 1c43 adds r3, r0, #1 + 8010422: d1f3 bne.n 801040c <__sfputs_r+0xa> + 8010424: bdf8 pop {r3, r4, r5, r6, r7, pc} + ... + +08010428 <_vfiprintf_r>: + 8010428: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 801042c: 460d mov r5, r1 + 801042e: b09d sub sp, #116 ; 0x74 + 8010430: 4614 mov r4, r2 + 8010432: 4698 mov r8, r3 + 8010434: 4606 mov r6, r0 + 8010436: b118 cbz r0, 8010440 <_vfiprintf_r+0x18> + 8010438: 6a03 ldr r3, [r0, #32] + 801043a: b90b cbnz r3, 8010440 <_vfiprintf_r+0x18> + 801043c: f000 fb34 bl 8010aa8 <__sinit> + 8010440: 6e6b ldr r3, [r5, #100] ; 0x64 + 8010442: 07d9 lsls r1, r3, #31 + 8010444: d405 bmi.n 8010452 <_vfiprintf_r+0x2a> + 8010446: 89ab ldrh r3, [r5, #12] + 8010448: 059a lsls r2, r3, #22 + 801044a: d402 bmi.n 8010452 <_vfiprintf_r+0x2a> + 801044c: 6da8 ldr r0, [r5, #88] ; 0x58 + 801044e: f000 fd9a bl 8010f86 <__retarget_lock_acquire_recursive> + 8010452: 89ab ldrh r3, [r5, #12] + 8010454: 071b lsls r3, r3, #28 + 8010456: d501 bpl.n 801045c <_vfiprintf_r+0x34> + 8010458: 692b ldr r3, [r5, #16] + 801045a: b99b cbnz r3, 8010484 <_vfiprintf_r+0x5c> + 801045c: 4629 mov r1, r5 + 801045e: 4630 mov r0, r6 + 8010460: f000 fca8 bl 8010db4 <__swsetup_r> + 8010464: b170 cbz r0, 8010484 <_vfiprintf_r+0x5c> + 8010466: 6e6b ldr r3, [r5, #100] ; 0x64 + 8010468: 07dc lsls r4, r3, #31 + 801046a: d504 bpl.n 8010476 <_vfiprintf_r+0x4e> + 801046c: f04f 30ff mov.w r0, #4294967295 + 8010470: b01d add sp, #116 ; 0x74 + 8010472: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8010476: 89ab ldrh r3, [r5, #12] + 8010478: 0598 lsls r0, r3, #22 + 801047a: d4f7 bmi.n 801046c <_vfiprintf_r+0x44> + 801047c: 6da8 ldr r0, [r5, #88] ; 0x58 + 801047e: f000 fd83 bl 8010f88 <__retarget_lock_release_recursive> + 8010482: e7f3 b.n 801046c <_vfiprintf_r+0x44> + 8010484: 2300 movs r3, #0 + 8010486: 9309 str r3, [sp, #36] ; 0x24 + 8010488: 2320 movs r3, #32 + 801048a: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 801048e: f8cd 800c str.w r8, [sp, #12] + 8010492: 2330 movs r3, #48 ; 0x30 + 8010494: f8df 81b0 ldr.w r8, [pc, #432] ; 8010648 <_vfiprintf_r+0x220> + 8010498: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 801049c: f04f 0901 mov.w r9, #1 + 80104a0: 4623 mov r3, r4 + 80104a2: 469a mov sl, r3 + 80104a4: f813 2b01 ldrb.w r2, [r3], #1 + 80104a8: b10a cbz r2, 80104ae <_vfiprintf_r+0x86> + 80104aa: 2a25 cmp r2, #37 ; 0x25 + 80104ac: d1f9 bne.n 80104a2 <_vfiprintf_r+0x7a> + 80104ae: ebba 0b04 subs.w fp, sl, r4 + 80104b2: d00b beq.n 80104cc <_vfiprintf_r+0xa4> + 80104b4: 465b mov r3, fp + 80104b6: 4622 mov r2, r4 + 80104b8: 4629 mov r1, r5 + 80104ba: 4630 mov r0, r6 + 80104bc: f7ff ffa1 bl 8010402 <__sfputs_r> + 80104c0: 3001 adds r0, #1 + 80104c2: f000 80a9 beq.w 8010618 <_vfiprintf_r+0x1f0> + 80104c6: 9a09 ldr r2, [sp, #36] ; 0x24 + 80104c8: 445a add r2, fp + 80104ca: 9209 str r2, [sp, #36] ; 0x24 + 80104cc: f89a 3000 ldrb.w r3, [sl] + 80104d0: 2b00 cmp r3, #0 + 80104d2: f000 80a1 beq.w 8010618 <_vfiprintf_r+0x1f0> + 80104d6: 2300 movs r3, #0 + 80104d8: f04f 32ff mov.w r2, #4294967295 + 80104dc: e9cd 2305 strd r2, r3, [sp, #20] + 80104e0: f10a 0a01 add.w sl, sl, #1 + 80104e4: 9304 str r3, [sp, #16] + 80104e6: 9307 str r3, [sp, #28] + 80104e8: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 80104ec: 931a str r3, [sp, #104] ; 0x68 + 80104ee: 4654 mov r4, sl + 80104f0: 2205 movs r2, #5 + 80104f2: f814 1b01 ldrb.w r1, [r4], #1 + 80104f6: 4854 ldr r0, [pc, #336] ; (8010648 <_vfiprintf_r+0x220>) + 80104f8: f7ef ff0a bl 8000310 + 80104fc: 9a04 ldr r2, [sp, #16] + 80104fe: b9d8 cbnz r0, 8010538 <_vfiprintf_r+0x110> + 8010500: 06d1 lsls r1, r2, #27 + 8010502: bf44 itt mi + 8010504: 2320 movmi r3, #32 + 8010506: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 801050a: 0713 lsls r3, r2, #28 + 801050c: bf44 itt mi + 801050e: 232b movmi r3, #43 ; 0x2b + 8010510: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 8010514: f89a 3000 ldrb.w r3, [sl] + 8010518: 2b2a cmp r3, #42 ; 0x2a + 801051a: d015 beq.n 8010548 <_vfiprintf_r+0x120> + 801051c: 9a07 ldr r2, [sp, #28] + 801051e: 4654 mov r4, sl + 8010520: 2000 movs r0, #0 + 8010522: f04f 0c0a mov.w ip, #10 + 8010526: 4621 mov r1, r4 + 8010528: f811 3b01 ldrb.w r3, [r1], #1 + 801052c: 3b30 subs r3, #48 ; 0x30 + 801052e: 2b09 cmp r3, #9 + 8010530: d94d bls.n 80105ce <_vfiprintf_r+0x1a6> + 8010532: b1b0 cbz r0, 8010562 <_vfiprintf_r+0x13a> + 8010534: 9207 str r2, [sp, #28] + 8010536: e014 b.n 8010562 <_vfiprintf_r+0x13a> + 8010538: eba0 0308 sub.w r3, r0, r8 + 801053c: fa09 f303 lsl.w r3, r9, r3 + 8010540: 4313 orrs r3, r2 + 8010542: 9304 str r3, [sp, #16] + 8010544: 46a2 mov sl, r4 + 8010546: e7d2 b.n 80104ee <_vfiprintf_r+0xc6> + 8010548: 9b03 ldr r3, [sp, #12] + 801054a: 1d19 adds r1, r3, #4 + 801054c: 681b ldr r3, [r3, #0] + 801054e: 9103 str r1, [sp, #12] + 8010550: 2b00 cmp r3, #0 + 8010552: bfbb ittet lt + 8010554: 425b neglt r3, r3 + 8010556: f042 0202 orrlt.w r2, r2, #2 + 801055a: 9307 strge r3, [sp, #28] + 801055c: 9307 strlt r3, [sp, #28] + 801055e: bfb8 it lt + 8010560: 9204 strlt r2, [sp, #16] + 8010562: 7823 ldrb r3, [r4, #0] + 8010564: 2b2e cmp r3, #46 ; 0x2e + 8010566: d10c bne.n 8010582 <_vfiprintf_r+0x15a> + 8010568: 7863 ldrb r3, [r4, #1] + 801056a: 2b2a cmp r3, #42 ; 0x2a + 801056c: d134 bne.n 80105d8 <_vfiprintf_r+0x1b0> + 801056e: 9b03 ldr r3, [sp, #12] + 8010570: 1d1a adds r2, r3, #4 + 8010572: 681b ldr r3, [r3, #0] + 8010574: 9203 str r2, [sp, #12] + 8010576: 2b00 cmp r3, #0 + 8010578: bfb8 it lt + 801057a: f04f 33ff movlt.w r3, #4294967295 + 801057e: 3402 adds r4, #2 + 8010580: 9305 str r3, [sp, #20] + 8010582: f8df a0d4 ldr.w sl, [pc, #212] ; 8010658 <_vfiprintf_r+0x230> + 8010586: 7821 ldrb r1, [r4, #0] + 8010588: 2203 movs r2, #3 + 801058a: 4650 mov r0, sl + 801058c: f7ef fec0 bl 8000310 + 8010590: b138 cbz r0, 80105a2 <_vfiprintf_r+0x17a> + 8010592: 9b04 ldr r3, [sp, #16] + 8010594: eba0 000a sub.w r0, r0, sl + 8010598: 2240 movs r2, #64 ; 0x40 + 801059a: 4082 lsls r2, r0 + 801059c: 4313 orrs r3, r2 + 801059e: 3401 adds r4, #1 + 80105a0: 9304 str r3, [sp, #16] + 80105a2: f814 1b01 ldrb.w r1, [r4], #1 + 80105a6: 4829 ldr r0, [pc, #164] ; (801064c <_vfiprintf_r+0x224>) + 80105a8: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 80105ac: 2206 movs r2, #6 + 80105ae: f7ef feaf bl 8000310 + 80105b2: 2800 cmp r0, #0 + 80105b4: d03f beq.n 8010636 <_vfiprintf_r+0x20e> + 80105b6: 4b26 ldr r3, [pc, #152] ; (8010650 <_vfiprintf_r+0x228>) + 80105b8: bb1b cbnz r3, 8010602 <_vfiprintf_r+0x1da> + 80105ba: 9b03 ldr r3, [sp, #12] + 80105bc: 3307 adds r3, #7 + 80105be: f023 0307 bic.w r3, r3, #7 + 80105c2: 3308 adds r3, #8 + 80105c4: 9303 str r3, [sp, #12] + 80105c6: 9b09 ldr r3, [sp, #36] ; 0x24 + 80105c8: 443b add r3, r7 + 80105ca: 9309 str r3, [sp, #36] ; 0x24 + 80105cc: e768 b.n 80104a0 <_vfiprintf_r+0x78> + 80105ce: fb0c 3202 mla r2, ip, r2, r3 + 80105d2: 460c mov r4, r1 + 80105d4: 2001 movs r0, #1 + 80105d6: e7a6 b.n 8010526 <_vfiprintf_r+0xfe> + 80105d8: 2300 movs r3, #0 + 80105da: 3401 adds r4, #1 + 80105dc: 9305 str r3, [sp, #20] + 80105de: 4619 mov r1, r3 + 80105e0: f04f 0c0a mov.w ip, #10 + 80105e4: 4620 mov r0, r4 + 80105e6: f810 2b01 ldrb.w r2, [r0], #1 + 80105ea: 3a30 subs r2, #48 ; 0x30 + 80105ec: 2a09 cmp r2, #9 + 80105ee: d903 bls.n 80105f8 <_vfiprintf_r+0x1d0> + 80105f0: 2b00 cmp r3, #0 + 80105f2: d0c6 beq.n 8010582 <_vfiprintf_r+0x15a> + 80105f4: 9105 str r1, [sp, #20] + 80105f6: e7c4 b.n 8010582 <_vfiprintf_r+0x15a> + 80105f8: fb0c 2101 mla r1, ip, r1, r2 + 80105fc: 4604 mov r4, r0 + 80105fe: 2301 movs r3, #1 + 8010600: e7f0 b.n 80105e4 <_vfiprintf_r+0x1bc> + 8010602: ab03 add r3, sp, #12 + 8010604: 9300 str r3, [sp, #0] + 8010606: 462a mov r2, r5 + 8010608: 4b12 ldr r3, [pc, #72] ; (8010654 <_vfiprintf_r+0x22c>) + 801060a: a904 add r1, sp, #16 + 801060c: 4630 mov r0, r6 + 801060e: f3af 8000 nop.w + 8010612: 4607 mov r7, r0 + 8010614: 1c78 adds r0, r7, #1 + 8010616: d1d6 bne.n 80105c6 <_vfiprintf_r+0x19e> + 8010618: 6e6b ldr r3, [r5, #100] ; 0x64 + 801061a: 07d9 lsls r1, r3, #31 + 801061c: d405 bmi.n 801062a <_vfiprintf_r+0x202> + 801061e: 89ab ldrh r3, [r5, #12] + 8010620: 059a lsls r2, r3, #22 + 8010622: d402 bmi.n 801062a <_vfiprintf_r+0x202> + 8010624: 6da8 ldr r0, [r5, #88] ; 0x58 + 8010626: f000 fcaf bl 8010f88 <__retarget_lock_release_recursive> + 801062a: 89ab ldrh r3, [r5, #12] + 801062c: 065b lsls r3, r3, #25 + 801062e: f53f af1d bmi.w 801046c <_vfiprintf_r+0x44> + 8010632: 9809 ldr r0, [sp, #36] ; 0x24 + 8010634: e71c b.n 8010470 <_vfiprintf_r+0x48> + 8010636: ab03 add r3, sp, #12 + 8010638: 9300 str r3, [sp, #0] + 801063a: 462a mov r2, r5 + 801063c: 4b05 ldr r3, [pc, #20] ; (8010654 <_vfiprintf_r+0x22c>) + 801063e: a904 add r1, sp, #16 + 8010640: 4630 mov r0, r6 + 8010642: f000 f883 bl 801074c <_printf_i> + 8010646: e7e4 b.n 8010612 <_vfiprintf_r+0x1ea> + 8010648: 08014f16 .word 0x08014f16 + 801064c: 08014f20 .word 0x08014f20 + 8010650: 00000000 .word 0x00000000 + 8010654: 08010403 .word 0x08010403 + 8010658: 08014f1c .word 0x08014f1c + +0801065c : + 801065c: 4613 mov r3, r2 + 801065e: 460a mov r2, r1 + 8010660: 4601 mov r1, r0 + 8010662: 4802 ldr r0, [pc, #8] ; (801066c ) + 8010664: 6800 ldr r0, [r0, #0] + 8010666: f7ff bedf b.w 8010428 <_vfiprintf_r> + 801066a: bf00 nop + 801066c: 240000cc .word 0x240000cc + +08010670 <_printf_common>: + 8010670: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8010674: 4616 mov r6, r2 + 8010676: 4699 mov r9, r3 + 8010678: 688a ldr r2, [r1, #8] + 801067a: 690b ldr r3, [r1, #16] + 801067c: f8dd 8020 ldr.w r8, [sp, #32] + 8010680: 4293 cmp r3, r2 + 8010682: bfb8 it lt + 8010684: 4613 movlt r3, r2 + 8010686: 6033 str r3, [r6, #0] + 8010688: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 801068c: 4607 mov r7, r0 + 801068e: 460c mov r4, r1 + 8010690: b10a cbz r2, 8010696 <_printf_common+0x26> + 8010692: 3301 adds r3, #1 + 8010694: 6033 str r3, [r6, #0] + 8010696: 6823 ldr r3, [r4, #0] + 8010698: 0699 lsls r1, r3, #26 + 801069a: bf42 ittt mi + 801069c: 6833 ldrmi r3, [r6, #0] + 801069e: 3302 addmi r3, #2 + 80106a0: 6033 strmi r3, [r6, #0] + 80106a2: 6825 ldr r5, [r4, #0] + 80106a4: f015 0506 ands.w r5, r5, #6 + 80106a8: d106 bne.n 80106b8 <_printf_common+0x48> + 80106aa: f104 0a19 add.w sl, r4, #25 + 80106ae: 68e3 ldr r3, [r4, #12] + 80106b0: 6832 ldr r2, [r6, #0] + 80106b2: 1a9b subs r3, r3, r2 + 80106b4: 42ab cmp r3, r5 + 80106b6: dc26 bgt.n 8010706 <_printf_common+0x96> + 80106b8: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 + 80106bc: 1e13 subs r3, r2, #0 + 80106be: 6822 ldr r2, [r4, #0] + 80106c0: bf18 it ne + 80106c2: 2301 movne r3, #1 + 80106c4: 0692 lsls r2, r2, #26 + 80106c6: d42b bmi.n 8010720 <_printf_common+0xb0> + 80106c8: f104 0243 add.w r2, r4, #67 ; 0x43 + 80106cc: 4649 mov r1, r9 + 80106ce: 4638 mov r0, r7 + 80106d0: 47c0 blx r8 + 80106d2: 3001 adds r0, #1 + 80106d4: d01e beq.n 8010714 <_printf_common+0xa4> + 80106d6: 6823 ldr r3, [r4, #0] + 80106d8: 6922 ldr r2, [r4, #16] + 80106da: f003 0306 and.w r3, r3, #6 + 80106de: 2b04 cmp r3, #4 + 80106e0: bf02 ittt eq + 80106e2: 68e5 ldreq r5, [r4, #12] + 80106e4: 6833 ldreq r3, [r6, #0] + 80106e6: 1aed subeq r5, r5, r3 + 80106e8: 68a3 ldr r3, [r4, #8] + 80106ea: bf0c ite eq + 80106ec: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 80106f0: 2500 movne r5, #0 + 80106f2: 4293 cmp r3, r2 + 80106f4: bfc4 itt gt + 80106f6: 1a9b subgt r3, r3, r2 + 80106f8: 18ed addgt r5, r5, r3 + 80106fa: 2600 movs r6, #0 + 80106fc: 341a adds r4, #26 + 80106fe: 42b5 cmp r5, r6 + 8010700: d11a bne.n 8010738 <_printf_common+0xc8> + 8010702: 2000 movs r0, #0 + 8010704: e008 b.n 8010718 <_printf_common+0xa8> + 8010706: 2301 movs r3, #1 + 8010708: 4652 mov r2, sl + 801070a: 4649 mov r1, r9 + 801070c: 4638 mov r0, r7 + 801070e: 47c0 blx r8 + 8010710: 3001 adds r0, #1 + 8010712: d103 bne.n 801071c <_printf_common+0xac> + 8010714: f04f 30ff mov.w r0, #4294967295 + 8010718: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 801071c: 3501 adds r5, #1 + 801071e: e7c6 b.n 80106ae <_printf_common+0x3e> + 8010720: 18e1 adds r1, r4, r3 + 8010722: 1c5a adds r2, r3, #1 + 8010724: 2030 movs r0, #48 ; 0x30 + 8010726: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 801072a: 4422 add r2, r4 + 801072c: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 8010730: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 8010734: 3302 adds r3, #2 + 8010736: e7c7 b.n 80106c8 <_printf_common+0x58> + 8010738: 2301 movs r3, #1 + 801073a: 4622 mov r2, r4 + 801073c: 4649 mov r1, r9 + 801073e: 4638 mov r0, r7 + 8010740: 47c0 blx r8 + 8010742: 3001 adds r0, #1 + 8010744: d0e6 beq.n 8010714 <_printf_common+0xa4> + 8010746: 3601 adds r6, #1 + 8010748: e7d9 b.n 80106fe <_printf_common+0x8e> + ... + +0801074c <_printf_i>: + 801074c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 8010750: 7e0f ldrb r7, [r1, #24] + 8010752: 9d0c ldr r5, [sp, #48] ; 0x30 + 8010754: 2f78 cmp r7, #120 ; 0x78 + 8010756: 4691 mov r9, r2 + 8010758: 4680 mov r8, r0 + 801075a: 460c mov r4, r1 + 801075c: 469a mov sl, r3 + 801075e: f101 0243 add.w r2, r1, #67 ; 0x43 + 8010762: d807 bhi.n 8010774 <_printf_i+0x28> + 8010764: 2f62 cmp r7, #98 ; 0x62 + 8010766: d80a bhi.n 801077e <_printf_i+0x32> + 8010768: 2f00 cmp r7, #0 + 801076a: f000 80d4 beq.w 8010916 <_printf_i+0x1ca> + 801076e: 2f58 cmp r7, #88 ; 0x58 + 8010770: f000 80c0 beq.w 80108f4 <_printf_i+0x1a8> + 8010774: f104 0542 add.w r5, r4, #66 ; 0x42 + 8010778: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 801077c: e03a b.n 80107f4 <_printf_i+0xa8> + 801077e: f1a7 0363 sub.w r3, r7, #99 ; 0x63 + 8010782: 2b15 cmp r3, #21 + 8010784: d8f6 bhi.n 8010774 <_printf_i+0x28> + 8010786: a101 add r1, pc, #4 ; (adr r1, 801078c <_printf_i+0x40>) + 8010788: f851 f023 ldr.w pc, [r1, r3, lsl #2] + 801078c: 080107e5 .word 0x080107e5 + 8010790: 080107f9 .word 0x080107f9 + 8010794: 08010775 .word 0x08010775 + 8010798: 08010775 .word 0x08010775 + 801079c: 08010775 .word 0x08010775 + 80107a0: 08010775 .word 0x08010775 + 80107a4: 080107f9 .word 0x080107f9 + 80107a8: 08010775 .word 0x08010775 + 80107ac: 08010775 .word 0x08010775 + 80107b0: 08010775 .word 0x08010775 + 80107b4: 08010775 .word 0x08010775 + 80107b8: 080108fd .word 0x080108fd + 80107bc: 08010825 .word 0x08010825 + 80107c0: 080108b7 .word 0x080108b7 + 80107c4: 08010775 .word 0x08010775 + 80107c8: 08010775 .word 0x08010775 + 80107cc: 0801091f .word 0x0801091f + 80107d0: 08010775 .word 0x08010775 + 80107d4: 08010825 .word 0x08010825 + 80107d8: 08010775 .word 0x08010775 + 80107dc: 08010775 .word 0x08010775 + 80107e0: 080108bf .word 0x080108bf + 80107e4: 682b ldr r3, [r5, #0] + 80107e6: 1d1a adds r2, r3, #4 + 80107e8: 681b ldr r3, [r3, #0] + 80107ea: 602a str r2, [r5, #0] + 80107ec: f104 0542 add.w r5, r4, #66 ; 0x42 + 80107f0: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 80107f4: 2301 movs r3, #1 + 80107f6: e09f b.n 8010938 <_printf_i+0x1ec> + 80107f8: 6820 ldr r0, [r4, #0] + 80107fa: 682b ldr r3, [r5, #0] + 80107fc: 0607 lsls r7, r0, #24 + 80107fe: f103 0104 add.w r1, r3, #4 + 8010802: 6029 str r1, [r5, #0] + 8010804: d501 bpl.n 801080a <_printf_i+0xbe> + 8010806: 681e ldr r6, [r3, #0] + 8010808: e003 b.n 8010812 <_printf_i+0xc6> + 801080a: 0646 lsls r6, r0, #25 + 801080c: d5fb bpl.n 8010806 <_printf_i+0xba> + 801080e: f9b3 6000 ldrsh.w r6, [r3] + 8010812: 2e00 cmp r6, #0 + 8010814: da03 bge.n 801081e <_printf_i+0xd2> + 8010816: 232d movs r3, #45 ; 0x2d + 8010818: 4276 negs r6, r6 + 801081a: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 801081e: 485a ldr r0, [pc, #360] ; (8010988 <_printf_i+0x23c>) + 8010820: 230a movs r3, #10 + 8010822: e012 b.n 801084a <_printf_i+0xfe> + 8010824: 682b ldr r3, [r5, #0] + 8010826: 6820 ldr r0, [r4, #0] + 8010828: 1d19 adds r1, r3, #4 + 801082a: 6029 str r1, [r5, #0] + 801082c: 0605 lsls r5, r0, #24 + 801082e: d501 bpl.n 8010834 <_printf_i+0xe8> + 8010830: 681e ldr r6, [r3, #0] + 8010832: e002 b.n 801083a <_printf_i+0xee> + 8010834: 0641 lsls r1, r0, #25 + 8010836: d5fb bpl.n 8010830 <_printf_i+0xe4> + 8010838: 881e ldrh r6, [r3, #0] + 801083a: 4853 ldr r0, [pc, #332] ; (8010988 <_printf_i+0x23c>) + 801083c: 2f6f cmp r7, #111 ; 0x6f + 801083e: bf0c ite eq + 8010840: 2308 moveq r3, #8 + 8010842: 230a movne r3, #10 + 8010844: 2100 movs r1, #0 + 8010846: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 801084a: 6865 ldr r5, [r4, #4] + 801084c: 60a5 str r5, [r4, #8] + 801084e: 2d00 cmp r5, #0 + 8010850: bfa2 ittt ge + 8010852: 6821 ldrge r1, [r4, #0] + 8010854: f021 0104 bicge.w r1, r1, #4 + 8010858: 6021 strge r1, [r4, #0] + 801085a: b90e cbnz r6, 8010860 <_printf_i+0x114> + 801085c: 2d00 cmp r5, #0 + 801085e: d04b beq.n 80108f8 <_printf_i+0x1ac> + 8010860: 4615 mov r5, r2 + 8010862: fbb6 f1f3 udiv r1, r6, r3 + 8010866: fb03 6711 mls r7, r3, r1, r6 + 801086a: 5dc7 ldrb r7, [r0, r7] + 801086c: f805 7d01 strb.w r7, [r5, #-1]! + 8010870: 4637 mov r7, r6 + 8010872: 42bb cmp r3, r7 + 8010874: 460e mov r6, r1 + 8010876: d9f4 bls.n 8010862 <_printf_i+0x116> + 8010878: 2b08 cmp r3, #8 + 801087a: d10b bne.n 8010894 <_printf_i+0x148> + 801087c: 6823 ldr r3, [r4, #0] + 801087e: 07de lsls r6, r3, #31 + 8010880: d508 bpl.n 8010894 <_printf_i+0x148> + 8010882: 6923 ldr r3, [r4, #16] + 8010884: 6861 ldr r1, [r4, #4] + 8010886: 4299 cmp r1, r3 + 8010888: bfde ittt le + 801088a: 2330 movle r3, #48 ; 0x30 + 801088c: f805 3c01 strble.w r3, [r5, #-1] + 8010890: f105 35ff addle.w r5, r5, #4294967295 + 8010894: 1b52 subs r2, r2, r5 + 8010896: 6122 str r2, [r4, #16] + 8010898: f8cd a000 str.w sl, [sp] + 801089c: 464b mov r3, r9 + 801089e: aa03 add r2, sp, #12 + 80108a0: 4621 mov r1, r4 + 80108a2: 4640 mov r0, r8 + 80108a4: f7ff fee4 bl 8010670 <_printf_common> + 80108a8: 3001 adds r0, #1 + 80108aa: d14a bne.n 8010942 <_printf_i+0x1f6> + 80108ac: f04f 30ff mov.w r0, #4294967295 + 80108b0: b004 add sp, #16 + 80108b2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80108b6: 6823 ldr r3, [r4, #0] + 80108b8: f043 0320 orr.w r3, r3, #32 + 80108bc: 6023 str r3, [r4, #0] + 80108be: 4833 ldr r0, [pc, #204] ; (801098c <_printf_i+0x240>) + 80108c0: 2778 movs r7, #120 ; 0x78 + 80108c2: f884 7045 strb.w r7, [r4, #69] ; 0x45 + 80108c6: 6823 ldr r3, [r4, #0] + 80108c8: 6829 ldr r1, [r5, #0] + 80108ca: 061f lsls r7, r3, #24 + 80108cc: f851 6b04 ldr.w r6, [r1], #4 + 80108d0: d402 bmi.n 80108d8 <_printf_i+0x18c> + 80108d2: 065f lsls r7, r3, #25 + 80108d4: bf48 it mi + 80108d6: b2b6 uxthmi r6, r6 + 80108d8: 07df lsls r7, r3, #31 + 80108da: bf48 it mi + 80108dc: f043 0320 orrmi.w r3, r3, #32 + 80108e0: 6029 str r1, [r5, #0] + 80108e2: bf48 it mi + 80108e4: 6023 strmi r3, [r4, #0] + 80108e6: b91e cbnz r6, 80108f0 <_printf_i+0x1a4> + 80108e8: 6823 ldr r3, [r4, #0] + 80108ea: f023 0320 bic.w r3, r3, #32 + 80108ee: 6023 str r3, [r4, #0] + 80108f0: 2310 movs r3, #16 + 80108f2: e7a7 b.n 8010844 <_printf_i+0xf8> + 80108f4: 4824 ldr r0, [pc, #144] ; (8010988 <_printf_i+0x23c>) + 80108f6: e7e4 b.n 80108c2 <_printf_i+0x176> + 80108f8: 4615 mov r5, r2 + 80108fa: e7bd b.n 8010878 <_printf_i+0x12c> + 80108fc: 682b ldr r3, [r5, #0] + 80108fe: 6826 ldr r6, [r4, #0] + 8010900: 6961 ldr r1, [r4, #20] + 8010902: 1d18 adds r0, r3, #4 + 8010904: 6028 str r0, [r5, #0] + 8010906: 0635 lsls r5, r6, #24 + 8010908: 681b ldr r3, [r3, #0] + 801090a: d501 bpl.n 8010910 <_printf_i+0x1c4> + 801090c: 6019 str r1, [r3, #0] + 801090e: e002 b.n 8010916 <_printf_i+0x1ca> + 8010910: 0670 lsls r0, r6, #25 + 8010912: d5fb bpl.n 801090c <_printf_i+0x1c0> + 8010914: 8019 strh r1, [r3, #0] + 8010916: 2300 movs r3, #0 + 8010918: 6123 str r3, [r4, #16] + 801091a: 4615 mov r5, r2 + 801091c: e7bc b.n 8010898 <_printf_i+0x14c> + 801091e: 682b ldr r3, [r5, #0] + 8010920: 1d1a adds r2, r3, #4 + 8010922: 602a str r2, [r5, #0] + 8010924: 681d ldr r5, [r3, #0] + 8010926: 6862 ldr r2, [r4, #4] + 8010928: 2100 movs r1, #0 + 801092a: 4628 mov r0, r5 + 801092c: f7ef fcf0 bl 8000310 + 8010930: b108 cbz r0, 8010936 <_printf_i+0x1ea> + 8010932: 1b40 subs r0, r0, r5 + 8010934: 6060 str r0, [r4, #4] + 8010936: 6863 ldr r3, [r4, #4] + 8010938: 6123 str r3, [r4, #16] + 801093a: 2300 movs r3, #0 + 801093c: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8010940: e7aa b.n 8010898 <_printf_i+0x14c> + 8010942: 6923 ldr r3, [r4, #16] + 8010944: 462a mov r2, r5 + 8010946: 4649 mov r1, r9 + 8010948: 4640 mov r0, r8 + 801094a: 47d0 blx sl + 801094c: 3001 adds r0, #1 + 801094e: d0ad beq.n 80108ac <_printf_i+0x160> + 8010950: 6823 ldr r3, [r4, #0] + 8010952: 079b lsls r3, r3, #30 + 8010954: d413 bmi.n 801097e <_printf_i+0x232> + 8010956: 68e0 ldr r0, [r4, #12] + 8010958: 9b03 ldr r3, [sp, #12] + 801095a: 4298 cmp r0, r3 + 801095c: bfb8 it lt + 801095e: 4618 movlt r0, r3 + 8010960: e7a6 b.n 80108b0 <_printf_i+0x164> + 8010962: 2301 movs r3, #1 + 8010964: 4632 mov r2, r6 + 8010966: 4649 mov r1, r9 + 8010968: 4640 mov r0, r8 + 801096a: 47d0 blx sl + 801096c: 3001 adds r0, #1 + 801096e: d09d beq.n 80108ac <_printf_i+0x160> + 8010970: 3501 adds r5, #1 + 8010972: 68e3 ldr r3, [r4, #12] + 8010974: 9903 ldr r1, [sp, #12] + 8010976: 1a5b subs r3, r3, r1 + 8010978: 42ab cmp r3, r5 + 801097a: dcf2 bgt.n 8010962 <_printf_i+0x216> + 801097c: e7eb b.n 8010956 <_printf_i+0x20a> + 801097e: 2500 movs r5, #0 + 8010980: f104 0619 add.w r6, r4, #25 + 8010984: e7f5 b.n 8010972 <_printf_i+0x226> + 8010986: bf00 nop + 8010988: 08014f27 .word 0x08014f27 + 801098c: 08014f38 .word 0x08014f38 + +08010990 : + 8010990: 2300 movs r3, #0 + 8010992: b510 push {r4, lr} + 8010994: 4604 mov r4, r0 + 8010996: e9c0 3300 strd r3, r3, [r0] + 801099a: e9c0 3304 strd r3, r3, [r0, #16] + 801099e: 6083 str r3, [r0, #8] + 80109a0: 8181 strh r1, [r0, #12] + 80109a2: 6643 str r3, [r0, #100] ; 0x64 + 80109a4: 81c2 strh r2, [r0, #14] + 80109a6: 6183 str r3, [r0, #24] + 80109a8: 4619 mov r1, r3 + 80109aa: 2208 movs r2, #8 + 80109ac: 305c adds r0, #92 ; 0x5c + 80109ae: f000 fa69 bl 8010e84 + 80109b2: 4b0d ldr r3, [pc, #52] ; (80109e8 ) + 80109b4: 6263 str r3, [r4, #36] ; 0x24 + 80109b6: 4b0d ldr r3, [pc, #52] ; (80109ec ) + 80109b8: 62a3 str r3, [r4, #40] ; 0x28 + 80109ba: 4b0d ldr r3, [pc, #52] ; (80109f0 ) + 80109bc: 62e3 str r3, [r4, #44] ; 0x2c + 80109be: 4b0d ldr r3, [pc, #52] ; (80109f4 ) + 80109c0: 6323 str r3, [r4, #48] ; 0x30 + 80109c2: 4b0d ldr r3, [pc, #52] ; (80109f8 ) + 80109c4: 6224 str r4, [r4, #32] + 80109c6: 429c cmp r4, r3 + 80109c8: d006 beq.n 80109d8 + 80109ca: f103 0268 add.w r2, r3, #104 ; 0x68 + 80109ce: 4294 cmp r4, r2 + 80109d0: d002 beq.n 80109d8 + 80109d2: 33d0 adds r3, #208 ; 0xd0 + 80109d4: 429c cmp r4, r3 + 80109d6: d105 bne.n 80109e4 + 80109d8: f104 0058 add.w r0, r4, #88 ; 0x58 + 80109dc: e8bd 4010 ldmia.w sp!, {r4, lr} + 80109e0: f000 bad0 b.w 8010f84 <__retarget_lock_init_recursive> + 80109e4: bd10 pop {r4, pc} + 80109e6: bf00 nop + 80109e8: 08010cb5 .word 0x08010cb5 + 80109ec: 08010cd7 .word 0x08010cd7 + 80109f0: 08010d0f .word 0x08010d0f + 80109f4: 08010d33 .word 0x08010d33 + 80109f8: 24007ccc .word 0x24007ccc + +080109fc : + 80109fc: 4a02 ldr r2, [pc, #8] ; (8010a08 ) + 80109fe: 4903 ldr r1, [pc, #12] ; (8010a0c ) + 8010a00: 4803 ldr r0, [pc, #12] ; (8010a10 ) + 8010a02: f000 b869 b.w 8010ad8 <_fwalk_sglue> + 8010a06: bf00 nop + 8010a08: 24000074 .word 0x24000074 + 8010a0c: 080112f1 .word 0x080112f1 + 8010a10: 24000080 .word 0x24000080 + +08010a14 : + 8010a14: 6841 ldr r1, [r0, #4] + 8010a16: 4b0c ldr r3, [pc, #48] ; (8010a48 ) + 8010a18: 4299 cmp r1, r3 + 8010a1a: b510 push {r4, lr} + 8010a1c: 4604 mov r4, r0 + 8010a1e: d001 beq.n 8010a24 + 8010a20: f000 fc66 bl 80112f0 <_fflush_r> + 8010a24: 68a1 ldr r1, [r4, #8] + 8010a26: 4b09 ldr r3, [pc, #36] ; (8010a4c ) + 8010a28: 4299 cmp r1, r3 + 8010a2a: d002 beq.n 8010a32 + 8010a2c: 4620 mov r0, r4 + 8010a2e: f000 fc5f bl 80112f0 <_fflush_r> + 8010a32: 68e1 ldr r1, [r4, #12] + 8010a34: 4b06 ldr r3, [pc, #24] ; (8010a50 ) + 8010a36: 4299 cmp r1, r3 + 8010a38: d004 beq.n 8010a44 + 8010a3a: 4620 mov r0, r4 + 8010a3c: e8bd 4010 ldmia.w sp!, {r4, lr} + 8010a40: f000 bc56 b.w 80112f0 <_fflush_r> + 8010a44: bd10 pop {r4, pc} + 8010a46: bf00 nop + 8010a48: 24007ccc .word 0x24007ccc + 8010a4c: 24007d34 .word 0x24007d34 + 8010a50: 24007d9c .word 0x24007d9c + +08010a54 : + 8010a54: b510 push {r4, lr} + 8010a56: 4b0b ldr r3, [pc, #44] ; (8010a84 ) + 8010a58: 4c0b ldr r4, [pc, #44] ; (8010a88 ) + 8010a5a: 4a0c ldr r2, [pc, #48] ; (8010a8c ) + 8010a5c: 601a str r2, [r3, #0] + 8010a5e: 4620 mov r0, r4 + 8010a60: 2200 movs r2, #0 + 8010a62: 2104 movs r1, #4 + 8010a64: f7ff ff94 bl 8010990 + 8010a68: f104 0068 add.w r0, r4, #104 ; 0x68 + 8010a6c: 2201 movs r2, #1 + 8010a6e: 2109 movs r1, #9 + 8010a70: f7ff ff8e bl 8010990 + 8010a74: f104 00d0 add.w r0, r4, #208 ; 0xd0 + 8010a78: 2202 movs r2, #2 + 8010a7a: e8bd 4010 ldmia.w sp!, {r4, lr} + 8010a7e: 2112 movs r1, #18 + 8010a80: f7ff bf86 b.w 8010990 + 8010a84: 24007e04 .word 0x24007e04 + 8010a88: 24007ccc .word 0x24007ccc + 8010a8c: 080109fd .word 0x080109fd + +08010a90 <__sfp_lock_acquire>: + 8010a90: 4801 ldr r0, [pc, #4] ; (8010a98 <__sfp_lock_acquire+0x8>) + 8010a92: f000 ba78 b.w 8010f86 <__retarget_lock_acquire_recursive> + 8010a96: bf00 nop + 8010a98: 24007e0d .word 0x24007e0d + +08010a9c <__sfp_lock_release>: + 8010a9c: 4801 ldr r0, [pc, #4] ; (8010aa4 <__sfp_lock_release+0x8>) + 8010a9e: f000 ba73 b.w 8010f88 <__retarget_lock_release_recursive> + 8010aa2: bf00 nop + 8010aa4: 24007e0d .word 0x24007e0d + +08010aa8 <__sinit>: + 8010aa8: b510 push {r4, lr} + 8010aaa: 4604 mov r4, r0 + 8010aac: f7ff fff0 bl 8010a90 <__sfp_lock_acquire> + 8010ab0: 6a23 ldr r3, [r4, #32] + 8010ab2: b11b cbz r3, 8010abc <__sinit+0x14> + 8010ab4: e8bd 4010 ldmia.w sp!, {r4, lr} + 8010ab8: f7ff bff0 b.w 8010a9c <__sfp_lock_release> + 8010abc: 4b04 ldr r3, [pc, #16] ; (8010ad0 <__sinit+0x28>) + 8010abe: 6223 str r3, [r4, #32] + 8010ac0: 4b04 ldr r3, [pc, #16] ; (8010ad4 <__sinit+0x2c>) + 8010ac2: 681b ldr r3, [r3, #0] + 8010ac4: 2b00 cmp r3, #0 + 8010ac6: d1f5 bne.n 8010ab4 <__sinit+0xc> + 8010ac8: f7ff ffc4 bl 8010a54 + 8010acc: e7f2 b.n 8010ab4 <__sinit+0xc> + 8010ace: bf00 nop + 8010ad0: 08010a15 .word 0x08010a15 + 8010ad4: 24007e04 .word 0x24007e04 + +08010ad8 <_fwalk_sglue>: + 8010ad8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8010adc: 4607 mov r7, r0 + 8010ade: 4688 mov r8, r1 + 8010ae0: 4614 mov r4, r2 + 8010ae2: 2600 movs r6, #0 + 8010ae4: e9d4 9501 ldrd r9, r5, [r4, #4] + 8010ae8: f1b9 0901 subs.w r9, r9, #1 + 8010aec: d505 bpl.n 8010afa <_fwalk_sglue+0x22> + 8010aee: 6824 ldr r4, [r4, #0] + 8010af0: 2c00 cmp r4, #0 + 8010af2: d1f7 bne.n 8010ae4 <_fwalk_sglue+0xc> + 8010af4: 4630 mov r0, r6 + 8010af6: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8010afa: 89ab ldrh r3, [r5, #12] + 8010afc: 2b01 cmp r3, #1 + 8010afe: d907 bls.n 8010b10 <_fwalk_sglue+0x38> + 8010b00: f9b5 300e ldrsh.w r3, [r5, #14] + 8010b04: 3301 adds r3, #1 + 8010b06: d003 beq.n 8010b10 <_fwalk_sglue+0x38> + 8010b08: 4629 mov r1, r5 + 8010b0a: 4638 mov r0, r7 + 8010b0c: 47c0 blx r8 + 8010b0e: 4306 orrs r6, r0 + 8010b10: 3568 adds r5, #104 ; 0x68 + 8010b12: e7e9 b.n 8010ae8 <_fwalk_sglue+0x10> + +08010b14 <_fwrite_r>: + 8010b14: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8010b18: 9c08 ldr r4, [sp, #32] + 8010b1a: 468a mov sl, r1 + 8010b1c: 4690 mov r8, r2 + 8010b1e: fb02 f903 mul.w r9, r2, r3 + 8010b22: 4606 mov r6, r0 + 8010b24: b118 cbz r0, 8010b2e <_fwrite_r+0x1a> + 8010b26: 6a03 ldr r3, [r0, #32] + 8010b28: b90b cbnz r3, 8010b2e <_fwrite_r+0x1a> + 8010b2a: f7ff ffbd bl 8010aa8 <__sinit> + 8010b2e: 6e63 ldr r3, [r4, #100] ; 0x64 + 8010b30: 07dd lsls r5, r3, #31 + 8010b32: d405 bmi.n 8010b40 <_fwrite_r+0x2c> + 8010b34: 89a3 ldrh r3, [r4, #12] + 8010b36: 0598 lsls r0, r3, #22 + 8010b38: d402 bmi.n 8010b40 <_fwrite_r+0x2c> + 8010b3a: 6da0 ldr r0, [r4, #88] ; 0x58 + 8010b3c: f000 fa23 bl 8010f86 <__retarget_lock_acquire_recursive> + 8010b40: 89a3 ldrh r3, [r4, #12] + 8010b42: 0719 lsls r1, r3, #28 + 8010b44: d516 bpl.n 8010b74 <_fwrite_r+0x60> + 8010b46: 6923 ldr r3, [r4, #16] + 8010b48: b1a3 cbz r3, 8010b74 <_fwrite_r+0x60> + 8010b4a: 2500 movs r5, #0 + 8010b4c: 454d cmp r5, r9 + 8010b4e: d01f beq.n 8010b90 <_fwrite_r+0x7c> + 8010b50: 68a7 ldr r7, [r4, #8] + 8010b52: f81a 1005 ldrb.w r1, [sl, r5] + 8010b56: 3f01 subs r7, #1 + 8010b58: 2f00 cmp r7, #0 + 8010b5a: 60a7 str r7, [r4, #8] + 8010b5c: da04 bge.n 8010b68 <_fwrite_r+0x54> + 8010b5e: 69a3 ldr r3, [r4, #24] + 8010b60: 429f cmp r7, r3 + 8010b62: db0f blt.n 8010b84 <_fwrite_r+0x70> + 8010b64: 290a cmp r1, #10 + 8010b66: d00d beq.n 8010b84 <_fwrite_r+0x70> + 8010b68: 6823 ldr r3, [r4, #0] + 8010b6a: 1c5a adds r2, r3, #1 + 8010b6c: 6022 str r2, [r4, #0] + 8010b6e: 7019 strb r1, [r3, #0] + 8010b70: 3501 adds r5, #1 + 8010b72: e7eb b.n 8010b4c <_fwrite_r+0x38> + 8010b74: 4621 mov r1, r4 + 8010b76: 4630 mov r0, r6 + 8010b78: f000 f91c bl 8010db4 <__swsetup_r> + 8010b7c: 2800 cmp r0, #0 + 8010b7e: d0e4 beq.n 8010b4a <_fwrite_r+0x36> + 8010b80: 2500 movs r5, #0 + 8010b82: e005 b.n 8010b90 <_fwrite_r+0x7c> + 8010b84: 4622 mov r2, r4 + 8010b86: 4630 mov r0, r6 + 8010b88: f000 f8d7 bl 8010d3a <__swbuf_r> + 8010b8c: 3001 adds r0, #1 + 8010b8e: d1ef bne.n 8010b70 <_fwrite_r+0x5c> + 8010b90: 6e63 ldr r3, [r4, #100] ; 0x64 + 8010b92: 07da lsls r2, r3, #31 + 8010b94: d405 bmi.n 8010ba2 <_fwrite_r+0x8e> + 8010b96: 89a3 ldrh r3, [r4, #12] + 8010b98: 059b lsls r3, r3, #22 + 8010b9a: d402 bmi.n 8010ba2 <_fwrite_r+0x8e> + 8010b9c: 6da0 ldr r0, [r4, #88] ; 0x58 + 8010b9e: f000 f9f3 bl 8010f88 <__retarget_lock_release_recursive> + 8010ba2: fbb5 f0f8 udiv r0, r5, r8 + 8010ba6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + ... + +08010bac : + 8010bac: b507 push {r0, r1, r2, lr} + 8010bae: 9300 str r3, [sp, #0] + 8010bb0: 4613 mov r3, r2 + 8010bb2: 460a mov r2, r1 + 8010bb4: 4601 mov r1, r0 + 8010bb6: 4803 ldr r0, [pc, #12] ; (8010bc4 ) + 8010bb8: 6800 ldr r0, [r0, #0] + 8010bba: f7ff ffab bl 8010b14 <_fwrite_r> + 8010bbe: b003 add sp, #12 + 8010bc0: f85d fb04 ldr.w pc, [sp], #4 + 8010bc4: 240000cc .word 0x240000cc + +08010bc8 : + 8010bc8: b40f push {r0, r1, r2, r3} + 8010bca: b507 push {r0, r1, r2, lr} + 8010bcc: 4906 ldr r1, [pc, #24] ; (8010be8 ) + 8010bce: ab04 add r3, sp, #16 + 8010bd0: 6808 ldr r0, [r1, #0] + 8010bd2: f853 2b04 ldr.w r2, [r3], #4 + 8010bd6: 6881 ldr r1, [r0, #8] + 8010bd8: 9301 str r3, [sp, #4] + 8010bda: f7ff fc25 bl 8010428 <_vfiprintf_r> + 8010bde: b003 add sp, #12 + 8010be0: f85d eb04 ldr.w lr, [sp], #4 + 8010be4: b004 add sp, #16 + 8010be6: 4770 bx lr + 8010be8: 240000cc .word 0x240000cc + +08010bec : + 8010bec: 4b02 ldr r3, [pc, #8] ; (8010bf8 ) + 8010bee: 4601 mov r1, r0 + 8010bf0: 6818 ldr r0, [r3, #0] + 8010bf2: 6882 ldr r2, [r0, #8] + 8010bf4: f000 bc18 b.w 8011428 <_putc_r> + 8010bf8: 240000cc .word 0x240000cc + +08010bfc <_puts_r>: + 8010bfc: 6a03 ldr r3, [r0, #32] + 8010bfe: b570 push {r4, r5, r6, lr} + 8010c00: 6884 ldr r4, [r0, #8] + 8010c02: 4605 mov r5, r0 + 8010c04: 460e mov r6, r1 + 8010c06: b90b cbnz r3, 8010c0c <_puts_r+0x10> + 8010c08: f7ff ff4e bl 8010aa8 <__sinit> + 8010c0c: 6e63 ldr r3, [r4, #100] ; 0x64 + 8010c0e: 07db lsls r3, r3, #31 + 8010c10: d405 bmi.n 8010c1e <_puts_r+0x22> + 8010c12: 89a3 ldrh r3, [r4, #12] + 8010c14: 0598 lsls r0, r3, #22 + 8010c16: d402 bmi.n 8010c1e <_puts_r+0x22> + 8010c18: 6da0 ldr r0, [r4, #88] ; 0x58 + 8010c1a: f000 f9b4 bl 8010f86 <__retarget_lock_acquire_recursive> + 8010c1e: 89a3 ldrh r3, [r4, #12] + 8010c20: 0719 lsls r1, r3, #28 + 8010c22: d513 bpl.n 8010c4c <_puts_r+0x50> + 8010c24: 6923 ldr r3, [r4, #16] + 8010c26: b18b cbz r3, 8010c4c <_puts_r+0x50> + 8010c28: 3e01 subs r6, #1 + 8010c2a: 68a3 ldr r3, [r4, #8] + 8010c2c: f816 1f01 ldrb.w r1, [r6, #1]! + 8010c30: 3b01 subs r3, #1 + 8010c32: 60a3 str r3, [r4, #8] + 8010c34: b9e9 cbnz r1, 8010c72 <_puts_r+0x76> + 8010c36: 2b00 cmp r3, #0 + 8010c38: da2e bge.n 8010c98 <_puts_r+0x9c> + 8010c3a: 4622 mov r2, r4 + 8010c3c: 210a movs r1, #10 + 8010c3e: 4628 mov r0, r5 + 8010c40: f000 f87b bl 8010d3a <__swbuf_r> + 8010c44: 3001 adds r0, #1 + 8010c46: d007 beq.n 8010c58 <_puts_r+0x5c> + 8010c48: 250a movs r5, #10 + 8010c4a: e007 b.n 8010c5c <_puts_r+0x60> + 8010c4c: 4621 mov r1, r4 + 8010c4e: 4628 mov r0, r5 + 8010c50: f000 f8b0 bl 8010db4 <__swsetup_r> + 8010c54: 2800 cmp r0, #0 + 8010c56: d0e7 beq.n 8010c28 <_puts_r+0x2c> + 8010c58: f04f 35ff mov.w r5, #4294967295 + 8010c5c: 6e63 ldr r3, [r4, #100] ; 0x64 + 8010c5e: 07da lsls r2, r3, #31 + 8010c60: d405 bmi.n 8010c6e <_puts_r+0x72> + 8010c62: 89a3 ldrh r3, [r4, #12] + 8010c64: 059b lsls r3, r3, #22 + 8010c66: d402 bmi.n 8010c6e <_puts_r+0x72> + 8010c68: 6da0 ldr r0, [r4, #88] ; 0x58 + 8010c6a: f000 f98d bl 8010f88 <__retarget_lock_release_recursive> + 8010c6e: 4628 mov r0, r5 + 8010c70: bd70 pop {r4, r5, r6, pc} + 8010c72: 2b00 cmp r3, #0 + 8010c74: da04 bge.n 8010c80 <_puts_r+0x84> + 8010c76: 69a2 ldr r2, [r4, #24] + 8010c78: 429a cmp r2, r3 + 8010c7a: dc06 bgt.n 8010c8a <_puts_r+0x8e> + 8010c7c: 290a cmp r1, #10 + 8010c7e: d004 beq.n 8010c8a <_puts_r+0x8e> + 8010c80: 6823 ldr r3, [r4, #0] + 8010c82: 1c5a adds r2, r3, #1 + 8010c84: 6022 str r2, [r4, #0] + 8010c86: 7019 strb r1, [r3, #0] + 8010c88: e7cf b.n 8010c2a <_puts_r+0x2e> + 8010c8a: 4622 mov r2, r4 + 8010c8c: 4628 mov r0, r5 + 8010c8e: f000 f854 bl 8010d3a <__swbuf_r> + 8010c92: 3001 adds r0, #1 + 8010c94: d1c9 bne.n 8010c2a <_puts_r+0x2e> + 8010c96: e7df b.n 8010c58 <_puts_r+0x5c> + 8010c98: 6823 ldr r3, [r4, #0] + 8010c9a: 250a movs r5, #10 + 8010c9c: 1c5a adds r2, r3, #1 + 8010c9e: 6022 str r2, [r4, #0] + 8010ca0: 701d strb r5, [r3, #0] + 8010ca2: e7db b.n 8010c5c <_puts_r+0x60> + +08010ca4 : + 8010ca4: 4b02 ldr r3, [pc, #8] ; (8010cb0 ) + 8010ca6: 4601 mov r1, r0 + 8010ca8: 6818 ldr r0, [r3, #0] + 8010caa: f7ff bfa7 b.w 8010bfc <_puts_r> + 8010cae: bf00 nop + 8010cb0: 240000cc .word 0x240000cc + +08010cb4 <__sread>: + 8010cb4: b510 push {r4, lr} + 8010cb6: 460c mov r4, r1 + 8010cb8: f9b1 100e ldrsh.w r1, [r1, #14] + 8010cbc: f000 f91a bl 8010ef4 <_read_r> + 8010cc0: 2800 cmp r0, #0 + 8010cc2: bfab itete ge + 8010cc4: 6d63 ldrge r3, [r4, #84] ; 0x54 + 8010cc6: 89a3 ldrhlt r3, [r4, #12] + 8010cc8: 181b addge r3, r3, r0 + 8010cca: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 8010cce: bfac ite ge + 8010cd0: 6563 strge r3, [r4, #84] ; 0x54 + 8010cd2: 81a3 strhlt r3, [r4, #12] + 8010cd4: bd10 pop {r4, pc} + +08010cd6 <__swrite>: + 8010cd6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8010cda: 461f mov r7, r3 + 8010cdc: 898b ldrh r3, [r1, #12] + 8010cde: 05db lsls r3, r3, #23 + 8010ce0: 4605 mov r5, r0 + 8010ce2: 460c mov r4, r1 + 8010ce4: 4616 mov r6, r2 + 8010ce6: d505 bpl.n 8010cf4 <__swrite+0x1e> + 8010ce8: f9b1 100e ldrsh.w r1, [r1, #14] + 8010cec: 2302 movs r3, #2 + 8010cee: 2200 movs r2, #0 + 8010cf0: f000 f8ee bl 8010ed0 <_lseek_r> + 8010cf4: 89a3 ldrh r3, [r4, #12] + 8010cf6: f9b4 100e ldrsh.w r1, [r4, #14] + 8010cfa: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8010cfe: 81a3 strh r3, [r4, #12] + 8010d00: 4632 mov r2, r6 + 8010d02: 463b mov r3, r7 + 8010d04: 4628 mov r0, r5 + 8010d06: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 8010d0a: f000 b905 b.w 8010f18 <_write_r> + +08010d0e <__sseek>: + 8010d0e: b510 push {r4, lr} + 8010d10: 460c mov r4, r1 + 8010d12: f9b1 100e ldrsh.w r1, [r1, #14] + 8010d16: f000 f8db bl 8010ed0 <_lseek_r> + 8010d1a: 1c43 adds r3, r0, #1 + 8010d1c: 89a3 ldrh r3, [r4, #12] + 8010d1e: bf15 itete ne + 8010d20: 6560 strne r0, [r4, #84] ; 0x54 + 8010d22: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 8010d26: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 8010d2a: 81a3 strheq r3, [r4, #12] + 8010d2c: bf18 it ne + 8010d2e: 81a3 strhne r3, [r4, #12] + 8010d30: bd10 pop {r4, pc} + +08010d32 <__sclose>: + 8010d32: f9b1 100e ldrsh.w r1, [r1, #14] + 8010d36: f000 b8bb b.w 8010eb0 <_close_r> + +08010d3a <__swbuf_r>: + 8010d3a: b5f8 push {r3, r4, r5, r6, r7, lr} + 8010d3c: 460e mov r6, r1 + 8010d3e: 4614 mov r4, r2 + 8010d40: 4605 mov r5, r0 + 8010d42: b118 cbz r0, 8010d4c <__swbuf_r+0x12> + 8010d44: 6a03 ldr r3, [r0, #32] + 8010d46: b90b cbnz r3, 8010d4c <__swbuf_r+0x12> + 8010d48: f7ff feae bl 8010aa8 <__sinit> + 8010d4c: 69a3 ldr r3, [r4, #24] + 8010d4e: 60a3 str r3, [r4, #8] + 8010d50: 89a3 ldrh r3, [r4, #12] + 8010d52: 071a lsls r2, r3, #28 + 8010d54: d525 bpl.n 8010da2 <__swbuf_r+0x68> + 8010d56: 6923 ldr r3, [r4, #16] + 8010d58: b31b cbz r3, 8010da2 <__swbuf_r+0x68> + 8010d5a: 6823 ldr r3, [r4, #0] + 8010d5c: 6922 ldr r2, [r4, #16] + 8010d5e: 1a98 subs r0, r3, r2 + 8010d60: 6963 ldr r3, [r4, #20] + 8010d62: b2f6 uxtb r6, r6 + 8010d64: 4283 cmp r3, r0 + 8010d66: 4637 mov r7, r6 + 8010d68: dc04 bgt.n 8010d74 <__swbuf_r+0x3a> + 8010d6a: 4621 mov r1, r4 + 8010d6c: 4628 mov r0, r5 + 8010d6e: f000 fabf bl 80112f0 <_fflush_r> + 8010d72: b9e0 cbnz r0, 8010dae <__swbuf_r+0x74> + 8010d74: 68a3 ldr r3, [r4, #8] + 8010d76: 3b01 subs r3, #1 + 8010d78: 60a3 str r3, [r4, #8] + 8010d7a: 6823 ldr r3, [r4, #0] + 8010d7c: 1c5a adds r2, r3, #1 + 8010d7e: 6022 str r2, [r4, #0] + 8010d80: 701e strb r6, [r3, #0] + 8010d82: 6962 ldr r2, [r4, #20] + 8010d84: 1c43 adds r3, r0, #1 + 8010d86: 429a cmp r2, r3 + 8010d88: d004 beq.n 8010d94 <__swbuf_r+0x5a> + 8010d8a: 89a3 ldrh r3, [r4, #12] + 8010d8c: 07db lsls r3, r3, #31 + 8010d8e: d506 bpl.n 8010d9e <__swbuf_r+0x64> + 8010d90: 2e0a cmp r6, #10 + 8010d92: d104 bne.n 8010d9e <__swbuf_r+0x64> + 8010d94: 4621 mov r1, r4 + 8010d96: 4628 mov r0, r5 + 8010d98: f000 faaa bl 80112f0 <_fflush_r> + 8010d9c: b938 cbnz r0, 8010dae <__swbuf_r+0x74> + 8010d9e: 4638 mov r0, r7 + 8010da0: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8010da2: 4621 mov r1, r4 + 8010da4: 4628 mov r0, r5 + 8010da6: f000 f805 bl 8010db4 <__swsetup_r> + 8010daa: 2800 cmp r0, #0 + 8010dac: d0d5 beq.n 8010d5a <__swbuf_r+0x20> + 8010dae: f04f 37ff mov.w r7, #4294967295 + 8010db2: e7f4 b.n 8010d9e <__swbuf_r+0x64> + +08010db4 <__swsetup_r>: + 8010db4: b538 push {r3, r4, r5, lr} + 8010db6: 4b2a ldr r3, [pc, #168] ; (8010e60 <__swsetup_r+0xac>) + 8010db8: 4605 mov r5, r0 + 8010dba: 6818 ldr r0, [r3, #0] + 8010dbc: 460c mov r4, r1 + 8010dbe: b118 cbz r0, 8010dc8 <__swsetup_r+0x14> + 8010dc0: 6a03 ldr r3, [r0, #32] + 8010dc2: b90b cbnz r3, 8010dc8 <__swsetup_r+0x14> + 8010dc4: f7ff fe70 bl 8010aa8 <__sinit> + 8010dc8: 89a3 ldrh r3, [r4, #12] + 8010dca: f9b4 200c ldrsh.w r2, [r4, #12] + 8010dce: 0718 lsls r0, r3, #28 + 8010dd0: d422 bmi.n 8010e18 <__swsetup_r+0x64> + 8010dd2: 06d9 lsls r1, r3, #27 + 8010dd4: d407 bmi.n 8010de6 <__swsetup_r+0x32> + 8010dd6: 2309 movs r3, #9 + 8010dd8: 602b str r3, [r5, #0] + 8010dda: f042 0340 orr.w r3, r2, #64 ; 0x40 + 8010dde: 81a3 strh r3, [r4, #12] + 8010de0: f04f 30ff mov.w r0, #4294967295 + 8010de4: e034 b.n 8010e50 <__swsetup_r+0x9c> + 8010de6: 0758 lsls r0, r3, #29 + 8010de8: d512 bpl.n 8010e10 <__swsetup_r+0x5c> + 8010dea: 6b61 ldr r1, [r4, #52] ; 0x34 + 8010dec: b141 cbz r1, 8010e00 <__swsetup_r+0x4c> + 8010dee: f104 0344 add.w r3, r4, #68 ; 0x44 + 8010df2: 4299 cmp r1, r3 + 8010df4: d002 beq.n 8010dfc <__swsetup_r+0x48> + 8010df6: 4628 mov r0, r5 + 8010df8: f000 f8f4 bl 8010fe4 <_free_r> + 8010dfc: 2300 movs r3, #0 + 8010dfe: 6363 str r3, [r4, #52] ; 0x34 + 8010e00: 89a3 ldrh r3, [r4, #12] + 8010e02: f023 0324 bic.w r3, r3, #36 ; 0x24 + 8010e06: 81a3 strh r3, [r4, #12] + 8010e08: 2300 movs r3, #0 + 8010e0a: 6063 str r3, [r4, #4] + 8010e0c: 6923 ldr r3, [r4, #16] + 8010e0e: 6023 str r3, [r4, #0] + 8010e10: 89a3 ldrh r3, [r4, #12] + 8010e12: f043 0308 orr.w r3, r3, #8 + 8010e16: 81a3 strh r3, [r4, #12] + 8010e18: 6923 ldr r3, [r4, #16] + 8010e1a: b94b cbnz r3, 8010e30 <__swsetup_r+0x7c> + 8010e1c: 89a3 ldrh r3, [r4, #12] + 8010e1e: f403 7320 and.w r3, r3, #640 ; 0x280 + 8010e22: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8010e26: d003 beq.n 8010e30 <__swsetup_r+0x7c> + 8010e28: 4621 mov r1, r4 + 8010e2a: 4628 mov r0, r5 + 8010e2c: f000 fac0 bl 80113b0 <__smakebuf_r> + 8010e30: 89a0 ldrh r0, [r4, #12] + 8010e32: f9b4 200c ldrsh.w r2, [r4, #12] + 8010e36: f010 0301 ands.w r3, r0, #1 + 8010e3a: d00a beq.n 8010e52 <__swsetup_r+0x9e> + 8010e3c: 2300 movs r3, #0 + 8010e3e: 60a3 str r3, [r4, #8] + 8010e40: 6963 ldr r3, [r4, #20] + 8010e42: 425b negs r3, r3 + 8010e44: 61a3 str r3, [r4, #24] + 8010e46: 6923 ldr r3, [r4, #16] + 8010e48: b943 cbnz r3, 8010e5c <__swsetup_r+0xa8> + 8010e4a: f010 0080 ands.w r0, r0, #128 ; 0x80 + 8010e4e: d1c4 bne.n 8010dda <__swsetup_r+0x26> + 8010e50: bd38 pop {r3, r4, r5, pc} + 8010e52: 0781 lsls r1, r0, #30 + 8010e54: bf58 it pl + 8010e56: 6963 ldrpl r3, [r4, #20] + 8010e58: 60a3 str r3, [r4, #8] + 8010e5a: e7f4 b.n 8010e46 <__swsetup_r+0x92> + 8010e5c: 2000 movs r0, #0 + 8010e5e: e7f7 b.n 8010e50 <__swsetup_r+0x9c> + 8010e60: 240000cc .word 0x240000cc + +08010e64 : + 8010e64: b510 push {r4, lr} + 8010e66: 3901 subs r1, #1 + 8010e68: 4402 add r2, r0 + 8010e6a: 4290 cmp r0, r2 + 8010e6c: d101 bne.n 8010e72 + 8010e6e: 2000 movs r0, #0 + 8010e70: e005 b.n 8010e7e + 8010e72: 7803 ldrb r3, [r0, #0] + 8010e74: f811 4f01 ldrb.w r4, [r1, #1]! + 8010e78: 42a3 cmp r3, r4 + 8010e7a: d001 beq.n 8010e80 + 8010e7c: 1b18 subs r0, r3, r4 + 8010e7e: bd10 pop {r4, pc} + 8010e80: 3001 adds r0, #1 + 8010e82: e7f2 b.n 8010e6a + +08010e84 : + 8010e84: 4402 add r2, r0 + 8010e86: 4603 mov r3, r0 + 8010e88: 4293 cmp r3, r2 + 8010e8a: d100 bne.n 8010e8e + 8010e8c: 4770 bx lr + 8010e8e: f803 1b01 strb.w r1, [r3], #1 + 8010e92: e7f9 b.n 8010e88 + +08010e94 : + 8010e94: b2c9 uxtb r1, r1 + 8010e96: 4603 mov r3, r0 + 8010e98: f810 2b01 ldrb.w r2, [r0], #1 + 8010e9c: b11a cbz r2, 8010ea6 + 8010e9e: 428a cmp r2, r1 + 8010ea0: d1f9 bne.n 8010e96 + 8010ea2: 4618 mov r0, r3 + 8010ea4: 4770 bx lr + 8010ea6: 2900 cmp r1, #0 + 8010ea8: bf18 it ne + 8010eaa: 2300 movne r3, #0 + 8010eac: e7f9 b.n 8010ea2 + ... + +08010eb0 <_close_r>: + 8010eb0: b538 push {r3, r4, r5, lr} + 8010eb2: 4d06 ldr r5, [pc, #24] ; (8010ecc <_close_r+0x1c>) + 8010eb4: 2300 movs r3, #0 + 8010eb6: 4604 mov r4, r0 + 8010eb8: 4608 mov r0, r1 + 8010eba: 602b str r3, [r5, #0] + 8010ebc: f7ef fda1 bl 8000a02 <_close> + 8010ec0: 1c43 adds r3, r0, #1 + 8010ec2: d102 bne.n 8010eca <_close_r+0x1a> + 8010ec4: 682b ldr r3, [r5, #0] + 8010ec6: b103 cbz r3, 8010eca <_close_r+0x1a> + 8010ec8: 6023 str r3, [r4, #0] + 8010eca: bd38 pop {r3, r4, r5, pc} + 8010ecc: 24007e08 .word 0x24007e08 + +08010ed0 <_lseek_r>: + 8010ed0: b538 push {r3, r4, r5, lr} + 8010ed2: 4d07 ldr r5, [pc, #28] ; (8010ef0 <_lseek_r+0x20>) + 8010ed4: 4604 mov r4, r0 + 8010ed6: 4608 mov r0, r1 + 8010ed8: 4611 mov r1, r2 + 8010eda: 2200 movs r2, #0 + 8010edc: 602a str r2, [r5, #0] + 8010ede: 461a mov r2, r3 + 8010ee0: f7ef fdb6 bl 8000a50 <_lseek> + 8010ee4: 1c43 adds r3, r0, #1 + 8010ee6: d102 bne.n 8010eee <_lseek_r+0x1e> + 8010ee8: 682b ldr r3, [r5, #0] + 8010eea: b103 cbz r3, 8010eee <_lseek_r+0x1e> + 8010eec: 6023 str r3, [r4, #0] + 8010eee: bd38 pop {r3, r4, r5, pc} + 8010ef0: 24007e08 .word 0x24007e08 + +08010ef4 <_read_r>: + 8010ef4: b538 push {r3, r4, r5, lr} + 8010ef6: 4d07 ldr r5, [pc, #28] ; (8010f14 <_read_r+0x20>) + 8010ef8: 4604 mov r4, r0 + 8010efa: 4608 mov r0, r1 + 8010efc: 4611 mov r1, r2 + 8010efe: 2200 movs r2, #0 + 8010f00: 602a str r2, [r5, #0] + 8010f02: 461a mov r2, r3 + 8010f04: f7ef fd60 bl 80009c8 <_read> + 8010f08: 1c43 adds r3, r0, #1 + 8010f0a: d102 bne.n 8010f12 <_read_r+0x1e> + 8010f0c: 682b ldr r3, [r5, #0] + 8010f0e: b103 cbz r3, 8010f12 <_read_r+0x1e> + 8010f10: 6023 str r3, [r4, #0] + 8010f12: bd38 pop {r3, r4, r5, pc} + 8010f14: 24007e08 .word 0x24007e08 + +08010f18 <_write_r>: + 8010f18: b538 push {r3, r4, r5, lr} + 8010f1a: 4d07 ldr r5, [pc, #28] ; (8010f38 <_write_r+0x20>) + 8010f1c: 4604 mov r4, r0 + 8010f1e: 4608 mov r0, r1 + 8010f20: 4611 mov r1, r2 + 8010f22: 2200 movs r2, #0 + 8010f24: 602a str r2, [r5, #0] + 8010f26: 461a mov r2, r3 + 8010f28: f7ef fa71 bl 800040e <_write> + 8010f2c: 1c43 adds r3, r0, #1 + 8010f2e: d102 bne.n 8010f36 <_write_r+0x1e> + 8010f30: 682b ldr r3, [r5, #0] + 8010f32: b103 cbz r3, 8010f36 <_write_r+0x1e> + 8010f34: 6023 str r3, [r4, #0] + 8010f36: bd38 pop {r3, r4, r5, pc} + 8010f38: 24007e08 .word 0x24007e08 + +08010f3c <__libc_init_array>: + 8010f3c: b570 push {r4, r5, r6, lr} + 8010f3e: 4d0d ldr r5, [pc, #52] ; (8010f74 <__libc_init_array+0x38>) + 8010f40: 4c0d ldr r4, [pc, #52] ; (8010f78 <__libc_init_array+0x3c>) + 8010f42: 1b64 subs r4, r4, r5 + 8010f44: 10a4 asrs r4, r4, #2 + 8010f46: 2600 movs r6, #0 + 8010f48: 42a6 cmp r6, r4 + 8010f4a: d109 bne.n 8010f60 <__libc_init_array+0x24> + 8010f4c: 4d0b ldr r5, [pc, #44] ; (8010f7c <__libc_init_array+0x40>) + 8010f4e: 4c0c ldr r4, [pc, #48] ; (8010f80 <__libc_init_array+0x44>) + 8010f50: f000 fb1c bl 801158c <_init> + 8010f54: 1b64 subs r4, r4, r5 + 8010f56: 10a4 asrs r4, r4, #2 + 8010f58: 2600 movs r6, #0 + 8010f5a: 42a6 cmp r6, r4 + 8010f5c: d105 bne.n 8010f6a <__libc_init_array+0x2e> + 8010f5e: bd70 pop {r4, r5, r6, pc} + 8010f60: f855 3b04 ldr.w r3, [r5], #4 + 8010f64: 4798 blx r3 + 8010f66: 3601 adds r6, #1 + 8010f68: e7ee b.n 8010f48 <__libc_init_array+0xc> + 8010f6a: f855 3b04 ldr.w r3, [r5], #4 + 8010f6e: 4798 blx r3 + 8010f70: 3601 adds r6, #1 + 8010f72: e7f2 b.n 8010f5a <__libc_init_array+0x1e> + 8010f74: 08014f88 .word 0x08014f88 + 8010f78: 08014f88 .word 0x08014f88 + 8010f7c: 08014f88 .word 0x08014f88 + 8010f80: 08014f8c .word 0x08014f8c + +08010f84 <__retarget_lock_init_recursive>: + 8010f84: 4770 bx lr + +08010f86 <__retarget_lock_acquire_recursive>: + 8010f86: 4770 bx lr + +08010f88 <__retarget_lock_release_recursive>: + 8010f88: 4770 bx lr + +08010f8a : + 8010f8a: 440a add r2, r1 + 8010f8c: 4291 cmp r1, r2 + 8010f8e: f100 33ff add.w r3, r0, #4294967295 + 8010f92: d100 bne.n 8010f96 + 8010f94: 4770 bx lr + 8010f96: b510 push {r4, lr} + 8010f98: f811 4b01 ldrb.w r4, [r1], #1 + 8010f9c: f803 4f01 strb.w r4, [r3, #1]! + 8010fa0: 4291 cmp r1, r2 + 8010fa2: d1f9 bne.n 8010f98 + 8010fa4: bd10 pop {r4, pc} + ... + +08010fa8 <__assert_func>: + 8010fa8: b51f push {r0, r1, r2, r3, r4, lr} + 8010faa: 4614 mov r4, r2 + 8010fac: 461a mov r2, r3 + 8010fae: 4b09 ldr r3, [pc, #36] ; (8010fd4 <__assert_func+0x2c>) + 8010fb0: 681b ldr r3, [r3, #0] + 8010fb2: 4605 mov r5, r0 + 8010fb4: 68d8 ldr r0, [r3, #12] + 8010fb6: b14c cbz r4, 8010fcc <__assert_func+0x24> + 8010fb8: 4b07 ldr r3, [pc, #28] ; (8010fd8 <__assert_func+0x30>) + 8010fba: 9100 str r1, [sp, #0] + 8010fbc: e9cd 3401 strd r3, r4, [sp, #4] + 8010fc0: 4906 ldr r1, [pc, #24] ; (8010fdc <__assert_func+0x34>) + 8010fc2: 462b mov r3, r5 + 8010fc4: f000 f9bc bl 8011340 + 8010fc8: f000 fa94 bl 80114f4 + 8010fcc: 4b04 ldr r3, [pc, #16] ; (8010fe0 <__assert_func+0x38>) + 8010fce: 461c mov r4, r3 + 8010fd0: e7f3 b.n 8010fba <__assert_func+0x12> + 8010fd2: bf00 nop + 8010fd4: 240000cc .word 0x240000cc + 8010fd8: 08014f49 .word 0x08014f49 + 8010fdc: 08014f56 .word 0x08014f56 + 8010fe0: 08014f84 .word 0x08014f84 + +08010fe4 <_free_r>: + 8010fe4: b537 push {r0, r1, r2, r4, r5, lr} + 8010fe6: 2900 cmp r1, #0 + 8010fe8: d044 beq.n 8011074 <_free_r+0x90> + 8010fea: f851 3c04 ldr.w r3, [r1, #-4] + 8010fee: 9001 str r0, [sp, #4] + 8010ff0: 2b00 cmp r3, #0 + 8010ff2: f1a1 0404 sub.w r4, r1, #4 + 8010ff6: bfb8 it lt + 8010ff8: 18e4 addlt r4, r4, r3 + 8010ffa: f000 f8e7 bl 80111cc <__malloc_lock> + 8010ffe: 4a1e ldr r2, [pc, #120] ; (8011078 <_free_r+0x94>) + 8011000: 9801 ldr r0, [sp, #4] + 8011002: 6813 ldr r3, [r2, #0] + 8011004: b933 cbnz r3, 8011014 <_free_r+0x30> + 8011006: 6063 str r3, [r4, #4] + 8011008: 6014 str r4, [r2, #0] + 801100a: b003 add sp, #12 + 801100c: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 8011010: f000 b8e2 b.w 80111d8 <__malloc_unlock> + 8011014: 42a3 cmp r3, r4 + 8011016: d908 bls.n 801102a <_free_r+0x46> + 8011018: 6825 ldr r5, [r4, #0] + 801101a: 1961 adds r1, r4, r5 + 801101c: 428b cmp r3, r1 + 801101e: bf01 itttt eq + 8011020: 6819 ldreq r1, [r3, #0] + 8011022: 685b ldreq r3, [r3, #4] + 8011024: 1949 addeq r1, r1, r5 + 8011026: 6021 streq r1, [r4, #0] + 8011028: e7ed b.n 8011006 <_free_r+0x22> + 801102a: 461a mov r2, r3 + 801102c: 685b ldr r3, [r3, #4] + 801102e: b10b cbz r3, 8011034 <_free_r+0x50> + 8011030: 42a3 cmp r3, r4 + 8011032: d9fa bls.n 801102a <_free_r+0x46> + 8011034: 6811 ldr r1, [r2, #0] + 8011036: 1855 adds r5, r2, r1 + 8011038: 42a5 cmp r5, r4 + 801103a: d10b bne.n 8011054 <_free_r+0x70> + 801103c: 6824 ldr r4, [r4, #0] + 801103e: 4421 add r1, r4 + 8011040: 1854 adds r4, r2, r1 + 8011042: 42a3 cmp r3, r4 + 8011044: 6011 str r1, [r2, #0] + 8011046: d1e0 bne.n 801100a <_free_r+0x26> + 8011048: 681c ldr r4, [r3, #0] + 801104a: 685b ldr r3, [r3, #4] + 801104c: 6053 str r3, [r2, #4] + 801104e: 440c add r4, r1 + 8011050: 6014 str r4, [r2, #0] + 8011052: e7da b.n 801100a <_free_r+0x26> + 8011054: d902 bls.n 801105c <_free_r+0x78> + 8011056: 230c movs r3, #12 + 8011058: 6003 str r3, [r0, #0] + 801105a: e7d6 b.n 801100a <_free_r+0x26> + 801105c: 6825 ldr r5, [r4, #0] + 801105e: 1961 adds r1, r4, r5 + 8011060: 428b cmp r3, r1 + 8011062: bf04 itt eq + 8011064: 6819 ldreq r1, [r3, #0] + 8011066: 685b ldreq r3, [r3, #4] + 8011068: 6063 str r3, [r4, #4] + 801106a: bf04 itt eq + 801106c: 1949 addeq r1, r1, r5 + 801106e: 6021 streq r1, [r4, #0] + 8011070: 6054 str r4, [r2, #4] + 8011072: e7ca b.n 801100a <_free_r+0x26> + 8011074: b003 add sp, #12 + 8011076: bd30 pop {r4, r5, pc} + 8011078: 24007e10 .word 0x24007e10 + +0801107c : + 801107c: 4b02 ldr r3, [pc, #8] ; (8011088 ) + 801107e: 4601 mov r1, r0 + 8011080: 6818 ldr r0, [r3, #0] + 8011082: f000 b823 b.w 80110cc <_malloc_r> + 8011086: bf00 nop + 8011088: 240000cc .word 0x240000cc + +0801108c : + 801108c: b570 push {r4, r5, r6, lr} + 801108e: 4e0e ldr r6, [pc, #56] ; (80110c8 ) + 8011090: 460c mov r4, r1 + 8011092: 6831 ldr r1, [r6, #0] + 8011094: 4605 mov r5, r0 + 8011096: b911 cbnz r1, 801109e + 8011098: f000 fa1c bl 80114d4 <_sbrk_r> + 801109c: 6030 str r0, [r6, #0] + 801109e: 4621 mov r1, r4 + 80110a0: 4628 mov r0, r5 + 80110a2: f000 fa17 bl 80114d4 <_sbrk_r> + 80110a6: 1c43 adds r3, r0, #1 + 80110a8: d00a beq.n 80110c0 + 80110aa: 1cc4 adds r4, r0, #3 + 80110ac: f024 0403 bic.w r4, r4, #3 + 80110b0: 42a0 cmp r0, r4 + 80110b2: d007 beq.n 80110c4 + 80110b4: 1a21 subs r1, r4, r0 + 80110b6: 4628 mov r0, r5 + 80110b8: f000 fa0c bl 80114d4 <_sbrk_r> + 80110bc: 3001 adds r0, #1 + 80110be: d101 bne.n 80110c4 + 80110c0: f04f 34ff mov.w r4, #4294967295 + 80110c4: 4620 mov r0, r4 + 80110c6: bd70 pop {r4, r5, r6, pc} + 80110c8: 24007e14 .word 0x24007e14 + +080110cc <_malloc_r>: + 80110cc: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 80110d0: 1ccd adds r5, r1, #3 + 80110d2: f025 0503 bic.w r5, r5, #3 + 80110d6: 3508 adds r5, #8 + 80110d8: 2d0c cmp r5, #12 + 80110da: bf38 it cc + 80110dc: 250c movcc r5, #12 + 80110de: 2d00 cmp r5, #0 + 80110e0: 4607 mov r7, r0 + 80110e2: db01 blt.n 80110e8 <_malloc_r+0x1c> + 80110e4: 42a9 cmp r1, r5 + 80110e6: d905 bls.n 80110f4 <_malloc_r+0x28> + 80110e8: 230c movs r3, #12 + 80110ea: 603b str r3, [r7, #0] + 80110ec: 2600 movs r6, #0 + 80110ee: 4630 mov r0, r6 + 80110f0: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 80110f4: f8df 80d0 ldr.w r8, [pc, #208] ; 80111c8 <_malloc_r+0xfc> + 80110f8: f000 f868 bl 80111cc <__malloc_lock> + 80110fc: f8d8 3000 ldr.w r3, [r8] + 8011100: 461c mov r4, r3 + 8011102: bb5c cbnz r4, 801115c <_malloc_r+0x90> + 8011104: 4629 mov r1, r5 + 8011106: 4638 mov r0, r7 + 8011108: f7ff ffc0 bl 801108c + 801110c: 1c43 adds r3, r0, #1 + 801110e: 4604 mov r4, r0 + 8011110: d155 bne.n 80111be <_malloc_r+0xf2> + 8011112: f8d8 4000 ldr.w r4, [r8] + 8011116: 4626 mov r6, r4 + 8011118: 2e00 cmp r6, #0 + 801111a: d145 bne.n 80111a8 <_malloc_r+0xdc> + 801111c: 2c00 cmp r4, #0 + 801111e: d048 beq.n 80111b2 <_malloc_r+0xe6> + 8011120: 6823 ldr r3, [r4, #0] + 8011122: 4631 mov r1, r6 + 8011124: 4638 mov r0, r7 + 8011126: eb04 0903 add.w r9, r4, r3 + 801112a: f000 f9d3 bl 80114d4 <_sbrk_r> + 801112e: 4581 cmp r9, r0 + 8011130: d13f bne.n 80111b2 <_malloc_r+0xe6> + 8011132: 6821 ldr r1, [r4, #0] + 8011134: 1a6d subs r5, r5, r1 + 8011136: 4629 mov r1, r5 + 8011138: 4638 mov r0, r7 + 801113a: f7ff ffa7 bl 801108c + 801113e: 3001 adds r0, #1 + 8011140: d037 beq.n 80111b2 <_malloc_r+0xe6> + 8011142: 6823 ldr r3, [r4, #0] + 8011144: 442b add r3, r5 + 8011146: 6023 str r3, [r4, #0] + 8011148: f8d8 3000 ldr.w r3, [r8] + 801114c: 2b00 cmp r3, #0 + 801114e: d038 beq.n 80111c2 <_malloc_r+0xf6> + 8011150: 685a ldr r2, [r3, #4] + 8011152: 42a2 cmp r2, r4 + 8011154: d12b bne.n 80111ae <_malloc_r+0xe2> + 8011156: 2200 movs r2, #0 + 8011158: 605a str r2, [r3, #4] + 801115a: e00f b.n 801117c <_malloc_r+0xb0> + 801115c: 6822 ldr r2, [r4, #0] + 801115e: 1b52 subs r2, r2, r5 + 8011160: d41f bmi.n 80111a2 <_malloc_r+0xd6> + 8011162: 2a0b cmp r2, #11 + 8011164: d917 bls.n 8011196 <_malloc_r+0xca> + 8011166: 1961 adds r1, r4, r5 + 8011168: 42a3 cmp r3, r4 + 801116a: 6025 str r5, [r4, #0] + 801116c: bf18 it ne + 801116e: 6059 strne r1, [r3, #4] + 8011170: 6863 ldr r3, [r4, #4] + 8011172: bf08 it eq + 8011174: f8c8 1000 streq.w r1, [r8] + 8011178: 5162 str r2, [r4, r5] + 801117a: 604b str r3, [r1, #4] + 801117c: 4638 mov r0, r7 + 801117e: f104 060b add.w r6, r4, #11 + 8011182: f000 f829 bl 80111d8 <__malloc_unlock> + 8011186: f026 0607 bic.w r6, r6, #7 + 801118a: 1d23 adds r3, r4, #4 + 801118c: 1af2 subs r2, r6, r3 + 801118e: d0ae beq.n 80110ee <_malloc_r+0x22> + 8011190: 1b9b subs r3, r3, r6 + 8011192: 50a3 str r3, [r4, r2] + 8011194: e7ab b.n 80110ee <_malloc_r+0x22> + 8011196: 42a3 cmp r3, r4 + 8011198: 6862 ldr r2, [r4, #4] + 801119a: d1dd bne.n 8011158 <_malloc_r+0x8c> + 801119c: f8c8 2000 str.w r2, [r8] + 80111a0: e7ec b.n 801117c <_malloc_r+0xb0> + 80111a2: 4623 mov r3, r4 + 80111a4: 6864 ldr r4, [r4, #4] + 80111a6: e7ac b.n 8011102 <_malloc_r+0x36> + 80111a8: 4634 mov r4, r6 + 80111aa: 6876 ldr r6, [r6, #4] + 80111ac: e7b4 b.n 8011118 <_malloc_r+0x4c> + 80111ae: 4613 mov r3, r2 + 80111b0: e7cc b.n 801114c <_malloc_r+0x80> + 80111b2: 230c movs r3, #12 + 80111b4: 603b str r3, [r7, #0] + 80111b6: 4638 mov r0, r7 + 80111b8: f000 f80e bl 80111d8 <__malloc_unlock> + 80111bc: e797 b.n 80110ee <_malloc_r+0x22> + 80111be: 6025 str r5, [r4, #0] + 80111c0: e7dc b.n 801117c <_malloc_r+0xb0> + 80111c2: 605b str r3, [r3, #4] + 80111c4: deff udf #255 ; 0xff + 80111c6: bf00 nop + 80111c8: 24007e10 .word 0x24007e10 + +080111cc <__malloc_lock>: + 80111cc: 4801 ldr r0, [pc, #4] ; (80111d4 <__malloc_lock+0x8>) + 80111ce: f7ff beda b.w 8010f86 <__retarget_lock_acquire_recursive> + 80111d2: bf00 nop + 80111d4: 24007e0c .word 0x24007e0c + +080111d8 <__malloc_unlock>: + 80111d8: 4801 ldr r0, [pc, #4] ; (80111e0 <__malloc_unlock+0x8>) + 80111da: f7ff bed5 b.w 8010f88 <__retarget_lock_release_recursive> + 80111de: bf00 nop + 80111e0: 24007e0c .word 0x24007e0c + +080111e4 <__sflush_r>: + 80111e4: 898a ldrh r2, [r1, #12] + 80111e6: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 80111ea: 4605 mov r5, r0 + 80111ec: 0710 lsls r0, r2, #28 + 80111ee: 460c mov r4, r1 + 80111f0: d458 bmi.n 80112a4 <__sflush_r+0xc0> + 80111f2: 684b ldr r3, [r1, #4] + 80111f4: 2b00 cmp r3, #0 + 80111f6: dc05 bgt.n 8011204 <__sflush_r+0x20> + 80111f8: 6c0b ldr r3, [r1, #64] ; 0x40 + 80111fa: 2b00 cmp r3, #0 + 80111fc: dc02 bgt.n 8011204 <__sflush_r+0x20> + 80111fe: 2000 movs r0, #0 + 8011200: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8011204: 6ae6 ldr r6, [r4, #44] ; 0x2c + 8011206: 2e00 cmp r6, #0 + 8011208: d0f9 beq.n 80111fe <__sflush_r+0x1a> + 801120a: 2300 movs r3, #0 + 801120c: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 8011210: 682f ldr r7, [r5, #0] + 8011212: 6a21 ldr r1, [r4, #32] + 8011214: 602b str r3, [r5, #0] + 8011216: d032 beq.n 801127e <__sflush_r+0x9a> + 8011218: 6d60 ldr r0, [r4, #84] ; 0x54 + 801121a: 89a3 ldrh r3, [r4, #12] + 801121c: 075a lsls r2, r3, #29 + 801121e: d505 bpl.n 801122c <__sflush_r+0x48> + 8011220: 6863 ldr r3, [r4, #4] + 8011222: 1ac0 subs r0, r0, r3 + 8011224: 6b63 ldr r3, [r4, #52] ; 0x34 + 8011226: b10b cbz r3, 801122c <__sflush_r+0x48> + 8011228: 6c23 ldr r3, [r4, #64] ; 0x40 + 801122a: 1ac0 subs r0, r0, r3 + 801122c: 2300 movs r3, #0 + 801122e: 4602 mov r2, r0 + 8011230: 6ae6 ldr r6, [r4, #44] ; 0x2c + 8011232: 6a21 ldr r1, [r4, #32] + 8011234: 4628 mov r0, r5 + 8011236: 47b0 blx r6 + 8011238: 1c43 adds r3, r0, #1 + 801123a: 89a3 ldrh r3, [r4, #12] + 801123c: d106 bne.n 801124c <__sflush_r+0x68> + 801123e: 6829 ldr r1, [r5, #0] + 8011240: 291d cmp r1, #29 + 8011242: d82b bhi.n 801129c <__sflush_r+0xb8> + 8011244: 4a29 ldr r2, [pc, #164] ; (80112ec <__sflush_r+0x108>) + 8011246: 410a asrs r2, r1 + 8011248: 07d6 lsls r6, r2, #31 + 801124a: d427 bmi.n 801129c <__sflush_r+0xb8> + 801124c: 2200 movs r2, #0 + 801124e: 6062 str r2, [r4, #4] + 8011250: 04d9 lsls r1, r3, #19 + 8011252: 6922 ldr r2, [r4, #16] + 8011254: 6022 str r2, [r4, #0] + 8011256: d504 bpl.n 8011262 <__sflush_r+0x7e> + 8011258: 1c42 adds r2, r0, #1 + 801125a: d101 bne.n 8011260 <__sflush_r+0x7c> + 801125c: 682b ldr r3, [r5, #0] + 801125e: b903 cbnz r3, 8011262 <__sflush_r+0x7e> + 8011260: 6560 str r0, [r4, #84] ; 0x54 + 8011262: 6b61 ldr r1, [r4, #52] ; 0x34 + 8011264: 602f str r7, [r5, #0] + 8011266: 2900 cmp r1, #0 + 8011268: d0c9 beq.n 80111fe <__sflush_r+0x1a> + 801126a: f104 0344 add.w r3, r4, #68 ; 0x44 + 801126e: 4299 cmp r1, r3 + 8011270: d002 beq.n 8011278 <__sflush_r+0x94> + 8011272: 4628 mov r0, r5 + 8011274: f7ff feb6 bl 8010fe4 <_free_r> + 8011278: 2000 movs r0, #0 + 801127a: 6360 str r0, [r4, #52] ; 0x34 + 801127c: e7c0 b.n 8011200 <__sflush_r+0x1c> + 801127e: 2301 movs r3, #1 + 8011280: 4628 mov r0, r5 + 8011282: 47b0 blx r6 + 8011284: 1c41 adds r1, r0, #1 + 8011286: d1c8 bne.n 801121a <__sflush_r+0x36> + 8011288: 682b ldr r3, [r5, #0] + 801128a: 2b00 cmp r3, #0 + 801128c: d0c5 beq.n 801121a <__sflush_r+0x36> + 801128e: 2b1d cmp r3, #29 + 8011290: d001 beq.n 8011296 <__sflush_r+0xb2> + 8011292: 2b16 cmp r3, #22 + 8011294: d101 bne.n 801129a <__sflush_r+0xb6> + 8011296: 602f str r7, [r5, #0] + 8011298: e7b1 b.n 80111fe <__sflush_r+0x1a> + 801129a: 89a3 ldrh r3, [r4, #12] + 801129c: f043 0340 orr.w r3, r3, #64 ; 0x40 + 80112a0: 81a3 strh r3, [r4, #12] + 80112a2: e7ad b.n 8011200 <__sflush_r+0x1c> + 80112a4: 690f ldr r7, [r1, #16] + 80112a6: 2f00 cmp r7, #0 + 80112a8: d0a9 beq.n 80111fe <__sflush_r+0x1a> + 80112aa: 0793 lsls r3, r2, #30 + 80112ac: 680e ldr r6, [r1, #0] + 80112ae: bf08 it eq + 80112b0: 694b ldreq r3, [r1, #20] + 80112b2: 600f str r7, [r1, #0] + 80112b4: bf18 it ne + 80112b6: 2300 movne r3, #0 + 80112b8: eba6 0807 sub.w r8, r6, r7 + 80112bc: 608b str r3, [r1, #8] + 80112be: f1b8 0f00 cmp.w r8, #0 + 80112c2: dd9c ble.n 80111fe <__sflush_r+0x1a> + 80112c4: 6a21 ldr r1, [r4, #32] + 80112c6: 6aa6 ldr r6, [r4, #40] ; 0x28 + 80112c8: 4643 mov r3, r8 + 80112ca: 463a mov r2, r7 + 80112cc: 4628 mov r0, r5 + 80112ce: 47b0 blx r6 + 80112d0: 2800 cmp r0, #0 + 80112d2: dc06 bgt.n 80112e2 <__sflush_r+0xfe> + 80112d4: 89a3 ldrh r3, [r4, #12] + 80112d6: f043 0340 orr.w r3, r3, #64 ; 0x40 + 80112da: 81a3 strh r3, [r4, #12] + 80112dc: f04f 30ff mov.w r0, #4294967295 + 80112e0: e78e b.n 8011200 <__sflush_r+0x1c> + 80112e2: 4407 add r7, r0 + 80112e4: eba8 0800 sub.w r8, r8, r0 + 80112e8: e7e9 b.n 80112be <__sflush_r+0xda> + 80112ea: bf00 nop + 80112ec: dfbffffe .word 0xdfbffffe + +080112f0 <_fflush_r>: + 80112f0: b538 push {r3, r4, r5, lr} + 80112f2: 690b ldr r3, [r1, #16] + 80112f4: 4605 mov r5, r0 + 80112f6: 460c mov r4, r1 + 80112f8: b913 cbnz r3, 8011300 <_fflush_r+0x10> + 80112fa: 2500 movs r5, #0 + 80112fc: 4628 mov r0, r5 + 80112fe: bd38 pop {r3, r4, r5, pc} + 8011300: b118 cbz r0, 801130a <_fflush_r+0x1a> + 8011302: 6a03 ldr r3, [r0, #32] + 8011304: b90b cbnz r3, 801130a <_fflush_r+0x1a> + 8011306: f7ff fbcf bl 8010aa8 <__sinit> + 801130a: f9b4 300c ldrsh.w r3, [r4, #12] + 801130e: 2b00 cmp r3, #0 + 8011310: d0f3 beq.n 80112fa <_fflush_r+0xa> + 8011312: 6e62 ldr r2, [r4, #100] ; 0x64 + 8011314: 07d0 lsls r0, r2, #31 + 8011316: d404 bmi.n 8011322 <_fflush_r+0x32> + 8011318: 0599 lsls r1, r3, #22 + 801131a: d402 bmi.n 8011322 <_fflush_r+0x32> + 801131c: 6da0 ldr r0, [r4, #88] ; 0x58 + 801131e: f7ff fe32 bl 8010f86 <__retarget_lock_acquire_recursive> + 8011322: 4628 mov r0, r5 + 8011324: 4621 mov r1, r4 + 8011326: f7ff ff5d bl 80111e4 <__sflush_r> + 801132a: 6e63 ldr r3, [r4, #100] ; 0x64 + 801132c: 07da lsls r2, r3, #31 + 801132e: 4605 mov r5, r0 + 8011330: d4e4 bmi.n 80112fc <_fflush_r+0xc> + 8011332: 89a3 ldrh r3, [r4, #12] + 8011334: 059b lsls r3, r3, #22 + 8011336: d4e1 bmi.n 80112fc <_fflush_r+0xc> + 8011338: 6da0 ldr r0, [r4, #88] ; 0x58 + 801133a: f7ff fe25 bl 8010f88 <__retarget_lock_release_recursive> + 801133e: e7dd b.n 80112fc <_fflush_r+0xc> + +08011340 : + 8011340: b40e push {r1, r2, r3} + 8011342: b503 push {r0, r1, lr} + 8011344: 4601 mov r1, r0 + 8011346: ab03 add r3, sp, #12 + 8011348: 4805 ldr r0, [pc, #20] ; (8011360 ) + 801134a: f853 2b04 ldr.w r2, [r3], #4 + 801134e: 6800 ldr r0, [r0, #0] + 8011350: 9301 str r3, [sp, #4] + 8011352: f7ff f869 bl 8010428 <_vfiprintf_r> + 8011356: b002 add sp, #8 + 8011358: f85d eb04 ldr.w lr, [sp], #4 + 801135c: b003 add sp, #12 + 801135e: 4770 bx lr + 8011360: 240000cc .word 0x240000cc + +08011364 <__swhatbuf_r>: + 8011364: b570 push {r4, r5, r6, lr} + 8011366: 460c mov r4, r1 + 8011368: f9b1 100e ldrsh.w r1, [r1, #14] + 801136c: 2900 cmp r1, #0 + 801136e: b096 sub sp, #88 ; 0x58 + 8011370: 4615 mov r5, r2 + 8011372: 461e mov r6, r3 + 8011374: da0d bge.n 8011392 <__swhatbuf_r+0x2e> + 8011376: 89a3 ldrh r3, [r4, #12] + 8011378: f013 0f80 tst.w r3, #128 ; 0x80 + 801137c: f04f 0100 mov.w r1, #0 + 8011380: bf0c ite eq + 8011382: f44f 6380 moveq.w r3, #1024 ; 0x400 + 8011386: 2340 movne r3, #64 ; 0x40 + 8011388: 2000 movs r0, #0 + 801138a: 6031 str r1, [r6, #0] + 801138c: 602b str r3, [r5, #0] + 801138e: b016 add sp, #88 ; 0x58 + 8011390: bd70 pop {r4, r5, r6, pc} + 8011392: 466a mov r2, sp + 8011394: f000 f87c bl 8011490 <_fstat_r> + 8011398: 2800 cmp r0, #0 + 801139a: dbec blt.n 8011376 <__swhatbuf_r+0x12> + 801139c: 9901 ldr r1, [sp, #4] + 801139e: f401 4170 and.w r1, r1, #61440 ; 0xf000 + 80113a2: f5a1 5300 sub.w r3, r1, #8192 ; 0x2000 + 80113a6: 4259 negs r1, r3 + 80113a8: 4159 adcs r1, r3 + 80113aa: f44f 6380 mov.w r3, #1024 ; 0x400 + 80113ae: e7eb b.n 8011388 <__swhatbuf_r+0x24> + +080113b0 <__smakebuf_r>: + 80113b0: 898b ldrh r3, [r1, #12] + 80113b2: b573 push {r0, r1, r4, r5, r6, lr} + 80113b4: 079d lsls r5, r3, #30 + 80113b6: 4606 mov r6, r0 + 80113b8: 460c mov r4, r1 + 80113ba: d507 bpl.n 80113cc <__smakebuf_r+0x1c> + 80113bc: f104 0347 add.w r3, r4, #71 ; 0x47 + 80113c0: 6023 str r3, [r4, #0] + 80113c2: 6123 str r3, [r4, #16] + 80113c4: 2301 movs r3, #1 + 80113c6: 6163 str r3, [r4, #20] + 80113c8: b002 add sp, #8 + 80113ca: bd70 pop {r4, r5, r6, pc} + 80113cc: ab01 add r3, sp, #4 + 80113ce: 466a mov r2, sp + 80113d0: f7ff ffc8 bl 8011364 <__swhatbuf_r> + 80113d4: 9900 ldr r1, [sp, #0] + 80113d6: 4605 mov r5, r0 + 80113d8: 4630 mov r0, r6 + 80113da: f7ff fe77 bl 80110cc <_malloc_r> + 80113de: b948 cbnz r0, 80113f4 <__smakebuf_r+0x44> + 80113e0: f9b4 300c ldrsh.w r3, [r4, #12] + 80113e4: 059a lsls r2, r3, #22 + 80113e6: d4ef bmi.n 80113c8 <__smakebuf_r+0x18> + 80113e8: f023 0303 bic.w r3, r3, #3 + 80113ec: f043 0302 orr.w r3, r3, #2 + 80113f0: 81a3 strh r3, [r4, #12] + 80113f2: e7e3 b.n 80113bc <__smakebuf_r+0xc> + 80113f4: 89a3 ldrh r3, [r4, #12] + 80113f6: 6020 str r0, [r4, #0] + 80113f8: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80113fc: 81a3 strh r3, [r4, #12] + 80113fe: 9b00 ldr r3, [sp, #0] + 8011400: 6163 str r3, [r4, #20] + 8011402: 9b01 ldr r3, [sp, #4] + 8011404: 6120 str r0, [r4, #16] + 8011406: b15b cbz r3, 8011420 <__smakebuf_r+0x70> + 8011408: f9b4 100e ldrsh.w r1, [r4, #14] + 801140c: 4630 mov r0, r6 + 801140e: f000 f851 bl 80114b4 <_isatty_r> + 8011412: b128 cbz r0, 8011420 <__smakebuf_r+0x70> + 8011414: 89a3 ldrh r3, [r4, #12] + 8011416: f023 0303 bic.w r3, r3, #3 + 801141a: f043 0301 orr.w r3, r3, #1 + 801141e: 81a3 strh r3, [r4, #12] + 8011420: 89a3 ldrh r3, [r4, #12] + 8011422: 431d orrs r5, r3 + 8011424: 81a5 strh r5, [r4, #12] + 8011426: e7cf b.n 80113c8 <__smakebuf_r+0x18> + +08011428 <_putc_r>: + 8011428: b570 push {r4, r5, r6, lr} + 801142a: 460d mov r5, r1 + 801142c: 4614 mov r4, r2 + 801142e: 4606 mov r6, r0 + 8011430: b118 cbz r0, 801143a <_putc_r+0x12> + 8011432: 6a03 ldr r3, [r0, #32] + 8011434: b90b cbnz r3, 801143a <_putc_r+0x12> + 8011436: f7ff fb37 bl 8010aa8 <__sinit> + 801143a: 6e63 ldr r3, [r4, #100] ; 0x64 + 801143c: 07d8 lsls r0, r3, #31 + 801143e: d405 bmi.n 801144c <_putc_r+0x24> + 8011440: 89a3 ldrh r3, [r4, #12] + 8011442: 0599 lsls r1, r3, #22 + 8011444: d402 bmi.n 801144c <_putc_r+0x24> + 8011446: 6da0 ldr r0, [r4, #88] ; 0x58 + 8011448: f7ff fd9d bl 8010f86 <__retarget_lock_acquire_recursive> + 801144c: 68a3 ldr r3, [r4, #8] + 801144e: 3b01 subs r3, #1 + 8011450: 2b00 cmp r3, #0 + 8011452: 60a3 str r3, [r4, #8] + 8011454: da05 bge.n 8011462 <_putc_r+0x3a> + 8011456: 69a2 ldr r2, [r4, #24] + 8011458: 4293 cmp r3, r2 + 801145a: db12 blt.n 8011482 <_putc_r+0x5a> + 801145c: b2eb uxtb r3, r5 + 801145e: 2b0a cmp r3, #10 + 8011460: d00f beq.n 8011482 <_putc_r+0x5a> + 8011462: 6823 ldr r3, [r4, #0] + 8011464: 1c5a adds r2, r3, #1 + 8011466: 6022 str r2, [r4, #0] + 8011468: 701d strb r5, [r3, #0] + 801146a: b2ed uxtb r5, r5 + 801146c: 6e63 ldr r3, [r4, #100] ; 0x64 + 801146e: 07da lsls r2, r3, #31 + 8011470: d405 bmi.n 801147e <_putc_r+0x56> + 8011472: 89a3 ldrh r3, [r4, #12] + 8011474: 059b lsls r3, r3, #22 + 8011476: d402 bmi.n 801147e <_putc_r+0x56> + 8011478: 6da0 ldr r0, [r4, #88] ; 0x58 + 801147a: f7ff fd85 bl 8010f88 <__retarget_lock_release_recursive> + 801147e: 4628 mov r0, r5 + 8011480: bd70 pop {r4, r5, r6, pc} + 8011482: 4629 mov r1, r5 + 8011484: 4622 mov r2, r4 + 8011486: 4630 mov r0, r6 + 8011488: f7ff fc57 bl 8010d3a <__swbuf_r> + 801148c: 4605 mov r5, r0 + 801148e: e7ed b.n 801146c <_putc_r+0x44> + +08011490 <_fstat_r>: + 8011490: b538 push {r3, r4, r5, lr} + 8011492: 4d07 ldr r5, [pc, #28] ; (80114b0 <_fstat_r+0x20>) + 8011494: 2300 movs r3, #0 + 8011496: 4604 mov r4, r0 + 8011498: 4608 mov r0, r1 + 801149a: 4611 mov r1, r2 + 801149c: 602b str r3, [r5, #0] + 801149e: f7ef fabc bl 8000a1a <_fstat> + 80114a2: 1c43 adds r3, r0, #1 + 80114a4: d102 bne.n 80114ac <_fstat_r+0x1c> + 80114a6: 682b ldr r3, [r5, #0] + 80114a8: b103 cbz r3, 80114ac <_fstat_r+0x1c> + 80114aa: 6023 str r3, [r4, #0] + 80114ac: bd38 pop {r3, r4, r5, pc} + 80114ae: bf00 nop + 80114b0: 24007e08 .word 0x24007e08 + +080114b4 <_isatty_r>: + 80114b4: b538 push {r3, r4, r5, lr} + 80114b6: 4d06 ldr r5, [pc, #24] ; (80114d0 <_isatty_r+0x1c>) + 80114b8: 2300 movs r3, #0 + 80114ba: 4604 mov r4, r0 + 80114bc: 4608 mov r0, r1 + 80114be: 602b str r3, [r5, #0] + 80114c0: f7ef fabb bl 8000a3a <_isatty> + 80114c4: 1c43 adds r3, r0, #1 + 80114c6: d102 bne.n 80114ce <_isatty_r+0x1a> + 80114c8: 682b ldr r3, [r5, #0] + 80114ca: b103 cbz r3, 80114ce <_isatty_r+0x1a> + 80114cc: 6023 str r3, [r4, #0] + 80114ce: bd38 pop {r3, r4, r5, pc} + 80114d0: 24007e08 .word 0x24007e08 + +080114d4 <_sbrk_r>: + 80114d4: b538 push {r3, r4, r5, lr} + 80114d6: 4d06 ldr r5, [pc, #24] ; (80114f0 <_sbrk_r+0x1c>) + 80114d8: 2300 movs r3, #0 + 80114da: 4604 mov r4, r0 + 80114dc: 4608 mov r0, r1 + 80114de: 602b str r3, [r5, #0] + 80114e0: f7ef fac4 bl 8000a6c <_sbrk> + 80114e4: 1c43 adds r3, r0, #1 + 80114e6: d102 bne.n 80114ee <_sbrk_r+0x1a> + 80114e8: 682b ldr r3, [r5, #0] + 80114ea: b103 cbz r3, 80114ee <_sbrk_r+0x1a> + 80114ec: 6023 str r3, [r4, #0] + 80114ee: bd38 pop {r3, r4, r5, pc} + 80114f0: 24007e08 .word 0x24007e08 + +080114f4 : + 80114f4: b508 push {r3, lr} + 80114f6: 2006 movs r0, #6 + 80114f8: f000 f82c bl 8011554 + 80114fc: 2001 movs r0, #1 + 80114fe: f7ef fa59 bl 80009b4 <_exit> + +08011502 <_raise_r>: + 8011502: 291f cmp r1, #31 + 8011504: b538 push {r3, r4, r5, lr} + 8011506: 4604 mov r4, r0 + 8011508: 460d mov r5, r1 + 801150a: d904 bls.n 8011516 <_raise_r+0x14> + 801150c: 2316 movs r3, #22 + 801150e: 6003 str r3, [r0, #0] + 8011510: f04f 30ff mov.w r0, #4294967295 + 8011514: bd38 pop {r3, r4, r5, pc} + 8011516: 6bc2 ldr r2, [r0, #60] ; 0x3c + 8011518: b112 cbz r2, 8011520 <_raise_r+0x1e> + 801151a: f852 3021 ldr.w r3, [r2, r1, lsl #2] + 801151e: b94b cbnz r3, 8011534 <_raise_r+0x32> + 8011520: 4620 mov r0, r4 + 8011522: f000 f831 bl 8011588 <_getpid_r> + 8011526: 462a mov r2, r5 + 8011528: 4601 mov r1, r0 + 801152a: 4620 mov r0, r4 + 801152c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 8011530: f000 b818 b.w 8011564 <_kill_r> + 8011534: 2b01 cmp r3, #1 + 8011536: d00a beq.n 801154e <_raise_r+0x4c> + 8011538: 1c59 adds r1, r3, #1 + 801153a: d103 bne.n 8011544 <_raise_r+0x42> + 801153c: 2316 movs r3, #22 + 801153e: 6003 str r3, [r0, #0] + 8011540: 2001 movs r0, #1 + 8011542: e7e7 b.n 8011514 <_raise_r+0x12> + 8011544: 2400 movs r4, #0 + 8011546: f842 4025 str.w r4, [r2, r5, lsl #2] + 801154a: 4628 mov r0, r5 + 801154c: 4798 blx r3 + 801154e: 2000 movs r0, #0 + 8011550: e7e0 b.n 8011514 <_raise_r+0x12> + ... + +08011554 : + 8011554: 4b02 ldr r3, [pc, #8] ; (8011560 ) + 8011556: 4601 mov r1, r0 + 8011558: 6818 ldr r0, [r3, #0] + 801155a: f7ff bfd2 b.w 8011502 <_raise_r> + 801155e: bf00 nop + 8011560: 240000cc .word 0x240000cc + +08011564 <_kill_r>: + 8011564: b538 push {r3, r4, r5, lr} + 8011566: 4d07 ldr r5, [pc, #28] ; (8011584 <_kill_r+0x20>) + 8011568: 2300 movs r3, #0 + 801156a: 4604 mov r4, r0 + 801156c: 4608 mov r0, r1 + 801156e: 4611 mov r1, r2 + 8011570: 602b str r3, [r5, #0] + 8011572: f7ef fa0d bl 8000990 <_kill> + 8011576: 1c43 adds r3, r0, #1 + 8011578: d102 bne.n 8011580 <_kill_r+0x1c> + 801157a: 682b ldr r3, [r5, #0] + 801157c: b103 cbz r3, 8011580 <_kill_r+0x1c> + 801157e: 6023 str r3, [r4, #0] + 8011580: bd38 pop {r3, r4, r5, pc} + 8011582: bf00 nop + 8011584: 24007e08 .word 0x24007e08 + +08011588 <_getpid_r>: + 8011588: f7ef b9fa b.w 8000980 <_getpid> + +0801158c <_init>: + 801158c: b5f8 push {r3, r4, r5, r6, r7, lr} + 801158e: bf00 nop + 8011590: bcf8 pop {r3, r4, r5, r6, r7} + 8011592: bc08 pop {r3} + 8011594: 469e mov lr, r3 + 8011596: 4770 bx lr + +08011598 <_fini>: + 8011598: b5f8 push {r3, r4, r5, r6, r7, lr} + 801159a: bf00 nop + 801159c: bcf8 pop {r3, r4, r5, r6, r7} + 801159e: bc08 pop {r3} + 80115a0: 469e mov lr, r3 + 80115a2: 4770 bx lr diff --git a/Debug/lwip_test.map b/Debug/lwip_test.map new file mode 100644 index 0000000..d954933 --- /dev/null +++ b/Debug/lwip_test.map @@ -0,0 +1,26455 @@ +Archive member included to satisfy reference by file (symbol) + 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C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crti.o +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/crt0.o +LOAD ./Core/Src/main.o +LOAD ./Core/Src/stm32h7xx_hal_msp.o +LOAD ./Core/Src/stm32h7xx_it.o +LOAD ./Core/Src/syscalls.o +LOAD ./Core/Src/sysmem.o +LOAD ./Core/Src/system_stm32h7xx.o +LOAD ./Core/Startup/startup_stm32h723vghx.o +LOAD ./Drivers/BSP/Components/lan8742/lan8742.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o +LOAD ./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o +LOAD ./LWFTP/lwftp.o +LOAD ./LWFTP/lwftp_mod.o +LOAD ./LWIP/App/lwip.o +LOAD ./LWIP/Target/ethernetif.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/api_lib.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/api_msg.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/err.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/if_api.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/netbuf.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/netdb.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/netifapi.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/sockets.o +LOAD ./Middlewares/Third_Party/LwIP/src/api/tcpip.o +LOAD ./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/altcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/def.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/dns.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/init.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/ip.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/mem.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/memp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/netif.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/pbuf.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/raw.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/stats.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/sys.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/tcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/tcp_in.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/tcp_out.o +LOAD ./Middlewares/Third_Party/LwIP/src/core/timeouts.o +LOAD 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./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o +LOAD ./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o 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C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libnosys.a +END GROUP +START GROUP +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard\libgcc.a +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libnosys.a +END GROUP +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtend.o +LOAD C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtn.o + 0x0000000024050000 _estack = (ORIGIN (RAM_D1) + LENGTH (RAM_D1)) + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0x2cc + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0x2cc ./Core/Startup/startup_stm32h723vghx.o + 0x0000000008000000 g_pfnVectors + 0x00000000080002cc . = ALIGN (0x4) + +.text 0x00000000080002d0 0x111b4 + 0x00000000080002d0 . = ALIGN (0x4) + *(.text) + .text 0x00000000080002d0 0x40 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+dp/hard/crtbegin.o + .text 0x0000000008000310 0x10 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-strlen.o) + 0x0000000008000310 strlen + .text 0x0000000008000320 0xa0 C:/ST/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard\libc_nano.a(libc_a-memchr.o) + 0x0000000008000320 memchr + *(.text*) + .text.ITM_SendChar + 0x00000000080003c0 0x4e ./Core/Src/main.o + .text._write 0x000000000800040e 0x38 ./Core/Src/main.o + 0x000000000800040e _write + *fill* 0x0000000008000446 0x2 + .text.LOG_TRACE + 0x0000000008000448 0x1c ./Core/Src/main.o + 0x0000000008000448 LOG_TRACE + .text.data_source + 0x0000000008000464 0x78 ./Core/Src/main.o + .text.ftp_connect_callback + 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0x62 (size before relaxing) diff --git a/Debug/makefile b/Debug/makefile new file mode 100644 index 0000000..e78f415 --- /dev/null +++ b/Debug/makefile @@ -0,0 +1,105 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Middlewares/Third_Party/LwIP/src/netif/ppp/subdir.mk +-include Middlewares/Third_Party/LwIP/src/netif/subdir.mk +-include Middlewares/Third_Party/LwIP/src/core/ipv6/subdir.mk +-include Middlewares/Third_Party/LwIP/src/core/ipv4/subdir.mk +-include Middlewares/Third_Party/LwIP/src/core/subdir.mk +-include Middlewares/Third_Party/LwIP/src/apps/mqtt/subdir.mk +-include Middlewares/Third_Party/LwIP/src/api/subdir.mk +-include LWIP/Target/subdir.mk +-include LWIP/App/subdir.mk +-include LWFTP/subdir.mk +-include Drivers/STM32H7xx_HAL_Driver/Src/subdir.mk +-include Drivers/BSP/Components/lan8742/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := lwip_test +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +lwip_test.elf \ + +MAP_FILES += \ +lwip_test.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +lwip_test.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: lwip_test.elf secondary-outputs + +# Tool invocations +lwip_test.elf lwip_test.map: $(OBJS) $(USER_OBJS) C:\_NoSleep\STM32\lwip_test\STM32H723VGHX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "lwip_test.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m7 -T"C:\_NoSleep\STM32\lwip_test\STM32H723VGHX_FLASH.ld" --specs=nosys.specs -Wl,-Map="lwip_test.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv5-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +lwip_test.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "lwip_test.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) default.size.stdout lwip_test.elf lwip_test.list lwip_test.map + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/Debug/objects.list b/Debug/objects.list new file mode 100644 index 0000000..bae596b --- /dev/null +++ b/Debug/objects.list @@ -0,0 +1,112 @@ +"./Core/Src/main.o" +"./Core/Src/stm32h7xx_hal_msp.o" +"./Core/Src/stm32h7xx_it.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32h7xx.o" +"./Core/Startup/startup_stm32h723vghx.o" +"./Drivers/BSP/Components/lan8742/lan8742.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.o" +"./Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.o" +"./LWFTP/lwftp.o" +"./LWFTP/lwftp_mod.o" +"./LWIP/App/lwip.o" +"./LWIP/Target/ethernetif.o" +"./Middlewares/Third_Party/LwIP/src/api/api_lib.o" +"./Middlewares/Third_Party/LwIP/src/api/api_msg.o" +"./Middlewares/Third_Party/LwIP/src/api/err.o" +"./Middlewares/Third_Party/LwIP/src/api/if_api.o" +"./Middlewares/Third_Party/LwIP/src/api/netbuf.o" +"./Middlewares/Third_Party/LwIP/src/api/netdb.o" +"./Middlewares/Third_Party/LwIP/src/api/netifapi.o" +"./Middlewares/Third_Party/LwIP/src/api/sockets.o" +"./Middlewares/Third_Party/LwIP/src/api/tcpip.o" +"./Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.o" +"./Middlewares/Third_Party/LwIP/src/core/altcp.o" +"./Middlewares/Third_Party/LwIP/src/core/altcp_alloc.o" +"./Middlewares/Third_Party/LwIP/src/core/altcp_tcp.o" +"./Middlewares/Third_Party/LwIP/src/core/def.o" +"./Middlewares/Third_Party/LwIP/src/core/dns.o" +"./Middlewares/Third_Party/LwIP/src/core/inet_chksum.o" +"./Middlewares/Third_Party/LwIP/src/core/init.o" +"./Middlewares/Third_Party/LwIP/src/core/ip.o" +"./Middlewares/Third_Party/LwIP/src/core/mem.o" +"./Middlewares/Third_Party/LwIP/src/core/memp.o" +"./Middlewares/Third_Party/LwIP/src/core/netif.o" +"./Middlewares/Third_Party/LwIP/src/core/pbuf.o" +"./Middlewares/Third_Party/LwIP/src/core/raw.o" +"./Middlewares/Third_Party/LwIP/src/core/stats.o" +"./Middlewares/Third_Party/LwIP/src/core/sys.o" +"./Middlewares/Third_Party/LwIP/src/core/tcp.o" +"./Middlewares/Third_Party/LwIP/src/core/tcp_in.o" +"./Middlewares/Third_Party/LwIP/src/core/tcp_out.o" +"./Middlewares/Third_Party/LwIP/src/core/timeouts.o" +"./Middlewares/Third_Party/LwIP/src/core/udp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.o" +"./Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.o" +"./Middlewares/Third_Party/LwIP/src/netif/bridgeif.o" +"./Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.o" +"./Middlewares/Third_Party/LwIP/src/netif/ethernet.o" +"./Middlewares/Third_Party/LwIP/src/netif/lowpan6.o" +"./Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.o" +"./Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.o" +"./Middlewares/Third_Party/LwIP/src/netif/slipif.o" +"./Middlewares/Third_Party/LwIP/src/netif/zepif.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/auth.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/demand.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/eap.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/magic.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/mppe.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/upap.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/utils.o" +"./Middlewares/Third_Party/LwIP/src/netif/ppp/vj.o" diff --git a/Debug/objects.mk b/Debug/objects.mk new file mode 100644 index 0000000..820854b --- /dev/null +++ b/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/Debug/sources.mk b/Debug/sources.mk new file mode 100644 index 0000000..5035afa --- /dev/null +++ b/Debug/sources.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/BSP/Components/lan8742 \ +Drivers/STM32H7xx_HAL_Driver/Src \ +LWFTP \ +LWIP/App \ +LWIP/Target \ +Middlewares/Third_Party/LwIP/src/api \ +Middlewares/Third_Party/LwIP/src/apps/mqtt \ +Middlewares/Third_Party/LwIP/src/core \ +Middlewares/Third_Party/LwIP/src/core/ipv4 \ +Middlewares/Third_Party/LwIP/src/core/ipv6 \ +Middlewares/Third_Party/LwIP/src/netif \ +Middlewares/Third_Party/LwIP/src/netif/ppp \ + diff --git a/Drivers/BSP/Components/lan8742/lan8742.c b/Drivers/BSP/Components/lan8742/lan8742.c new file mode 100644 index 0000000..a268393 --- /dev/null +++ b/Drivers/BSP/Components/lan8742/lan8742.c @@ -0,0 +1,664 @@ +/** + ****************************************************************************** + * @file lan8742.c + * @author MCD Application Team + * @brief This file provides a set of functions needed to manage the LAN742 + * PHY devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "lan8742.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @defgroup LAN8742 LAN8742 + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup LAN8742_Private_Defines LAN8742 Private Defines + * @{ + */ +#define LAN8742_SW_RESET_TO ((uint32_t)500U) +#define LAN8742_INIT_TO ((uint32_t)2000U) +#define LAN8742_MAX_DEV_ADDR ((uint32_t)31U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LAN8742_Private_Functions LAN8742 Private Functions + * @{ + */ + +/** + * @brief Register IO functions to component object + * @param pObj: device object of LAN8742_Object_t. + * @param ioctx: holds device IO functions. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_ERROR if missing mandatory function + */ +int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx) +{ + if(!pObj || !ioctx->ReadReg || !ioctx->WriteReg || !ioctx->GetTick) + { + return LAN8742_STATUS_ERROR; + } + + pObj->IO.Init = ioctx->Init; + pObj->IO.DeInit = ioctx->DeInit; + pObj->IO.ReadReg = ioctx->ReadReg; + pObj->IO.WriteReg = ioctx->WriteReg; + pObj->IO.GetTick = ioctx->GetTick; + + return LAN8742_STATUS_OK; +} + +/** + * @brief Initialize the lan8742 and configure the needed hardware resources + * @param pObj: device object LAN8742_Object_t. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_ADDRESS_ERROR if cannot find device address + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + * LAN8742_STATUS_RESET_TIMEOUT if cannot perform a software reset + */ + int32_t LAN8742_Init(lan8742_Object_t *pObj) + { + uint32_t tickstart = 0, regvalue = 0, addr = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->Is_Initialized == 0) + { + if(pObj->IO.Init != 0) + { + /* GPIO and Clocks initialization */ + pObj->IO.Init(); + } + + /* for later check */ + pObj->DevAddr = LAN8742_MAX_DEV_ADDR + 1; + + /* Get the device address from special mode register */ + for(addr = 0; addr <= LAN8742_MAX_DEV_ADDR; addr ++) + { + if(pObj->IO.ReadReg(addr, LAN8742_SMR, ®value) < 0) + { + status = LAN8742_STATUS_READ_ERROR; + /* Can't read from this device address + continue with next address */ + continue; + } + + if((regvalue & LAN8742_SMR_PHY_ADDR) == addr) + { + pObj->DevAddr = addr; + status = LAN8742_STATUS_OK; + break; + } + } + + if(pObj->DevAddr > LAN8742_MAX_DEV_ADDR) + { + status = LAN8742_STATUS_ADDRESS_ERROR; + } + + /* if device address is matched */ + if(status == LAN8742_STATUS_OK) + { + /* set a software reset */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, LAN8742_BCR_SOFT_RESET) >= 0) + { + /* get software reset status */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) >= 0) + { + tickstart = pObj->IO.GetTick(); + + /* wait until software reset is done or timeout occured */ + while(regvalue & LAN8742_BCR_SOFT_RESET) + { + if((pObj->IO.GetTick() - tickstart) <= LAN8742_SW_RESET_TO) + { + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, ®value) < 0) + { + status = LAN8742_STATUS_READ_ERROR; + break; + } + } + else + { + status = LAN8742_STATUS_RESET_TIMEOUT; + break; + } + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + } + else + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + } + + if(status == LAN8742_STATUS_OK) + { + tickstart = pObj->IO.GetTick(); + + /* Wait for 2s to perform initialization */ + while((pObj->IO.GetTick() - tickstart) <= LAN8742_INIT_TO) + { + } + pObj->Is_Initialized = 1; + } + + return status; + } + +/** + * @brief De-Initialize the lan8742 and it's hardware resources + * @param pObj: device object LAN8742_Object_t. + * @retval None + */ +int32_t LAN8742_DeInit(lan8742_Object_t *pObj) +{ + if(pObj->Is_Initialized) + { + if(pObj->IO.DeInit != 0) + { + if(pObj->IO.DeInit() < 0) + { + return LAN8742_STATUS_ERROR; + } + } + + pObj->Is_Initialized = 0; + } + + return LAN8742_STATUS_OK; +} + +/** + * @brief Disable the LAN8742 power down mode. + * @param pObj: device object LAN8742_Object_t. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_DisablePowerDownMode(lan8742_Object_t *pObj) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) + { + readval &= ~LAN8742_BCR_POWER_DOWN; + + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Enable the LAN8742 power down mode. + * @param pObj: device object LAN8742_Object_t. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_EnablePowerDownMode(lan8742_Object_t *pObj) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) + { + readval |= LAN8742_BCR_POWER_DOWN; + + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Start the auto negotiation process. + * @param pObj: device object LAN8742_Object_t. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_StartAutoNego(lan8742_Object_t *pObj) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) + { + readval |= LAN8742_BCR_AUTONEGO_EN; + + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Get the link state of LAN8742 device. + * @param pObj: Pointer to device object. + * @param pLinkState: Pointer to link state + * @retval LAN8742_STATUS_LINK_DOWN if link is down + * LAN8742_STATUS_AUTONEGO_NOTDONE if Auto nego not completed + * LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD + * LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD + * LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD + * LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj) +{ + uint32_t readval = 0; + + /* Read Status register */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) + { + return LAN8742_STATUS_READ_ERROR; + } + + /* Read Status register again */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BSR, &readval) < 0) + { + return LAN8742_STATUS_READ_ERROR; + } + + if((readval & LAN8742_BSR_LINK_STATUS) == 0) + { + /* Return Link Down status */ + return LAN8742_STATUS_LINK_DOWN; + } + + /* Check Auto negotiaition */ + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) < 0) + { + return LAN8742_STATUS_READ_ERROR; + } + + if((readval & LAN8742_BCR_AUTONEGO_EN) != LAN8742_BCR_AUTONEGO_EN) + { + if(((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) && ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE)) + { + return LAN8742_STATUS_100MBITS_FULLDUPLEX; + } + else if ((readval & LAN8742_BCR_SPEED_SELECT) == LAN8742_BCR_SPEED_SELECT) + { + return LAN8742_STATUS_100MBITS_HALFDUPLEX; + } + else if ((readval & LAN8742_BCR_DUPLEX_MODE) == LAN8742_BCR_DUPLEX_MODE) + { + return LAN8742_STATUS_10MBITS_FULLDUPLEX; + } + else + { + return LAN8742_STATUS_10MBITS_HALFDUPLEX; + } + } + else /* Auto Nego enabled */ + { + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_PHYSCSR, &readval) < 0) + { + return LAN8742_STATUS_READ_ERROR; + } + + /* Check if auto nego not done */ + if((readval & LAN8742_PHYSCSR_AUTONEGO_DONE) == 0) + { + return LAN8742_STATUS_AUTONEGO_NOTDONE; + } + + if((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_FD) + { + return LAN8742_STATUS_100MBITS_FULLDUPLEX; + } + else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_100BTX_HD) + { + return LAN8742_STATUS_100MBITS_HALFDUPLEX; + } + else if ((readval & LAN8742_PHYSCSR_HCDSPEEDMASK) == LAN8742_PHYSCSR_10BT_FD) + { + return LAN8742_STATUS_10MBITS_FULLDUPLEX; + } + else + { + return LAN8742_STATUS_10MBITS_HALFDUPLEX; + } + } +} + +/** + * @brief Set the link state of LAN8742 device. + * @param pObj: Pointer to device object. + * @param pLinkState: link state can be one of the following + * LAN8742_STATUS_100MBITS_FULLDUPLEX if 100Mb/s FD + * LAN8742_STATUS_100MBITS_HALFDUPLEX if 100Mb/s HD + * LAN8742_STATUS_10MBITS_FULLDUPLEX if 10Mb/s FD + * LAN8742_STATUS_10MBITS_HALFDUPLEX if 10Mb/s HD + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_ERROR if parameter error + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_SetLinkState(lan8742_Object_t *pObj, uint32_t LinkState) +{ + uint32_t bcrvalue = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &bcrvalue) >= 0) + { + /* Disable link config (Auto nego, speed and duplex) */ + bcrvalue &= ~(LAN8742_BCR_AUTONEGO_EN | LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE); + + if(LinkState == LAN8742_STATUS_100MBITS_FULLDUPLEX) + { + bcrvalue |= (LAN8742_BCR_SPEED_SELECT | LAN8742_BCR_DUPLEX_MODE); + } + else if (LinkState == LAN8742_STATUS_100MBITS_HALFDUPLEX) + { + bcrvalue |= LAN8742_BCR_SPEED_SELECT; + } + else if (LinkState == LAN8742_STATUS_10MBITS_FULLDUPLEX) + { + bcrvalue |= LAN8742_BCR_DUPLEX_MODE; + } + else + { + /* Wrong link status parameter */ + status = LAN8742_STATUS_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + if(status == LAN8742_STATUS_OK) + { + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, bcrvalue) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + + return status; +} + +/** + * @brief Enable loopback mode. + * @param pObj: Pointer to device object. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_EnableLoopbackMode(lan8742_Object_t *pObj) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) + { + readval |= LAN8742_BCR_LOOPBACK; + + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Disable loopback mode. + * @param pObj: Pointer to device object. + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_BCR, &readval) >= 0) + { + readval &= ~LAN8742_BCR_LOOPBACK; + + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_BCR, readval) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Enable IT source. + * @param pObj: Pointer to device object. + * @param Interrupt: IT source to be enabled + * should be a value or a combination of the following: + * LAN8742_WOL_IT + * LAN8742_ENERGYON_IT + * LAN8742_AUTONEGO_COMPLETE_IT + * LAN8742_REMOTE_FAULT_IT + * LAN8742_LINK_DOWN_IT + * LAN8742_AUTONEGO_LP_ACK_IT + * LAN8742_PARALLEL_DETECTION_FAULT_IT + * LAN8742_AUTONEGO_PAGE_RECEIVED_IT + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0) + { + readval |= Interrupt; + + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Disable IT source. + * @param pObj: Pointer to device object. + * @param Interrupt: IT source to be disabled + * should be a value or a combination of the following: + * LAN8742_WOL_IT + * LAN8742_ENERGYON_IT + * LAN8742_AUTONEGO_COMPLETE_IT + * LAN8742_REMOTE_FAULT_IT + * LAN8742_LINK_DOWN_IT + * LAN8742_AUTONEGO_LP_ACK_IT + * LAN8742_PARALLEL_DETECTION_FAULT_IT + * LAN8742_AUTONEGO_PAGE_RECEIVED_IT + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + * LAN8742_STATUS_WRITE_ERROR if connot write to register + */ +int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_IMR, &readval) >= 0) + { + readval &= ~Interrupt; + + /* Apply configuration */ + if(pObj->IO.WriteReg(pObj->DevAddr, LAN8742_IMR, readval) < 0) + { + status = LAN8742_STATUS_WRITE_ERROR; + } + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Clear IT flag. + * @param pObj: Pointer to device object. + * @param Interrupt: IT flag to be cleared + * should be a value or a combination of the following: + * LAN8742_WOL_IT + * LAN8742_ENERGYON_IT + * LAN8742_AUTONEGO_COMPLETE_IT + * LAN8742_REMOTE_FAULT_IT + * LAN8742_LINK_DOWN_IT + * LAN8742_AUTONEGO_LP_ACK_IT + * LAN8742_PARALLEL_DETECTION_FAULT_IT + * LAN8742_AUTONEGO_PAGE_RECEIVED_IT + * @retval LAN8742_STATUS_OK if OK + * LAN8742_STATUS_READ_ERROR if connot read register + */ +int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt) +{ + uint32_t readval = 0; + int32_t status = LAN8742_STATUS_OK; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) < 0) + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @brief Get IT Flag status. + * @param pObj: Pointer to device object. + * @param Interrupt: IT Flag to be checked, + * should be a value or a combination of the following: + * LAN8742_WOL_IT + * LAN8742_ENERGYON_IT + * LAN8742_AUTONEGO_COMPLETE_IT + * LAN8742_REMOTE_FAULT_IT + * LAN8742_LINK_DOWN_IT + * LAN8742_AUTONEGO_LP_ACK_IT + * LAN8742_PARALLEL_DETECTION_FAULT_IT + * LAN8742_AUTONEGO_PAGE_RECEIVED_IT + * @retval 1 IT flag is SET + * 0 IT flag is RESET + * LAN8742_STATUS_READ_ERROR if connot read register + */ +int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt) +{ + uint32_t readval = 0; + int32_t status = 0; + + if(pObj->IO.ReadReg(pObj->DevAddr, LAN8742_ISFR, &readval) >= 0) + { + status = ((readval & Interrupt) == Interrupt); + } + else + { + status = LAN8742_STATUS_READ_ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/BSP/Components/lan8742/lan8742.h b/Drivers/BSP/Components/lan8742/lan8742.h new file mode 100644 index 0000000..c1620dd --- /dev/null +++ b/Drivers/BSP/Components/lan8742/lan8742.h @@ -0,0 +1,448 @@ +/** + ****************************************************************************** + * @file lan8742.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the + * lan8742.c PHY driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LAN8742_H +#define LAN8742_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @defgroup LAN8742 + * @{ + */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LAN8742_Exported_Constants LAN8742 Exported Constants + * @{ + */ + +/** @defgroup LAN8742_Registers_Mapping LAN8742 Registers Mapping + * @{ + */ +#define LAN8742_BCR ((uint16_t)0x0000U) +#define LAN8742_BSR ((uint16_t)0x0001U) +#define LAN8742_PHYI1R ((uint16_t)0x0002U) +#define LAN8742_PHYI2R ((uint16_t)0x0003U) +#define LAN8742_ANAR ((uint16_t)0x0004U) +#define LAN8742_ANLPAR ((uint16_t)0x0005U) +#define LAN8742_ANER ((uint16_t)0x0006U) +#define LAN8742_ANNPTR ((uint16_t)0x0007U) +#define LAN8742_ANNPRR ((uint16_t)0x0008U) +#define LAN8742_MMDACR ((uint16_t)0x000DU) +#define LAN8742_MMDAADR ((uint16_t)0x000EU) +#define LAN8742_ENCTR ((uint16_t)0x0010U) +#define LAN8742_MCSR ((uint16_t)0x0011U) +#define LAN8742_SMR ((uint16_t)0x0012U) +#define LAN8742_TPDCR ((uint16_t)0x0018U) +#define LAN8742_TCSR ((uint16_t)0x0019U) +#define LAN8742_SECR ((uint16_t)0x001AU) +#define LAN8742_SCSIR ((uint16_t)0x001BU) +#define LAN8742_CLR ((uint16_t)0x001CU) +#define LAN8742_ISFR ((uint16_t)0x001DU) +#define LAN8742_IMR ((uint16_t)0x001EU) +#define LAN8742_PHYSCSR ((uint16_t)0x001FU) +/** + * @} + */ + +/** @defgroup LAN8742_BCR_Bit_Definition LAN8742 BCR Bit Definition + * @{ + */ +#define LAN8742_BCR_SOFT_RESET ((uint16_t)0x8000U) +#define LAN8742_BCR_LOOPBACK ((uint16_t)0x4000U) +#define LAN8742_BCR_SPEED_SELECT ((uint16_t)0x2000U) +#define LAN8742_BCR_AUTONEGO_EN ((uint16_t)0x1000U) +#define LAN8742_BCR_POWER_DOWN ((uint16_t)0x0800U) +#define LAN8742_BCR_ISOLATE ((uint16_t)0x0400U) +#define LAN8742_BCR_RESTART_AUTONEGO ((uint16_t)0x0200U) +#define LAN8742_BCR_DUPLEX_MODE ((uint16_t)0x0100U) +/** + * @} + */ + +/** @defgroup LAN8742_BSR_Bit_Definition LAN8742 BSR Bit Definition + * @{ + */ +#define LAN8742_BSR_100BASE_T4 ((uint16_t)0x8000U) +#define LAN8742_BSR_100BASE_TX_FD ((uint16_t)0x4000U) +#define LAN8742_BSR_100BASE_TX_HD ((uint16_t)0x2000U) +#define LAN8742_BSR_10BASE_T_FD ((uint16_t)0x1000U) +#define LAN8742_BSR_10BASE_T_HD ((uint16_t)0x0800U) +#define LAN8742_BSR_100BASE_T2_FD ((uint16_t)0x0400U) +#define LAN8742_BSR_100BASE_T2_HD ((uint16_t)0x0200U) +#define LAN8742_BSR_EXTENDED_STATUS ((uint16_t)0x0100U) +#define LAN8742_BSR_AUTONEGO_CPLT ((uint16_t)0x0020U) +#define LAN8742_BSR_REMOTE_FAULT ((uint16_t)0x0010U) +#define LAN8742_BSR_AUTONEGO_ABILITY ((uint16_t)0x0008U) +#define LAN8742_BSR_LINK_STATUS ((uint16_t)0x0004U) +#define LAN8742_BSR_JABBER_DETECT ((uint16_t)0x0002U) +#define LAN8742_BSR_EXTENDED_CAP ((uint16_t)0x0001U) +/** + * @} + */ + +/** @defgroup LAN8742_PHYI1R_Bit_Definition LAN8742 PHYI1R Bit Definition + * @{ + */ +#define LAN8742_PHYI1R_OUI_3_18 ((uint16_t)0xFFFFU) +/** + * @} + */ + +/** @defgroup LAN8742_PHYI2R_Bit_Definition LAN8742 PHYI2R Bit Definition + * @{ + */ +#define LAN8742_PHYI2R_OUI_19_24 ((uint16_t)0xFC00U) +#define LAN8742_PHYI2R_MODEL_NBR ((uint16_t)0x03F0U) +#define LAN8742_PHYI2R_REVISION_NBR ((uint16_t)0x000FU) +/** + * @} + */ + +/** @defgroup LAN8742_ANAR_Bit_Definition LAN8742 ANAR Bit Definition + * @{ + */ +#define LAN8742_ANAR_NEXT_PAGE ((uint16_t)0x8000U) +#define LAN8742_ANAR_REMOTE_FAULT ((uint16_t)0x2000U) +#define LAN8742_ANAR_PAUSE_OPERATION ((uint16_t)0x0C00U) +#define LAN8742_ANAR_PO_NOPAUSE ((uint16_t)0x0000U) +#define LAN8742_ANAR_PO_SYMMETRIC_PAUSE ((uint16_t)0x0400U) +#define LAN8742_ANAR_PO_ASYMMETRIC_PAUSE ((uint16_t)0x0800U) +#define LAN8742_ANAR_PO_ADVERTISE_SUPPORT ((uint16_t)0x0C00U) +#define LAN8742_ANAR_100BASE_TX_FD ((uint16_t)0x0100U) +#define LAN8742_ANAR_100BASE_TX ((uint16_t)0x0080U) +#define LAN8742_ANAR_10BASE_T_FD ((uint16_t)0x0040U) +#define LAN8742_ANAR_10BASE_T ((uint16_t)0x0020U) +#define LAN8742_ANAR_SELECTOR_FIELD ((uint16_t)0x000FU) +/** + * @} + */ + +/** @defgroup LAN8742_ANLPAR_Bit_Definition LAN8742 ANLPAR Bit Definition + * @{ + */ +#define LAN8742_ANLPAR_NEXT_PAGE ((uint16_t)0x8000U) +#define LAN8742_ANLPAR_REMOTE_FAULT ((uint16_t)0x2000U) +#define LAN8742_ANLPAR_PAUSE_OPERATION ((uint16_t)0x0C00U) +#define LAN8742_ANLPAR_PO_NOPAUSE ((uint16_t)0x0000U) +#define LAN8742_ANLPAR_PO_SYMMETRIC_PAUSE ((uint16_t)0x0400U) +#define LAN8742_ANLPAR_PO_ASYMMETRIC_PAUSE ((uint16_t)0x0800U) +#define LAN8742_ANLPAR_PO_ADVERTISE_SUPPORT ((uint16_t)0x0C00U) +#define LAN8742_ANLPAR_100BASE_TX_FD ((uint16_t)0x0100U) +#define LAN8742_ANLPAR_100BASE_TX ((uint16_t)0x0080U) +#define LAN8742_ANLPAR_10BASE_T_FD ((uint16_t)0x0040U) +#define LAN8742_ANLPAR_10BASE_T ((uint16_t)0x0020U) +#define LAN8742_ANLPAR_SELECTOR_FIELD ((uint16_t)0x000FU) +/** + * @} + */ + +/** @defgroup LAN8742_ANER_Bit_Definition LAN8742 ANER Bit Definition + * @{ + */ +#define LAN8742_ANER_RX_NP_LOCATION_ABLE ((uint16_t)0x0040U) +#define LAN8742_ANER_RX_NP_STORAGE_LOCATION ((uint16_t)0x0020U) +#define LAN8742_ANER_PARALLEL_DETECT_FAULT ((uint16_t)0x0010U) +#define LAN8742_ANER_LP_NP_ABLE ((uint16_t)0x0008U) +#define LAN8742_ANER_NP_ABLE ((uint16_t)0x0004U) +#define LAN8742_ANER_PAGE_RECEIVED ((uint16_t)0x0002U) +#define LAN8742_ANER_LP_AUTONEG_ABLE ((uint16_t)0x0001U) +/** + * @} + */ + +/** @defgroup LAN8742_ANNPTR_Bit_Definition LAN8742 ANNPTR Bit Definition + * @{ + */ +#define LAN8742_ANNPTR_NEXT_PAGE ((uint16_t)0x8000U) +#define LAN8742_ANNPTR_MESSAGE_PAGE ((uint16_t)0x2000U) +#define LAN8742_ANNPTR_ACK2 ((uint16_t)0x1000U) +#define LAN8742_ANNPTR_TOGGLE ((uint16_t)0x0800U) +#define LAN8742_ANNPTR_MESSAGGE_CODE ((uint16_t)0x07FFU) +/** + * @} + */ + +/** @defgroup LAN8742_ANNPRR_Bit_Definition LAN8742 ANNPRR Bit Definition + * @{ + */ +#define LAN8742_ANNPTR_NEXT_PAGE ((uint16_t)0x8000U) +#define LAN8742_ANNPRR_ACK ((uint16_t)0x4000U) +#define LAN8742_ANNPRR_MESSAGE_PAGE ((uint16_t)0x2000U) +#define LAN8742_ANNPRR_ACK2 ((uint16_t)0x1000U) +#define LAN8742_ANNPRR_TOGGLE ((uint16_t)0x0800U) +#define LAN8742_ANNPRR_MESSAGGE_CODE ((uint16_t)0x07FFU) +/** + * @} + */ + +/** @defgroup LAN8742_MMDACR_Bit_Definition LAN8742 MMDACR Bit Definition + * @{ + */ +#define LAN8742_MMDACR_MMD_FUNCTION ((uint16_t)0xC000U) +#define LAN8742_MMDACR_MMD_FUNCTION_ADDR ((uint16_t)0x0000U) +#define LAN8742_MMDACR_MMD_FUNCTION_DATA ((uint16_t)0x4000U) +#define LAN8742_MMDACR_MMD_DEV_ADDR ((uint16_t)0x001FU) +/** + * @} + */ + +/** @defgroup LAN8742_ENCTR_Bit_Definition LAN8742 ENCTR Bit Definition + * @{ + */ +#define LAN8742_ENCTR_TX_ENABLE ((uint16_t)0x8000U) +#define LAN8742_ENCTR_TX_TIMER ((uint16_t)0x6000U) +#define LAN8742_ENCTR_TX_TIMER_1S ((uint16_t)0x0000U) +#define LAN8742_ENCTR_TX_TIMER_768MS ((uint16_t)0x2000U) +#define LAN8742_ENCTR_TX_TIMER_512MS ((uint16_t)0x4000U) +#define LAN8742_ENCTR_TX_TIMER_265MS ((uint16_t)0x6000U) +#define LAN8742_ENCTR_RX_ENABLE ((uint16_t)0x1000U) +#define LAN8742_ENCTR_RX_MAX_INTERVAL ((uint16_t)0x0C00U) +#define LAN8742_ENCTR_RX_MAX_INTERVAL_64MS ((uint16_t)0x0000U) +#define LAN8742_ENCTR_RX_MAX_INTERVAL_256MS ((uint16_t)0x0400U) +#define LAN8742_ENCTR_RX_MAX_INTERVAL_512MS ((uint16_t)0x0800U) +#define LAN8742_ENCTR_RX_MAX_INTERVAL_1S ((uint16_t)0x0C00U) +#define LAN8742_ENCTR_EX_CROSS_OVER ((uint16_t)0x0002U) +#define LAN8742_ENCTR_EX_MANUAL_CROSS_OVER ((uint16_t)0x0001U) +/** + * @} + */ + +/** @defgroup LAN8742_MCSR_Bit_Definition LAN8742 MCSR Bit Definition + * @{ + */ +#define LAN8742_MCSR_EDPWRDOWN ((uint16_t)0x2000U) +#define LAN8742_MCSR_FARLOOPBACK ((uint16_t)0x0200U) +#define LAN8742_MCSR_ALTINT ((uint16_t)0x0040U) +#define LAN8742_MCSR_ENERGYON ((uint16_t)0x0002U) +/** + * @} + */ + +/** @defgroup LAN8742_SMR_Bit_Definition LAN8742 SMR Bit Definition + * @{ + */ +#define LAN8742_SMR_MODE ((uint16_t)0x00E0U) +#define LAN8742_SMR_PHY_ADDR ((uint16_t)0x001FU) +/** + * @} + */ + +/** @defgroup LAN8742_TPDCR_Bit_Definition LAN8742 TPDCR Bit Definition + * @{ + */ +#define LAN8742_TPDCR_DELAY_IN ((uint16_t)0x8000U) +#define LAN8742_TPDCR_LINE_BREAK_COUNTER ((uint16_t)0x7000U) +#define LAN8742_TPDCR_PATTERN_HIGH ((uint16_t)0x0FC0U) +#define LAN8742_TPDCR_PATTERN_LOW ((uint16_t)0x003FU) +/** + * @} + */ + +/** @defgroup LAN8742_TCSR_Bit_Definition LAN8742 TCSR Bit Definition + * @{ + */ +#define LAN8742_TCSR_TDR_ENABLE ((uint16_t)0x8000U) +#define LAN8742_TCSR_TDR_AD_FILTER_ENABLE ((uint16_t)0x4000U) +#define LAN8742_TCSR_TDR_CH_CABLE_TYPE ((uint16_t)0x0600U) +#define LAN8742_TCSR_TDR_CH_CABLE_DEFAULT ((uint16_t)0x0000U) +#define LAN8742_TCSR_TDR_CH_CABLE_SHORTED ((uint16_t)0x0200U) +#define LAN8742_TCSR_TDR_CH_CABLE_OPEN ((uint16_t)0x0400U) +#define LAN8742_TCSR_TDR_CH_CABLE_MATCH ((uint16_t)0x0600U) +#define LAN8742_TCSR_TDR_CH_STATUS ((uint16_t)0x0100U) +#define LAN8742_TCSR_TDR_CH_LENGTH ((uint16_t)0x00FFU) +/** + * @} + */ + +/** @defgroup LAN8742_SCSIR_Bit_Definition LAN8742 SCSIR Bit Definition + * @{ + */ +#define LAN8742_SCSIR_AUTO_MDIX_ENABLE ((uint16_t)0x8000U) +#define LAN8742_SCSIR_CHANNEL_SELECT ((uint16_t)0x2000U) +#define LAN8742_SCSIR_SQE_DISABLE ((uint16_t)0x0800U) +#define LAN8742_SCSIR_XPOLALITY ((uint16_t)0x0010U) +/** + * @} + */ + +/** @defgroup LAN8742_CLR_Bit_Definition LAN8742 CLR Bit Definition + * @{ + */ +#define LAN8742_CLR_CABLE_LENGTH ((uint16_t)0xF000U) +/** + * @} + */ + +/** @defgroup LAN8742_IMR_ISFR_Bit_Definition LAN8742 IMR ISFR Bit Definition + * @{ + */ +#define LAN8742_INT_8 ((uint16_t)0x0100U) +#define LAN8742_INT_7 ((uint16_t)0x0080U) +#define LAN8742_INT_6 ((uint16_t)0x0040U) +#define LAN8742_INT_5 ((uint16_t)0x0020U) +#define LAN8742_INT_4 ((uint16_t)0x0010U) +#define LAN8742_INT_3 ((uint16_t)0x0008U) +#define LAN8742_INT_2 ((uint16_t)0x0004U) +#define LAN8742_INT_1 ((uint16_t)0x0002U) +/** + * @} + */ + +/** @defgroup LAN8742_PHYSCSR_Bit_Definition LAN8742 PHYSCSR Bit Definition + * @{ + */ +#define LAN8742_PHYSCSR_AUTONEGO_DONE ((uint16_t)0x1000U) +#define LAN8742_PHYSCSR_HCDSPEEDMASK ((uint16_t)0x001CU) +#define LAN8742_PHYSCSR_10BT_HD ((uint16_t)0x0004U) +#define LAN8742_PHYSCSR_10BT_FD ((uint16_t)0x0014U) +#define LAN8742_PHYSCSR_100BTX_HD ((uint16_t)0x0008U) +#define LAN8742_PHYSCSR_100BTX_FD ((uint16_t)0x0018U) +/** + * @} + */ + +/** @defgroup LAN8742_Status LAN8742 Status + * @{ + */ + +#define LAN8742_STATUS_READ_ERROR ((int32_t)-5) +#define LAN8742_STATUS_WRITE_ERROR ((int32_t)-4) +#define LAN8742_STATUS_ADDRESS_ERROR ((int32_t)-3) +#define LAN8742_STATUS_RESET_TIMEOUT ((int32_t)-2) +#define LAN8742_STATUS_ERROR ((int32_t)-1) +#define LAN8742_STATUS_OK ((int32_t) 0) +#define LAN8742_STATUS_LINK_DOWN ((int32_t) 1) +#define LAN8742_STATUS_100MBITS_FULLDUPLEX ((int32_t) 2) +#define LAN8742_STATUS_100MBITS_HALFDUPLEX ((int32_t) 3) +#define LAN8742_STATUS_10MBITS_FULLDUPLEX ((int32_t) 4) +#define LAN8742_STATUS_10MBITS_HALFDUPLEX ((int32_t) 5) +#define LAN8742_STATUS_AUTONEGO_NOTDONE ((int32_t) 6) +/** + * @} + */ + +/** @defgroup LAN8742_IT_Flags LAN8742 IT Flags + * @{ + */ +#define LAN8742_WOL_IT LAN8742_INT_8 +#define LAN8742_ENERGYON_IT LAN8742_INT_7 +#define LAN8742_AUTONEGO_COMPLETE_IT LAN8742_INT_6 +#define LAN8742_REMOTE_FAULT_IT LAN8742_INT_5 +#define LAN8742_LINK_DOWN_IT LAN8742_INT_4 +#define LAN8742_AUTONEGO_LP_ACK_IT LAN8742_INT_3 +#define LAN8742_PARALLEL_DETECTION_FAULT_IT LAN8742_INT_2 +#define LAN8742_AUTONEGO_PAGE_RECEIVED_IT LAN8742_INT_1 +/** + * @} + */ + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LAN8742_Exported_Types LAN8742 Exported Types + * @{ + */ +typedef int32_t (*lan8742_Init_Func) (void); +typedef int32_t (*lan8742_DeInit_Func) (void); +typedef int32_t (*lan8742_ReadReg_Func) (uint32_t, uint32_t, uint32_t *); +typedef int32_t (*lan8742_WriteReg_Func) (uint32_t, uint32_t, uint32_t); +typedef int32_t (*lan8742_GetTick_Func) (void); + +typedef struct +{ + lan8742_Init_Func Init; + lan8742_DeInit_Func DeInit; + lan8742_WriteReg_Func WriteReg; + lan8742_ReadReg_Func ReadReg; + lan8742_GetTick_Func GetTick; +} lan8742_IOCtx_t; + + +typedef struct +{ + uint32_t DevAddr; + uint32_t Is_Initialized; + lan8742_IOCtx_t IO; + void *pData; +}lan8742_Object_t; +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LAN8742_Exported_Functions LAN8742 Exported Functions + * @{ + */ +int32_t LAN8742_RegisterBusIO(lan8742_Object_t *pObj, lan8742_IOCtx_t *ioctx); +int32_t LAN8742_Init(lan8742_Object_t *pObj); +int32_t LAN8742_DeInit(lan8742_Object_t *pObj); +int32_t LAN8742_DisablePowerDownMode(lan8742_Object_t *pObj); +int32_t LAN8742_EnablePowerDownMode(lan8742_Object_t *pObj); +int32_t LAN8742_StartAutoNego(lan8742_Object_t *pObj); +int32_t LAN8742_GetLinkState(lan8742_Object_t *pObj); +int32_t LAN8742_SetLinkState(lan8742_Object_t *pObj, uint32_t LinkState); +int32_t LAN8742_EnableLoopbackMode(lan8742_Object_t *pObj); +int32_t LAN8742_DisableLoopbackMode(lan8742_Object_t *pObj); +int32_t LAN8742_EnableIT(lan8742_Object_t *pObj, uint32_t Interrupt); +int32_t LAN8742_DisableIT(lan8742_Object_t *pObj, uint32_t Interrupt); +int32_t LAN8742_ClearIT(lan8742_Object_t *pObj, uint32_t Interrupt); +int32_t LAN8742_GetITStatus(lan8742_Object_t *pObj, uint32_t Interrupt); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* LAN8742_H */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h new file mode 100644 index 0000000..dfe7f0f --- /dev/null +++ b/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h @@ -0,0 +1,24262 @@ +/** + ****************************************************************************** + * @file stm32h723xx.h + * @author MCD Application Team + * @brief CMSIS STM32H723xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h723xx + * @{ + */ + +#ifndef STM32H723xx_H +#define STM32H723xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL_RES0; /*!< Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1_TR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1_TR2; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + __IO uint32_t RES1_TR3; /*!< Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2_DIFSEL; /*!< ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 */ + __IO uint32_t HTR2_CALFACT; /*!< ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 */ + __IO uint32_t LTR3_RES10; /*!< ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 */ + __IO uint32_t HTR3_RES11; /*!< ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC */ + __IO uint32_t DIFSEL_RES12; /*!< ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 */ + __IO uint32_t CALFACT_RES13; /*!< ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 */ + __IO uint32_t CALFACT2_RES14; /*!< ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief COordincate Rotation DIgital Computer + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t RESERVED9[990]; /*!< Reserved, Address offset: 0x58-0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU peripheral identity register 4, Address offset: 0xFD0 */ + __IO uint32_t RESERVED10[3];/*!< Reserved, Address offset: 0xFD4-0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU peripheral identity register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU peripheral identity register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU peripheral identity register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU peripheral identity register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU component identity register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU component identity register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU component identity register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU component identity register 3, Address offset: 0xFFC */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ + __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */ + __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED[3]; /*!< Reserved, 0x64 to 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< Flash Option Status Current Register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< Flash Option Status to Program Register 2, Address offset: 0x74 */ +} FLASH_TypeDef; + +/** + * @brief Filter and Mathematical ACcelerator + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t ADC2ALT; /*!< ADC2 internal input alternate connection register, Address offset: 0x30 */ + uint32_t RESERVED4[60]; /*!< Reserved, 0x34-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED5[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + uint32_t RESERVED6[3]; /*!< Reserved, Address offset: 0x320-0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + __IO uint32_t UR18; /*!< SYSCFG user register 18, Address offset: 0x348 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; + +/** + * @brief DTS + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */ + __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */ + __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */ + __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */ + __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */ + __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */ +} +DTS_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */ + __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */ + __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */ + __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */ +} OCTOSPI_TypeDef; + +/** + * @} + */ +/** + * @brief OCTO Serial Peripheral Interface IO Manager + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[3]; /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */ +} OCTOSPIM_TypeDef; + +/** + * @} + */ + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 128KB) system data RAM1 accessible over over AXI */ +#define D1_AXISRAM2_BASE (0x24020000UL) /*!< Base address of : (up to 192KB) system data RAM2 accessible over over AXI to be shared with ITCM (64K granularity) */ +#define D1_AXISRAM_BASE D1_AXISRAM1_BASE /*!< Base address of : (up to 320KB) system data RAM1/2 accessible over over AXI */ + +#define D2_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM2_BASE (0x30004000UL) /*!< Base address of : (up to 16KB) system data RAM accessible over over AXI->AHB Bridge */ +#define D2_AHBSRAM_BASE D2_AHBSRAM1_BASE /*!< Base address of : (up to 32KB) system data RAM1/2 accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(16 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_END (0x080FFFFFUL) /*!< FLASH end address */ + + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define OCTOSPI1_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_OCTOSPI1_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) +#define OCTOSPI2_R_BASE (D1_AHB1PERIPH_BASE + 0xA000UL) +#define DLYB_OCTOSPI2_BASE (D1_AHB1PERIPH_BASE + 0xB000UL) +#define OCTOSPIM_BASE (D1_AHB1PERIPH_BASE + 0xB400UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define PSSI_BASE (D2_AHB2PERIPH_BASE + 0x0400UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) +#define FMAC_BASE (D2_AHB2PERIPH_BASE + 0x4000UL) +#define CORDIC_BASE (D2_AHB2PERIPH_BASE + 0x4400UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define I2C5_BASE (D2_APB1PERIPH_BASE + 0x6400UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) +#define FDCAN3_BASE (D2_APB1PERIPH_BASE + 0xD400UL) +#define TIM23_BASE (D2_APB1PERIPH_BASE + 0xE000UL) +#define TIM24_BASE (D2_APB1PERIPH_BASE + 0xE400UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define UART9_BASE (D2_APB2PERIPH_BASE + 0x1800UL) +#define USART10_BASE (D2_APB2PERIPH_BASE + 0x1C00UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7800UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + +#define DTS_BASE (D3_APB1PERIPH_BASE + 0x6800UL) + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) +#define RAMECC1_Monitor6_BASE (RAMECC1_BASE + 0xC0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define USART10 ((USART_TypeDef *) USART10_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define UART9 ((USART_TypeDef *) UART9_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define I2C5 ((I2C_TypeDef *) I2C5_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE) +#define TIM23 ((TIM_TypeDef *) TIM23_BASE) +#define TIM24 ((TIM_TypeDef *) TIM24_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define DTS ((DTS_TypeDef *) DTS_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define PSSI ((PSSI_TypeDef *) PSSI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) +#define FMAC ((FMAC_TypeDef *) FMAC_BASE) +#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) +#define RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + +#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) +#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE) +#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) +#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE) +#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) + +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_V90 +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +#define ADC3_CFGR_DMAEN_Pos (0U) +#define ADC3_CFGR_DMAEN_Msk (0x1UL << ADC3_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC3_CFGR_DMAEN ADC3_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC3_CFGR_DMACFG_Pos (1U) +#define ADC3_CFGR_DMACFG_Msk (0x1UL << ADC3_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC3_CFGR_DMACFG ADC3_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC3_CFGR_RES_Pos (3U) +#define ADC3_CFGR_RES_Msk (0x3UL << ADC3_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC3_CFGR_RES ADC3_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC3_CFGR_RES_0 (0x1UL << ADC3_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR_RES_1 (0x2UL << ADC3_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR_ALIGN_Pos (15U) +#define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +#define ADC3_CFGR2_OVSR_Pos (2U) +#define ADC3_CFGR2_OVSR_Msk (0x7UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC3_CFGR2_OVSR ADC3_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC3_CFGR2_OVSR_0 (0x1UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC3_CFGR2_OVSR_1 (0x2UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC3_CFGR2_OVSR_2 (0x4UL << ADC3_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC3_CFGR2_SWTRIG_Pos (25U) +#define ADC3_CFGR2_SWTRIG_Msk (0x1UL << ADC3_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC3_CFGR2_SWTRIG ADC3_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC3_CFGR2_BULB_Pos (26U) +#define ADC3_CFGR2_BULB_Msk (0x1UL << ADC3_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC3_CFGR2_BULB ADC3_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC3_CFGR2_SMPTRIG_Pos (27U) +#define ADC3_CFGR2_SMPTRIG_Msk (0x1UL << ADC3_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC3_CFGR2_SMPTRIG ADC3_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC3_TR1 register *******************/ +#define ADC3_TR1_LT1_Pos (0U) +#define ADC3_TR1_LT1_Msk (0xFFFUL << ADC3_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC3_TR1_LT1 ADC3_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC3_TR1_AWDFILT_Pos (12U) +#define ADC3_TR1_AWDFILT_Msk (0x7UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC3_TR1_AWDFILT ADC3_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC3_TR1_AWDFILT_0 (0x1UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC3_TR1_AWDFILT_1 (0x2UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC3_TR1_AWDFILT_2 (0x4UL << ADC3_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC3_TR1_HT1_Pos (16U) +#define ADC3_TR1_HT1_Msk (0xFFFUL << ADC3_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC3_TR1_HT1 ADC3_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC3_TR2 register *******************/ +#define ADC3_TR2_LT2_Pos (0U) +#define ADC3_TR2_LT2_Msk (0xFFUL << ADC3_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC3_TR2_LT2 ADC3_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC3_TR2_HT2_Pos (16U) +#define ADC3_TR2_HT2_Msk (0xFFUL << ADC3_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR2_HT2 ADC3_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC3_TR3 register *******************/ +#define ADC3_TR3_LT3_Pos (0U) +#define ADC3_TR3_LT3_Msk (0xFFUL << ADC3_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC3_TR3_LT3 ADC3_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC3_TR3_HT3_Pos (16U) +#define ADC3_TR3_HT3_Msk (0xFFUL << ADC3_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC3_TR3_HT3 ADC3_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR1_OFFSET1_Pos (0U) +#define ADC3_OFR1_OFFSET1_Msk (0xFFFUL << ADC3_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR1_OFFSET1 ADC3_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR1_OFFSETPOS_Pos (24U) +#define ADC3_OFR1_OFFSETPOS_Msk (0x1UL << ADC3_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR1_OFFSETPOS ADC3_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC3_OFR1_SATEN_Pos (25U) +#define ADC3_OFR1_SATEN_Msk (0x1UL << ADC3_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR1_SATEN ADC3_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC3_OFR1_OFFSET1_EN_Pos (31U) +#define ADC3_OFR1_OFFSET1_EN_Msk (0x1UL << ADC3_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR1_OFFSET1_EN ADC3_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR2_OFFSET2_Pos (0U) +#define ADC3_OFR2_OFFSET2_Msk (0xFFFUL << ADC3_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR2_OFFSET2 ADC3_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR2_OFFSETPOS_Pos (24U) +#define ADC3_OFR2_OFFSETPOS_Msk (0x1UL << ADC3_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR2_OFFSETPOS ADC3_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC3_OFR2_SATEN_Pos (25U) +#define ADC3_OFR2_SATEN_Msk (0x1UL << ADC3_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR2_SATEN ADC3_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC3_OFR2_OFFSET2_EN_Pos (31U) +#define ADC3_OFR2_OFFSET2_EN_Msk (0x1UL << ADC3_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR2_OFFSET2_EN ADC3_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR3_OFFSET3_Pos (0U) +#define ADC3_OFR3_OFFSET3_Msk (0xFFFUL << ADC3_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR3_OFFSET3 ADC3_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR3_OFFSETPOS_Pos (24U) +#define ADC3_OFR3_OFFSETPOS_Msk (0x1UL << ADC3_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR3_OFFSETPOS ADC3_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC3_OFR3_SATEN_Pos (25U) +#define ADC3_OFR3_SATEN_Msk (0x1UL << ADC3_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR3_SATEN ADC3_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC3_OFR3_OFFSET3_EN_Pos (31U) +#define ADC3_OFR3_OFFSET3_EN_Msk (0x1UL << ADC3_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR3_OFFSET3_EN ADC3_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +#define ADC3_OFR4_OFFSET4_Pos (0U) +#define ADC3_OFR4_OFFSET4_Msk (0xFFFUL << ADC3_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC3_OFR4_OFFSET4 ADC3_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET1_CH[4:0] */ + +#define ADC3_OFR4_OFFSETPOS_Pos (24U) +#define ADC3_OFR4_OFFSETPOS_Msk (0x1UL << ADC3_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC3_OFR4_OFFSETPOS ADC3_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC3_OFR4_SATEN_Pos (25U) +#define ADC3_OFR4_SATEN_Msk (0x1UL << ADC3_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC3_OFR4_SATEN ADC3_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC3_OFR4_OFFSET4_EN_Pos (31U) +#define ADC3_OFR4_OFFSET4_EN_Msk (0x1UL << ADC3_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC3_OFR4_OFFSET4_EN ADC3_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..e917f35 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..feec324 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..12d68fd --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/Drivers/CMSIS/Include/core_armv81mml.h b/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000..8441e57 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..344dca5 --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..5ddb8ae --- /dev/null +++ b/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..cafae5a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..d104965 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..b79c6af --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..8157ca7 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..7fed59a --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm35p.h b/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000..5579c82 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..12c023b --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..c4515d8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..cf92577 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..40f3af8 --- /dev/null +++ b/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..0041d4d --- /dev/null +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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b/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4027 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32C0) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h new file mode 100644 index 0000000..ef50a4a --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -0,0 +1,1185 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_H +#define STM32H7xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_conf.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ +/** @defgroup REV_ID device revision ID + * @{ + */ +#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ +#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ +#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ +#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ + + +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) + + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) + +/** + * @} + */ + +#if !defined(SYSCFG_PMCR_BOOSTEN) +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + +/** + * @} + */ +#endif /* ! SYSCFG_PMCR_BOOSTEN */ + + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) || defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +/** @defgroup SYSCFG_Adc2_Alternate_Connection SYSCFG ADC2 Alternate Connection + * @{ + */ + +/** @brief Adc2 Alternate Connection on Vinp[16] and Vinp[17] + */ +#define SYSCFG_ADC2_ROUT0_DAC1_1 ((uint32_t)0x00000000) /*!< DAC1_out1 connected to ADC2 VINP[16] */ +#define SYSCFG_ADC2_ROUT0_VBAT4 SYSCFG_ADC2ALT_ADC2_ROUT0 /*!< VBAT/4 connected to ADC2 VINP[16] */ +#define SYSCFG_ADC2_ROUT1_DAC1_2 ((uint32_t)0x00000000) /*!< DAC1_out2 connected to ADC2 VINP[17] */ +#define SYSCFG_ADC2_ROUT1_VREFINT SYSCFG_ADC2ALT_ADC2_ROUT1 /*!< VREFINT connected to ADC2 VINP[17] */ + +#define IS_SYSCFG_ADC2ALT_ROUT0(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT0_DAC1_1) || \ + ((__VALUE__) == SYSCFG_ADC2_ROUT0_VBAT4)) +#define IS_SYSCFG_ADC2ALT_ROUT1(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT1_DAC1_2) || \ + ((__VALUE__) == SYSCFG_ADC2_ROUT1_VREFINT)) + +/** + * @} + */ +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0 || SYSCFG_ADC2ALT_ADC2_ROUT1*/ + + +/** @defgroup SYSCFG_Ethernet_Config Ethernet Config + * @{ + */ +#define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */ +#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */ + +#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \ + ((CONFIG) == SYSCFG_ETH_RMII)) + +/** + * @} + */ + + +/** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config + * @{ + */ +#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */ +#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */ +#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */ +#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */ + + + + +#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */ +#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */ +#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */ +#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/ +#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */ +#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */ +#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */ +#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */ + +/** + * @} + */ + +#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \ + (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \ + (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \ + (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3)) + + +#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE)) + + +/** @defgroup SYSCFG_Boot_Config Boot Config + * @{ + */ +#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */ +#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */ + +#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \ + ((REGISTER) == SYSCFG_BOOT_ADDR1)) + +#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE) + +/** + * @} + */ + + +/** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config + * @{ + */ +#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ +#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */ + +#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \ + ((SELECT) == SYSCFG_REGISTER_CODE)) + +#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup EXTI_Event_Input_Config Event Input Config + * @{ + */ + +#define EXTI_MODE_IT ((uint32_t)0x00010000) +#define EXTI_MODE_EVT ((uint32_t)0x00020000) +#define EXTI_RISING_EDGE ((uint32_t)0x00100000) +#define EXTI_FALLING_EDGE ((uint32_t)0x00200000) + +#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE)) +#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT)) + +#define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */ +#define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */ +#define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */ +#define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */ +#define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */ +#define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */ +#define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */ +#define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */ +#define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */ +#define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */ +#define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */ +#define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */ +#define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */ +#define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */ +#define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */ +#define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */ +#define EXTI_LINE16 ((uint32_t)0x10) +#define EXTI_LINE17 ((uint32_t)0x11) +#define EXTI_LINE18 ((uint32_t)0x12) +#define EXTI_LINE19 ((uint32_t)0x13) +#define EXTI_LINE20 ((uint32_t)0x14) +#define EXTI_LINE21 ((uint32_t)0x15) +#define EXTI_LINE22 ((uint32_t)0x16) +#define EXTI_LINE23 ((uint32_t)0x17) +#define EXTI_LINE24 ((uint32_t)0x18) +#define EXTI_LINE25 ((uint32_t)0x19) +#define EXTI_LINE26 ((uint32_t)0x1A) +#define EXTI_LINE27 ((uint32_t)0x1B) +#define EXTI_LINE28 ((uint32_t)0x1C) +#define EXTI_LINE29 ((uint32_t)0x1D) +#define EXTI_LINE30 ((uint32_t)0x1E) +#define EXTI_LINE31 ((uint32_t)0x1F) +#define EXTI_LINE32 ((uint32_t)0x20) +#define EXTI_LINE33 ((uint32_t)0x21) +#define EXTI_LINE34 ((uint32_t)0x22) +#define EXTI_LINE35 ((uint32_t)0x23) +#define EXTI_LINE36 ((uint32_t)0x24) +#define EXTI_LINE37 ((uint32_t)0x25) +#define EXTI_LINE38 ((uint32_t)0x26) +#define EXTI_LINE39 ((uint32_t)0x27) + +#define EXTI_LINE40 ((uint32_t)0x28) +#define EXTI_LINE41 ((uint32_t)0x29) +#define EXTI_LINE42 ((uint32_t)0x2A) +#define EXTI_LINE43 ((uint32_t)0x2B) +#define EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */ +/* EXTI_LINE45 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE46 ((uint32_t)0x2E) +#else +/* EXTI_LINE46 Reserved */ +#endif /* DUAL_CORE */ +#define EXTI_LINE47 ((uint32_t)0x2F) +#define EXTI_LINE48 ((uint32_t)0x30) +#define EXTI_LINE49 ((uint32_t)0x31) +#define EXTI_LINE50 ((uint32_t)0x32) +#define EXTI_LINE51 ((uint32_t)0x33) +#define EXTI_LINE52 ((uint32_t)0x34) +#define EXTI_LINE53 ((uint32_t)0x35) +#define EXTI_LINE54 ((uint32_t)0x36) +#define EXTI_LINE55 ((uint32_t)0x37) +#define EXTI_LINE56 ((uint32_t)0x38) +#define EXTI_LINE57 ((uint32_t)0x39) +#define EXTI_LINE58 ((uint32_t)0x3A) +#define EXTI_LINE59 ((uint32_t)0x3B) +#define EXTI_LINE60 ((uint32_t)0x3C) +#define EXTI_LINE61 ((uint32_t)0x3D) +#define EXTI_LINE62 ((uint32_t)0x3E) +#define EXTI_LINE63 ((uint32_t)0x3F) +#define EXTI_LINE64 ((uint32_t)0x40) +#define EXTI_LINE65 ((uint32_t)0x41) +#define EXTI_LINE66 ((uint32_t)0x42) +#define EXTI_LINE67 ((uint32_t)0x43) +#define EXTI_LINE68 ((uint32_t)0x44) +#define EXTI_LINE69 ((uint32_t)0x45) +#define EXTI_LINE70 ((uint32_t)0x46) +#define EXTI_LINE71 ((uint32_t)0x47) +#define EXTI_LINE72 ((uint32_t)0x48) +#define EXTI_LINE73 ((uint32_t)0x49) +#define EXTI_LINE74 ((uint32_t)0x4A) +#define EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */ +#define EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */ +#if defined(DUAL_CORE) +#define EXTI_LINE77 ((uint32_t)0x4D) +#define EXTI_LINE78 ((uint32_t)0x4E) +#define EXTI_LINE79 ((uint32_t)0x4F) +#define EXTI_LINE80 ((uint32_t)0x50) +#else +/* EXTI_LINE77 Reserved */ +/* EXTI_LINE78 Reserved */ +/* EXTI_LINE79 Reserved */ +/* EXTI_LINE80 Reserved */ +#endif /* DUAL_CORE */ +/* EXTI_LINE81 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE82 ((uint32_t)0x52) +#else +/* EXTI_LINE82 Reserved */ +#endif /* DUAL_CORE */ +/* EXTI_LINE83 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE84 ((uint32_t)0x54) +#else +/* EXTI_LINE84 Reserved */ +#endif /* DUAL_CORE */ +#define EXTI_LINE85 ((uint32_t)0x55) +#define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */ +#define EXTI_LINE87 ((uint32_t)0x57) +#define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */ +#define EXTI_LINE89 ((uint32_t)0x59) /* Not available in all family lines */ +#define EXTI_LINE90 ((uint32_t)0x5A) /* Not available in all family lines */ +#define EXTI_LINE91 ((uint32_t)0x5B) /* Not available in all family lines */ + +#if defined(DUAL_CORE) +#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ + ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84) || \ + ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) +#else +#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ + ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) +#endif /* DUAL_CORE */ + +#if defined(DUAL_CORE) +#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ + ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE78) || \ + ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82)) +#else +#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ + ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ + ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) +#else +#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ + ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \ + ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53)) +#elif (POWER_DOMAINS_NUMBER == 3U) +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE88)) +#else +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88)) +#endif /*DUAL_CORE*/ + + +#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/ +#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/ +#if defined (LPTIM4) +#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/ +#else +#define LPTIM2_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM2 out selected as D3 domain pendclear source*/ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/ +#else +#define LPTIM3_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM3 out selected as D3 domain pendclear source*/ +#endif /* LPTIM5 */ +#if defined (LPTIM4) && defined (LPTIM5) +#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ + ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR)) +#else +#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ + ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR)) +#endif /* LPTIM4 LPTIM5 */ +/** + * @} + */ + + +/** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config + * @{ + */ +#define FMC_SWAPBMAP_DISABLE (0x00000000U) +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0 +#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1 + +#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \ + ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \ + ((__MODE__) == FMC_SWAPBMAP_SDRAMB2)) +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ +#if defined(DUAL_CORE) +/** @defgroup ART_Exported_Macros ART Exported Macros + * @{ + */ + +/** @brief ART Enable Macro. + * Enable the Cortex-M4 ART cache. + */ +#define __HAL_ART_ENABLE() SET_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Disable Macro. + * Disable the Cortex-M4 ART cache. + */ +#define __HAL_ART_DISABLE() CLEAR_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Cache BaseAddress Config. + * Configure the Cortex-M4 ART cache Base Address. + */ +#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL)) + +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief SYSCFG Break AXIRAM double ECC lock. + * Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML) + +/** @brief SYSCFG Break ITCM double ECC lock. + * Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML) + +/** @brief SYSCFG Break DTCM double ECC lock. + * Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML) + +/** @brief SYSCFG Break SRAM1 double ECC lock. + * Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L) + +/** @brief SYSCFG Break SRAM2 double ECC lock. + * Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L) + +/** @brief SYSCFG Break SRAM3 double ECC lock. + * Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L) + +/** @brief SYSCFG Break SRAM4 double ECC lock. + * Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L) + +/** @brief SYSCFG Break Backup SRAM double ECC lock. + * Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML) + +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L) + +/** @brief SYSCFG Break FLASH double ECC lock. + * Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL) + +#if defined(DUAL_CORE) +/** @brief SYSCFG Break Cortex-M4 Lockup lock. + * Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L) +#endif /* DUAL_CORE */ + +#if !defined(SYSCFG_PMCR_BOOSTEN) +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of : + * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 + * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#endif /* !SYSCFG_PMCR_BOOSTEN */ +/** + * @} + */ + +/** @defgroup DBG_Exported_Macros DBG Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1)) + +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14)) +#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1)) +#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1)) +#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2)) +#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_FREEZE_I2C5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) +#define __HAL_DBGMCU_FREEZE_TIM23() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_FREEZE_TIM24() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ + +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8)) +#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15)) +#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16)) +#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17)) +#define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM)) + +#define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4)) +#define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2)) +#define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3)) +#define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4)) +#define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC)) +#define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1)) + + +#define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1)) + +#define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2)) +#define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3)) +#define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4)) +#define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5)) +#define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6)) +#define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7)) +#define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12)) +#define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13)) +#define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14)) +#define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1)) +#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1)) +#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2)) +#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_UnFreeze_I2C5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) +#define __HAL_DBGMCU_UnFreeze_TIM23() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_UnFreeze_TIM24() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ + +#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1)) +#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8)) +#define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15)) +#define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16)) +#define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17)) +#define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM)) + +#define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4)) +#define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2)) +#define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3)) +#define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4)) +#define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5)) +#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC)) +#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1)) + + +#if defined(DUAL_CORE) +#define __HAL_DBGMCU_FREEZE2_IWDG2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG2)) +#define __HAL_DBGMCU_FREEZE2_WWDG2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2)) + +#define __HAL_DBGMCU_UnFreeze2_IWDG2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2)) +#define __HAL_DBGMCU_UnFreeze2_WWDG2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2)) + + +#define __HAL_DBGMCU_FREEZE2_WWDG1() (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1)) + +#define __HAL_DBGMCU_FREEZE2_TIM2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2)) +#define __HAL_DBGMCU_FREEZE2_TIM3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3)) +#define __HAL_DBGMCU_FREEZE2_TIM4() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4)) +#define __HAL_DBGMCU_FREEZE2_TIM5() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5)) +#define __HAL_DBGMCU_FREEZE2_TIM6() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6)) +#define __HAL_DBGMCU_FREEZE2_TIM7() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7)) +#define __HAL_DBGMCU_FREEZE2_TIM12() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12)) +#define __HAL_DBGMCU_FREEZE2_TIM13() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13)) +#define __HAL_DBGMCU_FREEZE2_TIM14() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14)) +#define __HAL_DBGMCU_FREEZE2_LPTIM1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1)) +#define __HAL_DBGMCU_FREEZE2_I2C1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1)) +#define __HAL_DBGMCU_FREEZE2_I2C2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2)) +#define __HAL_DBGMCU_FREEZE2_I2C3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3)) +#define __HAL_DBGMCU_FREEZE2_FDCAN() (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN)) + + +#define __HAL_DBGMCU_FREEZE2_TIM1() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1)) +#define __HAL_DBGMCU_FREEZE2_TIM8() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8)) +#define __HAL_DBGMCU_FREEZE2_TIM15() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15)) +#define __HAL_DBGMCU_FREEZE2_TIM16() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16)) +#define __HAL_DBGMCU_FREEZE2_TIM17() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17)) +#define __HAL_DBGMCU_FREEZE2_HRTIM() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM)) + +#define __HAL_DBGMCU_FREEZE2_I2C4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4)) +#define __HAL_DBGMCU_FREEZE2_LPTIM2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2)) +#define __HAL_DBGMCU_FREEZE2_LPTIM3() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3)) +#define __HAL_DBGMCU_FREEZE2_LPTIM4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4)) +#define __HAL_DBGMCU_FREEZE2_LPTIM5() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5)) +#define __HAL_DBGMCU_FREEZE2_RTC() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC)) +#define __HAL_DBGMCU_FREEZE2_IWDG1() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1)) + +#define __HAL_DBGMCU_UnFreeze2_WWDG1() (DBGMCU->APB3FZ2 &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1)) + +#define __HAL_DBGMCU_UnFreeze2_TIM2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2)) +#define __HAL_DBGMCU_UnFreeze2_TIM3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3)) +#define __HAL_DBGMCU_UnFreeze2_TIM4() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4)) +#define __HAL_DBGMCU_UnFreeze2_TIM5() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5)) +#define __HAL_DBGMCU_UnFreeze2_TIM6() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6)) +#define __HAL_DBGMCU_UnFreeze2_TIM7() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7)) +#define __HAL_DBGMCU_UnFreeze2_TIM12() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12)) +#define __HAL_DBGMCU_UnFreeze2_TIM13() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13)) +#define __HAL_DBGMCU_UnFreeze2_TIM14() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1)) +#define __HAL_DBGMCU_UnFreeze2_I2C1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1)) +#define __HAL_DBGMCU_UnFreeze2_I2C2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2)) +#define __HAL_DBGMCU_UnFreeze2_I2C3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3)) +#define __HAL_DBGMCU_UnFreeze2_FDCAN() (DBGMCU->APB1HFZ2 &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN)) + + +#define __HAL_DBGMCU_UnFreeze2_TIM1() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM1)) +#define __HAL_DBGMCU_UnFreeze2_TIM8() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM8)) +#define __HAL_DBGMCU_UnFreeze2_TIM15() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM15)) +#define __HAL_DBGMCU_UnFreeze2_TIM16() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM16)) +#define __HAL_DBGMCU_UnFreeze2_TIM17() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM17)) +#define __HAL_DBGMCU_UnFreeze2_HRTIM() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM)) + +#define __HAL_DBGMCU_UnFreeze2_I2C4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_I2C4)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM3() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM5() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5)) +#define __HAL_DBGMCU_UnFreeze2_RTC() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_RTC)) +#define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1)) + +#endif /*DUAL_CORE*/ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +/** @defgroup HAL_Group1 Initialization and de-initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); + +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @defgroup HAL_Group2 HAL Control functions + * + */ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +#if defined(SYSCFG_PMCR_EPIS_SEL) +void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); +#endif /* SYSCFG_PMCR_EPIS_SEL */ +void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); +#if defined(SYSCFG_PMCR_BOOSTEN) +void HAL_SYSCFG_EnableBOOST(void); +void HAL_SYSCFG_DisableBOOST(void); +#endif /* SYSCFG_PMCR_BOOSTEN */ + +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) +void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/ + +#if defined(DUAL_CORE) +void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); +void HAL_SYSCFG_EnableCM7BOOT(void); +void HAL_SYSCFG_DisableCM7BOOT(void); +void HAL_SYSCFG_EnableCM4BOOT(void); +void HAL_SYSCFG_DisableCM4BOOT(void); +#endif /*DUAL_CORE*/ +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +void HAL_SYSCFG_EnableIOSpeedOptimize(void); +void HAL_SYSCFG_DisableIOSpeedOptimize(void); +void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode); +void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#if defined(SYSCFG_CCCR_NCC_MMC) +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#endif /* SYSCFG_CCCR_NCC_MMC */ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +#if defined(DUAL_CORE) +void HAL_EnableDomain2DBGSleepMode(void); +void HAL_DisableDomain2DBGSleepMode(void); +void HAL_EnableDomain2DBGStopMode(void); +void HAL_DisableDomain2DBGStopMode(void); +void HAL_EnableDomain2DBGStandbyMode(void); +void HAL_DisableDomain2DBGStandbyMode(void); +#endif /*DUAL_CORE*/ +#if defined(DBGMCU_CR_DBG_STOPD3) +void HAL_EnableDomain3DBGStopMode(void); +void HAL_DisableDomain3DBGStopMode(void); +#endif /*DBGMCU_CR_DBG_STOPD3*/ +#if defined(DBGMCU_CR_DBG_STANDBYD3) +void HAL_EnableDomain3DBGStandbyMode(void); +void HAL_DisableDomain3DBGStandbyMode(void); +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ +void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ); +void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +#if defined(DUAL_CORE) +void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line); +#endif /*DUAL_CORE*/ +void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line); +void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); +#if defined(DUAL_CORE) +void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); +#endif /*DUAL_CORE*/ +void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc); +void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig); +uint32_t HAL_GetFMCMemorySwappingConfig(void); +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h new file mode 100644 index 0000000..2645c28 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CORTEX_H +#define STM32H7xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +#if !defined(CORE_CM4) +#define MPU_REGION_NUMBER8 ((uint8_t)0x08) +#define MPU_REGION_NUMBER9 ((uint8_t)0x09) +#define MPU_REGION_NUMBER10 ((uint8_t)0x0A) +#define MPU_REGION_NUMBER11 ((uint8_t)0x0B) +#define MPU_REGION_NUMBER12 ((uint8_t)0x0C) +#define MPU_REGION_NUMBER13 ((uint8_t)0x0D) +#define MPU_REGION_NUMBER14 ((uint8_t)0x0E) +#define MPU_REGION_NUMBER15 ((uint8_t)0x0F) +#endif /* !defined(CORE_CM4) */ + +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + + + +/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier + * @{ + */ +#define CM7_CPUID ((uint32_t)0x00000003) + +#if defined(DUAL_CORE) +#define CM4_CPUID ((uint32_t)0x00000001) +#endif /*DUAL_CORE*/ +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +uint32_t HAL_GetCurrentCPUID(void); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) + +#define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#if !defined(CORE_CM4) +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7) || \ + ((NUMBER) == MPU_REGION_NUMBER8) || \ + ((NUMBER) == MPU_REGION_NUMBER9) || \ + ((NUMBER) == MPU_REGION_NUMBER10) || \ + ((NUMBER) == MPU_REGION_NUMBER11) || \ + ((NUMBER) == MPU_REGION_NUMBER12) || \ + ((NUMBER) == MPU_REGION_NUMBER13) || \ + ((NUMBER) == MPU_REGION_NUMBER14) || \ + ((NUMBER) == MPU_REGION_NUMBER15)) +#else +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) +#endif /* !defined(CORE_CM4) */ + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CORTEX_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h new file mode 100644 index 0000000..69101d6 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DEF +#define STM32H7xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +#define UNUSED(x) ((void)(x)) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5 */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__CC_ARM) /* ARM Compiler */ + #define ALIGN_32BYTES(buf) __align(32) buf +#endif + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DEF */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h new file mode 100644 index 0000000..82f6f21 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -0,0 +1,1333 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DMA_H +#define STM32H7xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified stream. + This parameter can be a value of @ref DMA_Request_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Transfer complete level structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + void *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */ +#define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */ +#define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */ + +/** + * @} + */ + +/** @defgroup DMA_Request_selection DMA Request selection + * @brief DMA Request selection + * @{ + */ +/* DMAMUX1 requests */ +#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ + +#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ +#define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ +#define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ +#define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ +#define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ + +#define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */ +#define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */ + +#define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ +#define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ +#define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ + +#define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ + +#define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ +#define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ + +#define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ +#define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ +#define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ +#define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ + +#define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ + +#define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ + +#define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ +#define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ +#define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ +#define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ +#define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ +#define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ + +#define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ +#define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ +#define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ +#define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ +#define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ +#define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ +#define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ + +#define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ +#define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ +#define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ +#define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ +#define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ +#define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ + +#define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ +#define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ + +#define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ +#define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ +#define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ +#define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ + +#define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ +#define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ + +#define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ +#define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ + +#define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ +#define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ + +#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ + +#if defined (PSSI) +#define DMA_REQUEST_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ +#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */ +#else +#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif /* PSSI */ + +#define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ +#define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ + +#define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ + +#define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ +#define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ +#define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ +#define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ + +#define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ +#define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ +#define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ +#define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ + +#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ +#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ + +#if defined(SAI2) +#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ +#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ +#endif /* SAI2 */ + +#define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ +#define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ + +#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ +#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ + +#if defined(HRTIM1) +#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ +#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6*/ +#endif /* HRTIM1 */ + +#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ +#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ +#define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ +#define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ + +#define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ +#define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ +#define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ + +#define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ + +#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ + +#if defined(SAI3) +#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ +#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif /* SAI3 */ + +#if defined(ADC3) +#define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */ +#endif /* ADC3 */ + +#if defined(UART9) +#define DMA_REQUEST_UART9_RX 116U /*!< DMAMUX1 UART9 request */ +#define DMA_REQUEST_UART9_TX 117U /*!< DMAMUX1 UART9 request */ +#endif /* UART9 */ + +#if defined(USART10) +#define DMA_REQUEST_USART10_RX 118U /*!< DMAMUX1 USART10 request */ +#define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */ +#endif /* USART10 */ + +#if defined(FMAC) +#define DMA_REQUEST_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ +#define DMA_REQUEST_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ +#endif /* FMAC */ + +#if defined(CORDIC) +#define DMA_REQUEST_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ +#define DMA_REQUEST_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ +#endif /* CORDIC */ + +#if defined(I2C5) +#define DMA_REQUEST_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ +#define DMA_REQUEST_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ +#endif /* I2C5 */ + +#if defined(TIM23) +#define DMA_REQUEST_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ +#define DMA_REQUEST_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ +#define DMA_REQUEST_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ +#define DMA_REQUEST_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ +#define DMA_REQUEST_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ +#define DMA_REQUEST_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ +#endif /* TIM23 */ + +#if defined(TIM24) +#define DMA_REQUEST_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ +#define DMA_REQUEST_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ +#define DMA_REQUEST_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ +#define DMA_REQUEST_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ +#define DMA_REQUEST_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ +#define DMA_REQUEST_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ +#endif /* TIM24 */ + +/* DMAMUX2 requests */ +#define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ +#define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ +#define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ +#define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ +#define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ +#define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ +#define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ +#define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ +#define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ +#define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ +#define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ +#define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ +#define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ +#define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ +#define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ +#if defined(SAI4) +#define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ +#define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ +#endif /* SAI4 */ +#if defined(ADC3) +#define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */ +#endif /* ADC3 */ +#if defined(DAC2) +#define BDMA_REQUEST_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ +#endif /* DAC2 */ +#if defined(DFSDM2_Channel0) +#define BDMA_REQUEST_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 request */ +#endif /* DFSDM1_Channel0 */ + +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ +#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ +#define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) /*!< Double buffer mode with first target memory M0 */ +#define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) +#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) +#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) +#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) +#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) +#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) +#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) +#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) +#define DMA_IT_FE ((uint32_t)0x00000080U) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) +#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) +#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) +#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) +#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) +#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) +#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) +#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) +#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) +#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) +#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) +#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) +#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) +#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) +#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) +#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) +#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) +#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) +#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) +#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) +/** + * @} + */ + +/** @defgroup BDMA_flag_definitions BDMA flag definitions + * @brief BDMA flag definitions + * @{ + */ +#define BDMA_FLAG_GL0 ((uint32_t)0x00000001) +#define BDMA_FLAG_TC0 ((uint32_t)0x00000002) +#define BDMA_FLAG_HT0 ((uint32_t)0x00000004) +#define BDMA_FLAG_TE0 ((uint32_t)0x00000008) +#define BDMA_FLAG_GL1 ((uint32_t)0x00000010) +#define BDMA_FLAG_TC1 ((uint32_t)0x00000020) +#define BDMA_FLAG_HT1 ((uint32_t)0x00000040) +#define BDMA_FLAG_TE1 ((uint32_t)0x00000080) +#define BDMA_FLAG_GL2 ((uint32_t)0x00000100) +#define BDMA_FLAG_TC2 ((uint32_t)0x00000200) +#define BDMA_FLAG_HT2 ((uint32_t)0x00000400) +#define BDMA_FLAG_TE2 ((uint32_t)0x00000800) +#define BDMA_FLAG_GL3 ((uint32_t)0x00001000) +#define BDMA_FLAG_TC3 ((uint32_t)0x00002000) +#define BDMA_FLAG_HT3 ((uint32_t)0x00004000) +#define BDMA_FLAG_TE3 ((uint32_t)0x00008000) +#define BDMA_FLAG_GL4 ((uint32_t)0x00010000) +#define BDMA_FLAG_TC4 ((uint32_t)0x00020000) +#define BDMA_FLAG_HT4 ((uint32_t)0x00040000) +#define BDMA_FLAG_TE4 ((uint32_t)0x00080000) +#define BDMA_FLAG_GL5 ((uint32_t)0x00100000) +#define BDMA_FLAG_TC5 ((uint32_t)0x00200000) +#define BDMA_FLAG_HT5 ((uint32_t)0x00400000) +#define BDMA_FLAG_TE5 ((uint32_t)0x00800000) +#define BDMA_FLAG_GL6 ((uint32_t)0x01000000) +#define BDMA_FLAG_TC6 ((uint32_t)0x02000000) +#define BDMA_FLAG_HT6 ((uint32_t)0x04000000) +#define BDMA_FLAG_TE6 ((uint32_t)0x08000000) +#define BDMA_FLAG_GL7 ((uint32_t)0x10000000) +#define BDMA_FLAG_TC7 ((uint32_t)0x20000000) +#define BDMA_FLAG_HT7 ((uint32_t)0x40000000) +#define BDMA_FLAG_TE7 ((uint32_t)0x80000000) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__: specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__: DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ +((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ +((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN)) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__: DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\ + (uint32_t)0x00000000) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__: DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ + (uint32_t)0x00000000) + +/** + * @brief Returns the current BDMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(BDMA1) +#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#else +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#endif /* BDMA1 */ + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#if defined(BDMA1) +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#else +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#endif /* BDMA1 */ + +#define DMA_TO_BDMA_IT(__DMA_IT__) \ +((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ + (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\ + (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ + (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\ + ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\ + ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\ + ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\ + (uint32_t)0x00000000) + + +#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__))) + +#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ + (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__))) + +#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ + (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__)))) + +#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__)))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__: DMA handle + * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\ + (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__))) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__: DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\ + (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR)) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32h7xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Types DMA Private Types + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ + +#if defined(TIM24) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG)) +#elif defined(ADC3) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3)) +#else +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX)) +#endif /* TIM24 */ + +#if defined(ADC3) +#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3)) +#else +#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0)) +#endif /* ADC3 */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL) || \ + ((MODE) == DMA_DOUBLE_BUFFER_M0) || \ + ((MODE) == DMA_DOUBLE_BUFFER_M1)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h new file mode 100644 index 0000000..cde5755 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DMA_EX_H +#define STM32H7xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ + +}HAL_DMA_MemoryTypeDef; + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE*/ + + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event. + This parameters can be in the range 1 to 32 */ + +}HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event. + This parameters can be in the range 1 to 32 */ + +}HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMAEx_Exported_Constants DMA Exported Constants + * @brief DMAEx Exported constants + * @{ + */ + +/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection + * @brief DMAEx MUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ + +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */ +#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */ +#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */ +#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */ +#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */ +#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */ +#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */ +#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */ +#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */ +#define HAL_DMAMUX2_SYNC_EXTI0 14U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX2_SYNC_EXTI2 15U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */ + +/** + * @} + */ + +/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection + * @brief DMAEx MUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + + +/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection + * @brief DMAEx MUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ + +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */ +#if defined(LPTIM4) +#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */ +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */ +#endif /* LPTIM5 */ +#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */ +#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */ +#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */ +#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */ +#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */ +#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */ +#if defined(ADC3) +#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */ +#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */ +#endif /* ADC3 */ +#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */ +#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */ + + +/** + * @} + */ + +/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection + * @brief DMAEx MUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO) +#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO) +#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h new file mode 100644 index 0000000..0a14686 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h @@ -0,0 +1,1855 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_eth.h + * @author MCD Application Team + * @brief Header file of ETH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_ETH_H +#define STM32H7xx_HAL_ETH_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined(ETH) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ETH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef ETH_TX_DESC_CNT +#define ETH_TX_DESC_CNT 4U +#endif /* ETH_TX_DESC_CNT */ + +#ifndef ETH_RX_DESC_CNT +#define ETH_RX_DESC_CNT 4U +#endif /* ETH_RX_DESC_CNT */ + +#ifndef ETH_SWRESET_TIMEOUT +#define ETH_SWRESET_TIMEOUT 500U +#endif /* ETH_SWRESET_TIMEOUT */ + +#ifndef ETH_MDIO_BUS_TIMEOUT +#define ETH_MDIO_BUS_TIMEOUT 1000U +#endif /* ETH_MDIO_BUS_TIMEOUT */ + +#ifndef ETH_MAC_US_TICK +#define ETH_MAC_US_TICK 1000000U +#endif /* ETH_MAC_US_TICK */ + +/*********************** Descriptors struct def section ************************/ +/** @defgroup ETH_Exported_Types ETH Exported Types + * @{ + */ + +/** + * @brief ETH DMA Descriptor structure definition + */ +typedef struct +{ + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + uint32_t BackupAddr0; /* used to store rx buffer 1 address */ + uint32_t BackupAddr1; /* used to store rx buffer 2 address */ +} ETH_DMADescTypeDef; +/** + * + */ + +/** + * @brief ETH Buffers List structure definition + */ +typedef struct __ETH_BufferTypeDef +{ + uint8_t *buffer; /*gState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + } while(0) +#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @brief Enables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT source enabled or disabled. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The ETH DMA IT Source enabled or disabled + */ +#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The state of ETH DMA IT (SET or RESET) + */ +#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Clears the specified ETHERNET DMA flag. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) + +/** + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts + * @retval The state of ETH MAC IT (SET or RESET). + */ +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) + +/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ +#define ETH_WAKEUP_EXTI_LINE 0x00400000U /* !< 86 - 64 = 22 */ + +/** + * @brief Enable the ETH WAKEUP Exti Line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__)) + +/** + * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI ETH WAKEUP Line Status. + */ +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__)) + +/** + * @brief Clear the ETH WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__)) + +#if defined(DUAL_CORE) +/** + * @brief Enable the ETH WAKEUP Exti Line by Core2. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__)) + +/** + * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI ETH WAKEUP Line Status. + */ +#define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__)) + +/** + * @brief Clear the ETH WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__)) +#endif /* DUAL_CORE */ + +/** + * @brief enable rising edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \ + (EXTI->RTSR3 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\ + (EXTI->FTSR3 |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\ + (EXTI->FTSR3 |= (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__)) + +#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__)) +/** + * @} + */ + +/* Include ETH HAL Extension module */ +#include "stm32h7xx_hal_eth_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de initialization functions **********************************/ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode); +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); + +#ifdef HAL_ETH_USE_PTP +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset); +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); +#endif /* HAL_ETH_USE_PTP */ + +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); + +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue); +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue); + +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth); +void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxAllocateCallback(uint8_t **buff); +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); +void HAL_ETH_TxFreeCallback(uint32_t *buff); +void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* MAC & DMA Configuration APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, + uint32_t VLANIdentifier); + +/* MAC L2 Packet Filtering APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); + +/* MAC Power Down APIs *****************************************************/ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_ETH_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h new file mode 100644 index 0000000..b9580fa --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h @@ -0,0 +1,368 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_eth_ex.h + * @author MCD Application Team + * @brief Header file of ETH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_ETH_EX_H +#define STM32H7xx_HAL_ETH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(ETH) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ETHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Types ETHEx Exported Types + * @{ + */ + +/** + * @brief ETH RX VLAN structure definition + */ +typedef struct +{ + FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */ + + uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive + This parameter can be a value of + @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */ + + FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */ + + FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */ + + FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */ + + FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */ + + uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive + This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */ + + uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check + This parameter can be a value of @ref ETHEx_VLAN_Type_Check */ + + FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */ +} ETH_RxVLANConfigTypeDef; +/** + * + */ + +/** + * @brief ETH TX VLAN structure definition + */ +typedef struct +{ + FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */ + + FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */ + + uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets + This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */ +} ETH_TxVLANConfigTypeDef; +/** + * + */ + +/** + * @brief ETH L3 filter structure definition + */ +typedef struct +{ + uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6 + This parameter can be a value of @ref ETHEx_L3_Protocol */ + + uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match + This parameter can be a value of @ref ETHEx_L3_Source_Match */ + + uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match + This parameter can be a value of @ref ETHEx_L3_Destination_Match */ + + uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match + This parameter can be a value from 0 to 31 */ + + uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match + This parameter can be a value from 0 to 31 */ + + uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used + This parameter can be a value from 0x0 to 0xFFFFFFFF */ + + uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used + This parameter can be a value from 0 to 0xFFFFFFFF */ + + uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used + This parameter must be a table of 4 words (4* 32 bits) */ +} ETH_L3FilterConfigTypeDef; +/** + * + */ + +/** + * @brief ETH L4 filter structure definition + */ +typedef struct +{ + uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP + This parameter can be a value of @ref ETHEx_L4_Protocol */ + + uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match + This parameter can be a value of @ref ETHEx_L4_Source_Match */ + + uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match + This parameter can be a value of @ref ETHEx_L4_Destination_Match */ + + uint32_t SourcePort; /*!< Sets the L4 filter source port + This parameter must be a value from 0x0 to 0xFFFF */ + + uint32_t DestinationPort; /*!< Sets the L4 filter destination port + This parameter must be a value from 0x0 to 0xFFFF */ +} ETH_L4FilterConfigTypeDef; +/** + * + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants + * @{ + */ + +/** @defgroup ETHEx_LPI_Event ETHEx LPI Event + * @{ + */ +#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN +#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX +#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN +#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX +/** + * @} + */ + +/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter + * @{ + */ +#define ETH_L3_FILTER_0 0x00000000U +#define ETH_L3_FILTER_1 0x0000000CU +/** + * @} + */ + +/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter + * @{ + */ +#define ETH_L4_FILTER_0 0x00000000U +#define ETH_L4_FILTER_1 0x0000000CU +/** + * @} + */ + +/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol + * @{ + */ +#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN +#define ETH_L3_IPV4_MATCH 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match + * @{ + */ +#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM +#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM) +#define ETH_L3_SRC_ADDR_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match + * @{ + */ +#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM +#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM) +#define ETH_L3_DEST_ADDR_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol + * @{ + */ +#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN +#define ETH_L4_TCP_MATCH 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match + * @{ + */ +#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM +#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) +#define ETH_L4_SRC_PORT_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match + * @{ + */ +#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM +#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM) +#define ETH_L4_DEST_PORT_MATCH_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping + * @{ + */ +#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP +#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS +#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS +#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP +/** + * @} + */ + +/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping + * @{ + */ +#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP +#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS +#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS +#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP +/** + * @} + */ + +/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check + * @{ + */ +#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC +#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL) +#define ETH_VLANTYPECHECK_CVLAN 0x00000000U +/** + * @} + */ + +/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control + * @{ + */ +#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG) +#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE) +#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT) +#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE) +/** + * @} + */ + +/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag + * @{ + */ +#define ETH_INNER_TX_VLANTAG 0x00000001U +#define ETH_OUTER_TX_VLANTAG 0x00000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ETHEx_Exported_Functions + * @{ + */ + +/** @addtogroup ETHEx_Exported_Functions_Group1 + * @{ + */ +/* MAC ARP Offloading APIs ***************************************************/ +void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth); +void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); + +/* MAC L3 L4 Filtering APIs ***************************************************/ +void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig); +HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth); +void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); +void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable); +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig); +HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig); +void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier); + +/* Energy Efficient Ethernet APIs *********************************************/ +void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, + FunctionalState TxClockStop); +void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth); +uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_ETH_EX_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h new file mode 100644 index 0000000..91d7d95 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_EXTI_H +#define STM32H7xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ + + uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD + domain. This parameter can be a value of @ref + EXTI_PendClear_Source */ + +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x00U) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x01U) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x02U) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x03U) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x04U) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x05U) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x06U) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x07U) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x08U) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x09U) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0AU) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0BU) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0CU) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0DU) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0EU) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0FU) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x13U) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x14U) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x15U) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x19U) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x02U) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x03U) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) +#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) +#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U) +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) +#if !defined(USB2_OTG_FS) +#define EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU) +#else +#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#endif /* USB2_OTG_FS */ +#define EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU) +#if defined(DSI) +#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU) +#else +#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU) +#endif /* DSI */ +#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU) +#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U) +#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U) +#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U) +#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U) +#if defined(LPTIM4) +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U) +#else +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U) +#else +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#endif /*LPTIM5*/ +#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) +#if defined(EXTI_IMR2_IM57) +#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#else +#define EXTI_LINE_57 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x19U) +#endif /*EXTI_IMR2_IM57*/ +#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#if defined(EXTI_IMR2_IM59) +#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#else +#define EXTI_LINE_59 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x1BU) +#endif /*EXTI_IMR2_IM59*/ +#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) +#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) +#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) +#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) +#define EXTI_LINE_64 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) +#define EXTI_LINE_65 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) +#define EXTI_LINE_66 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U) +#define EXTI_LINE_67 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U) +#define EXTI_LINE_68 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) +#define EXTI_LINE_69 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) +#define EXTI_LINE_70 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) +#define EXTI_LINE_71 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) +#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) +#define EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U) +#define EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) +#if defined(ADC3) +#define EXTI_LINE_75 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) +#else +#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU) +#endif /* ADC3 */ +#if defined(SAI4) +#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#else +#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU) +#endif /* SAI4 */ +#if defined (DUAL_CORE) +#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU) +#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU) +#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU) +#define EXTI_LINE_80 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U) +#else +#define EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU) +#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU) +#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU) +#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U) +#if defined (DUAL_CORE) +#define EXTI_LINE_82 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U) +#else +#define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U) +#if defined (DUAL_CORE) +#define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U) +#else +#define EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#if defined(ETH) +#define EXTI_LINE_86 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#else +#define EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U) +#endif /* ETH */ +#define EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#if defined(DTS) +#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U) +#endif /* DTS */ +#if defined(EXTI_IMR3_IM89) +#define EXTI_LINE_89 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#endif /*EXTI_IMR3_IM89*/ +#if defined(EXTI_IMR3_IM90) +#define EXTI_LINE_90 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#endif /*EXTI_IMR3_IM90*/ +#if defined(I2C5) +#define EXTI_LINE_91 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#endif /*I2C5*/ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +#if defined(DUAL_CORE) +#define EXTI_MODE_CORE1_INTERRUPT EXTI_MODE_INTERRUPT +#define EXTI_MODE_CORE1_EVENT EXTI_MODE_EVENT +#define EXTI_MODE_CORE2_INTERRUPT 0x00000010U +#define EXTI_MODE_CORE2_EVENT 0x00000020U +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOD 0x00000003U +#define EXTI_GPIOE 0x00000004U +#define EXTI_GPIOF 0x00000005U +#define EXTI_GPIOG 0x00000006U +#define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) +#define EXTI_GPIOI 0x00000008U +#endif /*GPIOI*/ +#define EXTI_GPIOJ 0x00000009U +#define EXTI_GPIOK 0x0000000AU + +/** + * @} + */ + +/** @defgroup EXTI_PendClear_Source EXTI PendClear Source + * @brief + * @{ + */ +#define EXTI_D3_PENDCLR_SRC_NONE 0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero */ +#define EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#define EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/ +#if defined (LPTIM4) +#define EXTI_D3_PENDCLR_SRC_LPTIM4 0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif +#if defined (LPTIM5) +#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24U +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28U +#define EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16U +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) +#define EXTI_REG3 (0x02UL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) +#define EXTI_PIN_MASK 0x0000001FUL + +/** + * @brief EXTI Target and bit usage + */ +#define EXTI_TARGET_SHIFT 20U +#define EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT) +#if defined (DUAL_CORE) +#define EXTI_TARGET_MSK_CPU2 (0x04UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2) +#define EXTI_TARGET_MSK_ALL_CPU (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2) +#else +#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1) +#define EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1 +#endif /* DUAL_CORE */ +#define EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#if defined (DUAL_CORE) +#define EXTI_MODE_MASK (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT) +#else +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) +#endif /* DUAL_CORE */ + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if (STM32H7_DEV_ID == 0x483UL) +#define EXTI_LINE_NB 92UL +#elif (STM32H7_DEV_ID == 0x480UL) +#define EXTI_LINE_NB 89UL +#else +#define EXTI_LINE_NB 88UL +#endif /* EXTI_LINE_91 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_PROPERTY(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) +#if defined (DUAL_CORE) +#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)) +#else +#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)) +#endif + +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK |\ + EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \ + IS_EXTI_PROPERTY(__EXTI_LINE__) && IS_EXTI_TARGET(__EXTI_LINE__) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL)))) + +#define IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)|| \ + ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00UL) + +#if defined(GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /*GPIOI*/ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL) +#if defined (LPTIM4) && defined (LPTIM5) +#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5)) +#else +#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3)) +#endif /* LPTIM4 && LPTIM5 */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_EXTI_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h new file mode 100644 index 0000000..a4773b5 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h @@ -0,0 +1,861 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FLASH_H +#define STM32H7xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE_BANK1, + FLASH_PROC_MASSERASE_BANK1, + FLASH_PROC_PROGRAM_BANK1, + FLASH_PROC_SECTERASE_BANK2, + FLASH_PROC_MASSERASE_BANK2, + FLASH_PROC_PROGRAM_BANK2, + FLASH_PROC_ALLBANK_MASSERASE +} FLASH_ProcedureTypeDef; + + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in IT context */ + + __IO uint32_t VoltageForErase; /*!< Internal variable to provide voltage range selected by user in IT context */ + + __IO uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ + +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */ +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */ +#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */ +#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */ +#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */ +#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */ +#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */ +#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */ + +#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */ +#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */ +#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */ +#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */ +#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */ +#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */ +#define HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1 */ +#define HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1 */ + +#define HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2 /*!< Write Protection Error on Bank 2 */ +#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */ +#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */ +#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */ +#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */ +#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */ +#define HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2 /*!< ECC Double Detection Error on Bank 2 */ +#define HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2 /*!< CRC Read Error on Bank2 */ + +#define HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR /*!< Option Byte Change Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word at a specified address */ +#if defined (FLASH_OPTCR_PG_OTP) +#define FLASH_TYPEPROGRAM_OTPWORD 0x02U /*!< Program an OTP word at a specified address */ +#endif /* FLASH_OPTCR_PG_OTP */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< Write Buffer Not Empty flag */ +#define FLASH_FLAG_QW FLASH_SR_QW /*!< Wait Queue on flag */ +#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC Busy flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */ +#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< Strobe Error flag */ +#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */ +#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */ +#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */ +#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */ +#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC End of Calculation flag */ +#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */ + +#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */ +#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Write Buffer Not Empty on Bank 1 flag */ +#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Wait Queue on Bank 1 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC Busy on Bank 1 flag */ +#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */ +#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */ +#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */ +#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< Strobe Error on Bank 1 flag */ +#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */ +#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */ +#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */ +#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */ +#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC End of Calculation on Bank 1 flag */ +#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */ + +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ + FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ + FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \ + FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \ + FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ + FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ + FLASH_FLAG_RDPERR_BANK1 | FLASH_FLAG_RDSERR_BANK1 | \ + FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \ + FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#endif /* FLASH_SR_OPERR */ + +#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \ + FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \ + FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \ + FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */ + +#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */ +#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Write Buffer Not Empty on Bank 2 flag */ +#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Wait Queue on Bank 2 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC Busy on Bank 2 flag */ +#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */ +#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */ +#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */ +#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */ +#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */ +#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */ +#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */ +#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */ +#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC End of Calculation on Bank 2 flag */ +#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */ + +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ + FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ + FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \ + FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \ + FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ + FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ + FLASH_FLAG_RDPERR_BANK2 | FLASH_FLAG_RDSERR_BANK2 | \ + FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \ + FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#endif /* FLASH_SR_OPERR */ + +#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \ + FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \ + FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \ + FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Bank 1 Operation Interrupt source */ +#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE /*!< Write Protection Error on Bank 1 Interrupt source */ +#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */ +#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */ +#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ +#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */ +#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */ +#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */ +#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE /*!< Double Detection ECC Error on Bank 1 Interrupt source */ +#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */ +#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */ + +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ + FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ + FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \ + FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \ + FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \ + FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ + FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ + FLASH_IT_INCERR_BANK1 | FLASH_IT_RDPERR_BANK1 | \ + FLASH_IT_RDSERR_BANK1 | FLASH_IT_SNECCERR_BANK1 | \ + FLASH_IT_DBECCERR_BANK1 | FLASH_IT_CRCEND_BANK1 | \ + FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ + +#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */ +#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */ +#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */ +#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */ +#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ +#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */ +#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */ +#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */ +#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 Interrupt source */ +#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */ +#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */ + +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ + FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ + FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \ + FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \ + FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \ + FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ + FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ + FLASH_IT_INCERR_BANK2 | FLASH_IT_RDPERR_BANK2 | \ + FLASH_IT_RDSERR_BANK2 | FLASH_IT_SNECCERR_BANK2 | \ + FLASH_IT_DBECCERR_BANK2 | FLASH_IT_CRCEND_BANK2 | \ + FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ +/** + * @} + */ + +#if defined (FLASH_CR_PSIZE) +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE 0x00000000U /*!< Flash program/erase by 8 bits */ +#define FLASH_PSIZE_HALF_WORD FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ +#define FLASH_PSIZE_WORD FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ +#define FLASH_PSIZE_DOUBLE_WORD FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ +/** + * @} + */ +#endif /* FLASH_CR_PSIZE */ + + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU +#define FLASH_OPT_KEY1 0x08192A3BU +#define FLASH_OPT_KEY2 0x4C5D6E7FU +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */ +#if (FLASH_SECTOR_TOTAL == 128) +#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */ +#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */ +#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */ +#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */ +#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */ +#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */ +#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */ +#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */ +#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */ +#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */ +#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */ +#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */ +#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */ +#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */ +#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */ +#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */ +#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */ +#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */ +#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */ +#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */ +#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */ +#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */ +#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */ +#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */ +#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */ +#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */ +#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */ +#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */ +#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */ +#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */ +#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */ +#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */ +#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */ +#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */ +#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */ +#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */ +#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */ +#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */ +#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */ +#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */ +#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */ +#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */ +#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */ +#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */ +#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */ +#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */ +#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */ +#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */ +#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */ +#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */ +#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */ +#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */ +#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */ +#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */ +#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */ +#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */ +#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */ +#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */ +#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */ +#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */ +#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */ +#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */ +#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */ +#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */ +#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */ +#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */ +#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */ +#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */ +#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */ +#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */ +#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */ +#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */ +#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */ +#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */ +#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */ +#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */ +#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */ +#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */ +#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */ +#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */ +#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */ +#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */ +#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */ +#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */ +#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */ +#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */ +#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */ +#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */ +#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */ +#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */ +#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */ +#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */ +#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */ +#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */ +#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */ +#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */ +#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */ +#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */ +#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */ +#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */ +#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */ +#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */ +#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */ +#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */ +#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__: FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * In case of Bank 1 This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source + * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source + * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source + * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source + * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source + * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source + * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source + * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source + * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources + * @retval none + */ + +#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__)) + +#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ + __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \ + __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ + + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * In case of Bank 1 This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source + * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source + * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source + * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source + * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source + * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source + * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source + * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source + * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources + * @retval none + */ + +#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__)) + +#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ + __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \ + __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ + + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param __FLAG__: specifies the FLASH flag to check. + * In case of Bank 1 This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag + * @arg FLASH_FLAG_WBNE_BANK1 : Write Buffer Not Empty on Bank 1 flag + * @arg FLASH_FLAG_QW_BANK1 : Wait Queue on Bank 1 flag + * @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag + * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag + * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag + * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag + * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag + * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag + * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag + * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag + * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag + * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag + * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag + * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag + * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * + * In case of Bank 2 This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag + * @arg FLASH_FLAG_WBNE_BANK2 : Write Buffer Not Empty on Bank 2 flag + * @arg FLASH_FLAG_QW_BANK2 : Wait Queue on Bank 2 flag + * @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag + * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag + * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag + * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag + * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag + * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag + * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag + * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag + * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag + * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag + * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag + * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag + * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__)) + +#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU))) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \ + __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_GET_FLAG(__FLAG__) __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ + + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__: specifies the FLASH flags to clear. + * In case of Bank 1, this parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag + * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag + * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag + * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag + * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag + * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag + * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag + * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag + * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag + * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag + * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag + * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags + * @arg FLASH_FLAG_ALL_BANK1 : All Bank 1 flags + * + * In case of Bank 2, this parameter can be any combination of the following values : + * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag + * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag + * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag + * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag + * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag + * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag + * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag + * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag + * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag + * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag + * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag + * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags + * @arg FLASH_FLAG_ALL_BANK2 : All Bank 2 flags + * @retval none + */ + +#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__)) + +#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \ + __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ + +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32h7xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) +#endif /* FLASH_OPTCR_PG_OTP */ + +#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT)) +#if defined (DUAL_BANK) +#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT)) +#endif /* DUAL_BANK */ + +#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG)) +#if defined (DUAL_BANK) +#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG)) +#endif /* DUAL_BANK */ + +#if defined (DUAL_BANK) +#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE)) +#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END)) +#else +#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) <= FLASH_END)) +#endif /* DUAL_BANK */ + +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#else +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#endif /* DUAL_BANK */ + +#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U)) + +#if defined (DUAL_BANK) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) +#else +#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) +#endif /* DUAL_BANK */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank); +HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout); +HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FLASH_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h new file mode 100644 index 0000000..28bb380 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h @@ -0,0 +1,1013 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FLASH_EX_H +#define STM32H7xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASH_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ + + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ + + uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not + when RDP level decreased from Level 1 to Level 0 or during a mass erase. + This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */ + + uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). + This parameter must be a value between begin and end of a bank */ + + uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). + This parameter must be a value between PCROP Start address and end of a bank */ + + uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 + or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ + + uint32_t BootAddr0; /*!< Boot Address 0. + This parameter must be a value between begin and end of a bank */ + + uint32_t BootAddr1; /*!< Boot Address 1. + This parameter must be a value between begin and end of a bank */ +#if defined(DUAL_CORE) + uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1 + or both. + This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ + + uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0. + This parameter must be a value between begin and end of a bank */ + + uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1. + This parameter must be a value between begin and end of a bank */ +#endif /*DUAL_CORE*/ + + uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not + when RDP level decreased from Level 1 to Level 0 or during a mass erase. + This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ + + uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. + This parameter must be a value between begin address and end address of bank1 */ + + uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. + This parameter must be a value between Secure Area Start address and end address of a bank1 */ + +#if defined (FLASH_OTPBL_LOCKBL) + uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. + This parameter must be a value of @ref FLASHEx_OTP_Blocks */ +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM. + This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost. + This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeCRC; /*!< CRC Selection Type. + This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ + + uint32_t BurstSize; /*!< CRC Burst Size. + This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ + + uint32_t Bank; /*!< Select bank where CRC computation is enabled. + This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ + + uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation + This parameter must be a value of @ref FLASH_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be computed. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t CRCStartAddr; /*!< CRC Start address. + This parameter must be a value between begin address and end address of a bank */ + + uint32_t CRCEndAddr; /*!< CRC End address. + This parameter must be a value between CRC Start address and end address of a bank */ + +} FLASH_CRCInitTypeDef; + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */ +/** + * @} + */ + +#if defined (FLASH_CR_PSIZE) +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */ +#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ +#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ +#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ +/** + * @} + */ +#endif /* FLASH_CR_PSIZE */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ +#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ +#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ +#if defined (DUAL_CORE) +#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */ +#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */ +#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */ +#else /* Single core */ +#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ +#endif /*DUAL_CORE*/ +#if defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */ +#endif /* FLASH_OTPBL_LOCKBL */ +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (DUAL_CORE) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */ +#elif defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */ +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */ +#else +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD) /*!< All option byte configuration */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 0xAA00U +#define OB_RDP_LEVEL_1 0x5500U +#define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */ +#define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ +#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ +#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ +#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ +/** + * @} + */ + + + +/** @defgroup FLASHEx_Boot_Address FLASH Boot Address + * @{ + */ +#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ +#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ + +/* Unused FLASH Latency defines */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ +/** + * @} + */ + +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 0x01U /*!< Bank 1 */ +#if defined (DUAL_BANK) +#define FLASH_BANK_2 0x02U /*!< Bank 2 */ +#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ +#endif /* DUAL_BANK */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP + * @{ + */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 or during a mass erase */ +#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 128) +#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ +#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ +#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ +#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ +#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ +#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ +#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ +#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ +#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ +#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ +#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ +#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ +#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ +#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ +#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ +#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ +#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ +#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ +#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ +#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ +#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ +#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ +#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ +#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ +#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ +#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ +#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ +#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ +#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ +#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ +#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ +#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ +#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ +#else +#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY + * @{ + */ +#define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */ +#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE + * @{ + */ +#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7 + * @{ + */ +#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */ +#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */ + +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4 + * @{ + */ +#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */ +#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */ +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW + * @{ + */ +#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */ +#define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW + * @{ + */ +#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/ +#define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/ +/** + * @} + */ +#endif + +/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1 + * @{ + */ +#define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */ +#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1 + * @{ + */ +#define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */ +#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */ +/** + * @} + */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) +/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2 + * @{ + */ +#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */ +#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2 + * @{ + */ +#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */ +#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */ +/** + * @} + */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) +/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK + * @{ + */ +#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ +#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */ +/** + * @} + */ +#endif /* DUAL_BANK */ + +/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV + * @{ + */ +#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ +#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ +/** + * @} + */ + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV + * @{ + */ +#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */ +#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */ +/** + * @} + */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST + * @{ + */ +#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */ +#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED + * @{ + */ +#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + + /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type + * @{ + */ +#define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */ +#define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/ +#define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/ +#define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */ +#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ +#define OB_USER_SECURITY 0x0040U /*!< security selection */ +#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ +#if defined (DUAL_BANK) +#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ +#endif /* DUAL_BANK */ +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ +#if defined (DUAL_CORE) +#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ +#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ +#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ +#endif /*DUAL_CORE*/ +#if defined (FLASH_OPTSR_NRST_STOP_D2) +#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */ +#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_CORE) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#elif defined (FLASH_OPTSR_VDDMMC_HSLV) +#if defined (DUAL_BANK) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_VDDMMC_HSLV) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_VDDMMC_HSLV) +#endif /* DUAL_BANK */ +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#else /* Single core */ +#if defined (DUAL_BANK) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV ) +#endif /* DUAL_BANK */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION + * @{ + */ +#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ +#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ +#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP + * @{ + */ +#define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level + is decreased from Level 1 to Level 0 or during a mass erase */ +#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type + * @{ + */ +#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ +#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ +#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size + * @{ + */ +#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */ +/** + * @} + */ + +/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay + * @{ + */ +#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */ +#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */ +#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */ +#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ +/** + * @} + */ + +#if defined (FLASH_OTPBL_LOCKBL) +/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks + * @{ + */ +#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ +#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ +#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ +#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ +#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ +#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ +#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ +#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ +#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ +#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ +#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ +#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ +#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ +#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ +#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ +#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ +#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */ +/** + * @} + */ +#endif /* FLASH_OTPBL_LOCKBL */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Address + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) + +#if defined (FLASH_CR_PSIZE) +/** + * @brief Set the FLASH Program/Erase parallelism. + * @param __PSIZE__ FLASH Program/Erase parallelism + * This parameter can be a value of @ref FLASH_Program_Parallelism + * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) + * @retval none + */ +#if defined (DUAL_BANK) +#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ + MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ + MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) +#else +#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) +#endif /* DUAL_BANK */ + +/** + * @brief Get the FLASH Program/Erase parallelism. + * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2) + * @retval FLASH Program/Erase parallelism + * This return value can be a value of @ref FLASH_Program_Parallelism + */ +#if defined (DUAL_BANK) +#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ + READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ + READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) +#else +#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) +#endif /* DUAL_BANK */ + +#endif /* FLASH_CR_PSIZE */ + +/** + * @brief Set the FLASH Programming Delay. + * @param __DELAY__ FLASH Programming Delay + * This parameter can be a value of @ref FLASHEx_Programming_Delay + * @retval none + */ +#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) + +/** + * @brief Get the FLASH Programming Delay. + * @retval FLASH Programming Delay + * This return value can be a value of @ref FLASHEx_Programming_Delay + */ +#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) + /** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Program operation functions *************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); +#if defined (DUAL_BANK) +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); +#endif /* DUAL_BANK */ + +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ + +/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#if defined (FLASH_CR_PSIZE) +#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) +#endif /* FLASH_CR_PSIZE */ + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ + (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) + +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ + ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) + +#if (FLASH_SECTOR_TOTAL == 8U) +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#else +#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U) +#endif /* FLASH_SECTOR_TOTAL == 8U */ + +#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ + ((CONFIG) == OB_PCROP_RDP_ERASE)) + +#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ + ((CONFIG) == OB_SECURE_RDP_ERASE)) + +#if defined (DUAL_BANK) +#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) +#endif /* DUAL_BANK */ + +#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE)) +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + +#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) +#if defined (DUAL_CORE) +#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW)) +#endif /* DUAL_CORE */ +#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) + +#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \ + ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) + +#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) + +#if defined (DUAL_CORE) +#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE)) + +#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE)) +#endif /* DUAL_CORE */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) +#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2)) + +#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2)) +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \ + ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB)) +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE)) +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ + (((TYPE) & ~OB_USER_ALL) == 0U)) + +#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ + ((VALUE) == OB_BOOT_ADD1) || \ + ((VALUE) == OB_BOOT_ADD_BOTH)) + +#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ + ((VALUE) == FLASH_CRC_SECTORS) || \ + ((VALUE) == FLASH_CRC_BANK)) + +#if defined (FLASH_OTPBL_LOCKBL) +#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U)) +#endif /* FLASH_OTPBL_LOCKBL */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FLASH_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h new file mode 100644 index 0000000..1cd9178 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_GPIO_H +#define STM32H7xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< High speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +#if defined(DUAL_CORE) +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) +#endif + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32h7xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_GPIO_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h new file mode 100644 index 0000000..7a8edd3 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h @@ -0,0 +1,487 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_GPIO_EX_H +#define STM32H7xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */ +#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_D2PWREN ((uint8_t)0x00) /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */ +#if defined(DUAL_CORE) +#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#endif /* DUAL_CORE */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#if defined(SAI4) +#define GPIO_AF1_SAI4 ((uint8_t)0x01) /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* SAI4 */ +#define GPIO_AF1_FMC ((uint8_t)0x01) /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ + + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ +#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(FDCAN3) +#define GPIO_AF2_FDCAN3 ((uint8_t)0x02) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */ +#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */ +#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */ +#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */ +#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#if defined(HRTIM1) +#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF3_LTDC ((uint8_t)0x03) /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ +#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#if defined(USART10) +#define GPIO_AF4_USART10 ((uint8_t)0x04) /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /*USART10*/ +#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(PSSI) +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#if defined(OCTOSPIM) +#define GPIO_AF4_OCTOSPIM_P1 ((uint8_t)0x04) /* OCTOSPI Manager Port 1 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ +#if defined(FDCAN3) +#define GPIO_AF5_FDCAN3 ((uint8_t)0x05) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF6_I2C5 ((uint8_t)0x06) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(SAI3) +#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */ +#endif /* SAI3 */ +#if defined(OCTOSPIM) +#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */ +#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ +#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */ +#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */ +#if defined(SAI2) +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */ +#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#if defined(SAI4) +#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ +#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */ +#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */ +#if defined(QUADSPI) +#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if defined(OCTOSPIM) +#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 10 selection + */ +#if defined(SAI2) +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */ +#if defined(USB2_OTG_FS) +#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */ +#endif /*USB2_OTG_FS*/ +#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */ +#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */ +#if defined(QUADSPI) +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if !defined(USB2_OTG_FS) +#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /* !USB2_OTG_FS */ +#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */ +#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */ +#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */ +#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(USART10) +#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */ +#endif /* USART10 */ +#if defined(UART9) +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#endif /* UART9 */ +#if defined(ETH) +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */ +#endif /* ETH */ +#if defined(LTDC) +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /*LTDC*/ +#if defined(OCTOSPIM) +#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(USB2_OTG_FS) +#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */ +#endif /* USB2_OTG_FS */ +#if defined(OCTOSPIM) +#define GPIO_AF12_OCTOSPIM_P1 ((uint8_t)0x0C) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */ +#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(DSI) +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(PSSI) +#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */ +#if defined(TIM23) +#define GPIO_AF13_TIM23 ((uint8_t)0x0D) /* TIM23 Alternate Function mapping */ +#endif /*TIM23*/ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */ +#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ +#if defined(TIM24) +#define GPIO_AF14_TIM24 ((uint8_t)0x0E) /* TIM24 Alternate Function mapping */ +#endif /*TIM24*/ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @brief GPIO pin available on the platform + */ +/* Defines the available pins per GPIOs */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_All +#define GPIOE_PIN_AVAILABLE GPIO_PIN_All +#define GPIOF_PIN_AVAILABLE GPIO_PIN_All +#define GPIOG_PIN_AVAILABLE GPIO_PIN_All +#if defined(GPIOI) +#define GPIOI_PIN_AVAILABLE GPIO_PIN_All +#endif /*GPIOI*/ +#if defined(GPIOI) +#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All +#else +#define GPIOJ_PIN_AVAILABLE (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 ) +#endif /* GPIOI */ +#define GPIOH_PIN_AVAILABLE GPIO_PIN_All +#if defined(GPIOI) +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) +#else +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 ) +#endif /* GPIOI */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined(GPIOI) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ + ((__GPIOx__) == (GPIOH))? 7UL :\ + ((__GPIOx__) == (GPIOI))? 8UL :\ + ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ + ((__GPIOx__) == (GPIOH))? 7UL :\ + ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#endif /* GPIOI */ + +/** + * @} + */ + +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_GPIO_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h new file mode 100644 index 0000000..45f6e07 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_HSEM_H +#define STM32H7xx_HAL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HSEM + * @{ + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** + * @brief SemID to mask helper Macro. + * @param __SEMID__: semaphore ID from 0 to 31 + * @retval Semaphore Mask. + */ +#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) + +/** + * @brief Enables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1IER |= (__SEM_MASK__)) : \ + (HSEM->C2IER |= (__SEM_MASK__))) +#else +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) +#endif /* DUAL_CORE */ +/** + * @brief Disables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1IER &= ~(__SEM_MASK__)) : \ + (HSEM->C2IER &= ~(__SEM_MASK__))) +#else +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) +#endif /* DUAL_CORE */ + +/** + * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where an interrupt occurred. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + ((__SEM_MASK__) & HSEM->C1MISR) : \ + ((__SEM_MASK__) & HSEM->C2MISR1)) +#else +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) +#endif /* DUAL_CORE */ + +/** + * @brief Get the semaphores release status flags. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where Release flags rise. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (__SEM_MASK__) & HSEM->C1ISR : \ + (__SEM_MASK__) & HSEM->C2ISR) +#else +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) +#endif /* DUAL_CORE */ + +/** + * @brief Clears the HSEM Interrupt flags. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1ICR |= (__SEM_MASK__)) : \ + (HSEM->C2ICR |= (__SEM_MASK__))) +#else +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * @{ + */ + +/* HSEM semaphore take (lock) using 2-Step method ****************************/ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID); +/* HSEM semaphore fast take (lock) using 1-Step method ***********************/ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID); +/* HSEM Release **************************************************************/ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID); +/* HSEM Release All************************************************************/ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID); +/* HSEM Check semaphore state Taken or not **********************************/ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); + +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * @{ + */ +/* HSEM Set Clear Key *********************************************************/ +void HAL_HSEM_SetClearKey(uint32_t Key); +/* HSEM Get Clear Key *********************************************************/ +uint32_t HAL_HSEM_GetClearKey(void); +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group3 + * @brief HSEM Notification functions + * @{ + */ +/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/ +void HAL_HSEM_ActivateNotification(uint32_t SemMask); +/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask); +/* HSEM Free Callback (When a semaphore is released) *******************************/ +void HAL_HSEM_FreeCallback(uint32_t SemMask); +/* HSEM IRQ Handler **********************************************************/ +void HAL_HSEM_IRQHandler(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HSEM_Private_Macros HSEM Private Macros + * @{ + */ + +#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX ) + +#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX ) + +#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX ) + +#if defined(DUAL_CORE) +#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \ + ((__COREID__) == HSEM_CPU2_COREID)) +#else +#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID) +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_HSEM_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h new file mode 100644 index 0000000..f706250 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h @@ -0,0 +1,839 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_I2C_H +#define STM32H7xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32h7xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_I2C_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h new file mode 100644 index 0000000..e701b8b --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_I2C_EX_H +#define STM32H7xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#if defined(SYSCFG_PMCR_I2C5_FMP) +#define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ +#else +#define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */ +#endif /* SYSCFG_PMCR_I2C5_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_I2C_EX_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h new file mode 100644 index 0000000..a39cc0d --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h @@ -0,0 +1,868 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_mdma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_MDMA_H +#define STM32H7xx_HAL_MDMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup MDMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Types MDMA Exported Types + * @brief MDMA Exported Types + * @{ + */ + +/** + * @brief MDMA Configuration Structure definition + */ +typedef struct +{ + + uint32_t Request; /*!< Specifies the MDMA request. + This parameter can be a value of @ref MDMA_Request_selection*/ + + uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a : + a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer + This parameter can be a value of @ref MDMA_Transfer_TriggerMode */ + + uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx. + This parameter can be a value of @ref MDMA_Priority_level */ + + uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness. + This parameter can be a value of @ref MDMA_Endianness */ + + uint32_t SourceInc; /*!< Specifies if the Source increment mode . + This parameter can be a value of @ref MDMA_Source_increment_mode */ + + uint32_t DestinationInc; /*!< Specifies if the Destination increment mode . + This parameter can be a value of @ref MDMA_Destination_increment_mode */ + + uint32_t SourceDataSize; /*!< Specifies the source data size. + This parameter can be a value of @ref MDMA_Source_data_size */ + + uint32_t DestDataSize; /*!< Specifies the destination data size. + This parameter can be a value of @ref MDMA_Destination_data_size */ + + + uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode. + This parameter can be a value of @ref MDMA_data_Alignment */ + + uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes), + this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/ + + uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref MDMA_Source_burst + @note : the burst may be FIXED/INCR based on SourceInc value , + the BURST must be programmed as to ensure that the burst size will be lower than than + BufferTransferLength */ + + uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref MDMA_Destination_burst + @note : the burst may be FIXED/INCR based on DestinationInc value , + the BURST must be programmed as to ensure that the burst size will be lower than than + BufferTransferLength */ + + int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset + signed value : if > 0 then increment the next block source Address by offset from where the last block ends + if < 0 then decrement the next block source Address by offset from where the last block ends + if == 0, the next block source address starts from where the last block ends + */ + + + int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset + signed value : if > 0 then increment the next block destination Address by offset from where the last block ends + if < 0 then decrement the next block destination Address by offset from where the last block ends + if == 0, the next block destination address starts from where the last block ends + */ + +}MDMA_InitTypeDef; + +/** + * @brief HAL MDMA linked list node structure definition + * @note The Linked list node allows to define a new MDMA configuration + * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). + * When CLAR register is configured to a non NULL value , each time a transfer ends, + * a new configuration (linked list node) is automatically loaded from the address given in CLAR register. + */ +typedef struct +{ + __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */ + __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */ + __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */ + __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */ + __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */ + __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */ + __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */ + __IO uint32_t Reserved; /*!< Reserved register */ + __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */ + __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */ + +}MDMA_LinkNodeTypeDef; + +/** + * @brief HAL MDMA linked list node configuration structure definition + * @note used with HAL_MDMA_LinkedList_CreateNode function + */ +typedef struct +{ + MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */ + uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */ + uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */ + uint32_t BlockDataLength; /*!< The data length of a block in bytes */ + uint32_t BlockCount; /*!< The number of blocks to be transferred */ + + uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served. + PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ + + uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served. + PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ + + +}MDMA_LinkNodeConfTypeDef; + + +/** + * @brief HAL MDMA State structure definition + */ +typedef enum +{ + HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */ + HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */ + HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */ + HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */ + HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */ + +}HAL_MDMA_StateTypeDef; + +/** + * @brief HAL MDMA Level Complete structure definition + */ +typedef enum +{ + HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */ + HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */ + HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */ + +}HAL_MDMA_LevelCompleteTypeDef; + +/** + * @brief HAL MDMA Callbacks IDs structure definition + */ +typedef enum +{ + HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */ + HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */ + HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */ + HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */ + +}HAL_MDMA_CallbackIDTypeDef; + + +/** + * @brief MDMA handle Structure definition + */ +typedef struct __MDMA_HandleTypeDef +{ + MDMA_Channel_TypeDef *Instance; /*!< Register base address */ + + MDMA_InitTypeDef Init; /*!< MDMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< MDMA locking object */ + + __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */ + + void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */ + + void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */ + + void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */ + + void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */ + + void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */ + + + MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list + (after the initial node defined by the Init struct) + this parameter is used internally by the MDMA driver + to construct the linked list node + */ + + MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list + this parameter is used internally by the MDMA driver + to construct the linked list node + */ + uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */ + + __IO uint32_t ErrorCode; /*!< MDMA Error code */ + +} MDMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Constants MDMA Exported Constants + * @brief MDMA Exported constants + * @{ + */ + +/** @defgroup MDMA_Error_Codes MDMA Error Codes + * @brief MDMA Error Codes + * @{ + */ +#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */ +#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */ +#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */ +#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */ +#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */ +#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */ +#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ +#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */ +#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */ + +/** + * @} + */ + +/** @defgroup MDMA_Request_selection MDMA Request selection + * @brief MDMA_Request_selection + * @{ + */ + +#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */ +#if defined (LTDC) +#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */ +#endif /* LTDC */ +#if defined (JPEG) +#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */ +#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */ +#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */ +#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */ +#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */ +#endif /* JPEG */ +#if defined (OCTOSPI1) +#define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag */ +#endif /* OCTOSPI1 */ +#if defined (QUADSPI) +#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */ +#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */ +#endif /* QUADSPI */ +#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */ + +#if defined (DSI) +#define MDMA_REQUEST_DSI_TEARING_EFFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */ +#define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */ +#endif /* DSI */ + +#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */ + +#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag */ +#define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) /*!< MDMA HW request is SDMMC1 Command End Flag */ + +#if defined (OCTOSPI2) +#define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U) /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U) /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag */ +#endif /* OCTOSPI2 */ + +#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */ + +/** + * @} + */ + +/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode + * @brief MDMA Transfer Trigger Mode + * @{ + */ +#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ +#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ +#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ +#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */ + +/** + * @} + */ + +/** @defgroup MDMA_Priority_level MDMA Priority level + * @brief MDMA Priority level + * @{ + */ +#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ +#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */ +#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */ +#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */ + +/** + * @} + */ + + +/** @defgroup MDMA_Endianness MDMA Endianness + * @brief MDMA Endianness + * @{ + */ +#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ +#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ +#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */ +#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode + * @brief MDMA Source increment mode + * @{ + */ +#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ +#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ +#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ +#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode + * @brief MDMA Destination increment mode + * @{ + */ +#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ +#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ +#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ +#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_data_size MDMA Source data size + * @brief MDMA Source data size + * @{ + */ +#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ +#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ +#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ +#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_data_size MDMA Destination data size + * @brief MDMA Destination data size + * @{ + */ +#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ +#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ +#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ +#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */ + +/** + * @} + */ + +/** @defgroup MDMA_data_Alignment MDMA data alignment + * @brief MDMA data alignment + * @{ + */ +#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size + All data are right aligned, in Little Endien mode. */ +#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ +#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , + Note : this mode is allowed only if the Source data size is smaller than Destination data size */ +#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_burst MDMA Source burst + * @brief MDMA Source burst + * @{ + */ +#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ +#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ +#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ +#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ +#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ +#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ +#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_burst MDMA Destination burst + * @brief MDMA Destination burst + * @{ + */ +#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ +#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ +#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ +#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ +#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ +#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ +#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ + +/** + * @} + */ + +/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions + * @brief MDMA interrupt enable definitions + * @{ + */ +#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ +#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */ +#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ +#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ +#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ + +/** + * @} + */ + +/** @defgroup MDMA_flag_definitions MDMA flag definitions + * @brief MDMA flag definitions + * @{ + */ +#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ +#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ +#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ +#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ +#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ +#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel request Active flag */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Macros MDMA Exported Macros + * @{ + */ + +/** + * @brief Enable the specified MDMA Channel. + * @param __HANDLE__: MDMA handle + * @retval None + */ +#define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN) + +/** + * @brief Disable the specified MDMA Channel. + * @param __HANDLE__: MDMA handle + * @retval None + */ +#define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN) + +/** + * @brief Get the MDMA Channel pending flags. + * @param __HANDLE__: MDMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg MDMA_FLAG_TE : Transfer Error flag. + * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. + * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. + * @arg MDMA_FLAG_BT : Block Transfer complete flag. + * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. + * @arg MDMA_FLAG_CRQA : Channel request Active flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) + +/** + * @brief Clear the MDMA Stream pending flags. + * @param __HANDLE__: MDMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg MDMA_FLAG_TE : Transfer Error flag. + * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. + * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. + * @arg MDMA_FLAG_BT : Block Transfer complete flag. + * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. + * @retval None + */ +#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__)) + +/** + * @brief Enables the specified MDMA Channel interrupts. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval None + */ +#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified MDMA Channel interrupts. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval None + */ +#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified MDMA Channel interrupt is enabled or not. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt source to check. + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval The state of MDMA_IT (SET or RESET). + */ +#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx. + * @param __HANDLE__ : MDMA handle + * @param __COUNTER__: Number of data in bytes to be transferred. + * @retval None + */ +#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) + +/** + * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer. + * @param __HANDLE__ : MDMA handle + * @retval The number of remaining data in bytes in the current MDMA Channelx transfer. + */ +#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MDMA_Exported_Functions MDMA Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData); + +HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)); +HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/* Linked list operation functions ********************************************/ +/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions + * @brief Linked list operation functions + * @{ + */ + +HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); + + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma); +void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); +uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MDMA_Private_Types MDMA Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MDMA_Private_Defines MDMA Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Variables MDMA Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Constants MDMA Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MDMA_Private_Macros MDMA Private Macros + * @{ + */ + +#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \ + ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \ + ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \ + ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) + + +#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ + ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ + ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ + ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) + +#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) + + +#if defined (OCTOSPI2) +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC)) +#else +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END)) +#endif /* OCTOSPI2 */ + +#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \ + ((__INC__) == MDMA_SRC_INC_BYTE ) || \ + ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \ + ((__INC__) == MDMA_SRC_INC_WORD ) || \ + ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \ + ((__INC__) == MDMA_SRC_DEC_BYTE) || \ + ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \ + ((__INC__) == MDMA_SRC_DEC_WORD) || \ + ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD)) + +#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \ + ((__INC__) == MDMA_DEST_INC_BYTE ) || \ + ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \ + ((__INC__) == MDMA_DEST_INC_WORD ) || \ + ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \ + ((__INC__) == MDMA_DEST_DEC_BYTE) || \ + ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \ + ((__INC__) == MDMA_DEST_DEC_WORD) || \ + ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD)) + +#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD)) + +#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) + +#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) + + +#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_128BEATS)) + + +#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \ + ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \ + ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \ + ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_128BEATS)) + + #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \ + ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_FULL_TRANSFER)) + +#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) + +#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U)) + +#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U)) + +#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Functions MDMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_MDMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h new file mode 100644 index 0000000..91a9054 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h @@ -0,0 +1,809 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PWR_H +#define STM32H7xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This + parameter can be a value of @ref + PWR_PVD_detection_level. + */ + + uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the PVD + event. This parameter can be a value of @ref + PWR_PVD_Mode. + */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector + level 0 selection : 1V95 */ +#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector + level 1 selection : 2V1 */ +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector + level 2 selection : 2V25 */ +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector + level 3 selection : 2V4 */ +#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector + level 4 selection : 2V55 */ +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector + level 5 selection : 2V7 */ +#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector + level 6 selection : 2V85 */ +#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage + (Compare internally to VREF) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (0x01U) +#define PWR_SLEEPENTRY_WFE (0x02U) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI (0x01U) +#define PWR_STOPENTRY_WFE (0x02U) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#if defined(PWR_SRDCR_VOS) +#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1) +#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) +#else +#define PWR_REGULATOR_VOLTAGE_SCALE0 (0U) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) +#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) +#endif /* PWR_SRDCR_VOS */ +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +/* PWR CPU flag */ +#define PWR_FLAG_STOP (0x01U) +#if defined (PWR_CPUCR_SBF_D2) +#define PWR_FLAG_SB_D1 (0x02U) +#define PWR_FLAG_SB_D2 (0x03U) +#endif /* defined (PWR_CPUCR_SBF_D2) */ +#define PWR_FLAG_SB (0x04U) +#if defined (DUAL_CORE) +#define PWR_FLAG_CPU_HOLD (0x05U) +#define PWR_FLAG_CPU2_HOLD (0x06U) +#define PWR_FLAG2_STOP (0x07U) +#define PWR_FLAG2_SB_D1 (0x08U) +#define PWR_FLAG2_SB_D2 (0x09U) +#define PWR_FLAG2_SB (0x0AU) +#endif /* defined (DUAL_CORE) */ +#define PWR_FLAG_PVDO (0x0BU) +#define PWR_FLAG_AVDO (0x0CU) +#define PWR_FLAG_ACTVOSRDY (0x0DU) +#define PWR_FLAG_ACTVOS (0x0EU) +#define PWR_FLAG_BRR (0x0FU) +#define PWR_FLAG_VOSRDY (0x10U) +#if defined (SMPS) +#define PWR_FLAG_SMPSEXTRDY (0x11U) +#else +#define PWR_FLAG_SCUEN (0x11U) +#endif /* defined (SMPS) */ +#if defined (PWR_CSR1_MMCVDO) +#define PWR_FLAG_MMCVDO (0x12U) +#endif /* defined (PWR_CSR1_MMCVDO) */ +#define PWR_FLAG_USB33RDY (0x13U) +#define PWR_FLAG_TEMPH (0x14U) +#define PWR_FLAG_TEMPL (0x15U) +#define PWR_FLAG_VBATH (0x16U) +#define PWR_FLAG_VBATL (0x17U) + +/* PWR Wake up flag */ +#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 +#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 +#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 +#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 +#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5 +#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6 +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK (0x0FFF3F3FU) +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Configure the main internal regulator output voltage. + * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a + * trade-off between performance and power consumption + * when the device does not operate at the maximum + * frequency (refer to the datasheet for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * Scale 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * Scale 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * Scale 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0 using + * __HAL_PWR_VOLTAGESCALING_CONFIG(). + * Transition to Voltage Scale 0 is only possible when the system is + * already in Voltage Scale 1. + * Transition from Voltage Scale 0 is only possible to Voltage Scale 1 + * then once in Voltage Scale 1 it is possible to switch to another + * voltage scale. + * After each regulator voltage setting, wait on VOSRDY flag to be set + * using macro __HAL_PWR_GET_FLAG(). + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. + * @retval None. + */ +#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#else /* 3 power domains devices */ +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Check the voltage scaling to be configured */ \ + if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \ + { \ + /* Configure the Voltage Scaling 1 */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + /* Enable the PWR overdrive */ \ + SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + } \ + else \ + { \ + /* Disable the PWR overdrive */ \ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Configure the Voltage Scaling x */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + } \ + UNUSED(tmpreg); \ +} while(0) +#else /* STM32H72xxx and STM32H73xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#endif /* defined(SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ + +/** @brief Check PWR flags are set or not. + * @param __FLAG__ : Specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD + * is enabled by the HAL_PWR_EnablePVD() + * function. + * The PVD is stopped by STANDBY mode. For this + * reason, this bit is equal to 0 after STANDBY + * or reset until the PVDE bit is set. + * @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD + * is enabled by the HAL_PWREx_EnableAVD() + * function. The AVD is stopped by STANDBY mode. + * For this reason, this bit is equal to 0 + * after STANDBY or reset until the AVDE bit + * is set. + * @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is + * ready. + * @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not + * reset when the device wakes up from STANDBY + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is ready. + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply + * from regulator is ready. + * @arg PWR_FLAG_TEMPH : This flag indicates that the temperature + * equal or above high threshold level. + * @arg PWR_FLAG_TEMPL : This flag indicates that the temperature + * equal or below low threshold level. + * @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal + * or above high threshold level. + * @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal + * or below low threshold level. + * @arg PWR_FLAG_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG_SB : This flag indicates that the system entered in + * STANDBY mode. + * @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG2_SB : This flag indicates that the system entered + * in STANDBY mode. + * @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes + * up with hold. + * @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes + * up with hold. + * @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS + * External supply is sready. + * @arg PWR_FLAG_SCUEN : This flag indicates that the supply + * configuration update is enabled. + * @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is + * above or equal to 1.2 V. + * @note The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, + * PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, + * PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags + * are used for all H7 family lines. + * The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, + * PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 + * dual core lines. + * The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 + * family except STM32H7Axxx and STM32H7Bxxx lines. + * The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and + * STM32H7Bxxx lines. + * The PWR_FLAG_SCUEN flag is used for devices that support only LDO + * regulator. + * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO + * and SMPS regulators. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#if defined (DUAL_CORE) /* Dual core lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\ + ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* Single core lines */ +#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */ +#if defined (SMPS) /* STM32H725 and STM32H735 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* defined (SMPS) */ +#else /* STM32H7Axxx and STM32H7Bxxx lines */ +#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H7Axx and STM32H7Bxx lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* SMPS */ +#endif /* PWR_CPUCR_SBF_D2 */ +#endif /* DUAL_CORE */ + +/** @brief Check PWR wake up flags are set or not. + * @param __FLAG__: specifies the wake up flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) + +#if defined (DUAL_CORE) +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2. + * This parameter can be one of the following values : + * @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 + * CPU flags. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ +do { \ + SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \ +} while(0) +#else +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags. + * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU + * flags are STOPF, SBF, SBF_D1 and SBF_D2. + * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) +#endif /* defined (DUAL_CORE) */ + +/** @brief Clear PWR wake up flags. + * @param __FLAG__ : Specifies the wake up flag to be cleared. + * This parameter can be one of the following values : + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval None. + */ +#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) + +/** + * @brief Enable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable the PVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable the PVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable event on PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable event on PVD EXTI D2 Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable event on PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable event on PVD EXTI D2 Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable the PVD Rising Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Rising Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Rising & Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Disable the PVD Rising & Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) + +#if defined (DUAL_CORE) +/** + * @brief Checks whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI D2 PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Clear the PVD EXTI D2 flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32h7xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit (void); +void HAL_PWR_EnableBkUpAccess (void); +void HAL_PWR_DisableBkUpAccess (void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD (void); +void HAL_PWR_DisablePVD (void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode (void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler (void); +void HAL_PWR_PVDCallback (void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit (void); +void HAL_PWR_DisableSleepOnExit (void); +void HAL_PWR_EnableSEVOnPend (void); +void HAL_PWR_DisableSEVOnPend (void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +/* Check PVD level parameter */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\ + ((LEVEL) == PWR_PVDLEVEL_1) ||\ + ((LEVEL) == PWR_PVDLEVEL_2) ||\ + ((LEVEL) == PWR_PVDLEVEL_3) ||\ + ((LEVEL) == PWR_PVDLEVEL_4) ||\ + ((LEVEL) == PWR_PVDLEVEL_5) ||\ + ((LEVEL) == PWR_PVDLEVEL_6) ||\ + ((LEVEL) == PWR_PVDLEVEL_7)) + +/* Check PVD mode parameter */ +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +/* Check low power regulator parameter */ +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +/* Check low power mode entry parameter */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +/* Check low power mode entry parameter */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE)) + +/* Check voltage scale level parameter */ +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H7xx_HAL_PWR_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h new file mode 100644 index 0000000..61c7609 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h @@ -0,0 +1,789 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PWR_EX_H +#define STM32H7xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ +/** + * @brief PWREx AVD configuration structure definition + */ +typedef struct +{ + uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This + parameter can be a value of @ref + PWREx_AVD_detection_level + */ + + uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD + event. This parameter can be a value of @ref + PWREx_AVD_Mode. + */ +}PWREx_AVDTypeDef; + +/** + * @brief PWREx Wakeup pin configuration structure definition + */ +typedef struct +{ + uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. + This parameter can be a value of @ref + PWREx_WakeUp_Pins + */ + + uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. + This parameter can be a value of @ref + PWREx_PIN_Polarity + */ + + uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This + parameter can be a value of @ref + PWREx_PIN_Pull + */ +}PWREx_WakeupPinTypeDef; + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief PWR VDDMMC voltage level enum definition + */ +typedef enum +{ + PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */ + PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */ +} PWREx_MMC_VoltageLevel; +#endif /* defined (PWR_CSR1_MMCVDO) */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins + * @{ + */ +/* High level and No pull (default configuration) */ +#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 + +/* High level and No pull */ +#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 + +/* Low level and No pull */ +#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) +#if defined (PWR_WKUPEPR_WKUPP5) +#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) +#endif /* defined (PWR_WKUPEPR_WKUPP5) */ +#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) +#if defined (PWR_WKUPEPR_WKUPP3) +#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) +#endif /* defined (PWR_WKUPEPR_WKUPP3) */ +#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) +#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration + * @{ + */ +#define PWR_PIN_POLARITY_HIGH (0x00000000U) +#define PWR_PIN_POLARITY_LOW (0x00000001U) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration + * @{ + */ +#define PWR_PIN_NO_PULL (0x00000000U) +#define PWR_PIN_PULL_UP (0x00000001U) +#define PWR_PIN_PULL_DOWN (0x00000002U) +/** + * @} + */ + +/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. + * @{ + */ +#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ +#if defined (PWR_WKUPFR_WKUPF5) +#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ +#endif /* defined (PWR_WKUPFR_WKUPF5) */ +#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\ + PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) +#else +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6) +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +/** + * @} + */ + +#if defined (DUAL_CORE) +/** @defgroup PWREx_Core_Select PWREx Core definition + * @{ + */ +#define PWR_CORE_CPU1 (0x00000000U) +#define PWR_CORE_CPU2 (0x00000001U) +/** + * @} + */ +#endif /* defined (DUAL_CORE) */ + +/** @defgroup PWREx_Domains PWREx Domains definition + * @{ + */ +#define PWR_D1_DOMAIN (0x00000000U) +#if defined (PWR_CPUCR_PDDS_D2) +#define PWR_D2_DOMAIN (0x00000001U) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ +#define PWR_D3_DOMAIN (0x00000002U) +/** + * @} + */ + +/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition + * @{ + */ +#if defined (DUAL_CORE) +#define PWR_D1_DOMAIN_FLAGS (0x00000000U) +#define PWR_D2_DOMAIN_FLAGS (0x00000001U) +#define PWR_ALL_DOMAIN_FLAGS (0x00000002U) +#else +#define PWR_CPU_FLAGS (0x00000000U) +#endif /* defined (DUAL_CORE) */ +/** + * @} + */ + +/** @defgroup PWREx_D3_State PWREx D3 Domain State + * @{ + */ +#define PWR_D3_DOMAIN_STOP (0x00000000U) +#define PWR_D3_DOMAIN_RUN (0x00000800U) + +/** + * @} + */ + +/** @defgroup PWREx_Supply_configuration PWREx Supply configuration + * @{ + */ +#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ +#if defined (SMPS) +#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */ +#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ +#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ +#endif /* defined (SMPS) */ +#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ + +#if defined (SMPS) +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ + PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#else +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#endif /* defined (SMPS) */ +/** + * @} + */ + + +/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level + * @{ + */ +#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0 + selection : 1V7 */ +#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1 + selection : 2V1 */ +#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2 + selection : 2V5 */ +#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3 + selection : 2V8 */ +/** + * @} + */ + +/** @defgroup PWREx_AVD_Mode PWREx AVD Mode + * @{ + */ +#define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) +#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) +#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds + * @{ + */ +#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) +#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL +#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH +/** + * @} + */ + +/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds + * @{ + */ +#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) +#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL +#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH +/** + * @} + */ +/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 + * @{ + */ +#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the AVD EXTI Line */ +/** + * @} + */ + +#if defined (PWR_CR1_SRDRAMSO) +/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection + * @{ + */ +#define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */ +#define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */ +#define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */ +#define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */ +#define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */ +#define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */ +/** + * @} + */ +#endif /* defined (PWR_CR1_SRDRAMSO) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Macro PWREx Exported Macro + * @{ + */ + +/** + * @brief Enable the AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable the AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable the AVD EXTI Line 16 + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable the AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable event on AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable event on AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Check whether the specified AVD EXTI interrupt flag is set or not. + * @retval EXTI AVD Line Status. + */ +#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) + +#if defined (DUAL_CORE) +/** + * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. + * @retval EXTI D2 AVD Line Status. + */ +#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Clear the AVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Clear the AVD EXTI D2 flag. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Generates a Software interrupt on AVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @{ + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig (void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange (void); +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetStopModeVoltageRange (void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @{ + */ +/* System low power control functions */ +#if defined (PWR_CPUCR_RETDS_CD) +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry); +#endif /* defined (PWR_CPUCR_RETDS_CD) */ +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain); +void HAL_PWREx_ConfigD3Domain (uint32_t D3State); +/* Clear Cortex-Mx pending flag */ +void HAL_PWREx_ClearPendingEvent (void); +#if defined (DUAL_CORE) +/* Clear domain flags */ +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags); +/* Core Hold/Release functions */ +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU); +void HAL_PWREx_ReleaseCore (uint32_t CPU); +#endif /* defined (DUAL_CORE) */ +/* Flash low power control functions */ +void HAL_PWREx_EnableFlashPowerDown (void); +void HAL_PWREx_DisableFlashPowerDown (void); +#if defined (PWR_CR1_SRDRAMSO) +/* Memory shut-off functions */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); +#endif /* defined(PWR_CR1_SRDRAMSO) */ +/* Wakeup Pins control functions */ +void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); +/* Power Wakeup PIN IRQ Handler */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void); +void HAL_PWREx_WKUP1_Callback (void); +void HAL_PWREx_WKUP2_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN3) +void HAL_PWREx_WKUP3_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +void HAL_PWREx_WKUP4_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN5) +void HAL_PWREx_WKUP5_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +void HAL_PWREx_WKUP6_Callback (void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions + * @{ + */ +/* Backup regulator control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void); +/* USB regulator control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void); +void HAL_PWREx_EnableUSBVoltageDetector (void); +void HAL_PWREx_DisableUSBVoltageDetector (void); +/* Battery control functions */ +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue); +void HAL_PWREx_DisableBatteryCharging (void); +#if defined (PWR_CR1_BOOSTE) +/* Analog Booster functions */ +void HAL_PWREx_EnableAnalogBooster (void); +void HAL_PWREx_DisableAnalogBooster (void); +#endif /* PWR_CR1_BOOSTE */ +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @{ + */ +/* Power VBAT/Temperature monitoring functions */ +void HAL_PWREx_EnableMonitoring (void); +void HAL_PWREx_DisableMonitoring (void); +uint32_t HAL_PWREx_GetTemperatureLevel (void); +uint32_t HAL_PWREx_GetVBATLevel (void); +#if defined (PWR_CSR1_MMCVDO) +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); +#endif /* PWR_CSR1_MMCVDO */ +/* Power AVD configuration functions */ +void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_EnableAVD (void); +void HAL_PWREx_DisableAVD (void); +/* Power PVD/AVD IRQ Handler */ +void HAL_PWREx_PVD_AVD_IRQHandler (void); +void HAL_PWREx_AVDCallback (void); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +/* Check PWR regulator configuration parameter */ +#if defined (SMPS) +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) + +#else +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) +#endif /* defined (SMPS) */ + +/* Check PWR regulator configuration in STOP mode parameter */ +#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) + +/* Check PWR domain parameter */ +#if defined (PWR_CPUCR_PDDS_D2) +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D2_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#else +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + +/* Check D3/SRD domain state parameter */ +#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\ + ((STATE) == PWR_D3_DOMAIN_RUN)) + +/* Check wake up pin parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ + +/* Check wake up pin polarity parameter */ +#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ + ((POLARITY) == PWR_PIN_POLARITY_LOW)) + +/* Check wake up pin pull configuration parameter */ +#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ + ((PULL) == PWR_PIN_PULL_UP) ||\ + ((PULL) == PWR_PIN_PULL_DOWN)) + +/* Check wake up flag parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG3) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG5) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#else +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ + +/* Check wake up flag parameter */ +#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ + ((LEVEL) == PWR_AVDLEVEL_1) ||\ + ((LEVEL) == PWR_AVDLEVEL_2) ||\ + ((LEVEL) == PWR_AVDLEVEL_3)) + +/* Check AVD mode parameter */ +#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_NORMAL) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) + +/* Check resistor battery parameter */ +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) +/* Check D1/CD CPU ID parameter */ +#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) + +#if defined (DUAL_CORE) +/* Check CPU parameter */ +#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) + +/* Check D2 CPU ID parameter */ +#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID) + +/* Check PWR domain flag parameter */ +#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \ + ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \ + ((FLAG) == PWR_ALL_DOMAIN_FLAGS)) +#endif /* defined (DUAL_CORE) */ + +#if defined (PWR_CR1_SRDRAMSO) +/* Check memory block parameter */ +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK)) +#endif /* defined (PWR_CR1_SRDRAMSO) */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7xx_HAL_PWR_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h new file mode 100644 index 0000000..1626c6d --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -0,0 +1,8266 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_RCC_H +#define STM32H7xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ + + uint32_t PLLP; /*!< PLLP: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + uint32_t PLLRGE; /*!AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN)) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN)) +#endif /* OCTOSPI2 */ +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN)) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN)) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN)) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN)) +#endif /* GFXMMU */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) +#endif /* JPEG */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) +#if defined (QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U) +#endif /* OCTOSPI2 */ +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ + +#define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) +#endif /* JPEG */ +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) +#if defined (QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) +#endif /* QUADSPI */ +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U) +#endif +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U) +#endif +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U) +#endif +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U) +#endif +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U) +#endif +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U) +#endif +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DUAL_CORE*/ + +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#endif +#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) +#endif /* USB2_OTG_FS */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U) +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) +#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) +#endif +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) +#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) +#endif +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U) +#endif /* USB2_OTG_FS */ + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DCMI && PSSI */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMAC */ + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CORDIC */ + +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#else +#define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ + +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#else +#define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ + +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_HSEMEN */ + +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* BDMA1 */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN)) +#define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN)) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN)) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN)) +#endif + +/** @brief Get the enable or disable status of the AHB2 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U) +#endif + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U) +#endif + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOI */ + +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN) +#define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN) +#endif +#define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Get the enable or disable status of the AHB4 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U) +#endif +#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) + +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U) +#endif +#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DSI*/ + +#define __HAL_RCC_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Get the enable or disable status of the APB3 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) + + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C5 */ + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM23 */ + +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN) +#endif /* TIM24 */ + + +/** @brief Get the enable or disable status of the APB1 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) +#define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U) +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) +#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) +#define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U) +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) +#define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) +#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U) +#endif /* TIM24 */ + + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*UART9*/ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*USART10*/ + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*SAI2*/ + +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*SAI3*/ + +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) +#endif /*HRTIM*/ + +/** @brief Get the enable or disable status of the APB2 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) +#endif /* SAI3 */ +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) +#endif /*HRTIM1*/ + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM5 */ + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DAC2 */ + +#define __HAL_RCC_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI4 */ + +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DTS*/ + +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN) +#endif /*DFSDM2*/ + +/** @brief Get the enable or disable status of the APB4 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) +#define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) +#define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U) +#endif /*DFSDM2*/ + +#if defined(DUAL_CORE) + +/* Exported macros for RCC_C1 -------------------------------------------------*/ + +/** @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + + + +#define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) + + + + +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) +#define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) + +/* Exported macros for RCC_C2 -------------------------------------------------*/ + +/** @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + + +#define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FLASH_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ITCM_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + + + +#define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN)) +#define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN)) +#define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN)) +#define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN)) +#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN)) + +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) +#define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) + + + +#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) + +#endif /*DUAL_CORE*/ + +/** @brief Enable or disable the AHB3 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */ +#else +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ +#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ + +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +#define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ +#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ + + + +/** @brief Force or release the AHB1 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */ +#else +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) +#endif /*USB2_OTG_FS*/ + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) +#endif /*USB2_OTG_FS*/ + +/** @brief Force or release the AHB2 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */ +#else +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ + + +/** @brief Force or release the AHB4 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */ +#else +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) +#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) +#endif + +#define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) +#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) +#endif + +/** @brief Force or release the APB3 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */ +#else +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST) +#endif /*DSI*/ + +#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST) +#endif /*DSI*/ + +/** @brief Force or release the APB1 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */ +#else +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */ +#else +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) +#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST) +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST) +#define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST) +#define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) +#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) +#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ + +#define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) +#define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST) +#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) +#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST) +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST) +#define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST) +#define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) +#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) +#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ + +/** @brief Force or release the APB2 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */ +#else +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ + +/** @brief Force or release the APB4 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */ +#else +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) +#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) +#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) +#define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) +#define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) +#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) +#define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ + +#define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) +#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST) +#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) +#define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(RCC_APB4RSTR_DAC2RST) +#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST) +#endif +#define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) +#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) +#define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ + +/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + + +#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif +#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) +#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif +#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) +#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U) +#endif +#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) +#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) +#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U) +#endif + +#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U) +#endif +#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) +#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) +#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U) +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN)) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN)) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) +#endif /* USB2_OTG_FS */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) +#endif /* ETH */ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) +#endif /* ETH */ +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U) +#endif /* USB2_OTG_FS */ + + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) +#endif + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) +#endif + +/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U) +#endif +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/ + + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#endif /* BDMA2 */ +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#endif /* ADC3 */ +#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE +#else +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif + + +/** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) +#endif + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) +#endif + + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + + +/** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U) + + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ + + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ + + +/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) +#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) +#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U) +#endif /* TIM24 */ + + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ + + +/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) +#if defined(UART9) +#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) +#endif /*HRTIM1*/ + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ + + +/** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) +#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) +#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U) +#endif /*DFSDM2*/ + + +#if defined(DUAL_CORE) + +/** @brief Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) + + +#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) + + + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) + +#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) + +#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) + + +#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) + +#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) + + +#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) + +/** @brief Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + + +#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) + + +#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) + + + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) + +#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) + +#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) + + +#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) + +#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) + +#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) + +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN + * @note After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP + */ +#else +/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN + * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP + */ +#endif /*DUAL_CORE*/ + +#if defined(RCC_D3AMR_BDMAAMEN) +#define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) +#endif +#if defined(RCC_D3AMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) +#define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) +#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN) +#endif + +#if defined(RCC_D3AMR_BDMAAMEN) +#define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) +#endif +#if defined(RCC_D3AMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) +#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN) +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) +#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(RCC_SRDAMR_DAC2AMEN) +#define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN) +#endif + + +#if defined(RCC_CKGAENR_AXICKG) +/** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register). + */ + +#define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG) + + +#define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG) + +#endif /* RCC_CKGAENR_AXICKG */ + + + + +/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param __STATE__ specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg RCC_HSI_OFF turn OFF the HSI oscillator + * @arg RCC_HSI_ON turn ON the HSI oscillator + * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset) + * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 + * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 + * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_CONFIG(__STATE__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) + + +/** @brief Macro to get the HSI divider. + * @retval The HSI divider. The returned value can be one + * of the following: + * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) + * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 + * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 + * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 + */ +#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after start-up + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICalibrationValue__: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x7F (3F for Rev Y device). + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + do { \ + if(HAL_GetREVID() <= REV_ID_Y) \ + { \ + if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \ + } \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \ + } \ + } while(0) + +#else +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for some peripherals. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI start-up time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + + +/** + * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). + * @note After enabling the HSI48, the application software should wait on + * HSI48RDY flag to be set indicating that HSI48 clock is stable and can + * be used to clock the USB. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); + +/** + * @brief Macros to enable or disable the Internal oscillator (CSI). + * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * start-up from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note CSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the CSI. + * @note After enabling the CSI, the application software should wait on + * CSIRDY flag to be set indicating that CSI clock is stable and can + * be used as system clock source. + * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator + * clock cycles. + */ +#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) +#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) + +/** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal CSI RC. + * @param __CSICalibrationValue__: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + if(HAL_GetREVID() <= REV_ID_Y) \ + { \ + if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ + } \ + else \ + { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } \ + } while(0) + +#else +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } while(0) + +#endif /*RCC_VER_X*/ +/** + * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the CSI start-up time. + * @note The enable of this function has not effect on the CSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) +#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) + + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (__HSE__). + * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), + * the application software should wait on HSERDY flag to be set indicating + * that HSE clock is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + * @arg RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*) + * + * (*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + */ +#if defined(RCC_CR_HSEEXT) +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + } \ + } while(0) +#else +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) +#endif /* RCC_CR_HSEEXT */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). + A duty cycle close to 50% is recommended. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) + * @param __STATE__: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + * @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*) + * + * (*) Available on some STM32H7 lines only. + */ +#if defined(RCC_BDCR_LSEEXT) +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + } \ + } while(0) +#else + +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) + +#endif /* RCC_BDCR_LSEEXT */ +/** + * @} + */ + +/** @brief Macros to enable or disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ + } while (0) + +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) + + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) + +/** + * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL is disabled. + * This is mainly used to save Power. + * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock). + * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) + +#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) + + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 + * @retval None + */ +#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + +#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + + +/** + * @brief Macro to configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . + * + * @param __PLLM1__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 4 and 512 or between 8 and 420(*). + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLLP1__: specifies the division factor for system clock. + * This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed) + * + * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLLR1__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL1P__, __PLL1Q__ or __PLL1R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * (**): For stm32h72xxx and stm32h73xxx family lines. + */ + + +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ + do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \ + WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \ + ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \ + } while(0) + + +/** @brief Macro to configure the PLLs clock source. + * @note This function must be used only when all PLLs are disabled. + * @param __PLLSOURCE__: specifies the PLLs entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) + + +/** + * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO + * + * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO + * It should be a value between 0 and 8191 + * @note Warning: The software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 + * 150 to 420 MHz if PLL1VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) + + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__)) + + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) + + + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_CFGR_SWS_CSI: CSI used as system clock. + * - RCC_CFGR_SWS_HSI: HSI used as system clock. + * - RCC_CFGR_SWS_HSE: HSE used as system clock. + * - RCC_CFGR_SWS_PLL: PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) + + +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC)) + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); + +/** + * @} + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON. + * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. + * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. + * @retval None + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + do{ \ + if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \ + { \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \ + } \ + else \ + { \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \ + } \ + } while(0) +#else +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); +#endif /*RCC_VER_X*/ +/** + * @brief Macro to configure the wake up from stop clock. + * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__)) + +/** + * @brief Macro to configure the Kernel wake up from stop clock. + * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source + * @retval None + */ +#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: HSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: HSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: CSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_HSECSS: HSE Clock Security interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: CSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_HSECSS: HSE Clock Security interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) + +#if defined(DUAL_CORE) +#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF) + +#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSIDIV: HSI divider flag + * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready + * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready + * @arg RCC_FLAG_PLLRDY: PLL1 clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_C1RST: CPU reset flag + * @arg RCC_FLAG_C2RST: CPU2 reset flag + * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag + * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag + * @arg RCC_FLAG_BORRST: BOR reset flag + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag + * @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag + * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag + * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset + * @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset + * @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset + * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset + * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag + * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#else + +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSIDIV: HSI divider flag + * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready (*) + * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready (*) + * @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*) + * @arg RCC_FLAG_CDCKRDY: CPU Domain clock ready (*) + * @arg RCC_FLAG_PLLRDY: PLL1 clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_CPURST: CPU reset flag + * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag (*) + * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag (*) + * @arg RCC_FLAG_CDRST: CD domain power switch reset flag (*) + * @arg RCC_FLAG_BORRST: BOR reset flag + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag + * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag + * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset + * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset + * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag + * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + * + * (*) Available on some STM32H7 lines only. + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos) + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32h7xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */ +#define CSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms */ +#define PLL_FRAC_TIMEOUT_VALUE (1U) /* PLL Fractional part waiting time before new latch enable : 1 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define RCC_DBP_TIMEOUT_VALUE (100U) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + +#if defined(RCC_CR_HSEEXT) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL)) +#else +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) +#endif /* RCC_CR_HSEEXT */ + +#if defined(RCC_BDCR_LSEEXT) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL)) +#else +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) +#endif /* RCC_BDCR_LSEEXT */ + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ + ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \ + ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8)) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ + ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_NONE) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \ + ((VALUE) == RCC_PLL1VCIRANGE_1) || \ + ((VALUE) == RCC_PLL1VCIRANGE_2) || \ + ((VALUE) == RCC_PLL1VCIRANGE_3)) + +#define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM)) + +#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) + +#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#if !defined(RCC_VER_2_0) +#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#else +#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U)) +#endif /* !RCC_VER_2_0 */ +#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ + ((VALUE) == RCC_PLL1_DIVQ) || \ + ((VALUE) == RCC_PLL1_DIVR)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ + ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \ + ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \ + ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \ + ((SYSCLK) == RCC_SYSCLK_DIV512)) + + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ + ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ + ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ + ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ + ((HCLK) == RCC_HCLK_DIV512)) + +#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \ + ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \ + ((CDPCLK1) == RCC_APB3_DIV16)) + +#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */ + +#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \ + ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \ + ((PCLK1) == RCC_APB1_DIV16)) + +#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \ + ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \ + ((PCLK2) == RCC_APB2_DIV16)) + +#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \ + ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \ + ((SRDPCLK1) == RCC_APB4_DIV16)) + +#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/ + +#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63)) + +#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ + ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ + ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ + ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ + ((DIV) == RCC_MCODIV_15)) + +#if defined(DUAL_CORE) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \ + ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \ + ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \ + ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV)) + +#else + +#if defined(RCC_CR_D2CKRDY) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \ + ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#else +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#endif /* RCC_CR_D2CKRDY */ + +#endif /*DUAL_CORE*/ + +#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU) +#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) + +#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \ + ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) + +#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ + ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_RCC_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h new file mode 100644 index 0000000..2fb1fd2 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -0,0 +1,4482 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_RCC_EX_H +#define STM32H7xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief PLL2 Clock structure definition + */ +typedef struct +{ + + uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ + + uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + uint32_t PLL2RGE; /*!CR, RCC_CR_PLL2ON) +#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) + +/** + * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled, + * This is mainly used to save Power. + * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) + +#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +/** + * @brief Macro to configures the PLL2 multiplication and division factors. + * @note This function must be used only when PLL2 is disabled. + * + * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock + * This parameter must be a number between 4 and 512 or between 8 and 420(*). + * @note You have to set the PLL2N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL2P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + */ + +#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ + do{ \ + MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ + WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ + ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ + } while(0) + +/** + * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO + * + * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 + * 150 to 420 MHz if PLL2VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) + + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) + +/** @brief Macros to enable or disable the main PLL3. + * @note After enabling PLL3, the application software should wait on + * PLL3RDY flag to be set indicating that PLL3 clock is stable and can + * be used as kernel clock source. + * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) +#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +/** + * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled, + * This is mainly used to save Power. + * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) + +#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) + +/** + * @brief Macro to configures the PLL3 multiplication and division factors. + * @note This function must be used only when PLL3 is disabled. + * + * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL3N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL3P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 2 and 128 (where odd numbers not allowed) + * + * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL3R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + */ + +#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ + do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \ + WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \ + ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \ + } while(0) + + + +/** + * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO + * + * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 + * 150 to 420 MHz if PLL3VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) + + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) +/** + * @brief Macro to Configure the SAI1 clock source. + * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL + * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 + * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 + * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC + * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock + * @retval None + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#else +#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SAI1SEL */ + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL + * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 + * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 + * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP + * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) +#else +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) +#endif /* RCC_D2CCIP1R_SAI1SEL */ + +/** + * @brief Macro to Configure the SPDIFRX clock source. + * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived + * from system PLL, PLL2, PLL3, or internal OSC clock + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL + * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 + * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 + * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#else +#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ + +/** + * @brief Macro to get the SPDIFRX clock source. + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) +#else +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ + +#if defined(SAI3) +/** + * @brief Macro to Configure the SAI2/3 clock source. + * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL + * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 + * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 + * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP + * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) + +/** @brief Macro to get the SAI2/3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL + * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 + * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 + * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP + * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock + */ +#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) + +/** + * @brief Macro to Configure the SAI2 clock source. + * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock + */ +#define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE + +/** + * @brief Macro to Configure the SAI3 clock source. + * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL + * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 + * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 + * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP + * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG + +/** @brief Macro to get the SAI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL + * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 + * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 + * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP + * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock + */ +#define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +/** + * @brief Macro to Configure the SAI2A clock source. + * @param __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__)) + +/** @brief Macro to get the SAI2A clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +/** + * @brief Macro to Configure the SAI2B clock source. + * @param __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__)) + +/** @brief Macro to get the SAI2B clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */ + + +#if defined(SAI4_Block_A) +/** + * @brief Macro to Configure the SAI4A clock source. + * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL + * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2 + * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3 + * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP + * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) + +/** @brief Macro to get the SAI4A clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock + */ +#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) +#endif /* SAI4_Block_A */ + +#if defined(SAI4_Block_B) +/** + * @brief Macro to Configure the SAI4B clock source. + * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) + +/** @brief Macro to get the SAI4B clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock + */ +#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) +#endif /* SAI4_Block_B */ + +/** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK). + * + * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) +/* alias */ +#define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* RCC_D2CCIP2R_I2C123SEL */ + +/** @brief macro to get the I2C1/2/3/5* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL))) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) +/* alias */ +#define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* RCC_D2CCIP2R_I2C123SEL */ + +/** @brief macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1CLKSource__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2CLKSource__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3CLKSource__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4CLKSource__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock + */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#else +#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#endif /* RCC_D3CCIPR_I2C4SEL */ + +/** @brief macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock + */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) +#else +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL))) +#endif /* RCC_D3CCIPR_I2C4SEL */ + +#if defined(I2C5) +/** @brief macro to configure the I2C5 clock (I2C5CLK). + * + * @param __I2C5CLKSource__ specifies the I2C5 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock + */ +#define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* I2C5 */ + +#if defined(I2C5) +/** @brief macro to get the I2C5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock + */ +#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* I2C5 */ + +/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK). + * + * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source. + * This parameter can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#endif /* RCC_D2CCIP2R_USART16SEL */ + +/** @brief macro to get the USART1/6/9* /10* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL))) +/* alias*/ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) +/* alias */ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ + +/** @brief macro to configure the USART234578 clock (USART234578CLK). + * + * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock + */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) +#else +#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +/** @brief macro to get the USART2/3/4/5/7/8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock + */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#else +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +/** @brief macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1CLKSource__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE + +/** @brief macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2CLKSource__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3CLKSource__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4CLKSource__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5CLKSource__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6CLKSource__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE + +/** @brief macro to configure the UART5 clock (UART7CLK). + * + * @param __UART7CLKSource__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART8 clock (UART8CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +#if defined(UART9) +/** @brief macro to configure the UART9 clock (UART9CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the UART9 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* UART9 */ + +#if defined(USART10) +/** @brief macro to configure the USART10 clock (USART10CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART10 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* USART10 */ + +/** @brief macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1CLKSource__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock + */ +#if defined (RCC_D3CCIPR_LPUART1SEL) +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#else +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#endif /* RCC_D3CCIPR_LPUART1SEL */ + +/** @brief macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock + */ +#if defined (RCC_D3CCIPR_LPUART1SEL) +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) +#else +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) +#endif /* RCC_D3CCIPR_LPUART1SEL */ + +/** @brief macro to configure the LPTIM1 clock source. + * + * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) +#else +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ + +/** @brief macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) +#else +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ + +/** @brief macro to configure the LPTIM2 clock source. + * + * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock + */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) +#else +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ + +/** @brief macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock + */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) +#else +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ + +/** @brief macro to configure the LPTIM3/4/5 clock source. + * + * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source. + * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock + */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) +#else +#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ + +/** @brief macro to get the LPTIM3/4/5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock + */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) +#else +#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ + +/** @brief macro to configure the LPTIM3 clock source. + * + * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source. + * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock + */ +#define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG + +/** @brief macro to get the LPTIM3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock + */ +#define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE + +#if defined(LPTIM4) +/** @brief macro to configure the LPTIM4 clock source. + * + * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. + * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock + */ +#define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG + + +/** @brief macro to get the LPTIM4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock + */ +#define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +/** @brief macro to configure the LPTIM5 clock source. + * + * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. + * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock + */ +#define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG + + +/** @brief macro to get the LPTIM5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock + */ +#define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM5 */ + +#if defined(QUADSPI) +/** @brief macro to configure the QSPI clock source. + * + * @param __QSPICLKSource__ specifies the QSPI clock source. + * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock + */ +#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) + + +/** @brief macro to get the QSPI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock + */ +#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @brief macro to configure the OSPI clock source. + * + * @param __OSPICLKSource__ specifies the OSPI clock source. + * @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#else +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ + +/** @brief macro to get the OSPI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL))) +#else +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL))) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + + +#if defined(DSI) +/** @brief macro to configure the DSI clock source. + * + * @param __DSICLKSource__ specifies the DSI clock source. + * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock + * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock + */ +#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__)) + + +/** @brief macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock + * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock + */ +#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL))) +#endif /*DSI*/ + +/** @brief macro to configure the FMC clock source. + * + * @param __FMCCLKSource__ specifies the FMC clock source. + * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) +#else +#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) +#endif /* RCC_D1CCIPR_FMCSEL */ + +/** @brief macro to get the FMC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) +#else +#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) +#endif /* RCC_D1CCIPR_FMCSEL */ + +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSource__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock + * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#else +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#endif /* RCC_D2CCIP2R_USBSEL */ + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock + * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) +#else +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) +#endif /* RCC_D2CCIP2R_USBSEL */ + +/** @brief Macro to configure the ADC clock + * @param __ADCCLKSource__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#else +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#endif /* RCC_D3CCIPR_ADCSEL */ + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) +#else +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) +#endif /* RCC_D3CCIPR_ADCSEL */ + +/** @brief Macro to configure the SWPMI1 clock + * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock + * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#else +#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SWPSEL */ + +/** @brief Macro to get the SWPMI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock + * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) +#else +#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) +#endif /* RCC_D2CCIP1R_SWPSEL */ + +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#else +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock + */ +#if defined (RCC_D2CCIP1R_DFSDM1SEL) +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) +#else +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ + +#if defined(DFSDM2_BASE) +/** @brief Macro to configure the DFSDM2 clock + * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) + +/** @brief Macro to get the DFSDM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL))) +#endif /* DFSDM2 */ + +/** @brief macro to configure the CEC clock (CECCLK). + * + * @param __CECCLKSource__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#else +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#endif /* RCC_D2CCIP2R_CECSEL */ + +/** @brief macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) +#else +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) +#endif /* RCC_D2CCIP2R_CECSEL */ + +/** @brief Macro to configure the CLKP : Oscillator clock for peripheral + * @param __CLKPSource__ specifies Oscillator clock for peripheral + * This parameter can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#else +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#endif /* RCC_D1CCIPR_CKPERSEL */ + +/** @brief Macro to get the Oscillator clock for peripheral source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) +#else +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) +#endif /* RCC_D1CCIPR_CKPERSEL */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @brief Macro to configure the FDCAN clock + * @param __FDCANCLKSource__ specifies clock source for FDCAN + * This parameter can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#else +#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#endif /* RCC_D2CCIP1R_FDCANSEL */ + +/** @brief Macro to get the FDCAN clock + * @retval The clock source can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) +#else +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL))) +#endif /* RCC_D2CCIP1R_FDCANSEL */ + +#endif /*FDCAN1 || FDCAN2*/ + +/** + * @brief Macro to Configure the SPI1/2/3 clock source. + * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL + * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 + * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 + * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP + * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#else +#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI123SEL */ + +/** @brief Macro to get the SPI1/2/3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL + * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 + * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 + * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP + * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) +#else +#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) +#endif /* RCC_D2CCIP1R_SPI123SEL */ + +/** + * @brief Macro to Configure the SPI1 clock source. + * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL + * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 + * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 + * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP + * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL + * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 + * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 + * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP + * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock + */ +#define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI2 clock source. + * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL + * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 + * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 + * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP + * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL + * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 + * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 + * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP + * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock + */ +#define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI3 clock source. + * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL + * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 + * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 + * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP + * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL + * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 + * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 + * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP + * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock + */ +#define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI4/5 clock source. + * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 + * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 + * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 + * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI + * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI + * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#else +#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI45SEL */ + +/** @brief Macro to get the SPI4/5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 + * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 + * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 + * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI + * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI + * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE +*/ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) +#else +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) +#endif /* RCC_D2CCIP1R_SPI45SEL */ + +/** + * @brief Macro to Configure the SPI4 clock source. + * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 + * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 + * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 + * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI + * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI + * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE + * @retval None + */ +#define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG + +/** @brief Macro to get the SPI4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 + * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 + * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 + * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI + * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI + * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE +*/ +#define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE + +/** + * @brief Macro to Configure the SPI5 clock source. + * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 + * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 + * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 + * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI + * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI + * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE + * @retval None + */ +#define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG + +/** @brief Macro to get the SPI5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 + * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 + * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 + * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI + * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI + * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE +*/ +#define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE + +/** + * @brief Macro to Configure the SPI6 clock source. + * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 + * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 + * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 + * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI + * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI + * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*) + * + * @retval None + * + * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines. + * + */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#else +#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +/** @brief Macro to get the SPI6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 + * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 + * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 + * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI + * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI + * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN +*/ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) +#else +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +/** @brief Macro to configure the SDMMC clock + * @param __SDMMCCLKSource__ specifies clock source for SDMMC + * This parameter can be one of the following values: + * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock + * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#else +#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#endif /* RCC_D1CCIPR_SDMMCSEL */ + +/** @brief Macro to get the SDMMC clock + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) +#else +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) +#endif /* RCC_D1CCIPR_SDMMCSEL */ + +/** @brief macro to configure the RNG clock (RNGCLK). + * + * @param __RNGCLKSource__ specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#else +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#endif /* RCC_D2CCIP2R_RNGSEL */ + +/** @brief macro to get the RNG clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) +#else +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) +#endif /* RCC_D2CCIP2R_RNGSEL */ + +#if defined(HRTIM1) +/** @brief Macro to configure the HRTIM1 prescaler clock source. + * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock + * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) + +/** @brief Macro to get the HRTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock + * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) +#endif /* HRTIM1 */ + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, + * else it is equal to 2 x Frcc_pclkx_d2 (default after reset) + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to 4 x Frcc_pclkx_d2 + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\ + RCC->CFGR |= (__PRESC__); \ + }while(0) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ +/** + * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after pre-scaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + + +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); +uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); +uint32_t HAL_RCCEx_GetD1SysClockFreq(void); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +#if defined(DUAL_CORE) +void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); +#endif /*DUAL_CORE*/ +#if defined(RCC_GCR_WW1RSC) +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); +#endif /*RCC_GCR_WW1RSC*/ +/** + * @} + */ + + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \ + ((VALUE) == RCC_PLL2_DIVQ) || \ + ((VALUE) == RCC_PLL2_DIVR)) + +#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ + ((VALUE) == RCC_PLL3_DIVQ) || \ + ((VALUE) == RCC_PLL3_DIVR)) + +#if defined(RCC_D2CCIP2R_USART16SEL) +#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +#else +#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +/* alias*/ +#define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ + +#if defined(RCC_D2CCIP2R_USART28SEL) +#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#else +#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) + +#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) + +#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) + +#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) + +#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) + +#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) + +#if defined(UART9) +#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_HSI)) +#endif + +#if defined(USART10) +#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_HSI)) +#endif + +#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) + +#if defined(I2C5) +#define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI)) + +#define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */ +#else +#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) +#endif /*I2C5*/ + +#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) + +#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) + +#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) + +#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_I2C4CLKSOURCE_CSI)) + +#if defined(I2C5) +#define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C5CLKSOURCE_CSI)) +#endif /*I2C5*/ + +#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ + ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ + ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) + +#if defined(HRTIM1) +#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ + ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) +#endif + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) + +#define IS_RCC_SAI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) + +#if defined(SAI3) +#define IS_RCC_SAI23CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) + +#define IS_RCC_SAI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) + + +#define IS_RCC_SAI3CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define IS_RCC_SAI2ACLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define IS_RCC_SAI2BCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF)) +#endif + +#define IS_RCC_SPI123CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) + +#define IS_RCC_SPI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) + +#define IS_RCC_SPI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) + +#define IS_RCC_SPI3CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) + +#define IS_RCC_SPI45CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) + +#define IS_RCC_SPI4CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) + +#define IS_RCC_SPI5CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) + +#if defined(RCC_D3CCIPR_SPI6SEL) +#define IS_RCC_SPI6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) +#else +#define IS_RCC_SPI6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +#if defined(SAI4) +#define IS_RCC_SAI4ACLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) + +#define IS_RCC_SAI4BCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) +#endif /*SAI4*/ + +#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \ + ((VALUE) == RCC_PLL2VCIRANGE_1) || \ + ((VALUE) == RCC_PLL2VCIRANGE_2) || \ + ((VALUE) == RCC_PLL2VCIRANGE_3)) + +#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \ + ((VALUE) == RCC_PLL3VCIRANGE_1) || \ + ((VALUE) == RCC_PLL3VCIRANGE_2) || \ + ((VALUE) == RCC_PLL3VCIRANGE_3)) + +#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \ + ((VALUE) == RCC_PLL2VCOMEDIUM)) + +#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ + ((VALUE) == RCC_PLL3VCOMEDIUM)) + +#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) + +#if defined(LPTIM4) +#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) +#endif /* LPTIM4*/ + +#if defined(LPTIM5) +#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) +#endif /*LPTIM5*/ + +#if defined(QUADSPI) +#define IS_RCC_QSPICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI1) +#define IS_RCC_OSPICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) +#endif /*OCTOSPI1 || OCTOSPI1*/ + +#if defined(DSI) +#define IS_RCC_DSICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2)) +#endif /*DSI*/ + +#define IS_RCC_FMCCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) + +#if defined(FDCAN1) || defined(FDCAN2) +#define IS_RCC_FDCANCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) +#endif /*FDCAN1 || FDCAN2*/ + +#define IS_RCC_SDMMC(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) + +#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) + +#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) + +#if defined(DFSDM2_BASE) +#define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \ + ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS)) +#endif /*DFSDM2*/ + +#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_CSI)) + +#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_HSE)) +#define IS_RCC_TIMPRES(VALUE) \ + (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ + ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined(DUAL_CORE) +#define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ + ((CORE) == RCC_BOOT_C2)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \ + ((WWDG) == RCC_WWDG2)) +#else +#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) + +#endif /*DUAL_CORE*/ + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_RCC_EX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h new file mode 100644 index 0000000..6daa529 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h @@ -0,0 +1,2462 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_TIM_H +#define STM32H7xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#if defined(TIM_BREAK_INPUT_SUPPORT) +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#endif /* TIM_BREAK_INPUT_SUPPORT */ +#define TIM_DMABASE_TISEL 0x0000001AU +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ +#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ +#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ +#endif /*TIM_BDTR_BKBID */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ +#endif /* TIM_BDTR_BKBID */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ +#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ +#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ +#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ +#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ +#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ +#define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */ +#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL)) + + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENABLE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ + ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32h7xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_TIM_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h new file mode 100644 index 0000000..ebad016 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_TIM_EX_H +#define STM32H7xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity + Not relevant when analog watchdog output of the DFSDM1 used as break input source */ +} TIMEx_BreakInputConfigTypeDef; + +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM8_ETR_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */ +#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */ +#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */ +#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */ +#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */ +#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ +#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */ + +#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ +#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */ + +#define TIM_TIM5_ETR_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */ +#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */ +#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */ +#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */ +#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */ + +#define TIM_TIM23_ETR_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */ +#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */ +#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */ + +#define TIM_TIM24_ETR_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */ +#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */ +#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */ +#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */ +#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */ +/** + * @} + */ +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1_TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ + +#define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8_TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP2 OUT */ + +#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to GPIO */ +#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ +#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */ + +#define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3_TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ +#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ +#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5_TI1 is connected to GPIO */ +#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to CAN TMP */ +#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to CAN RTP */ + +#define TIM_TIM12_TI1_GPIO 0x00000000U /*!< TIM12 TI1 is connected to GPIO */ +#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 TI1 is connected to SPDIF FS */ + +#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 CH1 */ +#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to TIM4 CH1 */ +#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15_TI1 is connected to RCC LSE */ +#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to RCC CSI */ +#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to RCC MCO2 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM3 CH2 */ +#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM4 CH2 */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 TI1 is connected to RCC LSI */ +#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to RCC LSE */ +#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to WKUP_IT */ + +#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 TI1 is connected to SPDIF FS */ +#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to RCC HSE 1Mhz */ +#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to RCC MCO1 */ + +#define TIM_TIM23_TI4_GPIO 0x00000000U /*!< TIM23_TI4 is connected to GPIO */ +#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23_TI4 is connected to COMP1 OUT */ +#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23_TI4 is connected to COMP2 OUT */ +#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM24_TI1_GPIO 0x00000000U /*!< TIM24_TI1 is connected to GPIO */ +#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24_TI1 is connected to CAN TMP */ +#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24_TI1 is connected to CAN RTP */ +#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24_TI1 is connected to CAN SOC */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\ + ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\ + ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\ + ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\ + ((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\ + ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\ + ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\ + ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\ + ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\ + ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\ + ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC)) + +#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\ + ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined(TIM_BREAK_INPUT_SUPPORT) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* TIM_BREAK_INPUT_SUPPORT */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); +#if defined(TIM_BDTR_BKBID) + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +#endif /* TIM_BDTR_BKBID */ +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_TIM_EX_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h new file mode 100644 index 0000000..4f15c6e --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h @@ -0,0 +1,6914 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_BUS_H +#define STM32H7xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN +#define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN + +#if defined(JPEG) +#define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN +#endif /* JPEG */ + +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#if defined(QUADSPI) +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) +#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN +#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN +#endif /*(OCTOSPI1) || (OCTOSPI2)*/ +#if defined(OCTOSPIM) +#define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) || defined(OTFDEC2) +#define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN +#define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN +#endif /* (OTFDEC1) || (OTFDEC2) */ +#if defined(GFXMMU) +#define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN +#endif /* GFXMMU */ +#define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN +#define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN +#define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN +#define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN +#define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN +#else +#define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN +#define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ +#if defined(CD_AXISRAM2_BASE) +#define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN +#endif /* CD_AXISRAM2_BASE */ +#if defined(CD_AXISRAM3_BASE) +#define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN +#endif /* CD_AXISRAM3_BASE */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN +#if defined(DUAL_CORE) +#define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN +#endif /* DUAL_CORE */ +#if defined(RCC_AHB1ENR_CRCEN) +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#endif /* RCC_AHB1ENR_CRCEN */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN +#define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN +#define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN +#endif /* ETH */ +#define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN +#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN +#if defined(USB2_OTG_FS) +#define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN +#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN +#endif /* USB2_OTG_FS */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN) +#define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN +#endif /* HSEM && RCC_AHB2ENR_HSEMEN */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN +#if defined(FMAC) +#define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN +#endif /* FMAC */ +#if defined(CORDIC) +#define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN +#endif /* CORDIC */ +#if defined(BDMA1) +#define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN +#endif /* BDMA1 */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN +#else +#define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN +#define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/ +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN +#else +#define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN +#define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/ +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN +#endif /* RCC_AHB2ENR_D2SRAM3EN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN +#define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN +#define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN +#define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN +#define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN +#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN +#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN +#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN +#if defined(GPIOI) +#define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN +#endif /* GPIOI */ +#define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN +#define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN +#if defined(RCC_AHB4ENR_CRCEN) +#define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN +#endif /* RCC_AHB4ENR_CRCEN */ +#if defined(BDMA2) +#define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN +#define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/ +#else +#define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN +#endif /* BDMA2 */ +#if defined(ADC3) +#define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN +#endif /* ADC3 */ +#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN) +#define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN +#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/ +#define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN +#if defined(RCC_AHB4LPENR_SRAM4LPEN) +#define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN +#define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4 +#else +#define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN +#define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ +#define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ +#endif /* RCC_AHB4ENR_D3SRAM1EN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH + * @{ + */ +#if defined(LTDC) +#define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN +#endif /* DSI */ +#define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN +#if defined(RCC_APB3ENR_WWDGEN) +#define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/ +#endif /* RCC_APB3ENR_WWDGEN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN +#if defined(DUAL_CORE) +#define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN +#endif /*DUAL_CORE*/ +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN +#if defined(I2C5) +#define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN +#endif /* I2C5 */ +#if defined(RCC_APB1LENR_CECEN) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN +#else +#define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN +#define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/ +#endif /* RCC_APB1LENR_CECEN */ +#define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN +#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN +#define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN +#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN +#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN +#if defined(TIM23) +#define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN +#endif /* TIM23 */ +#if defined(TIM24) +#define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN +#endif /* TIM24 */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#if defined(UART9) +#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN +#endif /* UART9 */ +#if defined(USART10) +#define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN +#endif /* USART10 */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(SAI3) +#define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN +#endif /* SAI3 */ +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#if defined(HRTIM1) +#define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN +#endif /* HRTIM1 */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH + * @{ + */ +#define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN +#define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN +#define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN +#define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN +#define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN +#define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN +#if defined(LPTIM4) +#define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN +#endif /* LPTIM5 */ +#if defined(DAC2) +#define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN +#endif /* DAC2 */ +#define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN +#define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN +#define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN +#if defined(SAI4) +#define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN +#endif /* SAI4 */ +#if defined(DTS) +#define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN +#endif /* DFSDM2_BASE */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH + * @{ + */ +#if defined(RCC_D3AMR_BDMAAMEN) +#define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN +#else +#define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN +#define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/ +#endif /* RCC_D3AMR_BDMAAMEN */ +#if defined(RCC_SRDAMR_GPIOAMEN) +#define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN +#endif /* RCC_SRDAMR_GPIOAMEN */ +#if defined(RCC_D3AMR_LPUART1AMEN) +#define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN +#else +#define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN +#endif /* RCC_D3AMR_LPUART1AMEN */ +#if defined(RCC_D3AMR_SPI6AMEN) +#define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN +#else +#define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN +#endif /* RCC_D3AMR_SPI6AMEN */ +#if defined(RCC_D3AMR_I2C4AMEN) +#define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN +#else +#define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN +#endif /* RCC_D3AMR_I2C4AMEN */ +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN +#else +#define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN +#endif /* RCC_D3AMR_LPTIM2AMEN */ +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN +#else +#define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN +#endif /* RCC_D3AMR_LPTIM3AMEN */ +#if defined(RCC_D3AMR_LPTIM4AMEN) +#define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN +#endif /* RCC_D3AMR_LPTIM4AMEN */ +#if defined(RCC_D3AMR_LPTIM5AMEN) +#define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN +#endif /* RCC_D3AMR_LPTIM5AMEN */ +#if defined(DAC2) +#define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN +#endif /* DAC2 */ +#if defined(RCC_D3AMR_COMP12AMEN) +#define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN +#else +#define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN +#endif /* RCC_D3AMR_COMP12AMEN */ +#if defined(RCC_D3AMR_VREFAMEN) +#define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN +#else +#define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN +#endif /* RCC_D3AMR_VREFAMEN */ +#if defined(RCC_D3AMR_RTCAMEN) +#define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN +#else +#define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN +#endif /* RCC_D3AMR_RTCAMEN */ +#if defined(RCC_D3AMR_CRCAMEN) +#define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN +#endif /* RCC_D3AMR_CRCAMEN */ +#if defined(SAI4) +#define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN +#endif /* SAI4 */ +#if defined(ADC3) +#define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN +#endif /* ADC3 */ +#if defined(RCC_SRDAMR_DTSAMEN) +#define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN +#endif /* RCC_SRDAMR_DTSAMEN */ +#if defined(RCC_D3AMR_DTSAMEN) +#define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN +#endif /* RCC_D3AMR_DTSAMEN */ +#if defined(DFSDM2_BASE) +#define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN +#endif /* DFSDM2_BASE */ +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN +#else +#define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN +#endif /* RCC_D3AMR_BKPRAMAMEN */ +#if defined(RCC_D3AMR_SRAM4AMEN) +#define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN +#else +#define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN +#define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM +#endif /* RCC_D3AMR_SRAM4AMEN */ +/** + * @} + */ + +#if defined(RCC_CKGAENR_AXICKG) +/** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH + * @{ + */ +#define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG +#define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG +#define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG +#define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG +#define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG +#define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG +#define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG +#define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG +#define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG +#define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG +#define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG +#define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG +#define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG +#define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG +#define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG +#define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG +#define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG +#define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG +#define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG +#define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG +#define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG +/** + * @} + */ +#endif /* RCC_CKGAENR_AXICKG */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4ENR, Periphs); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*) + * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*) + * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n + * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n + * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3ENR, Periphs); +} + +/** + * @brief Force APB3 peripherals reset. + * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*) + * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Release APB3 peripherals reset. + * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*) + * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*) + * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LLPENR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*) + * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*) + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*) + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4ENR, Periphs); +} + +/** + * @brief Force APB4 peripherals reset. + * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Release APB4 peripherals reset. + * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_CLKAM CLKAM + * @{ + */ + +/** + * @brief Enable peripherals clock for CLKAM Mode. + * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n + * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n + * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n + * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n + * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n + * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n + * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n + * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CLKAM_PERIPH_BDMA + * @arg @ref LL_CLKAM_PERIPH_GPIO (*) + * @arg @ref LL_CLKAM_PERIPH_LPUART1 + * @arg @ref LL_CLKAM_PERIPH_SPI6 + * @arg @ref LL_CLKAM_PERIPH_I2C4 + * @arg @ref LL_CLKAM_PERIPH_LPTIM2 + * @arg @ref LL_CLKAM_PERIPH_LPTIM3 + * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) + * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) + * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) + * @arg @ref LL_CLKAM_PERIPH_COMP12 + * @arg @ref LL_CLKAM_PERIPH_VREF + * @arg @ref LL_CLKAM_PERIPH_RTC + * @arg @ref LL_CLKAM_PERIPH_CRC (*) + * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) + * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) + * @arg @ref LL_CLKAM_PERIPH_DTS (*) + * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) + * @arg @ref LL_CLKAM_PERIPH_BKPRAM + * @arg @ref LL_CLKAM_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + +#if defined(RCC_D3AMR_BDMAAMEN) + SET_BIT(RCC->D3AMR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->D3AMR, Periphs); +#else + SET_BIT(RCC->SRDAMR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->SRDAMR, Periphs); +#endif /* RCC_D3AMR_BDMAAMEN */ + (void)tmpreg; +} + +/** + * @brief Disable peripherals clock for CLKAM Mode. + * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n + * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n + * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n + * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n + * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n + * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n + * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n + * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CLKAM_PERIPH_BDMA + * @arg @ref LL_CLKAM_PERIPH_GPIO (*) + * @arg @ref LL_CLKAM_PERIPH_LPUART1 + * @arg @ref LL_CLKAM_PERIPH_SPI6 + * @arg @ref LL_CLKAM_PERIPH_I2C4 + * @arg @ref LL_CLKAM_PERIPH_LPTIM2 + * @arg @ref LL_CLKAM_PERIPH_LPTIM3 + * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) + * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) + * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) + * @arg @ref LL_CLKAM_PERIPH_COMP12 + * @arg @ref LL_CLKAM_PERIPH_VREF + * @arg @ref LL_CLKAM_PERIPH_RTC + * @arg @ref LL_CLKAM_PERIPH_CRC (*) + * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) + * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) + * @arg @ref LL_CLKAM_PERIPH_DTS (*) + * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) + * @arg @ref LL_CLKAM_PERIPH_BKPRAM + * @arg @ref LL_CLKAM_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs) +{ +#if defined(RCC_D3AMR_BDMAAMEN) + CLEAR_BIT(RCC->D3AMR, Periphs); +#else + CLEAR_BIT(RCC->SRDAMR, Periphs); +#endif /* RCC_D3AMR_BDMAAMEN */ +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_CKGA CKGA + * @{ + */ + +#if defined(RCC_CKGAENR_AXICKG) + + +/** + * @brief Enable clock gating for AXI bus peripherals. + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * @retval None +*/ +__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->CKGAENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->CKGAENR, Periphs); + (void)tmpreg; +} + +#endif /* RCC_CKGAENR_AXICKG */ + +#if defined(RCC_CKGAENR_AXICKG) + +/** + * @brief Disable clock gating for AXI bus peripherals. + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * @retval None +*/ +__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) +{ + CLEAR_BIT(RCC->CKGAENR, Periphs); +} + +#endif /* RCC_CKGAENR_AXICKG */ + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @addtogroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable C1 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB3ENR, Periphs); +} + +/** + * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable C1 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB1ENR, Periphs); +} + +/** + * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable C1 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB2ENR, Periphs); +} + +/** + * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable C1 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB4ENR, Periphs); +} + +/** + * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable C1 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB3ENR, Periphs); +} + +/** + * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable C1 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1LENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1HENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable C1 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB2ENR, Periphs); +} + +/** + * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable C1 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB4ENR, Periphs); +} + +/** + * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) + * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) + * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable C2 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB3ENR, Periphs); +} + +/** + * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable C2 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB1ENR, Periphs); +} + +/** + * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable C2 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB2ENR, Periphs); +} + +/** + * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable C2 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB4ENR, Periphs); +} + +/** + * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable C2 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB3ENR, Periphs); +} + +/** + * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n + * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n + * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n + * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n + * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable C2 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1LENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1HENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable C2 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB2ENR, Periphs); +} + +/** + * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable C2 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB4ENR, Periphs); +} + +/** + * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB4LPENR, Periphs); +} + +/** + * @} + */ + +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_BUS_H */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h new file mode 100644 index 0000000..2b63e8f --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h @@ -0,0 +1,669 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_CORTEX_H +#define STM32H7xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01UL /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02UL /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03UL /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04UL /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */ +#if !defined(CORE_CM4) +#define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */ +#define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */ +#define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */ +#define LL_MPU_REGION_NUMBER11 0x0BUL /*!< REGION Number 11 */ +#define LL_MPU_REGION_NUMBER12 0x0CUL /*!< REGION Number 12 */ +#define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */ +#define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */ +#define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */ +#endif /* !defined(CORE_CM4) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ + +/* Legacy Define */ +#define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source); +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK)); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_CORTEX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h new file mode 100644 index 0000000..86ce847 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h @@ -0,0 +1,780 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_CRS_H +#define STM32H7xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 64, which corresponds to the middle of the trimming interval. + * The trimming step is specified in the product datasheet. + * A higher TRIM value corresponds to a higher output frequency. + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 127 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_CRS_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h new file mode 100644 index 0000000..100a2c5 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -0,0 +1,3287 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_DMA_H +#define STM32H7xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_dmamux.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ +static const uint8_t LL_DMA_STR_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) +}; + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Macros DMA LL Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0). + */ +#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Stream + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX1_Request_selection + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_LL_FIFOMODE + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream + + This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_PBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_STREAM STREAM + * @{ + */ +#define LL_DMA_STREAM_0 0x00000000U +#define LL_DMA_STREAM_1 0x00000001U +#define LL_DMA_STREAM_2 0x00000002U +#define LL_DMA_STREAM_3 0x00000003U +#define LL_DMA_STREAM_4 0x00000004U +#define LL_DMA_STREAM_5 0x00000005U +#define LL_DMA_STREAM_6 0x00000006U +#define LL_DMA_STREAM_7 0x00000007U +#define LL_DMA_STREAM_ALL 0xFFFF0000U +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE MODE + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ +#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + * @{ + */ +#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH PERIPH + * @{ + */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY MEMORY + * @{ + */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + * @{ + */ +#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ +#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY PRIORITY + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_MBURST MBURST + * @{ + */ +#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ +#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ +#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ +#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PBURST PBURST + * @{ + */ +#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ +#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ +#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ +#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + * @{ + */ +#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ +#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + * @{ + */ +#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ +#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ +#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ +#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ +#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ +#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + * @{ + */ +#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + * @{ + */ +/** + * @brief Convert DMAx_Streamy into DMAx + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval LL_DMA_STREAM_y + */ +#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + LL_DMA_STREAM_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + * @param __DMA_INSTANCE__ DMAx + * @param __STREAM__ LL_DMA_STREAM_y + * @retval DMAx_Streamy + */ +#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ + DMA2_Stream7) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA stream. + * @rmtoll CR EN LL_DMA_EnableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); +} + +/** + * @brief Disable DMA stream. + * @rmtoll CR EN LL_DMA_DisableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); +} + +/** + * @brief Check if DMA stream is enabled or disabled. + * @rmtoll CR EN LL_DMA_IsEnabledStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters linked to DMA transfer. + * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + * CR CIRC LL_DMA_ConfigTransfer\n + * CR PINC LL_DMA_ConfigTransfer\n + * CR MINC LL_DMA_ConfigTransfer\n + * CR PSIZE LL_DMA_ConfigTransfer\n + * CR MSIZE LL_DMA_ConfigTransfer\n + * CR PL LL_DMA_ConfigTransfer\n + * CR PFCTRL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + *@retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, + DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR)); +} + +/** + * @brief Set DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_SetMode\n + * CR PFCTRL LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); +} + +/** + * @brief Get DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_GetMode\n + * CR PFCTRL LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size); +} + +/** + * @brief Get Memory size. + * @rmtoll CR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE)); +} + +/** + * @brief Set Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param OffsetSize This parameter can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize); +} + +/** + * @brief Get Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + */ +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS)); +} + +/** + * @brief Set Stream priority level. + * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority); +} + +/** + * @brief Get Stream priority level. + * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); +} + +/** + * @brief Enable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + +/** + * @brief Disable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + +/** + * @brief Set Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_SetDataLength + * @note This action has no effect if + * stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param NbData Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_GetDataLength + * @note Once the stream is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT)); +} +/** + * @brief Set DMA request for DMA Streams on DMAMUX Channel x. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mburst This parameter can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst); +} + +/** + * @brief Get Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST)); +} + +/** + * @brief Set Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Pburst This parameter can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst); +} + +/** + * @brief Get Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Get FIFO status. + * @rmtoll FCR FS LL_DMA_GetFIFOStatus + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOSTATUS_0_25 + * @arg @ref LL_DMA_FIFOSTATUS_25_50 + * @arg @ref LL_DMA_FIFOSTATUS_50_75 + * @arg @ref LL_DMA_FIFOSTATUS_75_100 + * @arg @ref LL_DMA_FIFOSTATUS_EMPTY + * @arg @ref LL_DMA_FIFOSTATUS_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS)); +} + +/** + * @brief Disable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Enable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Select FIFO threshold. + * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold); +} + +/** + * @brief Get FIFO threshold. + * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH)); +} + +/** + * @brief Configure the FIFO . + * @rmtoll FCR FTH LL_DMA_ConfigFifo\n + * FCR DMDIS LL_DMA_ConfigFifo + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param FifoMode This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOMODE_ENABLE + * @arg @ref LL_DMA_FIFOMODE_DISABLE + * @param FifoThreshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA stream is enabled. + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * PAR PA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DstAddress Between 0 to 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @rmtoll PAR PA LL_DMA_SetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param PeriphAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress); +} + +/** + * @brief Get the Memory address. + * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); +} + +/** + * @brief Get the Peripheral address. + * @rmtoll PAR PA LL_DMA_GetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_SetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_GetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Stream 0 half transfer flag. + * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 half transfer flag. + * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 half transfer flag. + * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 half transfer flag. + * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 half transfer flag. + * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 half transfer flag. + * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 half transfer flag. + * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 half transfer flag. + * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 transfer complete flag. + * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 transfer complete flag. + * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 transfer complete flag. + * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 transfer complete flag. + * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 transfer complete flag. + * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 transfer complete flag. + * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 transfer complete flag. + * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 transfer complete flag. + * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 transfer error flag. + * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 transfer error flag. + * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 transfer error flag. + * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 transfer error flag. + * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 transfer error flag. + * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 transfer error flag. + * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 transfer error flag. + * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 transfer error flag. + * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 direct mode error flag. + * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 direct mode error flag. + * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 direct mode error flag. + * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 direct mode error flag. + * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 direct mode error flag. + * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 direct mode error flag. + * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 direct mode error flag. + * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 direct mode error flag. + * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 FIFO error flag. + * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 FIFO error flag. + * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 FIFO error flag. + * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 FIFO error flag. + * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 FIFO error flag. + * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 FIFO error flag. + * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 FIFO error flag. + * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 FIFO error flag. + * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Stream 0 half transfer flag. + * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0); +} + +/** + * @brief Clear Stream 1 half transfer flag. + * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1); +} + +/** + * @brief Clear Stream 2 half transfer flag. + * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2); +} + +/** + * @brief Clear Stream 3 half transfer flag. + * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3); +} + +/** + * @brief Clear Stream 4 half transfer flag. + * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4); +} + +/** + * @brief Clear Stream 5 half transfer flag. + * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5); +} + +/** + * @brief Clear Stream 6 half transfer flag. + * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6); +} + +/** + * @brief Clear Stream 7 half transfer flag. + * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7); +} + +/** + * @brief Clear Stream 0 transfer complete flag. + * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0); +} + +/** + * @brief Clear Stream 1 transfer complete flag. + * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1); +} + +/** + * @brief Clear Stream 2 transfer complete flag. + * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2); +} + +/** + * @brief Clear Stream 3 transfer complete flag. + * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3); +} + +/** + * @brief Clear Stream 4 transfer complete flag. + * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4); +} + +/** + * @brief Clear Stream 5 transfer complete flag. + * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5); +} + +/** + * @brief Clear Stream 6 transfer complete flag. + * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6); +} + +/** + * @brief Clear Stream 7 transfer complete flag. + * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7); +} + +/** + * @brief Clear Stream 0 transfer error flag. + * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0); +} + +/** + * @brief Clear Stream 1 transfer error flag. + * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1); +} + +/** + * @brief Clear Stream 2 transfer error flag. + * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2); +} + +/** + * @brief Clear Stream 3 transfer error flag. + * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3); +} + +/** + * @brief Clear Stream 4 transfer error flag. + * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4); +} + +/** + * @brief Clear Stream 5 transfer error flag. + * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5); +} + +/** + * @brief Clear Stream 6 transfer error flag. + * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6); +} + +/** + * @brief Clear Stream 7 transfer error flag. + * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7); +} + +/** + * @brief Clear Stream 0 direct mode error flag. + * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0); +} + +/** + * @brief Clear Stream 1 direct mode error flag. + * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1); +} + +/** + * @brief Clear Stream 2 direct mode error flag. + * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2); +} + +/** + * @brief Clear Stream 3 direct mode error flag. + * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3); +} + +/** + * @brief Clear Stream 4 direct mode error flag. + * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4); +} + +/** + * @brief Clear Stream 5 direct mode error flag. + * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5); +} + +/** + * @brief Clear Stream 6 direct mode error flag. + * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6); +} + +/** + * @brief Clear Stream 7 direct mode error flag. + * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7); +} + +/** + * @brief Clear Stream 0 FIFO error flag. + * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0); +} + +/** + * @brief Clear Stream 1 FIFO error flag. + * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1); +} + +/** + * @brief Clear Stream 2 FIFO error flag. + * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2); +} + +/** + * @brief Clear Stream 3 FIFO error flag. + * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3); +} + +/** + * @brief Clear Stream 4 FIFO error flag. + * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4); +} + +/** + * @brief Clear Stream 5 FIFO error flag. + * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5); +} + +/** + * @brief Clear Stream 6 FIFO error flag. + * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6); +} + +/** + * @brief Clear Stream 7 FIFO error flag. + * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Enable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_EnableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Enable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_EnableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Disable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_DisableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Disable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_DisableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Check if Half transfer interrupt is enabled. + * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error nterrup is enabled. + * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer complete interrupt is enabled. + * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Direct mode error interrupt is enabled. + * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if FIFO error interrupt is enabled. + * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_DMA_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h new file mode 100644 index 0000000..bf4cffa --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h @@ -0,0 +1,2436 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_DMAMUX_H +#define STM32H7xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) || defined (DMAMUX2) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RequestGenerator offset */ +#define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE) +/* Define used to get DMAMUX Channel Status offset */ +#define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE) +/* Define used to get DMAMUX RequestGenerator status offset */ +#define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ +#define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ +#define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection + * @brief DMAMUX1 Request selection + * @{ + */ +/* DMAMUX1 requests */ +#define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */ +#define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ +#define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ +#define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ +#define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ +#define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ +#define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */ +#define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */ +#define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ +#define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ +#define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ +#define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ +#define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ +#define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ +#define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ +#define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ +#define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ +#define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ +#define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ +#define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ +#define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ +#define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ +#define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ +#define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ +#define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ +#define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ +#define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ +#define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ +#define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ +#define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ +#define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ +#define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ +#define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ +#define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ +#define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ +#define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ +#define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ +#define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ +#define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ +#define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ +#define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ +#define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ +#define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ +#define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ +#define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ +#define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ +#define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ +#define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ +#define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ +#define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ +#define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ +#define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ +#define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ +#define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ +#define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ +#define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ +#define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ +#define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ +#define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ +#define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ +#define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ +#define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ +#define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ +#define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ +#define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ +#define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ +#define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ +#define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ +#define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ +#define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ +#define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ +#if defined (PSSI) +#define LL_DMAMUX1_REQ_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ +#define LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */ +#else +#define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif /* PSSI */ +#define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ +#define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ +#define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ +#define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ +#define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ +#define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ +#define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ +#define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ +#define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ +#define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ +#define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ +#define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ +#define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ +#if defined(SAI2) +#define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ +#define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ +#endif /* SAI2 */ +#define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ +#define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ +#define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request */ +#define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */ +#if defined (HRTIM1) +#define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6 */ +#endif /* HRTIM1 */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM1 Filter2 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM1 Filter3 request */ +#define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ +#define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ +#define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ +#define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ +#define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ +#define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ +#define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ +#define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ +#if defined (SAI3) +#define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ +#define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif /* SAI3 */ +#if defined (ADC3) +#define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */ +#endif /* ADC3 */ +#if defined (UART9) +#define LL_DMAMUX1_REQ_UART9_RX 116U /*!< DMAMUX1 UART9 RX request */ +#define LL_DMAMUX1_REQ_UART9_TX 117U /*!< DMAMUX1 UART9 TX request */ +#endif /* UART9 */ +#if defined (USART10) +#define LL_DMAMUX1_REQ_USART10_RX 118U /*!< DMAMUX1 USART10 RX request */ +#define LL_DMAMUX1_REQ_USART10_TX 119U /*!< DMAMUX1 USART10 TX request */ +#endif /* USART10 */ +#if defined(FMAC) +#define LL_DMAMUX1_REQ_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ +#define LL_DMAMUX1_REQ_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ +#endif /* FMAC */ +#if defined(CORDIC) +#define LL_DMAMUX1_REQ_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ +#define LL_DMAMUX1_REQ_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ +#endif /* CORDIC */ +#if defined(I2C5) +#define LL_DMAMUX1_REQ_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ +#define LL_DMAMUX1_REQ_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ +#endif /* I2C5 */ +#if defined(TIM23) +#define LL_DMAMUX1_REQ_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ +#define LL_DMAMUX1_REQ_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ +#define LL_DMAMUX1_REQ_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ +#define LL_DMAMUX1_REQ_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ +#define LL_DMAMUX1_REQ_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ +#define LL_DMAMUX1_REQ_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ +#endif /* TIM23 */ +#if defined(TIM24) +#define LL_DMAMUX1_REQ_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ +#define LL_DMAMUX1_REQ_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ +#define LL_DMAMUX1_REQ_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ +#define LL_DMAMUX1_REQ_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ +#define LL_DMAMUX1_REQ_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ +#define LL_DMAMUX1_REQ_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ +#endif /* TIM24 */ +/** + * @} + */ + +/** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection + * @brief DMAMUX2 Request selection + * @{ + */ +/* DMAMUX2 requests */ +#define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */ +#define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ +#define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ +#define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ +#define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ +#define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ +#define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ +#define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ +#define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ +#define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ +#define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ +#define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ +#define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ +#define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ +#define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ +#if defined (SAI4) +#define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ +#define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ +#endif /* SAI4 */ +#if defined (ADC3) +#define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */ +#endif /* ADC3 */ +#if defined (DAC2) +#define LL_DMAMUX2_REQ_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ +#endif /* DAC2 */ +#if defined (DFSDM2_Channel0) +#define LL_DMAMUX2_REQ_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 Filter0 request */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ + + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ + +#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */ +#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */ +#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */ +#define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */ +#define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */ +#define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */ +#define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */ +#define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */ +#define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */ +#define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */ +#define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */ + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +#define LL_DMAMUX_REQ_GEN_4 0x00000004U +#define LL_DMAMUX_REQ_GEN_5 0x00000005U +#define LL_DMAMUX_REQ_GEN_6 0x00000006U +#define LL_DMAMUX_REQ_GEN_7 0x00000007U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ + +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */ +#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */ +#if defined (LPTIM4) +#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */ +#endif /* LPTIM5 */ +#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */ +#define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */ +#define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */ +#define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */ +#define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */ +#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */ +#define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */ +#if defined (ADC3) +#define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */ +#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */ +#endif /* ADC3 */ +#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */ +#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. + * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. + * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0 + * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0 + * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2 + * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 12. + * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 13. + * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 14. + * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 15. + * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 4 Trigger Event Overrun Flag. + * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 5 Trigger Event Overrun Flag. + * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 6 Trigger Event Overrun Flag. + * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 7 Trigger Event Overrun Flag. + * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 12. + * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 13. + * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 14. + * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 15. + * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15); +} + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @brief Clear Request Generator 4 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4); +} + +/** + * @brief Clear Request Generator 5 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5); +} + +/** + * @brief Clear Request Generator 6 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6); +} + +/** + * @brief Clear Request Generator 7 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE)); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 || DMAMUX2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_DMAMUX_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h new file mode 100644 index 0000000..885f22d --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h @@ -0,0 +1,3285 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_LL_EXTI_H +#define __STM32H7xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_64_95; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ +#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#if defined(USB2_OTG_FS) +#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#endif /* USB2_OTG_FS */ +#if defined(DSI) +#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#endif /* DSI */ +#define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ +#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ +#define LL_EXTI_LINE_49 EXTI_IMR2_IM49 /*!< Extended line 49 */ +#define LL_EXTI_LINE_50 EXTI_IMR2_IM50 /*!< Extended line 50 */ +#define LL_EXTI_LINE_51 EXTI_IMR2_IM51 /*!< Extended line 51 */ +#define LL_EXTI_LINE_52 EXTI_IMR2_IM52 /*!< Extended line 52 */ +#define LL_EXTI_LINE_53 EXTI_IMR2_IM53 /*!< Extended line 53 */ +#define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */ +#define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */ +#define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */ +#if defined(EXTI_IMR2_IM57) +#define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */ +#endif /*EXTI_IMR2_IM57*/ +#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ +#if defined(EXTI_IMR2_IM59) +#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ +#endif /*EXTI_IMR2_IM59*/ +#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ +#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ +#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ +#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_64 EXTI_IMR3_IM64 /*!< Extended line 64 */ +#define LL_EXTI_LINE_65 EXTI_IMR3_IM65 /*!< Extended line 65 */ +#define LL_EXTI_LINE_66 EXTI_IMR3_IM66 /*!< Extended line 66 */ +#define LL_EXTI_LINE_67 EXTI_IMR3_IM67 /*!< Extended line 67 */ +#define LL_EXTI_LINE_68 EXTI_IMR3_IM68 /*!< Extended line 68 */ +#define LL_EXTI_LINE_69 EXTI_IMR3_IM69 /*!< Extended line 69 */ +#define LL_EXTI_LINE_70 EXTI_IMR3_IM70 /*!< Extended line 70 */ +#define LL_EXTI_LINE_71 EXTI_IMR3_IM71 /*!< Extended line 71 */ +#define LL_EXTI_LINE_72 EXTI_IMR3_IM72 /*!< Extended line 72 */ +#define LL_EXTI_LINE_73 EXTI_IMR3_IM73 /*!< Extended line 73 */ +#define LL_EXTI_LINE_74 EXTI_IMR3_IM74 /*!< Extended line 74 */ +#if defined(ADC3) +#define LL_EXTI_LINE_75 EXTI_IMR3_IM75 /*!< Extended line 75 */ +#endif /* ADC3 */ +#if defined(SAI4) +#define LL_EXTI_LINE_76 EXTI_IMR3_IM76 /*!< Extended line 76 */ +#endif /* SAI4 */ +#if defined(DUAL_CORE) +#define LL_EXTI_LINE_77 EXTI_IMR3_IM77 /*!< Extended line 77 */ +#define LL_EXTI_LINE_78 EXTI_IMR3_IM78 /*!< Extended line 78 */ +#define LL_EXTI_LINE_79 EXTI_IMR3_IM79 /*!< Extended line 79 */ +#define LL_EXTI_LINE_80 EXTI_IMR3_IM80 /*!< Extended line 80 */ +#define LL_EXTI_LINE_82 EXTI_IMR3_IM82 /*!< Extended line 82 */ +#define LL_EXTI_LINE_84 EXTI_IMR3_IM84 /*!< Extended line 84 */ +#endif /* DUAL_CORE */ +#define LL_EXTI_LINE_85 EXTI_IMR3_IM85 /*!< Extended line 85 */ +#if defined(ETH) +#define LL_EXTI_LINE_86 EXTI_IMR3_IM86 /*!< Extended line 86 */ +#endif /* ETH */ +#define LL_EXTI_LINE_87 EXTI_IMR3_IM87 /*!< Extended line 87 */ +#if defined(DTS) +#define LL_EXTI_LINE_88 EXTI_IMR3_IM88 /*!< Extended line 88 */ +#endif /* DTS */ +#if defined(EXTI_IMR3_IM89) +#define LL_EXTI_LINE_89 EXTI_IMR3_IM89 /*!< Extended line 89 */ +#endif /* EXTI_IMR3_IM89 */ +#if defined(EXTI_IMR3_IM90) +#define LL_EXTI_LINE_90 EXTI_IMR3_IM90 /*!< Extended line 90 */ +#endif /* EXTI_IMR3_IM90 */ +#if defined(I2C5) +#define LL_EXTI_LINE_91 EXTI_IMR3_IM91 /*!< Extended line 91 */ +#endif /* I2C5 */ +#define LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x01U) /*!< Cortex-M7 Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x02U) /*!< Cortex-M7 Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U) /*!< Cortex-M7 Interrupt & Event Mode */ + +#if defined(DUAL_CORE) +#define LL_EXTI_MODE_C1_IT LL_EXTI_MODE_IT /*!< Cortex-M7 Interrupt Mode */ +#define LL_EXTI_MODE_C1_EVENT LL_EXTI_MODE_EVENT /*!< Cortex-M7 Event Mode */ +#define LL_EXTI_MODE_C1_IT_EVENT LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */ + +#define LL_EXTI_MODE_C2_IT ((uint8_t)0x10U) /*!< Cortex-M4 Interrupt Mode */ +#define LL_EXTI_MODE_C2_EVENT ((uint8_t)0x20U) /*!< Cortex-M4 Event Mode */ +#define LL_EXTI_MODE_C2_IT_EVENT ((uint8_t)0x30U) /*!< Cortex-M4 Interrupt & Event Mode */ +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source + * @{ + */ +#define LL_EXTI_D3_PEND_CLR_DMACH6 ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */ +#define LL_EXTI_D3_PEND_CLR_DMACH7 ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */ +#if defined (LPTIM4) +#define LL_EXTI_D3_PEND_CLR_LPTIM4 ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */ +#else +#define LL_EXTI_D3_PEND_CLR_LPTIM2 ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */ +#endif /*LPTIM4*/ +#if defined (LPTIM5) +#define LL_EXTI_D3_PEND_CLR_LPTIM5 ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */ +#else +#define LL_EXTI_D3_PEND_CLR_LPTIM3 ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */ +#endif /*LPTIM5*/ +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) + +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR1, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR2, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR1, ExtiLine); +} + + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR2, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#endif /* DUAL_CORE */ + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(DUAL_CORE) + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR1, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR1, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR2, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_EnableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_DisableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR3, ExtiLine); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll RTSR3 RTx LL_EXTI_IsEnabledRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR3 FTx LL_EXTI_EnableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR3 FTx LL_EXTI_DisableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR3, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll FTSR3 FTx LL_EXTI_IsEnabledFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR1 + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 64 to 95 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR3 + * register (by writing a 1 into the bit) + * @rmtoll SWIER3 SWIx LL_EXTI_GenerateSWI_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER3, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_IsActiveFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_ReadFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine)); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_ClearFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR3, ExtiLine); +} + +#if defined(DUAL_CORE) + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_IsActiveFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_ReadFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine)); +} +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_ClearFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR3, ExtiLine); +} + +#endif /* DUAL_CORE */ + +/** + * @brief Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_EnablePendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->D3PMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_EnablePendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->D3PMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_DisablePendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->D3PMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_DisablePendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->D3PMR2, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_IsEnabledPendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_IsEnabledPendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15 + * @rmtoll D3PCR1L PCSx LL_D3_EXTI_SetPendClearSel_0_15 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc)); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31 + * @rmtoll D3PCR1H PCSx LL_D3_EXTI_SetPendClearSel_16_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc)); +} + + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47 + * @rmtoll D3PCR2L PCSx LL_D3_EXTI_SetPendClearSel_32_47 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc)); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63 + * @rmtoll D3PCR2H PCSx LL_D3_EXTI_SetPendClearSel_48_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15 + * @rmtoll D3PCR1L PCSx LL_D3_EXTI_GetPendClearSel_0_15 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31 + * @rmtoll D3PCR1H PCSx LL_D3_EXTI_GetPendClearSel_16_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos))); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47 + * @rmtoll D3PCR2L PCSx LL_D3_EXTI_GetPendClearSel_32_47 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63 + * @rmtoll D3PCR2H PCSx LL_D3_EXTI_GetPendClearSel_48_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos))); +} + + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{, + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_EXTI_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h new file mode 100644 index 0000000..b51f9d3 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h @@ -0,0 +1,984 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_GPIO_H +#define STM32H7xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask << 16U); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_GPIO_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h new file mode 100644 index 0000000..cff88b5 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h @@ -0,0 +1,902 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_HSEM_H +#define STM32H7xx_LL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(HSEM) + +/** @defgroup HSEM_LL HSEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants + * @{ + */ + +/** @defgroup HSEM_LL_EC_COREID COREID Defines + * @{ + */ +#define LL_HSEM_COREID_NONE 0U +#define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1 +#if defined(DUAL_CORE) +#define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2 +#endif /* DUAL_CORE */ +#define LL_HSEM_COREID HSEM_CR_COREID_CURRENT +/** + * @} + */ + + +/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_HSEM_ReadReg function + * @{ + */ + +#define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0 +#define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1 +#define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2 +#define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3 +#define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4 +#define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5 +#define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6 +#define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7 +#define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8 +#define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9 +#define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10 +#define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11 +#define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12 +#define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13 +#define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14 +#define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15 +#if (HSEM_SEMID_MAX == 15) +#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU +#else /* HSEM_SEMID_MAX == 31 */ +#define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16 +#define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17 +#define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18 +#define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19 +#define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20 +#define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21 +#define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22 +#define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23 +#define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24 +#define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25 +#define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26 +#define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27 +#define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28 +#define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29 +#define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30 +#define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31 +#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +#endif /* HSEM_SEMID_MAX == 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_LL_EF_Data_Management Data_Management + * @{ + */ + + +/** + * @brief Return 1 if the semaphore is locked, else return 0. + * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Get core id. + * @rmtoll R COREID LL_HSEM_GetCoreId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HSEM_COREID_NONE + * @arg @ref LL_HSEM_COREID_CPU1 + * @arg @ref LL_HSEM_COREID_CPU2 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); +} + +/** + * @brief Get process id. + * @rmtoll R PROCID LL_HSEM_GetProcessId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Process number. Value between Min_Data=0 and Max_Data=255 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); +} + +/** + * @brief Get the lock by writing in R register. + * @note The R register has to be read to determined if the lock is taken. + * @rmtoll R LOCK LL_HSEM_SetLock + * @rmtoll R COREID LL_HSEM_SetLock + * @rmtoll R PROCID LL_HSEM_SetLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); +} + +/** + * @brief Get the lock with 2-step lock. + * @rmtoll R LOCK LL_HSEM_2StepLock + * @rmtoll R COREID LL_HSEM_2StepLock + * @rmtoll R PROCID LL_HSEM_2StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @retval 1 lock fail, 0 lock successful or already locked by same process and core + */ +__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); + return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL); +} + +/** + * @brief Get the lock with 1-step lock. + * @rmtoll RLR LOCK LL_HSEM_1StepLock + * @rmtoll RLR COREID LL_HSEM_1StepLock + * @rmtoll RLR PROCID LL_HSEM_1StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval 1 lock fail, 0 lock successful or already locked by same core + */ +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); +} + +/** + * @brief Release the lock of the semaphore. + * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0. + * @rmtoll R LOCK LL_HSEM_ReleaseLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process number. Value between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process)); +} + +/** + * @brief Get the lock status of the semaphore. + * @rmtoll R LOCK LL_HSEM_GetStatus + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval 0 semaphore is free, 1 semaphore is locked */ +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); +} + +/** + * @brief Set the key. + * @rmtoll KEYR KEY LL_HSEM_SetKey + * @param HSEMx HSEM Instance. + * @param key Key value. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) +{ + WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Get the key. + * @rmtoll KEYR KEY LL_HSEM_GetKey + * @param HSEMx HSEM Instance. + * @retval key to unlock all semaphore from the same core + */ +__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) +{ + return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Release all semaphore with the same core id. + * @rmtoll CR KEY LL_HSEM_ResetAllLock + * @rmtoll CR SEC LL_HSEM_ResetAllLock + * @rmtoll CR PRIV LL_HSEM_ResetAllLock + * @param HSEMx HSEM Instance. + * @param key Key value. + * @param core This parameter can be one of the following values: + * @arg @ref LL_HSEM_COREID_CPU1 + * @arg @ref LL_HSEM_COREID_CPU2 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) +{ + WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); +} + +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable interrupt. + * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + SET_BIT(HSEMx->C1IER, SemaphoreMask); +} + +/** + * @brief Disable interrupt. + * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + CLEAR_BIT(HSEMx->C1IER, SemaphoreMask); +} + +/** + * @brief Check if interrupt is enabled. + * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable interrupt. + * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + SET_BIT(HSEMx->C2IER, SemaphoreMask); +} + +/** + * @brief Disable interrupt. + * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + CLEAR_BIT(HSEMx->C2IER, SemaphoreMask); +} + +/** + * @brief Check if interrupt is enabled. + * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Clear interrupt status. + * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + WRITE_REG(HSEMx->C1ICR, SemaphoreMask); +} + +/** + * @brief Get interrupt status from ISR register. + * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +/** + * @brief Get interrupt status from MISR register. + * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Clear interrupt status. + * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + WRITE_REG(HSEMx->C2ICR, SemaphoreMask); +} + +/** + * @brief Get interrupt status from ISR register. + * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +/** + * @brief Get interrupt status from MISR register. + * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(HSEM) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_HSEM_H */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h new file mode 100644 index 0000000..be137a4 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h @@ -0,0 +1,2301 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_PWR_H +#define STM32H7xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +/* Wake-Up Pins PWR register offsets */ +#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL +#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU +/** + * @} + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */ +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */ +#endif /* DUAL_CORE */ +#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */ +#if defined (PWR_WKUPCR_WKUPC5) +#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */ +#endif /* defined (PWR_WKUPCR_WKUPC5) */ +#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */ +#if defined (PWR_WKUPCR_WKUPC3) +#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */ +#endif /* defined (PWR_WKUPCR_WKUPC3) */ +#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */ +#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */ +#define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */ +#define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */ +#define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */ +#if defined (PWR_CSR1_MMCVDO) +#define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */ +#endif /* PWR_CSR1_MMCVDO */ + +#define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */ +#define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */ +#define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */ +#define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */ +#define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */ + +#define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */ +#define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */ + +#if defined (PWR_CPUCR_SBF_D2) +#define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ +#endif /* PWR_CPUCR_SBF_D2 */ +#if defined (PWR_CPUCR_SBF_D1) +#define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ +#endif /* PWR_CPUCR_SBF_D1 */ +#define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */ +#define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */ +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */ +#endif /* DUAL_CORE */ + +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ +#define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ +#define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */ +#define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */ +#define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */ +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */ +#else +#define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ +#if defined (PWR_WKUPFR_WKUPF5) +#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ +#endif /* defined (PWR_WKUPFR_WKUPF5) */ +#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Power mode + * @{ + */ +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */ +#else +#define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */ +#define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */ +#else +#define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */ +#define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +#define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */ +#define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling + * @{ + */ +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */ +#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */ +#endif /* defined (SYSCFG_PWRCR_ODEN) */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ +#endif /* PWR_CPUCR_PDDS_D2 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector + * @{ + */ +#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */ +#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ +#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */ +#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */ +#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */ +#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector + * @{ + */ +#define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */ +#define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */ +#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */ +#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */ + +/** + * @} + */ + +/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */ +#define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */ +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */ +#if defined (PWR_WKUPEPR_WKUPEN5) +#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */ +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration + * @{ + */ +#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */ +#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */ +#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration + * @{ + */ +#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ +#if defined (SMPS) +#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */ +#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ +#define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ +#endif /* SMPS */ +#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + + /** + * @brief Set the voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); +} + +/** + * @brief Get the voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR1 PVDEN LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR1 PVDEN LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR1 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR1 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); +} + +#if defined (PWR_CR1_BOOSTE) +/** + * @brief Enable the Analog Voltage Booster (VDDA) + * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the Analog Voltage Booster (VDDA) + * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_BOOSTE */ + +#if defined (PWR_CR1_AVD_READY) +/** + * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready + * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVD_READY); +} + +/** + * @brief Disable the Analog Voltage Ready (VDDA) + * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AVD_READY */ + +/** + * @brief Set the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); +} + +/** + * @brief Get the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + */ +__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS)); +} + +/** + * @brief Enable Analog Power Voltage Detector + * @rmtoll CR1 AVDEN LL_PWR_EnableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable Analog Power Voltage Detector + * @rmtoll CR1 AVDEN LL_PWR_DisableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Check if Analog Power Voltage Detector is enabled + * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll CR1 ALS LL_PWR_SetAVDLevel + * @param AVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); +} + +/** + * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll CR1 ALS LL_PWR_GetAVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS)); +} + +#if defined (PWR_CR1_AXIRAM1SO) +/** + * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); +} + +/** + * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); +} + +/** + * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM1SO */ + +#if defined (PWR_CR1_AXIRAM2SO) +/** + * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); +} + +/** + * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); +} + +/** + * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM2SO */ + +#if defined (PWR_CR1_AXIRAM3SO) +/** + * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); +} + +/** + * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); +} + +/** + * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM3SO */ + +#if defined (PWR_CR1_AHBRAM1SO) +/** + * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); +} + +/** + * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); +} + +/** + * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AHBRAM1SO */ + +#if defined (PWR_CR1_AHBRAM2SO) +/** + * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); +} + +/** + * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); +} + +/** + * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AHBRAM2SO */ + +#if defined (PWR_CR1_ITCMSO) +/** + * @brief Enable the ITCM shut-off in DStop/DStop2 mode + * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ITCMSO); +} + +/** + * @brief Disable the ITCM shut-off in DStop/DStop2 mode + * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO); +} + +/** + * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_ITCMSO */ + +#if defined (PWR_CR1_HSITFSO) +/** + * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode + * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_HSITFSO); +} + +/** + * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode + * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO); +} + +/** + * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_HSITFSO */ + +#if defined (PWR_CR1_SRDRAMSO) +/** + * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode + * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); +} + +/** + * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode + * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); +} + +/** + * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_SRDRAMSO */ + +/** + * @brief Enable Backup Regulator + * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator + * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and + * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup + * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, + * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that + * the data written into the RAM will be maintained in the Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_BREN); +} + +/** + * @brief Disable Backup Regulator + * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_BREN); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL); +} + +/** + * @brief Enable VBAT and Temperature monitoring + * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMonitoring(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Disable VBAT and Temperature monitoring + * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Check if the VBAT and Temperature monitoring is enabled + * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL); +} + +#if defined (SMPS) +/** + * @brief Configure the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply + * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); +} +#else +/** + * @brief Configure the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply + * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply + * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); +} +#endif /* defined (SMPS) */ + +#if defined (SMPS) +/** + * @brief Get the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_GetSupply + * @rmtoll CR3 LDOEN LL_PWR_GetSupply + * @rmtoll CR3 SMPSEN LL_PWR_GetSupply + * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply + * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); +} +#else +/** + * @brief Get the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_GetSupply + * @rmtoll CR3 LDOEN LL_PWR_GetSupply + * @rmtoll CR3 SCUEN LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); +} +#endif /* defined (SMPS) */ + +/** + * @brief Enable battery charging + * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Disable battery charging + * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Check if battery charging is enabled + * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Battery charge resistor impedance + * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor); +} + +/** + * @brief Get the Battery charge resistor impedance + * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS)); +} + +/** + * @brief Enable the USB regulator + * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBReg(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_USBREGEN); +} + +/** + * @brief Disable the USB regulator + * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBReg(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN); +} + +/** + * @brief Check if the USB regulator is enabled + * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the USB voltage detector + * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Disable the USB voltage detector + * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Check if the USB voltage detector is enabled + * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL); +} + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D1STOP + * @arg @ref LL_PWR_CPU_MODE_D1STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); +} +#else +/** + * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_CDSTOP + * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D1STOP + * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D1STOP + * @arg @ref LL_PWR_CPU_MODE_D1STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); +} +#else +/** + * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_CDSTOP + * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D1STOP + * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1)); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D2STOP + * @arg @ref LL_PWR_CPU_MODE_D2STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D2STOP + * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D2STOP + * @arg @ref LL_PWR_CPU_MODE_D2STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D2STOP + * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2)); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D3STOP + * @arg @ref LL_PWR_CPU_MODE_D3STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); +} +#else +/** + * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_SRDSTOP + * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D3STOP + * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D3STOP + * @arg @ref LL_PWR_CPU_MODE_D3STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3)); +} +#else +/** + * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_SRDSTOP + * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D3STOP + * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3)); +} +#endif /* DUAL_CORE */ + +#if defined (DUAL_CORE) +/** + * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode + * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_HoldCPU1(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); +} + +/** + * @brief Release the CPU1 and allocated peripherals + * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ReleaseCPU1(void) +{ + CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); +} + +/** + * @brief Ckeck if the CPU1 and allocated peripherals are held + * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL); +} + +/** + * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode + * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_HoldCPU2(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); +} + +/** + * @brief Release the CPU2 and allocated peripherals + * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ReleaseCPU2(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); +} + +/** + * @brief Ckeck if the CPU2 and allocated peripherals are held + * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief D3 domain remains in Run mode regardless of CPU subsystem modes + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); +} +#else +/** + * @brief SRD domain remains in Run mode regardless of CPU subsystem modes + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief D3 domain follows CPU subsystem modes + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); +} +#else +/** + * @brief SRD domain follows CPU subsystem modes + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief D3 domain follows CPU2 subsystem modes + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Check if D3 is kept in Run mode when CPU enters low power mode + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL); +} +#else +/** + * @brief Check if SRD is kept in Run mode when CPU enters low power mode + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 + * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ +#if defined (PWR_CPUCR_PDDS_D2) + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); +#else + MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling + * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking + * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit. + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ +#if defined (PWR_CPUCR_PDDS_D2) + return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS)); +#else + return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS)); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin Pull None + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Up + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Down + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Get the Wake-Up pin pull + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL + * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP + * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) +{ + uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the voltage level is ready for current actual used VOS + * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDDA voltage is below the selected AVD threshold + * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); +} + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief Indicate whether VDDMMC voltage is below 1V2 + * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL); +} +#endif /* PWR_CSR1_MMCVDO */ + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below low threshold + * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below high threshold + * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below low threshold + * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below high threshold + * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL); +} + +#if defined (SMPS) +/** + * @brief Indicate whether the SMPS external supply is ready or not + * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL); +} +#endif /* SMPS */ + +/** + * @brief Indicate whether the USB supply is ready or not + * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get HOLD2 Flag + * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL); +} + +/** + * @brief Get HOLD1 Flag + * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get CPU System Stop Flag + * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 System Stop Flag + * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get CPU System Standby Flag + * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 System Standby Flag + * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_SBF_D1) +/** + * @brief Get CPU D1 Domain Standby Flag + * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_SBF_D1 */ + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 D1 Domain Standby Flag + * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_SBF_D2) +/** + * @brief Get CPU D2 Domain Standby Flag + * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_SBF_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 D2 Domain Standby Flag + * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range + * or if its output voltage is still changing to the required voltage level + * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ +#if defined (PWR_CPUCR_PDDS_D2) + return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL); +#else + return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Get Wake-up Flag 6 + * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL); +} + +#if defined (PWR_WKUPFR_WKUPF5) +/** + * @brief Get Wake-up Flag 5 + * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL); +} +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); +} + +#if defined (PWR_WKUPFR_WKUPF3) +/** + * @brief Get Wake-up Flag 3 + * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); +} +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); +} + +/** + * @brief Clear CPU STANDBY, STOP and HOLD flags + * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); +} + +#if defined (DUAL_CORE) +/** + * @brief Clear CPU2 STANDBY, STOP and HOLD flags + * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); +} +#endif /* DUAL_CORE */ + +/** + * @brief Clear Wake-up Flag 6 + * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6); +} + +#if defined (PWR_WKUPCR_WKUPC5) +/** + * @brief Clear Wake-up Flag 5 + * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5); +} +#endif /* defined (PWR_WKUPCR_WKUPC5) */ + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); +} + +#if defined (PWR_WKUPCR_WKUPC3) +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); +} +#endif /* defined (PWR_WKUPCR_WKUPC3) */ + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); +} + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_PWR_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h new file mode 100644 index 0000000..bd700dc --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h @@ -0,0 +1,6404 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_RCC_H +#define STM32H7xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ +extern const uint8_t LL_RCC_PrescTable[16]; + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif + +/* 32 24 16 8 0 + -------------------------------------------------------- + | Mask | ClkSource | Bit | Register | + | | Config | Position | Offset | + --------------------------------------------------------*/ + +#if defined(RCC_VER_2_0) +/* Clock source register offset Vs CDCCIPR register */ +#define CDCCIP 0x0UL +#define CDCCIP1 0x4UL +#define CDCCIP2 0x8UL +#define SRDCCIP 0xCUL +#else +/* Clock source register offset Vs D1CCIPR register */ +#define D1CCIP 0x0UL +#define D2CCIP1 0x4UL +#define D2CCIP2 0x8UL +#define D3CCIP 0xCUL +#endif /* RCC_VER_2_0 */ + +#define LL_RCC_REG_SHIFT 0U +#define LL_RCC_POS_SHIFT 8U +#define LL_RCC_CONFIG_SHIFT 16U +#define LL_RCC_MASK_SHIFT 24U + +#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) + +#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) + +#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ + (( __POS__ ) << LL_RCC_POS_SHIFT) | \ + (( __REG__ ) << LL_RCC_REG_SHIFT) | \ + (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t CPUCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; + uint32_t PCLK3_Frequency; + uint32_t PCLK4_Frequency; +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @brief PLL Clocks Frequency Structure + */ +typedef struct +{ + uint32_t PLL_P_Frequency; + uint32_t PLL_Q_Frequency; + uint32_t PLL_R_Frequency; +} LL_PLL_ClocksTypeDef; + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#if defined(RCC_VER_X) || defined(RCC_VER_3_0) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#else +#define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* RCC_VER_X || RCC_VER_3_0 */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */ +#endif /* CSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider + * @{ + */ +#define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1 +#define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2 +#define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4 +#define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U) +#define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0) +#define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1) +#define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI +#define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE +#define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source + * @{ + */ +#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) +#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source + * @{ + */ +#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) +#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler + * @{ + */ +#if defined(RCC_D1CFGR_D1CPRE_DIV1) +#define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1 +#define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2 +#define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4 +#define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8 +#define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16 +#define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64 +#define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128 +#define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256 +#define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512 +#else +#define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1 +#define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2 +#define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4 +#define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8 +#define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16 +#define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64 +#define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128 +#define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256 +#define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512 +#endif /* RCC_D1CFGR_D1CPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler + * @{ + */ +#if defined(RCC_D1CFGR_HPRE_DIV1) +#define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1 +#define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2 +#define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4 +#define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8 +#define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16 +#define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64 +#define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128 +#define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256 +#define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512 +#else +#define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1 +#define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2 +#define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4 +#define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8 +#define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16 +#define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64 +#define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128 +#define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256 +#define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512 +#endif /* RCC_D1CFGR_HPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#if defined(RCC_D2CFGR_D2PPRE1_DIV1) +#define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1 +#define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2 +#define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4 +#define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8 +#define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16 +#else +#define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1 +#define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2 +#define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4 +#define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8 +#define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16 +#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2) + * @{ + */ +#if defined(RCC_D2CFGR_D2PPRE2_DIV1) +#define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1 +#define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2 +#define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4 +#define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8 +#define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16 +#else +#define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1 +#define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2 +#define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4 +#define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8 +#define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16 +#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3) + * @{ + */ +#if defined(RCC_D1CFGR_D1PPRE_DIV1) +#define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1 +#define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2 +#define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4 +#define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8 +#define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16 +#else +#define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1 +#define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2 +#define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4 +#define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8 +#define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16 +#endif /* RCC_D1CFGR_D1PPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4) + * @{ + */ +#if defined(RCC_D3CFGR_D3PPRE_DIV1) +#define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1 +#define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2 +#define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4 +#define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8 +#define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16 +#else +#define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1 +#define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2 +#define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4 +#define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8 +#define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16 +#endif /* RCC_D3CFGR_D3PPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U) +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0) +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1) +#define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) +#define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2) +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U) +#define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0) +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1) +#define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) +#define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2) +#define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE) +#define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE) + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U) +#define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5) +#define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0) +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1) +#define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) +#define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2) +#define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) +/* Aliases */ +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_RCC_USART16_CLKSOURCE_PCLK2 +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_RCC_USART16_CLKSOURCE_PLL2Q +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_RCC_USART16_CLKSOURCE_PLL3Q +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_RCC_USART16_CLKSOURCE_HSI +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_RCC_USART16_CLKSOURCE_CSI +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_RCC_USART16_CLKSOURCE_LSE + +#elif defined(RCC_D2CCIP2R_USART16910SEL) +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0) +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2) +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) +/* Aliases */ +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q +#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI +#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI +#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE + +#else +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0) +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2) +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) +/* Aliases */ +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q +#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI +#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI +#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE +#endif /* RCC_D2CCIP2R_USART16SEL */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) +#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2) +#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) +#else +#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) +#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2) +#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) +#endif /* RCC_D2CCIP2R_USART28SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#if defined(RCC_D3CCIPR_LPUART1SEL) +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2) +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2) +#else +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2) +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2) +#endif /* RCC_D3CCIPR_LPUART1SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#if defined (RCC_D2CCIP2R_I2C123SEL) +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0) +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1) +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) +/* Aliases */ +#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_RCC_I2C123_CLKSOURCE_PCLK1 +#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_RCC_I2C123_CLKSOURCE_PLL3R +#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_RCC_I2C123_CLKSOURCE_HSI +#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_RCC_I2C123_CLKSOURCE_CSI + +#elif defined (RCC_D2CCIP2R_I2C1235SEL) +#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) +#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0) +#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1) +#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) +/* Aliases */ +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1 +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI + +#else +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0) +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1) +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) +#endif /* RCC_D2CCIP2R_I2C123SEL */ +#if defined (RCC_D3CCIPR_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) +#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1) +#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) +#else +#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) +#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1) +#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) +#endif /* RCC_D3CCIPR_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) +#else +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2) +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) +#else +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2) +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2) +#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) +#else +#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2) +#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) +/* aliases*/ +#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4 +#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P +#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R +#define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE +#define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI +#define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP +#endif /* RCC_D3CCIPR_LPTIM345SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2) +#else +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2) +#endif +#if defined(SAI3) +#define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) +#define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0) +#define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1) +#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) +#define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2) +#endif /* SAI3 */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) +#define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0) +#define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1) +#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) +#define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2) +#define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) +#define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0) +#define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1) +#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) +#define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2) +#define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI4_Block_A) +#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) +#define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0) +#define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1) +#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) +#define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2) +#if defined(RCC_VER_3_0) +#define LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) +#endif /* RCC_VER_3_0 */ +#endif /* SAI4_Block_A */ +#if defined(SAI4_Block_B) +#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) +#define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0) +#define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1) +#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) +#define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2) +#if defined(RCC_VER_3_0) +#define LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) +#endif /* RCC_VER_3_0 */ +#endif /* SAI4_Block_B */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL) +#else +#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL) +#endif /* RCC_D1CCIPR_SDMMCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) +#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0) +#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1) +#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0) +#else +#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) +#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0) +#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1) +#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0) +#endif /* RCC_D2CCIP2R_RNGSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) +#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0) +#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1) +#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0) +#else +#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) +#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0) +#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1) +#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0) +#endif /* RCC_D2CCIP2R_USBSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) +#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0) +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1) +#else +#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) +#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0) +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1) +#endif +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY (0x00000000U) +#define LL_RCC_DSI_CLKSOURCE_PLL2Q (RCC_D1CCIPR_DSISEL) +/** + * @} + */ +#endif /* DSI */ + +/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL) +#else +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +/** + * @} + */ + +#if defined(DFSDM2_BASE) +/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 clock source selection + * @{ + */ +#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL) +/** + * @} + */ +#endif /* DFSDM2_BASE */ + +/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0) +#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1) +#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1) +#else +#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0) +#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1) +#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1) +#endif /* RCC_D1CCIPR_FMCSEL */ +/** + * @} + */ + +#if defined(QUADSPI) +/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection + * @{ + */ +#define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0) +#define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1) +#define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1) +/** + * @} + */ +#endif /* QUADSPI */ + + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_OCTOSPISEL) +#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0) +#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1) +#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1) +#else +#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0) +#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1) +#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1) +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +/** + * @} + */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + + +/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) +#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1) +#else +#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) +#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1) +#endif /* RCC_D1CCIPR_CKPERSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) +#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0) +#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2) +#else +#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) +#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0) +#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2) +#endif /* RCC_D2CCIP1R_SPI123SEL */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) +#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) +#else +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) +#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) +#endif /* (RCC_D2CCIP1R_SPI45SEL */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) +#else +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) +#endif /* RCC_D3CCIPR_SPI6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0) +#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1) +#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1) +#else +#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0) +#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1) +#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +/** + * @} + */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0) +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1) +#else +#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0) +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1) +#endif /* RCC_D2CCIP1R_FDCANSEL */ +/** + * @} + */ +#endif /*FDCAN1 || FDCAN2*/ + +/** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) +#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL) +#else +#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) +#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL) +#endif /* RCC_D2CCIP1R_SWPSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) +#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0) +#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1) +#else +#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) +#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0) +#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1) +#endif /* RCC_D3CCIPR_ADCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source + * @{ + */ +#if defined (RCC_D2CCIP2R_USART16SEL) +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) +#elif defined (RCC_D2CCIP2R_USART16910SEL) +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) +/* alias*/ +#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE +#else +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) +/* alias*/ +#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ +#if defined (RCC_D2CCIP2R_USART28SEL) +#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) +#else +#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP2R_USART28SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source + * @{ + */ +#if defined(RCC_D3CCIPR_LPUART1SEL) +#define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL +#else +#define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL +#endif /* RCC_D3CCIPR_LPUART1SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source + * @{ + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE +#elif defined(RCC_D2CCIP2R_I2C1235SEL) +#define LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE +#else +#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE +#endif /* RCC_D2CCIP2R_I2C123SEL */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) +#else +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source + * @{ + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP2R_LPTIM1SEL) */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */ +#endif /* RCC_D3CCIPR_LPTIM345SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SAI1SEL */ +#if defined(RCC_D2CCIP1R_SAI23SEL) +#define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SAI23SEL */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(RCC_D3CCIPR_SAI4ASEL) +#define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SAI4ASEL */ +#if defined(RCC_D3CCIPR_SAI4BSEL) +#define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SAI4BSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL +#else +#define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL +#endif /* RCC_D1CCIPR_SDMMCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#if (RCC_D2CCIP2R_RNGSEL) +#define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL +#else +#define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL +#endif /* RCC_D2CCIP2R_RNGSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#if (RCC_D2CCIP2R_USBSEL) +#define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL +#else +#define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL +#endif /* RCC_D2CCIP2R_USBSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#if (RCC_D2CCIP2R_CECSEL) +#define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL +#else +#define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL +#endif /* RCC_D2CCIP2R_CECSEL */ +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL +/** + * @} + */ +#endif /* DSI */ + +/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL +#else +#define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +/** + * @} + */ + +#if defined(DFSDM2_BASE) +/** @defgroup RCC_LL_EC_DFSDM2 Peripheral DFSDM2 get clock source + * @{ + */ +#define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL +/** + * @} + */ +#endif /* DFSDM2_BASE */ + + + +/** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL +#else +#define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL +#endif +/** + * @} + */ + +#if defined(QUADSPI) +/** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source + * @{ + */ +#define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL +/** + * @} + */ +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source + * @{ + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL +#else +#define LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL +#endif /* RCC_CDCCIPR_OCTOSPISEL */ +/** + * @} + */ +#endif /* OCTOSPI1 || OCTOSPI2 */ + +/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL +#else +#define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL +#endif /* RCC_D1CCIPR_CKPERSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SPI123SEL */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SPI45SEL */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SPI6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL +#else +#define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +/** + * @} + */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL +#else +#define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL +#endif +/** + * @} + */ +#endif /*FDCAN1 || FDCAN2*/ + +/** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL +#else +#define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL +#endif /* RCC_D2CCIP1R_SWPSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL +#else +#define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL +#endif /* RCC_D3CCIPR_ADCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U) +#define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0) +#define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1) +#define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U) +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE) +/** + * @} + */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection + * @{ + */ +#define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */ +#define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */ +/** + * @} + */ +#endif /* HRTIM1 */ + +/** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI +#define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE +#define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range + * @{ + */ +#define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U) +#define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001) +#define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002) +#define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range + * @{ + */ +#define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */ +#define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */ +/** + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the SYSCLK frequency + * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P) + * @param __SYSPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval SYSCLK clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_D1CPRE) +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_D1CPRE */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency. + * @param __HPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_HPRE) +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_HPRE */ + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D2CFGR_D2PPRE1) +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)) +#endif /* RCC_D2CFGR_D2PPRE1 */ + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#if defined(RCC_D2CFGR_D2PPRE2) +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)) +#endif /* RCC_D2CFGR_D2PPRE2 */ + +/** + * @brief Helper macro to calculate the PCLK3 frequency (APB3) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB3PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_D1PPRE) +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_D1PPRE */ + +/** + * @brief Helper macro to calculate the PCLK4 frequency (ABP4) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB4PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D3CFGR_D3PPRE) +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU)) +#endif /* RCC_D3CFGR_D3PPRE */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless + * a reset occurs or system enter in standby mode. + * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSHSEON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +#if defined(RCC_CR_HSEEXT) +/** + * @brief Select the Analog HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +} + +/** + * @brief Select the Digital HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); +} +#endif /* RCC_CR_HSEEXT */ + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI new divider applied and ready + * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV1 + * @arg @ref LL_RCC_HSI_DIV2 + * @arg @ref LL_RCC_HSI_DIV4 + * @arg @ref LL_RCC_HSI_DIV8 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); +} + +/** + * @brief Get HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV1 + * @arg @ref LL_RCC_HSI_DIV2 + * @arg @ref LL_RCC_HSI_DIV4 + * @arg @ref LL_RCC_HSI_DIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} + +/** + * @brief Enable HSI oscillator in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI oscillator in Stop mode + * @rmtoll CR HSION LL_RCC_HSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration + * @retval A value between 0 and 4095 (0xFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value, + * should trim the HSI to 64 MHz +/- 1 % + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value can be a value between 0 and 127 (63 for Cut1.x) + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U); + } + else + { + /* STM32H7 Rev.V */ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); + } +#else + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval A value between 0 and 127 (63 for Cut1.x) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_CSI CSI + * @{ + */ + +/** + * @brief Enable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Disable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Check if CSI clock is ready + * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Disable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Get CSI Calibration value + * @note When CSITRIM is written, CSICAL is updated with the sum of + * CSITRIM and the factory trim value + * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration + * @retval A value between 0 and 255 (0xFF) + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Set CSI Calibration trimming + * @note user-programmable trimming value that is added to the CSICAL + * @note Default value is 16, which, when added to the CSICAL value, + * should trim the CSI to 4 MHz +/- 1 % + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming + * @param Value can be a value between 0 and 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U); + } + else + { + /* STM32H7 Rev.V */ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); + } +#else + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Get CSI Calibration trimming + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming + * @retval A value between 0 and 31 + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 clock is ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of + * HSI48TRIM and the factory trim value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval A value between 0 and 1023 (0x3FF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} +/** + * @} + */ + +#if defined(RCC_CR_D1CKRDY) + +/** @defgroup RCC_LL_EF_D1CLK D1CKREADY + * @{ + */ + +/** + * @brief Check if D1 clock is ready + * @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ +#else + +/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY + * @{ + */ + +/** + * @brief Check if CPU clock is ready + * @rmtoll CR CPUCKRDY LL_RCC_CPUCK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL); +} +/* alias */ +#define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady +/** + * @} + */ +#endif /* RCC_CR_D1CKRDY */ + +#if defined(RCC_CR_D2CKRDY) + +/** @defgroup RCC_LL_EF_D2CLK D2CKREADY + * @{ + */ + +/** + * @brief Check if D2 clock is ready + * @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL); +} +/** + * @} + */ +#else + +/** @defgroup RCC_LL_EF_CDCLK CDCKREADY + * @{ + */ + +/** + * @brief Check if CD clock is ready + * @rmtoll CR CDCKRDY LL_RCC_CDCK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL); +} +#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady +/** + * @} + */ +#endif /* RCC_CR_D2CKRDY */ + +/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET + * @{ + */ +#if defined(RCC_GCR_WW1RSC) + +/** + * @brief Enable system wide reset for Window Watch Dog 1 + * @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset + * @retval None. + */ +__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_WW1RSC); +} + +/** + * @brief Check if Window Watch Dog 1 reset is system wide + * @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL); +} +#endif /* RCC_GCR_WW1RSC */ + +#if defined(DUAL_CORE) +/** + * @brief Enable system wide reset for Window Watch Dog 2 + * @rmtoll GCR WW1RSC LL_RCC_WWDG2_EnableSystemReset + * @retval None. + */ +__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_WW2RSC); +} + +/** + * @brief Check if Window Watch Dog 2 reset is system wide + * @rmtoll GCR WW2RSC LL_RCC_WWDG2_IsSystemReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup RCC_LL_EF_BOOT_CPU CPU + * @{ + */ + +/** + * @brief Force CM4 boot (if hold by option byte BCM4 = 0) + * @rmtoll GCR BOOT_C2 LL_RCC_ForceCM4Boot + * @retval None. + */ +__STATIC_INLINE void LL_RCC_ForceCM4Boot(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2); +} + +/** + * @brief Check if CM4 boot is forced + * @rmtoll GCR BOOT_C2 LL_RCC_IsCM4BootForced + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL); +} + +/** + * @brief Force CM7 boot (if hold by option byte BCM7 = 0) + * @rmtoll GCR BOOT_C1 LL_RCC_ForceCM7Boot + * @retval None. + */ +__STATIC_INLINE void LL_RCC_ForceCM7Boot(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1); +} + +/** + * @brief Check if CM7 boot is forced + * @rmtoll GCR BOOT_C1 LL_RCC_IsCM7BootForced + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /*DUAL_CORE*/ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable the Clock Security System on LSE. + * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless + * a clock failure is detected. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE failure is detected by Clock Security System + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +#if defined(RCC_BDCR_LSEEXT) +/** + * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} + +/** + * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} +#endif /* RCC_BDCR_LSEEXT */ + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Configure the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source); +} + +/** + * @brief Get the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +} + +/** + * @brief Configure the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source); +} + +/** + * @brief Get the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK)); +} + +/** + * @brief Set System prescaler + * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_D1CPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler); +#endif /* RCC_D1CFGR_D1CPRE */ +} + +/** + * @brief Set AHB prescaler + * @rmtoll D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_HPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler); +#endif /* RCC_D1CFGR_HPRE */ +} + +/** + * @brief Set APB1 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D2CFGR_D2PPRE1) + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler); +#endif /* RCC_D2CFGR_D2PPRE1 */ +} + +/** + * @brief Set APB2 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D2CFGR_D2PPRE2) + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler); +#endif /* RCC_D2CFGR_D2PPRE2 */ +} + +/** + * @brief Set APB3 prescaler + * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_D1PPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler); +#endif /* RCC_D1CFGR_D1PPRE */ +} + +/** + * @brief Set APB4 prescaler + * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D3CFGR_D3PPRE) + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler); +#else + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler); +#endif /* RCC_D3CFGR_D3PPRE */ +} + +/** + * @brief Get System prescaler + * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void) +{ +#if defined(RCC_D1CFGR_D1CPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE)); +#endif /* RCC_D1CFGR_D1CPRE */ +} + +/** + * @brief Get AHB prescaler + * @rmtoll D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ +#if defined(RCC_D1CFGR_HPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE)); +#endif /* RCC_D1CFGR_HPRE */ +} + +/** + * @brief Get APB1 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ +#if defined(RCC_D2CFGR_D2PPRE1) + return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1)); +#endif /* RCC_D2CFGR_D2PPRE1 */ +} + +/** + * @brief Get APB2 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ +#if defined(RCC_D2CFGR_D2PPRE2) + return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2)); +#endif /* RCC_D2CFGR_D2PPRE2 */ +} + +/** + * @brief Get APB3 prescaler + * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) +{ +#if defined(RCC_D1CFGR_D1PPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE)); +#endif /* RCC_D1CFGR_D1PPRE */ +} + +/** + * @brief Get APB4 prescaler + * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void) +{ +#if defined(RCC_D3CFGR_D3PPRE) + return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE)); +#endif /* RCC_D3CFGR_D3PPRE */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK + * @arg @ref LL_RCC_MCO2SOURCE_CSI + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO1_DIV_6 + * @arg @ref LL_RCC_MCO1_DIV_7 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_9 + * @arg @ref LL_RCC_MCO1_DIV_10 + * @arg @ref LL_RCC_MCO1_DIV_11 + * @arg @ref LL_RCC_MCO1_DIV_12 + * @arg @ref LL_RCC_MCO1_DIV_13 + * @arg @ref LL_RCC_MCO1_DIV_14 + * @arg @ref LL_RCC_MCO1_DIV_15 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_6 + * @arg @ref LL_RCC_MCO2_DIV_7 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_9 + * @arg @ref LL_RCC_MCO2_DIV_10 + * @arg @ref LL_RCC_MCO2_DIV_11 + * @arg @ref LL_RCC_MCO2_DIV_12 + * @arg @ref LL_RCC_MCO2_DIV_13 + * @arg @ref LL_RCC_MCO2_DIV_14 + * @arg @ref LL_RCC_MCO2_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure periph clock source + * @rmtoll D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource\n + * D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource\n + * D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource)); +#else + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource)); +#endif /* */ + MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); +} + +/** + * @brief Configure USARTx clock source + * @rmtoll D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n + * D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D3CCIPR_LPUART1SEL) + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource); +#else + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource); +#endif /* RCC_D3CCIPR_LPUART1SEL */ +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n + * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource + * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n + * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource + * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n + * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SDMMCx clock source + * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_SDMMCSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource); +#endif /* RCC_D1CCIPR_SDMMCSEL */ +} + +/** + * @brief Configure RNGx clock source + * @rmtoll D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_RNGSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource); +#endif /* RCC_D2CCIP2R_RNGSEL */ +} + +/** + * @brief Configure USBx clock source + * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_USBSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource); +#endif /* RCC_D2CCIP2R_USBSEL */ +} + +/** + * @brief Configure CECx clock source + * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_CECSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource); +#endif /* RCC_D2CCIP2R_CECSEL */ +} + +#if defined(DSI) +/** + * @brief Configure DSIx clock source + * @rmtoll D1CCIPR DSISEL LL_RCC_SetDSIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource); +} +#endif /* DSI */ + +/** + * @brief Configure DFSDMx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource); +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +} + +#if defined(DFSDM2_BASE) +/** + * @brief Configure DFSDMx Kernel clock source + * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource); +} +#endif /* DFSDM2_BASE */ + +/** + * @brief Configure FMCx Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource); +#endif /* RCC_D1CCIPR_FMCSEL */ +} + +#if defined(QUADSPI) +/** + * @brief Configure QSPIx Kernel clock source + * @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource); +} +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** + * @brief Configure OSPIx Kernel clock source + * @rmtoll D1CCIPR OPISEL LL_RCC_SetOSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_OCTOSPISEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource); +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +} +#endif /* OCTOSPI1 || OCTOSPI2 */ + +/** + * @brief Configure CLKP Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_CKPERSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource); +#endif /* RCC_D1CCIPR_CKPERSEL */ +} + +/** + * @brief Configure SPIx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n + * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n + * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SPDIFx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_SPDIFSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource); +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +} + +/** + * @brief Configure FDCANx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_FDCANSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource); +#endif /* RCC_D2CCIP1R_FDCANSEL */ +} + +/** + * @brief Configure SWPx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_SWPSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource); +#endif /* RCC_D2CCIP1R_SWPSEL */ +} + +/** + * @brief Configure ADCx Kernel clock source + * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D3CCIPR_ADCSEL) + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource); +#else + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource); +#endif /* RCC_D3CCIPR_ADCSEL */ +} + +/** + * @brief Get periph clock source + * @rmtoll D1CCIPR / CDCCIPR * LL_RCC_GetClockSource\n + * D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource\n + * D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource\n + * D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @arg @ref LL_RCC_I2C123_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI23_CLKSOURCE + * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI45_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph))); +#else + const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph))); +#endif /* RCC_D1CCIPR_FMCSEL */ + return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT)); +} + +/** + * @brief Get USARTx clock source + * @rmtoll D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n + * D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPUART clock source + * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D3CCIPR_LPUART1SEL) + return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)); +#endif /* RCC_D3CCIPR_LPUART1SEL */ +} + +/** + * @brief Get I2Cx clock source + * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n + * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPTIM clock source + * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SAIx clock source + * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n + * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource + * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n + * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SDMMC clock source + * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_SDMMCSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)); +#endif /* RCC_D1CCIPR_SDMMCSEL */ +} + +/** + * @brief Get RNG clock source + * @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_RNGSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)); +#endif /* RCC_D2CCIP2R_RNGSEL */ +} + +/** + * @brief Get USB clock source + * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_USBSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)); +#endif /* RCC_D2CCIP2R_USBSEL */ +} + +/** + * @brief Get CEC clock source + * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_CECSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)); +#endif /* RCC_D2CCIP2R_CECSEL */ +} + +#if defined(DSI) +/** + * @brief Get DSI clock source + * @rmtoll D1CCIPR DSISEL LL_RCC_GetDSIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)); +} +#endif /* DSI */ + +/** + * @brief Get DFSDM Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_DFSDM1SEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)); +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +} + +#if defined(DFSDM2_BASE) +/** + * @brief Get DFSDM2 Kernel clock source + * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)); +} +#endif /* DFSDM2_BASE */ + +/** + * @brief Get FMC Kernel clock source + * @rmtoll D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_FMCSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)); +#endif /* RCC_D1CCIPR_FMCSEL */ +} + +#if defined(QUADSPI) +/** + * @brief Get QSPI Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)); +} +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** + * @brief Get OSPI Kernel clock source + * @rmtoll CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_OCTOSPISEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)); +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +} +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + +/** + * @brief Get CLKP Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_CKPERSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)); +#endif /* RCC_D1CCIPR_CKPERSEL */ +} + +/** + * @brief Get SPIx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n + * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n + * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE + * @arg @ref LL_RCC_SPI45_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all stm32h7xx lines. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SPDIF Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_SPDIFSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)); +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +} + +/** + * @brief Get FDCAN Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_FDCANSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)); +#endif /* RCC_D2CCIP1R_FDCANSEL */ +} + +/** + * @brief Get SWP Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_SWPSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)); +#endif /* RCC_D2CCIP1R_SWPSEL */ +} + +/** + * @brief Get ADC Kernel clock source + * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined (RCC_D3CCIPR_ADCSEL) + return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)); +#endif /* RCC_D3CCIPR_ADCSEL */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ +#if defined(RCC_BDCR_BDRST) + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +#else + CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +#endif /* RCC_BDCR_BDRST */ +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE)); +} + +/** + * @} + */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM + * @{ + */ + +/** + * @brief Set High Resolution Timers Clock Source + * @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler); +} +#endif /* HRTIM1 */ + +#if defined(HRTIM1) +/** + * @brief Get High Resolution Timers Clock Source + * @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU + */ +__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)); +} +/** + * @} + */ +#endif /* HRTIM1 */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLLSRC can be written only when All PLLs are disabled. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC)); +} + +/** + * @brief Enable PLL1 + * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Check if PLL1 Ready + * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); +} + +/** + * @brief Enable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); +} + +/** + * @brief Enable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); +} + +/** + * @brief Enable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Check if PLL1 P is enabled + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 Q is enabled + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 R is enabled + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 FRACN is enabled + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); +} + +/** + * @brief Disable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); +} + +/** + * @brief Disable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); +} + +/** + * @brief Disable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Set PLL1 VCO OutputRange + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos); +} + +/** + * @brief Set PLL1 VCO Input Range + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos); +} + +/** + * @brief Get PLL1 N Coefficient + * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 M Coefficient + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Get PLL1 P Coefficient + * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP + * @retval A value between 2 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 Q Coefficient + * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 R Coefficient + * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); +} + +/** + * @brief Set PLL1 N Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos); +} + +/** + * @brief Set PLL1 M Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Set PLL1 P Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP + * @param P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines. + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos); +} + +/** + * @brief Set PLL1 Q Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos); +} + +/** + * @brief Set PLL1 R Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos); +} + +/** + * @brief Set PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos); +} + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @note Cannot be disabled if the PLL2 clock is used as the system clock + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); +} + +/** + * @brief Enable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); +} + +/** + * @brief Enable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); +} + +/** + * @brief Enable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Check if PLL2 P is enabled + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 Q is enabled + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 R is enabled + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 FRACN is enabled + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); +} + +/** + * @brief Disable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); +} + +/** + * @brief Disable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); +} + +/** + * @brief Disable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Set PLL2 VCO OutputRange + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos); +} + +/** + * @brief Set PLL2 VCO Input Range + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos); +} + +/** + * @brief Get PLL2 N Coefficient + * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 M Coefficient + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Get PLL2 P Coefficient + * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 Q Coefficient + * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 R Coefficient + * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos); +} + +/** + * @brief Set PLL2 N Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos); +} + +/** + * @brief Set PLL2 M Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Set PLL2 P Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos); +} + +/** + * @brief Set PLL2 Q Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos); +} + +/** + * @brief Set PLL2 R Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos); +} + +/** + * @brief Set PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos); +} + +/** + * @brief Enable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLL3 + * @note Cannot be disabled if the PLL3 clock is used as the system clock + * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLL3 Ready + * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); +} + +/** + * @brief Enable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); +} + +/** + * @brief Enable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); +} + +/** + * @brief Enable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Check if PLL3 P is enabled + * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 Q is enabled + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 R is enabled + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 FRACN is enabled + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); +} + +/** + * @brief Disable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); +} + +/** + * @brief Disable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); +} + +/** + * @brief Disable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Set PLL3 VCO OutputRange + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos); +} + +/** + * @brief Set PLL3 VCO Input Range + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos); +} + +/** + * @brief Get PLL3 N Coefficient + * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 M Coefficient + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Get PLL3 P Coefficient + * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 Q Coefficient + * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 R Coefficient + * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos); +} + +/** + * @brief Set PLL3 N Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos); +} + +/** + * @brief Set PLL3 M Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Set PLL3 P Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos); +} + +/** + * @brief Set PLL3 Q Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos); +} + +/** + * @brief Set PLL3 R Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos); +} + +/** + * @brief Set PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos); +} + + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear CSI ready interrupt flag + * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC); +} + +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); +} + +/** + * @brief Clear PLL3 ready interrupt flag + * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Clear HSE Clock security system interrupt flag + * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSI ready interrupt occurred or not + * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 ready interrupt occurred or not + * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE Clock security system interrupt occurred or not + * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n + * RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL); +#endif /*DUAL_CORE*/ +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n + * RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL); +#endif /*DUAL_CORE*/ +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +#if defined(RCC_RSR_D1RSTF) +/** + * @brief Check if RCC flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_D1RSTF */ + +#if defined(RCC_RSR_CDRSTF) +/** + * @brief Check if RCC flag CD reset is set or not. + * @rmtoll RSR CDRSTF LL_RCC_IsActiveFlag_CDRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_CDRSTF */ + +#if defined(RCC_RSR_D2RSTF) +/** + * @brief Check if RCC flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_D2RSTF */ + +#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) +/** + * @brief Check if RCC flag CPU reset is set or not. + * @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n + * RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL); +#endif/*DUAL_CORE*/ +} +#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */ + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Set RMVF bit to clear all reset flags. + * @rmtoll RSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC_C1 flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWR1RSTF LL_C1_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_C1_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_C1_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_C1_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_C1_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_C1_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Software reset is set or not. + * @rmtoll RSR SFT1RSTF LL_C1_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_C1_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_C1_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_C1_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_C1_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_C1_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_C1_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag CPU reset is set or not. + * @rmtoll RSR C1RSTF LL_C1_RCC_IsActiveFlag_CPURST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_C1_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll RSR RMVF LL_C1_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF); +} + +/** + * @brief Check if RCC_C2 flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWR1RSTF LL_C2_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_C2_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_C2_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_C2_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_C2_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_C2_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Software reset is set or not. + * @rmtoll RSR SFT1RSTF LL_C2_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_C2_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_C2_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_C2_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_C2_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_C2_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_C2_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag CPU reset is set or not. + * @rmtoll RSR C1RSTF LL_C2_RCC_IsActiveFlag_CPURST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_C2_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll RSR RMVF LL_C2_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF); +} +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Enable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Enable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Disable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Disable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if CSI ready interrupt source is enabled or disabled. + * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL3 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +void LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR); + +void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); + +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +#if defined(DFSDM2_BASE) +uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource); +#endif /* DFSDM2_BASE */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource); +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource); +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource); +#if defined(QUADSPI) +uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) +uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource); +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + + +/** + * @} + */ +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_RCC_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h new file mode 100644 index 0000000..aa5149a --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h @@ -0,0 +1,2442 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_LL_SYSTEM_H +#define __STM32H7xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ +/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status + * @{ + */ +#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U +#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U +#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U +#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U +#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U +#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U +#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U +#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status + * @{ + */ +#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U +#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U +#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U +#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U +#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U +#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U +#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U +#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ +#if defined(I2C5) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */ +#endif /*I2C5*/ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control +* @{ +*/ +#if defined(SYSCFG_PMCR_BOOSTEN) +#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */ +#endif /*SYSCFG_PMCR_BOOSTEN*/ +#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */ +/** + * @} + */ + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection +* @{ +*/ +#define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */ +#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */ +/** + * @} + */ +#endif /* SYSCFG_PMCR_EPIS_SEL */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ +#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ +#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ +#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ +#endif /*GPIOI*/ +#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ +#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#if defined(SYSCFG_CFGR_SRAM3L) +#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ +#endif /*SYSCFG_CFGR_SRAM3L*/ + +#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection + with TIM1/8/15/16/17 and HRTIM Break Input + and also the PVDE and PLS bits of the Power Control Interface */ +#if defined(DUAL_CORE) +#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_CELL_CODE 0U +#define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS +/** + * @} + */ + +/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes + * @{ + */ +#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U +#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M +/** + * @} + */ + +#if defined (DUAL_CORE) +/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes + * @{ + */ +#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U +#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration + * @{ + */ +#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U +#define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U +#define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U +#define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U +/** + * @} + */ +#ifdef SYSCFG_UR17_TCM_AXI_CFG +/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package + * @{ + */ +#define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U +#define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U +#define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U +#define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U +/** + * @} + */ +#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */ +#if defined(SYSCFG_PKGR_PKG) +/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package + * @{ + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define LL_SYSCFG_LQFP100_PACKAGE 0U +#define LL_SYSCFG_TQFP144_PACKAGE 2U +#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U +#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U +#elif (STM32H7_DEV_ID == 0x483UL) +#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U +#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U +#define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U +#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U +#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U +#define LL_SYSCFG_LQFP144_PACKAGE 5U +#define LL_SYSCFG_UFBGA144_PACKAGE 6U +#define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U +#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U +#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U +#define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U +#endif /* STM32H7_DEV_ID == 0x450UL */ +/** + * @} + */ +#endif /* SYSCFG_PKGR_PKG */ + +/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level + * @{ + */ +#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U +#define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0 +#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1 +#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#if defined(I2C5) +#define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */ +#endif /*I2C5*/ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */ +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ +#if defined(TIM23) +#define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */ +#endif /*TIM23*/ +#if defined(TIM24) +#define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */ +#endif /*TIM24*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */ +#if defined(HRTIM1) +#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */ +#endif /*HRTIM1*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** + * @brief Select Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ETH_MII + * @arg @ref LL_SYSCFG_ETH_RMII + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ETH_MII + * @arg @ref LL_SYSCFG_ETH_RMII + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL)); +} + +#endif /* SYSCFG_PMCR_EPIS_SEL */ +/** + * @brief Open an Analog Switch + * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch + * @param AnalogSwitch This parameter can be one of the following values: + * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch) +{ + SET_BIT(SYSCFG->PMCR, AnalogSwitch); +} + +/** + * @brief Close an Analog Switch + * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch + * @param AnalogSwitch This parameter can be one of the following values: + * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch) +{ + CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch); +} +#ifdef SYSCFG_PMCR_BOOSTEN +/** + * @brief Enable the Analog booster to reduce the total harmonic distortion + * of the analog switch when the supply voltage is lower than 2.7 V + * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) +{ + SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} + +/** + * @brief Disable the Analog booster + * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} +#endif /*SYSCFG_PMCR_BOOSTEN*/ +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->PMCR, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U)); +} + +/** + * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs + * @note this feature is available on STM32H7 rev.B and above + * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) + * @retval None + * (*) value not defined in all devices + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break); +#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL, Break); +#elif defined(SYSCFG_CFGR_AXISRAML) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\ + Break); +#else + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\ + SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL, Break); +#endif /* DUAL_CORE */ +} + +/** + * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs + * @note this feature is available on STM32H7 rev.B and above + * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ +#if defined(DUAL_CORE) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L)); +#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#elif defined (SYSCFG_CFGR_AXISRAML) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#else + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#endif /* DUAL_CORE */ +} + +/** + * @brief Enable the Compensation Cell + * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + +/** + * @brief Disable the Compensation Cell + * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + +/** + * @brief Check if the Compensation Cell is enabled + * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag + * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL); +#endif /*SYSCFG_CCCSR_HSLV*/ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL); +} + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL); +} + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + +/** + * @brief Set the code selection for the I/O Compensation cell + * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode + * @param CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} + +/** + * @brief Get the code selected for the I/O Compensation cell + * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS)); +} + +#ifdef SYSCFG_CCCSR_CS_MMC + +/** + * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail + * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC)); +} +#endif /*SYSCFG_CCCSR_CS_MMC*/ + +/** + * @brief Get I/O compensation cell value for PMOS transistors + * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue + * @retval Returned value is the I/O compensation cell value for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV)); +} + +/** + * @brief Get I/O compensation cell value for NMOS transistors + * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue + * @retval Returned value is the I/O compensation cell value for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV)); +} + +/** + * @brief Set I/O compensation cell code for PMOS transistors + * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode); +} + +/** + * @brief Get I/O compensation cell code for PMOS transistors + * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC)); +} + +#ifdef SYSCFG_CCCR_PCC_MMC + +/** + * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail + * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode); +} + +/** + * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail + * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC)); +} +#endif /* SYSCFG_CCCR_PCC_MMC */ + +/** + * @brief Set I/O compensation cell code for NMOS transistors + * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode); +} + +/** + * @brief Get I/O compensation cell code for NMOS transistors + * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC)); +} + +#ifdef SYSCFG_CCCR_NCC_MMC + +/** + * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail. + * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode + * @param NMOSCode: NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode); +} + +/** + * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail. + * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC)); +} +#endif /*SYSCFG_CCCR_NCC_MMC*/ + +#ifdef SYSCFG_PKGR_PKG +/** + * @brief Get the device package + * @rmtoll PKGR PKG LL_SYSCFG_GetPackage + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*) + * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*) + * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*) + * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*) + * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*) + * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*) + * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**) + * + * (*) : For stm32h74xxx and stm32h75xxx family lines. + * (**): For stm32h72xxx and stm32h73xxx family lines. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG)); +} +#endif /*SYSCFG_PKGR_PKG*/ + +#ifdef SYSCFG_UR0_RDP +/** + * @brief Get the Flash memory protection level + * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel + * @retval Returned value can be one of the following values: + * 0xAA : RDP level 0 + * 0xCC : RDP level 2 + * Any other value : RDP level 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP)); +} +#ifdef SYSCFG_UR0_BKS +/** + * @brief Indicate if the Flash memory bank addresses are inverted or not + * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void) +{ + return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR0_BKS*/ + +/** + * @brief Get the BOR Threshold Reset Level + * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH)); +} +/** + * @brief BootCM7 address 0 configuration + * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress) +{ + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos)); +#else + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos)); +#endif /*DUAL_CORE*/ + +} + +/** + * @brief Get BootCM7 address 0 + * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0 + * @retval Returned the CM7 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void) +{ + /* Get CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos); +#else + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos); +#endif /*DUAL_CORE*/ +} + +/** + * @brief BootCM7 address 1 configuration + * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress) +{ + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress); +#else + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress); +#endif /*DUAL_CORE*/ +} + +/** + * @brief Get BootCM7 address 1 + * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1 + * @retval Returned the CM7 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void) +{ + /* Get CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1)); +#else + return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1)); +#endif /* DUAL_CORE */ +} + +#if defined(DUAL_CORE) +/** + * @brief BootCM4 address 0 configuration + * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress) +{ + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos)); +} + +/** + * @brief Get BootCM4 address 0 + * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0 + * @retval Returned the CM4 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void) +{ + /* Get CM4 BOOT ADD0 */ + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos); +} + +/** + * @brief BootCM4 address 1 configuration + * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress) +{ + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress); +} + +/** + * @brief Get BootCM4 address 1 + * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1 + * @retval Returned the CM4 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void) +{ + /* Get CM4 BOOT ADD0 */ + return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1)); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase + * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase + * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Get the protected area start address for Flash bank 1 + * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress + * @retval Returned the protected area start address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1)); +} + +/** + * @brief Get the protected area end address for Flash bank 1 + * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress + * @retval Returned the protected area end address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1)); +} + +/** + * @brief Get the secured area start address for Flash bank 1 + * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress + * @retval Returned the secured area start address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1)); +} + +/** + * @brief Get the secured area end address for Flash bank 1 + * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress + * @retval Returned the secured area end address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1)); +} + +#ifdef SYSCFG_UR8_MEPAD_BANK2 +/** + * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase + * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase + * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR8_MEPAD_BANK2*/ + +#ifdef SYSCFG_UR9_WRPN_BANK2 +/** + * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Get the protected area start address for Flash bank 2 + * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress + * @retval Returned the protected area start address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2)); +} +#endif /*SYSCFG_UR9_WRPN_BANK2*/ + +#ifdef SYSCFG_UR10_PAEND_BANK2 +/** + * @brief Get the protected area end address for Flash bank 2 + * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress + * @retval Returned the protected area end address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2)); +} + +/** + * @brief Get the secured area start address for Flash bank 2 + * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress + * @retval Returned the secured area start address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2)); +} +#endif /*SYSCFG_UR10_PAEND_BANK2*/ + +#ifdef SYSCFG_UR11_SAEND_BANK2 +/** + * @brief Get the secured area end address for Flash bank 2 + * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress + * @retval Returned the secured area end address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2)); +} +#endif /*SYSCFG_UR11_SAEND_BANK2*/ + +/** + * @brief Get the Independent Watchdog 1 control mode (Software or Hardware) + * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE + * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M)); +} + +#if defined (DUAL_CORE) +/** + * @brief Get the Independent Watchdog 2 control mode (Software or Hardware) + * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE + * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M)); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicates the Secure mode status + * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void) +{ + return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL); +} + +/** + * @brief Indicates if a reset is generated when D1 domain enters DStandby mode + * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Get the secured DTCM RAM size + * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS)); +} + +/** + * @brief Indicates if a reset is generated when D1 domain enters DStop mode + * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Indicates if a reset is generated when D2 domain enters DStandby mode + * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if a reset is generated when D2 domain enters DStop mode + * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicates if the independent watchdog is frozen in Standby mode + * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void) +{ + return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the independent watchdog is frozen in Stop mode + * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void) +{ + return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the device private key is programmed + * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void) +{ + return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the Product is working on the full voltage range or not + * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV + * @note When the IOHSLV option bit is set the Product is working below 2.7 V. + * When the IOHSLV option bit is reset the Product is working on the + * full voltage range. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void) +{ + return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL); +} + +#ifdef SYSCFG_UR17_TCM_AXI_CFG +/** + * @brief Get the size of ITCM-RAM and AXI-SRAM + * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB + * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB + * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB + * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB + */ +__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG)); +} +#endif /*SYSCFG_UR17_TCM_AXI_CFG*/ + +#ifdef SYSCFG_UR18_CPU_FREQ_BOOST +/** + * @brief Indicates if the CPU maximum frequency boost is enabled + * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void) +{ + return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/ + +#endif /*SYSCFG_UR0_RDP*/ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable D1 Domain/CDomain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Enable D1 Domain/CDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Enable D1 Domain/CDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +#if defined (DUAL_CORE) +/** + * @brief Enable D2 Domain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Disable D2 Domain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Enable D2 Domain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Disable D2 Domain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Enable D2 Domain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} + +/** + * @brief Disable D2 Domain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} +#endif /* DUAL_CORE */ + + +#if defined(DBGMCU_CR_DBG_STOPD3) +/** + * @brief Enable D3 Domain/SRDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} + +/** + * @brief Disable D3 Domain/SRDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} +#endif /*DBGMCU_CR_DBG_STOPD3*/ + +#if defined(DBGMCU_CR_DBG_STANDBYD3) +/** + * @brief Enable D3 Domain/SRDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} + +/** + * @brief Disable D3 Domain/SRDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ + +/** + * @brief Enable the trace port clock + * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); +} + +/** + * @brief Disable the trace port clock + * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); +} + +/** + * @brief Enable the Domain1/CDomain debug clock enable + * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); +} + +/** + * @brief Disable the Domain1/CDomain debug clock enable + * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); +} + +/** + * @brief Enable the Domain3/SRDomain debug clock enable + * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); +} + +/** + * @brief Disable the Domain3/SRDomain debug clock enable + * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); +} + +#define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U +#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN +/** + * @brief Set the direction of the bi-directional trigger pin TRGIO + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n + * @param PinDirection This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION + * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection); +} + +/** + * @brief Get the direction of the bi-directional trigger pin TRGIO + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION + * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN)); +} + +/** + * @brief Freeze APB1 group1 peripherals + * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN +/** + * @brief Freeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) || defined(TIM24) +/** + * @brief Freeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} +#endif /* TIM23 || TIM24 */ + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph + * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph + * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Freeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB3FZ1, Periphs); +} + +/** + * @brief Unfreeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB3FZ1, Periphs); +} + +/** + * @brief Freeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB4FZ1, Periphs); +} + +/** + * @brief Unfreeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB4FZ1, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EF_ART ART + * @{ + */ + +/** + * @brief Enable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Enable + * @retval None + */ +__STATIC_INLINE void LL_ART_Enable(void) +{ + SET_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Disable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Disable + * @retval None + */ +__STATIC_INLINE void LL_ART_Disable(void) +{ + CLEAR_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Check if the Cortex-M4 ART cache is enabled + * @rmtoll ART_CTR EN LL_ART_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ART_IsEnabled(void) +{ + return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL); +} + +/** + * @brief Set the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress + * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache. + * @retval None + */ +__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress) +{ + MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL)); +} + +/** + * @brief Get the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress + * @retval the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache + */ +__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void) +{ + return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_SYSTEM_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h new file mode 100644 index 0000000..635ea59 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h @@ -0,0 +1,401 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_UTILS_H +#define STM32H7xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_system.h" +#include "stm32h7xx_ll_bus.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetM(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetN(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetP(). */ + + uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO. + This parameter can be a value between 0 and 8191 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetFRACN(). */ + + uint32_t VCO_Input; /*!< PLL clock Input range. + This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOInputRange(). */ + + uint32_t VCO_Output; /*!< PLL clock Output range. + This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOOutputRange(). */ + +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output. + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetSysPrescaler(). */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_AHB_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB3CLKDivider; /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB3_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB3Prescaler(). */ + + uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB4_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB4Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE /*!< TQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL /*!< TFBGA100 or LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL /*!< LQFP100 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL /*!< TFBGA100 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL /*!< WLCSP132 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */ +#elif (STM32H7_DEV_ID == 0x483UL) +#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE /*!< VFQFPN68 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE /*!< TFBGA100 or LQFP100 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE /*!< LQFP100 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE /*!< TFBGA100 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE /*!< WLCSP115 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE /*!< LQFP144 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE /*!< UFBGA144 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE /*!< LQFP144 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE /*!< UFBGA169 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE /*!< UFBGA176+25 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE /*!< LQFP176 Industrial package type */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP144 + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS (*) + * + * (*) Packages available on some STM32H7 lines only. + * @note For some SM32H7 lines, enabling the SYSCFG clock is mandatory. + the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ +#if defined(SYSCFG_PKGR_PKG) + + return LL_SYSCFG_GetPackage(); +#else + return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS))); + +#endif /* SYSCFG_PKGR_PKG */ +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t CPU_Frequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t CPU_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, + uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_UTILS_H */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt b/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c new file mode 100644 index 0000000..cd71d08 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -0,0 +1,1311 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** + * @brief STM32H7xx HAL Driver version number V1.11.1 + */ +#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ +#define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */ +#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ + |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32H7xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + +uint32_t common_system_clock; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure Cortex-M4 Instruction cache through ART accelerator */ + __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */ + __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ + __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB4_FORCE_RESET(); + __HAL_RCC_AHB4_RELEASE_RESET(); + + __HAL_RCC_APB3_FORCE_RESET(); + __HAL_RCC_APB3_RELEASE_RESET(); + + __HAL_RCC_APB1L_FORCE_RESET(); + __HAL_RCC_APB1L_RELEASE_RESET(); + + __HAL_RCC_APB1H_FORCE_RESET(); + __HAL_RCC_APB1H_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB4_FORCE_RESET(); + __HAL_RCC_APB4_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if((uint32_t)uwTickFreq == 0UL) + { + return HAL_ERROR; + } + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup HAL_Group2 + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32H7xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V. + * This requires VDDA equal to or higher than 2.1 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V. + * This requires VDDA equal to or higher than 1.8 V. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode specifies the high impedance mode + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) + { + if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** + * @brief Ethernet PHY Interface Selection either MII or RMII + * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface + * This parameter can be one of the following values: + * @arg SYSCFG_ETH_MII : Select the Media Independent Interface + * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface + * @retval None + */ +void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface)); + + MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); +} +#endif /* SYSCFG_PMCR_EPIS_SEL */ + +/** + * @brief Analog Switch control for dual analog pads. + * @param SYSCFG_AnalogSwitch: Selects the analog pad + * This parameter can be one or a combination of the following values: + * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch + * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch + * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch + * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch + * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C) + * This parameter can be one or a combination of the following values: + * @arg SYSCFG_SWITCH_PA0_OPEN + * @arg SYSCFG_SWITCH_PA0_CLOSE + * @arg SYSCFG_SWITCH_PA1_OPEN + * @arg SYSCFG_SWITCH_PA1_CLOSE + * @arg SYSCFG_SWITCH_PC2_OPEN + * @arg SYSCFG_SWITCH_PC2_CLOSE + * @arg SYSCFG_SWITCH_PC3_OPEN + * @arg SYSCFG_SWITCH_PC3_CLOSE + * @retval None + */ + +void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); + assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); + + MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); +} + +#if defined(SYSCFG_PMCR_BOOSTEN) +/** + * @brief Enables the booster to reduce the total harmonic distortion of the analog + * switch when the supply voltage is lower than 2.7 V. + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +void HAL_SYSCFG_EnableBOOST(void) +{ + SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} + +/** + * @brief Disables the booster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +void HAL_SYSCFG_DisableBOOST(void) +{ + CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} +#endif /* SYSCFG_PMCR_BOOSTEN */ + +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) +/** + * @brief BootCM7 address 0 configuration + * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + * This parameter can be one of the following values: + * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1 + * @retval None + */ +void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + { + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos)); +#else + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos)); +#endif /*DUAL_CORE*/ + } + else + { + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16)); +#else + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16)); +#endif /*DUAL_CORE*/ + } +} +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */ + +#if defined(DUAL_CORE) +/** + * @brief BootCM4 address 0 configuration + * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + * This parameter can be one of the following values: + * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1 + * @retval None + */ +void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + + if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + { + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos)); + } + + else + { + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16)); + } +} + +/** + * @brief Enables the Cortex-M7 boot + * @retval None + */ +void HAL_SYSCFG_EnableCM7BOOT(void) +{ + SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7); +} + +/** + * @brief Disables the Cortex-M7 boot + * @note Disabling the boot will gate the CPU clock + * @retval None + */ +void HAL_SYSCFG_DisableCM7BOOT(void) +{ + CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ; +} + +/** + * @brief Enables the Cortex-M4 boot + * @retval None + */ +void HAL_SYSCFG_EnableCM4BOOT(void) +{ + SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); +} + +/** + * @brief Disables the Cortex-M4 boot + * @note Disabling the boot will gate the CPU clock + * @retval None + */ +void HAL_SYSCFG_DisableCM4BOOT(void) +{ + CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); +} +#endif /*DUAL_CORE*/ +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + + +/** + * @brief To Enable optimize the I/O speed when the product voltage is low. + * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + * higher than 2.5 V might be destructive. + * @retval None + */ +void HAL_SYSCFG_EnableIOSpeedOptimize(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + * higher than 2.5 V might be destructive. + * @retval None + */ +void HAL_SYSCFG_DisableIOSpeedOptimize(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode)); + MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode)); +} + +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_PMOSCode: PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @param SYSCFG_NMOSCode: NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); +} + +#if defined(SYSCFG_CCCR_NCC_MMC) +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); +} +#endif /* SYSCFG_CCCR_NCC_MMC */ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout0 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16] + * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16] + */ +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0); +} +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout1 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17] + * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17] + */ +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1); +} +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ + +/** + * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + + +/** + * @brief Enable the Debug Module during Domain1/CDomain STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable the Debug Module during Domain1 SLEEP mode + * @retval None + */ +void HAL_EnableDomain2DBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Disable the Debug Module during Domain2 SLEEP mode + * @retval None + */ +void HAL_DisableDomain2DBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Enable the Debug Module during Domain2 STOP mode + * @retval None + */ +void HAL_EnableDomain2DBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Disable the Debug Module during Domain2 STOP mode + * @retval None + */ +void HAL_DisableDomain2DBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Enable the Debug Module during Domain2 STANDBY mode + * @retval None + */ +void HAL_EnableDomain2DBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} + +/** + * @brief Disable the Debug Module during Domain2 STANDBY mode + * @retval None + */ +void HAL_DisableDomain2DBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} +#endif /*DUAL_CORE*/ + +#if defined(DBGMCU_CR_DBG_STOPD3) +/** + * @brief Enable the Debug Module during Domain3/SRDomain STOP mode + * @retval None + */ +void HAL_EnableDomain3DBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} + +/** + * @brief Disable the Debug Module during Domain3/SRDomain STOP mode + * @retval None + */ +void HAL_DisableDomain3DBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} +#endif /*DBGMCU_CR_DBG_STOPD3*/ + +#if defined(DBGMCU_CR_DBG_STANDBYD3) +/** + * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode + * @retval None + */ +void HAL_EnableDomain3DBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} + +/** + * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode + * @retval None + */ +void HAL_DisableDomain3DBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ + +/** + * @brief Set the FMC Memory Mapping Swapping config. + * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be + FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 + * @retval HAL state + */ +void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig) +{ + /* Check the parameter */ + assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig)); + MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig); +} + +/** + * @brief Get FMC Bank mapping mode. + * @retval The FMC Bank mapping mode. This parameter can be + FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 +*/ +uint32_t HAL_GetFMCMemorySwappingConfig(void) +{ + return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP); +} + +/** + * @brief Configure the EXTI input event line edge + * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21), + * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86. + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Edge: Specifies EXTI line Edge used. + * This parameter can be one of the following values : + * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection + * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection + * @retval None + */ +void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ) +{ + /* Check the parameter */ + assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge)); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + + if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE) + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE) + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86. + * @retval None + */ +void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); +} + + +/** + * @brief Clears the EXTI's line pending flags for Domain D1 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @retval None + */ +void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + +} + +#if defined(DUAL_CORE) +/** + * @brief Clears the EXTI's line pending flags for Domain D2 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @retval None + */ +void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_D2_LINE(EXTI_Line)); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); +} + +#endif /*DUAL_CORE*/ +/** + * @brief Configure the EXTI input event line for Domain D1 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. + * This parameter can be one or a combination of the following values : + * @arg EXTI_MODE_IT : Interrupt Mode selected + * @arg EXTI_MODE_EVT : Event Mode selected + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + + * @retval None + */ +void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +{ + /* Check the parameter */ + assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); + + if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } + + if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + else + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } +} + +#if defined(DUAL_CORE) +/** + * @brief Configure the EXTI input event line for Domain D2 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. + * This parameter can be one or a combination of the following values : + * @arg EXTI_MODE_IT : Interrupt Mode selected + * @arg EXTI_MODE_EVT : Event Mode selected + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + + * @retval None + */ +void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +{ + /* Check the parameter */ + assert_param(IS_EXTI_D2_LINE(EXTI_Line)); + assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); + + if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } + + if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + else + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } +} +#endif /*DUAL_CORE*/ + +/** + * @brief Configure the EXTI input event line for Domain D3 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34, + * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53) + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event. + * This parameter can be one of the following values : + * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source + * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source + * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source + * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source + * @retval None + */ +void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc ) +{ + __IO uint32_t *pRegv; + + /* Check the parameter */ + assert_param(IS_EXTI_D3_LINE(EXTI_Line)); + assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc)); + + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + + if(((EXTI_Line>>4)%2UL) == 0UL) + { + pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL)); + } + else + { + pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL)); + } + MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL))); + +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c new file mode 100644 index 0000000..05730c1 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined + inside the stm32h7xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enables the MPU + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != 0UL) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval status - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval status - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if defined(DUAL_CORE) + +/** + * @brief Returns the current CPU ID. + * @retval CPU identifier + */ +uint32_t HAL_GetCurrentCPUID(void) +{ + if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U) + { + return CM7_CPUID; + } + else + { + return CM4_CPUID; + } +} + +#else + +/** +* @brief Returns the current CPU ID. +* @retval CPU identifier +*/ +uint32_t HAL_GetCurrentCPUID(void) +{ + return CM7_CPUID; +} + +#endif /*DUAL_CORE*/ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c new file mode 100644 index 0000000..dada223 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -0,0 +1,2062 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/** @addtogroup DMA_Private_Types + * @{ + */ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +typedef struct +{ + __IO uint32_t ISR; /*!< BDMA interrupt status register */ + __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */ +} BDMA_Base_Registers; +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */ + +#define BDMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ +#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction */ + +/* DMA to BDMA conversion */ +#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \ + ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \ + BDMA_PERIPH_TO_MEMORY) + +#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U) +#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U) + +#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U) +#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U) + +#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U) + +#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U) + +#if defined(UART9) +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX ))) +#else +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX ))) + +#endif +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + The HAL_DMA_DeInit function allows to deinitialize the DMA stream. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t registerValue; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Get the CR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + registerValue |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be + lock when transferring data to/from USART/UART */ +#if (STM32H7_DEV_ID == 0x450UL) + if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) + { +#endif /* STM32H7_DEV_ID == 0x450UL */ + if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + { + registerValue |= DMA_SxCR_TRBUFF; + } +#if (STM32H7_DEV_ID == 0x450UL) + } +#endif /* STM32H7_DEV_ID == 0x450UL */ + + /* Write to DMA Stream CR register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; + + /* Get the FCR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + registerValue |= hdma->Init.FIFOMode; + + /* the FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + registerValue |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 */ + if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* Check the request parameter */ + assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Get the CR register value */ + registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ + registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ + BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ + BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ + BDMA_CCR_CT)); + + /* Prepare the DMA Channel configuration */ + registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | + DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + DMA_TO_BDMA_MODE(hdma->Init.Mode) | + DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); + + /* Write to DMA Channel CR register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; + + /* calculation of the channel index */ + hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Initialize parameters for DMAMUX request generator : + if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 + */ + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Reset DMA Streamx control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; + + /* Get DMA steam Base Address */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Reset DMA Channel control register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U; + + /* Reset DMA Channel memory 0 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U; + + /* Reset DMA Channel memory 1 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U; + + /* Get DMA steam Base Address */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + /* Return error status */ + return HAL_ERROR; + } + +#if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */ + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ +#endif /* BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->DMAmuxChannel != 0U) + { + /* Resett he DMAMUX channel that corresponds to the DMA stream */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + } + + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Register and Unregister DMA callbacks + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Enable Half Transfer IT if corresponding Callback is set */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + } + } + else /* BDMA channel */ + { + /* Enable Common interrupts */ + MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /*Enable Half Transfer IT if corresponding Callback is set */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check if DMAMUX Synchronization is enabled */ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + const __IO uint32_t *enableRegister; + + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Disable DMA All Interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while(((*enableRegister) & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel: Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t cpltlevel_mask; + uint32_t tickstart = HAL_GetTick(); + + /* IT status register */ + __IO uint32_t *isr_reg; + /* IT clear flag register */ + __IO uint32_t *ifcr_reg; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Polling mode not supported in circular mode and double buffering mode */ + if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + else /* BDMA channel */ + { + /* Polling mode not supported in circular mode */ + if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + + while(((*isr_reg) & cpltlevel_mask) == 0U) + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + else /* BDMA channel */ + { + if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* if timeout then abort the current transfer */ + /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */ + (void) HAL_DMA_Abort(hdma); + /* + Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check for DMAMUX Request generator (if used) overrun status */ + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + } + } + + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU)); + } + + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/ + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU)); + } + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr_dma, tmpisr_bdma; + uint32_t ccr_reg; + __IO uint32_t count = 0U; + uint32_t timeout = SystemCoreClock / 9600U; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr_dma = regs_dma->ISR; + tmpisr_bdma = regs_bdma->ISR; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) + { + /* Disable the transfer error interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) + { + /* Clear the FIFO error flag */ + regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) + { + /* Clear the direct mode error flag */ + regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Multi_Buffering mode enabled */ + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Clear the transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the transfer complete interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); + + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Change the DMA state to error if DMA disable fails */ + hdma->State = HAL_DMA_STATE_ERROR; + } + else + { + /* Change the DMA state to Ready if DMA disable success */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); + + /* Half Transfer Complete Interrupt management ******************************/ + if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) + { + /* Clear the half transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 1 */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 0 */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) + { + /* Clear the transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for Memory 1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for Memory 0 */ + hdma->XferCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Transfer Error Interrupt management **************************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback: pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval None + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Clear DBM bit */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Configure DMA Channel data length */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); + } + } + else /* BDMA instance(s) */ + { + /* return pointer to ISR and IFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Memory Data size equal to Byte */ + if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + break; + + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + return status; +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number; + uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); + + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } + else + { + /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ + (stream_baseaddress >= ((uint32_t)DMA2_Stream0))) + { + stream_number += 8U; + } + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; + } + else + { + /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + } + + hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c new file mode 100644 index 0000000..a134b4e --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c @@ -0,0 +1,712 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler . + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + -@- Multi (Double) buffer mode is possible with DMA and BDMA instances. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable the Double buffer mode */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + + /* Clear all flags */ + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA instance(s) */ + { + /* Enable the Double buffer mode */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + + /* Clear all flags */ + *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable the Double buffer mode */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + + /* Clear all flags */ + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA instance(s) */ + { + /* Enable the Double buffer mode */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + + /* Clear all flags */ + *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + } + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + /*Enable Half Transfer IT if corresponding Callback is set*/ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + } + } + else /* BDMA instance(s) */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + /*Enable Half Transfer IT if corresponding Callback is set*/ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check if DMAMUX Synchronization is enabled*/ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address: The new address + * @param memory: the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + if(memory == MEMORY0) + { + /* change the memory0 address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address; + } + else + { + /* change the memory1 address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address; + } + } + else /* BDMA instance(s) */ + { + if(memory == MEMORY0) + { + /* change the memory0 address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address; + } + else + { + /* change the memory1 address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address; + } + } + + return HAL_OK; +} + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + uint32_t syncSignalID = 0; + uint32_t syncPolarity = 0; + + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + if(pSyncConfig->SyncEnable == ENABLE) + { + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + } + else + { + assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + } + syncSignalID = pSyncConfig->SyncSignalID; + syncPolarity = pSyncConfig->SyncPolarity; + } + + /*Check if the DMA state is ready */ + if(hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Disable the synchronization and event generation before applying a new config */ + CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE)); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG( hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID) , \ + (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \ + ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + + /* Process Locked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + HAL_StatusTypeDef status; + HAL_DMA_StateTypeDef temp_state = hdma->State; + + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + } + else + { + assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + } + + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if(hdma->DMAmuxRequestGen == 0U) + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* error status */ + status = HAL_ERROR; + } + else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) + { + /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters */ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ + pRequestGeneratorConfig->Polarity; + /* Process Locked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if(hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Configure DMA Stream data length */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + } + } + else /* BDMA instance(s) */ + { + /* Configure DMA Stream data length */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + + /* Configure DMA Stream source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + } + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c new file mode 100644 index 0000000..f1c09d9 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c @@ -0,0 +1,3361 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_eth.c + * @author MCD Application Team + * @brief ETH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Ethernet (ETH) peripheral: + * + Initialization and deinitialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The ETH HAL driver can be used as follows: + + (#)Declare a ETH_HandleTypeDef handle structure, for example: + ETH_HandleTypeDef heth; + + (#)Fill parameters of Init structure in heth handle + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: + (##) Enable the Ethernet interface clock using + (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE() + (+++) __HAL_RCC_ETH1TX_CLK_ENABLE() + (+++) __HAL_RCC_ETH1RX_CLK_ENABLE() + + (##) Initialize the related GPIO clocks + (##) Configure Ethernet pinout + (##) Configure Ethernet NVIC interrupt (in Interrupt mode) + + (#) Ethernet data reception is asynchronous, so call the following API + to start the listening mode: + (##) HAL_ETH_Start(): + This API starts the MAC and DMA transmission and reception process, + without enabling end of transfer interrupts, in this mode user + has to poll for data reception by calling HAL_ETH_ReadData() + (##) HAL_ETH_Start_IT(): + This API starts the MAC and DMA transmission and reception process, + end of transfer interrupts are enabled in this mode, + HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received + + (#) When data is received user can call the following API to get received data: + (##) HAL_ETH_ReadData(): Read a received packet + + (#) For transmission path, two APIs are available: + (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode + (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode, + HAL_ETH_TxCpltCallback() will be executed when end of transfer occur + + (#) Communication with an external PHY device: + (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY + (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register + + (#) Configure the Ethernet MAC after ETH peripheral initialization + (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef + (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef + + (#) Configure the Ethernet DMA after ETH peripheral initialization + (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef + (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef + + (#) Configure the Ethernet PTP after ETH peripheral initialization + (##) Define HAL_ETH_USE_PTP to use PTP APIs. + (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers + (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission + (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp + (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp + + -@- The ARP offload feature is not supported in this driver. + + -@- The PTP offload feature is not supported in this driver. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_ETH_RegisterCallback() to register an interrupt callback. + + Function HAL_ETH_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks RxAllocateCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxPtpCallback(). + + Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + For specific callbacks RxAllocateCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxPtpCallback(). + + By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit + or HAL_ETH_Init function. + + When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ +#ifdef HAL_ETH_MODULE_ENABLED + +#if defined(ETH) + +/** @defgroup ETH ETH + * @brief ETH HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup ETH_Private_Constants ETH Private Constants + * @{ + */ +#define ETH_MACCR_MASK 0xFFFB7F7CU +#define ETH_MACECR_MASK 0x3F077FFFU +#define ETH_MACPFR_MASK 0x800007FFU +#define ETH_MACWTR_MASK 0x0000010FU +#define ETH_MACTFCR_MASK 0xFFFF00F2U +#define ETH_MACRFCR_MASK 0x00000003U +#define ETH_MTLTQOMR_MASK 0x00000072U +#define ETH_MTLRQOMR_MASK 0x0000007BU + +#define ETH_DMAMR_MASK 0x00007802U +#define ETH_DMASBMR_MASK 0x0000D001U +#define ETH_DMACCR_MASK 0x00013FFFU +#define ETH_DMACTCR_MASK 0x003F1010U +#define ETH_DMACRCR_MASK 0x803F0000U +#define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \ + ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \ + ETH_MACPCSR_RWKPFE) + +/* Timeout values */ +#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \ + ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\ + ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE)) + +#define ETH_MACTSCR_MASK 0x0087FF2FU + +#define ETH_MACSTSUR_VALUE 0xFFFFFFFFU +#define ETH_MACSTNUR_VALUE 0xBB9ACA00U +#define ETH_SEGMENT_SIZE_DEFAULT 0x218U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Macros ETH Private Macros + * @{ + */ +/* Helper macros for TX descriptor handling */ +#define INCR_TX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ + } while (0) + +/* Helper macros for RX descriptor handling */ +#define INCR_RX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ + } while (0) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions ETH Private Functions + * @{ + */ +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode); +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup ETH_Exported_Functions ETH Exported Functions + * @{ + */ + +/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the ETH peripheral: + + (+) User must Implement HAL_ETH_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO and NVIC ). + + (+) Call the function HAL_ETH_Init() to configure the selected device with + the selected configuration: + (++) MAC address + (++) Media interface (MII or RMII) + (++) Rx DMA Descriptors Tab + (++) Tx DMA Descriptors Tab + (++) Length of Rx Buffers + + (+) Call the function HAL_ETH_DeInit() to restore the default configuration + of the selected ETH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the Ethernet peripheral registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tickstart; + + if (heth == NULL) + { + return HAL_ERROR; + } + if (heth->gState == HAL_ETH_STATE_RESET) + { + heth->gState = HAL_ETH_STATE_BUSY; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + + ETH_InitCallbacksToDefault(heth); + + if (heth->MspInitCallback == NULL) + { + heth->MspInitCallback = HAL_ETH_MspInit; + } + + /* Init the low level hardware */ + heth->MspInitCallback(heth); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit(heth); + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + } + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + if (heth->Init.MediaInterface == HAL_ETH_MII_MODE) + { + HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII); + } + else + { + HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII); + } + + /* Dummy read to sync with ETH */ + (void)SYSCFG->PMCR; + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for software reset */ + while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U) + { + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) + { + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + /* Return Error */ + return HAL_ERROR; + } + } + + /*------------------ MDIO CSR Clock Range Configuration --------------------*/ + HAL_ETH_SetMDIOClockRange(heth); + + /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/ + WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U)); + + /*------------------ MAC, MTL and DMA default Configuration ----------------*/ + ETH_MACDMAConfig(heth); + + /* SET DSL to 64 bit */ + MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT); + + /* Set Receive Buffers Length (must be a multiple of 4) */ + if ((heth->Init.RxBuffLen % 0x4U) != 0x0U) + { + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_PARAM; + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + /* Return Error */ + return HAL_ERROR; + } + else + { + MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1)); + } + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + ETH_DMATxDescListInit(heth); + + /*------------------ DMA Rx Descriptors Configuration ----------------------*/ + ETH_DMARxDescListInit(heth); + + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + /* Set MAC addr bits 32 to 47 */ + heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | + ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); + + heth->ErrorCode = HAL_ETH_ERROR_NONE; + heth->gState = HAL_ETH_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the ETH peripheral. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) +{ + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + + if (heth->MspDeInitCallback == NULL) + { + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + } + /* DeInit the low level hardware */ + heth->MspDeInitCallback(heth); +#else + + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspDeInit(heth); + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ + + /* Set ETH HAL state to Disabled */ + heth->gState = HAL_ETH_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes ETH MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ETH Callback + * To be used instead of the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = pCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = pCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = pCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = pCallback; + break; + + case HAL_ETH_EEE_CB_ID : + heth->EEECallback = pCallback; + break; + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = pCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (heth->gState == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an ETH Callback + * ETH callabck is redirected to the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_EEE_CB_ID EEE Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (heth->gState == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = HAL_ETH_ErrorCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = HAL_ETH_PMTCallback; + break; + + case HAL_ETH_EEE_CB_ID : + heth->EEECallback = HAL_ETH_EEECallback; + break; + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (heth->gState == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief ETH Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the ETH + data transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Enables Ethernet MAC and DMA reception and transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_READY) + { + heth->gState = HAL_ETH_STATE_BUSY; + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Clear Tx and Rx process stopped flags */ + heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); + + heth->gState = HAL_ETH_STATE_STARTED; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_READY) + { + heth->gState = HAL_ETH_STATE_BUSY; + + /* save IT mode to ETH Handle */ + heth->RxDescList.ItMode = 1U; + /* Disable Rx MMC Interrupts */ + SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \ + ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM); + + /* Disable Tx MMC Interrupts */ + SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \ + ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM); + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Clear Tx and Rx process stopped flags */ + heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS); + + /* Enable ETH DMA interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | + ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); + + heth->gState = HAL_ETH_STATE_STARTED; + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t descindex; + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + + /* Disable interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE | + ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE)); + + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST); + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR); + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + /* Set the Flush Transmit FIFO bit */ + SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ); + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Clear IOC bit to all Rx descriptors */ + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + { + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; + CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC); + } + + heth->RxDescList.ItMode = 0U; + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in polling mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @param Timeout: timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout) +{ + uint32_t tickstart; + ETH_DMADescTypeDef *dmatxdesc; + + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE) + { + /* Set the ETH error code */ + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + + tickstart = HAL_GetTick(); + + /* Wait for data to be transmitted or timeout occurred */ + while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET) + { + if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + heth->DMAErrorCode = heth->Instance->DMACSR; + /* Return function status */ + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; + /* Clear TX descriptor so that we can proceed */ + dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD); + return HAL_ERROR; + } + } + } + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in interrupt mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig) +{ + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Save the packet pointer to release. */ + heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; + + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) + { + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + + return HAL_OK; + + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Read a received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pAppBuff: Pointer to an application buffer to receive the packet. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) +{ + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; + + + if (pAppBuff == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState != HAL_ETH_STATE_STARTED) + { + return HAL_ERROR; + } + + descidx = heth->RxDescList.RxDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; + + /* Check if descriptor is not owned by DMA */ + while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + && (rxdataready == 0U)) + { + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_CTXT) != (uint32_t)RESET) + { + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1; + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0; + } + if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) + { + /* Check if first descriptor */ + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) + { + heth->RxDescList.RxDescCnt = 0; + heth->RxDescList.RxDataLength = 0; + } + + /* Check if last descriptor */ + bufflength = heth->Init.RxBuffLen; + if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET) + { + bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; + + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3; + + /* Packet ready */ + rxdataready = 1; + } + + /* Link data */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Link callback*/ + heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, bufflength); +#else + /* Link callback */ + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->RxDescList.RxDescCnt++; + heth->RxDescList.RxDataLength += bufflength; + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccnt++; + } + + heth->RxDescList.RxBuildDescCnt += desccnt; + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); + } + + heth->RxDescList.RxDescIdx = descidx; + + if (rxdataready == 1U) + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; + + return HAL_OK; + } + + /* Packet not ready */ + return HAL_ERROR; +} + +/** + * @brief This function gives back Rx Desc of the last received Packet + * to the DMA, so ETH DMA will be able to use these descriptors + * to receive next Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) +{ + uint32_t descidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + uint8_t allocStatus = 1U; + + descidx = heth->RxDescList.RxBuildDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount = heth->RxDescList.RxBuildDescCnt; + + while ((desccount > 0U) && (allocStatus != 0U)) + { + /* Check if a buffer's attached the descriptor */ + if (READ_REG(dmarxdesc->BackupAddr0) == 0U) + { + /* Get a new buffer. */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Allocate callback*/ + heth->rxAllocateCallback(&buff); +#else + /* Allocate callback */ + HAL_ETH_RxAllocateCallback(&buff); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + if (buff == NULL) + { + allocStatus = 0U; + } + else + { + WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); + WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff); + } + } + + if (allocStatus != 0U) + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + if (heth->RxDescList.ItMode != 0U) + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC); + } + else + { + WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V); + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount--; + } + } + + if (heth->RxDescList.RxBuildDescCnt != desccount) + { + /* Set the Tail pointer address */ + WRITE_REG(heth->Instance->DMACRDTPR, 0); + + heth->RxDescList.RxBuildDescIdx = descidx; + heth->RxDescList.RxBuildDescCnt = desccount; + } +} + +/** + * @brief Register the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxAllocateCallback: pointer to function to alloc buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback) +{ + if (rxAllocateCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to allocate buffer */ + heth->rxAllocateCallback = rxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Rx Allocate callback. + * @param buff: pointer to allocated buffer + * @retval None + */ +__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxAllocateCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Link callback. + * @param pStart: pointer to packet start + * @param pStart: pointer to packet end + * @param buff: pointer to received data + * @param Length: received data length + * @retval None + */ +__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(pStart); + UNUSED(pEnd); + UNUSED(buff); + UNUSED(Length); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxLinkCallback could be implemented in the user file + */ +} + +/** + * @brief Set the Rx link data function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxLinkCallback: pointer to function to link data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback) +{ + if (rxLinkCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to link data */ + heth->rxLinkCallback = rxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx link callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Get the error state of the last received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pErrorCode: pointer to uint32_t to hold the error code + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode) +{ + /* Get error bits. */ + *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK); + + return HAL_OK; +} + +/** + * @brief Set the Tx free function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txFreeCallback: pointer to function to release the packet + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback) +{ + if (txFreeCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to free transmmitted packet */ + heth->txFreeCallback = txFreeCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx free callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; + + return HAL_OK; +} + +/** + * @brief Tx Free callback. + * @param buff: pointer to buffer to free + * @retval None + */ +__weak void HAL_ETH_TxFreeCallback(uint32_t *buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxFreeCallback could be implemented in the user file + */ +} + +/** + * @brief Release transmitted Tx packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t numOfBuf = dmatxdesclist->BuffersInUse; + uint32_t idx = dmatxdesclist->releaseIndex; + uint8_t pktTxStatus = 1U; + uint8_t pktInUse; +#ifdef HAL_ETH_USE_PTP + ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; +#endif /* HAL_ETH_USE_PTP */ + + /* Loop through buffers in use. */ + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + { + pktInUse = 1U; + numOfBuf--; + /* If no packet, just examine the next packet. */ + if (dmatxdesclist->PacketAddress[idx] == NULL) + { + /* No packet in use, skip to next. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + pktInUse = 0U; + } + + if (pktInUse != 0U) + { + /* Determine if the packet has been transmitted. */ + if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U) + { +#ifdef HAL_ETH_USE_PTP + /* Disable Ptp transmission */ + CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); + + /* Get timestamp low */ + timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1; +#endif /* HAL_ETH_USE_PTP */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered callbacks*/ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); +#else + /* Call callbacks */ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the entry in the in-use array. */ + dmatxdesclist->PacketAddress[idx] = NULL; + + /* Update the transmit relesae index and number of buffers in use. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + dmatxdesclist->BuffersInUse = numOfBuf; + dmatxdesclist->releaseIndex = idx; + } + else + { + /* Get out of the loop! */ + pktTxStatus = 0U; + } + } + } + return HAL_OK; +} + +#ifdef HAL_ETH_USE_PTP +/** + * @brief Set the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + uint32_t tmpTSCR; + ETH_TimeTypeDef time; + + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + + tmpTSCR = ptpconfig->Timestamp | + ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) | + ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) | + ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_MACTSCR_TSCTRLSSR_Pos) | + ((uint32_t)ptpconfig->TimestampV2 << ETH_MACTSCR_TSVER2ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEthernet << ETH_MACTSCR_TSIPENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv6 << ETH_MACTSCR_TSIPV6ENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv4 << ETH_MACTSCR_TSIPV4ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEvent << ETH_MACTSCR_TSEVNTENA_Pos) | + ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) | + ((uint32_t)ptpconfig->TimestampSnapshots << ETH_MACTSCR_SNAPTYPSEL_Pos) | + ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) | + ((uint32_t)ptpconfig->TimestampChecksumCorrection << ETH_MACTSCR_CSC_Pos) | + ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos); + + /* Write to MACTSCR */ + MODIFY_REG(heth->Instance->MACTSCR, ETH_MACTSCR_MASK, tmpTSCR); + + /* Enable Timestamp */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA); + WRITE_REG(heth->Instance->MACSSIR, ptpconfig->TimestampSubsecondInc); + WRITE_REG(heth->Instance->MACTSAR, ptpconfig->TimestampAddend); + + /* Enable Timestamp */ + if (ptpconfig->TimestampAddendUpdate == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG); + while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) {} + } + + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT); + } + + /* Initialize Time */ + time.Seconds = 0; + time.NanoSeconds = 0; + HAL_ETH_PTP_SetTime(heth, &time); + + /* Ptp Init */ + SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT); + + /* Set PTP Configuration done */ + heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + ptpconfig->Timestamp = READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA); + ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSCFUPDT) >> ETH_MACTSCR_TSUPDT_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSENALL) >> ETH_MACTSCR_TSENALL_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSCTRLSSR) >> ETH_MACTSCR_TSCTRLSSR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSVER2ENA) >> ETH_MACTSCR_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPENA) >> ETH_MACTSCR_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPV6ENA) >> ETH_MACTSCR_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSIPV4ENA) >> ETH_MACTSCR_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSEVNTENA) >> ETH_MACTSCR_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSMSTRENA) >> ETH_MACTSCR_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampSnapshots = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_SNAPTYPSEL) >> ETH_MACTSCR_SNAPTYPSEL_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TSENMACADDR) >> ETH_MACTSCR_TSENMACADDR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampChecksumCorrection = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_CSC) >> ETH_MACTSCR_CSC_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR, + ETH_MACTSCR_TXTSSTSM) >> ETH_MACTSCR_TXTSSTSM_Pos) > 0U) + ? ENABLE : DISABLE; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to set + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Set Seconds */ + heth->Instance->MACSTSUR = time->Seconds; + + /* Set NanoSeconds */ + heth->Instance->MACSTNUR = time->NanoSeconds; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to get + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get Seconds */ + time->Seconds = heth->Instance->MACSTSUR; + + /* Get NanoSeconds */ + time->NanoSeconds = heth->Instance->MACSTNUR; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Update time for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains + * the time update information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) + { + /* Set Seconds update */ + heth->Instance->MACSTSUR = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U; + + if (READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) == ETH_MACTSCR_TSCTRLSSR) + { + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds; + } + else + { + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U; + } + } + else + { + /* Set Seconds update */ + heth->Instance->MACSTSUR = timeoffset->Seconds; + /* Set nanoSeconds update */ + heth->Instance->MACSTNUR = timeoffset->NanoSeconds; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Insert Timestamp in transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txtimestampconf: Enable or Disable timestamp in transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Enable Time Stamp transmission */ + SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get transmission timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * transmission timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t idx = dmatxdesclist->releaseIndex; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = dmatxdesc->DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = dmatxdesc->DESC1; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get receive timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * receive timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Register the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txPtpCallback: Function to handle Ptp transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback) +{ + if (txPtpCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + /* Set Function to handle Tx Ptp */ + heth->txPtpCallback = txPtpCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txPtpCallback = HAL_ETH_TxPtpCallback; + + return HAL_OK; +} + +/** + * @brief Tx Ptp callback. + * @param buff: pointer to application buffer + * @retval None + */ +__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxPtpCallback could be implemented in the user file + */ +} +#endif /* HAL_ETH_USE_PTP */ + +/** + * @brief This function handles ETH interrupt request. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + uint32_t macirqenable; + /* Packet received */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE)) + { + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + /* Packet transmitted */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE)) + { + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + + /* ETH DMA Error */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE)) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + + /* if fatal bus error occurred */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE)) + { + /* Get DMA error code */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS)); + + /* Disable all interrupts */ + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE); + + /* Set HAL state to ERROR */ + heth->gState = HAL_ETH_STATE_ERROR; + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + + /* Clear the interrupt summary flag */ + __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT | + ETH_DMACSR_RBU | ETH_DMACSR_AIS)); + } +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet DMA Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + } + } + + /* ETH MAC Error IT */ + macirqenable = heth->Instance->MACIER; + if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \ + ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE)) + { + heth->ErrorCode |= HAL_ETH_ERROR_MAC; + + /* Get MAC Rx Tx status and clear Status register pending bit */ + heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR); + + heth->gState = HAL_ETH_STATE_ERROR; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACErrorCode = (uint32_t)(0x0U); + } + + /* ETH PMT IT */ + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) + { + /* Get MAC Wake-up source and clear the status register pending bit */ + heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD)); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered PMT callback*/ + heth->PMTCallback(heth); +#else + /* Ethernet PMT callback */ + HAL_ETH_PMTCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACWakeUpEvent = (uint32_t)(0x0U); + } + + /* ETH EEE IT */ + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT)) + { + /* Get MAC LPI interrupt source and clear the status register pending bit */ + heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered EEE callback*/ + heth->EEECallback(heth); +#else + /* Ethernet EEE callback */ + HAL_ETH_EEECallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACLPIEvent = (uint32_t)(0x0U); + } + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* check ETH WAKEUP exti flag */ + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + else + { + /* check ETH WAKEUP exti flag */ + if (__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } +#else /* USE_HAL_ETH_REGISTER_CALLBACKS */ + /* check ETH WAKEUP exti flag */ + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet Power Management module IT callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_PMTCallback could be implemented in the user file + */ +} + +/** + * @brief Energy Efficient Etherent IT callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_EEECallback could be implemented in the user file + */ +} + +/** + * @brief ETH WAKEUP interrupt callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_WakeUpCallback could be implemented in the user file + */ +} + +/** + * @brief Read a PHY register + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param pRegValue: parameter to hold read value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) +{ + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) + { + return HAL_ERROR; + } + + /* Get the MACMDIOAR value */ + WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); + + /* Prepare the MDIO Address Register value + - Set the PHY device address + - Set the PHY register address + - Set the read mode + - Set the MII Busy bit */ + + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD); + SET_BIT(tmpreg, ETH_MACMDIOAR_MB); + + /* Write the result value into the MDII Address register */ + WRITE_REG(heth->Instance->MACMDIOAR, tmpreg); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag */ + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + /* Get MACMIIDR value */ + WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR); + + return HAL_OK; +} + + +/** + * @brief Writes to a PHY register. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param RegValue: the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) +{ + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET) + { + return HAL_ERROR; + } + + /* Get the MACMDIOAR value */ + WRITE_REG(tmpreg, heth->Instance->MACMDIOAR); + + /* Prepare the MDIO Address Register value + - Set the PHY device address + - Set the PHY register address + - Set the write mode + - Set the MII Busy bit */ + + MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16)); + MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR); + SET_BIT(tmpreg, ETH_MACMDIOAR_MB); + + + /* Give the value to the MII data register */ + WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue); + + /* Write the result value into the MII Address register */ + WRITE_REG(ETH->MACMDIOAR, tmpreg); + + tickstart = HAL_GetTick(); + + /* Wait for the Busy flag */ + while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U) + { + if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief ETH control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the ETH + peripheral. + +@endverbatim + * @{ + */ +/** + * @brief Get the configuration of the MAC and MTL subsystems. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold + * the configuration of the MAC. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + return HAL_ERROR; + } + + /* Get MAC parameters */ + macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN); + macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); + macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) + ? ENABLE : DISABLE; + macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, + ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE; + macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; + macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); + macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); + macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE; + macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE; + macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE; + macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE; + macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE; + macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE; + macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, + ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE; + macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG); + macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE; + macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC); + + macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL); + macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE; + macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE; + macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, + ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE; + macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) + ? ENABLE : DISABLE; + macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25; + + + macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE; + macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO); + + macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE; + macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE; + macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT); + macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16); + + + macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE; + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) + ? ENABLE : DISABLE; + + macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF)); + + macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF)); + macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE; + macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, + ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of the DMA. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + return HAL_ERROR; + } + + dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE; + dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB); + dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB) >> 15) > 0U) ? ENABLE : DISABLE; + + dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR | ETH_DMAMR_PR | ETH_DMAMR_DA)); + + dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL) >> 16) > 0U) ? ENABLE : DISABLE; + dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS); + + dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE; + dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL); + + dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE; + dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE; + dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL); + return HAL_OK; +} + +/** + * @brief Set the MAC configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains + * the configuration of the MAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetMACConfig(heth, macconf); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Set the ETH DMA configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetDMAConfig(heth, dmaconf); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configures the Clock range of ETH MDIO interface. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) +{ + uint32_t hclk; + uint32_t tmpreg; + + /* Get the ETHERNET MACMDIOAR value */ + tmpreg = (heth->Instance)->MACMDIOAR; + + /* Clear CSR Clock Range bits */ + tmpreg &= ~ETH_MACMDIOAR_CR; + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + /* Set CR bits depending on hclk value */ + if ((hclk >= 20000000U) && (hclk < 35000000U)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16; + } + else if ((hclk >= 35000000U) && (hclk < 60000000U)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26; + } + else if ((hclk >= 60000000U) && (hclk < 100000000U)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42; + } + else if ((hclk >= 100000000U) && (hclk < 150000000U)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62; + } + else /* (hclk >= 150000000)&&(hclk <= 200000000) */ + { + /* CSR Clock Range between 150-200 MHz */ + tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102; + } + + /* Configure the CSR Clock Range */ + (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg; +} + +/** + * @brief Set the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains + * the configuration of the ETH MAC filters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +{ + uint32_t filterconfig; + + if (pFilterConfig == NULL) + { + return HAL_ERROR; + } + + filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode | + ((uint32_t)pFilterConfig->HashUnicast << 1) | + ((uint32_t)pFilterConfig->HashMulticast << 2) | + ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | + ((uint32_t)pFilterConfig->PassAllMulticast << 4) | + ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | + ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | + ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | + ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | + pFilterConfig->ControlPacketsFilter); + + MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig); + + return HAL_OK; +} + +/** + * @brief Get the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold + * the configuration of the ETH MAC filters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +{ + if (pFilterConfig == NULL) + { + return HAL_ERROR; + } + + pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE; + pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, + ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; + pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF); + pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, + ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; + pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) + ? ENABLE : DISABLE; + pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Set the source MAC Address to be matched. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param AddrNbr: The MAC address to configure + * This parameter must be a value of the following: + * ETH_MAC_ADDRESS1 + * ETH_MAC_ADDRESS2 + * ETH_MAC_ADDRESS3 + * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr) +{ + uint32_t macaddrlr; + uint32_t macaddrhr; + + if (pMACAddr == NULL) + { + return HAL_ERROR; + } + + /* Get mac addr high reg offset */ + macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr); + /* Get mac addr low reg offset */ + macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr); + + /* Set MAC addr bits 32 to 47 */ + (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) | + ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]); + + /* Enable address and set source address bit */ + (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE); + + return HAL_OK; +} + +/** + * @brief Set the ETH Hash Table Value. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pHashTable: pointer to a table of two 32 bit values, that contains + * the 64 bits of the hash table. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) +{ + if (pHashTable == NULL) + { + return HAL_ERROR; + } + + heth->Instance->MACHT0R = pHashTable[0]; + heth->Instance->MACHT1R = pHashTable[1]; + + return HAL_OK; +} + +/** + * @brief Set the VLAN Identifier for Rx packets + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ComparisonBits: 12 or 16 bit comparison mode + must be a value of @ref ETH_VLAN_Tag_Comparison + * @param VLANIdentifier: VLAN Identifier value + * @retval None + */ +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) +{ + if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) + { + MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL, VLANIdentifier); + CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV); + } + else + { + MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID, VLANIdentifier); + SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV); + } +} + +/** + * @brief Enters the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure + * that contains the Power Down configuration + * @retval None. + */ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig) +{ + uint32_t powerdownconfig; + + powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) | + ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) | + ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) | + ((uint32_t)pPowerDownConfig->WakeUpForward << 10) | + ETH_MACPCSR_PWRDWN); + + /* Enable PMT interrupt */ + __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE); + + MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig); +} + +/** + * @brief Exits from the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) +{ + /* clear wake up sources */ + CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | + ETH_MACPCSR_RWKPFE); + + if (READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != (uint32_t)RESET) + { + /* Exit power down mode */ + CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN); + } + + /* Disable PMT interrupt */ + __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE); +} + +/** + * @brief Set the WakeUp filter. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilter: pointer to filter registers values + * @param Count: number of filter registers, must be from 1 to 8. + * @retval None. + */ +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count) +{ + uint32_t regindex; + + if (pFilter == NULL) + { + return HAL_ERROR; + } + + /* Reset Filter Pointer */ + SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST); + + /* Wake up packet filter config */ + for (regindex = 0; regindex < Count; regindex++) + { + /* Write filter regs */ + WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]); + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief ETH State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + ETH communication process, return Peripheral Errors occurred during communication + process + + +@endverbatim + * @{ + */ + +/** + * @brief Returns the ETH state. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +{ + return heth->gState; +} + +/** + * @brief Returns the ETH error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH Error Code + */ +uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth) +{ + return heth->ErrorCode; +} + +/** + * @brief Returns the ETH DMA error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH DMA Error Code + */ +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) +{ + return heth->DMAErrorCode; +} + +/** + * @brief Returns the ETH MAC error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC Error Code + */ +uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth) +{ + return heth->MACErrorCode; +} + +/** + * @brief Returns the ETH MAC WakeUp event source + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC WakeUp event source + */ +uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth) +{ + return heth->MACWakeUpEvent; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions ETH Private Functions + * @{ + */ + + +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + uint32_t macregval; + + /*------------------------ MACCR Configuration --------------------*/ + macregval = (macconf->InterPacketGapVal | + macconf->SourceAddrControl | + ((uint32_t)macconf->ChecksumOffload << 27) | + ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | + ((uint32_t)macconf->Support2KPacket << 22) | + ((uint32_t)macconf->CRCStripTypePacket << 21) | + ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | + ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | + ((uint32_t)macconf->JumboPacket << 16) | + macconf->Speed | + macconf->DuplexMode | + ((uint32_t)macconf->LoopbackMode << 12) | + ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | + ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) | + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | + macconf->BackOffLimit | + ((uint32_t)macconf->DeferralCheck << 4) | + macconf->PreambleLength); + + /* Write to MACCR */ + MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval); + + /*------------------------ MACECR Configuration --------------------*/ + macregval = ((macconf->ExtendedInterPacketGapVal << 25) | + ((uint32_t)macconf->ExtendedInterPacketGap << 24) | + ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | + ((uint32_t)macconf->SlowProtocolDetect << 17) | + ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) | + macconf->GiantPacketSizeLimit); + + /* Write to MACECR */ + MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval); + + /*------------------------ MACWTR Configuration --------------------*/ + macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) | + macconf->WatchdogTimeout); + + /* Write to MACWTR */ + MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval); + + /*------------------------ MACTFCR Configuration --------------------*/ + macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | + macconf->PauseLowThreshold | + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) | + (macconf->PauseTime << 16)); + + /* Write to MACTFCR */ + MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval); + + /*------------------------ MACRFCR Configuration --------------------*/ + macregval = ((uint32_t)macconf->ReceiveFlowControl | + ((uint32_t)macconf->UnicastPausePacketDetect << 1)); + + /* Write to MACRFCR */ + MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval); + + /*------------------------ MTLTQOMR Configuration --------------------*/ + /* Write to MTLTQOMR */ + MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode); + + /*------------------------ MTLRQOMR Configuration --------------------*/ + macregval = (macconf->ReceiveQueueMode | + ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | + ((uint32_t)macconf->ForwardRxErrorPacket << 4) | + ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3)); + + /* Write to MTLRQOMR */ + MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval); +} + +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + uint32_t dmaregval; + + /*------------------------ DMAMR Configuration --------------------*/ + MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration); + + /*------------------------ DMASBMR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | + dmaconf->BurstMode | + ((uint32_t)dmaconf->RebuildINCRxBurst << 15)); + + MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval); + + /*------------------------ DMACCR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) | + dmaconf->MaximumSegmentSize); + + MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval); + + /*------------------------ DMACTCR Configuration --------------------*/ + dmaregval = (dmaconf->TxDMABurstLength | + ((uint32_t)dmaconf->SecondPacketOperate << 4) | + ((uint32_t)dmaconf->TCPSegmentation << 12)); + + MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval); + + /*------------------------ DMACRCR Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) | + dmaconf->RxDMABurstLength); + + /* Write to DMACRCR */ + MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval); +} + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) +{ + ETH_MACConfigTypeDef macDefaultConf; + ETH_DMAConfigTypeDef dmaDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + macDefaultConf.AutomaticPadCRCStrip = ENABLE; + macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; + macDefaultConf.CarrierSenseBeforeTransmit = DISABLE; + macDefaultConf.CarrierSenseDuringTransmit = DISABLE; + macDefaultConf.ChecksumOffload = ENABLE; + macDefaultConf.CRCCheckingRxPackets = ENABLE; + macDefaultConf.CRCStripTypePacket = ENABLE; + macDefaultConf.DeferralCheck = DISABLE; + macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE; + macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; + macDefaultConf.ExtendedInterPacketGap = DISABLE; + macDefaultConf.ExtendedInterPacketGapVal = 0x0; + macDefaultConf.ForwardRxErrorPacket = DISABLE; + macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE; + macDefaultConf.GiantPacketSizeLimit = 0x618; + macDefaultConf.GiantPacketSizeLimitControl = DISABLE; + macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT; + macDefaultConf.Jabber = ENABLE; + macDefaultConf.JumboPacket = DISABLE; + macDefaultConf.LoopbackMode = DISABLE; + macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4; + macDefaultConf.PauseTime = 0x0; + macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7; + macDefaultConf.ProgrammableWatchdog = DISABLE; + macDefaultConf.ReceiveFlowControl = DISABLE; + macDefaultConf.ReceiveOwn = ENABLE; + macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD; + macDefaultConf.RetryTransmission = ENABLE; + macDefaultConf.SlowProtocolDetect = DISABLE; + macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0; + macDefaultConf.Speed = ETH_SPEED_100M; + macDefaultConf.Support2KPacket = DISABLE; + macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD; + macDefaultConf.TransmitFlowControl = DISABLE; + macDefaultConf.UnicastPausePacketDetect = DISABLE; + macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; + macDefaultConf.Watchdog = ENABLE; + macDefaultConf.WatchdogTimeout = ETH_MACWTR_WTO_2KB; + macDefaultConf.ZeroQuantaPause = ENABLE; + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + dmaDefaultConf.AddressAlignedBeats = ENABLE; + dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; + dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1; + dmaDefaultConf.FlushRxPacket = DISABLE; + dmaDefaultConf.PBLx8Mode = DISABLE; + dmaDefaultConf.RebuildINCRxBurst = DISABLE; + dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.SecondPacketOperate = DISABLE; + dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.TCPSegmentation = DISABLE; + dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT; + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); +} + + +/** + * @brief Initializes the DMA Tx descriptors. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmatxdesc; + uint32_t i; + + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + { + dmatxdesc = heth->Init.TxDesc + i; + + WRITE_REG(dmatxdesc->DESC0, 0x0); + WRITE_REG(dmatxdesc->DESC1, 0x0); + WRITE_REG(dmatxdesc->DESC2, 0x0); + WRITE_REG(dmatxdesc->DESC3, 0x0); + + WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); + + } + + heth->TxDescList.CurTxDesc = 0; + + /* Set Transmit Descriptor Ring Length */ + WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U)); + + /* Set Transmit Descriptor List Address */ + WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc); + + /* Set Transmit Descriptor Tail pointer */ + WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t i; + + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + { + dmarxdesc = heth->Init.RxDesc + i; + + WRITE_REG(dmarxdesc->DESC0, 0x0); + WRITE_REG(dmarxdesc->DESC1, 0x0); + WRITE_REG(dmarxdesc->DESC2, 0x0); + WRITE_REG(dmarxdesc->DESC3, 0x0); + WRITE_REG(dmarxdesc->BackupAddr0, 0x0); + WRITE_REG(dmarxdesc->BackupAddr1, 0x0); + + + /* Set Rx descritors addresses */ + WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + + } + + WRITE_REG(heth->RxDescList.RxDescIdx, 0); + WRITE_REG(heth->RxDescList.RxDescCnt, 0); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); + WRITE_REG(heth->RxDescList.ItMode, 0); + + /* Set Receive Descriptor Ring Length */ + WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U))); + + /* Set Receive Descriptor List Address */ + WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc); + + /* Set Receive Descriptor Tail pointer Address */ + WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U)))); +} + +/** + * @brief Prepare Tx DMA descriptor before transmission. + * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Tx packet configuration + * @param ItMode: Enable or disable Tx EOT interrept + * @retval Status + */ +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + uint32_t firstdescidx = dmatxdesclist->CurTxDesc; + uint32_t idx; + uint32_t descnbr = 0; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + uint32_t bd_count = 0; + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + return HAL_ETH_ERROR_BUSY; + } + + /***************************************************************************/ + /***************** Context descriptor configuration (Optional) **********/ + /***************************************************************************/ + /* If VLAN tag is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + { + /* Set vlan tag value */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag); + /* Set vlan tag valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV); + /* Set the descriptor as the vlan input source */ + SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI); + + /* if inner VLAN is enabled */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET) + { + /* Set inner vlan tag value */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16)); + /* Set inner vlan tag valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV); + + /* Set Vlan Tag control */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl); + + /* Set the descriptor as the inner vlan input source */ + SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI); + /* Enable double VLAN processing */ + SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP); + } + } + + /* if tcp segmentation is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + /* Set MSS value */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize); + /* Set MSS valid bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV); + } + + if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)) + { + /* Set as context descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set own bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + descnbr += 1U; + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + { + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx]; + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Clear own bit */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN); + + return HAL_ETH_ERROR_BUSY; + } + } + + /***************************************************************************/ + /***************** Normal descriptors configuration *****************/ + /***************************************************************************/ + + descnbr += 1U; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + + if (txbuffer->next != NULL) + { + txbuffer = txbuffer->next; + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + /* Set TCP Header length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19)); + /* Set TCP payload length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + /* Set TCP Segmentation Enabled bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); + } + else + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl); + } + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET) + { + /* Set Vlan Tag control */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); + } + + /* Mark it as First Descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + /* Mark it as NORMAL descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* set OWN bit of FIRST descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + + /* If source address insertion/replacement is enabled for this packet */ + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl); + } + + /* only if the packet is split into more than one descriptors > 1 */ + while (txbuffer->next != NULL) + { + /* Clear the LD bit of previous descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* Clear the FD bit of new Descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + descidx = firstdescidx; + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* clear previous desc own bit */ + for (idx = 0; idx < descnbr; idx ++) + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + } + + return HAL_ETH_ERROR_BUSY; + } + + descnbr += 1U; + + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + + if (txbuffer->next != NULL) + { + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + { + /* Set TCP payload length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + /* Set TCP Segmentation Enabled bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); + } + else + { + /* Set the packet length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + { + /* Checksum Insertion Control */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + } + } + + bd_count += 1U; + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set Own bit */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + /* Mark it as NORMAL descriptor */ + CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + } + + if (ItMode != ((uint32_t)RESET)) + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + } + + /* Mark it as LAST descriptor */ + SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; + + dmatxdesclist->CurTxDesc = descidx; + + /* disable the interrupt */ + __disable_irq(); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + + /* Enable interrupts back */ + __enable_irq(); + + + /* Return function status */ + return HAL_ETH_ERROR_NONE; +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) +{ + /* Init the ETH Callback settings */ + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ + heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ + heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ + heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */ + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; /* Legacy weak RxLinkCallback */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; /* Legacy weak TxFreeCallback */ +#ifdef HAL_ETH_USE_PTP + heth->txPtpCallback = HAL_ETH_TxPtpCallback; /* Legacy weak TxPtpCallback */ +#endif /* HAL_ETH_USE_PTP */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */ +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#endif /* HAL_ETH_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c new file mode 100644 index 0000000..ad9870c --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth_ex.c @@ -0,0 +1,578 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_eth_ex.c + * @author MCD Application Team + * @brief ETH HAL Extended module driver. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +#ifdef HAL_ETH_MODULE_ENABLED + +#if defined(ETH) + +/** @defgroup ETHEx ETHEx + * @brief ETH HAL Extended module driver + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ETHEx_Private_Constants ETHEx Private Constants + * @{ + */ +#define ETH_MACL4CR_MASK (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \ + ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \ + ETH_MACL3L4CR_L4DPIM) + +#define ETH_MACL3CR_MASK (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \ + ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \ + ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \ + ETH_MACL3L4CR_L3HDBM) + +#define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \ + ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \ + ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \ + ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \ + ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \ + ETH_MACVTR_VTIM | ETH_MACVTR_ETV) + +#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \ + ETH_MACVIR_VLP | ETH_MACVIR_VLC) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions + * @{ + */ + +/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure ARP offload module + (+) Configure L3 and L4 filters + (+) Configure Extended VLAN features + (+) Configure Energy Efficient Ethernet module + +@endverbatim + * @{ + */ + +/** + * @brief Enables ARP Offload. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth) +{ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP); +} + +/** + * @brief Disables ARP Offload. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth) +{ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP); +} + +/** + * @brief Set the ARP Match IP address + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param IpAddress: IP Address to be matched for incoming ARP requests + * @retval None + */ +void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress) +{ + WRITE_REG(heth->Instance->MACARPAR, IpAddress); +} + +/** + * @brief Configures the L4 Filter, this function allow to: + * set the layer 4 protocol to be matched (TCP or UDP) + * enable/disable L4 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L4 filter to configured, this parameter must be one of the following + * ETH_L4_FILTER_0 + * ETH_L4_FILTER_1 + * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure + * that contains L4 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig) +{ + __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)); + + if (pL4FilterConfig == NULL) + { + return HAL_ERROR; + } + + /* Write configuration to (MACL3L4C0R + filter )register */ + MODIFY_REG(*configreg, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol | + pL4FilterConfig->SrcPortFilterMatch | + pL4FilterConfig->DestPortFilterMatch)); + + configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)); + + /* Write configuration to (MACL4A0R + filter )register */ + MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP), (pL4FilterConfig->SourcePort | + (pL4FilterConfig->DestinationPort << 16))); + + /* Enable L4 filter */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); + + return HAL_OK; +} + +/** + * @brief Configures the L4 Filter, this function allow to: + * set the layer 4 protocol to be matched (TCP or UDP) + * enable/disable L4 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L4 filter to configured, this parameter must be one of the following + * ETH_L4_FILTER_0 + * ETH_L4_FILTER_1 + * @param pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure + * that contains L4 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L4FilterConfigTypeDef *pL4FilterConfig) +{ + if (pL4FilterConfig == NULL) + { + return HAL_ERROR; + } + + /* Get configuration to (MACL3L4C0R + filter )register */ + pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L4PEN); + pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)); + pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM)); + + /* Get configuration to (MACL3L4C0R + filter )register */ + pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), + ETH_MACL4AR_L4DP) >> 16); + pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP); + + return HAL_OK; +} + +/** + * @brief Configures the L3 Filter, this function allow to: + * set the layer 3 protocol to be matched (IPv4 or IPv6) + * enable/disable L3 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L3 filter to configured, this parameter must be one of the following + * ETH_L3_FILTER_0 + * ETH_L3_FILTER_1 + * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure + * that contains L3 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig) +{ + __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)); + + if (pL3FilterConfig == NULL) + { + return HAL_ERROR; + } + + /* Write configuration to (MACL3L4C0R + filter )register */ + MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol | + pL3FilterConfig->SrcAddrFilterMatch | + pL3FilterConfig->DestAddrFilterMatch | + (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) | + (pL3FilterConfig->DestAddrHigherBitsMatch << 11))); + + /* Check if IPv6 protocol is selected */ + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + /* Set the IPv6 address match */ + /* Set Bits[31:0] of 128-bit IP addr */ + *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0]; + /* Set Bits[63:32] of 128-bit IP addr */ + *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1]; + /* update Bits[95:64] of 128-bit IP addr */ + *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2]; + /* update Bits[127:96] of 128-bit IP addr */ + *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3]; + } + else /* IPv4 protocol is selected */ + { + /* Set the IPv4 source address match */ + *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr; + /* Set the IPv4 destination address match */ + *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr; + } + + return HAL_OK; +} + +/** + * @brief Configures the L3 Filter, this function allow to: + * set the layer 3 protocol to be matched (IPv4 or IPv6) + * enable/disable L3 source/destination port perfect/inverse match. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param Filter: L3 filter to configured, this parameter must be one of the following + * ETH_L3_FILTER_0 + * ETH_L3_FILTER_1 + * @param pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure + * that will contain the L3 filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, + ETH_L3FilterConfigTypeDef *pL3FilterConfig) +{ + if (pL3FilterConfig == NULL) + { + return HAL_ERROR; + } + + pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3PEN); + pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)); + pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)); + pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3HSBM) >> 6); + pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), + ETH_MACL3L4CR_L3HDBM) >> 11); + + if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH) + { + pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)); + pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)); + pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)); + pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)); + } + else + { + pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)); + pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)); + } + + return HAL_OK; +} + +/** + * @brief Enables L3 and L4 filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth) +{ + /* Enable L3/L4 filter */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); +} + +/** + * @brief Disables L3 and L4 filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth) +{ + /* Disable L3/L4 filter */ + CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE); +} + +/** + * @brief Get the VLAN Configuration for Receive Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure + * that will contain the VLAN filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) +{ + if (pVlanConfig == NULL) + { + return HAL_ERROR; + } + + pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE; + pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS); + pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE; + pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, + ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE; + pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS); + pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, + (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)); + pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) + ? DISABLE : ENABLE; + + return HAL_OK; +} + +/** + * @brief Set the VLAN Configuration for Receive Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure + * that contains VLAN filter configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig) +{ + if (pVlanConfig == NULL) + { + return HAL_ERROR; + } + + /* Write config to MACVTR */ + MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) | + pVlanConfig->StripInnerVLANTag | + ((uint32_t)pVlanConfig->InnerVLANTag << 27) | + ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) | + ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) | + ((uint32_t)pVlanConfig->VLANTagInStatus << 24) | + pVlanConfig->StripVLANTag | + pVlanConfig->VLANTypeCheck | + ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17))); + + return HAL_OK; +} + +/** + * @brief Set the VLAN Hash Table + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANHashTable: VLAN hash table 16 bit value + * @retval None + */ +void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable) +{ + MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable); +} + +/** + * @brief Get the VLAN Configuration for Transmit Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANTag: Selects the vlan tag, this parameter must be one of the following + * ETH_OUTER_TX_VLANTAG + * ETH_INNER_TX_VLANTAG + * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure + * that will contain the Tx VLAN filter configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig) +{ + if (pVlanConfig == NULL) + { + return HAL_ERROR; + } + + if (VLANTag == ETH_INNER_TX_VLANTAG) + { + pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE; + pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC)); + } + else + { + pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE; + pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE; + pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC)); + } + + return HAL_OK;; +} + +/** + * @brief Set the VLAN Configuration for Transmit Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANTag: Selects the vlan tag, this parameter must be one of the following + * ETH_OUTER_TX_VLANTAG + * ETH_INNER_TX_VLANTAG + * @param pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure + * that contains Tx VLAN filter configuration. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, + ETH_TxVLANConfigTypeDef *pVlanConfig) +{ + if (VLANTag == ETH_INNER_TX_VLANTAG) + { + MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) | + ((uint32_t)pVlanConfig->SVLANType << 19) | + pVlanConfig->VLANTagControl)); + /* Enable Double VLAN processing */ + SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP); + } + else + { + MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) | + ((uint32_t)pVlanConfig->SVLANType << 19) | + pVlanConfig->VLANTagControl)); + } + + return HAL_OK; +} + +/** + * @brief Set the VLAN Tag Identifier for Transmit Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param VLANTag: Selects the vlan tag, this parameter must be one of the following + * ETH_OUTER_TX_VLANTAG + * ETH_INNER_TX_VLANTAG + * @param VLANIdentifier: VLAN Identifier 16 bit value + * @retval None + */ +void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier) +{ + if (VLANTag == ETH_INNER_TX_VLANTAG) + { + MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier); + } + else + { + MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier); + } +} + +/** + * @brief Enables the VLAN Tag Filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth) +{ + /* Enable VLAN processing */ + SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE); +} + +/** + * @brief Disables the VLAN Tag Filtering process. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth) +{ + /* Disable VLAN processing */ + CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE); +} + +/** + * @brief Enters the Low Power Idle (LPI) mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param TxAutomate: Enable/Disable automate enter/exit LPI mode. + * @param TxClockStop: Enable/Disable Tx clock stop in LPI mode. + * @retval None + */ +void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop) +{ + /* Enable LPI Interrupts */ + __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE); + + /* Write to LPI Control register: Enter low power mode */ + MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), + (((uint32_t)TxAutomate << 19) | + ((uint32_t)TxClockStop << 21) | + ETH_MACLCSR_LPIEN)); +} + +/** + * @brief Exits the Low Power Idle (LPI) mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth) +{ + /* Clear the LPI Config and exit low power mode */ + CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE)); + + /* Enable LPI Interrupts */ + __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE); +} + + +/** + * @brief Returns the ETH MAC LPI event + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC WakeUp event + */ +uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth) +{ + return heth->MACLPIEvent; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ETH */ + +#endif /* HAL_ETH_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c new file mode 100644 index 0000000..c9090f7 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c @@ -0,0 +1,859 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt (CORE1 or CORE2 in case of dual core line ) + (++) Event (CORE1 or CORE2 in case of dual core line ) + (++) a combination of the previous + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear source. + It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain). + Value can be one of the following: + (++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 0 + (+++) On a configurable Line : the D3 domain wakeup signal is + automatically cleared after after the Delay + Rising Edge detect + (+++) On a direct Line : the D3 domain wakeup signal is + cleared after the direct event input signal is cleared + + (++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b00 : + DMA ch6 event selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b01 : + DMA ch7 event selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b10 : + LPTIM4 out selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b11 : + LPTIM5 out selected as D3 domain pendclear source + + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain), + choose gpio D3 PendClearSource using PendClearSource + member from EXTI_PendClear_Source structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + +#if defined (DUAL_CORE) + /* Configure interrupt mode for Core2 : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; +#endif /* DUAL_CORE */ + + /* Configure the D3 PendClear source in case of Wakeup target is Any */ + if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource)); + + /*Calc the PMR register address for the given line */ + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE) + { + /* Clear D3PMRx register for the given line */ + regval &= ~maskline; + /* Store D3PMRx register value */ + *regaddr = regval; + } + else + { + /* Set D3PMRx register to 1 for the given line */ + regval |= maskline; + /* Store D3PMRx register value */ + *regaddr = regval; + + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL)); + *regaddr = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + pExtiConfig->Mode = EXTI_MODE_NONE; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } +#if defined (DUAL_CORE) + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT; + } +#endif /*DUAL_CORE*/ + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00U; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + /* Get default Pend Clear Source */ + pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; + + /* 3] Get D3 Pend Clear source */ + if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + if(((*regaddr) & linepos) != 0UL) + { + /* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */ + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos)); + } + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + +#if defined (DUAL_CORE) + /* 1] Clear CM4 interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear CM4 event mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; +#endif /* DUAL_CORE */ + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL))); + SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* 4] Clear D3 Config lines */ + if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = (*regaddr & ~maskline); + + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + /*Clear D3 PendClear source */ + *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL)); + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4*/ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* Get pending bit */ + regval = (*regaddr & maskline); + + if (regval != 0x00U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4 */ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4 */ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* Clear Pending bit */ + *regaddr = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c new file mode 100644 index 0000000..a3fe346 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c @@ -0,0 +1,1201 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) Error code correction (ECC) : Data in flash are 266-bits word + (10 bits added per flash word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32H7xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: 256-bit word only + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_FLASH_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + [..] + (@) For any Flash memory program operation (erase or program), the CPU clock frequency + (HCLK) must be at least 1MHz. + (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + a Flash memory operation. + (@) The application can simultaneously request a read and a write operation through each AXI + interface. + As the Flash memory is divided into two independent banks, the embedded Flash + memory interface can drive different operations at the same time on each bank. For + example a read, write or erase operation can be executed on bank 1 while another read, + write or erase operation is executed on bank 2. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Functions FLASH Exported functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program a flash word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress; + __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + uint32_t bank; + uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else + if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ + { + bank = FLASH_BANK_1; + } +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + { + bank = FLASH_BANK_2; + } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + + if(status == HAL_OK) + { +#if defined (DUAL_BANK) + if(bank == FLASH_BANK_1) + { +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + } + else + { + /* Set PG bit */ + SET_BIT(FLASH->CR2, FLASH_CR_PG); + } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } +#endif /* DUAL_BANK */ + + __ISB(); + __DSB(); + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } + + __ISB(); + __DSB(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + if(bank == FLASH_BANK_1) + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + } + else + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR2, FLASH_CR_PG); + } + } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + } +#endif /* DUAL_BANK */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program a flash word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress; + __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + uint32_t bank; + uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else + if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ + { + bank = FLASH_BANK_1; + } +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + { + bank = FLASH_BANK_2; + } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + pFlash.Address = FlashAddress; + +#if defined (DUAL_BANK) + if(bank == FLASH_BANK_1) + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2; + + /* Set PG bit */ + SET_BIT(FLASH->CR2, FLASH_CR_PG); + + /* Enable End of Operation and Error interrupts for Bank2 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ + } +#else /* Single Bank */ + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ +#endif /* DUAL_BANK */ + + __ISB(); + __DSB(); + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } + + __ISB(); + __DSB(); + } + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t temp; + uint32_t errorflag; + FLASH_ProcedureTypeDef procedure; + + /* Check FLASH Bank1 End of Operation flag */ + if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1) + { + /* Nb of sector to erased can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if(pFlash.NbSectorsToErase != 0U) + { + /* Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear bank 1 End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + + /* Increment sector number */ + pFlash.Sector++; + temp = pFlash.Sector; + FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called */ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } + else + { + procedure = pFlash.ProcedureOnGoing; + + if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1); + } + else if(procedure == FLASH_PROC_PROGRAM_BANK1) + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else + { + /* Nothing to do */ + } + + if((procedure != FLASH_PROC_SECTERASE_BANK2) && \ + (procedure != FLASH_PROC_MASSERASE_BANK2) && \ + (procedure != FLASH_PROC_PROGRAM_BANK2)) + { + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } + } + +#if defined (DUAL_BANK) + /* Check FLASH Bank2 End of Operation flag */ + if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2) + { + /*Nb of sector to erased can be decreased*/ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase*/ + if(pFlash.NbSectorsToErase != 0U) + { + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear bank 2 End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + + /*Increment sector number*/ + pFlash.Sector++; + temp = pFlash.Sector; + FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called */ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } + else + { + procedure = pFlash.ProcedureOnGoing; + + if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /*MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2); + } + else if(procedure == FLASH_PROC_PROGRAM_BANK2) + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else + { + /* Nothing to do */ + } + + if((procedure != FLASH_PROC_SECTERASE_BANK1) && \ + (procedure != FLASH_PROC_MASSERASE_BANK1) && \ + (procedure != FLASH_PROC_PROGRAM_BANK1)) + { + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } + } +#endif /* DUAL_BANK */ + + /* Check FLASH Bank1 operation error flags */ +#if defined (FLASH_SR_OPERR) + errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ + FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); +#else + errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ + FLASH_FLAG_INCERR_BANK1); +#endif /* FLASH_SR_OPERR */ + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= errorflag; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag); + + procedure = pFlash.ProcedureOnGoing; + + if(procedure == FLASH_PROC_SECTERASE_BANK1) + { + /* Return the faulty sector */ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /* Return the faulty bank */ + temp = FLASH_BANK_1; + } + else + { + /* Return the faulty address */ + temp = pFlash.Address; + } + + /* Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + } + +#if defined (DUAL_BANK) + /* Check FLASH Bank2 operation error flags */ +#if defined (FLASH_SR_OPERR) + errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ + FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU); +#else + errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ + FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU); +#endif /* FLASH_SR_OPERR */ + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= (errorflag | 0x80000000U); + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag); + + procedure = pFlash.ProcedureOnGoing; + + if(procedure== FLASH_PROC_SECTERASE_BANK2) + { + /*return the faulty sector*/ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /*return the faulty bank*/ + temp = FLASH_BANK_2; + } + else + { + /*return the faulty address*/ + temp = pFlash.Address; + } + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + } +#endif /* DUAL_BANK */ + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { +#if defined (FLASH_CR_OPERRIE) + /* Disable Bank1 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); + +#if defined (DUAL_BANK) + /* Disable Bank2 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#endif /* DUAL_BANK */ +#else + /* Disable Bank1 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + +#if defined (DUAL_BANK) + /* Disable Bank2 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* DUAL_BANK */ +#endif /* FLASH_CR_OPERRIE */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased + * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank1 Registers access */ + WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash Bank2 is unlocked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Locks the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */ + SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + + /* Verify Flash Bank1 is locked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U) + { + return HAL_ERROR; + } + +#if defined (DUAL_BANK) + /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */ + SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + + /* Verify Flash Bank2 is locked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U) + { + return HAL_ERROR; + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2); + + /* Verify that the Option Bytes are unlocked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); + + /* Verify that the Option Bytes are locked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Launch the option bytes loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + HAL_StatusTypeDef status; + + /* Wait for CRC computation to be completed */ + if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } +#if defined (DUAL_BANK) + else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } +#endif /* DUAL_BANK */ + else + { + status = HAL_OK; + } + + if (status == HAL_OK) + { + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART); + + /* Wait for OB change operation to be completed */ + status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval HAL_FLASH_ERRORCode The returned value can be: + * @arg HAL_FLASH_ERROR_NONE : No error set + * + * @arg HAL_FLASH_ERROR_WRP_BANK1 : Write Protection Error on Bank 1 + * @arg HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1 + * @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1 + * @arg HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1 + * @arg HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1 + * @arg HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1 + * @arg HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1 + * @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1 + * @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1 + * @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1 + * + * @arg HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2 + * @arg HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2 + * @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2 + * @arg HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2 + * @arg HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2 + * @arg HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2 + * @arg HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2 + * @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2 + * @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2 + * @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2 +*/ + +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) +{ + /* Wait for the FLASH operation to complete by polling on QW flag to be reset. + Even if the FLASH operation fails, the QW flag will be reset and an error + flag will be set */ + + uint32_t bsyflag = FLASH_FLAG_QW_BANK1; + uint32_t errorflag = 0; + uint32_t tickstart = HAL_GetTick(); + + assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + +#if defined (DUAL_BANK) + + if (Bank == FLASH_BANK_2) + { + /* Select bsyflag depending on Bank */ + bsyflag = FLASH_FLAG_QW_BANK2; + } +#endif /* DUAL_BANK */ + + while(__HAL_FLASH_GET_FLAG(bsyflag)) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Get Error Flags */ + if (Bank == FLASH_BANK_1) + { + errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; + } +#if defined (DUAL_BANK) + else + { + errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; + } +#endif /* DUAL_BANK */ + + /* In case of error reported in Flash SR1 or SR2 register */ + if((errorflag & 0x7FFFFFFFU) != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= errorflag; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(errorflag); + + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if(Bank == FLASH_BANK_1) + { + if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } +#if defined (DUAL_BANK) + else + { + if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Wait for a FLASH Option Bytes change operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout) +{ + /* Get timeout */ + uint32_t tickstart = HAL_GetTick(); + + /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */ + while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check option byte change error */ + if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE; + + /* Clear the OB error flag */ + FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR; + + return HAL_ERROR; + } + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @brief Wait for a FLASH CRC computation to complete. + * @param Timeout maximum flash operation timeout + * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) +{ + uint32_t bsyflag; + uint32_t tickstart = HAL_GetTick(); + + assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + + /* Select bsyflag depending on Bank */ + if(Bank == FLASH_BANK_1) + { + bsyflag = FLASH_FLAG_CRC_BUSY_BANK1; + } + else + { + bsyflag = FLASH_FLAG_CRC_BUSY_BANK2; + } + + /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */ + while(__HAL_FLASH_GET_FLAG(bsyflag)) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH CRC read error flag */ + if(Bank == FLASH_BANK_1) + { + if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1)) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1; + + /* Clear FLASH CRC read error pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1); + + return HAL_ERROR; + } + } +#if defined (DUAL_BANK) + else + { + if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2)) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2; + + /* Clear FLASH CRC read error pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2); + + return HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c new file mode 100644 index 0000000..fd4acec --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c @@ -0,0 +1,1860 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32H7xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) PCROP protection for all banks + (+) Global readout protection (RDP) + (+) Write protection + (+) Secure access only protection + (+) Bank / register swapping (when Dual-Bank) + (+) Cyclic Redundancy Check (CRC) + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32H7xx devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Sector erase, bank erase and dual-bank mass erase + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to: + (++) Set/Reset the write protection per bank + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (++) PCROP protection configuration and control per bank + (++) Secure area configuration and control per bank + (++) Core Boot address configuration + (++) TCM / AXI shared RAM configuration + (++) CPU Frequency Boost configuration + + (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(), + HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions + + (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to: + (++) Enable CRC feature + (++) Program the desired burst size + (++) Define the user Flash Area on which the CRC has be computed + (++) Perform the CRC computation + (++) Disable CRC feature + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks); +static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); +static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank); +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank); +static void FLASH_OB_RDPConfig(uint32_t RDPLevel); +static uint32_t FLASH_OB_GetRDP(void); +static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks); +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank); +static void FLASH_OB_BOR_LevelConfig(uint32_t Level); +static uint32_t FLASH_OB_GetBOR(void); +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); +static uint32_t FLASH_OB_GetUser(void); +static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); +static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); +static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks); +static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank); +static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank); +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank); + +#if defined (DUAL_CORE) +static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); +static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); +#endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block); +static uint32_t FLASH_OB_OTP_GetLock(void); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig); +static uint32_t FLASH_OB_SharedRAM_GetConfig(void); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost); +static uint32_t FLASH_OB_CPUFreq_GetBoost(void); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that contains the configuration + * information on faulty sector in case of error (0xFFFFFFFF means that all + * the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed on Bank1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + if(status == HAL_OK) + { + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + + /* Wait for last operation to be completed on Bank 1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + /* if the erase operation is completed, disable the Bank1 BER Bit */ + FLASH->CR1 &= (~FLASH_CR_BER); + } +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + /* if the erase operation is completed, disable the Bank2 BER Bit */ + FLASH->CR2 &= (~FLASH_CR_BER); + } +#endif /* DUAL_BANK */ + } + else + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + /* Erase by sector by sector to be done*/ + for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++) + { + FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange); + + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + } +#if defined (DUAL_BANK) + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + } +#endif /* DUAL_BANK */ + + if(status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector */ + *SectorError = sector_index; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed on Bank 1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ + } +#if defined (DUAL_BANK) + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Enable End of Operation and Error interrupts for Bank 2 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ + } +#endif /* DUAL_BANK */ + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + if(pEraseInit->Banks == FLASH_BANK_1) + { + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1; + } +#if defined (DUAL_BANK) + else if(pEraseInit->Banks == FLASH_BANK_2) + { + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2; + } +#endif /* DUAL_BANK */ + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE; + } + + FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + } + else + { + /* Erase by sector to be done */ +#if defined (DUAL_BANK) + if(pEraseInit->Banks == FLASH_BANK_1) + { + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2; + } +#else + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; +#endif /* DUAL_BANK */ + + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = pEraseInit->VoltageRange; + + /* Erase first sector and wait for IT */ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange); + } + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } +#if defined (DUAL_BANK) + else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } +#endif /* DUAL_BANK */ + else + { + status = HAL_OK; + } + + if(status == HAL_OK) + { + /*Write protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + + if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks); + } + else + { + /*Disable of Write protection on the selected Sector*/ + FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) + { + /* Configure the Read protection level */ + FLASH_OB_RDPConfig(pOBInit->RDPLevel); + } + + /* User Configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Configure the user option bytes */ + FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); + } + + /* PCROP Configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) + { + assert_param(IS_FLASH_BANK(pOBInit->Banks)); + + /*Configure the Proprietary code readout protection */ + FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks); + } + + /* BOR Level configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + +#if defined(DUAL_CORE) + /* CM7 Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD) + { + FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + } + + /* CM4 Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD) + { + FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1); + } +#else /* Single Core*/ + /* Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD) + { + FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + } +#endif /*DUAL_CORE*/ + + /* Secure area configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA) + { + FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks); + } + +#if defined(FLASH_OTPBL_LOCKBL) + /* OTP Block Lock configuration */ + if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK) + { + FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock); + } +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined(FLASH_OPTSR2_TCM_AXI_SHARED) + /* TCM / AXI Shared RAM configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM) + { + FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig); + } +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined(FLASH_OPTSR2_CPUFREQ_BOOST) + /* CPU Frequency Boost configuration */ + if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST) + { + FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState); + } +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2, + * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR); + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + +#if defined (DUAL_BANK) + if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) +#else + if (pOBInit->Banks == FLASH_BANK_1) +#endif /* DUAL_BANK */ + { + pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA); + + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks); + + /* Get the Proprietary code readout protection */ + FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks); + + /*Get Bank Secure area*/ + FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks); + } + + /*Get Boot Address*/ + FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1)); +#if defined(DUAL_CORE) + pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD; + + /*Get CM4 Boot Address*/ + FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1)); +#else + pOBInit->OptionType |= OPTIONBYTE_BOOTADD; +#endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) + pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK; + + /* Get OTP Block Lock */ + pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock(); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM; + + /* Get TCM / AXI Shared RAM */ + pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig(); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST; + + /* Get CPU Frequency Boost */ + pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost(); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ +} + +/** + * @brief Unlock the FLASH Bank1 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void) +{ + if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank1 Registers access */ + WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH Bank1 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */ + SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + return HAL_OK; +} + +#if defined (DUAL_BANK) +/** + * @brief Unlock the FLASH Bank2 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void) +{ + if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH Bank2 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */ + SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + return HAL_OK; +} +#endif /* DUAL_BANK */ + +/* + * @brief Perform a CRC computation on the specified FLASH memory area + * @param pCRCInit pointer to an FLASH_CRCInitTypeDef structure that + * contains the configuration information for the CRC computation. + * @note CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7 + * @note The application should avoid running a CRC on PCROP or secure-only + * user Flash memory area since it may alter the expected CRC value. + * A special error flag (CRC read error: CRCRDERR) can be used to + * detect such a case. + * @retval HAL Status +*/ +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result) +{ + HAL_StatusTypeDef status; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank)); + assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC)); + + /* Wait for OB change operation to be completed */ + status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (pCRCInit->Bank == FLASH_BANK_1) + { + /* Enable CRC feature */ + FLASH->CR1 |= FLASH_CR_CRC_EN; + + /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + + /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */ + FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + + if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + { + /* Clear sectors list */ + FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT; + + /* Select CRC sectors */ + for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++) + { + FLASH_CRC_AddSector(sector_index, FLASH_BANK_1); + } + } + else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + { + /* Enable Bank 1 CRC select bit */ + FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK; + } + else + { + /* Select CRC start and end addresses */ + FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1); + } + + /* Start the CRC calculation */ + FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC; + + /* Wait on CRC busy flag */ + status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + + /* Return CRC result */ + (*CRC_Result) = FLASH->CRCDATA; + + /* Disable CRC feature */ + FLASH->CR1 &= (~FLASH_CR_CRC_EN); + + /* Clear CRC flags */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1); + } +#if defined (DUAL_BANK) + else + { + /* Enable CRC feature */ + FLASH->CR2 |= FLASH_CR_CRC_EN; + + /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + + /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */ + FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + + if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + { + /* Clear sectors list */ + FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT; + + /* Add CRC sectors */ + for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++) + { + FLASH_CRC_AddSector(sector_index, FLASH_BANK_2); + } + } + else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + { + /* Enable Bank 2 CRC select bit */ + FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK; + } + else + { + /* Select CRC start and end addresses */ + FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2); + } + + /* Start the CRC calculation */ + FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC; + + /* Wait on CRC busy flag */ + status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + + /* Return CRC result */ + (*CRC_Result) = FLASH->CRCDATA; + + /* Disable CRC feature */ + FLASH->CR2 &= (~FLASH_CR_CRC_EN); + + /* Clear CRC flags */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2); + } +#endif /* DUAL_BANK */ + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory + * @param VoltageRange The device program/erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ +#if defined (FLASH_CR_PSIZE) + assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ + assert_param(IS_FLASH_BANK(Banks)); + +#if defined (DUAL_BANK) + /* Flash Mass Erase */ + if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange for Bank1 and Bank2 */ + FLASH->CR1 &= (~FLASH_CR_PSIZE); + FLASH->CR2 &= (~FLASH_CR_PSIZE); + + /* Set voltage range */ + FLASH->CR1 |= VoltageRange; + FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Set Mass Erase Bit */ + FLASH->OPTCR |= FLASH_OPTCR_MER; + } + else +#endif /* DUAL_BANK */ + { + /* Proceed to erase Flash Bank */ + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank1 */ + FLASH->CR1 &= (~FLASH_CR_PSIZE); + FLASH->CR1 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Erase Bank1 */ + FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank2 */ + FLASH->CR2 &= (~FLASH_CR_PSIZE); + FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Erase Bank2 */ + FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); + } +#endif /* DUAL_BANK */ + } +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * This parameter can be a value of @ref FLASH_Sectors + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * @param VoltageRange The device program/erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) +{ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); +#if defined (FLASH_CR_PSIZE) + assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank1 */ + FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + + FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank1 */ + FLASH->CR1 &= ~(FLASH_CR_SNB); + + FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank2 */ + FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + + FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank2 */ + FLASH->CR2 &= ~(FLASH_CR_SNB); + + FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: enable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: enable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors + * + * @retval HAL FLASH State + */ +static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Enable Write Protection for bank 1 */ + FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN)); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Enable Write Protection for bank 2 */ + FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN)); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sector(s) to disable write protection. + * This parameter can be one of the following values: + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: disable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: disable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors + * + * @retval HAL FLASH State + */ +static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Disable Write Protection for bank 1 */ + FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Disable Write Protection for bank 2 */ + FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get the write protection of the given bank 1 or bank 2 sectors + * @param WRPState gives the write protection state on the given bank. + * This parameter can be one of the following values: + * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE + + * @param WRPSector gives the write protected sector(s) on the given bank . + * This parameter can be one of the following values: + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL + * + * @param Bank the specific bank to apply WRP sectors + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: Get bank1 WRP sectors + * @arg FLASH_BANK_2: Get bank2 WRP sectors + * @arg FLASH_BANK_BOTH: note allowed in this functions + * + * @retval HAL FLASH State + */ +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank) +{ + uint32_t regvalue = 0U; + + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->WPSN_CUR1; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->WPSN_CUR2; + } +#endif /* DUAL_BANK */ + + (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN; + + if(*WRPSector == 0U) + { + (*WRPState) = OB_WRPSTATE_DISABLE; + } + else + { + (*WRPState) = OB_WRPSTATE_ENABLE; + } +} + +/** + * @brief Set the read protection level. + * + * @note To configure the RDP level, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the RDP level, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * to go back to level 1 or 0 !!! + * + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @retval HAL status + */ +static void FLASH_OB_RDPConfig(uint32_t RDPLevel) +{ + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel); +} + +/** + * @brief Get the read protection level. + * @retval RDPLevel specifies the read protection level. + * This return value can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdp_level; + } +} + +#if defined(DUAL_CORE) +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param UserType The FLASH User Option Bytes to be modified : + * a combination of @ref FLASHEx_OB_USER_Type + * + * @param UserConfig The FLASH User Option Bytes values: + * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), + * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + * + * @retval HAL status + */ +#else +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param UserType The FLASH User Option Bytes to be modified : + * a combination of @arg FLASHEx_OB_USER_Type + * + * @param UserConfig The FLASH User Option Bytes values: + * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + * + * @retval HAL status + */ +#endif /*DUAL_CORE*/ +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) +{ + uint32_t optr_reg_val = 0; + uint32_t optr_reg_mask = 0; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + + if((UserType & OB_USER_IWDG1_SW) != 0U) + { + /* IWDG_HW option byte should be modified */ + assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW)); + + /* Set value and mask for IWDG_HW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW); + optr_reg_mask |= FLASH_OPTSR_IWDG1_SW; + } +#if defined(DUAL_CORE) + if((UserType & OB_USER_IWDG2_SW) != 0U) + { + /* IWDG2_SW option byte should be modified */ + assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW)); + + /* Set value and mask for IWDG2_SW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW); + optr_reg_mask |= FLASH_OPTSR_IWDG2_SW; + } +#endif /*DUAL_CORE*/ + if((UserType & OB_USER_NRST_STOP_D1) != 0U) + { + /* NRST_STOP option byte should be modified */ + assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1)); + + /* Set value and mask for NRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1); + optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1; + } + + if((UserType & OB_USER_NRST_STDBY_D1) != 0U) + { + /* NRST_STDBY option byte should be modified */ + assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1)); + + /* Set value and mask for NRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1); + optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1; + } + + if((UserType & OB_USER_IWDG_STOP) != 0U) + { + /* IWDG_STOP option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP)); + + /* Set value and mask for IWDG_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP); + optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP; + } + + if((UserType & OB_USER_IWDG_STDBY) != 0U) + { + /* IWDG_STDBY option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY)); + + /* Set value and mask for IWDG_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY); + optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY; + } + + if((UserType & OB_USER_ST_RAM_SIZE) != 0U) + { + /* ST_RAM_SIZE option byte should be modified */ + assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE)); + + /* Set value and mask for ST_RAM_SIZE option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE); + optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE; + } + + if((UserType & OB_USER_SECURITY) != 0U) + { + /* SECURITY option byte should be modified */ + assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY)); + + /* Set value and mask for SECURITY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY); + optr_reg_mask |= FLASH_OPTSR_SECURITY; + } + +#if defined(DUAL_CORE) + if((UserType & OB_USER_BCM4) != 0U) + { + /* BCM4 option byte should be modified */ + assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4)); + + /* Set value and mask for BCM4 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4); + optr_reg_mask |= FLASH_OPTSR_BCM4; + } + + if((UserType & OB_USER_BCM7) != 0U) + { + /* BCM7 option byte should be modified */ + assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7)); + + /* Set value and mask for BCM7 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7); + optr_reg_mask |= FLASH_OPTSR_BCM7; + } +#endif /* DUAL_CORE */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) + if((UserType & OB_USER_NRST_STOP_D2) != 0U) + { + /* NRST_STOP option byte should be modified */ + assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2)); + + /* Set value and mask for NRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2); + optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2; + } + + if((UserType & OB_USER_NRST_STDBY_D2) != 0U) + { + /* NRST_STDBY option byte should be modified */ + assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2)); + + /* Set value and mask for NRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2); + optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2; + } +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) + if((UserType & OB_USER_SWAP_BANK) != 0U) + { + /* SWAP_BANK_OPT option byte should be modified */ + assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT)); + + /* Set value and mask for SWAP_BANK_OPT option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT); + optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT; + } +#endif /* DUAL_BANK */ + + if((UserType & OB_USER_IOHSLV) != 0U) + { + /* IOHSLV_OPT option byte should be modified */ + assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV)); + + /* Set value and mask for IOHSLV_OPT option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV); + optr_reg_mask |= FLASH_OPTSR_IO_HSLV; + } + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) + if((UserType & OB_USER_VDDMMC_HSLV) != 0U) + { + /* VDDMMC_HSLV option byte should be modified */ + assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV)); + + /* Set value and mask for VDDMMC_HSLV option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV); + optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV; + } +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + + /* Configure the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val); +} + +#if defined(DUAL_CORE) +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values + * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), + * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + */ +#else +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values + * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + */ +#endif /*DUAL_CORE*/ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR); + userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP)); + + return userConfig; +} + +/** + * @brief Configure the Proprietary code readout protection of the desired addresses + * + * @note To configure the PCROP options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the PCROP options, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not + * when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal + * This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration + * + * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the bank + * + * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection + * This parameter can be an address between PCROPStartAddr and end of the bank + * + * @param Banks the specific bank to apply PCROP protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: PCROP on specified bank1 area + * @arg FLASH_BANK_2: PCROP on specified bank2 area + * @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks) + * + * @retval None + */ +static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_OB_PCROP_RDP(PCROPConfig)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr)); + + /* Configure the Proprietary code readout protection */ + FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8) | \ + (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ + PCROPConfig; + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr)); + + /* Configure the Proprietary code readout protection */ + FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8) | \ + (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ + PCROPConfig; + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get the Proprietary code readout protection configuration on a given Bank + * + * @param PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not + * when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal + * + * @param PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank + * + * @param PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank + * + * @param Bank the specific bank to apply PCROP protection + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: PCROP on specified bank1 area + * @arg FLASH_BANK_2: PCROP on specified bank2 area + * @arg FLASH_BANK_BOTH: is not allowed here + * + * @retval None + */ +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank) +{ + uint32_t regvalue = 0; + uint32_t bankBase = 0; + + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->PRAR_CUR1; + bankBase = FLASH_BANK1_BASE; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->PRAR_CUR2; + bankBase = FLASH_BANK2_BASE; + } +#endif /* DUAL_BANK */ + + (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP); + + (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase; + (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos; + (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V + * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V + * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V + * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V + * @retval None + */ +static void FLASH_OB_BOR_LevelConfig(uint32_t Level) +{ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Configure BOR_LEV option byte */ + MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level); +} + +/** + * @brief Get the BOR Level. + * @retval The Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V + * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V + * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V + * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V + */ +static uint32_t FLASH_OB_GetBOR(void) +{ + return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV); +} + +/** + * @brief Set Boot address + * @param BootOption Boot address option byte to be programmed, + * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION + (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) + * + * @param BootAddress0 Specifies the Boot Address 0 + * @param BootAddress1 Specifies the Boot Address 1 + * @retval HAL Status + */ +static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); + + if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress0)); + + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16)); +#else /* Single Core*/ + MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16)); +#endif /* DUAL_CORE */ + } + + if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress1)); + + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1); +#else /* Single Core*/ + MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1); +#endif /* DUAL_CORE */ + } +} + +/** + * @brief Get Boot address + * @param BootAddress0 Specifies the Boot Address 0. + * @param BootAddress1 Specifies the Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +{ + uint32_t regvalue; + +#if defined(DUAL_CORE) + regvalue = FLASH->BOOT7_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1); +#else /* Single Core */ + regvalue = FLASH->BOOT_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1); +#endif /* DUAL_CORE */ +} + +#if defined(DUAL_CORE) +/** + * @brief Set CM4 Boot address + * @param BootOption Boot address option byte to be programmed, + * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION + (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) + * + * @param BootAddress0 Specifies the CM4 Boot Address 0. + * @param BootAddress1 Specifies the CM4 Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); + + if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress0)); + + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16)); + + } + + if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress1)); + + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1); + } +} + +/** + * @brief Get CM4 Boot address + * @param BootAddress0 Specifies the CM4 Boot Address 0. + * @param BootAddress1 Specifies the CM4 Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +{ + uint32_t regvalue; + + regvalue = FLASH->BOOT4_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Set secure area configuration + * @param SecureAreaConfig specify if the secure area will be deleted or not + * when RDP level decreased from Level 1 to Level 0 or during a mass erase. + * + * @param SecureAreaStartAddr Specifies the secure area start address + * @param SecureAreaEndAddr Specifies the secure area end address + * @param Banks the specific bank to apply Security protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Secure area on specified bank1 area + * @arg FLASH_BANK_2: Secure area on specified bank2 area + * @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks) + * @retval None + */ +static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_OB_SECURE_RDP(SecureAreaConfig)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr)); + + /* Configure the secure area */ + FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8) | \ + (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ + (SecureAreaConfig & FLASH_SCAR_DMES); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr)); + + /* Configure the secure area */ + FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8) | \ + (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ + (SecureAreaConfig & FLASH_SCAR_DMES); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get secure area configuration + * @param SecureAreaConfig indicates if the secure area will be deleted or not + * when RDP level decreased from Level 1 to Level 0 or during a mass erase. + * @param SecureAreaStartAddr gives the secure area start address + * @param SecureAreaEndAddr gives the secure area end address + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank) +{ + uint32_t regvalue = 0; + uint32_t bankBase = 0; + + /* Check Bank parameter value */ + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->SCAR_CUR1; + bankBase = FLASH_BANK1_BASE; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->SCAR_CUR2; + bankBase = FLASH_BANK2_BASE; + } +#endif /* DUAL_BANK */ + + /* Get the secure area settings */ + (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES); + (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase; + (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos; + (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase; +} + +/** + * @brief Add a CRC sector to the list of sectors on which the CRC will be calculated + * @param Sector Specifies the CRC sector number + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + + if (Bank == FLASH_BANK_1) + { + /* Clear CRC sector */ + FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT); + + /* Select CRC Sector and activate ADD_SECT bit */ + FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT; + } +#if defined (DUAL_BANK) + else + { + /* Clear CRC sector */ + FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT); + + /* Select CRC Sector and activate ADD_SECT bit */ + FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT; + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Select CRC start and end memory addresses on which the CRC will be calculated + * @param CRCStartAddr Specifies the CRC start address + * @param CRCEndAddr Specifies the CRC end address + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank) +{ + if (Bank == FLASH_BANK_1) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr)); + + /* Write CRC Start and End addresses */ + FLASH->CRCSADD1 = CRCStartAddr; + FLASH->CRCEADD1 = CRCEndAddr; + } +#if defined (DUAL_BANK) + else + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr)); + + /* Write CRC Start and End addresses */ + FLASH->CRCSADD2 = CRCStartAddr; + FLASH->CRCEADD2 = CRCEndAddr; + } +#endif /* DUAL_BANK */ +} +/** + * @} + */ + +#if defined (FLASH_OTPBL_LOCKBL) +/** + * @brief Configure the OTP Block Lock. + * @param OTP_Block specifies the OTP Block to lock. + * This parameter can be a value of @ref FLASHEx_OTP_Blocks + * @retval None + */ +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block) +{ + /* Check the parameters */ + assert_param(IS_OTP_BLOCK(OTP_Block)); + + /* Configure the OTP Block lock in the option bytes register */ + FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL); +} + +/** + * @brief Get the OTP Block Lock. + * @retval OTP_Block specifies the OTP Block to lock. + * This return value can be a value of @ref FLASHEx_OTP_Blocks + */ +static uint32_t FLASH_OB_OTP_GetLock(void) +{ + return (FLASH->OTPBL_CUR); +} +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** + * @brief Configure the TCM / AXI Shared RAM. + * @param SharedRamConfig specifies the Shared RAM configuration. + * This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + * @retval None + */ +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig)); + + /* Configure the TCM / AXI Shared RAM in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig); +} + +/** + * @brief Get the TCM / AXI Shared RAM configuration. + * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration. + * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + */ +static uint32_t FLASH_OB_SharedRAM_GetConfig(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED); +} +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** + * @brief Configure the CPU Frequency Boost. + * @param FreqBoost specifies the CPU Frequency Boost state. + * This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + * @retval None + */ +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost)); + + /* Configure the CPU Frequency Boost in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost); +} + +/** + * @brief Get the CPU Frequency Boost state. + * @retval FreqBoost returns the CPU Frequency Boost state. + * This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + */ +static uint32_t FLASH_OB_CPUFreq_GetBoost(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST); +} +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c new file mode 100644 index 0000000..3580f78 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -0,0 +1,555 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#if defined(DUAL_CORE) +#define EXTI_CPU1 (0x01000000U) +#define EXTI_CPU2 (0x02000000U) +#endif /*DUAL_CORE*/ +#define GPIO_NUMBER (16U) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t temp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0x00U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + temp = EXTI_CurrentCPU->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->EMR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI_CurrentCPU->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->IMR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t tmp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position) ; + + if (iocurrent != 0x00U) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FUL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration for Current CPU */ + EXTI_CurrentCPU->IMR1 &= ~(iocurrent); + EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence*/ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ +#if defined(DUAL_CORE) && defined(CORE_CM4) + if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#else + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#endif +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c new file mode 100644 index 0000000..1d17bac --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c @@ -0,0 +1,447 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hsem.c + * @author MCD Application Team + * @brief HSEM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the semaphore peripheral: + * + Semaphore Take function (2-Step Procedure) , non blocking + * + Semaphore FastTake function (1-Step Procedure) , non blocking + * + Semaphore Status check + * + Semaphore Clear Key Set and Get + * + Release and release all functions + * + Semaphore notification enabling and disabling and callnack functions + * + IRQ handler management + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters : + (++) the semaphore ID from 0 to 31 + (++) the process ID from 0 to 255 + (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter : + (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero + (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter : + (++) the semaphore ID from 0_ID to 31 + (++) It returns 1 if the given semaphore is taken otherwise (Free) zero + (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters : + (++) the semaphore ID from 0 to 31 + (++) the process ID from 0 to 255: + (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt + may be generated when enabled (notification activated). If ProcessID or MasterID does not match, + semaphore remains taken (locked) + + (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All + This function takes as parameters : + (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by + HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions + (++) the Master ID: + (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds + to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the + Key or the MasterID doesn't match, semaphores remains taken (locked) + + (#)Semaphores Release all key functions: + (++) HAL_HSEM_SetClearKey() to set semaphore release all Key + (++) HAL_HSEM_GetClearKey() to get release all Key + (#)Semaphores notification functions : + (++) HAL_HSEM_ActivateNotification to activate a notification callback on + a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released + the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released + semaphores (bitfield). + + (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield). + (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask + Used by the notification functions + *** HSEM HAL driver macros list *** + ============================================= + [..] Below the list of most used macros in HSEM HAL driver. + + (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask. + [..] Example of use : + [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25). + [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example. + (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not. + (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags. + (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup HSEM HSEM + * @brief HSEM HAL module driver + * @{ + */ + +#ifdef HAL_HSEM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(DUAL_CORE) +/** @defgroup HSEM_Private_Constants HSEM Private Constants + * @{ + */ + +#ifndef HSEM_R_MASTERID +#define HSEM_R_MASTERID HSEM_R_COREID +#endif + +#ifndef HSEM_RLR_MASTERID +#define HSEM_RLR_MASTERID HSEM_RLR_COREID +#endif + +#ifndef HSEM_CR_MASTERID +#define HSEM_CR_MASTERID HSEM_CR_COREID +#endif + +/** + * @} + */ +#endif /* DUAL_CORE */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * +@verbatim + ============================================================================== + ##### HSEM Take and Release functions ##### + ============================================================================== +[..] This section provides functions allowing to: + (+) Take a semaphore with 2 Step method + (+) Fast Take a semaphore with 1 Step method + (+) Check semaphore state Taken or not + (+) Release a semaphore + (+) Release all semaphore at once + +@endverbatim + * @{ + */ + + +/** + * @brief Take a semaphore in 2 Step mode. + * @param SemID: semaphore ID from 0 to 31 + * @param ProcessID: Process ID from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + +#if USE_MULTI_CORE_SHARED_CODE != 0U + /* First step write R register with MasterID, processID and take bit=1*/ + HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK); + + /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */ + if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK)) + { + /*take success when MasterID and ProcessID match and take bit set*/ + return HAL_OK; + } +#else + /* First step write R register with MasterID, processID and take bit=1*/ + HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK); + + /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */ + if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK)) + { + /*take success when MasterID and ProcessID match and take bit set*/ + return HAL_OK; + } +#endif + + /* Semaphore take fails*/ + return HAL_ERROR; +} + +/** + * @brief Fast Take a semaphore with 1 Step mode. + * @param SemID: semaphore ID from 0 to 31 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + +#if USE_MULTI_CORE_SHARED_CODE != 0U + /* Read the RLR register to take the semaphore */ + if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK)) + { + /*take success when MasterID match and take bit set*/ + return HAL_OK; + } +#else + /* Read the RLR register to take the semaphore */ + if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK)) + { + /*take success when MasterID match and take bit set*/ + return HAL_OK; + } +#endif + + /* Semaphore take fails */ + return HAL_ERROR; +} +/** + * @brief Check semaphore state Taken or not. + * @param SemID: semaphore ID + * @retval HAL HSEM state + */ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID) +{ + return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL); +} + + +/** + * @brief Release a semaphore. + * @param SemID: semaphore ID from 0 to 31 + * @param ProcessID: Process ID from 0 to 255 + * @retval None + */ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + + /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */ +#if USE_MULTI_CORE_SHARED_CODE != 0U + HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID)); +#else + HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT); +#endif + +} + +/** + * @brief Release All semaphore used by a given Master . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @param CoreID: CoreID of the CPU that is using semaphores to be released + * @retval None + */ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID) +{ + assert_param(IS_HSEM_KEY(Key)); + assert_param(IS_HSEM_COREID(CoreID)); + + HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos)); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * +@verbatim + ============================================================================== + ##### HSEM Set and Get Key functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Set semaphore Key + (+) Get semaphore Key +@endverbatim + + * @{ + */ + +/** + * @brief Set semaphore Key . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @retval None + */ +void HAL_HSEM_SetClearKey(uint32_t Key) +{ + assert_param(IS_HSEM_KEY(Key)); + + MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos)); + +} + +/** + * @brief Get semaphore Key . + * @retval Semaphore Key , value from 0 to 0xFFFF + */ +uint32_t HAL_HSEM_GetClearKey(void) +{ + return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management + * @brief HSEM Notification functions. + * +@verbatim + ============================================================================== + ##### HSEM IRQ handler management and Notification functions ##### + ============================================================================== +[..] This section provides HSEM IRQ handler and Notification function. + +@endverbatim + * @{ + */ + +/** + * @brief Activate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_ActivateNotification(uint32_t SemMask) +{ +#if USE_MULTI_CORE_SHARED_CODE != 0U + /*enable the semaphore mask interrupts */ + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /*Use interrupt line 0 for CPU1 Master */ + HSEM->C1IER |= SemMask; + } + else /* HSEM_CPU2_COREID */ + { + /*Use interrupt line 1 for CPU2 Master*/ + HSEM->C2IER |= SemMask; + } +#else + HSEM_COMMON->IER |= SemMask; +#endif +} + +/** + * @brief Deactivate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask) +{ +#if USE_MULTI_CORE_SHARED_CODE != 0U + /*enable the semaphore mask interrupts */ + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /*Use interrupt line 0 for CPU1 Master */ + HSEM->C1IER &= ~SemMask; + } + else /* HSEM_CPU2_COREID */ + { + /*Use interrupt line 1 for CPU2 Master*/ + HSEM->C2IER &= ~SemMask; + } +#else + HSEM_COMMON->IER &= ~SemMask; +#endif +} + +/** + * @brief This function handles HSEM interrupt request + * @retval None + */ +void HAL_HSEM_IRQHandler(void) +{ + uint32_t statusreg; +#if USE_MULTI_CORE_SHARED_CODE != 0U + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /* Get the list of masked freed semaphores*/ + statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/ + + /*Disable Interrupts*/ + HSEM->C1IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM->C1ICR = ((uint32_t)statusreg); + } + else /* HSEM_CPU2_COREID */ + { + /* Get the list of masked freed semaphores*/ + statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/ + + /*Disable Interrupts*/ + HSEM->C2IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM->C2ICR = ((uint32_t)statusreg); + } +#else + /* Get the list of masked freed semaphores*/ + statusreg = HSEM_COMMON->MISR; + + /*Disable Interrupts*/ + HSEM_COMMON->IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM_COMMON->ICR = ((uint32_t)statusreg); + +#endif + /* Call FreeCallback */ + HAL_HSEM_FreeCallback(statusreg); +} + +/** + * @brief Semaphore Released Callback. + * @param SemMask: Mask of Released semaphores + * @retval None + */ +__weak void HAL_HSEM_FreeCallback(uint32_t SemMask) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(SemMask); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HSEM_FreeCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_HSEM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c new file mode 100644 index 0000000..c9ad0e7 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -0,0 +1,7268 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive stream or channel depends on Instance + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream or channel depends on Instance + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream or channel depends on Instance + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream or channel depends on Instance */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream or channel depends on Instance */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t treatdmaerror = 0U; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + if (hi2c->hdmatx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmaerror = 1U; + } + } + + if (hi2c->hdmarx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmaerror = 1U; + } + } + + /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */ + if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c new file mode 100644 index 0000000..d9b8e46 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32H7xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c new file mode 100644 index 0000000..089d9fb --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c @@ -0,0 +1,1899 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_mdma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Master Direct Memory Access (MDMA) peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the MDMA Channel + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and MDMA requests. + + (#) + For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters: + transfer request , channel priority, data endianness, Source increment, destination increment , + source data size, destination data size, data alignment, source Burst, destination Burst , + buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer + or full transfer) source and destination block address offset, mask address and data. + + If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node. + Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero. + Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position. + User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the + last node of the list to the first one in order to make the list circular. + In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init + + -@- The initial transfer itself (node 0 corresponding to the Init). + User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove + the connection between last node and first one. + + Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list. + When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops), + the linked list remains circular and node 2 becomes the first one. + Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user). + + [..] + (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be + transfer upon a request : + (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data + with BufferTransferLength defined within the HAL_MDMA_Init. + (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block + with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + or within the current linked list node parameters. + (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks + with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + or within the current linked list node parameters. + (++) MDMA_FULL_TRANSFER : each request triggers a full transfer + all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level + In this case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns + when the abort ends or timeout (should not be called from an interrupt service routine). + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the MDMA interrupt is configured. + (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of MDMA handle structure). + + (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately + then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel has effectively aborted. + (could be called from an interrupt service routine). + + (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks + from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferBufferCpltCallback : buffer transfer complete callback. + (++) XferBlockCpltCallback : block transfer complete callback. + (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + + [..] + (+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to + trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions: + (++) This function returns an error if used while the Transfer has ended or not started. + (++) If used while the current request has not been served yet (current request transfer on going) + this function returns an error and the new request is ignored. + + Generally this function should be used in conjunctions with the MDMA callbacks: + (++) example 1: + (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER + (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID) + (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data. + (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer + request using HAL_MDMA_GenerateSWRequest. + + (++) example 2: + (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER + (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID) + (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data. + (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask + for a new block transfer request using HAL_MDMA_GenerateSWRequest. + + [..] Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection. + + *** MDMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in MDMA HAL driver. + + (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel. + (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel. + (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags. + (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags. + (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts. + (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts. + (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the header file of the MDMA HAL driver for more useful macros. + + [..] + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup MDMA MDMA + * @brief MDMA HAL module driver + * @{ + */ + +#ifdef HAL_MDMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup MDMA_Private_Constants + * @{ + */ +#define HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */ +#define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup MDMA_Private_Functions_Prototypes + * @{ + */ +static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +static void MDMA_Init(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions + * @{ + */ + +/** @addtogroup MDMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to : + Initialize and de-initialize the MDMA channel. + Register and Unregister MDMA callbacks + [..] + The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in + reference manual. + The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel. + HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows + respectevely to register/unregister an MDMA callback function. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MDMA according to the specified + * parameters in the MDMA_InitTypeDef and create the associated handle. + * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance)); + assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority)); + assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness)); + assert_param(IS_MDMA_REQUEST(hmdma->Init.Request)); + assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc)); + assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc)); + assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize)); + assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize)); + assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment)); + assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst)); + assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst)); + assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength)); + assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); + + + /* Allocate lock resource */ + __HAL_UNLOCK(hmdma); + + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Check if the MDMA channel is effectively disabled */ + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) + { + /* Update error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT; + + /* Change the MDMA state */ + hmdma->State = HAL_MDMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the MDMA channel registers */ + MDMA_Init(hmdma); + + /* Reset the MDMA first/last linkedlist node addresses and node counter */ + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Initialize the MDMA state */ + hmdma->State = HAL_MDMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the MDMA peripheral + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma) +{ + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Disable the selected MDMA Channelx */ + __HAL_MDMA_DISABLE(hmdma); + + /* Reset MDMA Channel control register */ + hmdma->Instance->CCR = 0; + hmdma->Instance->CTCR = 0; + hmdma->Instance->CBNDTR = 0; + hmdma->Instance->CSAR = 0; + hmdma->Instance->CDAR = 0; + hmdma->Instance->CBRUR = 0; + hmdma->Instance->CLAR = 0; + hmdma->Instance->CTBR = 0; + hmdma->Instance->CMAR = 0; + hmdma->Instance->CMDR = 0; + + /* Clear all flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC)); + + /* Reset the MDMA first/last linkedlist node addresses and node counter */ + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Initialize the MDMA state */ + hmdma->State = HAL_MDMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return HAL_OK; +} + +/** + * @brief Config the Post request Mask address and Mask data + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param MaskAddress: specifies the address to be updated (written) with MaskData after a request is served. + * @param MaskData: specifies the value to be written to MaskAddress after a request is served. + * MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* if HW request set Post Request MaskAddress and MaskData, */ + if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U) + { + /* Set the HW request clear Mask and Data */ + hmdma->Instance->CMAR = MaskAddress; + hmdma->Instance->CMDR = MaskData; + + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + if(MaskAddress == 0U) + { + hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM; + } + else + { + hmdma->Instance->CTCR |= MDMA_CTCR_BWM; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @brief Register callbacks + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CallbackID: User Callback identifier + * @param pCallback: pointer to callbacsk function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + switch (CallbackID) + { + case HAL_MDMA_XFER_CPLT_CB_ID: + hmdma->XferCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + hmdma->XferBufferCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + hmdma->XferBlockCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + hmdma->XferRepeatBlockCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_ERROR_CB_ID: + hmdma->XferErrorCallback = pCallback; + break; + + case HAL_MDMA_XFER_ABORT_CB_ID: + hmdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CallbackID: User Callback identifier + * a HAL_MDMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + switch (CallbackID) + { + case HAL_MDMA_XFER_CPLT_CB_ID: + hmdma->XferCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + hmdma->XferBufferCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + hmdma->XferBlockCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + hmdma->XferRepeatBlockCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_ERROR_CB_ID: + hmdma->XferErrorCallback = NULL; + break; + + case HAL_MDMA_XFER_ABORT_CB_ID: + hmdma->XferAbortCallback = NULL; + break; + + case HAL_MDMA_XFER_ALL_CB_ID: + hmdma->XferCpltCallback = NULL; + hmdma->XferBufferCpltCallback = NULL; + hmdma->XferBlockCpltCallback = NULL; + hmdma->XferRepeatBlockCpltCallback = NULL; + hmdma->XferErrorCallback = NULL; + hmdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### Linked list operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Create a linked list node + (+) Add a node to the MDMA linked list + (+) Remove a node from the MDMA linked list + (+) Enable/Disable linked list circular mode +@endverbatim + * @{ + */ + +/** + * @brief Initializes an MDMA Link Node according to the specified + * parameters in the pMDMA_LinkedListNodeConfig . + * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * registers configurations. + * @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains + * the configuration information for the specified MDMA Linked List Node. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig) +{ + uint32_t addressMask; + uint32_t blockoffset; + + /* Check the MDMA peripheral state */ + if((pNode == NULL) || (pNodeConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority)); + assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness)); + assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc)); + assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc)); + assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize)); + assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize)); + assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment)); + assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst)); + assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst)); + assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength)); + assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset)); + + assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount)); + + + /* Configure next Link node Address Register to zero */ + pNode->CLAR = 0; + + /* Configure the Link Node registers*/ + pNode->CTBR = 0; + pNode->CMAR = 0; + pNode->CMDR = 0; + pNode->Reserved = 0; + + /* Write new CTCR Register value */ + pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \ + pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + pNodeConfig->Init.DestBurst | \ + ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + pNodeConfig->Init.TransferTriggerMode; + + /* If SW request set the CTCR register to SW Request Mode*/ + if(pNodeConfig->Init.Request == MDMA_REQUEST_SW) + { + pNode->CTCR |= MDMA_CTCR_SWRM; + } + + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U)) + { + pNode->CTCR |= MDMA_CTCR_BWM; + } + + /* Set the new CBNDTR Register value */ + pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC; + + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ + if(pNodeConfig->Init.SourceBlockAddressOffset < 0) + { + pNode->CBNDTR |= MDMA_CBNDTR_BRSUM; + /*write new CBRUR Register value : source repeat block offset */ + blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset); + pNode->CBRUR = blockoffset & 0x0000FFFFU; + } + else + { + /*write new CBRUR Register value : source repeat block offset */ + pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + } + + /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ + if(pNodeConfig->Init.DestBlockAddressOffset < 0) + { + pNode->CBNDTR |= MDMA_CBNDTR_BRDUM; + /*write new CBRUR Register value : destination repeat block offset */ + blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset); + pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + else + { + /*write new CBRUR Register value : destination repeat block offset */ + pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + + /* Configure MDMA Link Node data length */ + pNode->CBNDTR |= pNodeConfig->BlockDataLength; + + /* Configure MDMA Link Node destination address */ + pNode->CDAR = pNodeConfig->DstAddress; + + /* Configure MDMA Link Node Source address */ + pNode->CSAR = pNodeConfig->SrcAddress; + + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ + if(pNodeConfig->Init.Request != MDMA_REQUEST_SW) + { + /* Set the HW request in CTBR register */ + pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL; + /* Set the HW request clear Mask and Data */ + pNode->CMAR = pNodeConfig->PostRequestMaskAddress; + pNode->CMDR = pNodeConfig->PostRequestMaskData; + } + + addressMask = pNodeConfig->SrcAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHBSbus is used as source (read operation) on channel x */ + pNode->CTBR |= MDMA_CTBR_SBUS; + } + + addressMask = pNodeConfig->DstAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHB bus is used as destination (write operation) on channel x */ + pNode->CTBR |= MDMA_CTBR_DBUS; + } + + return HAL_OK; +} + +/** + * @brief Connect a node to the linked list. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * to be add to the list. + * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node + * at the end of the list + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode) +{ + MDMA_LinkNodeTypeDef *pNode; + uint32_t counter = 0, nodeInserted = 0; + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if((hmdma == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Check if this is the first node (after the Inititlization node) */ + if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) + { + if(pPrevNode == NULL) + { + /* if this is the first node after the initialization + connect this node to the node 0 by updating + the MDMA channel CLAR register to this node address */ + hmdma->Instance->CLAR = (uint32_t)pNewNode; + /* Set the MDMA handle First linked List node*/ + hmdma->FirstLinkedListNodeAddress = pNewNode; + + /*reset New node link */ + pNewNode->CLAR = 0; + + /* Update the Handle last node address */ + hmdma->LastLinkedListNodeAddress = pNewNode; + + hmdma->LinkedListNodeCounter = 1; + } + else + { + hal_status = HAL_ERROR; + } + } + else if(hmdma->FirstLinkedListNodeAddress != pNewNode) + { + /* Check if the node to insert already exists*/ + pNode = hmdma->FirstLinkedListNodeAddress; + while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK)) + { + if(pNode->CLAR == (uint32_t)pNewNode) + { + hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */ + } + pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + counter++; + } + + if(hal_status == HAL_OK) + { + /* Check if the previous node is the last one in the current list or zero */ + if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL)) + { + /* insert the new node at the end of the list */ + pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR; + hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; + /* Update the Handle last node address */ + hmdma->LastLinkedListNodeAddress = pNewNode; + /* Increment the linked list node counter */ + hmdma->LinkedListNodeCounter++; + } + else + { + /*insert the new node after the pPreviousNode node */ + pNode = hmdma->FirstLinkedListNodeAddress; + counter = 0; + while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U)) + { + counter++; + if(pNode == pPrevNode) + { + /*Insert the new node after the previous one */ + pNewNode->CLAR = pNode->CLAR; + pNode->CLAR = (uint32_t)pNewNode; + /* Increment the linked list node counter */ + hmdma->LinkedListNodeCounter++; + nodeInserted = 1; + } + else + { + pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + } + } + + if(nodeInserted == 0U) + { + hal_status = HAL_ERROR; + } + } + } + } + else + { + hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } +} + +/** + * @brief Disconnect/Remove a node from the transfer linked list. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * to be removed from the list. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode) +{ + MDMA_LinkNodeTypeDef *ptmpNode; + uint32_t counter = 0, nodeDeleted = 0; + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if((hmdma == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */ + { + /* Delete 1st node */ + if(hmdma->LastLinkedListNodeAddress == pNode) + { + /*if the last node is at the same time the first one (1 single node after the init node 0) + then update the last node too */ + + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + hmdma->Instance->CLAR = 0; + } + else + { + if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR) + { + /* if last node is looping to first (circular list) one update the last node connection */ + hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR; + } + + /* if deleting the first node after the initialization + connect the next node to the node 0 by updating + the MDMA channel CLAR register to this node address */ + hmdma->Instance->CLAR = pNode->CLAR; + hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + /* Update the Handle node counter */ + hmdma->LinkedListNodeCounter--; + } + } + else /* Deleting any other node */ + { + /*Deleted node is not the first one : find it */ + ptmpNode = hmdma->FirstLinkedListNodeAddress; + while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U)) + { + counter++; + if(ptmpNode->CLAR == ((uint32_t)pNode)) + { + /* if deleting the last node */ + if(pNode == hmdma->LastLinkedListNodeAddress) + { + /*Update the linked list last node address in the handle*/ + hmdma->LastLinkedListNodeAddress = ptmpNode; + } + /* update the next node link after deleting pMDMA_LinkedListNode */ + ptmpNode->CLAR = pNode->CLAR; + nodeDeleted = 1; + /* Update the Handle node counter */ + hmdma->LinkedListNodeCounter--; + } + else + { + ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR; + } + } + + if(nodeDeleted == 0U) + { + /* last node reashed without finding the node to delete : return error */ + hal_status = HAL_ERROR; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } +} + +/** + * @brief Make the linked list circular by connecting the last node to the first. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else + { + /* to enable circular mode Last Node should be connected to first node */ + hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; + } + + } + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; +} + +/** + * @brief Disable the linked list circular mode by setting the last node connection to null + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else + { + /* to disable circular mode Last Node should be connected to NULL */ + hmdma->LastLinkedListNodeAddress->CLAR = 0; + } + + } + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start MDMA transfer + (+) Configure the source, destination address and data length and + Start MDMA transfer with interrupt + (+) Abort MDMA transfer + (+) Poll for transfer complete + (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW) + (+) Handle MDMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the MDMA Transfer. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress : The source memory Buffer address + * @param DstAddress : The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount : The number of a blocks to be transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + /* Check the parameters */ + assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_MDMA_DISABLE(hmdma); + + /* Configure the source, destination address and the data length */ + MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); + + /* Enable the Peripheral */ + __HAL_MDMA_ENABLE(hmdma); + + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* activate If SW request mode*/ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Starts the MDMA Transfer with interrupts enabled. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress : The source memory Buffer address + * @param DstAddress : The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount : The number of a blocks to be transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + /* Check the parameters */ + assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_MDMA_DISABLE(hmdma); + + /* Configure the source, destination address and the data length */ + MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); + + /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC)); + + if(hmdma->XferBlockCpltCallback != NULL) + { + /* if Block transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT); + } + + if(hmdma->XferRepeatBlockCpltCallback != NULL) + { + /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT); + } + + if(hmdma->XferBufferCpltCallback != NULL) + { + /* if buffer transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC); + } + + /* Enable the Peripheral */ + __HAL_MDMA_ENABLE(hmdma); + + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* activate If SW request mode*/ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Aborts the MDMA Transfer. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * + * @note After disabling a MDMA Channel, a check for wait until the MDMA Channel is + * effectively disabled is added. If a Channel is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Channel will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); + + /* Disable the channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Check if the MDMA Channel is effectively disabled */ + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) + { + /* Update error code */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the MDMA state */ + hmdma->State = HAL_MDMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Clear all interrupt flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC)); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the MDMA state*/ + hmdma->State = HAL_MDMA_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Aborts the MDMA Transfer in Interrupt mode. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma) +{ + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + /* No transfer ongoing */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hmdma->State = HAL_MDMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_MDMA_DISABLE(hmdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CompleteLevel: Specifies the MDMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + uint32_t levelFlag, errorFlag; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + /* No transfer ongoing */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC : \ + (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ + (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \ + MDMA_FLAG_BRT); + + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U) + { + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) + { + /* Get the transfer error source flag */ + errorFlag = hmdma->Instance->CESR; + + if((errorFlag & MDMA_CESR_TED) == 0U) + { + /* Update error code : Read Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; + } + else + { + /* Update error code : Write Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + } + + if((errorFlag & MDMA_CESR_TEMD) != 0U) + { + /* Update error code : Error Mask Data */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; + } + + if((errorFlag & MDMA_CESR_TELD) != 0U) + { + /* Update error code : Error Linked list */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; + } + + if((errorFlag & MDMA_CESR_ASE) != 0U) + { + /* Update error code : Address/Size alignment error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; + } + + if((errorFlag & MDMA_CESR_BSE) != 0U) + { + /* Update error code : Block Size error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; + } + + (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */ + + /* + Note that the Abort function will + - Clear all transfer flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; + + (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */ + + /* + Note that the Abort function will + - Clear all transfer flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + } + } + } + + /* Clear the transfer level flag */ + if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); + + } + else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT)); + + } + else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT)); + } + else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC)); + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Generate an MDMA SW request trigger to activate the request on the given Channel. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma) +{ + uint32_t request_mode; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Get the softawre request mode */ + request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM; + + if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U) + { + /* if no Transfer on going (MDMA enable bit not set) return error */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U)) + { + /* if an MDMA ongoing request has not yet end or if request mode is not SW request return error */ + hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY; + + return HAL_ERROR; + } + else + { + /* Set the SW request bit to activate the request on the Channel */ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + + return HAL_OK; + } +} + +/** + * @brief Handles MDMA interrupt request. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval None + */ +void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) +{ + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600U; + + uint32_t generalIntFlag, errorFlag; + + /* General Interrupt Flag management ****************************************/ + generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU); + if((MDMA->GISR0 & generalIntFlag) == 0U) + { + return; /* the General interrupt flag for the current channel is down , nothing to do */ + } + + /* Transfer Error Interrupt management ***************************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U) + { + /* Disable the transfer error interrupt */ + __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE); + + /* Get the transfer error source flag */ + errorFlag = hmdma->Instance->CESR; + + if((errorFlag & MDMA_CESR_TED) == 0U) + { + /* Update error code : Read Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; + } + else + { + /* Update error code : Write Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + } + + if((errorFlag & MDMA_CESR_TEMD) != 0U) + { + /* Update error code : Error Mask Data */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; + } + + if((errorFlag & MDMA_CESR_TELD) != 0U) + { + /* Update error code : Error Linked list */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; + } + + if((errorFlag & MDMA_CESR_ASE) != 0U) + { + /* Update error code : Address/Size alignment error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; + } + + if((errorFlag & MDMA_CESR_BSE) != 0U) + { + /* Update error code : Block Size error error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; + } + + /* Clear the transfer error flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE); + } + } + + /* Buffer Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U) + { + /* Clear the buffer transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); + + if(hmdma->XferBufferCpltCallback != NULL) + { + /* Buffer transfer callback */ + hmdma->XferBufferCpltCallback(hmdma); + } + } + } + + /* Block Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT); + + if(hmdma->XferBlockCpltCallback != NULL) + { + /* Block transfer callback */ + hmdma->XferBlockCpltCallback(hmdma); + } + } + } + + /* Repeated Block Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U) + { + /* Clear the repeat block transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT); + + if(hmdma->XferRepeatBlockCpltCallback != NULL) + { + /* Repeated Block transfer callback */ + hmdma->XferRepeatBlockCpltCallback(hmdma); + } + } + } + + /* Channel Transfer Complete Interrupt management ***********************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U) + { + /* Disable all the transfer interrupts */ + __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); + + if(HAL_MDMA_STATE_ABORT == hmdma->State) + { + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the DMA state */ + hmdma->State = HAL_MDMA_STATE_READY; + + if(hmdma->XferAbortCallback != NULL) + { + hmdma->XferAbortCallback(hmdma); + } + return; + } + + /* Clear the Channel Transfer Complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_READY; + + if(hmdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hmdma->XferCpltCallback(hmdma); + } + } + } + + /* manage error case */ + if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE) + { + hmdma->State = HAL_MDMA_STATE_ABORT; + + /* Disable the channel */ + __HAL_MDMA_DISABLE(hmdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Change the MDMA state to error if MDMA disable fails */ + hmdma->State = HAL_MDMA_STATE_ERROR; + } + else + { + /* Change the MDMA state to Ready if MDMA disable success */ + hmdma->State = HAL_MDMA_STATE_READY; + } + + + if (hmdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hmdma->XferErrorCallback(hmdma); + } + } +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group4 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the MDMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the MDMA state. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL state + */ +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) +{ + return hmdma->State; +} + +/** + * @brief Return the MDMA error code + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval MDMA Error Code + */ +uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) +{ + return hmdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MDMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the MDMA Transfer parameter. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount: The number of blocks to be transferred + * @retval HAL status + */ +static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + uint32_t addressMask; + + /* Configure the MDMA Channel data length */ + MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT)); + + /* Configure the MDMA block repeat count */ + MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC); + + /* Clear all interrupt flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF); + + /* Configure MDMA Channel destination address */ + hmdma->Instance->CDAR = DstAddress; + + /* Configure MDMA Channel Source address */ + hmdma->Instance->CSAR = SrcAddress; + + addressMask = SrcAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHBSbus is used as source (read operation) on channel x */ + hmdma->Instance->CTBR |= MDMA_CTBR_SBUS; + } + else + { + /*The AXI bus is used as source (read operation) on channel x */ + hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS); + } + + addressMask = DstAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHB bus is used as destination (write operation) on channel x */ + hmdma->Instance->CTBR |= MDMA_CTBR_DBUS; + } + else + { + /*The AXI bus is used as destination (write operation) on channel x */ + hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS); + } + + /* Set the linked list register to the first node of the list */ + hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; +} + +/** + * @brief Initializes the MDMA handle according to the specified + * parameters in the MDMA_InitTypeDef + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval None + */ +static void MDMA_Init(MDMA_HandleTypeDef *hmdma) +{ + uint32_t blockoffset; + + /* Prepare the MDMA Channel configuration */ + hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness; + + /* Write new CTCR Register value */ + hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ + hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ + hmdma->Init.DestBurst | \ + ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + hmdma->Init.TransferTriggerMode; + + /* If SW request set the CTCR register to SW Request Mode */ + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM); + } + + /* Reset CBNDTR Register */ + hmdma->Instance->CBNDTR = 0; + + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ + if(hmdma->Init.SourceBlockAddressOffset < 0) + { + hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM; + /* Write new CBRUR Register value : source repeat block offset */ + blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset); + hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); + } + else + { + /* Write new CBRUR Register value : source repeat block offset */ + hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + } + + /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ + if(hmdma->Init.DestBlockAddressOffset < 0) + { + hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM; + /* Write new CBRUR Register value : destination repeat block offset */ + blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset); + hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + else + { + /*write new CBRUR Register value : destination repeat block offset */ + hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ + if(hmdma->Init.Request != MDMA_REQUEST_SW) + { + /* Set the HW request in CTRB register */ + hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL; + } + else /* SW request : reset the CTBR register */ + { + hmdma->Instance->CTBR = 0; + } + + /* Write Link Address Register */ + hmdma->Instance->CLAR = 0; +} + +/** + * @} + */ + +#endif /* HAL_MDMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c new file mode 100644 index 0000000..aeb9933 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c @@ -0,0 +1,873 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions. + * + Peripheral Control functions. + * + Interrupt Handling functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + In the H7 family, the number of power domains is different between + device lines. This difference is due to characteristics of each device. + + (#) Domain architecture overview for the different H7 lines: + (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757. + These devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals and a CPU + (Cortex-M4). The D3 domain contains the system control, I/O logic + and low-power peripherals. + (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753 + devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals. The D3 domains + contains the system control, I/O logic and low-power peripherals. + (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD). + The core domain (CD) contains a CPU (Cortex-M7), a Flash + memory and peripherals. The SmartRun domain contains the system + control, I/O logic and low-power peripherals. + + (#) Every entity have low power mode as described below : + (#) The CPU low power modes are : + (+) CPU CRUN. + (+) CPU CSLEEP. + (+) CPU CSTOP. + (#) The domain low power modes are : + (+) DRUN. + (+) DSTOP. + (+) DSTANDBY. + (#) The SYSTEM low power modes are : + (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from + Standby. In Run* mode, the performance is limited and the + system supply configuration shall be programmed. The system + enters Run mode only when the ACTVOSRDY bit in PWR control + status register 1 (PWR_CSR1) is set to 1. + (+) RUN. + (+) STOP. + (+) STANDBY. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Power management peripheral is active by default at startup level in + STM32h7xx lines. + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RTC registers, RTC backup + data registers and backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Power Voltage Detector, + then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start + and stop the PVD detection. + (+) PVD level could be one of the following values : + (++) 1V95 + (++) 2V1 + (++) 2V25 + (++) 2V4 + (++) 2V55 + (++) 2V7 + (++) 2V85 + (++) External voltage level + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High) and to enable and disable it. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP + mode. Wake-up from SLEEP mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in SLEEP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0 + mode for single core devices. For dual core devices, this API will enter + the domain (containing Cortex-Mx that executing this function) in DSTOP + mode. According to the used parameter, user could select the regulator to + be kept actif in low power mode and wake-up event type. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in CSTOP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + STANDBY mode for single core devices. For dual core devices, this API + will enter the domain (containing Cortex-Mx that executing this function) + in DSTANDBY mode. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-Mx re-entring in SLEEP mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-Mx to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt + request. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal + regulator output voltage. + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#if !defined (DUAL_CORE) +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#endif /* !defined (DUAL_CORE) */ + +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +#define PVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] + This section provides functions allowing to deinitialize power peripheral. + + [..] + After system reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit (void) +{ +} + +/** + * @brief Enable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess (void) +{ + /* Enable access to RTC and backup registers */ + SET_BIT (PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None. + */ +void HAL_PWR_DisableBkUpAccess (void) +{ + /* Disable access to RTC and backup registers */ + CLEAR_BIT (PWR->CR1, PWR_CR1_DBP); +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Power Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control Functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power peripheral. + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 + register). + + (+) A PVDO flag is available to indicate if VDD is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + + (+) The PVD is stopped in STANDBY mode. + + *** Wake-up pin configuration *** + ================================= + [..] + (+) Wake-up pin is used to wake up the system from STANDBY mode. + The pin pull is configurable through the WKUPEPR register to be in + No-pull, Pull-up and Pull-down. + The pin polarity is configurable through the WKUPEPR register to be + active on rising or falling edges. + + (+) There are up to six Wake-up pin in the STM32H7 devices family. + + *** Low Power modes configuration *** + ===================================== + [..] + The device present 3 principles low-power modes features: + (+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining + active (Powered and Clocked). + + (+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the + regulator is running. The Main regulator or the LP + regulator could be selected. + + (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE + supply regulator is powered off. + + *** SLEEP mode *** + ================== + [..] + (+) Entry: + The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, + SLEEPEntry) function. + + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction. + + -@@- The Regulator parameter is not used for the STM32H7 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from SLEEP mode. + + *** STOP mode *** + ================= + [..] + In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL, + the HSI, and the HSE RC oscillators are disabled. Internal SRAM and + register contents are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption in STOP mode, FLASH can be powered off before + entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the STOP mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, + STOPEntry) function with: + + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON: Main regulator ON. + (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction. + + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** STANDBY mode *** + ==================== + [..] + (+) + The system STANDBY mode allows to achieve the lowest power consumption. + It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator + disabled. The system is consequently powered off. The PLL, the HSI + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the RTC registers, RTC backup registers, + backup SRAM and standby circuitry. + + [..] + The voltage regulator is OFF. + + (++) Entry: + (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), + RTC wakeup, tamper event, time stamp event, external reset in NRST + pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an + RTC Wakeup event, a tamper event or a time-stamp event, without + depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes + + (++) To wake up from the STOP mode with an RTC alarm event, it is + necessary to configure the RTC to generate the RTC alarm using the + HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the STOP mode with an RTC Tamper or time stamp event, + it is necessary to configure the RTC to detect the tamper or time + stamp event using the HAL_RTCEx_SetTimeStamp_IT() or + HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the STOP mode with an RTC WakeUp event, it is + necessary to configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Programmable Voltage Detector(PVD). + * @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains + * the configuration information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. + * @retval None. + */ +void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the PVD configuration parameter */ + if (sConfigPVD == NULL) + { + return; + } + + /* Check the parameters */ + assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); + assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + + /* Clear previous config */ +#if !defined (DUAL_CORE) + __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_PVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); + +#if !defined (DUAL_CORE) + /* Interrupt mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT (); + } + + /* Event mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); + } +#endif /* !defined (DUAL_CORE) */ + + /* Rising edge configuration */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); + } + + /* Falling edge configuration */ + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); + } +} + +/** + * @brief Enable the Programmable Voltage Detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD (void) +{ + /* Enable the power voltage detector */ + SET_BIT (PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Disable the Programmable Voltage Detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD (void) +{ + /* Disable the power voltage detector */ + CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which + * sets the default (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity)); + + /* + Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge). + */ + MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity); +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, + * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. + * @retval None. + */ +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx)); + + /* Disable the wake up pin selected */ + CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); +} + +/** + * @brief Enter the current core in SLEEP mode (CSLEEP). + * @param Regulator : Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power + * regulator ON. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with the lower power + * families. + * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction. + * @note Ensure to clear pending events before calling this API through + * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } +} + +/** + * @brief Enter STOP mode. + * @note For single core devices, this API will enter the system in STOP mode + * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is + * cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTOP mode. If all + * Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is + * cleared, all the system will enter in STOP mode. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @note In System STOP mode, all I/O pins keep the same state as in Run mode. + * @note When exiting System STOP mode by issuing an interrupt or a wakeup + * event, the HSI RC oscillator is selected as default system wakeup + * clock. + * @note In System STOP mode, when the voltage regulator operates in low + * power mode, an additional startup delay is incurred when the system + * is waking up. By keeping the internal regulator ON during STOP mode, + * the consumption is higher although the startup time is reduced. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + + /* Select the regulator state in STOP mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + } + else + { + /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + } +#else /* Single core devices */ + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select STOP mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enter STANDBY mode. + * @note For single core devices, this API will enter the system in STANDBY + * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR + * register is cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTANDBY mode. If all + * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register + * is cleared, all the system will enter in STANDBY mode. + * @note The system enters Standby mode only when all domains are in DSTANDBY. + * @note When the System exit STANDBY mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock. + * @note It is recommended to disable all regulators before entring STANDBY + * mode for power consumption saving purpose. + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode (void) +{ + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3)); + } + else + { + /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3)); + } +#else /* Single core devices */ + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores(); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); +} + +/** + * @brief Indicate Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit (void) +{ + /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit (void) +{ + /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEVONPEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-Mx. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend (void) +{ + /* Set SEVONPEND bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-Mx. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend (void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions + * @brief Interrupt Handling functions + * +@verbatim + =============================================================================== + ##### Interrupt Handling Functions ##### + =============================================================================== + [..] + This section provides functions allowing to handle the PVD pending + interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None. + */ +void HAL_PWR_PVD_IRQHandler (void) +{ +#if defined (DUAL_CORE) + /* Check Cortex-Mx ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Check PWR EXTI D1 flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* Clear PWR EXTI D1 pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } + } + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) + { + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_PVD_EXTID2_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } + } +#else /* Single core devices */ + /* PVD EXTI line interrupt detected */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* Clear PWR EXTI pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } +#endif /* defined (DUAL_CORE) */ +} + +/** + * @brief PWR PVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_PVDCallback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c new file mode 100644 index 0000000..5d51ceb --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c @@ -0,0 +1,2142 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply + with the following different setups according to hardware (support SMPS): + (+) PWR_DIRECT_SMPS_SUPPLY + (+) PWR_SMPS_1V8_SUPPLIES_LDO + (+) PWR_SMPS_2V5_SUPPLIES_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT + (+) PWR_SMPS_2V5_SUPPLIES_EXT + (+) PWR_LDO_SUPPLY + (+) PWR_EXTERNAL_SOURCE_SUPPLY + + (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup. + + (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main + internal regulator output voltage. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_VOLTAGE_SCALE0 + (+) PWR_REGULATOR_VOLTAGE_SCALE1 + (+) PWR_REGULATOR_VOLTAGE_SCALE2 + (+) PWR_REGULATOR_VOLTAGE_SCALE3 + + (#) Call HAL_PWREx_GetVoltageRange() function to get the current output + voltage applied to the main regulator. + + (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the + main internal regulator output voltage in STOP mode. The voltage scaling + in STOP mode could be one of the following scales : + (+) PWR_REGULATOR_SVOS_SCALE3 + (+) PWR_REGULATOR_SVOS_SCALE4 + (+) PWR_REGULATOR_SVOS_SCALE5 + + (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current + output voltage applied to the main regulator in STOP mode. + + (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode + with core domain in D2STOP mode. This API is used only for STM32H7Axxx + and STM32H7Bxxx devices. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in + DSTOP mode. Call this API with all available power domains to enter the + system in STOP mode. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the + Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry. + + (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain + in DSTANDBY mode. Call this API with all available power domains to enter + the system in STANDBY mode. + + (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state + (RUN/STOP) when the system enter to low power mode. + + (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the + selected power domain. This API is used only for dual core devices. + + (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold + and release the selected CPU and and their domain peripherals when + exiting STOP mode. These APIs are used only for dual core devices. + + (#) Call HAL_PWREx_EnableFlashPowerDown() and + HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the + Flash Power Down in STOP mode. + + (#) Call HAL_PWREx_EnableMemoryShutOff() and + HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the + memory block shut-off in DStop or DStop2. These APIs are used only for + STM32H7Axxx and STM32H7Bxxx lines. + + (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin() + functions to enable and disable the Wake-up pin functionality for + the selected pin. + + (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag() + functions to manage wake-up flag for the selected pin. + + (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up + pins interrupts. + + (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions + to enable and disable the backup domain regulator. + + (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(), + HAL_PWREx_EnableUSBVoltageDetector() and + HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power + regulation functionalities. + + (#) Call HAL_PWREx_EnableBatteryCharging() and + HAL_PWREx_DisableBatteryCharging() functions to enable and disable the + battery charging feature with the selected resistor. + + (#) Call HAL_PWREx_EnableAnalogBooster() and + HAL_PWREx_DisableAnalogBooster() functions to enable and disable the + AVD boost feature when the VDD supply voltage is below 2V7. + + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() + functions to enable and disable the VBAT and Temperature monitoring. + When VBAT and Temperature monitoring feature is enables, use + HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get + respectively the Temperature level and VBAT level. + + (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring() + function to get VDDMMC voltage level. This API is used only for + STM32H7Axxx and STM32H7Bxxx lines + + (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured + (event mode and voltage threshold) in order to set up the Analog Voltage + Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD() + functions to start and stop the AVD detection. + (+) AVD level could be one of the following values : + (++) 1V7 + (++) 2V1 + (++) 2V5 + (++) 2V8 + + (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and + AVD interrupt request. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Constants + * @{ + */ + +/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask + * @{ + */ +#define AVD_MODE_IT (0x00010000U) +#define AVD_MODE_EVT (0x00020000U) +#define AVD_RISING_EDGE (0x00000001U) +#define AVD_FALLING_EDGE (0x00000002U) +#define AVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value + * @{ + */ +#define PWR_FLAG_SETTING_DELAY (1000U) +/** + * @} + */ + +/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets + * @{ + */ +/* Wake-Up Pins EXTI register mask */ +#if defined (EXTI_IMR2_IM57) +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\ + EXTI_IMR2_IM59 | EXTI_IMR2_IM60) +#else +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM58 | EXTI_IMR2_IM60) +#endif /* defined (EXTI_IMR2_IM57) */ + +/* Wake-Up Pins PWR Pin Pull shift offsets */ +#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] + (#) When the system is powered on, the POR monitors VDD supply. Once VDD is + above the POR threshold level, the voltage regulator is enabled in the + default supply configuration: + (+) The Voltage converter output level is set at 1V0 in accordance with + the VOS3 level configured in PWR (D3/SRD) domain control register + (PWR_D3CR/PWR_SRDCR). + (+) The system is kept in reset mode as long as VCORE is not ok. + (+) Once VCORE is ok, the system is taken out of reset and the HSI + oscillator is enabled. + (+) Once the oscillator is stable, the system is initialized: Flash memory + and option bytes are loaded and the CPU starts in Run* mode. + (+) The software shall then initialize the system including supply + configuration programming using the HAL_PWREx_ConfigSupply(). + (+) Once the supply configuration has been configured, the + HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR + control status register 1 (PWR_CSR1) to guarantee a valid voltage + levels: + (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the + system is in limited Run* mode, write accesses to the RAMs are not + permitted and VOS shall not be changed. + (++) Once ACTVOSRDY indicates that voltage levels are valid, the system + is in normal Run mode, write accesses to RAMs are allowed and VOS + can be changed. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power + * Domains. The LDO is Bypassed. + * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power + * Domains. The SMPS regulator is Bypassed. + * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @note The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all + * H7 lines. + * The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO, + * PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO, + * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and + * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS + * regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param (IS_PWR_SUPPLY (SupplySource)); + + /* Check if supply source was configured */ +#if defined (PWR_FLAG_SCUEN) + if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) +#else + if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) +#endif /* defined (PWR_FLAG_SCUEN) */ + { + /* Check supply configuration */ + if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) + { + /* Supply configuration update locked, can't apply a new supply config */ + return HAL_ERROR; + } + else + { + /* Supply configuration update locked, but new supply configuration + matches with old supply configuration : nothing to do + */ + return HAL_OK; + } + } + + /* Set the power supply configuration */ + MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + +#if defined (SMPS) + /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ + if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) + { + /* Get the current tick number */ + tickstart = HAL_GetTick (); + + /* Wait till SMPS external supply ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } +#endif /* defined (SMPS) */ + + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configuration. + */ +uint32_t HAL_PWREx_GetSupplyConfig (void) +{ + return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK); +} + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling : Specifies the regulator output voltage to achieve + * a tradeoff between performance and power + * consumption. + * This parameter can be one of the following values : + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * range 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * range 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * range 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0. + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling)); + + /* Get the voltage scaling */ + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling) + { + /* Old and new voltage scaling configuration match : nothing to do */ + return HAL_OK; + } + +#if defined (PWR_SRDCR_VOS) + /* Set the voltage range */ + MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); +#else +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0) + { + if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN) + { + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + /* Enable the PWR overdrive */ + SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + } + else + { + /* The voltage scale 0 is only possible when LDO regulator is enabled */ + return HAL_ERROR; + } + } + else + { + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1) + { + if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U) + { + /* Disable the PWR overdrive */ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } + } + + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); + } +#else /* STM32H72xxx and STM32H73xxx lines */ + /* Set the voltage range */ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); +#endif /* defined (SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @retval The current applied VOS selection. + */ +uint32_t HAL_PWREx_GetVoltageRange (void) +{ + /* Get the active voltage scaling */ + return (PWR->CSR1 & PWR_CSR1_ACTVOS); +} + +/** + * @brief Configure the main internal regulator output voltage in STOP mode. + * @param VoltageScaling : Specifies the regulator output voltage when the + * system enters Stop mode to achieve a tradeoff between performance + * and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range + * 3 mode. + * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range + * 4 mode. + * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range + * 5 mode. + * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage + * regulator in Low-power (LP) mode to further reduce power consumption. + * When preselecting SVOS3, the use of the voltage regulator low-power + * mode (LP) can be selected by LPDS register bit. + * @note The selected SVOS4 and SVOS5 levels add an additional startup delay + * when exiting from system Stop mode. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling)); + + /* Return the stop mode voltage range */ + MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling); + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage in STOP mode. + * @retval The actual applied VOS selection. + */ +uint32_t HAL_PWREx_GetStopModeVoltageRange (void) +{ + /* Return the stop voltage scaling */ + return (PWR->CR1 & PWR_CR1_SVOS); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @brief Low power control functions + * +@verbatim + =============================================================================== + ##### Low power control functions ##### + =============================================================================== + + *** Domains Low Power modes configuration *** + ============================================= + [..] + This section provides the extended low power mode control APIs. + The system presents 3 principles domains (D1, D2 and D3) that can be + operated in low-power modes (DSTOP or DSTANDBY mode): + + (+) DSTOP mode to enters a domain to STOP mode: + (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU + subsystem is in CSTOP mode and has allocated peripheral in the + domain. + In DSTOP mode the domain bus matrix clock is stopped. + (++) The system enters STOP mode using one of the following scenarios: + (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains + enter DSTOP mode. + (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains + enter DSTOP mode. + (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains + enter DSTOP mode. + (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain + enters DSTOP mode. + (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain + enters DSTOP mode. + (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain + enters DSTOP mode. + (+++) D1, D2 and D3 domains enter DSTOP mode. + (++) When the system enters STOP mode, the clocks are stopped and the + regulator is running in main or low power mode. + (++) D3 domain can be kept in Run mode regardless of the CPU status when + enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function. + + (+) DSTANDBY mode to enters a domain to STANDBY mode: + (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control + register (PWR_CPUCR) for the Dn domain selects Standby mode. + (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter + DSTANDBY mode. Consequently the VCORE supply regulator is powered + off. + + *** DSTOP mode *** + ================== + [..] + In DStop mode the domain bus matrix clock is stopped. + The Flash memory can enter low-power Stop mode when it is enabled through + FLPS in PWR_CR1 register. This allows a trade-off between domain DStop + restart time and low power consumption. + [..] + In DStop mode domain peripherals using the LSI or LSE clock and + peripherals having a kernel clock request are still able to operate. + [..] + Before entering DSTOP mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. + + (+) Entry: + The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, + STOPEntry, Domain) function with: + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON : Main regulator ON. + (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction + (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction + (++) Domain: + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode. + + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** DSTANDBY mode *** + ===================== + [..] + In DStandby mode: + (+) The domain bus matrix clock is stopped. + (+) The domain is powered down and the domain RAM and register contents + are lost. + [..] + Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. + + (+) Entry: + The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode + (Domain) function with: + (++) Domain: + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode. + + (+) Exit: + WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + wakeup, tamper event, time stamp event, external reset in NRST pin, + IWDG reset. + + *** Keep D3/SRD in RUN mode *** + =============================== + [..] + D3/SRD domain can be kept in Run mode regardless of the CPU status when + entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function + with : + (+) D3State: + (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system + mode. + (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless + of CPU subsystem mode. + + *** FLASH Power Down configuration **** + ======================================= + [..] + By setting the FLPS bit in the PWR_CR1 register using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters + power down mode when the device enters STOP mode. When the Flash memory is + in power down mode, an additional startup delay is incurred when waking up + from STOP mode. + + *** Wakeup Pins configuration **** + =================================== + [..] + Wakeup pins allow the system to exit from Standby mode. The configuration + of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) + function with: + (+) sPinParams: structure to enable and configure a wakeup pin: + (++) WakeUpPin: Wakeup pin to be enabled. + (++) PinPolarity: Wakeup pin polarity (rising or falling edge). + (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down). + [..] + The wakeup pins are internally connected to the EXTI lines [55-60] to + generate an interrupt if enabled. The EXTI lines configuration is done by + the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c + file. + [..] + When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is + called and the appropriate flag is set in the PWR_WKUPFR register. Then in + the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be + cleared and the appropriate user callback will be called. The user can add + his own code by customization of function pointer HAL_PWREx_WKUPx_Callback. + +@endverbatim + * @{ + */ + +#if defined (PWR_CPUCR_RETDS_CD) +/** + * @brief Enter the system to STOP mode with main domain in DSTOP2. + * @note In STOP mode, the domain bus matrix clock is stalled. + * @note In STOP mode, memories and registers are maintained and peripherals + * in CPU domain are no longer operational. + * @note All clocks in the VCORE domain are stopped, the PLL, the HSI and the + * HSE oscillators are disabled. Only Peripherals that have wakeup + * capability can switch on the HSI to receive a frame, and switch off + * the HSI after receiving the frame if it is not a wakeup frame. In + * this case the HSI clock is propagated only to the peripheral + * requesting it. + * @note When exiting STOP mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in + * RCC_CFGR register is set. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @retval None. + */ +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + + /* Select the regulator state in Stop mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD); + + /* Keep DSTOP mode when SmartRun domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __ISB (); + __DSB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} +#endif /* defined (PWR_CPUCR_RETDS_CD) */ + +/** + * @brief Enter a Domain to DSTOP mode. + * @note This API gives flexibility to manage independently each domain STOP + * mode. For dual core lines, this API should be executed with the + * corresponding Cortex-Mx to enter domain to DSTOP mode. When it is + * executed by all available Cortex-Mx, the system enter to STOP mode. + * For single core lines, calling this API with domain parameter set to + * PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode + * independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the + * CPUCR_RUN_D3 is cleared. + * @note In DStop mode the domain bus matrix clock is stopped. + * @note The system D3/SRD domain enter Stop mode only when the CPU subsystem + * is in CStop mode, the EXTI wakeup sources are inactive and at least + * one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for + * any domain request Stop. + * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache + * function in order to clean the D-Cache and guarantee the data + * integrity for the SRAM memories. + * @note In System Stop mode, the domain peripherals that use the LSI or LSE + * clock, and the peripherals that have a kernel clock request to + * select HSI or CSI as source, are still able to operate. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @param Domain : Specifies the Domain to enter in DSTOP mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode. + * @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode. + * @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode. + * @retval None. + */ +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the regulator state in Stop mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Select the domain Power Down DeepSleep */ + if (Domain == PWR_D1_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ + + /* Keep DSTOP mode when D1/CD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + } +#if defined (PWR_CPUCR_PDDS_D2) + else if (Domain == PWR_D2_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } + + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +#else + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* defined (DUAL_CORE) */ + } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + else + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + } + else + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); + } +#else + /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief Clear pending event. + * @note This API clears the pending event in order to enter a given CPU + * to CSLEEP or CSTOP. It should be called just before APIs performing + * enter low power mode using Wait For Event request. + * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ClearPendingEvent (void) +{ +#if defined (DUAL_CORE) + /* Check the current Core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + __WFE (); + } + else + { + __SEV (); + __WFE (); + } +#else + __WFE (); +#endif /* defined (DUAL_CORE) */ +} + +/** + * @brief Enter a Domain to DSTANDBY mode. + * @note This API gives flexibility to manage independently each domain + * STANDBY mode. For dual core lines, this API should be executed with + * the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When + * it is executed by all available Cortex-Mx, the system enter STANDBY + * mode. + * For single core lines, calling this API with D1/SRD the selected + * domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0 + * and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1. + * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for + * the Dn domain select Standby mode. When the system enters Standby + * mode, the voltage regulator is disabled. + * @note When D2 or D3 domain is in DStandby mode and the CPU sets the + * domain PDDS_Dn bit to select Stop mode, the domain remains in + * DStandby mode. The domain will only exit DStandby when the CPU + * allocates a peripheral in the domain. + * @note The system D3/SRD domain enters Standby mode only when the D1 and D2 + * domain are in DStandby. + * @note Before entering DSTANDBY mode it is recommended to call + * SCB_CleanDCache function in order to clean the D-Cache and guarantee + * the data integrity for the SRAM memories. + * @param Domain : Specifies the Domain to enter to STANDBY mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode. + * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode. + * @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode. + * @retval None + */ +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain) +{ + /* Check the parameters */ + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the domain Power Down DeepSleep */ + if (Domain == PWR_D1_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ + + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1); + +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1); +#endif /*DUAL_CORE*/ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); + } +#if defined (PWR_CPUCR_PDDS_D2) + else if (Domain == PWR_D2_DOMAIN) + { + /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2); + +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } + + /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); +#endif /* defined (DUAL_CORE) */ + } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + else + { + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief Configure the D3/SRD Domain state when the System in low power mode. + * @param D3State : Specifies the D3/SRD state. + * This parameter can be one of the following values : + * @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep + * CPU sub-system low power mode. + * @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode + * regardless of the CPU sub-system low + * power mode. + * @retval None + */ +void HAL_PWREx_ConfigD3Domain (uint32_t D3State) +{ + /* Check the parameter */ + assert_param (IS_D3_STATE (D3State)); + + /* Keep D3/SRD in run mode */ + MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); +} + +#if defined (DUAL_CORE) +/** + * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a + * given domain. + * @param DomainFlags : Specifies the Domain flags to be cleared. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags. + * @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags. + * @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags. + * @retval None. + */ +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags) +{ + /* Check the parameter */ + assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags)); + + /* D1 CPU flags */ + if (DomainFlags == PWR_D1_DOMAIN_FLAGS) + { + /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + } + /* D2 CPU flags */ + else if (DomainFlags == PWR_D2_DOMAIN_FLAGS) + { + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); + } + else + { + /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); + } +} + +/** + * @brief Hold the CPU and their domain peripherals when exiting STOP mode. + * @param CPU : Specifies the core to be held. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master. + * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param (IS_PWR_CORE (CPU)); + + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) + { + /* If CPU1 is not held */ + if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1) + { + /* Set HOLD2 bit */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); + } + else + { + status = HAL_ERROR; + } + } + else + { + /* If CPU2 is not held */ + if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2) + { + /* Set HOLD1 bit */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Release the CPU and their domain peripherals after a wake-up from + * STOP mode. + * @param CPU: Specifies the core to be released. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU1: Release the CPU1 and their domain + * peripherals from holding. + * @arg PWR_CORE_CPU2: Release the CPU2 and their domain + * peripherals from holding. + * @retval None + */ +void HAL_PWREx_ReleaseCore (uint32_t CPU) +{ + /* Check the parameters */ + assert_param (IS_PWR_CORE (CPU)); + + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) + { + /* Reset HOLD2 bit */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); + } + else + { + /* Reset HOLD1 bit */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); + } +} +#endif /* defined (DUAL_CORE) */ + + +/** + * @brief Enable the Flash Power Down in Stop mode. + * @note When Flash Power Down is enabled the Flash memory enters low-power + * mode when D1/SRD domain is in DStop mode. This feature allows to + * obtain the best trade-off between low-power consumption and restart + * time when exiting from DStop mode. + * @retval None. + */ +void HAL_PWREx_EnableFlashPowerDown (void) +{ + /* Enable the Flash Power Down */ + SET_BIT (PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop mode. + * @note When Flash Power Down is disabled the Flash memory is kept on + * normal mode when D1/SRD domain is in DStop mode. This feature allows + * to obtain the best trade-off between low-power consumption and + * restart time when exiting from DStop mode. + * @retval None. + */ +void HAL_PWREx_DisableFlashPowerDown (void) +{ + /* Disable the Flash Power Down */ + CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS); +} + +#if defined (PWR_CR1_SRDRAMSO) +/** + * @brief Enable memory block shut-off in DStop or DStop2 modes + * @note In DStop or DStop2 mode, the content of the memory blocks is + * maintained. Further power optimization can be obtained by switching + * off some memory blocks. This optimization implies loss of the memory + * content. The user can select which memory is discarded during STOP + * mode by means of xxSO bits. + * @param MemoryBlock : Specifies the memory block to shut-off during DStop or + * DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. + */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Enable memory block shut-off */ + SET_BIT (PWR->CR1, MemoryBlock); +} + +/** + * @brief Disable memory block shut-off in DStop or DStop2 modes + * @param MemoryBlock : Specifies the memory block to keep content during + * DStop or DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. + */ +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Disable memory block shut-off */ + CLEAR_BIT (PWR->CR1, MemoryBlock); +} +#endif /* defined (PWR_CR1_SRDRAMSO) */ + +/** + * @brief Enable the Wake-up PINx functionality. + * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that + * contains the configuration information for the wake-up + * Pin. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx. All combination are allowed: wake up only + * Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and + * Cortex-M4. + * @retval None. + */ +void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams) +{ + uint32_t pinConfig; + uint32_t regMask; + const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1; + + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin)); + assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity)); + assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull)); + + pinConfig = sPinParams->WakeUpPin | \ + (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \ + (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU)); + + regMask = sPinParams->WakeUpPin | \ + (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU)); + + /* Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge) */ + MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig); +#ifndef DUAL_CORE + /* Configure the Wakeup Pin EXTI Line */ + MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos)); +#endif /* !DUAL_CORE */ +} + +/** + * @brief Disable the Wake-up PINx functionality. + * @param WakeUpPin : Specifies the Wake-Up pin to be disabled. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN. + * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN. + * @arg PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN. + * @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN. + * @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN. + * @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN. + * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for + * devices that support GPIOI port. + * @retval None + */ +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin) +{ + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin)); + + /* Disable the WakeUpPin */ + CLEAR_BIT (PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Get the Wake-Up Pin pending flags. + * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Get wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all + * wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. + * @retval The Wake-Up pin flag. + */ +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + + /* Return the wake up pin flag */ + return (PWR->WKUPFR & WakeUpFlag); +} + +/** + * @brief Clear the Wake-Up pin pending flag. + * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from + * all wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag) +{ + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + + /* Clear the wake up event received from wake up pin x */ + SET_BIT (PWR->WKUPCR, WakeUpFlag); + + /* Check if the wake up event is well cleared */ + if ((PWR->WKUPFR & WakeUpFlag) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief This function handles the PWR WAKEUP PIN interrupt request. + * @note This API should be called under the WAKEUP_PIN_IRQHandler(). + * @retval None. + */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void) +{ + /* Wakeup pin EXTI line interrupt detected */ + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U) + { + /* Clear PWR WKUPF1 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1); + + /* PWR WKUP1 interrupt user callback */ + HAL_PWREx_WKUP1_Callback (); + } + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U) + { + /* Clear PWR WKUPF2 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2); + + /* PWR WKUP2 interrupt user callback */ + HAL_PWREx_WKUP2_Callback (); + } +#if defined (PWR_WKUPFR_WKUPF3) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U) + { + /* Clear PWR WKUPF3 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3); + + /* PWR WKUP3 interrupt user callback */ + HAL_PWREx_WKUP3_Callback (); + } +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U) + { + /* Clear PWR WKUPF4 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4); + + /* PWR WKUP4 interrupt user callback */ + HAL_PWREx_WKUP4_Callback (); + } +#if defined (PWR_WKUPFR_WKUPF5) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U) + { + /* Clear PWR WKUPF5 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5); + + /* PWR WKUP5 interrupt user callback */ + HAL_PWREx_WKUP5_Callback (); + } +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + else + { + /* Clear PWR WKUPF6 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6); + + /* PWR WKUP6 interrupt user callback */ + HAL_PWREx_WKUP6_Callback (); + } +} + +/** + * @brief PWR WKUP1 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP1_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP1Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP2 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP2_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP2Callback can be implemented in the user file + */ +} + +#if defined (PWR_WKUPFR_WKUPF3) +/** + * @brief PWR WKUP3 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP3_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP3Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + +/** + * @brief PWR WKUP4 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP4_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP4Callback can be implemented in the user file + */ +} + +#if defined (PWR_WKUPFR_WKUPF5) +/** + * @brief PWR WKUP5 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP5_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP5Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + +/** + * @brief PWR WKUP6 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP6_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP6Callback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions + * @brief Peripherals control functions + * +@verbatim + =============================================================================== + ##### Peripherals control functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only + from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its + content is retained even in Standby or VBAT mode when the low power + backup regulator is enabled. It can be considered as an internal + EEPROM when VBAT is always present. You can use the + HAL_PWREx_EnableBkUpReg() function to enable the low power backup + regulator. + (+) When the backup domain is supplied by VDD (analog switch connected to + VDD) the backup SRAM is powered from VDD which replaces the VBAT power + supply to save battery life. + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + (+) The main internal regulator can be configured to have a tradeoff + between performance and power consumption when the device does not + operate at the maximum frequency. This is done through + HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS + bit in PWR_D3CR register. + (+) The main internal regulator can be configured to operate in Low Power + mode when the system enters STOP mode to further reduce power + consumption. + This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS) + function which configure the SVOS bit in PWR_CR1 register. + The selected SVOS4 and SVOS5 levels add an additional startup delay + when exiting from system Stop mode. + -@- Refer to the product datasheets for more details. + + *** USB Regulator configuration *** + =================================== + [..] + (+) The USB transceivers are supplied from a dedicated VDD33USB supply + that can be provided either by the integrated USB regulator, or by an + external USB supply. + (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the + VDD33USB is then provided from the USB regulator. + (+) When the USB regulator is enabled, the VDD33USB supply level detector + shall be enabled through HAL_PWREx_EnableUSBVoltageDetector() + function. + (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() + function and VDD33USB can be provided from an external supply. In this + case VDD33USB and VDD50USB shall be connected together. + + *** VBAT battery charging *** + ============================= + [..] + (+) When VDD is present, the external battery connected to VBAT can be + charged through an internal resistance. VBAT charging can be performed + either through a 5 KOhm resistor or through a 1.5 KOhm resistor. + (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging + (ResistorValue) function with: + (++) ResistorValue: + (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor. + (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor. + (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() + function. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void) +{ + uint32_t tickstart; + + /* Enable the Backup regulator */ + SET_BIT (PWR->CR2, PWR_CR2_BREN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till Backup regulator ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void) +{ + uint32_t tickstart; + + /* Disable the Backup regulator */ + CLEAR_BIT (PWR->CR2, PWR_CR2_BREN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till Backup regulator ready flag is reset */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void) +{ + uint32_t tickstart; + + /* Enable the USB regulator */ + SET_BIT (PWR->CR3, PWR_CR3_USBREGEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till the USB regulator ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the USB Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void) +{ + uint32_t tickstart; + + /* Disable the USB regulator */ + CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till the USB regulator ready flag is reset */ + while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_EnableUSBVoltageDetector (void) +{ + /* Enable the USB voltage detector */ + SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Disable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_DisableUSBVoltageDetector (void) +{ + /* Disable the USB voltage detector */ + CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Enable the Battery charging. + * @note When VDD is present, charge the external battery through an internal + * resistor. + * @param ResistorValue : Specifies the charging resistor. + * This parameter can be one of the following values : + * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. + * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. + * @retval None. + */ +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue) +{ + /* Check the parameter */ + assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue)); + + /* Specify the charging resistor */ + MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue); + + /* Enable the Battery charging */ + SET_BIT (PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Disable the Battery charging. + * @retval None. + */ +void HAL_PWREx_DisableBatteryCharging (void) +{ + /* Disable the Battery charging */ + CLEAR_BIT (PWR->CR3, PWR_CR3_VBE); +} + +#if defined (PWR_CR1_BOOSTE) +/** + * @brief Enable the booster to guarantee the analog switch AC performance when + * the VDD supply voltage is below 2V7. + * @note The VDD supply voltage can be monitored through the PVD and the PLS + * field bits. + * @retval None. + */ +void HAL_PWREx_EnableAnalogBooster (void) +{ + /* Enable the Analog voltage */ + SET_BIT (PWR->CR1, PWR_CR1_AVD_READY); + + /* Enable VDDA booster */ + SET_BIT (PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the analog booster. + * @retval None. + */ +void HAL_PWREx_DisableAnalogBooster (void) +{ + /* Disable VDDA booster */ + CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE); + + /* Disable the Analog voltage */ + CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY); +} +#endif /* defined (PWR_CR1_BOOSTE) */ +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @brief Power Monitoring functions + * +@verbatim + =============================================================================== + ##### Power Monitoring functions ##### + =============================================================================== + + *** VBAT and Temperature supervision *** + ======================================== + [..] + (+) The VBAT battery voltage supply can be monitored by comparing it with + two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags + in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or + lower than the threshold. + (+) The temperature can be monitored by comparing it with two threshold + levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR + control register 2 (PWR_CR2), indicate whether the device temperature + is higher or lower than the threshold. + (+) The VBAT and the temperature monitoring is enabled by + HAL_PWREx_EnableMonitoring() function and disabled by + HAL_PWREx_DisableMonitoring() function. + (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can + be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or + PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD. + (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature + level which can be : + PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or + PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD. + + *** AVD configuration *** + ========================= + [..] + (+) The AVD is used to monitor the VDDA power supply by comparing it to a + threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 + register). + (+) A AVDO flag is available to indicate if VDDA is higher or lower + than the AVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro. + (+) The AVD is stopped in System Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_EnableMonitoring (void) +{ + /* Enable the VBAT and Temperature monitoring */ + SET_BIT (PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Disable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_DisableMonitoring (void) +{ + /* Disable the VBAT and Temperature monitoring */ + CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Indicate whether the junction temperature is between, above or below + * the thresholds. + * @retval Temperature level. + */ +uint32_t HAL_PWREx_GetTemperatureLevel (void) +{ + uint32_t tempLevel, regValue; + + /* Read the temperature flags */ + regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL)); + + /* Check if the temperature is below the threshold */ + if (regValue == PWR_CR2_TEMPL) + { + tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD; + } + /* Check if the temperature is above the threshold */ + else if (regValue == PWR_CR2_TEMPH) + { + tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD; + } + /* The temperature is between the thresholds */ + else + { + tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return tempLevel; +} + +/** + * @brief Indicate whether the Battery voltage level is between, above or below + * the thresholds. + * @retval VBAT level. + */ +uint32_t HAL_PWREx_GetVBATLevel (void) +{ + uint32_t VBATLevel, regValue; + + /* Read the VBAT flags */ + regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL)); + + /* Check if the VBAT is below the threshold */ + if (regValue == PWR_CR2_VBATL) + { + VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD; + } + /* Check if the VBAT is above the threshold */ + else if (regValue == PWR_CR2_VBATH) + { + VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD; + } + /* The VBAT is between the thresholds */ + else + { + VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return VBATLevel; +} + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief Get the VDDMMC voltage level. + * @retval The VDDMMC voltage level. + */ +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) +{ + PWREx_MMC_VoltageLevel mmc_voltage; + + /* Check voltage detector output on VDDMMC value */ + if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U) + { + mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2; + } + else + { + mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2; + } + + return mmc_voltage; +} +#endif /* defined (PWR_CSR1_MMCVDO) */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Analog Voltage Detector (AVD). + * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains + * the configuration information for the AVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) +{ + /* Check the parameters */ + assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); + assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); + + /* Set the ALS[18:17] bits according to AVDLevel value */ + MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); + + /* Clear any previous config */ +#if !defined (DUAL_CORE) + __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_AVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); + +#if !defined (DUAL_CORE) + /* Configure the interrupt mode */ + if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) + { + __HAL_PWR_AVD_EXTI_ENABLE_IT (); + } + + /* Configure the event mode */ + if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) + { + __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); + } +#endif /* !defined (DUAL_CORE) */ + + /* Rising edge configuration */ + if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); + } + + /* Falling edge configuration */ + if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); + } +} + +/** + * @brief Enable the Analog Voltage Detector (AVD). + * @retval None. + */ +void HAL_PWREx_EnableAVD (void) +{ + /* Enable the Analog Voltage Detector */ + SET_BIT (PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable the Analog Voltage Detector(AVD). + * @retval None. + */ +void HAL_PWREx_DisableAVD (void) +{ + /* Disable the Analog Voltage Detector */ + CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief This function handles the PWR PVD/AVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_AVD_IRQHandler (void) +{ + /* Check if the Programmable Voltage Detector is enabled (PVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U) + { +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ + { + /* Check PWR D1/CD EXTI flag */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + } + } +#if defined (DUAL_CORE) + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_PVD_EXTID2_CLEAR_FLAG(); + } + } +#endif /* defined (DUAL_CORE) */ + } + + /* Check if the Analog Voltage Detector is enabled (AVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U) + { +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ + { + /* Check PWR EXTI D1/CD flag */ + if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U) + { + /* PWR AVD interrupt user callback */ + HAL_PWREx_AVDCallback (); + + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_AVD_EXTI_CLEAR_FLAG (); + } + } +#if defined (DUAL_CORE) + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U) + { + /* PWR AVD interrupt user callback */ + HAL_PWREx_AVDCallback (); + + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_AVD_EXTID2_CLEAR_FLAG (); + } + } +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief PWR AVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_AVDCallback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_AVDCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c new file mode 100644 index 0000000..8c987ac --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -0,0 +1,1814 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except + internal SRAM, Flash, JTAG and PWR + (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analogue mode , except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses pre-scalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock kernel source(s) for peripherals which clocks are not + derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R + and RCC_D3CCIPR registers + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1 + AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral + clock, or PLL input.But even with frequency calibration, is less accurate than an + external crystal oscillator or ceramic resonator. + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI), + featuring three different output clocks and able to work either in integer or Fractional mode. + (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU + and to some peripherals. + (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals. + + + (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt) + exception vector. + + (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q) + or HSI48 clock (through a configurable pre-scaler) on PA8 pin. + + (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK, + LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin. + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System core clock through configurable + pre-scaler and used to clock the CPU, memory and peripherals mapped + on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers + and used to clock the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those + with dual clock domain where kernel source clock could be selected through + RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers. + + (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines. +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL1, PLL2 and PLL3 OFF + * - AHB, APB Bus pre-scaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Update the SystemCoreClock and SystemD2Clock global variables */ + SystemCoreClock = HSI_VALUE; + SystemD2Clock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON \ + | RCC_CR_HSI48ON | RCC_CR_CSSHSEON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL3 bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_D1CFGR_HPRE) + /* Reset D1CFGR register */ + CLEAR_REG(RCC->D1CFGR); + + /* Reset D2CFGR register */ + CLEAR_REG(RCC->D2CFGR); + + /* Reset D3CFGR register */ + CLEAR_REG(RCC->D3CFGR); +#else + /* Reset CDCFGR1 register */ + CLEAR_REG(RCC->CDCFGR1); + + /* Reset CDCFGR2 register */ + CLEAR_REG(RCC->CDCFGR2); + + /* Reset SRDCFGR register */ + CLEAR_REG(RCC->SRDCFGR); +#endif + + /* Reset PLLCKSELR register to default value */ + RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5; + + /* Reset PLLCFGR register to default value */ + WRITE_REG(RCC->PLLCFGR, 0x01FF0000U); + + /* Reset PLL1DIVR register to default value */ + WRITE_REG(RCC->PLL1DIVR, 0x01010280U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2DIVR register to default value */ + WRITE_REG(RCC->PLL2DIVR, 0x01010280U); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + + /* Reset PLL3DIVR register to default value */ + WRITE_REG(RCC->PLL3DIVR, 0x01010280U); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); + +#if defined(RCC_CR_HSEEXT) + /* Reset HSEEXT */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +#endif /* RCC_CR_HSEEXT */ + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Reset all RSR flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t temp1_pllckcfg, temp2_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* When the HSI is used as system clock it will not be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + { + return HAL_ERROR; + } + /* Otherwise, only HSI division and calibration are allowed */ + else + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- CSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + { + /* Check the parameters */ + assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); + assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); + + /* When the CSI is used as system clock it will not disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) + { + /* When CSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + } + } + else + { + /* Check the CSI State */ + if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) + { + /* Enable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*------------------------------ HSI48 Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLRGE_VALUE(RCC_OscInitStruct->PLL.PLLRGE)); + assert_param(IS_RCC_PLLVCO_VALUE(RCC_OscInitStruct->PLL.PLLVCOSEL)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Disable PLLFRACN . */ + __HAL_RCC_PLLFRACN_DISABLE(); + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + + /* Select PLL1 input reference frequency range: VCI */ + __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; + + /* Select PLL1 output frequency range : VCO */ + __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + + /* Enable PLL1Q Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* Enable PLL1R Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + + /* Enable PLL1FRACN . */ + __HAL_RCC_PLLFRACN_ENABLE(); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLLCKSELR; + temp2_pllckcfg = RCC->PLL1DIVR; + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } + else + { + /* Check if only fractional part needs to be updated */ + temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); + if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + /* Disable PLL1FRACEN */ + __HAL_RCC_PLLFRACN_DISABLE(); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) + { + } + /* Configure PLL1 PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + /* Enable PLL1FRACEN to latch new value. */ + __HAL_RCC_PLLFRACN_ENABLE(); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency: FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency + * and updated by HAL_InitTick() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + HAL_StatusTypeDef halstatus; + uint32_t tickstart; + uint32_t common_system_clock; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + + } + + /* Increasing the BUS frequency divider */ + /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + { +#if defined (RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#else + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { +#if defined (RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { +#if defined(RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif + } + + /*-------------------------- D3PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#endif + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { +#if defined (RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#else + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); +#if defined(RCC_D1CFGR_D1CPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); +#endif + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + return HAL_ERROR; + } + } + /* CSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + /* Decreasing the BUS frequency divider */ + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { +#if defined(RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#else + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + { +#if defined(RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#else + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { +#if defined(RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { +#if defined (RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif + } + + /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#endif + } + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Configure the source of time base considering new system clocks settings*/ + halstatus = HAL_InitTick(uwTickPrio); + + return halstatus; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx: specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source + * @param RCC_MCODiv: specifies the MCOx pre-scaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U))); + } +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON); +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*) + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; + float_t fracn1, pllvco; + uint32_t sysclockfreq; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + sysclockfreq = (uint32_t) HSI_VALUE; + } + + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; + pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; + sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); + } + else + { + sysclockfreq = 0U; + } + break; + + default: + sysclockfreq = CSI_VALUE; + break; + } + + return sysclockfreq; +} + + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return SystemD2Clock; +} + + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ +#if defined (RCC_D2CFGR_D2PPRE1) + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); +#else + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); +#endif +} + + +/** + * @brief Returns the D2 PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +#if defined(RCC_D2CFGR_D2PPRE2) + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); +#else + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); +#endif +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + + /* Get the HSE configuration -----------------------------------------------*/ +#if defined(RCC_CR_HSEEXT) + if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#else + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#endif /* RCC_CR_HSEEXT */ + + /* Get the CSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_CSION) == RCC_CR_CSION) + { + RCC_OscInitStruct->CSIState = RCC_CSI_ON; + } + else + { + RCC_OscInitStruct->CSIState = RCC_CSI_OFF; + } + +#if defined(RCC_VER_X) + if (HAL_GetREVID() <= REV_ID_Y) + { + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos); + } + else + { + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + } +#else + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +#endif /*RCC_VER_X*/ + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + +#if defined(RCC_VER_X) + if (HAL_GetREVID() <= REV_ID_Y) + { + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos); + } + else + { + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + } +#else + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ + + /* Get the LSE configuration -----------------------------------------------*/ +#if defined(RCC_BDCR_LSEEXT) + if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } +#else + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } +#endif /* RCC_BDCR_LSEEXT */ + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the HSI48 configuration ---------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + } + else + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE)); + RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos); + RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos)); +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency: Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + +#if defined(RCC_D1CFGR_D1CPRE) + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); + + /* Get the D1HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); + + /* Get the APB3 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); +#else + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE); + + /* Get the D1HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE); + + /* Get the APB3 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); +#endif + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c new file mode 100644 index 0000000..b771887 --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -0,0 +1,3935 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_defines RCCEx Private Defines + * @{ + */ +#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ +#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ + +#define DIVIDER_P_UPDATE 0U +#define DIVIDER_Q_UPDATE 1U +#define DIVIDER_R_UPDATE 2U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123, + * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, + * SAI4A*, SAI4B*, SPI6, RTC). + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * (*) : Available on some STM32H7 lines only. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /*---------------------------- SPDIFRX configuration -------------------------------*/ + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + + switch (PeriphClkInit->SpdifrxClockSelection) + { + case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ + /* Enable PLL1Q Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_HSI: + /* Internal OSC clock is used as source of SPDIFRX clock*/ + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPDIFRX clock*/ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SAI1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + switch (PeriphClkInit->Sai1ClockSelection) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PIN: + /* External clock is used as source of SAI1 clock*/ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(SAI3) + /*---------------------------- SAI2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) + { + switch (PeriphClkInit->Sai23ClockSelection) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PIN: + /* External clock is used as source of SAI2/3 clock*/ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2/3 clock*/ + __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + /*---------------------------- SAI2A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) + { + switch (PeriphClkInit->Sai2AClockSelection) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ + /* Enable SAI2A Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PIN: + /* External clock is used as source of SAI2A clock*/ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2A clock*/ + __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2A*/ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) + + /*---------------------------- SAI2B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) + { + switch (PeriphClkInit->Sai2BClockSelection) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PIN: + /* External clock is used as source of SAI2B clock*/ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2B clock*/ + __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2B*/ + +#if defined(SAI4) + /*---------------------------- SAI4A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) + { + switch (PeriphClkInit->Sai4AClockSelection) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4A clock */ + /* SAI4A clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4A clock*/ + __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + /*---------------------------- SAI4B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) + { + switch (PeriphClkInit->Sai4BClockSelection) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4B clock */ + /* SAI4B clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4B clock*/ + __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI4*/ + +#if defined(QUADSPI) + /*---------------------------- QSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) + { + switch (PeriphClkInit->QspiClockSelection) + { + case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ + /* Enable QSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_QSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_D1HCLK: + /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of QSPI clock*/ + __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /*---------------------------- OCTOSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + switch (PeriphClkInit->OspiClockSelection) + { + case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ + /* Enable OSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_OSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_HCLK: + /* HCLK clock selected as OSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of OSPI clock*/ + __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*OCTOSPI*/ + + /*---------------------------- SPI1/2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) + { + switch (PeriphClkInit->Spi123ClockSelection) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ + /* Enable SPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PIN: + /* External clock is used as source of SPI1/2/3 clock*/ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI1/2/3 clock*/ + __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI4/5 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) + { + switch (PeriphClkInit->Spi45ClockSelection) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for SPI4/5 */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI4/5 clock*/ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI4/5 clock*/ + __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI6 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + { + switch (PeriphClkInit->Spi6ClockSelection) + { + case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI6 clock source configuration done later after clock selection check */ + break; + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI6 clock*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: + /* 2S_CKIN is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#endif + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI6 clock*/ + __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(DSI) + /*---------------------------- DSI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + switch (PeriphClkInit->DsiClockSelection) + { + + case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* DSI clock source configuration done later after clock selection check */ + break; + + case RCC_DSICLKSOURCE_PHY: + /* PHY is used as clock source for DSI*/ + /* DSI clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of DSI clock*/ + __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*DSI*/ + +#if defined(FDCAN1) || defined(FDCAN2) + /*---------------------------- FDCAN configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + switch (PeriphClkInit->FdcanClockSelection) + { + case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ + /* Enable FDCAN Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_HSE: + /* HSE is used as clock source for FDCAN*/ + /* FDCAN clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FDCAN clock*/ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*FDCAN1 || FDCAN2*/ + + /*---------------------------- FMC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + { + switch (PeriphClkInit->FmcClockSelection) + { + case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ + /* Enable FMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* FMC clock source configuration done later after clock selection check */ + break; + + + case RCC_FMCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_HCLK: + /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FMC clock*/ + __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- RTC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg; + } + + /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ + if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*-------------------------- USART1/6 configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) + { + switch (PeriphClkInit->Usart16ClockSelection) + { + case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART1/6 clock */ + __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) + { + switch (PeriphClkInit->Usart234578ClockSelection) + { + case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART2/3/4/5/7/8 clock */ + __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- LPUART1 Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + switch (PeriphClkInit->Lpuart1ClockSelection) + { + case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_LSE: + /* LSE, oscillator is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPUART1 clock */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + switch (PeriphClkInit->Lptim1ClockSelection) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM1 clock*/ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) + { + switch (PeriphClkInit->Lptim2ClockSelection) + { + case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM2CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM2 clock*/ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM345 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) + { + switch (PeriphClkInit->Lptim345ClockSelection) + { + + case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM345CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM3/4/5 clock */ + __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ +#if defined(I2C5) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); + + if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); + + } +#else + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); + + if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); + + } +#endif /* I2C5 */ + + /*------------------------------ I2C4 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + + } + + /*---------------------------- ADC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + switch (PeriphClkInit->AdcClockSelection) + { + + case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ + /* ADC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of ADC clock*/ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ USB Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + + switch (PeriphClkInit->UsbClockSelection) + { + case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ + /* Enable USB Clock output generated form System USB . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ + + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of USB clock */ + /* USB clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USB clock*/ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------------- SDMMC Configuration ------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); + + switch (PeriphClkInit->SdmmcClockSelection) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ + /* Enable SDMMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SDMMC clock*/ + __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(LTDC) + /*-------------------------------------- LTDC Configuration -----------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* LTDC */ + + /*------------------------------ RNG Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + { + + switch (PeriphClkInit->RngClockSelection) + { + case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ + /* Enable RNG Clock output generated form System RNG . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of RNG clock */ + /* RNG clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of RNG clock*/ + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------ SWPMI1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); + + /* Configure the SWPMI1 interface clock source */ + __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); + } +#if defined(HRTIM1) + /*------------------------------ HRTIM1 clock Configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); + + /* Configure the HRTIM1 clock source */ + __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); + } +#endif /*HRTIM1*/ + /*------------------------------ DFSDM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + +#if defined(DFSDM2_BASE) + /*------------------------------ DFSDM2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM2 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } +#endif /* DFSDM2 */ + + /*------------------------------------ TIM configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*------------------------------------ CKPER configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + { + /* Check the parameters */ + assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); + + /* Configure the CKPER clock source */ + __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); + } + + /*------------------------------ CEC Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC interface clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*---------------------------- PLL2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*---------------------------- PLL3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + if (status == HAL_OK) + { + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks : + * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123, + * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC. + * SAI4A*, SAI4B*, SPI6, RTC, TIM). + * @retval None + * + * (*) : Available on some STM32H7 lines only. + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = + RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | + RCC_PERIPHCLK_CKPER; + +#if defined(I2C5) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; +#else + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; +#endif /*I2C5*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B; +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI3) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23; +#endif /* SAI3 */ +#if defined(SAI4) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A; + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; +#endif /* SAI4 */ +#if defined(DFSDM2_BASE) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2; +#endif /* DFSDM2 */ +#if defined(QUADSPI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI; +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; +#endif /* OCTOSPI1 || OCTOSPI2 */ +#if defined(HRTIM1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; +#endif /* HRTIM1 */ +#if defined(LTDC) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; +#endif /* LTDC */ +#if defined(DSI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI; +#endif /* DSI */ + + /* Get the PLL3 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); + PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos); + PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos); + + /* Get the PLL2 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); + PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos); + PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos); + + /* Get the USART1 configuration --------------------------------------------*/ + PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE(); + /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ + PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(I2C5) + /* Get the I2C1/2/3/5 clock source -----------------------------------------*/ + PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#else + /* Get the I2C1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#endif /*I2C5*/ + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ + PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE(); + /* Get the SAI1 clock source -----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#if defined(SAI3) + /* Get the SAI2/3 clock source ---------------------------------------------*/ + PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE(); +#endif /*SAI3*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL_0) + /* Get the SAI2A clock source ---------------------------------------------*/ + PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE(); +#endif /*SAI2A*/ +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + /* Get the SAI2B clock source ---------------------------------------------*/ + PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE(); +#endif /*SAI2B*/ +#if defined(SAI4) + /* Get the SAI4A clock source ----------------------------------------------*/ + PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE(); + /* Get the SAI4B clock source ----------------------------------------------*/ + PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE(); +#endif /*SAI4*/ + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USB clock source ------------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); + /* Get the SDMMC clock source ----------------------------------------------*/ + PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#if defined(HRTIM1) + /* Get the HRTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); +#endif /* HRTIM1 */ + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + /* Get the SWPMI1 clock source ---------------------------------------------*/ + PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); + /* Get the DFSDM1 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); +#if defined(DFSDM2_BASE) + /* Get the DFSDM2 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); +#endif /* DFSDM2 */ + /* Get the SPDIFRX clock source --------------------------------------------*/ + PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + /* Get the SPI1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE(); + /* Get the SPI4/5 clock source ---------------------------------------------*/ + PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE(); + /* Get the SPI6 clock source -----------------------------------------------*/ + PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); + /* Get the FDCAN clock source ----------------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + /* Get the FMC clock source ------------------------------------------------*/ + PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); +#if defined(QUADSPI) + /* Get the QSPI clock source -----------------------------------------------*/ + PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /* Get the OSPI clock source -----------------------------------------------*/ + PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 || OCTOSPI2 */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /*DSI*/ + + /* Get the CKPER clock source ----------------------------------------------*/ + PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk: Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*) + * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock + * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock + * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock + * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock + * @retval Frequency in KHz + * + * (*) : Available on some STM32H7 lines only. + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) +{ + PLL1_ClocksTypeDef pll1_clocks; + PLL2_ClocksTypeDef pll2_clocks; + PLL3_ClocksTypeDef pll3_clocks; + + /* This variable is used to store the clock frequency (value in Hz) */ + uint32_t frequency; + /* This variable is used to store the SAI and CKP clock source */ + uint32_t saiclocksource; + uint32_t ckpclocksource; + uint32_t srcclk; + + if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + + saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + +#if defined(SAI3) + else if (PeriphClk == RCC_PERIPHCLK_SAI23) + { + + saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + + else if (PeriphClk == RCC_PERIPHCLK_SAI2A) + { + saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + + } +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + else if (PeriphClk == RCC_PERIPHCLK_SAI2B) + { + + saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + break; + } + + case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif + +#if defined(SAI4) + else if (PeriphClk == RCC_PERIPHCLK_SAI4A) + { + + saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } + + else if (PeriphClk == RCC_PERIPHCLK_SAI4B) + { + + saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif /*SAI4*/ + else if (PeriphClk == RCC_PERIPHCLK_SPI123) + { + /* Get SPI1/2/3 clock source */ + srcclk = __HAL_RCC_GET_SPI123_SOURCE(); + + switch (srcclk) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI45) + { + /* Get SPI45 clock source */ + srcclk = __HAL_RCC_GET_SPI45_SOURCE(); + switch (srcclk) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + break; + } + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADC) + { + /* Get ADC clock source */ + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + switch (srcclk) + { + case RCC_ADCCLKSOURCE_PLL2: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_ADCCLKSOURCE_PLL3: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_ADCCLKSOURCE_CLKP: + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + /* Get SDMMC clock source */ + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); + + switch (srcclk) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI6) + { + /* Get SPI6 clock source */ + srcclk = __HAL_RCC_GET_SPI6_SOURCE(); + + switch (srcclk) + { + case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ + { + frequency = HAL_RCCEx_GetD3PCLK1Freq(); + break; + } + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#endif /* RCC_SPI6CLKSOURCE_PIN */ + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN) + { + /* Get FDCAN clock source */ + srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); + + switch (srcclk) + { + case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else + { + frequency = 0; + } + + return frequency; +} + + +/** + * @brief Returns the D1PCLK1 frequency + * @note Each time D1PCLK1 changes, this function must be called to update the + * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D1PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) +{ +#if defined(RCC_D1CFGR_D1PPRE) + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); +#endif +} + +/** + * @brief Returns the D3PCLK1 frequency + * @note Each time D3PCLK1 changes, this function must be called to update the + * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D3PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) +{ +#if defined(RCC_D3CFGR_D3PPRE) + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); +#endif +} +/** +* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency + * @note The PLL2 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL2CLK changes, this function must be called to update the + * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL2_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) +{ + uint32_t pllsource, pll2m, pll2fracen, hsivalue; + float_t fracn2, pll2vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N + PLL2xCLK = PLL2_VCO / PLL2x + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); + pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; + fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); + + if (pll2m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + else + { + pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + } + PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; + PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; + PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; + } + else + { + PLL2_Clocks->PLL2_P_Frequency = 0U; + PLL2_Clocks->PLL2_Q_Frequency = 0U; + PLL2_Clocks->PLL2_R_Frequency = 0U; + } +} + +/** +* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency + * @note The PLL3 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL3CLK changes, this function must be called to update the + * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL3_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) +{ + uint32_t pllsource, pll3m, pll3fracen, hsivalue; + float_t fracn3, pll3vco; + + /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N + PLL3xCLK = PLL3_VCO / PLLxR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; + pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; + fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); + + if (pll3m != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + else + { + pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + } + PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; + PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; + PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; + } + else + { + PLL3_Clocks->PLL3_P_Frequency = 0U; + PLL3_Clocks->PLL3_Q_Frequency = 0U; + PLL3_Clocks->PLL3_R_Frequency = 0U; + } + +} + +/** +* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency + * @note The PLL1 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL1CLK changes, this function must be called to update the + * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL1_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) +{ + uint32_t pllsource, pll1m, pll1fracen, hsivalue; + float_t fracn1, pll1vco; + + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); + pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pll1m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + + PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; + PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; + PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; + } + else + { + PLL1_Clocks->PLL1_P_Frequency = 0U; + PLL1_Clocks->PLL1_Q_Frequency = 0U; + PLL1_Clocks->PLL1_R_Frequency = 0U; + } + +} + +/** + * @brief Returns the main System frequency + * @note Each time System clock changes, this function must be called to update the + * right core clock value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCCEx_GetD1SysClockFreq(void) +{ + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return common_system_clock; +} +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions + * @brief Extended Peripheral Control functions + * @{ + */ +/** + * @brief Enables the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disables the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + /* Disable LSE CSS IT if any */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 18 */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); +#else + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +#endif /* DUAL_CORE && CORE_CM4 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock + * @param WakeUpClk: Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the oscillator Kernel clock source for wakeup from Stop + * @param WakeUpClk: Kernel Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection + * @retval None + */ +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable COREx boot independently of CMx_B option byte value + * @param RCC_BootCx: Boot Core to be enabled + * This parameter can be one of the following values: + * @arg RCC_BOOT_C1: CM7 core selection + * @arg RCC_BOOT_C2: CM4 core selection + * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY + * + * @retval None + */ +void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx) +{ + assert_param(IS_RCC_BOOT_CORE(RCC_BootCx)); + SET_BIT(RCC->GCR, RCC_BootCx) ; +} + +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** + * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @arg RCC_WWDG2: WWDG2 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} + +#else +#if defined(RCC_GCR_WW1RSC) +/** + * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} +#endif +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the up-counting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2)) + { + /* Use Rev.Y value of USB2 */ + value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity); + } + else + { + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + } + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the time-out +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg @ref RCC_CRS_TIMEOUT +* @arg @ref RCC_CRS_SYNCOK +* @arg @ref RCC_CRS_SYNCWARN +* @arg @ref RCC_CRS_SYNCERR +* @arg @ref RCC_CRS_SYNCMISS +* @arg @ref RCC_CRS_TRIMOVF +*/ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or time-out detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } + while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCCEx_Private_functions RCCEx Private Functions + * @{ + */ +/** + * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL2 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +{ + + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M)); + assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N)); + assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P)); + assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R)); + assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q)); + assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); + assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); + + /* Check that PLL2 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL2 multiplication and division factors. */ + __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, + pll2->PLL2N, + pll2->PLL2P, + pll2->PLL2Q, + pll2->PLL2R); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; + + /* Select PLL2 output frequency range : VCO */ + __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; + + /* Disable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_DISABLE(); + + /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); + + /* Enable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_ENABLE(); + + /* Enable the PLL2 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); + } + else + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); + } + + /* Enable PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + + +/** + * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL3 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M)); + assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N)); + assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P)); + assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R)); + assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q)); + assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); + assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); + + /* Check that PLL3 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL3. */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the PLL3 multiplication and division factors. */ + __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, + pll3->PLL3N, + pll3->PLL3P, + pll3->PLL3Q, + pll3->PLL3R); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; + + /* Select PLL3 output frequency range : VCO */ + __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; + + /* Disable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_DISABLE(); + + /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); + + /* Enable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_ENABLE(); + + /* Enable the PLL3 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); + } + else + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); + } + + /* Enable PLL3. */ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + + + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c new file mode 100644 index 0000000..eab578f --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -0,0 +1,7908 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + case TIM_CLOCKSOURCE_ITR4: + case TIM_CLOCKSOURCE_ITR5: + case TIM_CLOCKSOURCE_ITR6: + case TIM_CLOCKSOURCE_ITR7: + case TIM_CLOCKSOURCE_ITR8: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + case TIM_TS_ITR4: + case TIM_TS_ITR5: + case TIM_TS_ITR6: + case TIM_TS_ITR7: + case TIM_TS_ITR8: + case TIM_TS_ITR9: + case TIM_TS_ITR10: + case TIM_TS_ITR11: + case TIM_TS_ITR12: + case TIM_TS_ITR13: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_ITR4: Internal Trigger 4 (*) + * @arg TIM_TS_ITR5: Internal Trigger 5 + * @arg TIM_TS_ITR6: Internal Trigger 6 + * @arg TIM_TS_ITR7: Internal Trigger 7 + * @arg TIM_TS_ITR8: Internal Trigger 8 (*) + * @arg TIM_TS_ITR9: Internal Trigger 9 (*) + * @arg TIM_TS_ITR10: Internal Trigger 10 (*) + * @arg TIM_TS_ITR11: Internal Trigger 11 (*) + * @arg TIM_TS_ITR12: Internal Trigger 12 (*) + * @arg TIM_TS_ITR13: Internal Trigger 13 (*) + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * + * (*) Value not defined in all devices. + * + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c new file mode 100644 index 0000000..ad4cbee --- /dev/null +++ b/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c @@ -0,0 +1,2947 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(TIM_BDTR_BKBID) +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +#endif /* TIM_BDTR_BKBID */ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR12: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR13: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR2: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR2: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + +#if defined(TIM_BDTR_BKBID) + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Set BREAK AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + } + +#endif /* TIM_BDTR_BKBID */ + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); +#if defined(TIM_BDTR_BKBID) + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set BREAK2 AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } +#endif /* TIM_BDTR_BKBID */ + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + } + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM1_AF1_BKCMP1E; + bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM1_AF1_BKCMP2E; + bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BK0E; + bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} +#endif /*TIM_BREAK_INPUT_SUPPORT */ + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter is one of the following values: + * @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO + * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output + * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 + * + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output + * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A + * @arg TIM_TIM2_ETR_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO + * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output + * + * For TIM5, the parameter is one of the following values: + * @arg TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO + * @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * @arg TIM_TIM5_ETR_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * + * For TIM8, the parameter is one of the following values: + * @arg TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO + * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output + * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output + * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 + * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 + * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 + * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 + * + * For TIM23, the parameter is one of the following values: (*) + * @arg TIM_TIM23_ETR_GPIO TIM23_ETR is connected to GPIO + * @arg TIM_TIM23_ETR_COMP1 TIM23_ETR is connected to COMP1 output + * @arg TIM_TIM23_ETR_COMP2 TIM23_ETR is connected to COMP2 output + * + * For TIM24, the parameter is one of the following values: (*) + * @arg TIM_TIM24_ETR_GPIO TIM24_ETR is connected to GPIO + * @arg TIM_TIM24_ETR_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A + * @arg TIM_TIM24_ETR_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B + * @arg TIM_TIM24_ETR_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A + * @arg TIM_TIM24_ETR_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B + * + * (*) Value not defined in all devices. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: + * For TIM1, the parameter is one of the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output + * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output + * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output + * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output + * + * For TIM5, the parameter is one of the following values: + * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO + * @arg TIM_TIM5_TI1_CAN_TMP: TIM5 TI1 is connected to CAN TMP + * @arg TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP + * + * For TIM8, the parameter is one of the following values: + * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO + * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output + * + * For TIM12, the parameter can have the following values: (*) + * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO + * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS + * + * For TIM15, the parameter is one of the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1 + * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE + * @arg TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI + * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2 + * @arg TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2 + * + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt + * + * For TIM17, the parameter can have the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*) + * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz + * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1 + * + * For TIM23, the parameter can have the following values: (*) + * @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO + * @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output + * @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output + * @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output + * + * For TIM24, the parameter can have the following values: (*) + * @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO + * @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP + * @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP + * @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC + * + * (*) Value not defined in all devices. \n + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_3: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); + break; + case TIM_CHANNEL_4: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BDTR_BKBID) + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* TIM_BDTR_BKBID */ + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/LWFTP/_lwftp.c b/LWFTP/_lwftp.c new file mode 100644 index 0000000..4cf377c --- /dev/null +++ b/LWFTP/_lwftp.c @@ -0,0 +1,692 @@ +/* + * lwftp.c : a lightweight FTP client using raw API of LWIP + * + * Copyright (c) 2014 GEZEDO + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Laurent GONZALEZ + * + */ + +#include <_lwftp.h> +#include +#include "lwip/tcp.h" +#include "lwip/tcpip.h" + +/** Enable debugging for LWFTP */ +#ifndef LWFTP_DEBUG +#define LWFTP_DEBUG LWIP_DBG_ON +#endif + +#define LWFTP_TRACE (LWFTP_DEBUG|LWIP_DBG_TRACE) +#define LWFTP_STATE (LWFTP_DEBUG|LWIP_DBG_STATE) +#define LWFTP_WARNING (LWFTP_DEBUG|LWIP_DBG_LEVEL_WARNING) +#define LWFTP_SERIOUS (LWFTP_DEBUG|LWIP_DBG_LEVEL_SERIOUS) +#define LWFTP_SEVERE (LWFTP_DEBUG|LWIP_DBG_LEVEL_SEVERE) + +#define PTRNLEN(s) s,(sizeof(s)-1) + +static void lwftp_control_process(lwftp_session_t *s, struct tcp_pcb *tpcb, + struct pbuf *p); + +/** Close control or data pcb + * @param pointer to lwftp session data + */ +static err_t lwftp_pcb_close(struct tcp_pcb *tpcb) { + err_t error; + + tcp_err(tpcb, NULL); + tcp_recv(tpcb, NULL); + tcp_sent(tpcb, NULL); + error = tcp_close(tpcb); + if (error != ERR_OK) { + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:pcb close failure, not implemented\n")); + } + return ERR_OK; +} + +/** Send data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_send_next_data(lwftp_session_t *s) { + const char *data; + int len = 0; + err_t error = ERR_OK; + + if (s->data_source) { + len = s->data_source(s->handle, &data, s->data_pcb->mss); + if (len) { + error = tcp_write(s->data_pcb, data, len, 0); + if (error != ERR_OK) { + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:write failure (%s), not implemented\n",lwip_strerr(error))); + } + } + } + if (!len) { + LWIP_DEBUGF(LWFTP_STATE, ("lwftp:end of file\n")); + lwftp_pcb_close(s->data_pcb); + s->data_pcb = NULL; + } + return ERR_OK; +} + +/** Handle data connection incoming data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param pointer to incoming pbuf + * @param state of incoming process + */ +static err_t lwftp_data_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, + err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + if (p) { + if (s->data_sink) { + struct pbuf *q; + for (q = p; q; q = q->next) { + s->data_sink(s->handle, q->payload, q->len); + } + } else { + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp: sinking %d bytes\n",p->tot_len)); + } + tcp_recved(tpcb, p->tot_len); + pbuf_free(p); + } else { + // NULL pbuf shall lead to close the pcb. Close is postponed after + // the session state machine updates. No need to close right here. + // Instead we kindly tell data sink we are done + if (s->data_sink) { + s->data_sink(s->handle, NULL, 0); + } + } + return ERR_OK; +} + +/** Handle data connection acknowledge of sent data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_data_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (s->data_source) { + s->data_source(s->handle, NULL, len); + } + return lwftp_send_next_data(s); +} + +/** Handle data connection error + * @param pointer to lwftp session data + * @param state of connection + */ +static void lwftp_data_err(void *arg, err_t err) { + LWIP_UNUSED_ARG(err); + if (arg != NULL) { + lwftp_session_t *s = (lwftp_session_t*) arg; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed/error connecting for data to server (%s)\n",lwip_strerr(err))); + s->data_pcb = NULL; // No need to de-allocate PCB + if (s->control_state == LWFTP_XFERING) { // gracefully move control session ahead + s->control_state = LWFTP_DATAEND; + lwftp_control_process(s, NULL, NULL); + } + } +} + +/** Process newly connected PCB + * @param pointer to lwftp session data + * @param pointer to PCB + * @param state of connection + */ +static err_t lwftp_data_connected(void *arg, struct tcp_pcb *tpcb, err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (err == ERR_OK) { + LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected for data to server\n")); + s->data_state = LWFTP_CONNECTED; + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in data_connected (%s)\n",lwip_strerr(err))); + } + return err; +} + +/** Open data connection for passive transfer + * @param pointer to lwftp session data + * @param pointer to incoming PASV response + */ +static err_t lwftp_data_open(lwftp_session_t *s, struct pbuf *p) { + err_t error; + char *ptr; + ip_addr_t data_server; + u16_t data_port; + + // Find server connection parameter + ptr = strchr(p->payload, '('); + if (!ptr) + return ERR_BUF; + do { + unsigned int a = strtoul(ptr + 1, &ptr, 10); + unsigned int b = strtoul(ptr + 1, &ptr, 10); + unsigned int c = strtoul(ptr + 1, &ptr, 10); + unsigned int d = strtoul(ptr + 1, &ptr, 10); + IP4_ADDR(&data_server, a, b, c, d); + } while (0); + data_port = strtoul(ptr + 1, &ptr, 10) << 8; + data_port |= strtoul(ptr + 1, &ptr, 10) & 255; + if (*ptr != ')') + return ERR_BUF; + + // Open data session + tcp_arg(s->data_pcb, s); + tcp_err(s->data_pcb, lwftp_data_err); + tcp_recv(s->data_pcb, lwftp_data_recv); + tcp_sent(s->data_pcb, lwftp_data_sent); + error = tcp_connect(s->data_pcb, &data_server, data_port, + lwftp_data_connected); + return error; +} + +/** Send a message to control connection + * @param pointer to lwftp session data + * @param pointer to message string + */ +static err_t lwftp_send_msg(lwftp_session_t *s, const char *msg, size_t len) { + err_t error; + + LWIP_DEBUGF(LWFTP_TRACE,("lwftp:sending %s",msg)); + error = tcp_write(s->control_pcb, msg, len, 0); + if (error != ERR_OK) { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:cannot write (%s)\n",lwip_strerr(error))); + } + return error; +} + +/** Close data connection + * @param pointer to lwftp session data + * @param result to pass to callback fn (if called) + */ +static void lwftp_data_close(lwftp_session_t *s, int result) { + if (s->data_pcb) { + lwftp_pcb_close(s->data_pcb); + s->data_pcb = NULL; + } + if (s->done_fn) { + s->done_fn(s->handle, result); + } +} + +/** Close control connection + * @param pointer to lwftp session data + * @param result to pass to callback fn (if called) + */ +static void lwftp_control_close(lwftp_session_t *s, int result) { + if (s->data_pcb) { + lwftp_pcb_close(s->data_pcb); + s->data_pcb = NULL; + } + if (s->control_pcb) { + lwftp_pcb_close(s->control_pcb); + s->control_pcb = NULL; + } + s->control_state = LWFTP_CLOSED; + if ((result >= 0) && s->done_fn) { + s->done_fn(s->handle, result); + } +} + +/** Main client state machine + * @param pointer to lwftp session data + * @param pointer to PCB + * @param pointer to incoming data + */ +static void lwftp_control_process(lwftp_session_t *s, struct tcp_pcb *tpcb, + struct pbuf *p) { + uint response = 0; + int result = LWFTP_RESULT_ERR_SRVR_RESP; + + // Try to get response number + if (p) { + response = strtoul(p->payload, NULL, 10); + LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:got response %d\n",response)); + } + + switch (s->control_state) { + case LWFTP_CONNECTED: + if (response > 0) { + if (response == 220) { + lwftp_send_msg(s, PTRNLEN("USER ")); + lwftp_send_msg(s, s->user, strlen(s->user)); + lwftp_send_msg(s, PTRNLEN("\r\n")); + s->control_state = LWFTP_USER_SENT; + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + case LWFTP_USER_SENT: + if (response > 0) { + if (response == 331) { + lwftp_send_msg(s, PTRNLEN("PASS ")); + lwftp_send_msg(s, s->pass, strlen(s->pass)); + lwftp_send_msg(s, PTRNLEN("\r\n")); + s->control_state = LWFTP_PASS_SENT; + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + case LWFTP_PASS_SENT: + if (response > 0) { + if (response == 230) { + s->control_state = LWFTP_LOGGED; + LWIP_DEBUGF(LWFTP_STATE, ("lwftp: now logged in\n")); + if (s->done_fn) { + s->done_fn(s->handle, LWFTP_RESULT_LOGGED); + } + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + case LWFTP_TYPE_SENT: + if (response > 0) { + if (response == 200) { + lwftp_send_msg(s, PTRNLEN("PASV\r\n")); + s->control_state = LWFTP_PASV_SENT; + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + case LWFTP_PASV_SENT: + if (response > 0) { + if (response == 227) { + lwftp_data_open(s, p); + switch (s->target_state) { + case LWFTP_STOR_SENT: + lwftp_send_msg(s, PTRNLEN("STOR ")); + break; + case LWFTP_RETR_SENT: + lwftp_send_msg(s, PTRNLEN("RETR ")); + break; + default: + LOG_ERROR("Unexpected internal state"); + s->target_state = LWFTP_QUIT; + } + lwftp_send_msg(s, s->remote_path, strlen(s->remote_path)); + lwftp_send_msg(s, PTRNLEN("\r\n")); + s->control_state = s->target_state; + } else { + s->control_state = LWFTP_QUIT; + } + } + break; + case LWFTP_RETR_SENT: + if (response > 0) { + if (response == 150) { + s->control_state = LWFTP_XFERING; + } else if (response == 550) { + s->control_state = LWFTP_DATAEND; + result = LWFTP_RESULT_ERR_FILENAME; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: Failed to open file '%s'\n", s->remote_path)); + } else { + s->control_state = LWFTP_DATAEND; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response)); + } + } + break; + case LWFTP_STOR_SENT: + if (response > 0) { + if (response == 150) { + s->control_state = LWFTP_XFERING; + lwftp_data_sent(s, NULL, 0); + } else { + s->control_state = LWFTP_DATAEND; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 150, received %d\n",response)); + } + } + break; + case LWFTP_XFERING: + if (response > 0) { + if (response == 226) { + result = LWFTP_RESULT_OK; + } else { + result = LWFTP_RESULT_ERR_CLOSED; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 226, received %d\n",response)); + } + s->control_state = LWFTP_DATAEND; + } + break; + case LWFTP_DATAEND: + LOG_TRACE("forced end of data session"); + break; + case LWFTP_QUIT_SENT: + if (response > 0) { + if (response == 221) { + result = LWFTP_RESULT_OK; + } else { + result = LWFTP_RESULT_ERR_UNKNOWN; + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:expected 221, received %d\n",response)); + } + s->control_state = LWFTP_CLOSING; + } + break; + default: + LWIP_DEBUGF(LWFTP_SEVERE, ("lwftp:unhandled state (%d)\n",s->control_state)); + } + + // Free receiving pbuf if any + if (p) { + pbuf_free(p); + } + + // Handle second step in state machine + switch (s->control_state) { + case LWFTP_DATAEND: + lwftp_data_close(s, result); + s->control_state = LWFTP_LOGGED; + break; + case LWFTP_QUIT: + lwftp_send_msg(s, PTRNLEN("QUIT\r\n")); + tcp_output(s->control_pcb); + s->control_state = LWFTP_QUIT_SENT; + break; + case LWFTP_CLOSING: + // this function frees s, no use of s is allowed after + lwftp_control_close(s, result); + break; + default: + ; + } +} + +/** Start a RETR data session + * @param pointer to lwftp session + */ +static void lwftp_start_RETR(void *arg) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (s->control_state == LWFTP_LOGGED) { + lwftp_send_msg(s, PTRNLEN("TYPE I\r\n")); + s->control_state = LWFTP_TYPE_SENT; + s->target_state = LWFTP_RETR_SENT; + } else { + LOG_ERROR("Unexpected condition"); + if (s->done_fn) + s->done_fn(s->handle, LWFTP_RESULT_ERR_INTERNAL); + } +} + +/** Start a STOR data session + * @param pointer to lwftp session + */ +static void lwftp_start_STOR(void *arg) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (s->control_state == LWFTP_LOGGED) { + lwftp_send_msg(s, PTRNLEN("TYPE I\r\n")); + s->control_state = LWFTP_TYPE_SENT; + s->target_state = LWFTP_STOR_SENT; + } else { + LOG_ERROR("Unexpected condition"); + if (s->done_fn) + s->done_fn(s->handle, LWFTP_RESULT_ERR_INTERNAL); + } +} + +/** Send QUIT to terminate control session + * @param pointer to lwftp session + */ +static void lwftp_send_QUIT(void *arg) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (s->control_pcb) { + lwftp_send_msg(s, PTRNLEN("QUIT\r\n")); + tcp_output(s->control_pcb); + s->control_state = LWFTP_QUIT_SENT; + } +} + +/** Handle control connection incoming data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param pointer to incoming pbuf + * @param state of incoming process + */ +static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, + err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (err == ERR_OK) { + if (p) { + tcp_recved(tpcb, p->tot_len); + lwftp_control_process(s, tpcb, p); + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n")); + lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED); + } + } else { + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:failed to receive (%s)\n",lwip_strerr(err))); + lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN); + } + return err; +} + +/** Handle control connection acknowledge of sent data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) { + LWIP_DEBUGF(LWFTP_TRACE, ("lwftp:successfully sent %d bytes\n",len)); + return ERR_OK; +} + +/** Handle control connection error + * @param pointer to lwftp session data + * @param state of connection + */ +static void lwftp_control_err(void *arg, err_t err) { + LWIP_UNUSED_ARG(err); + if (arg != NULL) { + lwftp_session_t *s = (lwftp_session_t*) arg; + int result; + if (s->control_state == LWFTP_CLOSED) { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:failed to connect to server (%s)\n",lwip_strerr(err))); + result = LWFTP_RESULT_ERR_CONNECT; + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:connection closed by remote host\n")); + result = LWFTP_RESULT_ERR_CLOSED; + } + s->control_pcb = NULL; // No need to de-allocate PCB + lwftp_control_close(s, result); + } +} + +/** Process newly connected PCB + * @param pointer to lwftp session data + * @param pointer to PCB + * @param state of connection + */ +static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (err == ERR_OK) { + LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected to server\n")); + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:err in control_connected (%s)\n", lwip_strerr(err))); + if (s->done_fn) { + s->done_fn(s->handle, LWFTP_RESULT_ERR_CONNECT); // 연결 실패 상태 전달 + } + } + return err; +} + +/** Open a control session + * @param Session structure + */ +err_t lwftp_connect(lwftp_session_t *s) { + err_t error; + enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN; + + // Check user supplied data + if ((s->control_state != LWFTP_CLOSED) || s->control_pcb || s->data_pcb + || !s->user || !s->pass) { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid control session\n")); + retval = LWFTP_RESULT_ERR_ARGUMENT; + goto exit; + } + // Get sessions pcb + s->control_pcb = tcp_new(); + if (!s->control_pcb) { + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc control_pcb (low memory?)\n")); + retval = LWFTP_RESULT_ERR_MEMORY; + goto exit; + } + // Open control session + tcp_arg(s->control_pcb, s); + tcp_err(s->control_pcb, lwftp_control_err); + tcp_recv(s->control_pcb, lwftp_control_recv); + tcp_sent(s->control_pcb, lwftp_control_sent); + error = tcp_connect(s->control_pcb, &s->server_ip, s->server_port, + lwftp_control_connected); + if (error == ERR_OK) { + retval = LWFTP_RESULT_INPROGRESS; + goto exit; + } + + // Release pcbs in case of failure + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot connect control_pcb (%s)\n", lwip_strerr(error))); + lwftp_control_close(s, -1); + + exit: if (s->done_fn) + s->done_fn(s->handle, retval); + return retval; +} + +/** Retrieve data from a remote file + * @param Session structure + */ +err_t lwftp_retrieve(lwftp_session_t *s) { + err_t error; + enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN; + + // Check user supplied data + if ((s->control_state != LWFTP_LOGGED) || !s->remote_path || s->data_pcb) { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid session data\n")); + retval = LWFTP_RESULT_ERR_ARGUMENT; + goto exit; + } + // Get data pcb + s->data_pcb = tcp_new(); + if (!s->data_pcb) { + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc data_pcb (low memory?)\n")); + retval = LWFTP_RESULT_ERR_MEMORY; + goto exit; + } + // Initiate transfer + error = tcpip_callback(lwftp_start_RETR, s); + if (error == ERR_OK) { + retval = LWFTP_RESULT_INPROGRESS; + } else { + LOG_ERROR("cannot start RETR (%s)", lwip_strerr(error)); + retval = LWFTP_RESULT_ERR_INTERNAL; + } + + exit: if (s->done_fn) + s->done_fn(s->handle, retval); + return retval; +} + +/** Store data to a remote file + * @param Session structure + */ +err_t lwftp_store(lwftp_session_t *s) { + err_t error; + enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN; + + // Check user supplied data + if ((s->control_state != LWFTP_LOGGED) || !s->remote_path || s->data_pcb) { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp:invalid session data\n")); + retval = LWFTP_RESULT_ERR_ARGUMENT; + goto exit; + } + // Get data pcb + s->data_pcb = tcp_new(); + if (!s->data_pcb) { + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp:cannot alloc data_pcb (low memory?)\n")); + retval = LWFTP_RESULT_ERR_MEMORY; + goto exit; + } + // Initiate transfer + error = tcpip_callback(lwftp_start_STOR, s); + if (error == ERR_OK) { + retval = LWFTP_RESULT_INPROGRESS; + } else { + LOG_ERROR("cannot start STOR (%s)", lwip_strerr(error)); + retval = LWFTP_RESULT_ERR_INTERNAL; + } + + exit: if (s->done_fn) + s->done_fn(s->handle, retval); + return retval; +} + +/** Terminate FTP session + * @param Session structure + */ +//void lwftp_close(lwftp_session_t *s) +//{ +// err_t error; +// +// // Nothing to do when already closed +// if ( s->control_state == LWFTP_CLOSED ) return; +// +// // Initiate transfer +// error = tcpip_callback(lwftp_send_QUIT, s); +// if ( error != ERR_OK ) { +// // This is a critical error, try to close anyway +// // polling process may save us +// LOG_ERROR("cannot request for close"); +// s->control_state = LWFTP_QUIT; +// } +//} +void lwftp_close(lwftp_session_t *s) { + if (s->control_state == LWFTP_CLOSED) + return; + if (s->control_pcb != NULL) { + lwftp_send_msg(s, "QUIT\r\n", strlen("QUIT\r\n")); + tcp_output(s->control_pcb); + + lwftp_pcb_close(s->control_pcb); + s->control_pcb = NULL; + } + if (s->data_pcb != NULL) { + lwftp_pcb_close(s->data_pcb); + s->data_pcb = NULL; + } + s->control_state = LWFTP_CLOSED; +} diff --git a/LWFTP/_lwftp.h b/LWFTP/_lwftp.h new file mode 100644 index 0000000..9270884 --- /dev/null +++ b/LWFTP/_lwftp.h @@ -0,0 +1,109 @@ +/* + * lwftp.h : a lightweight FTP client using raw API of LWIP + * + * Copyright (c) 2014 GEZEDO + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Laurent GONZALEZ + * + */ + +#ifndef LWFTP_H +#define LWFTP_H + +#include "lwip/opt.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum lwftp_results { + LWFTP_RESULT_OK=0, + LWFTP_RESULT_INPROGRESS, + LWFTP_RESULT_LOGGED, + LWFTP_RESULT_ERR_UNKNOWN, /** Unknown error */ + LWFTP_RESULT_ERR_ARGUMENT, /** Wrong argument */ + LWFTP_RESULT_ERR_MEMORY, /** Out of memory */ + LWFTP_RESULT_ERR_CONNECT, /** Connection to server failed */ + LWFTP_RESULT_ERR_HOSTNAME, /** Failed to resolve server hostname */ + LWFTP_RESULT_ERR_CLOSED, /** Connection unexpectedly closed by remote server */ + LWFTP_RESULT_ERR_TIMEOUT, /** Connection timed out (server didn't respond in time) */ + LWFTP_RESULT_ERR_SRVR_RESP, /** Server responded with an unknown response code */ + LWFTP_RESULT_ERR_INTERNAL, /** Internal network stack error */ + LWFTP_RESULT_ERR_LOCAL, /** Local storage error */ + LWFTP_RESULT_ERR_FILENAME /** Remote host could not find file */ +}; + +/** LWFTP control connection state */ +typedef enum { + LWFTP_CLOSED=0, + LWFTP_CONNECTED, + LWFTP_USER_SENT, + LWFTP_PASS_SENT, + LWFTP_LOGGED, + LWFTP_TYPE_SENT, + LWFTP_PASV_SENT, + LWFTP_RETR_SENT, + LWFTP_STOR_SENT, + LWFTP_XFERING, + LWFTP_DATAEND, + LWFTP_QUIT, + LWFTP_QUIT_SENT, + LWFTP_CLOSING, +} lwftp_state_t; + +/** LWFTP session structure */ +typedef struct { + // User interface + ip_addr_t server_ip; + u16_t server_port; + const char *remote_path; + const char *user; + const char *pass; + void *handle; + uint (*data_source)(void*, const char**, uint); + uint (*data_sink)(void*, const char*, uint); + void (*done_fn)(void*, int); + uint timeout; + // Internal data + lwftp_state_t control_state; + lwftp_state_t target_state; + lwftp_state_t data_state; + struct tcp_pcb *control_pcb; + struct tcp_pcb *data_pcb; +} lwftp_session_t; + +// LWFTP API +err_t lwftp_connect(lwftp_session_t *s); +err_t lwftp_store(lwftp_session_t *s); +err_t lwftp_retrieve(lwftp_session_t *s); +void lwftp_close(lwftp_session_t *s); + +#ifdef __cplusplus +} +#endif + +#endif // LWFTP_H diff --git a/LWFTP/lwftp.c b/LWFTP/lwftp.c new file mode 100644 index 0000000..e017475 --- /dev/null +++ b/LWFTP/lwftp.c @@ -0,0 +1,78 @@ +/* + * lwftp_mod.c + * + * Created on: Feb 14, 2024 + * Author: SeungJu Lim + */ +#include +#include +#include "lwip/tcp.h" +#include "lwip/tcpip.h" + +/** Enable debugging for LWFTP */ +#ifndef LWFTP_DEBUG +#define LWFTP_DEBUG LWIP_DBG_ON +#endif + +#define LWFTP_TRACE (LWFTP_DEBUG|LWIP_DBG_TRACE) +#define LWFTP_STATE (LWFTP_DEBUG|LWIP_DBG_STATE) +#define LWFTP_WARNING (LWFTP_DEBUG|LWIP_DBG_LEVEL_WARNING) +#define LWFTP_SERIOUS (LWFTP_DEBUG|LWIP_DBG_LEVEL_SERIOUS) +#define LWFTP_SEVERE (LWFTP_DEBUG|LWIP_DBG_LEVEL_SEVERE) + +#define LOG_ERROR(format, ...) printf("ERROR: " format "\n", ##__VA_ARGS__) +#define LOG_TRACE(format, ...) printf("TRACE: " format "\n", ##__VA_ARGS__) + +#define PTRNLEN(s) s,(sizeof(s)-1) + + +err_t lwftp_connect(lwftp_session_t *s) { + err_t error; + enum lwftp_results retval = LWFTP_RESULT_ERR_UNKNOWN; + + // Check user supplied data + if ((s->control_state != LWFTP_CLOSED) || s->control_pcb || s->data_pcb + || !s->user || !s->pass) { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: invalid control session\n")); + retval = LWFTP_RESULT_ERR_ARGUMENT; + goto exit; + } + // Get sessions pcb + s->control_pcb = tcp_new(); + if (!s->control_pcb) { + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp: cannot alloc control_pcb (low memory?)\n")); + retval = LWFTP_RESULT_ERR_MEMORY; + goto exit; + } + // Open control session + tcp_arg(s->control_pcb, s); + tcp_err(s->control_pcb, lwftp_control_err); + tcp_recv(s->control_pcb, lwftp_control_recv); + tcp_sent(s->control_pcb, lwftp_control_sent); + error = tcp_connect(s->control_pcb, &s->server_ip, s->server_port, + lwftp_control_connected); + if (error == ERR_OK) { + retval = LWFTP_RESULT_INPROGRESS; + goto exit; + } + + // Release pcbs in case of failure + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp: cannot connect control_pcb (%s)\n", lwip_strerr(error))); + lwftp_control_close(s, -1); + + exit: if (s->done_fn) + s->done_fn(s->handle, retval); + + return retval; +} + +// +//err_t lwftp_store(lwftp_session_t *s) { +// +//} +//err_t lwftp_retrieve(lwftp_session_t *s) { +// +//} +//err_t lwftp_close(lwftp_session_t *s) { +// +//} diff --git a/LWFTP/lwftp.h b/LWFTP/lwftp.h new file mode 100644 index 0000000..1a28986 --- /dev/null +++ b/LWFTP/lwftp.h @@ -0,0 +1,85 @@ +/* + * lwftp_mod.h + * + * Created on: Feb 14, 2024 + * Author: SeungJu Lim + */ + + +#ifndef LWFTP_H +#define LWFTP_H + +#include "lwip/opt.h" +#include "lwip/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum lwftp_results { + LWFTP_RESULT_OK=0, + LWFTP_RESULT_INPROGRESS, + LWFTP_RESULT_LOGGED, + LWFTP_RESULT_ERR_UNKNOWN, /** Unknown error */ + LWFTP_RESULT_ERR_ARGUMENT, /** Wrong argument */ + LWFTP_RESULT_ERR_MEMORY, /** Out of memory */ + LWFTP_RESULT_ERR_CONNECT, /** Connection to server failed */ + LWFTP_RESULT_ERR_HOSTNAME, /** Failed to resolve server hostname */ + LWFTP_RESULT_ERR_CLOSED, /** Connection unexpectedly closed by remote server */ + LWFTP_RESULT_ERR_TIMEOUT, /** Connection timed out (server didn't respond in time) */ + LWFTP_RESULT_ERR_SRVR_RESP, /** Server responded with an unknown response code */ + LWFTP_RESULT_ERR_INTERNAL, /** Internal network stack error */ + LWFTP_RESULT_ERR_LOCAL, /** Local storage error */ + LWFTP_RESULT_ERR_FILENAME /** Remote host could not find file */ +}; + +/** LWFTP control connection state */ +typedef enum { + LWFTP_CLOSED=0, + LWFTP_CONNECTED, + LWFTP_USER_SENT, + LWFTP_PASS_SENT, + LWFTP_LOGGED, + LWFTP_TYPE_SENT, + LWFTP_PASV_SENT, + LWFTP_RETR_SENT, + LWFTP_STOR_SENT, + LWFTP_XFERING, + LWFTP_DATAEND, + LWFTP_QUIT, + LWFTP_QUIT_SENT, + LWFTP_CLOSING, +} lwftp_state_t; + +/** LWFTP session structure */ +typedef struct { + // User interface + ip_addr_t server_ip; + u16_t server_port; + const char *remote_path; + const char *user; + const char *pass; + void *handle; + uint (*data_source)(void*, const char**, uint); + uint (*data_sink)(void*, const char*, uint); + void (*done_fn)(void*, int); + uint timeout; + // Internal data + lwftp_state_t control_state; + lwftp_state_t target_state; + lwftp_state_t data_state; + struct tcp_pcb *control_pcb; + struct tcp_pcb *data_pcb; +} lwftp_session_t; + +// LWFTP API +err_t lwftp_connect(lwftp_session_t *s); +err_t lwftp_store(lwftp_session_t *s); +err_t lwftp_retrieve(lwftp_session_t *s); +void lwftp_close(lwftp_session_t *s); + +#ifdef __cplusplus +} +#endif + +#endif // LWFTP_H diff --git a/LWFTP/lwftp_control.c b/LWFTP/lwftp_control.c new file mode 100644 index 0000000..76275e7 --- /dev/null +++ b/LWFTP/lwftp_control.c @@ -0,0 +1,120 @@ +/* + * lwftp_mod.h + * + * Created on: Feb 14, 2024 + * Author: SeungJu Lim + */ + +/** Process newly connected PCB + * @param pointer to lwftp session data + * @param pointer to PCB + * @param state of connection + */ +static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (err == ERR_OK) { + LWIP_DEBUGF(LWFTP_STATE, ("lwftp:connected to server\n")); + s->control_state = LWFTP_CONNECTED; + } else { + LWIP_DEBUGF(LWFTP_WARNING, + ("lwftp:err in control_connected (%s)\n", lwip_strerr(err))); + } + return err; +} + +/** Close control connection + * @param pointer to lwftp session data + * @param result to pass to callback fn (if called) + */ +static void lwftp_control_close(lwftp_session_t *s, int result) { + if (s->data_pcb) { + lwftp_pcb_close(s->data_pcb); + s->data_pcb = NULL; + } + if (s->control_pcb) { + lwftp_pcb_close(s->control_pcb); + s->control_pcb = NULL; + } + s->control_state = LWFTP_CLOSED; + if ((result >= 0) && s->done_fn) { + s->done_fn(s->handle, result); + } +} + +/** Process newly connected PCB + * @param pointer to lwftp session data + * @param pointer to PCB + * @param state of connection + */ +static err_t lwftp_control_connected(void *arg, struct tcp_pcb *tpcb, err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (err == ERR_OK) { + LWIP_DEBUGF(LWFTP_STATE, ("lwftp: connected to server\n")); + s->control_state = LWFTP_CONNECTED; + } else { + LWIP_DEBUGF(LWFTP_WARNING, + ("lwftp: err in control_connected (%s)\n", lwip_strerr(err))); + } + return err; +} + +/** Handle control connection error + * @param pointer to lwftp session data + * @param state of connection + */ +static void lwftp_control_err(void *arg, err_t err) { + LWIP_UNUSED_ARG(err); + if (arg != NULL) { + lwftp_session_t *s = (lwftp_session_t*) arg; + int result; + if (s->control_state == LWFTP_CLOSED) { + LWIP_DEBUGF(LWFTP_WARNING, + ("lwftp: failed to connect to server (%s)\n", lwip_strerr(err))); + result = LWFTP_RESULT_ERR_CONNECT; + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n")); + result = LWFTP_RESULT_ERR_CLOSED; + } + s->control_pcb = NULL; // No need to de-allocate PCB + lwftp_control_close(s, result); + } +} + +/** Handle control connection incoming data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param pointer to incoming pbuf + * @param state of incoming process + */ +static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, + err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (err == ERR_OK) { + if (p) { + tcp_recved(tpcb, p->tot_len); + lwftp_control_process(s, tpcb, p); + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n")); + lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED); + } + } else { + LWIP_DEBUGF(LWFTP_SERIOUS, + ("lwftp: failed to receive (%s)\n", lwip_strerr(err))); + lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN); + } + return err; +} + +/** Handle control connection acknowledge of sent data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) { + LWIP_DEBUGF(LWFTP_TRACE, ("lwftp: successfully sent %d bytes\n", len)); + return ERR_OK; +} + diff --git a/LWFTP/lwftp_pcb.c b/LWFTP/lwftp_pcb.c new file mode 100644 index 0000000..3fb952d --- /dev/null +++ b/LWFTP/lwftp_pcb.c @@ -0,0 +1,82 @@ +/* + * lwftp_mod.h + * + * Created on: Feb 14, 2024 + * Author: SeungJu Lim + */ + +/** Handle control connection error + * @param pointer to lwftp session data + * @param state of connection + */ +static void lwftp_control_err(void *arg, err_t err) { + LWIP_UNUSED_ARG(err); + if (arg != NULL) { + lwftp_session_t *s = (lwftp_session_t*) arg; + int result; + if (s->control_state == LWFTP_CLOSED) { + LWIP_DEBUGF(LWFTP_WARNING, + ("lwftp: failed to connect to server (%s)\n", lwip_strerr(err))); + result = LWFTP_RESULT_ERR_CONNECT; + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n")); + result = LWFTP_RESULT_ERR_CLOSED; + } + s->control_pcb = NULL; // No need to de-allocate PCB + lwftp_control_close(s, result); + } +} + +/** Handle control connection incoming data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param pointer to incoming pbuf + * @param state of incoming process + */ +static err_t lwftp_control_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, + err_t err) { + lwftp_session_t *s = (lwftp_session_t*) arg; + + if (err == ERR_OK) { + if (p) { + tcp_recved(tpcb, p->tot_len); + lwftp_control_process(s, tpcb, p); + } else { + LWIP_DEBUGF(LWFTP_WARNING, ("lwftp: connection closed by remote host\n")); + lwftp_control_close(s, LWFTP_RESULT_ERR_CLOSED); + } + } else { + LWIP_DEBUGF(LWFTP_SERIOUS, ("lwftp: failed to receive (%s)\n",lwip_strerr(err))); + lwftp_control_close(s, LWFTP_RESULT_ERR_UNKNOWN); + } + return err; +} + +/** Handle control connection acknowledge of sent data + * @param pointer to lwftp session data + * @param pointer to PCB + * @param number of bytes sent + */ +static err_t lwftp_control_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) { + LWIP_DEBUGF(LWFTP_TRACE, ("lwftp: successfully sent %d bytes\n",len)); + return ERR_OK; +} + +/** Close control connection + * @param pointer to lwftp session data + * @param result to pass to callback fn (if called) + */ +static void lwftp_control_close(lwftp_session_t *s, int result) { + if (s->data_pcb) { + lwftp_pcb_close(s->data_pcb); + s->data_pcb = NULL; + } + if (s->control_pcb) { + lwftp_pcb_close(s->control_pcb); + s->control_pcb = NULL; + } + s->control_state = LWFTP_CLOSED; + if ((result >= 0) && s->done_fn) { + s->done_fn(s->handle, result); + } +} diff --git a/LWIP/App/lwip.c b/LWIP/App/lwip.c new file mode 100644 index 0000000..52595a3 --- /dev/null +++ b/LWIP/App/lwip.c @@ -0,0 +1,252 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : LWIP.c + * Description : This file provides initialization code for LWIP + * middleWare. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "lwip.h" +#include "lwip/init.h" +#include "lwip/netif.h" +#if defined ( __CC_ARM ) /* MDK ARM Compiler */ +#include "lwip/sio.h" +#endif /* MDK ARM Compiler */ +#include "ethernetif.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/* Private function prototypes -----------------------------------------------*/ +static void ethernet_link_status_updated(struct netif *netif); +static void Ethernet_Link_Periodic_Handle(struct netif *netif); +/* ETH Variables initialization ----------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +uint32_t EthernetLinkTimer; + +/* Variables Initialization */ +struct netif gnetif; +ip4_addr_t ipaddr; +ip4_addr_t netmask; +ip4_addr_t gw; +uint8_t IP_ADDRESS[4]; +uint8_t NETMASK_ADDRESS[4]; +uint8_t GATEWAY_ADDRESS[4]; + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + +/** + * LwIP initialization function + */ +void MX_LWIP_Init(void) +{ + /* IP addresses initialization */ + IP_ADDRESS[0] = 192; + IP_ADDRESS[1] = 168; + IP_ADDRESS[2] = 0; + IP_ADDRESS[3] = 120; + NETMASK_ADDRESS[0] = 255; + NETMASK_ADDRESS[1] = 255; + NETMASK_ADDRESS[2] = 255; + NETMASK_ADDRESS[3] = 0; + GATEWAY_ADDRESS[0] = 0; + GATEWAY_ADDRESS[1] = 0; + GATEWAY_ADDRESS[2] = 0; + GATEWAY_ADDRESS[3] = 0; + +/* USER CODE BEGIN IP_ADDRESSES */ +/* USER CODE END IP_ADDRESSES */ + + /* Initilialize the LwIP stack without RTOS */ + lwip_init(); + + /* IP addresses initialization without DHCP (IPv4) */ + IP4_ADDR(&ipaddr, IP_ADDRESS[0], IP_ADDRESS[1], IP_ADDRESS[2], IP_ADDRESS[3]); + IP4_ADDR(&netmask, NETMASK_ADDRESS[0], NETMASK_ADDRESS[1] , NETMASK_ADDRESS[2], NETMASK_ADDRESS[3]); + IP4_ADDR(&gw, GATEWAY_ADDRESS[0], GATEWAY_ADDRESS[1], GATEWAY_ADDRESS[2], GATEWAY_ADDRESS[3]); + + /* add the network interface (IPv4/IPv6) without RTOS */ + netif_add(&gnetif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, ðernet_input); + + /* Registers the default network interface */ + netif_set_default(&gnetif); + + /* We must always bring the network interface up connection or not... */ + netif_set_up(&gnetif); + + /* Set the link callback function, this function is called on change of link status*/ + netif_set_link_callback(&gnetif, ethernet_link_status_updated); + + /* Create the Ethernet link handler thread */ + +/* USER CODE BEGIN 3 */ + +/* USER CODE END 3 */ +} + +#ifdef USE_OBSOLETE_USER_CODE_SECTION_4 +/* Kept to help code migration. (See new 4_1, 4_2... sections) */ +/* Avoid to use this user section which will become obsolete. */ +/* USER CODE BEGIN 4 */ +/* USER CODE END 4 */ +#endif + +/** + * @brief Ethernet Link periodic check + * @param netif + * @retval None + */ +static void Ethernet_Link_Periodic_Handle(struct netif *netif) +{ +/* USER CODE BEGIN 4_4_1 */ +/* USER CODE END 4_4_1 */ + + /* Ethernet Link every 100ms */ + if (HAL_GetTick() - EthernetLinkTimer >= 100) + { + EthernetLinkTimer = HAL_GetTick(); + ethernet_link_check_state(netif); + } +/* USER CODE BEGIN 4_4 */ +/* USER CODE END 4_4 */ +} + +/** + * ---------------------------------------------------------------------- + * Function given to help user to continue LwIP Initialization + * Up to user to complete or change this function ... + * Up to user to call this function in main.c in while (1) of main(void) + *----------------------------------------------------------------------- + * Read a received packet from the Ethernet buffers + * Send it to the lwIP stack for handling + * Handle timeouts if LWIP_TIMERS is set and without RTOS + * Handle the llink status if LWIP_NETIF_LINK_CALLBACK is set and without RTOS + */ +void MX_LWIP_Process(void) +{ +/* USER CODE BEGIN 4_1 */ +/* USER CODE END 4_1 */ + ethernetif_input(&gnetif); + +/* USER CODE BEGIN 4_2 */ +/* USER CODE END 4_2 */ + /* Handle timeouts */ + sys_check_timeouts(); + + Ethernet_Link_Periodic_Handle(&gnetif); + +/* USER CODE BEGIN 4_3 */ +/* USER CODE END 4_3 */ +} + +/** + * @brief Notify the User about the network interface config status + * @param netif: the network interface + * @retval None + */ +static void ethernet_link_status_updated(struct netif *netif) +{ + if (netif_is_up(netif)) + { +/* USER CODE BEGIN 5 */ +/* USER CODE END 5 */ + } + else /* netif is down */ + { +/* USER CODE BEGIN 6 */ +/* USER CODE END 6 */ + } +} + +#if defined ( __CC_ARM ) /* MDK ARM Compiler */ +/** + * Opens a serial device for communication. + * + * @param devnum device number + * @return handle to serial device if successful, NULL otherwise + */ +sio_fd_t sio_open(u8_t devnum) +{ + sio_fd_t sd; + +/* USER CODE BEGIN 7 */ + sd = 0; // dummy code +/* USER CODE END 7 */ + + return sd; +} + +/** + * Sends a single character to the serial device. + * + * @param c character to send + * @param fd serial device handle + * + * @note This function will block until the character can be sent. + */ +void sio_send(u8_t c, sio_fd_t fd) +{ +/* USER CODE BEGIN 8 */ +/* USER CODE END 8 */ +} + +/** + * Reads from the serial device. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received - may be 0 if aborted by sio_read_abort + * + * @note This function will block until data can be received. The blocking + * can be cancelled by calling sio_read_abort(). + */ +u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len) +{ + u32_t recved_bytes; + +/* USER CODE BEGIN 9 */ + recved_bytes = 0; // dummy code +/* USER CODE END 9 */ + return recved_bytes; +} + +/** + * Tries to read from the serial device. Same as sio_read but returns + * immediately if no data is available and never blocks. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received + */ +u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len) +{ + u32_t recved_bytes; + +/* USER CODE BEGIN 10 */ + recved_bytes = 0; // dummy code +/* USER CODE END 10 */ + return recved_bytes; +} +#endif /* MDK ARM Compiler */ + diff --git a/LWIP/App/lwip.h b/LWIP/App/lwip.h new file mode 100644 index 0000000..b14adc0 --- /dev/null +++ b/LWIP/App/lwip.h @@ -0,0 +1,76 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : LWIP.h + * Description : This file provides code for the configuration + * of the LWIP. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ************************************************************************* + + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __mx_lwip_H +#define __mx_lwip_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "netif/etharp.h" +#include "lwip/dhcp.h" +#include "lwip/netif.h" +#include "lwip/timeouts.h" +#include "ethernetif.h" + +/* Includes for RTOS ---------------------------------------------------------*/ +#if WITH_RTOS +#include "lwip/tcpip.h" +#endif /* WITH_RTOS */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* Global Variables ----------------------------------------------------------*/ +extern ETH_HandleTypeDef heth; + +/* LWIP init function */ +void MX_LWIP_Init(void); + +#if !WITH_RTOS +/* USER CODE BEGIN 1 */ +/* Function defined in lwip.c to: + * - Read a received packet from the Ethernet buffers + * - Send it to the lwIP stack for handling + * - Handle timeouts if NO_SYS_NO_TIMERS not set + */ +void MX_LWIP_Process(void); + +/* USER CODE END 1 */ +#endif /* WITH_RTOS */ + +#ifdef __cplusplus +} +#endif +#endif /*__ mx_lwip_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/LWIP/Target/ethernetif.c b/LWIP/Target/ethernetif.c new file mode 100644 index 0000000..2b51dc5 --- /dev/null +++ b/LWIP/Target/ethernetif.c @@ -0,0 +1,766 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : ethernetif.c + * Description : This file provides code for the configuration + * of the ethernetif.c MiddleWare. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/timeouts.h" +#include "netif/ethernet.h" +#include "netif/etharp.h" +#include "lwip/ethip6.h" +#include "ethernetif.h" +#include "lan8742.h" +#include + +/* Within 'USER CODE' section, code will be kept by default at each generation */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* Private define ------------------------------------------------------------*/ + +/* Network interface name */ +#define IFNAME0 's' +#define IFNAME1 't' + +/* ETH Setting */ +#define ETH_DMA_TRANSMIT_TIMEOUT ( 20U ) +#define ETH_TX_BUFFER_MAX ((ETH_TX_DESC_CNT) * 2U) +/* ETH_RX_BUFFER_SIZE parameter is defined in lwipopts.h */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/* Private variables ---------------------------------------------------------*/ +/* +@Note: This interface is implemented to operate in zero-copy mode only: + - Rx buffers will be allocated from LwIP stack memory heap, + then passed to ETH HAL driver. + - Tx buffers will be allocated from LwIP stack memory heap, + then passed to ETH HAL driver. + +@Notes: + 1.a. ETH DMA Rx descriptors must be contiguous, the default count is 4, + to customize it please redefine ETH_RX_DESC_CNT in ETH GUI (Rx Descriptor Length) + so that updated value will be generated in stm32xxxx_hal_conf.h + 1.b. ETH DMA Tx descriptors must be contiguous, the default count is 4, + to customize it please redefine ETH_TX_DESC_CNT in ETH GUI (Tx Descriptor Length) + so that updated value will be generated in stm32xxxx_hal_conf.h + + 2.a. Rx Buffers number must be between ETH_RX_DESC_CNT and 2*ETH_RX_DESC_CNT + 2.b. Rx Buffers must have the same size: ETH_RX_BUFFER_SIZE, this value must + passed to ETH DMA in the init field (heth.Init.RxBuffLen) + 2.c The RX Ruffers addresses and sizes must be properly defined to be aligned + to L1-CACHE line size (32 bytes). +*/ + +/* Data Type Definitions */ +typedef enum +{ + RX_ALLOC_OK = 0x00, + RX_ALLOC_ERROR = 0x01 +} RxAllocStatusTypeDef; + +typedef struct +{ + struct pbuf_custom pbuf_custom; + uint8_t buff[(ETH_RX_BUFFER_SIZE + 31) & ~31] __ALIGNED(32); +} RxBuff_t; + +/* Memory Pool Declaration */ +#define ETH_RX_BUFFER_CNT 12U +LWIP_MEMPOOL_DECLARE(RX_POOL, ETH_RX_BUFFER_CNT, sizeof(RxBuff_t), "Zero-copy RX PBUF pool"); + +/* Variable Definitions */ +static uint8_t RxAllocStatus; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ + +#pragma location=0x30000000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x30000100 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ + +__attribute__((at(0x30000000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x30000100))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __GNUC__ ) /* GNU Compiler */ + +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ + +#endif + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + +/* Global Ethernet handle */ +ETH_HandleTypeDef heth; +ETH_TxPacketConfig TxConfig; + +/* Private function prototypes -----------------------------------------------*/ +int32_t ETH_PHY_IO_Init(void); +int32_t ETH_PHY_IO_DeInit (void); +int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal); +int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal); +int32_t ETH_PHY_IO_GetTick(void); + +lan8742_Object_t LAN8742; +lan8742_IOCtx_t LAN8742_IOCtx = {ETH_PHY_IO_Init, + ETH_PHY_IO_DeInit, + ETH_PHY_IO_WriteReg, + ETH_PHY_IO_ReadReg, + ETH_PHY_IO_GetTick}; + +/* USER CODE BEGIN 3 */ + +/* USER CODE END 3 */ + +/* Private functions ---------------------------------------------------------*/ +void pbuf_free_custom(struct pbuf *p); + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/******************************************************************************* + LL Driver Interface ( LwIP stack --> ETH) +*******************************************************************************/ +/** + * @brief In this function, the hardware should be initialized. + * Called from ethernetif_init(). + * + * @param netif the already initialized lwip network interface structure + * for this ethernetif + */ +static void low_level_init(struct netif *netif) +{ + HAL_StatusTypeDef hal_eth_init_status = HAL_OK; + /* Start ETH HAL Init */ + + uint8_t MACAddr[6] ; + heth.Instance = ETH; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + heth.Init.TxDesc = DMATxDscrTab; + heth.Init.RxDesc = DMARxDscrTab; + heth.Init.RxBuffLen = 1536; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + hal_eth_init_status = HAL_ETH_Init(&heth); + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + + /* End ETH HAL Init */ + + /* Initialize the RX POOL */ + LWIP_MEMPOOL_INIT(RX_POOL); + +#if LWIP_ARP || LWIP_ETHERNET + + /* set MAC hardware address length */ + netif->hwaddr_len = ETH_HWADDR_LEN; + + /* set MAC hardware address */ + netif->hwaddr[0] = heth.Init.MACAddr[0]; + netif->hwaddr[1] = heth.Init.MACAddr[1]; + netif->hwaddr[2] = heth.Init.MACAddr[2]; + netif->hwaddr[3] = heth.Init.MACAddr[3]; + netif->hwaddr[4] = heth.Init.MACAddr[4]; + netif->hwaddr[5] = heth.Init.MACAddr[5]; + + /* maximum transfer unit */ + netif->mtu = ETH_MAX_PAYLOAD; + + /* Accept broadcast address and ARP traffic */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + #if LWIP_ARP + netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; + #else + netif->flags |= NETIF_FLAG_BROADCAST; + #endif /* LWIP_ARP */ + +/* USER CODE BEGIN PHY_PRE_CONFIG */ + +/* USER CODE END PHY_PRE_CONFIG */ + /* Set PHY IO functions */ + LAN8742_RegisterBusIO(&LAN8742, &LAN8742_IOCtx); + + /* Initialize the LAN8742 ETH PHY */ + LAN8742_Init(&LAN8742); + + if (hal_eth_init_status == HAL_OK) + { + /* Get link state */ + ethernet_link_check_state(netif); + } + else + { + Error_Handler(); + } +#endif /* LWIP_ARP || LWIP_ETHERNET */ + +/* USER CODE BEGIN LOW_LEVEL_INIT */ + +/* USER CODE END LOW_LEVEL_INIT */ +} + +/** + * @brief This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param netif the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ + +static err_t low_level_output(struct netif *netif, struct pbuf *p) +{ + uint32_t i = 0U; + struct pbuf *q = NULL; + err_t errval = ERR_OK; + ETH_BufferTypeDef Txbuffer[ETH_TX_DESC_CNT] = {0}; + + memset(Txbuffer, 0 , ETH_TX_DESC_CNT*sizeof(ETH_BufferTypeDef)); + + for(q = p; q != NULL; q = q->next) + { + if(i >= ETH_TX_DESC_CNT) + return ERR_IF; + + Txbuffer[i].buffer = q->payload; + Txbuffer[i].len = q->len; + + if(i>0) + { + Txbuffer[i-1].next = &Txbuffer[i]; + } + + if(q->next == NULL) + { + Txbuffer[i].next = NULL; + } + + i++; + } + + TxConfig.Length = p->tot_len; + TxConfig.TxBuffer = Txbuffer; + TxConfig.pData = p; + + HAL_ETH_Transmit(&heth, &TxConfig, ETH_DMA_TRANSMIT_TIMEOUT); + + return errval; +} + +/** + * @brief Should allocate a pbuf and transfer the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static struct pbuf * low_level_input(struct netif *netif) +{ + struct pbuf *p = NULL; + + if(RxAllocStatus == RX_ALLOC_OK) + { + HAL_ETH_ReadData(&heth, (void **)&p); + } + + return p; +} + +/** + * @brief This function should be called when a packet is ready to be read + * from the interface. It uses the function low_level_input() that + * should handle the actual reception of bytes from the network + * interface. Then the type of the received packet is determined and + * the appropriate input function is called. + * + * @param netif the lwip network interface structure for this ethernetif + */ +void ethernetif_input(struct netif *netif) +{ + struct pbuf *p = NULL; + + do + { + p = low_level_input( netif ); + if (p != NULL) + { + if (netif->input( p, netif) != ERR_OK ) + { + pbuf_free(p); + } + } + } while(p!=NULL); +} + +#if !LWIP_ARP +/** + * This function has to be completed by user in case of ARP OFF. + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if ... + */ +static err_t low_level_output_arp_off(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) +{ + err_t errval; + errval = ERR_OK; + +/* USER CODE BEGIN 5 */ + +/* USER CODE END 5 */ + + return errval; + +} +#endif /* LWIP_ARP */ + +/** + * @brief Should be called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t ethernetif_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + netif->hostname = "lwip"; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + // MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS); + + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + +#if LWIP_IPV4 +#if LWIP_ARP || LWIP_ETHERNET +#if LWIP_ARP + netif->output = etharp_output; +#else + /* The user should write its own code in low_level_output_arp_off function */ + netif->output = low_level_output_arp_off; +#endif /* LWIP_ARP */ +#endif /* LWIP_ARP || LWIP_ETHERNET */ +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 + netif->output_ip6 = ethip6_output; +#endif /* LWIP_IPV6 */ + + netif->linkoutput = low_level_output; + + /* initialize the hardware */ + low_level_init(netif); + + return ERR_OK; +} + +/** + * @brief Custom Rx pbuf free callback + * @param pbuf: pbuf to be freed + * @retval None + */ +void pbuf_free_custom(struct pbuf *p) +{ + struct pbuf_custom* custom_pbuf = (struct pbuf_custom*)p; + LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); + + /* If the Rx Buffer Pool was exhausted, signal the ethernetif_input task to + * call HAL_ETH_GetRxDataBuffer to rebuild the Rx descriptors. */ + + if (RxAllocStatus == RX_ALLOC_ERROR) + { + RxAllocStatus = RX_ALLOC_OK; + } +} + +/* USER CODE BEGIN 6 */ + +/** +* @brief Returns the current time in milliseconds +* when LWIP_TIMERS == 1 and NO_SYS == 1 +* @param None +* @retval Current Time value +*/ +u32_t sys_now(void) +{ + return HAL_GetTick(); +} + +/* USER CODE END 6 */ + +/** + * @brief Initializes the ETH MSP. + * @param ethHandle: ETH handle + * @retval None + */ + +void HAL_ETH_MspInit(ETH_HandleTypeDef* ethHandle) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(ethHandle->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Enable Peripheral clock */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + __HAL_RCC_ETH1TX_CLK_ENABLE(); + __HAL_RCC_ETH1RX_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PC4 ------> ETH_RXD0 + PA1 ------> ETH_REF_CLK + PC5 ------> ETH_RXD1 + PA2 ------> ETH_MDIO + PB13 ------> ETH_TXD1 + PA7 ------> ETH_CRS_DV + PB11 ------> ETH_TX_EN + PB12 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* Peripheral interrupt init */ + HAL_NVIC_SetPriority(ETH_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } +} + +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* ethHandle) +{ + if(ethHandle->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Disable Peripheral clock */ + __HAL_RCC_ETH1MAC_CLK_DISABLE(); + __HAL_RCC_ETH1TX_CLK_DISABLE(); + __HAL_RCC_ETH1RX_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PC4 ------> ETH_RXD0 + PA1 ------> ETH_REF_CLK + PC5 ------> ETH_RXD1 + PA2 ------> ETH_MDIO + PB13 ------> ETH_TXD1 + PA7 ------> ETH_CRS_DV + PB11 ------> ETH_TX_EN + PB12 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_11|GPIO_PIN_12); + + /* Peripheral interrupt Deinit*/ + HAL_NVIC_DisableIRQ(ETH_IRQn); + + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } +} + +/******************************************************************************* + PHI IO Functions +*******************************************************************************/ +/** + * @brief Initializes the MDIO interface GPIO and clocks. + * @param None + * @retval 0 if OK, -1 if ERROR + */ +int32_t ETH_PHY_IO_Init(void) +{ + /* We assume that MDIO GPIO configuration is already done + in the ETH_MspInit() else it should be done here + */ + + /* Configure the MDIO Clock */ + HAL_ETH_SetMDIOClockRange(&heth); + + return 0; +} + +/** + * @brief De-Initializes the MDIO interface . + * @param None + * @retval 0 if OK, -1 if ERROR + */ +int32_t ETH_PHY_IO_DeInit (void) +{ + return 0; +} + +/** + * @brief Read a PHY register through the MDIO interface. + * @param DevAddr: PHY port address + * @param RegAddr: PHY register address + * @param pRegVal: pointer to hold the register value + * @retval 0 if OK -1 if Error + */ +int32_t ETH_PHY_IO_ReadReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t *pRegVal) +{ + if(HAL_ETH_ReadPHYRegister(&heth, DevAddr, RegAddr, pRegVal) != HAL_OK) + { + return -1; + } + + return 0; +} + +/** + * @brief Write a value to a PHY register through the MDIO interface. + * @param DevAddr: PHY port address + * @param RegAddr: PHY register address + * @param RegVal: Value to be written + * @retval 0 if OK -1 if Error + */ +int32_t ETH_PHY_IO_WriteReg(uint32_t DevAddr, uint32_t RegAddr, uint32_t RegVal) +{ + if(HAL_ETH_WritePHYRegister(&heth, DevAddr, RegAddr, RegVal) != HAL_OK) + { + return -1; + } + + return 0; +} + +/** + * @brief Get the time in millisecons used for internal PHY driver process. + * @retval Time value + */ +int32_t ETH_PHY_IO_GetTick(void) +{ + return HAL_GetTick(); +} + +/** + * @brief Check the ETH link state then update ETH driver and netif link accordingly. + * @retval None + */ +void ethernet_link_check_state(struct netif *netif) +{ + ETH_MACConfigTypeDef MACConf = {0}; + int32_t PHYLinkState = 0; + uint32_t linkchanged = 0U, speed = 0U, duplex = 0U; + + PHYLinkState = LAN8742_GetLinkState(&LAN8742); + + if(netif_is_link_up(netif) && (PHYLinkState <= LAN8742_STATUS_LINK_DOWN)) + { + HAL_ETH_Stop(&heth); + netif_set_down(netif); + netif_set_link_down(netif); + } + else if(!netif_is_link_up(netif) && (PHYLinkState > LAN8742_STATUS_LINK_DOWN)) + { + switch (PHYLinkState) + { + case LAN8742_STATUS_100MBITS_FULLDUPLEX: + duplex = ETH_FULLDUPLEX_MODE; + speed = ETH_SPEED_100M; + linkchanged = 1; + break; + case LAN8742_STATUS_100MBITS_HALFDUPLEX: + duplex = ETH_HALFDUPLEX_MODE; + speed = ETH_SPEED_100M; + linkchanged = 1; + break; + case LAN8742_STATUS_10MBITS_FULLDUPLEX: + duplex = ETH_FULLDUPLEX_MODE; + speed = ETH_SPEED_10M; + linkchanged = 1; + break; + case LAN8742_STATUS_10MBITS_HALFDUPLEX: + duplex = ETH_HALFDUPLEX_MODE; + speed = ETH_SPEED_10M; + linkchanged = 1; + break; + default: + break; + } + + if(linkchanged) + { + /* Get MAC Config MAC */ + HAL_ETH_GetMACConfig(&heth, &MACConf); + MACConf.DuplexMode = duplex; + MACConf.Speed = speed; + HAL_ETH_SetMACConfig(&heth, &MACConf); + HAL_ETH_Start(&heth); + netif_set_up(netif); + netif_set_link_up(netif); + } + } + +} + +void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ +/* USER CODE BEGIN HAL ETH RxAllocateCallback */ + struct pbuf_custom *p = LWIP_MEMPOOL_ALLOC(RX_POOL); + if (p) + { + /* Get the buff from the struct pbuf address. */ + *buff = (uint8_t *)p + offsetof(RxBuff_t, buff); + p->custom_free_function = pbuf_free_custom; + /* Initialize the struct pbuf. + * This must be performed whenever a buffer's allocated because it may be + * changed by lwIP or the app, e.g., pbuf_free decrements ref. */ + pbuf_alloced_custom(PBUF_RAW, 0, PBUF_REF, p, *buff, ETH_RX_BUFFER_SIZE); + } + else + { + RxAllocStatus = RX_ALLOC_ERROR; + *buff = NULL; + } +/* USER CODE END HAL ETH RxAllocateCallback */ +} + +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ +/* USER CODE BEGIN HAL ETH RxLinkCallback */ + + struct pbuf **ppStart = (struct pbuf **)pStart; + struct pbuf **ppEnd = (struct pbuf **)pEnd; + struct pbuf *p = NULL; + + /* Get the struct pbuf from the buff address. */ + p = (struct pbuf *)(buff - offsetof(RxBuff_t, buff)); + p->next = NULL; + p->tot_len = 0; + p->len = Length; + + /* Chain the buffer. */ + if (!*ppStart) + { + /* The first buffer of the packet. */ + *ppStart = p; + } + else + { + /* Chain the buffer to the end of the packet. */ + (*ppEnd)->next = p; + } + *ppEnd = p; + + /* Update the total length of all the buffers of the chain. Each pbuf in the chain should have its tot_len + * set to its own length, plus the length of all the following pbufs in the chain. */ + for (p = *ppStart; p != NULL; p = p->next) + { + p->tot_len += Length; + } + + /* Invalidate data cache because Rx DMA's writing to physical memory makes it stale. */ + SCB_InvalidateDCache_by_Addr((uint32_t *)buff, Length); + +/* USER CODE END HAL ETH RxLinkCallback */ +} + +void HAL_ETH_TxFreeCallback(uint32_t * buff) +{ +/* USER CODE BEGIN HAL ETH TxFreeCallback */ + + pbuf_free((struct pbuf *)buff); + +/* USER CODE END HAL ETH TxFreeCallback */ +} + +/* USER CODE BEGIN 8 */ + +/* USER CODE END 8 */ + diff --git a/LWIP/Target/ethernetif.h b/LWIP/Target/ethernetif.h new file mode 100644 index 0000000..230fd62 --- /dev/null +++ b/LWIP/Target/ethernetif.h @@ -0,0 +1,45 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : ethernetif.h + * Description : This file provides initialization code for LWIP + * middleWare. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef __ETHERNETIF_H__ +#define __ETHERNETIF_H__ + +#include "lwip/err.h" +#include "lwip/netif.h" + +/* Within 'USER CODE' section, code will be kept by default at each generation */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* Exported functions ------------------------------------------------------- */ +err_t ethernetif_init(struct netif *netif); + +void ethernetif_input(struct netif *netif); +void ethernet_link_check_state(struct netif *netif); + +void Error_Handler(void); +u32_t sys_jiffies(void); +u32_t sys_now(void); + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +#endif diff --git a/LWIP/Target/lwipopts.h b/LWIP/Target/lwipopts.h new file mode 100644 index 0000000..59e029b --- /dev/null +++ b/LWIP/Target/lwipopts.h @@ -0,0 +1,116 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : Target/lwipopts.h + * Description : This file overrides LwIP stack default configuration + * done in opt.h file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion --------------------------------------*/ +#ifndef __LWIPOPTS__H__ +#define __LWIPOPTS__H__ + +#include "main.h" + +/*-----------------------------------------------------------------------------*/ +/* Current version of LwIP supported by CubeMx: 2.1.2 -*/ +/*-----------------------------------------------------------------------------*/ + +/* Within 'USER CODE' section, code will be kept by default at each generation */ +/* USER CODE BEGIN 0 */ +#define LWIP_DEBUG 1 +#define NETIF_DEBUG LWIP_DBG_ON +#define DHCP_DEBUG LWIP_DBG_ON +//#define UDP_DEBUG LWIP_DBG_ON +#define MEMP_DEBUG LWIP_DBG_ON +#define MEM_DEBUG LWIP_DBG_ON +#define ICMP_DEBUG LWIP_DBG_ON +/* USER CODE END 0 */ + +#ifdef __cplusplus + extern "C" { +#endif + +/* STM32CubeMX Specific Parameters (not defined in opt.h) ---------------------*/ +/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/ +/*----- WITH_RTOS disabled (Since FREERTOS is not set) -----*/ +#define WITH_RTOS 0 +/*----- CHECKSUM_BY_HARDWARE enabled -----*/ +#define CHECKSUM_BY_HARDWARE 1 +/*-----------------------------------------------------------------------------*/ + +/* LwIP Stack Parameters (modified compared to initialization value in opt.h) -*/ +/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/ +/*----- Default value in ETH configuration GUI in CubeMx: 1524 -----*/ +#define ETH_RX_BUFFER_SIZE 1536 +/*----- Value in opt.h for NO_SYS: 0 -----*/ +#define NO_SYS 1 +/*----- Value in opt.h for SYS_LIGHTWEIGHT_PROT: 1 -----*/ +#define SYS_LIGHTWEIGHT_PROT 0 +/*----- Value in opt.h for MEM_ALIGNMENT: 1 -----*/ +#define MEM_ALIGNMENT 4 +/*----- Default Value for MEM_SIZE: 1600 ---*/ +#define MEM_SIZE 32232 +/*----- Default Value for H7 devices: 0x30044000 -----*/ +#define LWIP_RAM_HEAP_POINTER 0x30000200 +/*----- Value supported for H7 devices: 1 -----*/ +#define LWIP_SUPPORT_CUSTOM_PBUF 1 +/*----- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/ +#define LWIP_ETHERNET 1 +/*----- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/ +#define LWIP_DNS_SECURE 7 +/*----- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS - 1))/TCP_MSS -----*/ +#define TCP_SND_QUEUELEN 9 +/*----- Value in opt.h for TCP_SNDLOWAT: LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -*/ +#define TCP_SNDLOWAT 1071 +/*----- Value in opt.h for TCP_SNDQUEUELOWAT: LWIP_MAX(TCP_SND_QUEUELEN)/2, 5) -*/ +#define TCP_SNDQUEUELOWAT 5 +/*----- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4, TCP_MSS*4) -----*/ +#define TCP_WND_UPDATE_THRESHOLD 536 +/*----- Value in opt.h for LWIP_NETIF_LINK_CALLBACK: 0 -----*/ +#define LWIP_NETIF_LINK_CALLBACK 1 +/*----- Value in opt.h for LWIP_NETCONN: 1 -----*/ +#define LWIP_NETCONN 0 +/*----- Value in opt.h for LWIP_SOCKET: 1 -----*/ +#define LWIP_SOCKET 0 +/*----- Value in opt.h for RECV_BUFSIZE_DEFAULT: INT_MAX -----*/ +#define RECV_BUFSIZE_DEFAULT 2000000000 +/*----- Value in opt.h for LWIP_STATS: 1 -----*/ +#define LWIP_STATS 0 +/*----- Value in opt.h for CHECKSUM_GEN_IP: 1 -----*/ +#define CHECKSUM_GEN_IP 0 +/*----- Value in opt.h for CHECKSUM_GEN_UDP: 1 -----*/ +#define CHECKSUM_GEN_UDP 0 +/*----- Value in opt.h for CHECKSUM_GEN_TCP: 1 -----*/ +#define CHECKSUM_GEN_TCP 0 +/*----- Value in opt.h for CHECKSUM_GEN_ICMP6: 1 -----*/ +#define CHECKSUM_GEN_ICMP6 0 +/*----- Value in opt.h for CHECKSUM_CHECK_IP: 1 -----*/ +#define CHECKSUM_CHECK_IP 0 +/*----- Value in opt.h for CHECKSUM_CHECK_UDP: 1 -----*/ +#define CHECKSUM_CHECK_UDP 0 +/*----- Value in opt.h for CHECKSUM_CHECK_TCP: 1 -----*/ +#define CHECKSUM_CHECK_TCP 0 +/*----- Value in opt.h for CHECKSUM_CHECK_ICMP6: 1 -----*/ +#define CHECKSUM_CHECK_ICMP6 0 +/*-----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +#ifdef __cplusplus +} +#endif +#endif /*__LWIPOPTS__H__ */ diff --git a/Middlewares/Third_Party/LwIP/src/api/api_lib.c b/Middlewares/Third_Party/LwIP/src/api/api_lib.c new file mode 100644 index 0000000..e03b8b7 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/api_lib.c @@ -0,0 +1,1367 @@ +/** + * @file + * Sequential API External module + * + * @defgroup netconn Netconn API + * @ingroup sequential_api + * Thread-safe, to be called from non-TCPIP threads only. + * TX/RX handling based on @ref netbuf (containing @ref pbuf) + * to avoid copying data around. + * + * @defgroup netconn_common Common functions + * @ingroup netconn + * For use with TCP and UDP + * + * @defgroup netconn_tcp TCP only + * @ingroup netconn + * TCP only functions + * + * @defgroup netconn_udp UDP only + * @ingroup netconn + * UDP only functions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + */ + +/* This is the part of the API that is linked with + the application */ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/api.h" +#include "lwip/memp.h" + +#include "lwip/ip.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/priv/api_msg.h" +#include "lwip/priv/tcp_priv.h" +#include "lwip/priv/tcpip_priv.h" + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +#include + +#define API_MSG_VAR_REF(name) API_VAR_REF(name) +#define API_MSG_VAR_DECLARE(name) API_VAR_DECLARE(struct api_msg, name) +#define API_MSG_VAR_ALLOC(name) API_VAR_ALLOC(struct api_msg, MEMP_API_MSG, name, ERR_MEM) +#define API_MSG_VAR_ALLOC_RETURN_NULL(name) API_VAR_ALLOC(struct api_msg, MEMP_API_MSG, name, NULL) +#define API_MSG_VAR_FREE(name) API_VAR_FREE(MEMP_API_MSG, name) + +#if TCP_LISTEN_BACKLOG +/* need to allocate API message for accept so empty message pool does not result in event loss + * see bug #47512: MPU_COMPATIBLE may fail on empty pool */ +#define API_MSG_VAR_ALLOC_ACCEPT(msg) API_MSG_VAR_ALLOC(msg) +#define API_MSG_VAR_FREE_ACCEPT(msg) API_MSG_VAR_FREE(msg) +#else /* TCP_LISTEN_BACKLOG */ +#define API_MSG_VAR_ALLOC_ACCEPT(msg) +#define API_MSG_VAR_FREE_ACCEPT(msg) +#endif /* TCP_LISTEN_BACKLOG */ + +#if LWIP_NETCONN_FULLDUPLEX +#define NETCONN_RECVMBOX_WAITABLE(conn) (sys_mbox_valid(&(conn)->recvmbox) && (((conn)->flags & NETCONN_FLAG_MBOXINVALID) == 0)) +#define NETCONN_ACCEPTMBOX_WAITABLE(conn) (sys_mbox_valid(&(conn)->acceptmbox) && (((conn)->flags & (NETCONN_FLAG_MBOXCLOSED|NETCONN_FLAG_MBOXINVALID)) == 0)) +#define NETCONN_MBOX_WAITING_INC(conn) SYS_ARCH_INC(conn->mbox_threads_waiting, 1) +#define NETCONN_MBOX_WAITING_DEC(conn) SYS_ARCH_DEC(conn->mbox_threads_waiting, 1) +#else /* LWIP_NETCONN_FULLDUPLEX */ +#define NETCONN_RECVMBOX_WAITABLE(conn) sys_mbox_valid(&(conn)->recvmbox) +#define NETCONN_ACCEPTMBOX_WAITABLE(conn) (sys_mbox_valid(&(conn)->acceptmbox) && (((conn)->flags & NETCONN_FLAG_MBOXCLOSED) == 0)) +#define NETCONN_MBOX_WAITING_INC(conn) +#define NETCONN_MBOX_WAITING_DEC(conn) +#endif /* LWIP_NETCONN_FULLDUPLEX */ + +static err_t netconn_close_shutdown(struct netconn *conn, u8_t how); + +/** + * Call the lower part of a netconn_* function + * This function is then running in the thread context + * of tcpip_thread and has exclusive access to lwIP core code. + * + * @param fn function to call + * @param apimsg a struct containing the function to call and its parameters + * @return ERR_OK if the function was called, another err_t if not + */ +static err_t +netconn_apimsg(tcpip_callback_fn fn, struct api_msg *apimsg) +{ + err_t err; + +#ifdef LWIP_DEBUG + /* catch functions that don't set err */ + apimsg->err = ERR_VAL; +#endif /* LWIP_DEBUG */ + +#if LWIP_NETCONN_SEM_PER_THREAD + apimsg->op_completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + err = tcpip_send_msg_wait_sem(fn, apimsg, LWIP_API_MSG_SEM(apimsg)); + if (err == ERR_OK) { + return apimsg->err; + } + return err; +} + +/** + * Create a new netconn (of a specific type) that has a callback function. + * The corresponding pcb is also created. + * + * @param t the type of 'connection' to create (@see enum netconn_type) + * @param proto the IP protocol for RAW IP pcbs + * @param callback a function to call on status changes (RX available, TX'ed) + * @return a newly allocated struct netconn or + * NULL on memory error + */ +struct netconn * +netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, netconn_callback callback) +{ + struct netconn *conn; + API_MSG_VAR_DECLARE(msg); + API_MSG_VAR_ALLOC_RETURN_NULL(msg); + + conn = netconn_alloc(t, callback); + if (conn != NULL) { + err_t err; + + API_MSG_VAR_REF(msg).msg.n.proto = proto; + API_MSG_VAR_REF(msg).conn = conn; + err = netconn_apimsg(lwip_netconn_do_newconn, &API_MSG_VAR_REF(msg)); + if (err != ERR_OK) { + LWIP_ASSERT("freeing conn without freeing pcb", conn->pcb.tcp == NULL); + LWIP_ASSERT("conn has no recvmbox", sys_mbox_valid(&conn->recvmbox)); +#if LWIP_TCP + LWIP_ASSERT("conn->acceptmbox shouldn't exist", !sys_mbox_valid(&conn->acceptmbox)); +#endif /* LWIP_TCP */ +#if !LWIP_NETCONN_SEM_PER_THREAD + LWIP_ASSERT("conn has no op_completed", sys_sem_valid(&conn->op_completed)); + sys_sem_free(&conn->op_completed); +#endif /* !LWIP_NETCONN_SEM_PER_THREAD */ + sys_mbox_free(&conn->recvmbox); + memp_free(MEMP_NETCONN, conn); + API_MSG_VAR_FREE(msg); + return NULL; + } + } + API_MSG_VAR_FREE(msg); + return conn; +} + +/** + * @ingroup netconn_common + * Close a netconn 'connection' and free all its resources but not the netconn itself. + * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate + * after this returns. + * + * @param conn the netconn to delete + * @return ERR_OK if the connection was deleted + */ +err_t +netconn_prepare_delete(struct netconn *conn) +{ + err_t err; + API_MSG_VAR_DECLARE(msg); + + /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */ + if (conn == NULL) { + return ERR_OK; + } + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; +#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER + /* get the time we started, which is later compared to + sys_now() + conn->send_timeout */ + API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); +#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ +#if LWIP_TCP + API_MSG_VAR_REF(msg).msg.sd.polls_left = + ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; +#endif /* LWIP_TCP */ +#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + err = netconn_apimsg(lwip_netconn_do_delconn, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + if (err != ERR_OK) { + return err; + } + return ERR_OK; +} + +/** + * @ingroup netconn_common + * Close a netconn 'connection' and free its resources. + * UDP and RAW connection are completely closed, TCP pcbs might still be in a waitstate + * after this returns. + * + * @param conn the netconn to delete + * @return ERR_OK if the connection was deleted + */ +err_t +netconn_delete(struct netconn *conn) +{ + err_t err; + + /* No ASSERT here because possible to get a (conn == NULL) if we got an accept error */ + if (conn == NULL) { + return ERR_OK; + } + +#if LWIP_NETCONN_FULLDUPLEX + if (conn->flags & NETCONN_FLAG_MBOXINVALID) { + /* Already called netconn_prepare_delete() before */ + err = ERR_OK; + } else +#endif /* LWIP_NETCONN_FULLDUPLEX */ + { + err = netconn_prepare_delete(conn); + } + if (err == ERR_OK) { + netconn_free(conn); + } + return err; +} + +/** + * Get the local or remote IP address and port of a netconn. + * For RAW netconns, this returns the protocol instead of a port! + * + * @param conn the netconn to query + * @param addr a pointer to which to save the IP address + * @param port a pointer to which to save the port (or protocol for RAW) + * @param local 1 to get the local IP address, 0 to get the remote one + * @return ERR_CONN for invalid connections + * ERR_OK if the information was retrieved + */ +err_t +netconn_getaddr(struct netconn *conn, ip_addr_t *addr, u16_t *port, u8_t local) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_getaddr: invalid conn", (conn != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_getaddr: invalid addr", (addr != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_getaddr: invalid port", (port != NULL), return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.ad.local = local; +#if LWIP_MPU_COMPATIBLE + err = netconn_apimsg(lwip_netconn_do_getaddr, &API_MSG_VAR_REF(msg)); + *addr = msg->msg.ad.ipaddr; + *port = msg->msg.ad.port; +#else /* LWIP_MPU_COMPATIBLE */ + msg.msg.ad.ipaddr = addr; + msg.msg.ad.port = port; + err = netconn_apimsg(lwip_netconn_do_getaddr, &msg); +#endif /* LWIP_MPU_COMPATIBLE */ + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_common + * Bind a netconn to a specific local IP address and port. + * Binding one netconn twice might not always be checked correctly! + * + * @param conn the netconn to bind + * @param addr the local IP address to bind the netconn to + * (use IP4_ADDR_ANY/IP6_ADDR_ANY to bind to all addresses) + * @param port the local port to bind the netconn to (not used for RAW) + * @return ERR_OK if bound, any other err_t on failure + */ +err_t +netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_bind: invalid conn", (conn != NULL), return ERR_ARG;); + +#if LWIP_IPV4 + /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ + if (addr == NULL) { + addr = IP4_ADDR_ANY; + } +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV4 && LWIP_IPV6 + /* "Socket API like" dual-stack support: If IP to bind to is IP6_ADDR_ANY, + * and NETCONN_FLAG_IPV6_V6ONLY is 0, use IP_ANY_TYPE to bind + */ + if ((netconn_get_ipv6only(conn) == 0) && + ip_addr_cmp(addr, IP6_ADDR_ANY)) { + addr = IP_ANY_TYPE; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr); + API_MSG_VAR_REF(msg).msg.bc.port = port; + err = netconn_apimsg(lwip_netconn_do_bind, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_common + * Bind a netconn to a specific interface and port. + * Binding one netconn twice might not always be checked correctly! + * + * @param conn the netconn to bind + * @param if_idx the local interface index to bind the netconn to + * @return ERR_OK if bound, any other err_t on failure + */ +err_t +netconn_bind_if(struct netconn *conn, u8_t if_idx) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_bind_if: invalid conn", (conn != NULL), return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.bc.if_idx = if_idx; + err = netconn_apimsg(lwip_netconn_do_bind_if, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_common + * Connect a netconn to a specific remote IP address and port. + * + * @param conn the netconn to connect + * @param addr the remote IP address to connect to + * @param port the remote port to connect to (no used for RAW) + * @return ERR_OK if connected, return value of tcp_/udp_/raw_connect otherwise + */ +err_t +netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_connect: invalid conn", (conn != NULL), return ERR_ARG;); + +#if LWIP_IPV4 + /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ + if (addr == NULL) { + addr = IP4_ADDR_ANY; + } +#endif /* LWIP_IPV4 */ + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.bc.ipaddr = API_MSG_VAR_REF(addr); + API_MSG_VAR_REF(msg).msg.bc.port = port; + err = netconn_apimsg(lwip_netconn_do_connect, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_udp + * Disconnect a netconn from its current peer (only valid for UDP netconns). + * + * @param conn the netconn to disconnect + * @return See @ref err_t + */ +err_t +netconn_disconnect(struct netconn *conn) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_disconnect: invalid conn", (conn != NULL), return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; + err = netconn_apimsg(lwip_netconn_do_disconnect, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_tcp + * Set a TCP netconn into listen mode + * + * @param conn the tcp netconn to set to listen mode + * @param backlog the listen backlog, only used if TCP_LISTEN_BACKLOG==1 + * @return ERR_OK if the netconn was set to listen (UDP and RAW netconns + * don't return any error (yet?)) + */ +err_t +netconn_listen_with_backlog(struct netconn *conn, u8_t backlog) +{ +#if LWIP_TCP + API_MSG_VAR_DECLARE(msg); + err_t err; + + /* This does no harm. If TCP_LISTEN_BACKLOG is off, backlog is unused. */ + LWIP_UNUSED_ARG(backlog); + + LWIP_ERROR("netconn_listen: invalid conn", (conn != NULL), return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; +#if TCP_LISTEN_BACKLOG + API_MSG_VAR_REF(msg).msg.lb.backlog = backlog; +#endif /* TCP_LISTEN_BACKLOG */ + err = netconn_apimsg(lwip_netconn_do_listen, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(conn); + LWIP_UNUSED_ARG(backlog); + return ERR_ARG; +#endif /* LWIP_TCP */ +} + +/** + * @ingroup netconn_tcp + * Accept a new connection on a TCP listening netconn. + * + * @param conn the TCP listen netconn + * @param new_conn pointer where the new connection is stored + * @return ERR_OK if a new connection has been received or an error + * code otherwise + */ +err_t +netconn_accept(struct netconn *conn, struct netconn **new_conn) +{ +#if LWIP_TCP + err_t err; + void *accept_ptr; + struct netconn *newconn; +#if TCP_LISTEN_BACKLOG + API_MSG_VAR_DECLARE(msg); +#endif /* TCP_LISTEN_BACKLOG */ + + LWIP_ERROR("netconn_accept: invalid pointer", (new_conn != NULL), return ERR_ARG;); + *new_conn = NULL; + LWIP_ERROR("netconn_accept: invalid conn", (conn != NULL), return ERR_ARG;); + + /* NOTE: Although the opengroup spec says a pending error shall be returned to + send/recv/getsockopt(SO_ERROR) only, we return it for listening + connections also, to handle embedded-system errors */ + err = netconn_err(conn); + if (err != ERR_OK) { + /* return pending error */ + return err; + } + if (!NETCONN_ACCEPTMBOX_WAITABLE(conn)) { + /* don't accept if closed: this might block the application task + waiting on acceptmbox forever! */ + return ERR_CLSD; + } + + API_MSG_VAR_ALLOC_ACCEPT(msg); + + NETCONN_MBOX_WAITING_INC(conn); + if (netconn_is_nonblocking(conn)) { + if (sys_arch_mbox_tryfetch(&conn->acceptmbox, &accept_ptr) == SYS_ARCH_TIMEOUT) { + API_MSG_VAR_FREE_ACCEPT(msg); + NETCONN_MBOX_WAITING_DEC(conn); + return ERR_WOULDBLOCK; + } + } else { +#if LWIP_SO_RCVTIMEO + if (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { + API_MSG_VAR_FREE_ACCEPT(msg); + NETCONN_MBOX_WAITING_DEC(conn); + return ERR_TIMEOUT; + } +#else + sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0); +#endif /* LWIP_SO_RCVTIMEO*/ + } + NETCONN_MBOX_WAITING_DEC(conn); +#if LWIP_NETCONN_FULLDUPLEX + if (conn->flags & NETCONN_FLAG_MBOXINVALID) { + if (lwip_netconn_is_deallocated_msg(accept_ptr)) { + /* the netconn has been closed from another thread */ + API_MSG_VAR_FREE_ACCEPT(msg); + return ERR_CONN; + } + } +#endif + + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); + + if (lwip_netconn_is_err_msg(accept_ptr, &err)) { + /* a connection has been aborted: e.g. out of pcbs or out of netconns during accept */ + API_MSG_VAR_FREE_ACCEPT(msg); + return err; + } + if (accept_ptr == NULL) { + /* connection has been aborted */ + API_MSG_VAR_FREE_ACCEPT(msg); + return ERR_CLSD; + } + newconn = (struct netconn *)accept_ptr; +#if TCP_LISTEN_BACKLOG + /* Let the stack know that we have accepted the connection. */ + API_MSG_VAR_REF(msg).conn = newconn; + /* don't care for the return value of lwip_netconn_do_recv */ + netconn_apimsg(lwip_netconn_do_accepted, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); +#endif /* TCP_LISTEN_BACKLOG */ + + *new_conn = newconn; + /* don't set conn->last_err: it's only ERR_OK, anyway */ + return ERR_OK; +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(conn); + LWIP_UNUSED_ARG(new_conn); + return ERR_ARG; +#endif /* LWIP_TCP */ +} + +/** + * @ingroup netconn_common + * Receive data: actual implementation that doesn't care whether pbuf or netbuf + * is received (this is internal, it's just here for describing common errors) + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new pbuf/netbuf is stored when received data + * @param apiflags flags that control function behaviour. For now only: + * - NETCONN_DONTBLOCK: only read data that is available now, don't wait for more data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error) + * ERR_CONN if not connected + * ERR_CLSD if TCP connection has been closed + * ERR_WOULDBLOCK if the netconn is nonblocking but would block to wait for data + * ERR_TIMEOUT if the netconn has a receive timeout and no data was received + */ +static err_t +netconn_recv_data(struct netconn *conn, void **new_buf, u8_t apiflags) +{ + void *buf = NULL; + u16_t len; + + LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); + *new_buf = NULL; + LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); + + if (!NETCONN_RECVMBOX_WAITABLE(conn)) { + err_t err = netconn_err(conn); + if (err != ERR_OK) { + /* return pending error */ + return err; + } + return ERR_CONN; + } + + NETCONN_MBOX_WAITING_INC(conn); + if (netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK) || + (conn->flags & NETCONN_FLAG_MBOXCLOSED) || (conn->pending_err != ERR_OK)) { + if (sys_arch_mbox_tryfetch(&conn->recvmbox, &buf) == SYS_ARCH_TIMEOUT) { + err_t err; + NETCONN_MBOX_WAITING_DEC(conn); + err = netconn_err(conn); + if (err != ERR_OK) { + /* return pending error */ + return err; + } + if (conn->flags & NETCONN_FLAG_MBOXCLOSED) { + return ERR_CONN; + } + return ERR_WOULDBLOCK; + } + } else { +#if LWIP_SO_RCVTIMEO + if (sys_arch_mbox_fetch(&conn->recvmbox, &buf, conn->recv_timeout) == SYS_ARCH_TIMEOUT) { + NETCONN_MBOX_WAITING_DEC(conn); + return ERR_TIMEOUT; + } +#else + sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); +#endif /* LWIP_SO_RCVTIMEO*/ + } + NETCONN_MBOX_WAITING_DEC(conn); +#if LWIP_NETCONN_FULLDUPLEX + if (conn->flags & NETCONN_FLAG_MBOXINVALID) { + if (lwip_netconn_is_deallocated_msg(buf)) { + /* the netconn has been closed from another thread */ + API_MSG_VAR_FREE_ACCEPT(msg); + return ERR_CONN; + } + } +#endif + +#if LWIP_TCP +#if (LWIP_UDP || LWIP_RAW) + if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) +#endif /* (LWIP_UDP || LWIP_RAW) */ + { + err_t err; + /* Check if this is an error message or a pbuf */ + if (lwip_netconn_is_err_msg(buf, &err)) { + /* new_buf has been zeroed above already */ + if (err == ERR_CLSD) { + /* connection closed translates to ERR_OK with *new_buf == NULL */ + return ERR_OK; + } + return err; + } + len = ((struct pbuf *)buf)->tot_len; + } +#endif /* LWIP_TCP */ +#if LWIP_TCP && (LWIP_UDP || LWIP_RAW) + else +#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */ +#if (LWIP_UDP || LWIP_RAW) + { + LWIP_ASSERT("buf != NULL", buf != NULL); + len = netbuf_len((struct netbuf *)buf); + } +#endif /* (LWIP_UDP || LWIP_RAW) */ + +#if LWIP_SO_RCVBUF + SYS_ARCH_DEC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVMINUS, len); + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_recv_data: received %p, len=%"U16_F"\n", buf, len)); + + *new_buf = buf; + /* don't set conn->last_err: it's only ERR_OK, anyway */ + return ERR_OK; +} + +#if LWIP_TCP +static err_t +netconn_tcp_recvd_msg(struct netconn *conn, size_t len, struct api_msg *msg) +{ + LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) && + NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;); + + msg->conn = conn; + msg->msg.r.len = len; + + return netconn_apimsg(lwip_netconn_do_recv, msg); +} + +err_t +netconn_tcp_recvd(struct netconn *conn, size_t len) +{ + err_t err; + API_MSG_VAR_DECLARE(msg); + LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) && + NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + err = netconn_tcp_recvd_msg(conn, len, &API_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + return err; +} + +static err_t +netconn_recv_data_tcp(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags) +{ + err_t err; + struct pbuf *buf; + API_MSG_VAR_DECLARE(msg); +#if LWIP_MPU_COMPATIBLE + msg = NULL; +#endif + + if (!NETCONN_RECVMBOX_WAITABLE(conn)) { + /* This only happens when calling this function more than once *after* receiving FIN */ + return ERR_CONN; + } + if (netconn_is_flag_set(conn, NETCONN_FIN_RX_PENDING)) { + netconn_clear_flags(conn, NETCONN_FIN_RX_PENDING); + goto handle_fin; + } + + if (!(apiflags & NETCONN_NOAUTORCVD)) { + /* need to allocate API message here so empty message pool does not result in event loss + * see bug #47512: MPU_COMPATIBLE may fail on empty pool */ + API_MSG_VAR_ALLOC(msg); + } + + err = netconn_recv_data(conn, (void **)new_buf, apiflags); + if (err != ERR_OK) { + if (!(apiflags & NETCONN_NOAUTORCVD)) { + API_MSG_VAR_FREE(msg); + } + return err; + } + buf = *new_buf; + if (!(apiflags & NETCONN_NOAUTORCVD)) { + /* Let the stack know that we have taken the data. */ + u16_t len = buf ? buf->tot_len : 1; + /* don't care for the return value of lwip_netconn_do_recv */ + /* @todo: this should really be fixed, e.g. by retrying in poll on error */ + netconn_tcp_recvd_msg(conn, len, &API_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + } + + /* If we are closed, we indicate that we no longer wish to use the socket */ + if (buf == NULL) { + if (apiflags & NETCONN_NOFIN) { + /* received a FIN but the caller cannot handle it right now: + re-enqueue it and return "no data" */ + netconn_set_flags(conn, NETCONN_FIN_RX_PENDING); + return ERR_WOULDBLOCK; + } else { +handle_fin: + API_EVENT(conn, NETCONN_EVT_RCVMINUS, 0); + if (conn->pcb.ip == NULL) { + /* race condition: RST during recv */ + err = netconn_err(conn); + if (err != ERR_OK) { + return err; + } + return ERR_RST; + } + /* RX side is closed, so deallocate the recvmbox */ + netconn_close_shutdown(conn, NETCONN_SHUT_RD); + /* Don' store ERR_CLSD as conn->err since we are only half-closed */ + return ERR_CLSD; + } + } + return err; +} + +/** + * @ingroup netconn_tcp + * Receive data (in form of a pbuf) from a TCP netconn + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new pbuf is stored when received data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error, @see netconn_recv_data) + * ERR_ARG if conn is not a TCP netconn + */ +err_t +netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf) +{ + LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) && + NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;); + + return netconn_recv_data_tcp(conn, new_buf, 0); +} + +/** + * @ingroup netconn_tcp + * Receive data (in form of a pbuf) from a TCP netconn + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new pbuf is stored when received data + * @param apiflags flags that control function behaviour. For now only: + * - NETCONN_DONTBLOCK: only read data that is available now, don't wait for more data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error, @see netconn_recv_data) + * ERR_ARG if conn is not a TCP netconn + */ +err_t +netconn_recv_tcp_pbuf_flags(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags) +{ + LWIP_ERROR("netconn_recv_tcp_pbuf: invalid conn", (conn != NULL) && + NETCONNTYPE_GROUP(netconn_type(conn)) == NETCONN_TCP, return ERR_ARG;); + + return netconn_recv_data_tcp(conn, new_buf, apiflags); +} +#endif /* LWIP_TCP */ + +/** + * Receive data (in form of a netbuf) from a UDP or RAW netconn + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new netbuf is stored when received data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error) + * ERR_ARG if conn is not a UDP/RAW netconn + */ +err_t +netconn_recv_udp_raw_netbuf(struct netconn *conn, struct netbuf **new_buf) +{ + LWIP_ERROR("netconn_recv_udp_raw_netbuf: invalid conn", (conn != NULL) && + NETCONNTYPE_GROUP(netconn_type(conn)) != NETCONN_TCP, return ERR_ARG;); + + return netconn_recv_data(conn, (void **)new_buf, 0); +} + +/** + * Receive data (in form of a netbuf) from a UDP or RAW netconn + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new netbuf is stored when received data + * @param apiflags flags that control function behaviour. For now only: + * - NETCONN_DONTBLOCK: only read data that is available now, don't wait for more data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error) + * ERR_ARG if conn is not a UDP/RAW netconn + */ +err_t +netconn_recv_udp_raw_netbuf_flags(struct netconn *conn, struct netbuf **new_buf, u8_t apiflags) +{ + LWIP_ERROR("netconn_recv_udp_raw_netbuf: invalid conn", (conn != NULL) && + NETCONNTYPE_GROUP(netconn_type(conn)) != NETCONN_TCP, return ERR_ARG;); + + return netconn_recv_data(conn, (void **)new_buf, apiflags); +} + +/** + * @ingroup netconn_common + * Receive data (in form of a netbuf containing a packet buffer) from a netconn + * + * @param conn the netconn from which to receive data + * @param new_buf pointer where a new netbuf is stored when received data + * @return ERR_OK if data has been received, an error code otherwise (timeout, + * memory error or another error) + */ +err_t +netconn_recv(struct netconn *conn, struct netbuf **new_buf) +{ +#if LWIP_TCP + struct netbuf *buf = NULL; + err_t err; +#endif /* LWIP_TCP */ + + LWIP_ERROR("netconn_recv: invalid pointer", (new_buf != NULL), return ERR_ARG;); + *new_buf = NULL; + LWIP_ERROR("netconn_recv: invalid conn", (conn != NULL), return ERR_ARG;); + +#if LWIP_TCP +#if (LWIP_UDP || LWIP_RAW) + if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) +#endif /* (LWIP_UDP || LWIP_RAW) */ + { + struct pbuf *p = NULL; + /* This is not a listening netconn, since recvmbox is set */ + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + return ERR_MEM; + } + + err = netconn_recv_data_tcp(conn, &p, 0); + if (err != ERR_OK) { + memp_free(MEMP_NETBUF, buf); + return err; + } + LWIP_ASSERT("p != NULL", p != NULL); + + buf->p = p; + buf->ptr = p; + buf->port = 0; + ip_addr_set_zero(&buf->addr); + *new_buf = buf; + /* don't set conn->last_err: it's only ERR_OK, anyway */ + return ERR_OK; + } +#endif /* LWIP_TCP */ +#if LWIP_TCP && (LWIP_UDP || LWIP_RAW) + else +#endif /* LWIP_TCP && (LWIP_UDP || LWIP_RAW) */ + { +#if (LWIP_UDP || LWIP_RAW) + return netconn_recv_data(conn, (void **)new_buf, 0); +#endif /* (LWIP_UDP || LWIP_RAW) */ + } +} + +/** + * @ingroup netconn_udp + * Send data (in form of a netbuf) to a specific remote IP address and port. + * Only to be used for UDP and RAW netconns (not TCP). + * + * @param conn the netconn over which to send data + * @param buf a netbuf containing the data to send + * @param addr the remote IP address to which to send the data + * @param port the remote port to which to send the data + * @return ERR_OK if data was sent, any other err_t on error + */ +err_t +netconn_sendto(struct netconn *conn, struct netbuf *buf, const ip_addr_t *addr, u16_t port) +{ + if (buf != NULL) { + ip_addr_set(&buf->addr, addr); + buf->port = port; + return netconn_send(conn, buf); + } + return ERR_VAL; +} + +/** + * @ingroup netconn_udp + * Send data over a UDP or RAW netconn (that is already connected). + * + * @param conn the UDP or RAW netconn over which to send data + * @param buf a netbuf containing the data to send + * @return ERR_OK if data was sent, any other err_t on error + */ +err_t +netconn_send(struct netconn *conn, struct netbuf *buf) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_send: invalid conn", (conn != NULL), return ERR_ARG;); + + LWIP_DEBUGF(API_LIB_DEBUG, ("netconn_send: sending %"U16_F" bytes\n", buf->p->tot_len)); + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.b = buf; + err = netconn_apimsg(lwip_netconn_do_send, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_tcp + * Send data over a TCP netconn. + * + * @param conn the TCP netconn over which to send data + * @param dataptr pointer to the application buffer that contains the data to send + * @param size size of the application data to send + * @param apiflags combination of following flags : + * - NETCONN_COPY: data will be copied into memory belonging to the stack + * - NETCONN_MORE: for TCP connection, PSH flag will be set on last segment sent + * - NETCONN_DONTBLOCK: only write the data if all data can be written at once + * @param bytes_written pointer to a location that receives the number of written bytes + * @return ERR_OK if data was sent, any other err_t on error + */ +err_t +netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size, + u8_t apiflags, size_t *bytes_written) +{ + struct netvector vector; + vector.ptr = dataptr; + vector.len = size; + return netconn_write_vectors_partly(conn, &vector, 1, apiflags, bytes_written); +} + +/** + * Send vectorized data atomically over a TCP netconn. + * + * @param conn the TCP netconn over which to send data + * @param vectors array of vectors containing data to send + * @param vectorcnt number of vectors in the array + * @param apiflags combination of following flags : + * - NETCONN_COPY: data will be copied into memory belonging to the stack + * - NETCONN_MORE: for TCP connection, PSH flag will be set on last segment sent + * - NETCONN_DONTBLOCK: only write the data if all data can be written at once + * @param bytes_written pointer to a location that receives the number of written bytes + * @return ERR_OK if data was sent, any other err_t on error + */ +err_t +netconn_write_vectors_partly(struct netconn *conn, struct netvector *vectors, u16_t vectorcnt, + u8_t apiflags, size_t *bytes_written) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + u8_t dontblock; + size_t size; + int i; + + LWIP_ERROR("netconn_write: invalid conn", (conn != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_write: invalid conn->type", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP), return ERR_VAL;); + dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); +#if LWIP_SO_SNDTIMEO + if (conn->send_timeout != 0) { + dontblock = 1; + } +#endif /* LWIP_SO_SNDTIMEO */ + if (dontblock && !bytes_written) { + /* This implies netconn_write() cannot be used for non-blocking send, since + it has no way to return the number of bytes written. */ + return ERR_VAL; + } + + /* sum up the total size */ + size = 0; + for (i = 0; i < vectorcnt; i++) { + size += vectors[i].len; + if (size < vectors[i].len) { + /* overflow */ + return ERR_VAL; + } + } + if (size == 0) { + return ERR_OK; + } else if (size > SSIZE_MAX) { + ssize_t limited; + /* this is required by the socket layer (cannot send full size_t range) */ + if (!bytes_written) { + return ERR_VAL; + } + /* limit the amount of data to send */ + limited = SSIZE_MAX; + size = (size_t)limited; + } + + API_MSG_VAR_ALLOC(msg); + /* non-blocking write sends as much */ + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.w.vector = vectors; + API_MSG_VAR_REF(msg).msg.w.vector_cnt = vectorcnt; + API_MSG_VAR_REF(msg).msg.w.vector_off = 0; + API_MSG_VAR_REF(msg).msg.w.apiflags = apiflags; + API_MSG_VAR_REF(msg).msg.w.len = size; + API_MSG_VAR_REF(msg).msg.w.offset = 0; +#if LWIP_SO_SNDTIMEO + if (conn->send_timeout != 0) { + /* get the time we started, which is later compared to + sys_now() + conn->send_timeout */ + API_MSG_VAR_REF(msg).msg.w.time_started = sys_now(); + } else { + API_MSG_VAR_REF(msg).msg.w.time_started = 0; + } +#endif /* LWIP_SO_SNDTIMEO */ + + /* For locking the core: this _can_ be delayed on low memory/low send buffer, + but if it is, this is done inside api_msg.c:do_write(), so we can use the + non-blocking version here. */ + err = netconn_apimsg(lwip_netconn_do_write, &API_MSG_VAR_REF(msg)); + if (err == ERR_OK) { + if (bytes_written != NULL) { + *bytes_written = API_MSG_VAR_REF(msg).msg.w.offset; + } + /* for blocking, check all requested bytes were written, NOTE: send_timeout is + treated as dontblock (see dontblock assignment above) */ + if (!dontblock) { + LWIP_ASSERT("do_write failed to write all bytes", API_MSG_VAR_REF(msg).msg.w.offset == size); + } + } + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_tcp + * Close or shutdown a TCP netconn (doesn't delete it). + * + * @param conn the TCP netconn to close or shutdown + * @param how fully close or only shutdown one side? + * @return ERR_OK if the netconn was closed, any other err_t on error + */ +static err_t +netconn_close_shutdown(struct netconn *conn, u8_t how) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + LWIP_UNUSED_ARG(how); + + LWIP_ERROR("netconn_close: invalid conn", (conn != NULL), return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + API_MSG_VAR_REF(msg).conn = conn; +#if LWIP_TCP + /* shutting down both ends is the same as closing */ + API_MSG_VAR_REF(msg).msg.sd.shut = how; +#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER + /* get the time we started, which is later compared to + sys_now() + conn->send_timeout */ + API_MSG_VAR_REF(msg).msg.sd.time_started = sys_now(); +#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + API_MSG_VAR_REF(msg).msg.sd.polls_left = + ((LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT + TCP_SLOW_INTERVAL - 1) / TCP_SLOW_INTERVAL) + 1; +#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ +#endif /* LWIP_TCP */ + err = netconn_apimsg(lwip_netconn_do_close, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} + +/** + * @ingroup netconn_tcp + * Close a TCP netconn (doesn't delete it). + * + * @param conn the TCP netconn to close + * @return ERR_OK if the netconn was closed, any other err_t on error + */ +err_t +netconn_close(struct netconn *conn) +{ + /* shutting down both ends is the same as closing */ + return netconn_close_shutdown(conn, NETCONN_SHUT_RDWR); +} + +/** + * @ingroup netconn_common + * Get and reset pending error on a netconn + * + * @param conn the netconn to get the error from + * @return and pending error or ERR_OK if no error was pending + */ +err_t +netconn_err(struct netconn *conn) +{ + err_t err; + SYS_ARCH_DECL_PROTECT(lev); + if (conn == NULL) { + return ERR_OK; + } + SYS_ARCH_PROTECT(lev); + err = conn->pending_err; + conn->pending_err = ERR_OK; + SYS_ARCH_UNPROTECT(lev); + return err; +} + +/** + * @ingroup netconn_tcp + * Shut down one or both sides of a TCP netconn (doesn't delete it). + * + * @param conn the TCP netconn to shut down + * @param shut_rx shut down the RX side (no more read possible after this) + * @param shut_tx shut down the TX side (no more write possible after this) + * @return ERR_OK if the netconn was closed, any other err_t on error + */ +err_t +netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx) +{ + return netconn_close_shutdown(conn, (u8_t)((shut_rx ? NETCONN_SHUT_RD : 0) | (shut_tx ? NETCONN_SHUT_WR : 0))); +} + +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) +/** + * @ingroup netconn_udp + * Join multicast groups for UDP netconns. + * + * @param conn the UDP netconn for which to change multicast addresses + * @param multiaddr IP address of the multicast group to join or leave + * @param netif_addr the IP address of the network interface on which to send + * the igmp message + * @param join_or_leave flag whether to send a join- or leave-message + * @return ERR_OK if the action was taken, any err_t on error + */ +err_t +netconn_join_leave_group(struct netconn *conn, + const ip_addr_t *multiaddr, + const ip_addr_t *netif_addr, + enum netconn_igmp join_or_leave) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_join_leave_group: invalid conn", (conn != NULL), return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + +#if LWIP_IPV4 + /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ + if (multiaddr == NULL) { + multiaddr = IP4_ADDR_ANY; + } + if (netif_addr == NULL) { + netif_addr = IP4_ADDR_ANY; + } +#endif /* LWIP_IPV4 */ + + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.jl.multiaddr = API_MSG_VAR_REF(multiaddr); + API_MSG_VAR_REF(msg).msg.jl.netif_addr = API_MSG_VAR_REF(netif_addr); + API_MSG_VAR_REF(msg).msg.jl.join_or_leave = join_or_leave; + err = netconn_apimsg(lwip_netconn_do_join_leave_group, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} +/** + * @ingroup netconn_udp + * Join multicast groups for UDP netconns. + * + * @param conn the UDP netconn for which to change multicast addresses + * @param multiaddr IP address of the multicast group to join or leave + * @param if_idx the index of the netif + * @param join_or_leave flag whether to send a join- or leave-message + * @return ERR_OK if the action was taken, any err_t on error + */ +err_t +netconn_join_leave_group_netif(struct netconn *conn, + const ip_addr_t *multiaddr, + u8_t if_idx, + enum netconn_igmp join_or_leave) +{ + API_MSG_VAR_DECLARE(msg); + err_t err; + + LWIP_ERROR("netconn_join_leave_group: invalid conn", (conn != NULL), return ERR_ARG;); + + API_MSG_VAR_ALLOC(msg); + +#if LWIP_IPV4 + /* Don't propagate NULL pointer (IP_ADDR_ANY alias) to subsequent functions */ + if (multiaddr == NULL) { + multiaddr = IP4_ADDR_ANY; + } + if (if_idx == NETIF_NO_INDEX) { + return ERR_IF; + } +#endif /* LWIP_IPV4 */ + + API_MSG_VAR_REF(msg).conn = conn; + API_MSG_VAR_REF(msg).msg.jl.multiaddr = API_MSG_VAR_REF(multiaddr); + API_MSG_VAR_REF(msg).msg.jl.if_idx = if_idx; + API_MSG_VAR_REF(msg).msg.jl.join_or_leave = join_or_leave; + err = netconn_apimsg(lwip_netconn_do_join_leave_group_netif, &API_MSG_VAR_REF(msg)); + API_MSG_VAR_FREE(msg); + + return err; +} +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ + +#if LWIP_DNS +/** + * @ingroup netconn_common + * Execute a DNS query, only one IP address is returned + * + * @param name a string representation of the DNS host name to query + * @param addr a preallocated ip_addr_t where to store the resolved IP address + * @param dns_addrtype IP address type (IPv4 / IPv6) + * @return ERR_OK: resolving succeeded + * ERR_MEM: memory error, try again later + * ERR_ARG: dns client not initialized or invalid hostname + * ERR_VAL: dns server response was invalid + */ +#if LWIP_IPV4 && LWIP_IPV6 +err_t +netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype) +#else +err_t +netconn_gethostbyname(const char *name, ip_addr_t *addr) +#endif +{ + API_VAR_DECLARE(struct dns_api_msg, msg); +#if !LWIP_MPU_COMPATIBLE + sys_sem_t sem; +#endif /* LWIP_MPU_COMPATIBLE */ + err_t err; + err_t cberr; + + LWIP_ERROR("netconn_gethostbyname: invalid name", (name != NULL), return ERR_ARG;); + LWIP_ERROR("netconn_gethostbyname: invalid addr", (addr != NULL), return ERR_ARG;); +#if LWIP_MPU_COMPATIBLE + if (strlen(name) >= DNS_MAX_NAME_LENGTH) { + return ERR_ARG; + } +#endif + +#ifdef LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE +#if LWIP_IPV4 && LWIP_IPV6 + if (LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, dns_addrtype, &err)) { +#else + if (LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, NETCONN_DNS_DEFAULT, &err)) { +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + return err; + } +#endif /* LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE */ + + API_VAR_ALLOC(struct dns_api_msg, MEMP_DNS_API_MSG, msg, ERR_MEM); +#if LWIP_MPU_COMPATIBLE + strncpy(API_VAR_REF(msg).name, name, DNS_MAX_NAME_LENGTH - 1); + API_VAR_REF(msg).name[DNS_MAX_NAME_LENGTH - 1] = 0; +#else /* LWIP_MPU_COMPATIBLE */ + msg.err = &err; + msg.sem = &sem; + API_VAR_REF(msg).addr = API_VAR_REF(addr); + API_VAR_REF(msg).name = name; +#endif /* LWIP_MPU_COMPATIBLE */ +#if LWIP_IPV4 && LWIP_IPV6 + API_VAR_REF(msg).dns_addrtype = dns_addrtype; +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#if LWIP_NETCONN_SEM_PER_THREAD + API_VAR_REF(msg).sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else /* LWIP_NETCONN_SEM_PER_THREAD*/ + err = sys_sem_new(API_EXPR_REF(API_VAR_REF(msg).sem), 0); + if (err != ERR_OK) { + API_VAR_FREE(MEMP_DNS_API_MSG, msg); + return err; + } +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + cberr = tcpip_send_msg_wait_sem(lwip_netconn_do_gethostbyname, &API_VAR_REF(msg), API_EXPR_REF(API_VAR_REF(msg).sem)); +#if !LWIP_NETCONN_SEM_PER_THREAD + sys_sem_free(API_EXPR_REF(API_VAR_REF(msg).sem)); +#endif /* !LWIP_NETCONN_SEM_PER_THREAD */ + if (cberr != ERR_OK) { + API_VAR_FREE(MEMP_DNS_API_MSG, msg); + return cberr; + } + +#if LWIP_MPU_COMPATIBLE + *addr = msg->addr; + err = msg->err; +#endif /* LWIP_MPU_COMPATIBLE */ + + API_VAR_FREE(MEMP_DNS_API_MSG, msg); + return err; +} +#endif /* LWIP_DNS*/ + +#if LWIP_NETCONN_SEM_PER_THREAD +void +netconn_thread_init(void) +{ + sys_sem_t *sem = LWIP_NETCONN_THREAD_SEM_GET(); + if ((sem == NULL) || !sys_sem_valid(sem)) { + /* call alloc only once */ + LWIP_NETCONN_THREAD_SEM_ALLOC(); + LWIP_ASSERT("LWIP_NETCONN_THREAD_SEM_ALLOC() failed", sys_sem_valid(LWIP_NETCONN_THREAD_SEM_GET())); + } +} + +void +netconn_thread_cleanup(void) +{ + sys_sem_t *sem = LWIP_NETCONN_THREAD_SEM_GET(); + if ((sem != NULL) && sys_sem_valid(sem)) { + /* call free only once */ + LWIP_NETCONN_THREAD_SEM_FREE(); + } +} +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + +#endif /* LWIP_NETCONN */ diff --git a/Middlewares/Third_Party/LwIP/src/api/api_msg.c b/Middlewares/Third_Party/LwIP/src/api/api_msg.c new file mode 100644 index 0000000..3953102 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/api_msg.c @@ -0,0 +1,2173 @@ +/** + * @file + * Sequential API Internal module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/priv/api_msg.h" + +#include "lwip/ip.h" +#include "lwip/ip_addr.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" + +#include "lwip/memp.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" +#include "lwip/mld6.h" +#include "lwip/priv/tcpip_priv.h" + +#include + +/* netconns are polled once per second (e.g. continue write on memory error) */ +#define NETCONN_TCP_POLL_INTERVAL 2 + +#define SET_NONBLOCKING_CONNECT(conn, val) do { if (val) { \ + netconn_set_flags(conn, NETCONN_FLAG_IN_NONBLOCKING_CONNECT); \ +} else { \ + netconn_clear_flags(conn, NETCONN_FLAG_IN_NONBLOCKING_CONNECT); }} while(0) +#define IN_NONBLOCKING_CONNECT(conn) netconn_is_flag_set(conn, NETCONN_FLAG_IN_NONBLOCKING_CONNECT) + +#if LWIP_NETCONN_FULLDUPLEX +#define NETCONN_MBOX_VALID(conn, mbox) (sys_mbox_valid(mbox) && ((conn->flags & NETCONN_FLAG_MBOXINVALID) == 0)) +#else +#define NETCONN_MBOX_VALID(conn, mbox) sys_mbox_valid(mbox) +#endif + +/* forward declarations */ +#if LWIP_TCP +#if LWIP_TCPIP_CORE_LOCKING +#define WRITE_DELAYED , 1 +#define WRITE_DELAYED_PARAM , u8_t delayed +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define WRITE_DELAYED +#define WRITE_DELAYED_PARAM +#endif /* LWIP_TCPIP_CORE_LOCKING */ +static err_t lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM); +static err_t lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM); +#endif + +static void netconn_drain(struct netconn *conn); + +#if LWIP_TCPIP_CORE_LOCKING +#define TCPIP_APIMSG_ACK(m) +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define TCPIP_APIMSG_ACK(m) do { sys_sem_signal(LWIP_API_MSG_SEM(m)); } while(0) +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_NETCONN_FULLDUPLEX +const u8_t netconn_deleted = 0; + +int +lwip_netconn_is_deallocated_msg(void *msg) +{ + if (msg == &netconn_deleted) { + return 1; + } + return 0; +} +#endif /* LWIP_NETCONN_FULLDUPLEX */ + +#if LWIP_TCP +const u8_t netconn_aborted = 0; +const u8_t netconn_reset = 0; +const u8_t netconn_closed = 0; + +/** Translate an error to a unique void* passed via an mbox */ +static void * +lwip_netconn_err_to_msg(err_t err) +{ + switch (err) { + case ERR_ABRT: + return LWIP_CONST_CAST(void *, &netconn_aborted); + case ERR_RST: + return LWIP_CONST_CAST(void *, &netconn_reset); + case ERR_CLSD: + return LWIP_CONST_CAST(void *, &netconn_closed); + default: + LWIP_ASSERT("unhandled error", err == ERR_OK); + return NULL; + } +} + +int +lwip_netconn_is_err_msg(void *msg, err_t *err) +{ + LWIP_ASSERT("err != NULL", err != NULL); + + if (msg == &netconn_aborted) { + *err = ERR_ABRT; + return 1; + } else if (msg == &netconn_reset) { + *err = ERR_RST; + return 1; + } else if (msg == &netconn_closed) { + *err = ERR_CLSD; + return 1; + } + return 0; +} +#endif /* LWIP_TCP */ + + +#if LWIP_RAW +/** + * Receive callback function for RAW netconns. + * Doesn't 'eat' the packet, only copies it and sends it to + * conn->recvmbox + * + * @see raw.h (struct raw_pcb.recv) for parameters and return value + */ +static u8_t +recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr) +{ + struct pbuf *q; + struct netbuf *buf; + struct netconn *conn; + + LWIP_UNUSED_ARG(addr); + conn = (struct netconn *)arg; + + if ((conn != NULL) && NETCONN_MBOX_VALID(conn, &conn->recvmbox)) { +#if LWIP_SO_RCVBUF + int recv_avail; + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize) { + return 0; + } +#endif /* LWIP_SO_RCVBUF */ + /* copy the whole packet into new pbufs */ + q = pbuf_clone(PBUF_RAW, PBUF_RAM, p); + if (q != NULL) { + u16_t len; + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(q); + return 0; + } + + buf->p = q; + buf->ptr = q; + ip_addr_copy(buf->addr, *ip_current_src_addr()); + buf->port = pcb->protocol; + + len = q->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + netbuf_delete(buf); + return 0; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + } + } + + return 0; /* do not eat the packet */ +} +#endif /* LWIP_RAW*/ + +#if LWIP_UDP +/** + * Receive callback function for UDP netconns. + * Posts the packet to conn->recvmbox or deletes it on memory error. + * + * @see udp.h (struct udp_pcb.recv) for parameters + */ +static void +recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr, u16_t port) +{ + struct netbuf *buf; + struct netconn *conn; + u16_t len; +#if LWIP_SO_RCVBUF + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + LWIP_UNUSED_ARG(pcb); /* only used for asserts... */ + LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_udp must have an argument", arg != NULL); + conn = (struct netconn *)arg; + + if (conn == NULL) { + pbuf_free(p); + return; + } + + LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb); + +#if LWIP_SO_RCVBUF + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox) || + ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) { +#else /* LWIP_SO_RCVBUF */ + if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) { +#endif /* LWIP_SO_RCVBUF */ + pbuf_free(p); + return; + } + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(p); + return; + } else { + buf->p = p; + buf->ptr = p; + ip_addr_set(&buf->addr, addr); + buf->port = port; +#if LWIP_NETBUF_RECVINFO + if (conn->flags & NETCONN_FLAG_PKTINFO) { + /* get the UDP header - always in the first pbuf, ensured by udp_input */ + const struct udp_hdr *udphdr = (const struct udp_hdr *)ip_next_header_ptr(); + buf->flags = NETBUF_FLAG_DESTADDR; + ip_addr_set(&buf->toaddr, ip_current_dest_addr()); + buf->toport_chksum = udphdr->dest; + } +#endif /* LWIP_NETBUF_RECVINFO */ + } + + len = p->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + netbuf_delete(buf); + return; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } +} +#endif /* LWIP_UDP */ + +#if LWIP_TCP +/** + * Receive callback function for TCP netconns. + * Posts the packet to conn->recvmbox, but doesn't delete it on errors. + * + * @see tcp.h (struct tcp_pcb.recv) for parameters and return value + */ +static err_t +recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + struct netconn *conn; + u16_t len; + void *msg; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_tcp must have an argument", arg != NULL); + LWIP_ASSERT("err != ERR_OK unhandled", err == ERR_OK); + LWIP_UNUSED_ARG(err); /* for LWIP_NOASSERT */ + conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb); + + if (!NETCONN_MBOX_VALID(conn, &conn->recvmbox)) { + /* recvmbox already deleted */ + if (p != NULL) { + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } + return ERR_OK; + } + /* Unlike for UDP or RAW pcbs, don't check for available space + using recv_avail since that could break the connection + (data is already ACKed) */ + + if (p != NULL) { + msg = p; + len = p->tot_len; + } else { + msg = LWIP_CONST_CAST(void *, &netconn_closed); + len = 0; + } + + if (sys_mbox_trypost(&conn->recvmbox, msg) != ERR_OK) { + /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */ + return ERR_MEM; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + + return ERR_OK; +} + +/** + * Poll callback function for TCP netconns. + * Wakes up an application thread that waits for a connection to close + * or data to be sent. The application thread then takes the + * appropriate action to go on. + * + * Signals the conn->sem. + * netconn_close waits for conn->sem if closing failed. + * + * @see tcp.h (struct tcp_pcb.poll) for parameters and return value + */ +static err_t +poll_tcp(void *arg, struct tcp_pcb *pcb) +{ + struct netconn *conn = (struct netconn *)arg; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn->state == NETCONN_WRITE) { + lwip_netconn_do_writemore(conn WRITE_DELAYED); + } else if (conn->state == NETCONN_CLOSE) { +#if !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER + if (conn->current_msg && conn->current_msg->msg.sd.polls_left) { + conn->current_msg->msg.sd.polls_left--; + } +#endif /* !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER */ + lwip_netconn_do_close_internal(conn WRITE_DELAYED); + } + /* @todo: implement connect timeout here? */ + + /* Did a nonblocking write fail before? Then check available write-space. */ + if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) { + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + } + + return ERR_OK; +} + +/** + * Sent callback function for TCP netconns. + * Signals the conn->sem and calls API_EVENT. + * netconn_write waits for conn->sem if send buffer is low. + * + * @see tcp.h (struct tcp_pcb.sent) for parameters and return value + */ +static err_t +sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct netconn *conn = (struct netconn *)arg; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn) { + if (conn->state == NETCONN_WRITE) { + lwip_netconn_do_writemore(conn WRITE_DELAYED); + } else if (conn->state == NETCONN_CLOSE) { + lwip_netconn_do_close_internal(conn WRITE_DELAYED); + } + + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + netconn_clear_flags(conn, NETCONN_FLAG_CHECK_WRITESPACE); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, len); + } + } + + return ERR_OK; +} + +/** + * Error callback function for TCP netconns. + * Signals conn->sem, posts to all conn mboxes and calls API_EVENT. + * The application thread has then to decide what to do. + * + * @see tcp.h (struct tcp_pcb.err) for parameters + */ +static void +err_tcp(void *arg, err_t err) +{ + struct netconn *conn; + enum netconn_state old_state; + void *mbox_msg; + SYS_ARCH_DECL_PROTECT(lev); + + conn = (struct netconn *)arg; + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + SYS_ARCH_PROTECT(lev); + + /* when err is called, the pcb is deallocated, so delete the reference */ + conn->pcb.tcp = NULL; + /* store pending error */ + conn->pending_err = err; + /* prevent application threads from blocking on 'recvmbox'/'acceptmbox' */ + conn->flags |= NETCONN_FLAG_MBOXCLOSED; + + /* reset conn->state now before waking up other threads */ + old_state = conn->state; + conn->state = NETCONN_NONE; + + SYS_ARCH_UNPROTECT(lev); + + /* Notify the user layer about a connection error. Used to signal select. */ + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + /* Try to release selects pending on 'read' or 'write', too. + They will get an error if they actually try to read or write. */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + mbox_msg = lwip_netconn_err_to_msg(err); + /* pass error message to recvmbox to wake up pending recv */ + if (NETCONN_MBOX_VALID(conn, &conn->recvmbox)) { + /* use trypost to prevent deadlock */ + sys_mbox_trypost(&conn->recvmbox, mbox_msg); + } + /* pass error message to acceptmbox to wake up pending accept */ + if (NETCONN_MBOX_VALID(conn, &conn->acceptmbox)) { + /* use trypost to preven deadlock */ + sys_mbox_trypost(&conn->acceptmbox, mbox_msg); + } + + if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) || + (old_state == NETCONN_CONNECT)) { + /* calling lwip_netconn_do_writemore/lwip_netconn_do_close_internal is not necessary + since the pcb has already been deleted! */ + int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + + if (!was_nonblocking_connect) { + sys_sem_t *op_completed_sem; + /* set error return code */ + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + if (old_state == NETCONN_CLOSE) { + /* let close succeed: the connection is closed after all... */ + conn->current_msg->err = ERR_OK; + } else { + /* Write and connect fail */ + conn->current_msg->err = err; + } + op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + LWIP_ASSERT("inavlid op_completed_sem", sys_sem_valid(op_completed_sem)); + conn->current_msg = NULL; + /* wake up the waiting task */ + sys_sem_signal(op_completed_sem); + } else { + /* @todo: test what happens for error on nonblocking connect */ + } + } else { + LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL); + } +} + +/** + * Setup a tcp_pcb with the correct callback function pointers + * and their arguments. + * + * @param conn the TCP netconn to setup + */ +static void +setup_tcp(struct netconn *conn) +{ + struct tcp_pcb *pcb; + + pcb = conn->pcb.tcp; + tcp_arg(pcb, conn); + tcp_recv(pcb, recv_tcp); + tcp_sent(pcb, sent_tcp); + tcp_poll(pcb, poll_tcp, NETCONN_TCP_POLL_INTERVAL); + tcp_err(pcb, err_tcp); +} + +/** + * Accept callback function for TCP netconns. + * Allocates a new netconn and posts that to conn->acceptmbox. + * + * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value + */ +static err_t +accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) +{ + struct netconn *newconn; + struct netconn *conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + if (!NETCONN_MBOX_VALID(conn, &conn->acceptmbox)) { + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n")); + return ERR_VAL; + } + + if (newpcb == NULL) { + /* out-of-pcbs during connect: pass on this error to the application */ + if (sys_mbox_trypost(&conn->acceptmbox, lwip_netconn_err_to_msg(ERR_ABRT)) == ERR_OK) { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + return ERR_VAL; + } + LWIP_ASSERT("expect newpcb == NULL or err == ERR_OK", err == ERR_OK); + LWIP_UNUSED_ARG(err); /* for LWIP_NOASSERT */ + + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: newpcb->state: %s\n", tcp_debug_state_str(newpcb->state))); + + /* We have to set the callback here even though + * the new socket is unknown. newconn->socket is marked as -1. */ + newconn = netconn_alloc(conn->type, conn->callback); + if (newconn == NULL) { + /* outof netconns: pass on this error to the application */ + if (sys_mbox_trypost(&conn->acceptmbox, lwip_netconn_err_to_msg(ERR_ABRT)) == ERR_OK) { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + return ERR_MEM; + } + newconn->pcb.tcp = newpcb; + setup_tcp(newconn); + + /* handle backlog counter */ + tcp_backlog_delayed(newpcb); + + if (sys_mbox_trypost(&conn->acceptmbox, newconn) != ERR_OK) { + /* When returning != ERR_OK, the pcb is aborted in tcp_process(), + so do nothing here! */ + /* remove all references to this netconn from the pcb */ + struct tcp_pcb *pcb = newconn->pcb.tcp; + tcp_arg(pcb, NULL); + tcp_recv(pcb, NULL); + tcp_sent(pcb, NULL); + tcp_poll(pcb, NULL, 0); + tcp_err(pcb, NULL); + /* remove reference from to the pcb from this netconn */ + newconn->pcb.tcp = NULL; + /* no need to drain since we know the recvmbox is empty. */ + sys_mbox_free(&newconn->recvmbox); + sys_mbox_set_invalid(&newconn->recvmbox); + netconn_free(newconn); + return ERR_MEM; + } else { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Create a new pcb of a specific type. + * Called from lwip_netconn_do_newconn(). + * + * @param msg the api_msg describing the connection type + */ +static void +pcb_new(struct api_msg *msg) +{ + enum lwip_ip_addr_type iptype = IPADDR_TYPE_V4; + + LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL); + +#if LWIP_IPV6 && LWIP_IPV4 + /* IPv6: Dual-stack by default, unless netconn_set_ipv6only() is called */ + if (NETCONNTYPE_ISIPV6(netconn_type(msg->conn))) { + iptype = IPADDR_TYPE_ANY; + } +#endif + + /* Allocate a PCB for this connection */ + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new_ip_type(iptype, msg->msg.n.proto); + if (msg->conn->pcb.raw != NULL) { +#if LWIP_IPV6 + /* ICMPv6 packets should always have checksum calculated by the stack as per RFC 3542 chapter 3.1 */ + if (NETCONNTYPE_ISIPV6(msg->conn->type) && msg->conn->pcb.raw->protocol == IP6_NEXTH_ICMP6) { + msg->conn->pcb.raw->chksum_reqd = 1; + msg->conn->pcb.raw->chksum_offset = 2; + } +#endif /* LWIP_IPV6 */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + } + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new_ip_type(iptype); + if (msg->conn->pcb.udp != NULL) { +#if LWIP_UDPLITE + if (NETCONNTYPE_ISUDPLITE(msg->conn->type)) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + } +#endif /* LWIP_UDPLITE */ + if (NETCONNTYPE_ISUDPNOCHKSUM(msg->conn->type)) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + } + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new_ip_type(iptype); + if (msg->conn->pcb.tcp != NULL) { + setup_tcp(msg->conn); + } + break; +#endif /* LWIP_TCP */ + default: + /* Unsupported netconn type, e.g. protocol disabled */ + msg->err = ERR_VAL; + return; + } + if (msg->conn->pcb.ip == NULL) { + msg->err = ERR_MEM; + } +} + +/** + * Create a new pcb of a specific type inside a netconn. + * Called from netconn_new_with_proto_and_callback. + * + * @param m the api_msg describing the connection type + */ +void +lwip_netconn_do_newconn(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp == NULL) { + pcb_new(msg); + } + /* Else? This "new" connection already has a PCB allocated. */ + /* Is this an error condition? Should it be deleted? */ + /* We currently just are happy and return. */ + + TCPIP_APIMSG_ACK(msg); +} + +/** + * Create a new netconn (of a specific type) that has a callback function. + * The corresponding pcb is NOT created! + * + * @param t the type of 'connection' to create (@see enum netconn_type) + * @param callback a function to call on status changes (RX available, TX'ed) + * @return a newly allocated struct netconn or + * NULL on memory error + */ +struct netconn * +netconn_alloc(enum netconn_type t, netconn_callback callback) +{ + struct netconn *conn; + int size; + u8_t init_flags = 0; + + conn = (struct netconn *)memp_malloc(MEMP_NETCONN); + if (conn == NULL) { + return NULL; + } + + conn->pending_err = ERR_OK; + conn->type = t; + conn->pcb.tcp = NULL; + + /* If all sizes are the same, every compiler should optimize this switch to nothing */ + switch (NETCONNTYPE_GROUP(t)) { +#if LWIP_RAW + case NETCONN_RAW: + size = DEFAULT_RAW_RECVMBOX_SIZE; + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + size = DEFAULT_UDP_RECVMBOX_SIZE; +#if LWIP_NETBUF_RECVINFO + init_flags |= NETCONN_FLAG_PKTINFO; +#endif /* LWIP_NETBUF_RECVINFO */ + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + size = DEFAULT_TCP_RECVMBOX_SIZE; + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0); + goto free_and_return; + } + + if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) { + goto free_and_return; + } +#if !LWIP_NETCONN_SEM_PER_THREAD + if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) { + sys_mbox_free(&conn->recvmbox); + goto free_and_return; + } +#endif + +#if LWIP_TCP + sys_mbox_set_invalid(&conn->acceptmbox); +#endif + conn->state = NETCONN_NONE; +#if LWIP_SOCKET + /* initialize socket to -1 since 0 is a valid socket */ + conn->socket = -1; +#endif /* LWIP_SOCKET */ + conn->callback = callback; +#if LWIP_TCP + conn->current_msg = NULL; +#endif /* LWIP_TCP */ +#if LWIP_SO_SNDTIMEO + conn->send_timeout = 0; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + conn->recv_timeout = 0; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + conn->recv_bufsize = RECV_BUFSIZE_DEFAULT; + conn->recv_avail = 0; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + conn->linger = -1; +#endif /* LWIP_SO_LINGER */ + conn->flags = init_flags; + return conn; +free_and_return: + memp_free(MEMP_NETCONN, conn); + return NULL; +} + +/** + * Delete a netconn and all its resources. + * The pcb is NOT freed (since we might not be in the right thread context do this). + * + * @param conn the netconn to free + */ +void +netconn_free(struct netconn *conn) +{ + LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL); + +#if LWIP_NETCONN_FULLDUPLEX + /* in fullduplex, netconn is drained here */ + netconn_drain(conn); +#endif /* LWIP_NETCONN_FULLDUPLEX */ + + LWIP_ASSERT("recvmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->recvmbox)); +#if LWIP_TCP + LWIP_ASSERT("acceptmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->acceptmbox)); +#endif /* LWIP_TCP */ + +#if !LWIP_NETCONN_SEM_PER_THREAD + sys_sem_free(&conn->op_completed); + sys_sem_set_invalid(&conn->op_completed); +#endif + + memp_free(MEMP_NETCONN, conn); +} + +/** + * Delete rcvmbox and acceptmbox of a netconn and free the left-over data in + * these mboxes + * + * @param conn the netconn to free + * @bytes_drained bytes drained from recvmbox + * @accepts_drained pending connections drained from acceptmbox + */ +static void +netconn_drain(struct netconn *conn) +{ + void *mem; + + /* This runs when mbox and netconn are marked as closed, + so we don't need to lock against rx packets */ +#if LWIP_NETCONN_FULLDUPLEX + LWIP_ASSERT("netconn marked closed", conn->flags & NETCONN_FLAG_MBOXINVALID); +#endif /* LWIP_NETCONN_FULLDUPLEX */ + + /* Delete and drain the recvmbox. */ + if (sys_mbox_valid(&conn->recvmbox)) { + while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { +#if LWIP_NETCONN_FULLDUPLEX + if (!lwip_netconn_is_deallocated_msg(mem)) +#endif /* LWIP_NETCONN_FULLDUPLEX */ + { +#if LWIP_TCP + if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) { + err_t err; + if (!lwip_netconn_is_err_msg(mem, &err)) { + pbuf_free((struct pbuf *)mem); + } + } else +#endif /* LWIP_TCP */ + { + netbuf_delete((struct netbuf *)mem); + } + } + } + sys_mbox_free(&conn->recvmbox); + sys_mbox_set_invalid(&conn->recvmbox); + } + + /* Delete and drain the acceptmbox. */ +#if LWIP_TCP + if (sys_mbox_valid(&conn->acceptmbox)) { + while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { +#if LWIP_NETCONN_FULLDUPLEX + if (!lwip_netconn_is_deallocated_msg(mem)) +#endif /* LWIP_NETCONN_FULLDUPLEX */ + { + err_t err; + if (!lwip_netconn_is_err_msg(mem, &err)) { + struct netconn *newconn = (struct netconn *)mem; + /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */ + /* pcb might be set to NULL already by err_tcp() */ + /* drain recvmbox */ + netconn_drain(newconn); + if (newconn->pcb.tcp != NULL) { + tcp_abort(newconn->pcb.tcp); + newconn->pcb.tcp = NULL; + } + netconn_free(newconn); + } + } + } + sys_mbox_free(&conn->acceptmbox); + sys_mbox_set_invalid(&conn->acceptmbox); + } +#endif /* LWIP_TCP */ +} + +#if LWIP_NETCONN_FULLDUPLEX +static void +netconn_mark_mbox_invalid(struct netconn *conn) +{ + int i, num_waiting; + void *msg = LWIP_CONST_CAST(void *, &netconn_deleted); + + /* Prevent new calls/threads from reading from the mbox */ + conn->flags |= NETCONN_FLAG_MBOXINVALID; + + SYS_ARCH_LOCKED(num_waiting = conn->mbox_threads_waiting); + for (i = 0; i < num_waiting; i++) { + if (sys_mbox_valid_val(conn->recvmbox)) { + sys_mbox_trypost(&conn->recvmbox, msg); + } else { + sys_mbox_trypost(&conn->acceptmbox, msg); + } + } +} +#endif /* LWIP_NETCONN_FULLDUPLEX */ + +#if LWIP_TCP +/** + * Internal helper function to close a TCP netconn: since this sometimes + * doesn't work at the first attempt, this function is called from multiple + * places. + * + * @param conn the TCP netconn to close + */ +static err_t +lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM) +{ + err_t err; + u8_t shut, shut_rx, shut_tx, shut_close; + u8_t close_finished = 0; + struct tcp_pcb *tpcb; +#if LWIP_SO_LINGER + u8_t linger_wait_required = 0; +#endif /* LWIP_SO_LINGER */ + + LWIP_ASSERT("invalid conn", (conn != NULL)); + LWIP_ASSERT("this is for tcp netconns only", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)); + LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE)); + LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + + tpcb = conn->pcb.tcp; + shut = conn->current_msg->msg.sd.shut; + shut_rx = shut & NETCONN_SHUT_RD; + shut_tx = shut & NETCONN_SHUT_WR; + /* shutting down both ends is the same as closing + (also if RD or WR side was shut down before already) */ + if (shut == NETCONN_SHUT_RDWR) { + shut_close = 1; + } else if (shut_rx && + ((tpcb->state == FIN_WAIT_1) || + (tpcb->state == FIN_WAIT_2) || + (tpcb->state == CLOSING))) { + shut_close = 1; + } else if (shut_tx && ((tpcb->flags & TF_RXCLOSED) != 0)) { + shut_close = 1; + } else { + shut_close = 0; + } + + /* Set back some callback pointers */ + if (shut_close) { + tcp_arg(tpcb, NULL); + } + if (tpcb->state == LISTEN) { + tcp_accept(tpcb, NULL); + } else { + /* some callbacks have to be reset if tcp_close is not successful */ + if (shut_rx) { + tcp_recv(tpcb, NULL); + tcp_accept(tpcb, NULL); + } + if (shut_tx) { + tcp_sent(tpcb, NULL); + } + if (shut_close) { + tcp_poll(tpcb, NULL, 0); + tcp_err(tpcb, NULL); + } + } + /* Try to close the connection */ + if (shut_close) { +#if LWIP_SO_LINGER + /* check linger possibilites before calling tcp_close */ + err = ERR_OK; + /* linger enabled/required at all? (i.e. is there untransmitted data left?) */ + if ((conn->linger >= 0) && (conn->pcb.tcp->unsent || conn->pcb.tcp->unacked)) { + if ((conn->linger == 0)) { + /* data left but linger prevents waiting */ + tcp_abort(tpcb); + tpcb = NULL; + } else if (conn->linger > 0) { + /* data left and linger says we should wait */ + if (netconn_is_nonblocking(conn)) { + /* data left on a nonblocking netconn -> cannot linger */ + err = ERR_WOULDBLOCK; + } else if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= + (conn->linger * 1000)) { + /* data left but linger timeout has expired (this happens on further + calls to this function through poll_tcp */ + tcp_abort(tpcb); + tpcb = NULL; + } else { + /* data left -> need to wait for ACK after successful close */ + linger_wait_required = 1; + } + } + } + if ((err == ERR_OK) && (tpcb != NULL)) +#endif /* LWIP_SO_LINGER */ + { + err = tcp_close(tpcb); + } + } else { + err = tcp_shutdown(tpcb, shut_rx, shut_tx); + } + if (err == ERR_OK) { + close_finished = 1; +#if LWIP_SO_LINGER + if (linger_wait_required) { + /* wait for ACK of all unsent/unacked data by just getting called again */ + close_finished = 0; + err = ERR_INPROGRESS; + } +#endif /* LWIP_SO_LINGER */ + } else { + if (err == ERR_MEM) { + /* Closing failed because of memory shortage, try again later. Even for + nonblocking netconns, we have to wait since no standard socket application + is prepared for close failing because of resource shortage. + Check the timeout: this is kind of an lwip addition to the standard sockets: + we wait for some time when failing to allocate a segment for the FIN */ +#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER + s32_t close_timeout = LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT; +#if LWIP_SO_SNDTIMEO + if (conn->send_timeout > 0) { + close_timeout = conn->send_timeout; + } +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_LINGER + if (conn->linger >= 0) { + /* use linger timeout (seconds) */ + close_timeout = conn->linger * 1000U; + } +#endif + if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= close_timeout) { +#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + if (conn->current_msg->msg.sd.polls_left == 0) { +#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + close_finished = 1; + if (shut_close) { + /* in this case, we want to RST the connection */ + tcp_abort(tpcb); + err = ERR_OK; + } + } + } else { + /* Closing failed for a non-memory error: give up */ + close_finished = 1; + } + } + if (close_finished) { + /* Closing done (succeeded, non-memory error, nonblocking error or timeout) */ + sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg->err = err; + conn->current_msg = NULL; + conn->state = NETCONN_NONE; + if (err == ERR_OK) { + if (shut_close) { + /* Set back some callback pointers as conn is going away */ + conn->pcb.tcp = NULL; + /* Trigger select() in socket layer. Make sure everybody notices activity + on the connection, error first! */ + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + } + if (shut_rx) { + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + if (shut_tx) { + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + } +#if LWIP_TCPIP_CORE_LOCKING + if (delayed) +#endif + { + /* wake up the application task */ + sys_sem_signal(op_completed_sem); + } + return ERR_OK; + } + if (!close_finished) { + /* Closing failed and we want to wait: restore some of the callbacks */ + /* Closing of listen pcb will never fail! */ + LWIP_ASSERT("Closing a listen pcb may not fail!", (tpcb->state != LISTEN)); + if (shut_tx) { + tcp_sent(tpcb, sent_tcp); + } + /* when waiting for close, set up poll interval to 500ms */ + tcp_poll(tpcb, poll_tcp, 1); + tcp_err(tpcb, err_tcp); + tcp_arg(tpcb, conn); + /* don't restore recv callback: we don't want to receive any more data */ + } + /* If closing didn't succeed, we get called again either + from poll_tcp or from sent_tcp */ + LWIP_ASSERT("err != ERR_OK", err != ERR_OK); + return err; +} +#endif /* LWIP_TCP */ + +/** + * Delete the pcb inside a netconn. + * Called from netconn_delete. + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_delconn(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + enum netconn_state state = msg->conn->state; + LWIP_ASSERT("netconn state error", /* this only happens for TCP netconns */ + (state == NETCONN_NONE) || (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP)); +#if LWIP_NETCONN_FULLDUPLEX + /* In full duplex mode, blocking write/connect is aborted with ERR_CLSD */ + if (state != NETCONN_NONE) { + if ((state == NETCONN_WRITE) || + ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { + /* close requested, abort running write/connect */ + sys_sem_t *op_completed_sem; + LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); + op_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); + msg->conn->current_msg->err = ERR_CLSD; + msg->conn->current_msg = NULL; + msg->conn->state = NETCONN_NONE; + sys_sem_signal(op_completed_sem); + } + } +#else /* LWIP_NETCONN_FULLDUPLEX */ + if (((state != NETCONN_NONE) && + (state != NETCONN_LISTEN) && + (state != NETCONN_CONNECT)) || + ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { + /* This means either a blocking write or blocking connect is running + (nonblocking write returns and sets state to NONE) */ + msg->err = ERR_INPROGRESS; + } else +#endif /* LWIP_NETCONN_FULLDUPLEX */ + { + LWIP_ASSERT("blocking connect in progress", + (state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn)); + msg->err = ERR_OK; +#if LWIP_NETCONN_FULLDUPLEX + /* Mark mboxes invalid */ + netconn_mark_mbox_invalid(msg->conn); +#else /* LWIP_NETCONN_FULLDUPLEX */ + netconn_drain(msg->conn); +#endif /* LWIP_NETCONN_FULLDUPLEX */ + + if (msg->conn->pcb.tcp != NULL) { + + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + raw_remove(msg->conn->pcb.raw); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp->recv_arg = NULL; + udp_remove(msg->conn->pcb.udp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL); + msg->conn->state = NETCONN_CLOSE; + msg->msg.sd.shut = NETCONN_SHUT_RDWR; + msg->conn->current_msg = msg; +#if LWIP_TCPIP_CORE_LOCKING + if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + lwip_netconn_do_close_internal(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* API_EVENT is called inside lwip_netconn_do_close_internal, before releasing + the application thread, so we can return at this point! */ + return; +#endif /* LWIP_TCP */ + default: + break; + } + msg->conn->pcb.tcp = NULL; + } + /* tcp netconns don't come here! */ + + /* @todo: this lets select make the socket readable and writable, + which is wrong! errfd instead? */ + API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0); + } + if (sys_sem_valid(LWIP_API_MSG_SEM(msg))) { + TCPIP_APIMSG_ACK(msg); + } +} + +/** + * Bind a pcb contained in a netconn + * Called from netconn_bind. + * + * @param m the api_msg pointing to the connection and containing + * the IP address and port to bind to + */ +void +lwip_netconn_do_bind(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + err_t err; + + if (msg->conn->pcb.tcp != NULL) { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + err = raw_bind(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + err = udp_bind(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + err = tcp_bind(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_TCP */ + default: + err = ERR_VAL; + break; + } + } else { + err = ERR_VAL; + } + msg->err = err; + TCPIP_APIMSG_ACK(msg); +} +/** + * Bind a pcb contained in a netconn to an interface + * Called from netconn_bind_if. + * + * @param m the api_msg pointing to the connection and containing + * the IP address and port to bind to + */ +void +lwip_netconn_do_bind_if(void *m) +{ + struct netif *netif; + struct api_msg *msg = (struct api_msg *)m; + err_t err; + + netif = netif_get_by_index(msg->msg.bc.if_idx); + + if ((netif != NULL) && (msg->conn->pcb.tcp != NULL)) { + err = ERR_OK; + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + raw_bind_netif(msg->conn->pcb.raw, netif); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + udp_bind_netif(msg->conn->pcb.udp, netif); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + tcp_bind_netif(msg->conn->pcb.tcp, netif); + break; +#endif /* LWIP_TCP */ + default: + err = ERR_VAL; + break; + } + } else { + err = ERR_VAL; + } + msg->err = err; + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * TCP callback function if a connection (opened by tcp_connect/lwip_netconn_do_connect) has + * been established (or reset by the remote host). + * + * @see tcp.h (struct tcp_pcb.connected) for parameters and return values + */ +static err_t +lwip_netconn_do_connected(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct netconn *conn; + int was_blocking; + sys_sem_t *op_completed_sem = NULL; + + LWIP_UNUSED_ARG(pcb); + + conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + + LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT); + LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect", + (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn)); + + if (conn->current_msg != NULL) { + conn->current_msg->err = err; + op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + } + if ((NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) && (err == ERR_OK)) { + setup_tcp(conn); + } + was_blocking = !IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + LWIP_ASSERT("blocking connect state error", + (was_blocking && op_completed_sem != NULL) || + (!was_blocking && op_completed_sem == NULL)); + conn->current_msg = NULL; + conn->state = NETCONN_NONE; + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + if (was_blocking) { + sys_sem_signal(op_completed_sem); + } + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Connect a pcb contained inside a netconn + * Called from netconn_connect. + * + * @param m the api_msg pointing to the connection and containing + * the IP address and port to connect to + */ +void +lwip_netconn_do_connect(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + err_t err; + + if (msg->conn->pcb.tcp == NULL) { + /* This may happen when calling netconn_connect() a second time */ + err = ERR_CLSD; + } else { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + err = raw_connect(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + err = udp_connect(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + /* Prevent connect while doing any other action. */ + if (msg->conn->state == NETCONN_CONNECT) { + err = ERR_ALREADY; + } else if (msg->conn->state != NETCONN_NONE) { + err = ERR_ISCONN; + } else { + setup_tcp(msg->conn); + err = tcp_connect(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), + msg->msg.bc.port, lwip_netconn_do_connected); + if (err == ERR_OK) { + u8_t non_blocking = netconn_is_nonblocking(msg->conn); + msg->conn->state = NETCONN_CONNECT; + SET_NONBLOCKING_CONNECT(msg->conn, non_blocking); + if (non_blocking) { + err = ERR_INPROGRESS; + } else { + msg->conn->current_msg = msg; + /* sys_sem_signal() is called from lwip_netconn_do_connected (or err_tcp()), + when the connection is established! */ +#if LWIP_TCPIP_CORE_LOCKING + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CONNECT); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state != NETCONN_CONNECT); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + return; + } + } + } + break; +#endif /* LWIP_TCP */ + default: + LWIP_ERROR("Invalid netconn type", 0, do { + err = ERR_VAL; + } while (0)); + break; + } + } + msg->err = err; + /* For all other protocols, netconn_connect() calls netconn_apimsg(), + so use TCPIP_APIMSG_ACK() here. */ + TCPIP_APIMSG_ACK(msg); +} + +/** + * Disconnect a pcb contained inside a netconn + * Only used for UDP netconns. + * Called from netconn_disconnect. + * + * @param m the api_msg pointing to the connection to disconnect + */ +void +lwip_netconn_do_disconnect(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + +#if LWIP_UDP + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { + udp_disconnect(msg->conn->pcb.udp); + msg->err = ERR_OK; + } else +#endif /* LWIP_UDP */ + { + msg->err = ERR_VAL; + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Set a TCP pcb contained in a netconn into listen mode + * Called from netconn_listen. + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_listen(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + err_t err; + + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + if (msg->conn->state == NETCONN_NONE) { + struct tcp_pcb *lpcb; + if (msg->conn->pcb.tcp->state != CLOSED) { + /* connection is not closed, cannot listen */ + err = ERR_VAL; + } else { + u8_t backlog; +#if TCP_LISTEN_BACKLOG + backlog = msg->msg.lb.backlog; +#else /* TCP_LISTEN_BACKLOG */ + backlog = TCP_DEFAULT_LISTEN_BACKLOG; +#endif /* TCP_LISTEN_BACKLOG */ +#if LWIP_IPV4 && LWIP_IPV6 + /* "Socket API like" dual-stack support: If IP to listen to is IP6_ADDR_ANY, + * and NETCONN_FLAG_IPV6_V6ONLY is NOT set, use IP_ANY_TYPE to listen + */ + if (ip_addr_cmp(&msg->conn->pcb.ip->local_ip, IP6_ADDR_ANY) && + (netconn_get_ipv6only(msg->conn) == 0)) { + /* change PCB type to IPADDR_TYPE_ANY */ + IP_SET_TYPE_VAL(msg->conn->pcb.tcp->local_ip, IPADDR_TYPE_ANY); + IP_SET_TYPE_VAL(msg->conn->pcb.tcp->remote_ip, IPADDR_TYPE_ANY); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + lpcb = tcp_listen_with_backlog_and_err(msg->conn->pcb.tcp, backlog, &err); + + if (lpcb == NULL) { + /* in this case, the old pcb is still allocated */ + } else { + /* delete the recvmbox and allocate the acceptmbox */ + if (sys_mbox_valid(&msg->conn->recvmbox)) { + /** @todo: should we drain the recvmbox here? */ + sys_mbox_free(&msg->conn->recvmbox); + sys_mbox_set_invalid(&msg->conn->recvmbox); + } + err = ERR_OK; + if (!sys_mbox_valid(&msg->conn->acceptmbox)) { + err = sys_mbox_new(&msg->conn->acceptmbox, DEFAULT_ACCEPTMBOX_SIZE); + } + if (err == ERR_OK) { + msg->conn->state = NETCONN_LISTEN; + msg->conn->pcb.tcp = lpcb; + tcp_arg(msg->conn->pcb.tcp, msg->conn); + tcp_accept(msg->conn->pcb.tcp, accept_function); + } else { + /* since the old pcb is already deallocated, free lpcb now */ + tcp_close(lpcb); + msg->conn->pcb.tcp = NULL; + } + } + } + } else if (msg->conn->state == NETCONN_LISTEN) { + /* already listening, allow updating of the backlog */ + err = ERR_OK; + tcp_backlog_set(msg->conn->pcb.tcp, msg->msg.lb.backlog); + } else { + err = ERR_CONN; + } + } else { + err = ERR_ARG; + } + } else { + err = ERR_CONN; + } + msg->err = err; + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a RAW or UDP pcb contained in a netconn + * Called from netconn_send + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_send(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + err_t err = netconn_err(msg->conn); + if (err == ERR_OK) { + if (msg->conn->pcb.tcp != NULL) { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + err = raw_send(msg->conn->pcb.raw, msg->msg.b->p); + } else { + err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, &msg->msg.b->addr); + } + break; +#endif +#if LWIP_UDP + case NETCONN_UDP: +#if LWIP_CHECKSUM_ON_COPY + if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + err = udp_send_chksum(msg->conn->pcb.udp, msg->msg.b->p, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } else { + err = udp_sendto_chksum(msg->conn->pcb.udp, msg->msg.b->p, + &msg->msg.b->addr, msg->msg.b->port, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } +#else /* LWIP_CHECKSUM_ON_COPY */ + if (ip_addr_isany_val(msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + err = udp_send(msg->conn->pcb.udp, msg->msg.b->p); + } else { + err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, &msg->msg.b->addr, msg->msg.b->port); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + break; +#endif /* LWIP_UDP */ + default: + err = ERR_CONN; + break; + } + } else { + err = ERR_CONN; + } + } + msg->err = err; + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Indicate data has been received from a TCP pcb contained in a netconn + * Called from netconn_recv + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_recv(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + size_t remaining = msg->msg.r.len; + do { + u16_t recved = (u16_t)((remaining > 0xffff) ? 0xffff : remaining); + tcp_recved(msg->conn->pcb.tcp, recved); + remaining -= recved; + } while (remaining != 0); + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if TCP_LISTEN_BACKLOG +/** Indicate that a TCP pcb has been accepted + * Called from netconn_accept + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_accepted(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + tcp_backlog_accepted(msg->conn->pcb.tcp); + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* TCP_LISTEN_BACKLOG */ + +/** + * See if more data needs to be written from a previous call to netconn_write. + * Called initially from lwip_netconn_do_write. If the first call can't send all data + * (because of low memory or empty send-buffer), this function is called again + * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the + * blocking application thread (waiting in netconn_write) is released. + * + * @param conn netconn (that is currently in state NETCONN_WRITE) to process + * @return ERR_OK + * ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished + */ +static err_t +lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM) +{ + err_t err; + const void *dataptr; + u16_t len, available; + u8_t write_finished = 0; + size_t diff; + u8_t dontblock; + u8_t apiflags; + u8_t write_more; + + LWIP_ASSERT("conn != NULL", conn != NULL); + LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL); + LWIP_ASSERT("conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len", + conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len); + LWIP_ASSERT("conn->current_msg->msg.w.vector_cnt > 0", conn->current_msg->msg.w.vector_cnt > 0); + + apiflags = conn->current_msg->msg.w.apiflags; + dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); + +#if LWIP_SO_SNDTIMEO + if ((conn->send_timeout != 0) && + ((s32_t)(sys_now() - conn->current_msg->msg.w.time_started) >= conn->send_timeout)) { + write_finished = 1; + if (conn->current_msg->msg.w.offset == 0) { + /* nothing has been written */ + err = ERR_WOULDBLOCK; + } else { + /* partial write */ + err = ERR_OK; + } + } else +#endif /* LWIP_SO_SNDTIMEO */ + { + do { + dataptr = (const u8_t *)conn->current_msg->msg.w.vector->ptr + conn->current_msg->msg.w.vector_off; + diff = conn->current_msg->msg.w.vector->len - conn->current_msg->msg.w.vector_off; + if (diff > 0xffffUL) { /* max_u16_t */ + len = 0xffff; + apiflags |= TCP_WRITE_FLAG_MORE; + } else { + len = (u16_t)diff; + } + available = tcp_sndbuf(conn->pcb.tcp); + if (available < len) { + /* don't try to write more than sendbuf */ + len = available; + if (dontblock) { + if (!len) { + /* set error according to partial write or not */ + err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK; + goto err_mem; + } + } else { + apiflags |= TCP_WRITE_FLAG_MORE; + } + } + LWIP_ASSERT("lwip_netconn_do_writemore: invalid length!", + ((conn->current_msg->msg.w.vector_off + len) <= conn->current_msg->msg.w.vector->len)); + /* we should loop around for more sending in the following cases: + 1) We couldn't finish the current vector because of 16-bit size limitations. + tcp_write() and tcp_sndbuf() both are limited to 16-bit sizes + 2) We are sending the remainder of the current vector and have more */ + if ((len == 0xffff && diff > 0xffffUL) || + (len == (u16_t)diff && conn->current_msg->msg.w.vector_cnt > 1)) { + write_more = 1; + apiflags |= TCP_WRITE_FLAG_MORE; + } else { + write_more = 0; + } + err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags); + if (err == ERR_OK) { + conn->current_msg->msg.w.offset += len; + conn->current_msg->msg.w.vector_off += len; + /* check if current vector is finished */ + if (conn->current_msg->msg.w.vector_off == conn->current_msg->msg.w.vector->len) { + conn->current_msg->msg.w.vector_cnt--; + /* if we have additional vectors, move on to them */ + if (conn->current_msg->msg.w.vector_cnt > 0) { + conn->current_msg->msg.w.vector++; + conn->current_msg->msg.w.vector_off = 0; + } + } + } + } while (write_more && err == ERR_OK); + /* if OK or memory error, check available space */ + if ((err == ERR_OK) || (err == ERR_MEM)) { +err_mem: + if (dontblock && (conn->current_msg->msg.w.offset < conn->current_msg->msg.w.len)) { + /* non-blocking write did not write everything: mark the pcb non-writable + and let poll_tcp check writable space to mark the pcb writable again */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0); + conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE; + } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) || + (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT)) { + /* The queued byte- or pbuf-count exceeds the configured low-water limit, + let select mark this pcb as non-writable. */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, 0); + } + } + + if (err == ERR_OK) { + err_t out_err; + if ((conn->current_msg->msg.w.offset == conn->current_msg->msg.w.len) || dontblock) { + /* return sent length (caller reads length from msg.w.offset) */ + write_finished = 1; + } + out_err = tcp_output(conn->pcb.tcp); + if (out_err == ERR_RTE) { + /* If tcp_output fails because no route is found, + don't try writing any more but return the error + to the application thread. */ + err = out_err; + write_finished = 1; + } + } else if (err == ERR_MEM) { + /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called. + For blocking sockets, we do NOT return to the application + thread, since ERR_MEM is only a temporary error! Non-blocking + will remain non-writable until sent_tcp/poll_tcp is called */ + + /* tcp_write returned ERR_MEM, try tcp_output anyway */ + err_t out_err = tcp_output(conn->pcb.tcp); + if (out_err == ERR_RTE) { + /* If tcp_output fails because no route is found, + don't try writing any more but return the error + to the application thread. */ + err = out_err; + write_finished = 1; + } else if (dontblock) { + /* non-blocking write is done on ERR_MEM, set error according + to partial write or not */ + err = (conn->current_msg->msg.w.offset == 0) ? ERR_WOULDBLOCK : ERR_OK; + write_finished = 1; + } + } else { + /* On errors != ERR_MEM, we don't try writing any more but return + the error to the application thread. */ + write_finished = 1; + } + } + if (write_finished) { + /* everything was written: set back connection state + and back to application task */ + sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg->err = err; + conn->current_msg = NULL; + conn->state = NETCONN_NONE; +#if LWIP_TCPIP_CORE_LOCKING + if (delayed) +#endif + { + sys_sem_signal(op_completed_sem); + } + } +#if LWIP_TCPIP_CORE_LOCKING + else { + return ERR_MEM; + } +#endif + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a TCP pcb contained in a netconn + * Called from netconn_write + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_write(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + err_t err = netconn_err(msg->conn); + if (err == ERR_OK) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { +#if LWIP_TCP + if (msg->conn->state != NETCONN_NONE) { + /* netconn is connecting, closing or in blocking write */ + err = ERR_INPROGRESS; + } else if (msg->conn->pcb.tcp != NULL) { + msg->conn->state = NETCONN_WRITE; + /* set all the variables used by lwip_netconn_do_writemore */ + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL); + LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0); + msg->conn->current_msg = msg; +#if LWIP_TCPIP_CORE_LOCKING + if (lwip_netconn_do_writemore(msg->conn, 0) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state != NETCONN_WRITE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + lwip_netconn_do_writemore(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* for both cases: if lwip_netconn_do_writemore was called, don't ACK the APIMSG + since lwip_netconn_do_writemore ACKs it! */ + return; + } else { + err = ERR_CONN; + } +#else /* LWIP_TCP */ + err = ERR_VAL; +#endif /* LWIP_TCP */ +#if (LWIP_UDP || LWIP_RAW) + } else { + err = ERR_VAL; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + } + msg->err = err; + TCPIP_APIMSG_ACK(msg); +} + +/** + * Return a connection's local or remote address + * Called from netconn_getaddr + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_getaddr(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + if (msg->conn->pcb.ip != NULL) { + if (msg->msg.ad.local) { + ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), + msg->conn->pcb.ip->local_ip); + } else { + ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), + msg->conn->pcb.ip->remote_ip); + } + + msg->err = ERR_OK; + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (msg->msg.ad.local) { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.raw->protocol; + } else { + /* return an error as connecting is only a helper for upper layers */ + msg->err = ERR_CONN; + } + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + if (msg->msg.ad.local) { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->local_port; + } else { + if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) { + msg->err = ERR_CONN; + } else { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port; + } + } + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + if ((msg->msg.ad.local == 0) && + ((msg->conn->pcb.tcp->state == CLOSED) || (msg->conn->pcb.tcp->state == LISTEN))) { + /* pcb is not connected and remote name is requested */ + msg->err = ERR_CONN; + } else { + API_EXPR_DEREF(msg->msg.ad.port) = (msg->msg.ad.local ? msg->conn->pcb.tcp->local_port : msg->conn->pcb.tcp->remote_port); + } + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("invalid netconn_type", 0); + break; + } + } else { + msg->err = ERR_CONN; + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * Close or half-shutdown a TCP pcb contained in a netconn + * Called from netconn_close + * In contrast to closing sockets, the netconn is not deallocated. + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_close(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + +#if LWIP_TCP + enum netconn_state state = msg->conn->state; + /* First check if this is a TCP netconn and if it is in a correct state + (LISTEN doesn't support half shutdown) */ + if ((msg->conn->pcb.tcp != NULL) && + (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) && + ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) { + /* Check if we are in a connected state */ + if (state == NETCONN_CONNECT) { + /* TCP connect in progress: cannot shutdown */ + msg->err = ERR_CONN; + } else if (state == NETCONN_WRITE) { +#if LWIP_NETCONN_FULLDUPLEX + if (msg->msg.sd.shut & NETCONN_SHUT_WR) { + /* close requested, abort running write */ + sys_sem_t *write_completed_sem; + LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); + write_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); + msg->conn->current_msg->err = ERR_CLSD; + msg->conn->current_msg = NULL; + msg->conn->state = NETCONN_NONE; + state = NETCONN_NONE; + sys_sem_signal(write_completed_sem); + } else { + LWIP_ASSERT("msg->msg.sd.shut == NETCONN_SHUT_RD", msg->msg.sd.shut == NETCONN_SHUT_RD); + /* In this case, let the write continue and do not interfere with + conn->current_msg or conn->state! */ + msg->err = tcp_shutdown(msg->conn->pcb.tcp, 1, 0); + } + } + if (state == NETCONN_NONE) { +#else /* LWIP_NETCONN_FULLDUPLEX */ + msg->err = ERR_INPROGRESS; + } else { +#endif /* LWIP_NETCONN_FULLDUPLEX */ + if (msg->msg.sd.shut & NETCONN_SHUT_RD) { +#if LWIP_NETCONN_FULLDUPLEX + /* Mark mboxes invalid */ + netconn_mark_mbox_invalid(msg->conn); +#else /* LWIP_NETCONN_FULLDUPLEX */ + netconn_drain(msg->conn); +#endif /* LWIP_NETCONN_FULLDUPLEX */ + } + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL); + msg->conn->state = NETCONN_CLOSE; + msg->conn->current_msg = msg; +#if LWIP_TCPIP_CORE_LOCKING + if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + lwip_netconn_do_close_internal(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* for tcp netconns, lwip_netconn_do_close_internal ACKs the message */ + return; + } + } else +#endif /* LWIP_TCP */ + { + msg->err = ERR_CONN; + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) +/** + * Join multicast groups for UDP netconns. + * Called from netconn_join_leave_group + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_join_leave_group(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { +#if LWIP_UDP +#if LWIP_IPV6 && LWIP_IPV6_MLD + if (NETCONNTYPE_ISIPV6(msg->conn->type)) { + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = mld6_joingroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = mld6_leavegroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } + } else +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + { +#if LWIP_IGMP + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = igmp_joingroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = igmp_leavegroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } +#endif /* LWIP_IGMP */ + } +#endif /* LWIP_UDP */ +#if (LWIP_TCP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_TCP || LWIP_RAW) */ + } + } + TCPIP_APIMSG_ACK(msg); +} +/** + * Join multicast groups for UDP netconns. + * Called from netconn_join_leave_group_netif + * + * @param m the api_msg pointing to the connection + */ +void +lwip_netconn_do_join_leave_group_netif(void *m) +{ + struct api_msg *msg = (struct api_msg *)m; + struct netif *netif; + + netif = netif_get_by_index(msg->msg.jl.if_idx); + if (netif == NULL) { + msg->err = ERR_IF; + goto done; + } + + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { +#if LWIP_UDP +#if LWIP_IPV6 && LWIP_IPV6_MLD + if (NETCONNTYPE_ISIPV6(msg->conn->type)) { + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = mld6_joingroup_netif(netif, + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = mld6_leavegroup_netif(netif, + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } + } else +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + { +#if LWIP_IGMP + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = igmp_joingroup_netif(netif, + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = igmp_leavegroup_netif(netif, + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } +#endif /* LWIP_IGMP */ + } +#endif /* LWIP_UDP */ +#if (LWIP_TCP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_TCP || LWIP_RAW) */ + } + } + +done: + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ + +#if LWIP_DNS +/** + * Callback function that is called when DNS name is resolved + * (or on timeout). A waiting application thread is waked up by + * signaling the semaphore. + */ +static void +lwip_netconn_do_dns_found(const char *name, const ip_addr_t *ipaddr, void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg *)arg; + + /* we trust the internal implementation to be correct :-) */ + LWIP_UNUSED_ARG(name); + + if (ipaddr == NULL) { + /* timeout or memory error */ + API_EXPR_DEREF(msg->err) = ERR_VAL; + } else { + /* address was resolved */ + API_EXPR_DEREF(msg->err) = ERR_OK; + API_EXPR_DEREF(msg->addr) = *ipaddr; + } + /* wake up the application task waiting in netconn_gethostbyname */ + sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); +} + +/** + * Execute a DNS query + * Called from netconn_gethostbyname + * + * @param arg the dns_api_msg pointing to the query + */ +void +lwip_netconn_do_gethostbyname(void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg *)arg; + u8_t addrtype = +#if LWIP_IPV4 && LWIP_IPV6 + msg->dns_addrtype; +#else + LWIP_DNS_ADDRTYPE_DEFAULT; +#endif + + API_EXPR_DEREF(msg->err) = dns_gethostbyname_addrtype(msg->name, + API_EXPR_REF(msg->addr), lwip_netconn_do_dns_found, msg, addrtype); +#if LWIP_TCPIP_CORE_LOCKING + /* For core locking, only block if we need to wait for answer/timeout */ + if (API_EXPR_DEREF(msg->err) == ERR_INPROGRESS) { + UNLOCK_TCPIP_CORE(); + sys_sem_wait(API_EXPR_REF_SEM(msg->sem)); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("do_gethostbyname still in progress!!", API_EXPR_DEREF(msg->err) != ERR_INPROGRESS); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + if (API_EXPR_DEREF(msg->err) != ERR_INPROGRESS) { + /* on error or immediate success, wake up the application + * task waiting in netconn_gethostbyname */ + sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); + } +#endif /* LWIP_TCPIP_CORE_LOCKING */ +} +#endif /* LWIP_DNS */ + +#endif /* LWIP_NETCONN */ diff --git a/Middlewares/Third_Party/LwIP/src/api/err.c b/Middlewares/Third_Party/LwIP/src/api/err.c new file mode 100644 index 0000000..dd2b62d --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/err.c @@ -0,0 +1,115 @@ +/** + * @file + * Error Management module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/err.h" +#include "lwip/def.h" +#include "lwip/sys.h" + +#include "lwip/errno.h" + +#if !NO_SYS +/** Table to quickly map an lwIP error (err_t) to a socket error + * by using -err as an index */ +static const int err_to_errno_table[] = { + 0, /* ERR_OK 0 No error, everything OK. */ + ENOMEM, /* ERR_MEM -1 Out of memory error. */ + ENOBUFS, /* ERR_BUF -2 Buffer error. */ + EWOULDBLOCK, /* ERR_TIMEOUT -3 Timeout */ + EHOSTUNREACH, /* ERR_RTE -4 Routing problem. */ + EINPROGRESS, /* ERR_INPROGRESS -5 Operation in progress */ + EINVAL, /* ERR_VAL -6 Illegal value. */ + EWOULDBLOCK, /* ERR_WOULDBLOCK -7 Operation would block. */ + EADDRINUSE, /* ERR_USE -8 Address in use. */ + EALREADY, /* ERR_ALREADY -9 Already connecting. */ + EISCONN, /* ERR_ISCONN -10 Conn already established.*/ + ENOTCONN, /* ERR_CONN -11 Not connected. */ + -1, /* ERR_IF -12 Low-level netif error */ + ECONNABORTED, /* ERR_ABRT -13 Connection aborted. */ + ECONNRESET, /* ERR_RST -14 Connection reset. */ + ENOTCONN, /* ERR_CLSD -15 Connection closed. */ + EIO /* ERR_ARG -16 Illegal argument. */ +}; + +int +err_to_errno(err_t err) +{ + if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_to_errno_table))) { + return EIO; + } + return err_to_errno_table[-err]; +} +#endif /* !NO_SYS */ + +#ifdef LWIP_DEBUG + +static const char *err_strerr[] = { + "Ok.", /* ERR_OK 0 */ + "Out of memory error.", /* ERR_MEM -1 */ + "Buffer error.", /* ERR_BUF -2 */ + "Timeout.", /* ERR_TIMEOUT -3 */ + "Routing problem.", /* ERR_RTE -4 */ + "Operation in progress.", /* ERR_INPROGRESS -5 */ + "Illegal value.", /* ERR_VAL -6 */ + "Operation would block.", /* ERR_WOULDBLOCK -7 */ + "Address in use.", /* ERR_USE -8 */ + "Already connecting.", /* ERR_ALREADY -9 */ + "Already connected.", /* ERR_ISCONN -10 */ + "Not connected.", /* ERR_CONN -11 */ + "Low-level netif error.", /* ERR_IF -12 */ + "Connection aborted.", /* ERR_ABRT -13 */ + "Connection reset.", /* ERR_RST -14 */ + "Connection closed.", /* ERR_CLSD -15 */ + "Illegal argument." /* ERR_ARG -16 */ +}; + +/** + * Convert an lwip internal error to a string representation. + * + * @param err an lwip internal err_t + * @return a string representation for err + */ +const char * +lwip_strerr(err_t err) +{ + if ((err > 0) || (-err >= (err_t)LWIP_ARRAYSIZE(err_strerr))) { + return "Unknown error."; + } + return err_strerr[-err]; +} + +#endif /* LWIP_DEBUG */ diff --git a/Middlewares/Third_Party/LwIP/src/api/if_api.c b/Middlewares/Third_Party/LwIP/src/api/if_api.c new file mode 100644 index 0000000..8e094d0 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/if_api.c @@ -0,0 +1,102 @@ +/** + * @file + * Interface Identification APIs from: + * RFC 3493: Basic Socket Interface Extensions for IPv6 + * Section 4: Interface Identification + * + * @defgroup if_api Interface Identification API + * @ingroup socket + */ + +/* + * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Joel Cunningham + * + */ +#include "lwip/opt.h" + +#if LWIP_SOCKET + +#include "lwip/errno.h" +#include "lwip/if_api.h" +#include "lwip/netifapi.h" +#include "lwip/priv/sockets_priv.h" + +/** + * @ingroup if_api + * Maps an interface index to its corresponding name. + * @param ifindex interface index + * @param ifname shall point to a buffer of at least {IF_NAMESIZE} bytes + * @return If ifindex is an interface index, then the function shall return the + * value supplied in ifname, which points to a buffer now containing the interface name. + * Otherwise, the function shall return a NULL pointer. + */ +char * +lwip_if_indextoname(unsigned int ifindex, char *ifname) +{ +#if LWIP_NETIF_API + if (ifindex <= 0xff) { + err_t err = netifapi_netif_index_to_name((u8_t)ifindex, ifname); + if (!err && ifname[0] != '\0') { + return ifname; + } + } +#else /* LWIP_NETIF_API */ + LWIP_UNUSED_ARG(ifindex); + LWIP_UNUSED_ARG(ifname); +#endif /* LWIP_NETIF_API */ + set_errno(ENXIO); + return NULL; +} + +/** + * @ingroup if_api + * Returs the interface index corresponding to name ifname. + * @param ifname Interface name + * @return The corresponding index if ifname is the name of an interface; + * otherwise, zero. + */ +unsigned int +lwip_if_nametoindex(const char *ifname) +{ +#if LWIP_NETIF_API + err_t err; + u8_t idx; + + err = netifapi_netif_name_to_index(ifname, &idx); + if (!err) { + return idx; + } +#else /* LWIP_NETIF_API */ + LWIP_UNUSED_ARG(ifname); +#endif /* LWIP_NETIF_API */ + return 0; /* invalid index */ +} + +#endif /* LWIP_SOCKET */ diff --git a/Middlewares/Third_Party/LwIP/src/api/netbuf.c b/Middlewares/Third_Party/LwIP/src/api/netbuf.c new file mode 100644 index 0000000..3b910de --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/netbuf.c @@ -0,0 +1,250 @@ +/** + * @file + * Network buffer management + * + * @defgroup netbuf Network buffers + * @ingroup netconn + * Network buffer descriptor for @ref netconn. Based on @ref pbuf internally + * to avoid copying data around.\n + * Buffers must not be shared accross multiple threads, all functions except + * netbuf_new() and netbuf_delete() are not thread-safe. + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netbuf.h" +#include "lwip/memp.h" + +#include + +/** + * @ingroup netbuf + * Create (allocate) and initialize a new netbuf. + * The netbuf doesn't yet contain a packet buffer! + * + * @return a pointer to a new netbuf + * NULL on lack of memory + */ +struct +netbuf *netbuf_new(void) +{ + struct netbuf *buf; + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf != NULL) { + memset(buf, 0, sizeof(struct netbuf)); + } + return buf; +} + +/** + * @ingroup netbuf + * Deallocate a netbuf allocated by netbuf_new(). + * + * @param buf pointer to a netbuf allocated by netbuf_new() + */ +void +netbuf_delete(struct netbuf *buf) +{ + if (buf != NULL) { + if (buf->p != NULL) { + pbuf_free(buf->p); + buf->p = buf->ptr = NULL; + } + memp_free(MEMP_NETBUF, buf); + } +} + +/** + * @ingroup netbuf + * Allocate memory for a packet buffer for a given netbuf. + * + * @param buf the netbuf for which to allocate a packet buffer + * @param size the size of the packet buffer to allocate + * @return pointer to the allocated memory + * NULL if no memory could be allocated + */ +void * +netbuf_alloc(struct netbuf *buf, u16_t size) +{ + LWIP_ERROR("netbuf_alloc: invalid buf", (buf != NULL), return NULL;); + + /* Deallocate any previously allocated memory. */ + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, size, PBUF_RAM); + if (buf->p == NULL) { + return NULL; + } + LWIP_ASSERT("check that first pbuf can hold size", + (buf->p->len >= size)); + buf->ptr = buf->p; + return buf->p->payload; +} + +/** + * @ingroup netbuf + * Free the packet buffer included in a netbuf + * + * @param buf pointer to the netbuf which contains the packet buffer to free + */ +void +netbuf_free(struct netbuf *buf) +{ + LWIP_ERROR("netbuf_free: invalid buf", (buf != NULL), return;); + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = buf->ptr = NULL; +#if LWIP_CHECKSUM_ON_COPY + buf->flags = 0; + buf->toport_chksum = 0; +#endif /* LWIP_CHECKSUM_ON_COPY */ +} + +/** + * @ingroup netbuf + * Let a netbuf reference existing (non-volatile) data. + * + * @param buf netbuf which should reference the data + * @param dataptr pointer to the data to reference + * @param size size of the data + * @return ERR_OK if data is referenced + * ERR_MEM if data couldn't be referenced due to lack of memory + */ +err_t +netbuf_ref(struct netbuf *buf, const void *dataptr, u16_t size) +{ + LWIP_ERROR("netbuf_ref: invalid buf", (buf != NULL), return ERR_ARG;); + if (buf->p != NULL) { + pbuf_free(buf->p); + } + buf->p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); + if (buf->p == NULL) { + buf->ptr = NULL; + return ERR_MEM; + } + ((struct pbuf_rom *)buf->p)->payload = dataptr; + buf->p->len = buf->p->tot_len = size; + buf->ptr = buf->p; + return ERR_OK; +} + +/** + * @ingroup netbuf + * Chain one netbuf to another (@see pbuf_chain) + * + * @param head the first netbuf + * @param tail netbuf to chain after head, freed by this function, may not be reference after returning + */ +void +netbuf_chain(struct netbuf *head, struct netbuf *tail) +{ + LWIP_ERROR("netbuf_chain: invalid head", (head != NULL), return;); + LWIP_ERROR("netbuf_chain: invalid tail", (tail != NULL), return;); + pbuf_cat(head->p, tail->p); + head->ptr = head->p; + memp_free(MEMP_NETBUF, tail); +} + +/** + * @ingroup netbuf + * Get the data pointer and length of the data inside a netbuf. + * + * @param buf netbuf to get the data from + * @param dataptr pointer to a void pointer where to store the data pointer + * @param len pointer to an u16_t where the length of the data is stored + * @return ERR_OK if the information was retrieved, + * ERR_BUF on error. + */ +err_t +netbuf_data(struct netbuf *buf, void **dataptr, u16_t *len) +{ + LWIP_ERROR("netbuf_data: invalid buf", (buf != NULL), return ERR_ARG;); + LWIP_ERROR("netbuf_data: invalid dataptr", (dataptr != NULL), return ERR_ARG;); + LWIP_ERROR("netbuf_data: invalid len", (len != NULL), return ERR_ARG;); + + if (buf->ptr == NULL) { + return ERR_BUF; + } + *dataptr = buf->ptr->payload; + *len = buf->ptr->len; + return ERR_OK; +} + +/** + * @ingroup netbuf + * Move the current data pointer of a packet buffer contained in a netbuf + * to the next part. + * The packet buffer itself is not modified. + * + * @param buf the netbuf to modify + * @return -1 if there is no next part + * 1 if moved to the next part but now there is no next part + * 0 if moved to the next part and there are still more parts + */ +s8_t +netbuf_next(struct netbuf *buf) +{ + LWIP_ERROR("netbuf_next: invalid buf", (buf != NULL), return -1;); + if (buf->ptr->next == NULL) { + return -1; + } + buf->ptr = buf->ptr->next; + if (buf->ptr->next == NULL) { + return 1; + } + return 0; +} + +/** + * @ingroup netbuf + * Move the current data pointer of a packet buffer contained in a netbuf + * to the beginning of the packet. + * The packet buffer itself is not modified. + * + * @param buf the netbuf to modify + */ +void +netbuf_first(struct netbuf *buf) +{ + LWIP_ERROR("netbuf_first: invalid buf", (buf != NULL), return;); + buf->ptr = buf->p; +} + +#endif /* LWIP_NETCONN */ diff --git a/Middlewares/Third_Party/LwIP/src/api/netdb.c b/Middlewares/Third_Party/LwIP/src/api/netdb.c new file mode 100644 index 0000000..8771425 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/netdb.c @@ -0,0 +1,414 @@ +/** + * @file + * API functions for name resolving + * + * @defgroup netdbapi NETDB API + * @ingroup socket + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/netdb.h" + +#if LWIP_DNS && LWIP_SOCKET + +#include "lwip/err.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/ip_addr.h" +#include "lwip/api.h" +#include "lwip/dns.h" + +#include /* memset */ +#include /* atoi */ + +/** helper struct for gethostbyname_r to access the char* buffer */ +struct gethostbyname_r_helper { + ip_addr_t *addr_list[2]; + ip_addr_t addr; + char *aliases; +}; + +/** h_errno is exported in netdb.h for access by applications. */ +#if LWIP_DNS_API_DECLARE_H_ERRNO +int h_errno; +#endif /* LWIP_DNS_API_DECLARE_H_ERRNO */ + +/** define "hostent" variables storage: 0 if we use a static (but unprotected) + * set of variables for lwip_gethostbyname, 1 if we use a local storage */ +#ifndef LWIP_DNS_API_HOSTENT_STORAGE +#define LWIP_DNS_API_HOSTENT_STORAGE 0 +#endif + +/** define "hostent" variables storage */ +#if LWIP_DNS_API_HOSTENT_STORAGE +#define HOSTENT_STORAGE +#else +#define HOSTENT_STORAGE static +#endif /* LWIP_DNS_API_STATIC_HOSTENT */ + +/** + * Returns an entry containing addresses of address family AF_INET + * for the host with name name. + * Due to dns_gethostbyname limitations, only one address is returned. + * + * @param name the hostname to resolve + * @return an entry containing addresses of address family AF_INET + * for the host with name name + */ +struct hostent * +lwip_gethostbyname(const char *name) +{ + err_t err; + ip_addr_t addr; + + /* buffer variables for lwip_gethostbyname() */ + HOSTENT_STORAGE struct hostent s_hostent; + HOSTENT_STORAGE char *s_aliases; + HOSTENT_STORAGE ip_addr_t s_hostent_addr; + HOSTENT_STORAGE ip_addr_t *s_phostent_addr[2]; + HOSTENT_STORAGE char s_hostname[DNS_MAX_NAME_LENGTH + 1]; + + /* query host IP address */ + err = netconn_gethostbyname(name, &addr); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err)); + h_errno = HOST_NOT_FOUND; + return NULL; + } + + /* fill hostent */ + s_hostent_addr = addr; + s_phostent_addr[0] = &s_hostent_addr; + s_phostent_addr[1] = NULL; + strncpy(s_hostname, name, DNS_MAX_NAME_LENGTH); + s_hostname[DNS_MAX_NAME_LENGTH] = 0; + s_hostent.h_name = s_hostname; + s_aliases = NULL; + s_hostent.h_aliases = &s_aliases; + s_hostent.h_addrtype = AF_INET; + s_hostent.h_length = sizeof(ip_addr_t); + s_hostent.h_addr_list = (char **)&s_phostent_addr; + +#if DNS_DEBUG + /* dump hostent */ + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_name == %s\n", s_hostent.h_name)); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_aliases == %p\n", (void *)s_hostent.h_aliases)); + /* h_aliases are always empty */ + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addrtype == %d\n", s_hostent.h_addrtype)); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_length == %d\n", s_hostent.h_length)); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list == %p\n", (void *)s_hostent.h_addr_list)); + if (s_hostent.h_addr_list != NULL) { + u8_t idx; + for (idx = 0; s_hostent.h_addr_list[idx]; idx++) { + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i] == %p\n", idx, s_hostent.h_addr_list[idx])); + LWIP_DEBUGF(DNS_DEBUG, ("hostent.h_addr_list[%i]-> == %s\n", idx, ipaddr_ntoa((ip_addr_t *)s_hostent.h_addr_list[idx]))); + } + } +#endif /* DNS_DEBUG */ + +#if LWIP_DNS_API_HOSTENT_STORAGE + /* this function should return the "per-thread" hostent after copy from s_hostent */ + return sys_thread_hostent(&s_hostent); +#else + return &s_hostent; +#endif /* LWIP_DNS_API_HOSTENT_STORAGE */ +} + +/** + * Thread-safe variant of lwip_gethostbyname: instead of using a static + * buffer, this function takes buffer and errno pointers as arguments + * and uses these for the result. + * + * @param name the hostname to resolve + * @param ret pre-allocated struct where to store the result + * @param buf pre-allocated buffer where to store additional data + * @param buflen the size of buf + * @param result pointer to a hostent pointer that is set to ret on success + * and set to zero on error + * @param h_errnop pointer to an int where to store errors (instead of modifying + * the global h_errno) + * @return 0 on success, non-zero on error, additional error information + * is stored in *h_errnop instead of h_errno to be thread-safe + */ +int +lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, + size_t buflen, struct hostent **result, int *h_errnop) +{ + err_t err; + struct gethostbyname_r_helper *h; + char *hostname; + size_t namelen; + int lh_errno; + + if (h_errnop == NULL) { + /* ensure h_errnop is never NULL */ + h_errnop = &lh_errno; + } + + if (result == NULL) { + /* not all arguments given */ + *h_errnop = EINVAL; + return -1; + } + /* first thing to do: set *result to nothing */ + *result = NULL; + if ((name == NULL) || (ret == NULL) || (buf == NULL)) { + /* not all arguments given */ + *h_errnop = EINVAL; + return -1; + } + + namelen = strlen(name); + if (buflen < (sizeof(struct gethostbyname_r_helper) + LWIP_MEM_ALIGN_BUFFER(namelen + 1))) { + /* buf can't hold the data needed + a copy of name */ + *h_errnop = ERANGE; + return -1; + } + + h = (struct gethostbyname_r_helper *)LWIP_MEM_ALIGN(buf); + hostname = ((char *)h) + sizeof(struct gethostbyname_r_helper); + + /* query host IP address */ + err = netconn_gethostbyname(name, &h->addr); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG, ("lwip_gethostbyname(%s) failed, err=%d\n", name, err)); + *h_errnop = HOST_NOT_FOUND; + return -1; + } + + /* copy the hostname into buf */ + MEMCPY(hostname, name, namelen); + hostname[namelen] = 0; + + /* fill hostent */ + h->addr_list[0] = &h->addr; + h->addr_list[1] = NULL; + h->aliases = NULL; + ret->h_name = hostname; + ret->h_aliases = &h->aliases; + ret->h_addrtype = AF_INET; + ret->h_length = sizeof(ip_addr_t); + ret->h_addr_list = (char **)&h->addr_list; + + /* set result != NULL */ + *result = ret; + + /* return success */ + return 0; +} + +/** + * Frees one or more addrinfo structures returned by getaddrinfo(), along with + * any additional storage associated with those structures. If the ai_next field + * of the structure is not null, the entire list of structures is freed. + * + * @param ai struct addrinfo to free + */ +void +lwip_freeaddrinfo(struct addrinfo *ai) +{ + struct addrinfo *next; + + while (ai != NULL) { + next = ai->ai_next; + memp_free(MEMP_NETDB, ai); + ai = next; + } +} + +/** + * Translates the name of a service location (for example, a host name) and/or + * a service name and returns a set of socket addresses and associated + * information to be used in creating a socket with which to address the + * specified service. + * Memory for the result is allocated internally and must be freed by calling + * lwip_freeaddrinfo()! + * + * Due to a limitation in dns_gethostbyname, only the first address of a + * host is returned. + * Also, service names are not supported (only port numbers)! + * + * @param nodename descriptive name or address string of the host + * (may be NULL -> local address) + * @param servname port number as string of NULL + * @param hints structure containing input values that set socktype and protocol + * @param res pointer to a pointer where to store the result (set to NULL on failure) + * @return 0 on success, non-zero on failure + * + * @todo: implement AI_V4MAPPED, AI_ADDRCONFIG + */ +int +lwip_getaddrinfo(const char *nodename, const char *servname, + const struct addrinfo *hints, struct addrinfo **res) +{ + err_t err; + ip_addr_t addr; + struct addrinfo *ai; + struct sockaddr_storage *sa = NULL; + int port_nr = 0; + size_t total_size; + size_t namelen = 0; + int ai_family; + + if (res == NULL) { + return EAI_FAIL; + } + *res = NULL; + if ((nodename == NULL) && (servname == NULL)) { + return EAI_NONAME; + } + + if (hints != NULL) { + ai_family = hints->ai_family; + if ((ai_family != AF_UNSPEC) +#if LWIP_IPV4 + && (ai_family != AF_INET) +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 + && (ai_family != AF_INET6) +#endif /* LWIP_IPV6 */ + ) { + return EAI_FAMILY; + } + } else { + ai_family = AF_UNSPEC; + } + + if (servname != NULL) { + /* service name specified: convert to port number + * @todo?: currently, only ASCII integers (port numbers) are supported (AI_NUMERICSERV)! */ + port_nr = atoi(servname); + if ((port_nr <= 0) || (port_nr > 0xffff)) { + return EAI_SERVICE; + } + } + + if (nodename != NULL) { + /* service location specified, try to resolve */ + if ((hints != NULL) && (hints->ai_flags & AI_NUMERICHOST)) { + /* no DNS lookup, just parse for an address string */ + if (!ipaddr_aton(nodename, &addr)) { + return EAI_NONAME; + } +#if LWIP_IPV4 && LWIP_IPV6 + if ((IP_IS_V6_VAL(addr) && ai_family == AF_INET) || + (IP_IS_V4_VAL(addr) && ai_family == AF_INET6)) { + return EAI_NONAME; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + } else { +#if LWIP_IPV4 && LWIP_IPV6 + /* AF_UNSPEC: prefer IPv4 */ + u8_t type = NETCONN_DNS_IPV4_IPV6; + if (ai_family == AF_INET) { + type = NETCONN_DNS_IPV4; + } else if (ai_family == AF_INET6) { + type = NETCONN_DNS_IPV6; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + err = netconn_gethostbyname_addrtype(nodename, &addr, type); + if (err != ERR_OK) { + return EAI_FAIL; + } + } + } else { + /* service location specified, use loopback address */ + if ((hints != NULL) && (hints->ai_flags & AI_PASSIVE)) { + ip_addr_set_any_val(ai_family == AF_INET6, addr); + } else { + ip_addr_set_loopback_val(ai_family == AF_INET6, addr); + } + } + + total_size = sizeof(struct addrinfo) + sizeof(struct sockaddr_storage); + if (nodename != NULL) { + namelen = strlen(nodename); + if (namelen > DNS_MAX_NAME_LENGTH) { + /* invalid name length */ + return EAI_FAIL; + } + LWIP_ASSERT("namelen is too long", total_size + namelen + 1 > total_size); + total_size += namelen + 1; + } + /* If this fails, please report to lwip-devel! :-) */ + LWIP_ASSERT("total_size <= NETDB_ELEM_SIZE: please report this!", + total_size <= NETDB_ELEM_SIZE); + ai = (struct addrinfo *)memp_malloc(MEMP_NETDB); + if (ai == NULL) { + return EAI_MEMORY; + } + memset(ai, 0, total_size); + /* cast through void* to get rid of alignment warnings */ + sa = (struct sockaddr_storage *)(void *)((u8_t *)ai + sizeof(struct addrinfo)); + if (IP_IS_V6_VAL(addr)) { +#if LWIP_IPV6 + struct sockaddr_in6 *sa6 = (struct sockaddr_in6 *)sa; + /* set up sockaddr */ + inet6_addr_from_ip6addr(&sa6->sin6_addr, ip_2_ip6(&addr)); + sa6->sin6_family = AF_INET6; + sa6->sin6_len = sizeof(struct sockaddr_in6); + sa6->sin6_port = lwip_htons((u16_t)port_nr); + sa6->sin6_scope_id = ip6_addr_zone(ip_2_ip6(&addr)); + ai->ai_family = AF_INET6; +#endif /* LWIP_IPV6 */ + } else { +#if LWIP_IPV4 + struct sockaddr_in *sa4 = (struct sockaddr_in *)sa; + /* set up sockaddr */ + inet_addr_from_ip4addr(&sa4->sin_addr, ip_2_ip4(&addr)); + sa4->sin_family = AF_INET; + sa4->sin_len = sizeof(struct sockaddr_in); + sa4->sin_port = lwip_htons((u16_t)port_nr); + ai->ai_family = AF_INET; +#endif /* LWIP_IPV4 */ + } + + /* set up addrinfo */ + if (hints != NULL) { + /* copy socktype & protocol from hints if specified */ + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + if (nodename != NULL) { + /* copy nodename to canonname if specified */ + ai->ai_canonname = ((char *)ai + sizeof(struct addrinfo) + sizeof(struct sockaddr_storage)); + MEMCPY(ai->ai_canonname, nodename, namelen); + ai->ai_canonname[namelen] = 0; + } + ai->ai_addrlen = sizeof(struct sockaddr_storage); + ai->ai_addr = (struct sockaddr *)sa; + + *res = ai; + + return 0; +} + +#endif /* LWIP_DNS && LWIP_SOCKET */ diff --git a/Middlewares/Third_Party/LwIP/src/api/netifapi.c b/Middlewares/Third_Party/LwIP/src/api/netifapi.c new file mode 100644 index 0000000..25957cd --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/netifapi.c @@ -0,0 +1,380 @@ +/** + * @file + * Network Interface Sequential API module + * + * @defgroup netifapi NETIF API + * @ingroup sequential_api + * Thread-safe functions to be called from non-TCPIP threads + * + * @defgroup netifapi_netif NETIF related + * @ingroup netifapi + * To be called from non-TCPIP threads + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/opt.h" + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/etharp.h" +#include "lwip/netifapi.h" +#include "lwip/memp.h" +#include "lwip/priv/tcpip_priv.h" + +#include /* strncpy */ + +#define NETIFAPI_VAR_REF(name) API_VAR_REF(name) +#define NETIFAPI_VAR_DECLARE(name) API_VAR_DECLARE(struct netifapi_msg, name) +#define NETIFAPI_VAR_ALLOC(name) API_VAR_ALLOC(struct netifapi_msg, MEMP_NETIFAPI_MSG, name, ERR_MEM) +#define NETIFAPI_VAR_FREE(name) API_VAR_FREE(MEMP_NETIFAPI_MSG, name) + +/** + * Call netif_add() inside the tcpip_thread context. + */ +static err_t +netifapi_do_netif_add(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct netifapi_msg */ + struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m; + + if (!netif_add( msg->netif, +#if LWIP_IPV4 + API_EXPR_REF(msg->msg.add.ipaddr), + API_EXPR_REF(msg->msg.add.netmask), + API_EXPR_REF(msg->msg.add.gw), +#endif /* LWIP_IPV4 */ + msg->msg.add.state, + msg->msg.add.init, + msg->msg.add.input)) { + return ERR_IF; + } else { + return ERR_OK; + } +} + +#if LWIP_IPV4 +/** + * Call netif_set_addr() inside the tcpip_thread context. + */ +static err_t +netifapi_do_netif_set_addr(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct netifapi_msg */ + struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m; + + netif_set_addr( msg->netif, + API_EXPR_REF(msg->msg.add.ipaddr), + API_EXPR_REF(msg->msg.add.netmask), + API_EXPR_REF(msg->msg.add.gw)); + return ERR_OK; +} +#endif /* LWIP_IPV4 */ + +/** +* Call netif_name_to_index() inside the tcpip_thread context. +*/ +static err_t +netifapi_do_name_to_index(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct netifapi_msg */ + struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m; + + msg->msg.ifs.index = netif_name_to_index(msg->msg.ifs.name); + return ERR_OK; +} + +/** +* Call netif_index_to_name() inside the tcpip_thread context. +*/ +static err_t +netifapi_do_index_to_name(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct netifapi_msg */ + struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m; + + if (!netif_index_to_name(msg->msg.ifs.index, msg->msg.ifs.name)) { + /* return failure via empty name */ + msg->msg.ifs.name[0] = '\0'; + } + return ERR_OK; +} + +/** + * Call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) inside the + * tcpip_thread context. + */ +static err_t +netifapi_do_netif_common(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct netifapi_msg */ + struct netifapi_msg *msg = (struct netifapi_msg *)(void *)m; + + if (msg->msg.common.errtfunc != NULL) { + return msg->msg.common.errtfunc(msg->netif); + } else { + msg->msg.common.voidfunc(msg->netif); + return ERR_OK; + } +} + +#if LWIP_ARP && LWIP_IPV4 +/** + * @ingroup netifapi_arp + * Add or update an entry in the ARP cache. + * For an update, ipaddr is used to find the cache entry. + * + * @param ipaddr IPv4 address of cache entry + * @param ethaddr hardware address mapped to ipaddr + * @param type type of ARP cache entry + * @return ERR_OK: entry added/updated, else error from err_t + */ +err_t +netifapi_arp_add(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, enum netifapi_arp_entry type) +{ + err_t err; + + /* We only support permanent entries currently */ + LWIP_UNUSED_ARG(type); + +#if ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING + LOCK_TCPIP_CORE(); + err = etharp_add_static_entry(ipaddr, ethaddr); + UNLOCK_TCPIP_CORE(); +#else + /* @todo add new vars to struct netifapi_msg and create a 'do' func */ + LWIP_UNUSED_ARG(ipaddr); + LWIP_UNUSED_ARG(ethaddr); + err = ERR_VAL; +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING */ + + return err; +} + +/** + * @ingroup netifapi_arp + * Remove an entry in the ARP cache identified by ipaddr + * + * @param ipaddr IPv4 address of cache entry + * @param type type of ARP cache entry + * @return ERR_OK: entry removed, else error from err_t + */ +err_t +netifapi_arp_remove(const ip4_addr_t *ipaddr, enum netifapi_arp_entry type) +{ + err_t err; + + /* We only support permanent entries currently */ + LWIP_UNUSED_ARG(type); + +#if ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING + LOCK_TCPIP_CORE(); + err = etharp_remove_static_entry(ipaddr); + UNLOCK_TCPIP_CORE(); +#else + /* @todo add new vars to struct netifapi_msg and create a 'do' func */ + LWIP_UNUSED_ARG(ipaddr); + err = ERR_VAL; +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES && LWIP_TCPIP_CORE_LOCKING */ + + return err; +} +#endif /* LWIP_ARP && LWIP_IPV4 */ + +/** + * @ingroup netifapi_netif + * Call netif_add() in a thread-safe way by running that function inside the + * tcpip_thread context. + * + * @note for params @see netif_add() + */ +err_t +netifapi_netif_add(struct netif *netif, +#if LWIP_IPV4 + const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, +#endif /* LWIP_IPV4 */ + void *state, netif_init_fn init, netif_input_fn input) +{ + err_t err; + NETIFAPI_VAR_DECLARE(msg); + NETIFAPI_VAR_ALLOC(msg); + +#if LWIP_IPV4 + if (ipaddr == NULL) { + ipaddr = IP4_ADDR_ANY4; + } + if (netmask == NULL) { + netmask = IP4_ADDR_ANY4; + } + if (gw == NULL) { + gw = IP4_ADDR_ANY4; + } +#endif /* LWIP_IPV4 */ + + NETIFAPI_VAR_REF(msg).netif = netif; +#if LWIP_IPV4 + NETIFAPI_VAR_REF(msg).msg.add.ipaddr = NETIFAPI_VAR_REF(ipaddr); + NETIFAPI_VAR_REF(msg).msg.add.netmask = NETIFAPI_VAR_REF(netmask); + NETIFAPI_VAR_REF(msg).msg.add.gw = NETIFAPI_VAR_REF(gw); +#endif /* LWIP_IPV4 */ + NETIFAPI_VAR_REF(msg).msg.add.state = state; + NETIFAPI_VAR_REF(msg).msg.add.init = init; + NETIFAPI_VAR_REF(msg).msg.add.input = input; + err = tcpip_api_call(netifapi_do_netif_add, &API_VAR_REF(msg).call); + NETIFAPI_VAR_FREE(msg); + return err; +} + +#if LWIP_IPV4 +/** + * @ingroup netifapi_netif + * Call netif_set_addr() in a thread-safe way by running that function inside the + * tcpip_thread context. + * + * @note for params @see netif_set_addr() + */ +err_t +netifapi_netif_set_addr(struct netif *netif, + const ip4_addr_t *ipaddr, + const ip4_addr_t *netmask, + const ip4_addr_t *gw) +{ + err_t err; + NETIFAPI_VAR_DECLARE(msg); + NETIFAPI_VAR_ALLOC(msg); + + if (ipaddr == NULL) { + ipaddr = IP4_ADDR_ANY4; + } + if (netmask == NULL) { + netmask = IP4_ADDR_ANY4; + } + if (gw == NULL) { + gw = IP4_ADDR_ANY4; + } + + NETIFAPI_VAR_REF(msg).netif = netif; + NETIFAPI_VAR_REF(msg).msg.add.ipaddr = NETIFAPI_VAR_REF(ipaddr); + NETIFAPI_VAR_REF(msg).msg.add.netmask = NETIFAPI_VAR_REF(netmask); + NETIFAPI_VAR_REF(msg).msg.add.gw = NETIFAPI_VAR_REF(gw); + err = tcpip_api_call(netifapi_do_netif_set_addr, &API_VAR_REF(msg).call); + NETIFAPI_VAR_FREE(msg); + return err; +} +#endif /* LWIP_IPV4 */ + +/** + * call the "errtfunc" (or the "voidfunc" if "errtfunc" is NULL) in a thread-safe + * way by running that function inside the tcpip_thread context. + * + * @note use only for functions where there is only "netif" parameter. + */ +err_t +netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc, + netifapi_errt_fn errtfunc) +{ + err_t err; + NETIFAPI_VAR_DECLARE(msg); + NETIFAPI_VAR_ALLOC(msg); + + NETIFAPI_VAR_REF(msg).netif = netif; + NETIFAPI_VAR_REF(msg).msg.common.voidfunc = voidfunc; + NETIFAPI_VAR_REF(msg).msg.common.errtfunc = errtfunc; + err = tcpip_api_call(netifapi_do_netif_common, &API_VAR_REF(msg).call); + NETIFAPI_VAR_FREE(msg); + return err; +} + +/** +* @ingroup netifapi_netif +* Call netif_name_to_index() in a thread-safe way by running that function inside the +* tcpip_thread context. +* +* @param name the interface name of the netif +* @param idx output index of the found netif +*/ +err_t +netifapi_netif_name_to_index(const char *name, u8_t *idx) +{ + err_t err; + NETIFAPI_VAR_DECLARE(msg); + NETIFAPI_VAR_ALLOC(msg); + + *idx = 0; + +#if LWIP_MPU_COMPATIBLE + strncpy(NETIFAPI_VAR_REF(msg).msg.ifs.name, name, NETIF_NAMESIZE - 1); + NETIFAPI_VAR_REF(msg).msg.ifs.name[NETIF_NAMESIZE - 1] = '\0'; +#else + NETIFAPI_VAR_REF(msg).msg.ifs.name = LWIP_CONST_CAST(char *, name); +#endif /* LWIP_MPU_COMPATIBLE */ + err = tcpip_api_call(netifapi_do_name_to_index, &API_VAR_REF(msg).call); + if (!err) { + *idx = NETIFAPI_VAR_REF(msg).msg.ifs.index; + } + NETIFAPI_VAR_FREE(msg); + return err; +} + +/** +* @ingroup netifapi_netif +* Call netif_index_to_name() in a thread-safe way by running that function inside the +* tcpip_thread context. +* +* @param idx the interface index of the netif +* @param name output name of the found netif, empty '\0' string if netif not found. +* name should be of at least NETIF_NAMESIZE bytes +*/ +err_t +netifapi_netif_index_to_name(u8_t idx, char *name) +{ + err_t err; + NETIFAPI_VAR_DECLARE(msg); + NETIFAPI_VAR_ALLOC(msg); + + NETIFAPI_VAR_REF(msg).msg.ifs.index = idx; +#if !LWIP_MPU_COMPATIBLE + NETIFAPI_VAR_REF(msg).msg.ifs.name = name; +#endif /* LWIP_MPU_COMPATIBLE */ + err = tcpip_api_call(netifapi_do_index_to_name, &API_VAR_REF(msg).call); +#if LWIP_MPU_COMPATIBLE + if (!err) { + strncpy(name, NETIFAPI_VAR_REF(msg).msg.ifs.name, NETIF_NAMESIZE - 1); + name[NETIF_NAMESIZE - 1] = '\0'; + } +#endif /* LWIP_MPU_COMPATIBLE */ + NETIFAPI_VAR_FREE(msg); + return err; +} + +#endif /* LWIP_NETIF_API */ diff --git a/Middlewares/Third_Party/LwIP/src/api/sockets.c b/Middlewares/Third_Party/LwIP/src/api/sockets.c new file mode 100644 index 0000000..cb7df91 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/sockets.c @@ -0,0 +1,4160 @@ +/** + * @file + * Sockets BSD-Like API module + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * Improved by Marc Boucher and David Haas + * + */ + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sockets.h" +#include "lwip/priv/sockets_priv.h" +#include "lwip/api.h" +#include "lwip/igmp.h" +#include "lwip/inet.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/priv/tcpip_priv.h" +#include "lwip/mld6.h" +#if LWIP_CHECKSUM_ON_COPY +#include "lwip/inet_chksum.h" +#endif + +#if LWIP_COMPAT_SOCKETS == 2 && LWIP_POSIX_SOCKETS_IO_NAMES +#include +#endif + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +/* If the netconn API is not required publicly, then we include the necessary + files here to get the implementation */ +#if !LWIP_NETCONN +#undef LWIP_NETCONN +#define LWIP_NETCONN 1 +#include "api_msg.c" +#include "api_lib.c" +#include "netbuf.c" +#undef LWIP_NETCONN +#define LWIP_NETCONN 0 +#endif + +#define API_SELECT_CB_VAR_REF(name) API_VAR_REF(name) +#define API_SELECT_CB_VAR_DECLARE(name) API_VAR_DECLARE(struct lwip_select_cb, name) +#define API_SELECT_CB_VAR_ALLOC(name, retblock) API_VAR_ALLOC_EXT(struct lwip_select_cb, MEMP_SELECT_CB, name, retblock) +#define API_SELECT_CB_VAR_FREE(name) API_VAR_FREE(MEMP_SELECT_CB, name) + +#if LWIP_IPV4 +#define IP4ADDR_PORT_TO_SOCKADDR(sin, ipaddr, port) do { \ + (sin)->sin_len = sizeof(struct sockaddr_in); \ + (sin)->sin_family = AF_INET; \ + (sin)->sin_port = lwip_htons((port)); \ + inet_addr_from_ip4addr(&(sin)->sin_addr, ipaddr); \ + memset((sin)->sin_zero, 0, SIN_ZERO_LEN); }while(0) +#define SOCKADDR4_TO_IP4ADDR_PORT(sin, ipaddr, port) do { \ + inet_addr_to_ip4addr(ip_2_ip4(ipaddr), &((sin)->sin_addr)); \ + (port) = lwip_ntohs((sin)->sin_port); }while(0) +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +#define IP6ADDR_PORT_TO_SOCKADDR(sin6, ipaddr, port) do { \ + (sin6)->sin6_len = sizeof(struct sockaddr_in6); \ + (sin6)->sin6_family = AF_INET6; \ + (sin6)->sin6_port = lwip_htons((port)); \ + (sin6)->sin6_flowinfo = 0; \ + inet6_addr_from_ip6addr(&(sin6)->sin6_addr, ipaddr); \ + (sin6)->sin6_scope_id = ip6_addr_zone(ipaddr); }while(0) +#define SOCKADDR6_TO_IP6ADDR_PORT(sin6, ipaddr, port) do { \ + inet6_addr_to_ip6addr(ip_2_ip6(ipaddr), &((sin6)->sin6_addr)); \ + if (ip6_addr_has_scope(ip_2_ip6(ipaddr), IP6_UNKNOWN)) { \ + ip6_addr_set_zone(ip_2_ip6(ipaddr), (u8_t)((sin6)->sin6_scope_id)); \ + } \ + (port) = lwip_ntohs((sin6)->sin6_port); }while(0) +#endif /* LWIP_IPV6 */ + +#if LWIP_IPV4 && LWIP_IPV6 +static void sockaddr_to_ipaddr_port(const struct sockaddr *sockaddr, ip_addr_t *ipaddr, u16_t *port); + +#define IS_SOCK_ADDR_LEN_VALID(namelen) (((namelen) == sizeof(struct sockaddr_in)) || \ + ((namelen) == sizeof(struct sockaddr_in6))) +#define IS_SOCK_ADDR_TYPE_VALID(name) (((name)->sa_family == AF_INET) || \ + ((name)->sa_family == AF_INET6)) +#define SOCK_ADDR_TYPE_MATCH(name, sock) \ + ((((name)->sa_family == AF_INET) && !(NETCONNTYPE_ISIPV6((sock)->conn->type))) || \ + (((name)->sa_family == AF_INET6) && (NETCONNTYPE_ISIPV6((sock)->conn->type)))) +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) do { \ + if (IP_IS_ANY_TYPE_VAL(*ipaddr) || IP_IS_V6_VAL(*ipaddr)) { \ + IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port); \ + } else { \ + IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port); \ + } } while(0) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) sockaddr_to_ipaddr_port(sockaddr, ipaddr, &(port)) +#define DOMAIN_TO_NETCONN_TYPE(domain, type) (((domain) == AF_INET) ? \ + (type) : (enum netconn_type)((type) | NETCONN_TYPE_IPV6)) +#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ +#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in6)) +#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET6) +#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ + IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ + SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, port) +#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) +#else /*-> LWIP_IPV4: LWIP_IPV4 && LWIP_IPV6 */ +#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in)) +#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET) +#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ + IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ + SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, port) +#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) +#endif /* LWIP_IPV6 */ + +#define IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) (((name)->sa_family == AF_UNSPEC) || \ + IS_SOCK_ADDR_TYPE_VALID(name)) +#define SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock) (((name)->sa_family == AF_UNSPEC) || \ + SOCK_ADDR_TYPE_MATCH(name, sock)) +#define IS_SOCK_ADDR_ALIGNED(name) ((((mem_ptr_t)(name)) % 4) == 0) + + +#define LWIP_SOCKOPT_CHECK_OPTLEN(sock, optlen, opttype) do { if ((optlen) < sizeof(opttype)) { done_socket(sock); return EINVAL; }}while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, opttype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN(sock, optlen, opttype); \ + if ((sock)->conn == NULL) { done_socket(sock); return EINVAL; } }while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN(sock, optlen, opttype); \ + if (((sock)->conn == NULL) || ((sock)->conn->pcb.tcp == NULL)) { done_socket(sock); return EINVAL; } }while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, opttype, netconntype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype); \ + if (NETCONNTYPE_GROUP(netconn_type((sock)->conn)) != netconntype) { done_socket(sock); return ENOPROTOOPT; } }while(0) + + +#define LWIP_SETGETSOCKOPT_DATA_VAR_REF(name) API_VAR_REF(name) +#define LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(name) API_VAR_DECLARE(struct lwip_setgetsockopt_data, name) +#define LWIP_SETGETSOCKOPT_DATA_VAR_FREE(name) API_VAR_FREE(MEMP_SOCKET_SETGETSOCKOPT_DATA, name) +#if LWIP_MPU_COMPATIBLE +#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) do { \ + name = (struct lwip_setgetsockopt_data *)memp_malloc(MEMP_SOCKET_SETGETSOCKOPT_DATA); \ + if (name == NULL) { \ + sock_set_errno(sock, ENOMEM); \ + done_socket(sock); \ + return -1; \ + } }while(0) +#else /* LWIP_MPU_COMPATIBLE */ +#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) +#endif /* LWIP_MPU_COMPATIBLE */ + +#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD +#define LWIP_SO_SNDRCVTIMEO_OPTTYPE int +#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) (*(int *)(optval) = (val)) +#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((long)*(const int*)(optval)) +#else +#define LWIP_SO_SNDRCVTIMEO_OPTTYPE struct timeval +#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) do { \ + u32_t loc = (val); \ + ((struct timeval *)(optval))->tv_sec = (long)((loc) / 1000U); \ + ((struct timeval *)(optval))->tv_usec = (long)(((loc) % 1000U) * 1000U); }while(0) +#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((((const struct timeval *)(optval))->tv_sec * 1000) + (((const struct timeval *)(optval))->tv_usec / 1000)) +#endif + + +/** A struct sockaddr replacement that has the same alignment as sockaddr_in/ + * sockaddr_in6 if instantiated. + */ +union sockaddr_aligned { + struct sockaddr sa; +#if LWIP_IPV6 + struct sockaddr_in6 sin6; +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + struct sockaddr_in sin; +#endif /* LWIP_IPV4 */ +}; + +/* Define the number of IPv4 multicast memberships, default is one per socket */ +#ifndef LWIP_SOCKET_MAX_MEMBERSHIPS +#define LWIP_SOCKET_MAX_MEMBERSHIPS NUM_SOCKETS +#endif + +#if LWIP_IGMP +/* This is to keep track of IP_ADD_MEMBERSHIP calls to drop the membership when + a socket is closed */ +struct lwip_socket_multicast_pair { + /** the socket */ + struct lwip_sock *sock; + /** the interface address */ + ip4_addr_t if_addr; + /** the group address */ + ip4_addr_t multi_addr; +}; + +static struct lwip_socket_multicast_pair socket_ipv4_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS]; + +static int lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); +static void lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); +static void lwip_socket_drop_registered_memberships(int s); +#endif /* LWIP_IGMP */ + +#if LWIP_IPV6_MLD +/* This is to keep track of IP_JOIN_GROUP calls to drop the membership when + a socket is closed */ +struct lwip_socket_multicast_mld6_pair { + /** the socket */ + struct lwip_sock *sock; + /** the interface index */ + u8_t if_idx; + /** the group address */ + ip6_addr_t multi_addr; +}; + +static struct lwip_socket_multicast_mld6_pair socket_ipv6_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS]; + +static int lwip_socket_register_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr); +static void lwip_socket_unregister_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr); +static void lwip_socket_drop_registered_mld6_memberships(int s); +#endif /* LWIP_IPV6_MLD */ + +/** The global array of available sockets */ +static struct lwip_sock sockets[NUM_SOCKETS]; + +#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL +#if LWIP_TCPIP_CORE_LOCKING +/* protect the select_cb_list using core lock */ +#define LWIP_SOCKET_SELECT_DECL_PROTECT(lev) +#define LWIP_SOCKET_SELECT_PROTECT(lev) LOCK_TCPIP_CORE() +#define LWIP_SOCKET_SELECT_UNPROTECT(lev) UNLOCK_TCPIP_CORE() +#else /* LWIP_TCPIP_CORE_LOCKING */ +/* protect the select_cb_list using SYS_LIGHTWEIGHT_PROT */ +#define LWIP_SOCKET_SELECT_DECL_PROTECT(lev) SYS_ARCH_DECL_PROTECT(lev) +#define LWIP_SOCKET_SELECT_PROTECT(lev) SYS_ARCH_PROTECT(lev) +#define LWIP_SOCKET_SELECT_UNPROTECT(lev) SYS_ARCH_UNPROTECT(lev) +/** This counter is increased from lwip_select when the list is changed + and checked in select_check_waiters to see if it has changed. */ +static volatile int select_cb_ctr; +#endif /* LWIP_TCPIP_CORE_LOCKING */ +/** The global list of tasks waiting for select */ +static struct lwip_select_cb *select_cb_list; +#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */ + +#define sock_set_errno(sk, e) do { \ + const int sockerr = (e); \ + set_errno(sockerr); \ +} while (0) + +/* Forward declaration of some functions */ +#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL +static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); +#define DEFAULT_SOCKET_EVENTCB event_callback +static void select_check_waiters(int s, int has_recvevent, int has_sendevent, int has_errevent); +#else +#define DEFAULT_SOCKET_EVENTCB NULL +#endif +#if !LWIP_TCPIP_CORE_LOCKING +static void lwip_getsockopt_callback(void *arg); +static void lwip_setsockopt_callback(void *arg); +#endif +static int lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen); +static int lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen); +static int free_socket_locked(struct lwip_sock *sock, int is_tcp, struct netconn **conn, + union lwip_sock_lastdata *lastdata); +static void free_socket_free_elements(int is_tcp, struct netconn *conn, union lwip_sock_lastdata *lastdata); + +#if LWIP_IPV4 && LWIP_IPV6 +static void +sockaddr_to_ipaddr_port(const struct sockaddr *sockaddr, ip_addr_t *ipaddr, u16_t *port) +{ + if ((sockaddr->sa_family) == AF_INET6) { + SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6 *)(const void *)(sockaddr), ipaddr, *port); + ipaddr->type = IPADDR_TYPE_V6; + } else { + SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in *)(const void *)(sockaddr), ipaddr, *port); + ipaddr->type = IPADDR_TYPE_V4; + } +} +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +/** LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */ +void +lwip_socket_thread_init(void) +{ + netconn_thread_init(); +} + +/** LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */ +void +lwip_socket_thread_cleanup(void) +{ + netconn_thread_cleanup(); +} + +#if LWIP_NETCONN_FULLDUPLEX +/* Thread-safe increment of sock->fd_used, with overflow check */ +static int +sock_inc_used(struct lwip_sock *sock) +{ + int ret; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_ASSERT("sock != NULL", sock != NULL); + + SYS_ARCH_PROTECT(lev); + if (sock->fd_free_pending) { + /* prevent new usage of this socket if free is pending */ + ret = 0; + } else { + ++sock->fd_used; + ret = 1; + LWIP_ASSERT("sock->fd_used != 0", sock->fd_used != 0); + } + SYS_ARCH_UNPROTECT(lev); + return ret; +} + +/* Like sock_inc_used(), but called under SYS_ARCH_PROTECT lock. */ +static int +sock_inc_used_locked(struct lwip_sock *sock) +{ + LWIP_ASSERT("sock != NULL", sock != NULL); + + if (sock->fd_free_pending) { + LWIP_ASSERT("sock->fd_used != 0", sock->fd_used != 0); + return 0; + } + + ++sock->fd_used; + LWIP_ASSERT("sock->fd_used != 0", sock->fd_used != 0); + return 1; +} + +/* In full-duplex mode,sock->fd_used != 0 prevents a socket descriptor from being + * released (and possibly reused) when used from more than one thread + * (e.g. read-while-write or close-while-write, etc) + * This function is called at the end of functions using (try)get_socket*(). + */ +static void +done_socket(struct lwip_sock *sock) +{ + int freed = 0; + int is_tcp = 0; + struct netconn *conn = NULL; + union lwip_sock_lastdata lastdata; + SYS_ARCH_DECL_PROTECT(lev); + LWIP_ASSERT("sock != NULL", sock != NULL); + + SYS_ARCH_PROTECT(lev); + LWIP_ASSERT("sock->fd_used > 0", sock->fd_used > 0); + if (--sock->fd_used == 0) { + if (sock->fd_free_pending) { + /* free the socket */ + sock->fd_used = 1; + is_tcp = sock->fd_free_pending & LWIP_SOCK_FD_FREE_TCP; + freed = free_socket_locked(sock, is_tcp, &conn, &lastdata); + } + } + SYS_ARCH_UNPROTECT(lev); + + if (freed) { + free_socket_free_elements(is_tcp, conn, &lastdata); + } +} + +#else /* LWIP_NETCONN_FULLDUPLEX */ +#define sock_inc_used(sock) 1 +#define sock_inc_used_locked(sock) 1 +#define done_socket(sock) +#endif /* LWIP_NETCONN_FULLDUPLEX */ + +/* Translate a socket 'int' into a pointer (only fails if the index is invalid) */ +static struct lwip_sock * +tryget_socket_unconn_nouse(int fd) +{ + int s = fd - LWIP_SOCKET_OFFSET; + if ((s < 0) || (s >= NUM_SOCKETS)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("tryget_socket_unconn(%d): invalid\n", fd)); + return NULL; + } + return &sockets[s]; +} + +struct lwip_sock * +lwip_socket_dbg_get_socket(int fd) +{ + return tryget_socket_unconn_nouse(fd); +} + +/* Translate a socket 'int' into a pointer (only fails if the index is invalid) */ +static struct lwip_sock * +tryget_socket_unconn(int fd) +{ + struct lwip_sock *ret = tryget_socket_unconn_nouse(fd); + if (ret != NULL) { + if (!sock_inc_used(ret)) { + return NULL; + } + } + return ret; +} + +/* Like tryget_socket_unconn(), but called under SYS_ARCH_PROTECT lock. */ +static struct lwip_sock * +tryget_socket_unconn_locked(int fd) +{ + struct lwip_sock *ret = tryget_socket_unconn_nouse(fd); + if (ret != NULL) { + if (!sock_inc_used_locked(ret)) { + return NULL; + } + } + return ret; +} + +/** + * Same as get_socket but doesn't set errno + * + * @param fd externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +static struct lwip_sock * +tryget_socket(int fd) +{ + struct lwip_sock *sock = tryget_socket_unconn(fd); + if (sock != NULL) { + if (sock->conn) { + return sock; + } + done_socket(sock); + } + return NULL; +} + +/** + * Map a externally used socket index to the internal socket representation. + * + * @param fd externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +static struct lwip_sock * +get_socket(int fd) +{ + struct lwip_sock *sock = tryget_socket(fd); + if (!sock) { + if ((fd < LWIP_SOCKET_OFFSET) || (fd >= (LWIP_SOCKET_OFFSET + NUM_SOCKETS))) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", fd)); + } + set_errno(EBADF); + return NULL; + } + return sock; +} + +/** + * Allocate a new socket for a given netconn. + * + * @param newconn the netconn for which to allocate a socket + * @param accepted 1 if socket has been created by accept(), + * 0 if socket has been created by socket() + * @return the index of the new socket; -1 on error + */ +static int +alloc_socket(struct netconn *newconn, int accepted) +{ + int i; + SYS_ARCH_DECL_PROTECT(lev); + LWIP_UNUSED_ARG(accepted); + + /* allocate a new socket identifier */ + for (i = 0; i < NUM_SOCKETS; ++i) { + /* Protect socket array */ + SYS_ARCH_PROTECT(lev); + if (!sockets[i].conn) { +#if LWIP_NETCONN_FULLDUPLEX + if (sockets[i].fd_used) { + SYS_ARCH_UNPROTECT(lev); + continue; + } + sockets[i].fd_used = 1; + sockets[i].fd_free_pending = 0; +#endif + sockets[i].conn = newconn; + /* The socket is not yet known to anyone, so no need to protect + after having marked it as used. */ + SYS_ARCH_UNPROTECT(lev); + sockets[i].lastdata.pbuf = NULL; +#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL + LWIP_ASSERT("sockets[i].select_waiting == 0", sockets[i].select_waiting == 0); + sockets[i].rcvevent = 0; + /* TCP sendbuf is empty, but the socket is not yet writable until connected + * (unless it has been created by accept()). */ + sockets[i].sendevent = (NETCONNTYPE_GROUP(newconn->type) == NETCONN_TCP ? (accepted != 0) : 1); + sockets[i].errevent = 0; +#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */ + return i + LWIP_SOCKET_OFFSET; + } + SYS_ARCH_UNPROTECT(lev); + } + return -1; +} + +/** Free a socket (under lock) + * + * @param sock the socket to free + * @param is_tcp != 0 for TCP sockets, used to free lastdata + * @param conn the socekt's netconn is stored here, must be freed externally + * @param lastdata lastdata is stored here, must be freed externally + */ +static int +free_socket_locked(struct lwip_sock *sock, int is_tcp, struct netconn **conn, + union lwip_sock_lastdata *lastdata) +{ +#if LWIP_NETCONN_FULLDUPLEX + LWIP_ASSERT("sock->fd_used > 0", sock->fd_used > 0); + sock->fd_used--; + if (sock->fd_used > 0) { + sock->fd_free_pending = LWIP_SOCK_FD_FREE_FREE | (is_tcp ? LWIP_SOCK_FD_FREE_TCP : 0); + return 0; + } +#else /* LWIP_NETCONN_FULLDUPLEX */ + LWIP_UNUSED_ARG(is_tcp); +#endif /* LWIP_NETCONN_FULLDUPLEX */ + + *lastdata = sock->lastdata; + sock->lastdata.pbuf = NULL; + *conn = sock->conn; + sock->conn = NULL; + return 1; +} + +/** Free a socket's leftover members. + */ +static void +free_socket_free_elements(int is_tcp, struct netconn *conn, union lwip_sock_lastdata *lastdata) +{ + if (lastdata->pbuf != NULL) { + if (is_tcp) { + pbuf_free(lastdata->pbuf); + } else { + netbuf_delete(lastdata->netbuf); + } + } + if (conn != NULL) { + /* netconn_prepare_delete() has already been called, here we only free the conn */ + netconn_delete(conn); + } +} + +/** Free a socket. The socket's netconn must have been + * delete before! + * + * @param sock the socket to free + * @param is_tcp != 0 for TCP sockets, used to free lastdata + */ +static void +free_socket(struct lwip_sock *sock, int is_tcp) +{ + int freed; + struct netconn *conn; + union lwip_sock_lastdata lastdata; + SYS_ARCH_DECL_PROTECT(lev); + + /* Protect socket array */ + SYS_ARCH_PROTECT(lev); + + freed = free_socket_locked(sock, is_tcp, &conn, &lastdata); + SYS_ARCH_UNPROTECT(lev); + /* don't use 'sock' after this line, as another task might have allocated it */ + + if (freed) { + free_socket_free_elements(is_tcp, conn, &lastdata); + } +} + +/* Below this, the well-known socket functions are implemented. + * Use google.com or opengroup.org to get a good description :-) + * + * Exceptions are documented! + */ + +int +lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + struct lwip_sock *sock, *nsock; + struct netconn *newconn; + ip_addr_t naddr; + u16_t port = 0; + int newsock; + err_t err; + int recvevent; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* wait for a new connection */ + err = netconn_accept(sock->conn, &newconn); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_acept failed, err=%d\n", s, err)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + } else if (err == ERR_CLSD) { + sock_set_errno(sock, EINVAL); + } else { + sock_set_errno(sock, err_to_errno(err)); + } + done_socket(sock); + return -1; + } + LWIP_ASSERT("newconn != NULL", newconn != NULL); + + newsock = alloc_socket(newconn, 1); + if (newsock == -1) { + netconn_delete(newconn); + sock_set_errno(sock, ENFILE); + done_socket(sock); + return -1; + } + LWIP_ASSERT("invalid socket index", (newsock >= LWIP_SOCKET_OFFSET) && (newsock < NUM_SOCKETS + LWIP_SOCKET_OFFSET)); + nsock = &sockets[newsock - LWIP_SOCKET_OFFSET]; + + /* See event_callback: If data comes in right away after an accept, even + * though the server task might not have created a new socket yet. + * In that case, newconn->socket is counted down (newconn->socket--), + * so nsock->rcvevent is >= 1 here! + */ + SYS_ARCH_PROTECT(lev); + recvevent = (s16_t)(-1 - newconn->socket); + newconn->socket = newsock; + SYS_ARCH_UNPROTECT(lev); + + if (newconn->callback) { + LOCK_TCPIP_CORE(); + while (recvevent > 0) { + recvevent--; + newconn->callback(newconn, NETCONN_EVT_RCVPLUS, 0); + } + UNLOCK_TCPIP_CORE(); + } + + /* Note that POSIX only requires us to check addr is non-NULL. addrlen must + * not be NULL if addr is valid. + */ + if ((addr != NULL) && (addrlen != NULL)) { + union sockaddr_aligned tempaddr; + /* get the IP address and port of the remote host */ + err = netconn_peer(newconn, &naddr, &port); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_peer failed, err=%d\n", s, err)); + netconn_delete(newconn); + free_socket(nsock, 1); + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return -1; + } + + IPADDR_PORT_TO_SOCKADDR(&tempaddr, &naddr, port); + if (*addrlen > tempaddr.sa.sa_len) { + *addrlen = tempaddr.sa.sa_len; + } + MEMCPY(addr, &tempaddr, *addrlen); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); + ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port)); + } else { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d", s, newsock)); + } + + sock_set_errno(sock, 0); + done_socket(sock); + done_socket(nsock); + return newsock; +} + +int +lwip_bind(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + ip_addr_t local_addr; + u16_t local_port; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (!SOCK_ADDR_TYPE_MATCH(name, sock)) { + /* sockaddr does not match socket type (IPv4/IPv6) */ + sock_set_errno(sock, err_to_errno(ERR_VAL)); + done_socket(sock); + return -1; + } + + /* check size, family and alignment of 'name' */ + LWIP_ERROR("lwip_bind: invalid address", (IS_SOCK_ADDR_LEN_VALID(namelen) && + IS_SOCK_ADDR_TYPE_VALID(name) && IS_SOCK_ADDR_ALIGNED(name)), + sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;); + LWIP_UNUSED_ARG(namelen); + + SOCKADDR_TO_IPADDR_PORT(name, &local_addr, local_port); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, local_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", local_port)); + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(local_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&local_addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&local_addr), ip_2_ip6(&local_addr)); + IP_SET_TYPE_VAL(local_addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + err = netconn_bind(sock->conn, &local_addr, local_port); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + done_socket(sock); + return 0; +} + +int +lwip_close(int s) +{ + struct lwip_sock *sock; + int is_tcp = 0; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn != NULL) { + is_tcp = NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP; + } else { + LWIP_ASSERT("sock->lastdata == NULL", sock->lastdata.pbuf == NULL); + } + +#if LWIP_IGMP + /* drop all possibly joined IGMP memberships */ + lwip_socket_drop_registered_memberships(s); +#endif /* LWIP_IGMP */ +#if LWIP_IPV6_MLD + /* drop all possibly joined MLD6 memberships */ + lwip_socket_drop_registered_mld6_memberships(s); +#endif /* LWIP_IPV6_MLD */ + + err = netconn_prepare_delete(sock->conn); + if (err != ERR_OK) { + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return -1; + } + + free_socket(sock, is_tcp); + set_errno(0); + return 0; +} + +int +lwip_connect(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (!SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock)) { + /* sockaddr does not match socket type (IPv4/IPv6) */ + sock_set_errno(sock, err_to_errno(ERR_VAL)); + done_socket(sock); + return -1; + } + + LWIP_UNUSED_ARG(namelen); + if (name->sa_family == AF_UNSPEC) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); + err = netconn_disconnect(sock->conn); + } else { + ip_addr_t remote_addr; + u16_t remote_port; + + /* check size, family and alignment of 'name' */ + LWIP_ERROR("lwip_connect: invalid address", IS_SOCK_ADDR_LEN_VALID(namelen) && + IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) && IS_SOCK_ADDR_ALIGNED(name), + sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;); + + SOCKADDR_TO_IPADDR_PORT(name, &remote_addr, remote_port); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", remote_port)); + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(remote_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&remote_addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&remote_addr), ip_2_ip6(&remote_addr)); + IP_SET_TYPE_VAL(remote_addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + err = netconn_connect(sock->conn, &remote_addr, remote_port); + } + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + done_socket(sock); + return 0; +} + +/** + * Set a socket into listen mode. + * The socket may not have been used for another connection previously. + * + * @param s the socket to set to listening mode + * @param backlog (ATTENTION: needs TCP_LISTEN_BACKLOG=1) + * @return 0 on success, non-zero on failure + */ +int +lwip_listen(int s, int backlog) +{ + struct lwip_sock *sock; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* limit the "backlog" parameter to fit in an u8_t */ + backlog = LWIP_MIN(LWIP_MAX(backlog, 0), 0xff); + + err = netconn_listen_with_backlog(sock->conn, (u8_t)backlog); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + } else { + sock_set_errno(sock, err_to_errno(err)); + } + done_socket(sock); + return -1; + } + + sock_set_errno(sock, 0); + done_socket(sock); + return 0; +} + +#if LWIP_TCP +/* Helper function to loop over receiving pbufs from netconn + * until "len" bytes are received or we're otherwise done. + * Keeps sock->lastdata for peeking or partly copying. + */ +static ssize_t +lwip_recv_tcp(struct lwip_sock *sock, void *mem, size_t len, int flags) +{ + u8_t apiflags = NETCONN_NOAUTORCVD; + ssize_t recvd = 0; + ssize_t recv_left = (len <= SSIZE_MAX) ? (ssize_t)len : SSIZE_MAX; + + LWIP_ASSERT("no socket given", sock != NULL); + LWIP_ASSERT("this should be checked internally", NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP); + + if (flags & MSG_DONTWAIT) { + apiflags |= NETCONN_DONTBLOCK; + } + + do { + struct pbuf *p; + err_t err; + u16_t copylen; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: top while sock->lastdata=%p\n", (void *)sock->lastdata.pbuf)); + /* Check if there is data left from the last recv operation. */ + if (sock->lastdata.pbuf) { + p = sock->lastdata.pbuf; + } else { + /* No data was left from the previous operation, so we try to get + some from the network. */ + err = netconn_recv_tcp_pbuf_flags(sock->conn, &p, apiflags); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: netconn_recv err=%d, pbuf=%p\n", + err, (void *)p)); + + if (err != ERR_OK) { + if (recvd > 0) { + /* already received data, return that (this trusts in getting the same error from + netconn layer again next time netconn_recv is called) */ + goto lwip_recv_tcp_done; + } + /* We should really do some error checking here. */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: p == NULL, error is \"%s\"!\n", + lwip_strerr(err))); + sock_set_errno(sock, err_to_errno(err)); + if (err == ERR_CLSD) { + return 0; + } else { + return -1; + } + } + LWIP_ASSERT("p != NULL", p != NULL); + sock->lastdata.pbuf = p; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: buflen=%"U16_F" recv_left=%d off=%d\n", + p->tot_len, (int)recv_left, (int)recvd)); + + if (recv_left > p->tot_len) { + copylen = p->tot_len; + } else { + copylen = (u16_t)recv_left; + } + if (recvd + copylen < recvd) { + /* overflow */ + copylen = (u16_t)(SSIZE_MAX - recvd); + } + + /* copy the contents of the received buffer into + the supplied memory pointer mem */ + pbuf_copy_partial(p, (u8_t *)mem + recvd, copylen, 0); + + recvd += copylen; + + /* TCP combines multiple pbufs for one recv */ + LWIP_ASSERT("invalid copylen, len would underflow", recv_left >= copylen); + recv_left -= copylen; + + /* Unless we peek the incoming message... */ + if ((flags & MSG_PEEK) == 0) { + /* ... check if there is data left in the pbuf */ + LWIP_ASSERT("invalid copylen", p->tot_len >= copylen); + if (p->tot_len - copylen > 0) { + /* If so, it should be saved in the sock structure for the next recv call. + We store the pbuf but hide/free the consumed data: */ + sock->lastdata.pbuf = pbuf_free_header(p, copylen); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: lastdata now pbuf=%p\n", (void *)sock->lastdata.pbuf)); + } else { + sock->lastdata.pbuf = NULL; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recv_tcp: deleting pbuf=%p\n", (void *)p)); + pbuf_free(p); + } + } + /* once we have some data to return, only add more if we don't need to wait */ + apiflags |= NETCONN_DONTBLOCK | NETCONN_NOFIN; + /* @todo: do we need to support peeking more than one pbuf? */ + } while ((recv_left > 0) && !(flags & MSG_PEEK)); +lwip_recv_tcp_done: + if ((recvd > 0) && !(flags & MSG_PEEK)) { + /* ensure window update after copying all data */ + netconn_tcp_recvd(sock->conn, (size_t)recvd); + } + sock_set_errno(sock, 0); + return recvd; +} +#endif + +/* Convert a netbuf's address data to struct sockaddr */ +static int +lwip_sock_make_addr(struct netconn *conn, ip_addr_t *fromaddr, u16_t port, + struct sockaddr *from, socklen_t *fromlen) +{ + int truncated = 0; + union sockaddr_aligned saddr; + + LWIP_UNUSED_ARG(conn); + + LWIP_ASSERT("fromaddr != NULL", fromaddr != NULL); + LWIP_ASSERT("from != NULL", from != NULL); + LWIP_ASSERT("fromlen != NULL", fromlen != NULL); + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ + if (NETCONNTYPE_ISIPV6(netconn_type(conn)) && IP_IS_V4(fromaddr)) { + ip4_2_ipv4_mapped_ipv6(ip_2_ip6(fromaddr), ip_2_ip4(fromaddr)); + IP_SET_TYPE(fromaddr, IPADDR_TYPE_V6); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + IPADDR_PORT_TO_SOCKADDR(&saddr, fromaddr, port); + if (*fromlen < saddr.sa.sa_len) { + truncated = 1; + } else if (*fromlen > saddr.sa.sa_len) { + *fromlen = saddr.sa.sa_len; + } + MEMCPY(from, &saddr, *fromlen); + return truncated; +} + +#if LWIP_TCP +/* Helper function to get a tcp socket's remote address info */ +static int +lwip_recv_tcp_from(struct lwip_sock *sock, struct sockaddr *from, socklen_t *fromlen, const char *dbg_fn, int dbg_s, ssize_t dbg_ret) +{ + if (sock == NULL) { + return 0; + } + LWIP_UNUSED_ARG(dbg_fn); + LWIP_UNUSED_ARG(dbg_s); + LWIP_UNUSED_ARG(dbg_ret); + +#if !SOCKETS_DEBUG + if (from && fromlen) +#endif /* !SOCKETS_DEBUG */ + { + /* get remote addr/port from tcp_pcb */ + u16_t port; + ip_addr_t tmpaddr; + netconn_getaddr(sock->conn, &tmpaddr, &port, 0); + LWIP_DEBUGF(SOCKETS_DEBUG, ("%s(%d): addr=", dbg_fn, dbg_s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, tmpaddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, (int)dbg_ret)); + if (from && fromlen) { + return lwip_sock_make_addr(sock->conn, &tmpaddr, port, from, fromlen); + } + } + return 0; +} +#endif + +/* Helper function to receive a netbuf from a udp or raw netconn. + * Keeps sock->lastdata for peeking. + */ +static err_t +lwip_recvfrom_udp_raw(struct lwip_sock *sock, int flags, struct msghdr *msg, u16_t *datagram_len, int dbg_s) +{ + struct netbuf *buf; + u8_t apiflags; + err_t err; + u16_t buflen, copylen, copied; + int i; + + LWIP_UNUSED_ARG(dbg_s); + LWIP_ERROR("lwip_recvfrom_udp_raw: invalid arguments", (msg->msg_iov != NULL) || (msg->msg_iovlen <= 0), return ERR_ARG;); + + if (flags & MSG_DONTWAIT) { + apiflags = NETCONN_DONTBLOCK; + } else { + apiflags = 0; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw[UDP/RAW]: top sock->lastdata=%p\n", (void *)sock->lastdata.netbuf)); + /* Check if there is data left from the last recv operation. */ + buf = sock->lastdata.netbuf; + if (buf == NULL) { + /* No data was left from the previous operation, so we try to get + some from the network. */ + err = netconn_recv_udp_raw_netbuf_flags(sock->conn, &buf, apiflags); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw[UDP/RAW]: netconn_recv err=%d, netbuf=%p\n", + err, (void *)buf)); + + if (err != ERR_OK) { + return err; + } + LWIP_ASSERT("buf != NULL", buf != NULL); + sock->lastdata.netbuf = buf; + } + buflen = buf->p->tot_len; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw: buflen=%"U16_F"\n", buflen)); + + copied = 0; + /* copy the pbuf payload into the iovs */ + for (i = 0; (i < msg->msg_iovlen) && (copied < buflen); i++) { + u16_t len_left = (u16_t)(buflen - copied); + if (msg->msg_iov[i].iov_len > len_left) { + copylen = len_left; + } else { + copylen = (u16_t)msg->msg_iov[i].iov_len; + } + + /* copy the contents of the received buffer into + the supplied memory buffer */ + pbuf_copy_partial(buf->p, (u8_t *)msg->msg_iov[i].iov_base, copylen, copied); + copied = (u16_t)(copied + copylen); + } + + /* Check to see from where the data was.*/ +#if !SOCKETS_DEBUG + if (msg->msg_name && msg->msg_namelen) +#endif /* !SOCKETS_DEBUG */ + { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom_udp_raw(%d): addr=", dbg_s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, *netbuf_fromaddr(buf)); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", netbuf_fromport(buf), copied)); + if (msg->msg_name && msg->msg_namelen) { + lwip_sock_make_addr(sock->conn, netbuf_fromaddr(buf), netbuf_fromport(buf), + (struct sockaddr *)msg->msg_name, &msg->msg_namelen); + } + } + + /* Initialize flag output */ + msg->msg_flags = 0; + + if (msg->msg_control) { + u8_t wrote_msg = 0; +#if LWIP_NETBUF_RECVINFO + /* Check if packet info was recorded */ + if (buf->flags & NETBUF_FLAG_DESTADDR) { + if (IP_IS_V4(&buf->toaddr)) { +#if LWIP_IPV4 + if (msg->msg_controllen >= CMSG_SPACE(sizeof(struct in_pktinfo))) { + struct cmsghdr *chdr = CMSG_FIRSTHDR(msg); /* This will always return a header!! */ + struct in_pktinfo *pkti = (struct in_pktinfo *)CMSG_DATA(chdr); + chdr->cmsg_level = IPPROTO_IP; + chdr->cmsg_type = IP_PKTINFO; + chdr->cmsg_len = CMSG_LEN(sizeof(struct in_pktinfo)); + pkti->ipi_ifindex = buf->p->if_idx; + inet_addr_from_ip4addr(&pkti->ipi_addr, ip_2_ip4(netbuf_destaddr(buf))); + msg->msg_controllen = CMSG_SPACE(sizeof(struct in_pktinfo)); + wrote_msg = 1; + } else { + msg->msg_flags |= MSG_CTRUNC; + } +#endif /* LWIP_IPV4 */ + } + } +#endif /* LWIP_NETBUF_RECVINFO */ + + if (!wrote_msg) { + msg->msg_controllen = 0; + } + } + + /* If we don't peek the incoming message: zero lastdata pointer and free the netbuf */ + if ((flags & MSG_PEEK) == 0) { + sock->lastdata.netbuf = NULL; + netbuf_delete(buf); + } + if (datagram_len) { + *datagram_len = buflen; + } + return ERR_OK; +} + +ssize_t +lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen) +{ + struct lwip_sock *sock; + ssize_t ret; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags)); + sock = get_socket(s); + if (!sock) { + return -1; + } +#if LWIP_TCP + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + ret = lwip_recv_tcp(sock, mem, len, flags); + lwip_recv_tcp_from(sock, from, fromlen, "lwip_recvfrom", s, ret); + done_socket(sock); + return ret; + } else +#endif + { + u16_t datagram_len = 0; + struct iovec vec; + struct msghdr msg; + err_t err; + vec.iov_base = mem; + vec.iov_len = len; + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = 0; + msg.msg_iov = &vec; + msg.msg_iovlen = 1; + msg.msg_name = from; + msg.msg_namelen = (fromlen ? *fromlen : 0); + err = lwip_recvfrom_udp_raw(sock, flags, &msg, &datagram_len, s); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom[UDP/RAW](%d): buf == NULL, error is \"%s\"!\n", + s, lwip_strerr(err))); + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return -1; + } + ret = (ssize_t)LWIP_MIN(LWIP_MIN(len, datagram_len), SSIZE_MAX); + if (fromlen) { + *fromlen = msg.msg_namelen; + } + } + + sock_set_errno(sock, 0); + done_socket(sock); + return ret; +} + +ssize_t +lwip_read(int s, void *mem, size_t len) +{ + return lwip_recvfrom(s, mem, len, 0, NULL, NULL); +} + +ssize_t +lwip_readv(int s, const struct iovec *iov, int iovcnt) +{ + struct msghdr msg; + + msg.msg_name = NULL; + msg.msg_namelen = 0; + /* Hack: we have to cast via number to cast from 'const' pointer to non-const. + Blame the opengroup standard for this inconsistency. */ + msg.msg_iov = LWIP_CONST_CAST(struct iovec *, iov); + msg.msg_iovlen = iovcnt; + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = 0; + return lwip_recvmsg(s, &msg, 0); +} + +ssize_t +lwip_recv(int s, void *mem, size_t len, int flags) +{ + return lwip_recvfrom(s, mem, len, flags, NULL, NULL); +} + +ssize_t +lwip_recvmsg(int s, struct msghdr *message, int flags) +{ + struct lwip_sock *sock; + int i; + ssize_t buflen; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvmsg(%d, message=%p, flags=0x%x)\n", s, (void *)message, flags)); + LWIP_ERROR("lwip_recvmsg: invalid message pointer", message != NULL, return ERR_ARG;); + LWIP_ERROR("lwip_recvmsg: unsupported flags", (flags & ~(MSG_PEEK|MSG_DONTWAIT)) == 0, + set_errno(EOPNOTSUPP); return -1;); + + if ((message->msg_iovlen <= 0) || (message->msg_iovlen > IOV_MAX)) { + set_errno(EMSGSIZE); + return -1; + } + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* check for valid vectors */ + buflen = 0; + for (i = 0; i < message->msg_iovlen; i++) { + if ((message->msg_iov[i].iov_base == NULL) || ((ssize_t)message->msg_iov[i].iov_len <= 0) || + ((size_t)(ssize_t)message->msg_iov[i].iov_len != message->msg_iov[i].iov_len) || + ((ssize_t)(buflen + (ssize_t)message->msg_iov[i].iov_len) <= 0)) { + sock_set_errno(sock, err_to_errno(ERR_VAL)); + done_socket(sock); + return -1; + } + buflen = (ssize_t)(buflen + (ssize_t)message->msg_iov[i].iov_len); + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCP + int recv_flags = flags; + message->msg_flags = 0; + /* recv the data */ + buflen = 0; + for (i = 0; i < message->msg_iovlen; i++) { + /* try to receive into this vector's buffer */ + ssize_t recvd_local = lwip_recv_tcp(sock, message->msg_iov[i].iov_base, message->msg_iov[i].iov_len, recv_flags); + if (recvd_local > 0) { + /* sum up received bytes */ + buflen += recvd_local; + } + if ((recvd_local < 0) || (recvd_local < (int)message->msg_iov[i].iov_len) || + (flags & MSG_PEEK)) { + /* returned prematurely (or peeking, which might actually be limitated to the first iov) */ + if (buflen <= 0) { + /* nothing received at all, propagate the error */ + buflen = recvd_local; + } + break; + } + /* pass MSG_DONTWAIT to lwip_recv_tcp() to prevent waiting for more data */ + recv_flags |= MSG_DONTWAIT; + } + if (buflen > 0) { + /* reset socket error since we have received something */ + sock_set_errno(sock, 0); + } + /* " If the socket is connected, the msg_name and msg_namelen members shall be ignored." */ + done_socket(sock); + return buflen; +#else /* LWIP_TCP */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + done_socket(sock); + return -1; +#endif /* LWIP_TCP */ + } + /* else, UDP and RAW NETCONNs */ +#if LWIP_UDP || LWIP_RAW + { + u16_t datagram_len = 0; + err_t err; + err = lwip_recvfrom_udp_raw(sock, flags, message, &datagram_len, s); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvmsg[UDP/RAW](%d): buf == NULL, error is \"%s\"!\n", + s, lwip_strerr(err))); + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return -1; + } + if (datagram_len > buflen) { + message->msg_flags |= MSG_TRUNC; + } + + sock_set_errno(sock, 0); + done_socket(sock); + return (int)datagram_len; + } +#else /* LWIP_UDP || LWIP_RAW */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + done_socket(sock); + return -1; +#endif /* LWIP_UDP || LWIP_RAW */ +} + +ssize_t +lwip_send(int s, const void *data, size_t size, int flags) +{ + struct lwip_sock *sock; + err_t err; + u8_t write_flags; + size_t written; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n", + s, data, size, flags)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { +#if (LWIP_UDP || LWIP_RAW) + done_socket(sock); + return lwip_sendto(s, data, size, flags, NULL, 0); +#else /* (LWIP_UDP || LWIP_RAW) */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + done_socket(sock); + return -1; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + + write_flags = (u8_t)(NETCONN_COPY | + ((flags & MSG_MORE) ? NETCONN_MORE : 0) | + ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0)); + written = 0; + err = netconn_write_partly(sock->conn, data, size, write_flags, &written); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d written=%"SZT_F"\n", s, err, written)); + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + /* casting 'written' to ssize_t is OK here since the netconn API limits it to SSIZE_MAX */ + return (err == ERR_OK ? (ssize_t)written : -1); +} + +ssize_t +lwip_sendmsg(int s, const struct msghdr *msg, int flags) +{ + struct lwip_sock *sock; +#if LWIP_TCP + u8_t write_flags; + size_t written; +#endif + err_t err = ERR_OK; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + LWIP_ERROR("lwip_sendmsg: invalid msghdr", msg != NULL, + sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;); + LWIP_ERROR("lwip_sendmsg: invalid msghdr iov", msg->msg_iov != NULL, + sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;); + LWIP_ERROR("lwip_sendmsg: maximum iovs exceeded", (msg->msg_iovlen > 0) && (msg->msg_iovlen <= IOV_MAX), + sock_set_errno(sock, EMSGSIZE); done_socket(sock); return -1;); + LWIP_ERROR("lwip_sendmsg: unsupported flags", (flags & ~(MSG_DONTWAIT | MSG_MORE)) == 0, + sock_set_errno(sock, EOPNOTSUPP); done_socket(sock); return -1;); + + LWIP_UNUSED_ARG(msg->msg_control); + LWIP_UNUSED_ARG(msg->msg_controllen); + LWIP_UNUSED_ARG(msg->msg_flags); + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCP + write_flags = (u8_t)(NETCONN_COPY | + ((flags & MSG_MORE) ? NETCONN_MORE : 0) | + ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0)); + + written = 0; + err = netconn_write_vectors_partly(sock->conn, (struct netvector *)msg->msg_iov, (u16_t)msg->msg_iovlen, write_flags, &written); + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + /* casting 'written' to ssize_t is OK here since the netconn API limits it to SSIZE_MAX */ + return (err == ERR_OK ? (ssize_t)written : -1); +#else /* LWIP_TCP */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + done_socket(sock); + return -1; +#endif /* LWIP_TCP */ + } + /* else, UDP and RAW NETCONNs */ +#if LWIP_UDP || LWIP_RAW + { + struct netbuf chain_buf; + int i; + ssize_t size = 0; + + LWIP_UNUSED_ARG(flags); + LWIP_ERROR("lwip_sendmsg: invalid msghdr name", (((msg->msg_name == NULL) && (msg->msg_namelen == 0)) || + IS_SOCK_ADDR_LEN_VALID(msg->msg_namelen)), + sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;); + + /* initialize chain buffer with destination */ + memset(&chain_buf, 0, sizeof(struct netbuf)); + if (msg->msg_name) { + u16_t remote_port; + SOCKADDR_TO_IPADDR_PORT((const struct sockaddr *)msg->msg_name, &chain_buf.addr, remote_port); + netbuf_fromport(&chain_buf) = remote_port; + } +#if LWIP_NETIF_TX_SINGLE_PBUF + for (i = 0; i < msg->msg_iovlen; i++) { + size += msg->msg_iov[i].iov_len; + if ((msg->msg_iov[i].iov_len > INT_MAX) || (size < (int)msg->msg_iov[i].iov_len)) { + /* overflow */ + goto sendmsg_emsgsize; + } + } + if (size > 0xFFFF) { + /* overflow */ + goto sendmsg_emsgsize; + } + /* Allocate a new netbuf and copy the data into it. */ + if (netbuf_alloc(&chain_buf, (u16_t)size) == NULL) { + err = ERR_MEM; + } else { + /* flatten the IO vectors */ + size_t offset = 0; + for (i = 0; i < msg->msg_iovlen; i++) { + MEMCPY(&((u8_t *)chain_buf.p->payload)[offset], msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len); + offset += msg->msg_iov[i].iov_len; + } +#if LWIP_CHECKSUM_ON_COPY + { + /* This can be improved by using LWIP_CHKSUM_COPY() and aggregating the checksum for each IO vector */ + u16_t chksum = ~inet_chksum_pbuf(chain_buf.p); + netbuf_set_chksum(&chain_buf, chksum); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + err = ERR_OK; + } +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + /* create a chained netbuf from the IO vectors. NOTE: we assemble a pbuf chain + manually to avoid having to allocate, chain, and delete a netbuf for each iov */ + for (i = 0; i < msg->msg_iovlen; i++) { + struct pbuf *p; + if (msg->msg_iov[i].iov_len > 0xFFFF) { + /* overflow */ + goto sendmsg_emsgsize; + } + p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); + if (p == NULL) { + err = ERR_MEM; /* let netbuf_delete() cleanup chain_buf */ + break; + } + p->payload = msg->msg_iov[i].iov_base; + p->len = p->tot_len = (u16_t)msg->msg_iov[i].iov_len; + /* netbuf empty, add new pbuf */ + if (chain_buf.p == NULL) { + chain_buf.p = chain_buf.ptr = p; + /* add pbuf to existing pbuf chain */ + } else { + if (chain_buf.p->tot_len + p->len > 0xffff) { + /* overflow */ + pbuf_free(p); + goto sendmsg_emsgsize; + } + pbuf_cat(chain_buf.p, p); + } + } + /* save size of total chain */ + if (err == ERR_OK) { + size = netbuf_len(&chain_buf); + } +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + if (err == ERR_OK) { +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(chain_buf.addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&chain_buf.addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&chain_buf.addr), ip_2_ip6(&chain_buf.addr)); + IP_SET_TYPE_VAL(chain_buf.addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + /* send the data */ + err = netconn_send(sock->conn, &chain_buf); + } + + /* deallocated the buffer */ + netbuf_free(&chain_buf); + + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return (err == ERR_OK ? size : -1); +sendmsg_emsgsize: + sock_set_errno(sock, EMSGSIZE); + netbuf_free(&chain_buf); + done_socket(sock); + return -1; + } +#else /* LWIP_UDP || LWIP_RAW */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + done_socket(sock); + return -1; +#endif /* LWIP_UDP || LWIP_RAW */ +} + +ssize_t +lwip_sendto(int s, const void *data, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen) +{ + struct lwip_sock *sock; + err_t err; + u16_t short_size; + u16_t remote_port; + struct netbuf buf; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCP + done_socket(sock); + return lwip_send(s, data, size, flags); +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(flags); + sock_set_errno(sock, err_to_errno(ERR_ARG)); + done_socket(sock); + return -1; +#endif /* LWIP_TCP */ + } + + if (size > LWIP_MIN(0xFFFF, SSIZE_MAX)) { + /* cannot fit into one datagram (at least for us) */ + sock_set_errno(sock, EMSGSIZE); + done_socket(sock); + return -1; + } + short_size = (u16_t)size; + LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) || + (IS_SOCK_ADDR_LEN_VALID(tolen) && + ((to != NULL) && (IS_SOCK_ADDR_TYPE_VALID(to) && IS_SOCK_ADDR_ALIGNED(to))))), + sock_set_errno(sock, err_to_errno(ERR_ARG)); done_socket(sock); return -1;); + LWIP_UNUSED_ARG(tolen); + + /* initialize a buffer */ + buf.p = buf.ptr = NULL; +#if LWIP_CHECKSUM_ON_COPY + buf.flags = 0; +#endif /* LWIP_CHECKSUM_ON_COPY */ + if (to) { + SOCKADDR_TO_IPADDR_PORT(to, &buf.addr, remote_port); + } else { + remote_port = 0; + ip_addr_set_any(NETCONNTYPE_ISIPV6(netconn_type(sock->conn)), &buf.addr); + } + netbuf_fromport(&buf) = remote_port; + + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%"U16_F", flags=0x%x to=", + s, data, short_size, flags)); + ip_addr_debug_print_val(SOCKETS_DEBUG, buf.addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port)); + + /* make the buffer point to the data that should be sent */ +#if LWIP_NETIF_TX_SINGLE_PBUF + /* Allocate a new netbuf and copy the data into it. */ + if (netbuf_alloc(&buf, short_size) == NULL) { + err = ERR_MEM; + } else { +#if LWIP_CHECKSUM_ON_COPY + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_RAW) { + u16_t chksum = LWIP_CHKSUM_COPY(buf.p->payload, data, short_size); + netbuf_set_chksum(&buf, chksum); + } else +#endif /* LWIP_CHECKSUM_ON_COPY */ + { + MEMCPY(buf.p->payload, data, short_size); + } + err = ERR_OK; + } +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + err = netbuf_ref(&buf, data, short_size); +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + if (err == ERR_OK) { +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(buf.addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&buf.addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&buf.addr), ip_2_ip6(&buf.addr)); + IP_SET_TYPE_VAL(buf.addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + /* send the data */ + err = netconn_send(sock->conn, &buf); + } + + /* deallocated the buffer */ + netbuf_free(&buf); + + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return (err == ERR_OK ? short_size : -1); +} + +int +lwip_socket(int domain, int type, int protocol) +{ + struct netconn *conn; + int i; + + LWIP_UNUSED_ARG(domain); /* @todo: check this */ + + /* create a netconn */ + switch (type) { + case SOCK_RAW: + conn = netconn_new_with_proto_and_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_RAW), + (u8_t)protocol, DEFAULT_SOCKET_EVENTCB); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_DGRAM: + conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, + ((protocol == IPPROTO_UDPLITE) ? NETCONN_UDPLITE : NETCONN_UDP)), + DEFAULT_SOCKET_EVENTCB); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); +#if LWIP_NETBUF_RECVINFO + if (conn) { + /* netconn layer enables pktinfo by default, sockets default to off */ + conn->flags &= ~NETCONN_FLAG_PKTINFO; + } +#endif /* LWIP_NETBUF_RECVINFO */ + break; + case SOCK_STREAM: + conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_TCP), DEFAULT_SOCKET_EVENTCB); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", + domain, type, protocol)); + set_errno(EINVAL); + return -1; + } + + if (!conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); + set_errno(ENOBUFS); + return -1; + } + + i = alloc_socket(conn, 0); + + if (i == -1) { + netconn_delete(conn); + set_errno(ENFILE); + return -1; + } + conn->socket = i; + done_socket(&sockets[i - LWIP_SOCKET_OFFSET]); + LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); + set_errno(0); + return i; +} + +ssize_t +lwip_write(int s, const void *data, size_t size) +{ + return lwip_send(s, data, size, 0); +} + +ssize_t +lwip_writev(int s, const struct iovec *iov, int iovcnt) +{ + struct msghdr msg; + + msg.msg_name = NULL; + msg.msg_namelen = 0; + /* Hack: we have to cast via number to cast from 'const' pointer to non-const. + Blame the opengroup standard for this inconsistency. */ + msg.msg_iov = LWIP_CONST_CAST(struct iovec *, iov); + msg.msg_iovlen = iovcnt; + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = 0; + return lwip_sendmsg(s, &msg, 0); +} + +#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL +/* Add select_cb to select_cb_list. */ +static void +lwip_link_select_cb(struct lwip_select_cb *select_cb) +{ + LWIP_SOCKET_SELECT_DECL_PROTECT(lev); + + /* Protect the select_cb_list */ + LWIP_SOCKET_SELECT_PROTECT(lev); + + /* Put this select_cb on top of list */ + select_cb->next = select_cb_list; + if (select_cb_list != NULL) { + select_cb_list->prev = select_cb; + } + select_cb_list = select_cb; +#if !LWIP_TCPIP_CORE_LOCKING + /* Increasing this counter tells select_check_waiters that the list has changed. */ + select_cb_ctr++; +#endif + + /* Now we can safely unprotect */ + LWIP_SOCKET_SELECT_UNPROTECT(lev); +} + +/* Remove select_cb from select_cb_list. */ +static void +lwip_unlink_select_cb(struct lwip_select_cb *select_cb) +{ + LWIP_SOCKET_SELECT_DECL_PROTECT(lev); + + /* Take us off the list */ + LWIP_SOCKET_SELECT_PROTECT(lev); + if (select_cb->next != NULL) { + select_cb->next->prev = select_cb->prev; + } + if (select_cb_list == select_cb) { + LWIP_ASSERT("select_cb->prev == NULL", select_cb->prev == NULL); + select_cb_list = select_cb->next; + } else { + LWIP_ASSERT("select_cb->prev != NULL", select_cb->prev != NULL); + select_cb->prev->next = select_cb->next; + } +#if !LWIP_TCPIP_CORE_LOCKING + /* Increasing this counter tells select_check_waiters that the list has changed. */ + select_cb_ctr++; +#endif + LWIP_SOCKET_SELECT_UNPROTECT(lev); +} +#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */ + +#if LWIP_SOCKET_SELECT +/** + * Go through the readset and writeset lists and see which socket of the sockets + * set in the sets has events. On return, readset, writeset and exceptset have + * the sockets enabled that had events. + * + * @param maxfdp1 the highest socket index in the sets + * @param readset_in set of sockets to check for read events + * @param writeset_in set of sockets to check for write events + * @param exceptset_in set of sockets to check for error events + * @param readset_out set of sockets that had read events + * @param writeset_out set of sockets that had write events + * @param exceptset_out set os sockets that had error events + * @return number of sockets that had events (read/write/exception) (>= 0) + */ +static int +lwip_selscan(int maxfdp1, fd_set *readset_in, fd_set *writeset_in, fd_set *exceptset_in, + fd_set *readset_out, fd_set *writeset_out, fd_set *exceptset_out) +{ + int i, nready = 0; + fd_set lreadset, lwriteset, lexceptset; + struct lwip_sock *sock; + SYS_ARCH_DECL_PROTECT(lev); + + FD_ZERO(&lreadset); + FD_ZERO(&lwriteset); + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { + /* if this FD is not in the set, continue */ + if (!(readset_in && FD_ISSET(i, readset_in)) && + !(writeset_in && FD_ISSET(i, writeset_in)) && + !(exceptset_in && FD_ISSET(i, exceptset_in))) { + continue; + } + /* First get the socket's status (protected)... */ + SYS_ARCH_PROTECT(lev); + sock = tryget_socket_unconn_locked(i); + if (sock != NULL) { + void *lastdata = sock->lastdata.pbuf; + s16_t rcvevent = sock->rcvevent; + u16_t sendevent = sock->sendevent; + u16_t errevent = sock->errevent; + SYS_ARCH_UNPROTECT(lev); + + /* ... then examine it: */ + /* See if netconn of this socket is ready for read */ + if (readset_in && FD_ISSET(i, readset_in) && ((lastdata != NULL) || (rcvevent > 0))) { + FD_SET(i, &lreadset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); + nready++; + } + /* See if netconn of this socket is ready for write */ + if (writeset_in && FD_ISSET(i, writeset_in) && (sendevent != 0)) { + FD_SET(i, &lwriteset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); + nready++; + } + /* See if netconn of this socket had an error */ + if (exceptset_in && FD_ISSET(i, exceptset_in) && (errevent != 0)) { + FD_SET(i, &lexceptset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for exception\n", i)); + nready++; + } + done_socket(sock); + } else { + SYS_ARCH_UNPROTECT(lev); + /* no a valid open socket */ + return -1; + } + } + /* copy local sets to the ones provided as arguments */ + *readset_out = lreadset; + *writeset_out = lwriteset; + *exceptset_out = lexceptset; + + LWIP_ASSERT("nready >= 0", nready >= 0); + return nready; +} + +#if LWIP_NETCONN_FULLDUPLEX +/* Mark all of the set sockets in one of the three fdsets passed to select as used. + * All sockets are marked (and later unmarked), whether they are open or not. + * This is OK as lwip_selscan aborts select when non-open sockets are found. + */ +static void +lwip_select_inc_sockets_used_set(int maxfdp, fd_set *fdset, fd_set *used_sockets) +{ + SYS_ARCH_DECL_PROTECT(lev); + if (fdset) { + int i; + for (i = LWIP_SOCKET_OFFSET; i < maxfdp; i++) { + /* if this FD is in the set, lock it (unless already done) */ + if (FD_ISSET(i, fdset) && !FD_ISSET(i, used_sockets)) { + struct lwip_sock *sock; + SYS_ARCH_PROTECT(lev); + sock = tryget_socket_unconn_locked(i); + if (sock != NULL) { + /* leave the socket used until released by lwip_select_dec_sockets_used */ + FD_SET(i, used_sockets); + } + SYS_ARCH_UNPROTECT(lev); + } + } + } +} + +/* Mark all sockets passed to select as used to prevent them from being freed + * from other threads while select is running. + * Marked sockets are added to 'used_sockets' to mark them only once an be able + * to unmark them correctly. + */ +static void +lwip_select_inc_sockets_used(int maxfdp, fd_set *fdset1, fd_set *fdset2, fd_set *fdset3, fd_set *used_sockets) +{ + FD_ZERO(used_sockets); + lwip_select_inc_sockets_used_set(maxfdp, fdset1, used_sockets); + lwip_select_inc_sockets_used_set(maxfdp, fdset2, used_sockets); + lwip_select_inc_sockets_used_set(maxfdp, fdset3, used_sockets); +} + +/* Let go all sockets that were marked as used when starting select */ +static void +lwip_select_dec_sockets_used(int maxfdp, fd_set *used_sockets) +{ + int i; + for (i = LWIP_SOCKET_OFFSET; i < maxfdp; i++) { + /* if this FD is not in the set, continue */ + if (FD_ISSET(i, used_sockets)) { + struct lwip_sock *sock = tryget_socket_unconn_nouse(i); + LWIP_ASSERT("socket gone at the end of select", sock != NULL); + if (sock != NULL) { + done_socket(sock); + } + } + } +} +#else /* LWIP_NETCONN_FULLDUPLEX */ +#define lwip_select_inc_sockets_used(maxfdp1, readset, writeset, exceptset, used_sockets) +#define lwip_select_dec_sockets_used(maxfdp1, used_sockets) +#endif /* LWIP_NETCONN_FULLDUPLEX */ + +int +lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout) +{ + u32_t waitres = 0; + int nready; + fd_set lreadset, lwriteset, lexceptset; + u32_t msectimeout; + int i; + int maxfdp2; +#if LWIP_NETCONN_SEM_PER_THREAD + int waited = 0; +#endif +#if LWIP_NETCONN_FULLDUPLEX + fd_set used_sockets; +#endif + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%"S32_F" tvusec=%"S32_F")\n", + maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, + timeout ? (s32_t)timeout->tv_sec : (s32_t) - 1, + timeout ? (s32_t)timeout->tv_usec : (s32_t) - 1)); + + if ((maxfdp1 < 0) || (maxfdp1 > LWIP_SELECT_MAXNFDS)) { + set_errno(EINVAL); + return -1; + } + + lwip_select_inc_sockets_used(maxfdp1, readset, writeset, exceptset, &used_sockets); + + /* Go through each socket in each list to count number of sockets which + currently match */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + + if (nready < 0) { + /* one of the sockets in one of the fd_sets was invalid */ + set_errno(EBADF); + lwip_select_dec_sockets_used(maxfdp1, &used_sockets); + return -1; + } else if (nready > 0) { + /* one or more sockets are set, no need to wait */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); + } else { + /* If we don't have any current events, then suspend if we are supposed to */ + if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + } else { + /* None ready: add our semaphore to list: + We don't actually need any dynamic memory. Our entry on the + list is only valid while we are in this function, so it's ok + to use local variables (unless we're running in MPU compatible + mode). */ + API_SELECT_CB_VAR_DECLARE(select_cb); + API_SELECT_CB_VAR_ALLOC(select_cb, set_errno(ENOMEM); lwip_select_dec_sockets_used(maxfdp1, &used_sockets); return -1); + memset(&API_SELECT_CB_VAR_REF(select_cb), 0, sizeof(struct lwip_select_cb)); + + API_SELECT_CB_VAR_REF(select_cb).readset = readset; + API_SELECT_CB_VAR_REF(select_cb).writeset = writeset; + API_SELECT_CB_VAR_REF(select_cb).exceptset = exceptset; +#if LWIP_NETCONN_SEM_PER_THREAD + API_SELECT_CB_VAR_REF(select_cb).sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + if (sys_sem_new(&API_SELECT_CB_VAR_REF(select_cb).sem, 0) != ERR_OK) { + /* failed to create semaphore */ + set_errno(ENOMEM); + lwip_select_dec_sockets_used(maxfdp1, &used_sockets); + API_SELECT_CB_VAR_FREE(select_cb); + return -1; + } +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + lwip_link_select_cb(&API_SELECT_CB_VAR_REF(select_cb)); + + /* Increase select_waiting for each socket we are interested in */ + maxfdp2 = maxfdp1; + for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock; + SYS_ARCH_PROTECT(lev); + sock = tryget_socket_unconn_locked(i); + if (sock != NULL) { + sock->select_waiting++; + if (sock->select_waiting == 0) { + /* overflow - too many threads waiting */ + sock->select_waiting--; + nready = -1; + maxfdp2 = i; + SYS_ARCH_UNPROTECT(lev); + done_socket(sock); + set_errno(EBUSY); + break; + } + SYS_ARCH_UNPROTECT(lev); + done_socket(sock); + } else { + /* Not a valid socket */ + nready = -1; + maxfdp2 = i; + SYS_ARCH_UNPROTECT(lev); + set_errno(EBADF); + break; + } + } + } + + if (nready >= 0) { + /* Call lwip_selscan again: there could have been events between + the last scan (without us on the list) and putting us on the list! */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + if (!nready) { + /* Still none ready, just wait to be woken */ + if (timeout == 0) { + /* Wait forever */ + msectimeout = 0; + } else { + long msecs_long = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500) / 1000)); + if (msecs_long <= 0) { + /* Wait 1ms at least (0 means wait forever) */ + msectimeout = 1; + } else { + msectimeout = (u32_t)msecs_long; + } + } + + waitres = sys_arch_sem_wait(SELECT_SEM_PTR(API_SELECT_CB_VAR_REF(select_cb).sem), msectimeout); +#if LWIP_NETCONN_SEM_PER_THREAD + waited = 1; +#endif + } + } + + /* Decrease select_waiting for each socket we are interested in */ + for (i = LWIP_SOCKET_OFFSET; i < maxfdp2; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock; + SYS_ARCH_PROTECT(lev); + sock = tryget_socket_unconn_locked(i); + if (sock != NULL) { + /* for now, handle select_waiting==0... */ + LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); + if (sock->select_waiting > 0) { + sock->select_waiting--; + } + SYS_ARCH_UNPROTECT(lev); + done_socket(sock); + } else { + SYS_ARCH_UNPROTECT(lev); + /* Not a valid socket */ + nready = -1; + set_errno(EBADF); + } + } + } + + lwip_unlink_select_cb(&API_SELECT_CB_VAR_REF(select_cb)); + +#if LWIP_NETCONN_SEM_PER_THREAD + if (API_SELECT_CB_VAR_REF(select_cb).sem_signalled && (!waited || (waitres == SYS_ARCH_TIMEOUT))) { + /* don't leave the thread-local semaphore signalled */ + sys_arch_sem_wait(API_SELECT_CB_VAR_REF(select_cb).sem, 1); + } +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + sys_sem_free(&API_SELECT_CB_VAR_REF(select_cb).sem); +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + API_SELECT_CB_VAR_FREE(select_cb); + + if (nready < 0) { + /* This happens when a socket got closed while waiting */ + lwip_select_dec_sockets_used(maxfdp1, &used_sockets); + return -1; + } + + if (waitres == SYS_ARCH_TIMEOUT) { + /* Timeout */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + } else { + /* See what's set now after waiting */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); + } + } + } + + lwip_select_dec_sockets_used(maxfdp1, &used_sockets); + set_errno(0); + if (readset) { + *readset = lreadset; + } + if (writeset) { + *writeset = lwriteset; + } + if (exceptset) { + *exceptset = lexceptset; + } + return nready; +} +#endif /* LWIP_SOCKET_SELECT */ + +#if LWIP_SOCKET_POLL +/** Options for the lwip_pollscan function. */ +enum lwip_pollscan_opts +{ + /** Clear revents in each struct pollfd. */ + LWIP_POLLSCAN_CLEAR = 1, + + /** Increment select_waiting in each struct lwip_sock. */ + LWIP_POLLSCAN_INC_WAIT = 2, + + /** Decrement select_waiting in each struct lwip_sock. */ + LWIP_POLLSCAN_DEC_WAIT = 4 +}; + +/** + * Update revents in each struct pollfd. + * Optionally update select_waiting in struct lwip_sock. + * + * @param fds array of structures to update + * @param nfds number of structures in fds + * @param opts what to update and how + * @return number of structures that have revents != 0 + */ +static int +lwip_pollscan(struct pollfd *fds, nfds_t nfds, enum lwip_pollscan_opts opts) +{ + int nready = 0; + nfds_t fdi; + struct lwip_sock *sock; + SYS_ARCH_DECL_PROTECT(lev); + + /* Go through each struct pollfd in the array. */ + for (fdi = 0; fdi < nfds; fdi++) { + if ((opts & LWIP_POLLSCAN_CLEAR) != 0) { + fds[fdi].revents = 0; + } + + /* Negative fd means the caller wants us to ignore this struct. + POLLNVAL means we already detected that the fd is invalid; + if another thread has since opened a new socket with that fd, + we must not use that socket. */ + if (fds[fdi].fd >= 0 && (fds[fdi].revents & POLLNVAL) == 0) { + /* First get the socket's status (protected)... */ + SYS_ARCH_PROTECT(lev); + sock = tryget_socket_unconn_locked(fds[fdi].fd); + if (sock != NULL) { + void* lastdata = sock->lastdata.pbuf; + s16_t rcvevent = sock->rcvevent; + u16_t sendevent = sock->sendevent; + u16_t errevent = sock->errevent; + + if ((opts & LWIP_POLLSCAN_INC_WAIT) != 0) { + sock->select_waiting++; + if (sock->select_waiting == 0) { + /* overflow - too many threads waiting */ + sock->select_waiting--; + nready = -1; + SYS_ARCH_UNPROTECT(lev); + done_socket(sock); + break; + } + } else if ((opts & LWIP_POLLSCAN_DEC_WAIT) != 0) { + /* for now, handle select_waiting==0... */ + LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); + if (sock->select_waiting > 0) { + sock->select_waiting--; + } + } + SYS_ARCH_UNPROTECT(lev); + done_socket(sock); + + /* ... then examine it: */ + /* See if netconn of this socket is ready for read */ + if ((fds[fdi].events & POLLIN) != 0 && ((lastdata != NULL) || (rcvevent > 0))) { + fds[fdi].revents |= POLLIN; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_pollscan: fd=%d ready for reading\n", fds[fdi].fd)); + } + /* See if netconn of this socket is ready for write */ + if ((fds[fdi].events & POLLOUT) != 0 && (sendevent != 0)) { + fds[fdi].revents |= POLLOUT; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_pollscan: fd=%d ready for writing\n", fds[fdi].fd)); + } + /* See if netconn of this socket had an error */ + if (errevent != 0) { + /* POLLERR is output only. */ + fds[fdi].revents |= POLLERR; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_pollscan: fd=%d ready for exception\n", fds[fdi].fd)); + } + } else { + /* Not a valid socket */ + SYS_ARCH_UNPROTECT(lev); + /* POLLNVAL is output only. */ + fds[fdi].revents |= POLLNVAL; + return -1; + } + } + + /* Will return the number of structures that have events, + not the number of events. */ + if (fds[fdi].revents != 0) { + nready++; + } + } + + LWIP_ASSERT("nready >= 0", nready >= 0); + return nready; +} + +#if LWIP_NETCONN_FULLDUPLEX +/* Mark all sockets as used. + * + * All sockets are marked (and later unmarked), whether they are open or not. + * This is OK as lwip_pollscan aborts select when non-open sockets are found. + */ +static void +lwip_poll_inc_sockets_used(struct pollfd *fds, nfds_t nfds) +{ + nfds_t fdi; + + if(fds) { + /* Go through each struct pollfd in the array. */ + for (fdi = 0; fdi < nfds; fdi++) { + /* Increase the reference counter */ + tryget_socket_unconn(fds[fdi].fd); + } + } +} + +/* Let go all sockets that were marked as used when starting poll */ +static void +lwip_poll_dec_sockets_used(struct pollfd *fds, nfds_t nfds) +{ + nfds_t fdi; + + if(fds) { + /* Go through each struct pollfd in the array. */ + for (fdi = 0; fdi < nfds; fdi++) { + struct lwip_sock *sock = tryget_socket_unconn_nouse(fds[fdi].fd); + if (sock != NULL) { + done_socket(sock); + } + } + } +} +#else /* LWIP_NETCONN_FULLDUPLEX */ +#define lwip_poll_inc_sockets_used(fds, nfds) +#define lwip_poll_dec_sockets_used(fds, nfds) +#endif /* LWIP_NETCONN_FULLDUPLEX */ + +int +lwip_poll(struct pollfd *fds, nfds_t nfds, int timeout) +{ + u32_t waitres = 0; + int nready; + u32_t msectimeout; +#if LWIP_NETCONN_SEM_PER_THREAD + int waited = 0; +#endif + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll(%p, %d, %d)\n", + (void*)fds, (int)nfds, timeout)); + LWIP_ERROR("lwip_poll: invalid fds", ((fds != NULL && nfds > 0) || (fds == NULL && nfds == 0)), + set_errno(EINVAL); return -1;); + + lwip_poll_inc_sockets_used(fds, nfds); + + /* Go through each struct pollfd to count number of structures + which currently match */ + nready = lwip_pollscan(fds, nfds, LWIP_POLLSCAN_CLEAR); + + if (nready < 0) { + lwip_poll_dec_sockets_used(fds, nfds); + return -1; + } + + /* If we don't have any current events, then suspend if we are supposed to */ + if (!nready) { + API_SELECT_CB_VAR_DECLARE(select_cb); + + if (timeout == 0) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll: no timeout, returning 0\n")); + goto return_success; + } + API_SELECT_CB_VAR_ALLOC(select_cb, set_errno(EAGAIN); lwip_poll_dec_sockets_used(fds, nfds); return -1); + memset(&API_SELECT_CB_VAR_REF(select_cb), 0, sizeof(struct lwip_select_cb)); + + /* None ready: add our semaphore to list: + We don't actually need any dynamic memory. Our entry on the + list is only valid while we are in this function, so it's ok + to use local variables. */ + + API_SELECT_CB_VAR_REF(select_cb).poll_fds = fds; + API_SELECT_CB_VAR_REF(select_cb).poll_nfds = nfds; +#if LWIP_NETCONN_SEM_PER_THREAD + API_SELECT_CB_VAR_REF(select_cb).sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + if (sys_sem_new(&API_SELECT_CB_VAR_REF(select_cb).sem, 0) != ERR_OK) { + /* failed to create semaphore */ + set_errno(EAGAIN); + lwip_poll_dec_sockets_used(fds, nfds); + API_SELECT_CB_VAR_FREE(select_cb); + return -1; + } +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + lwip_link_select_cb(&API_SELECT_CB_VAR_REF(select_cb)); + + /* Increase select_waiting for each socket we are interested in. + Also, check for events again: there could have been events between + the last scan (without us on the list) and putting us on the list! */ + nready = lwip_pollscan(fds, nfds, LWIP_POLLSCAN_INC_WAIT); + + if (!nready) { + /* Still none ready, just wait to be woken */ + if (timeout < 0) { + /* Wait forever */ + msectimeout = 0; + } else { + /* timeout == 0 would have been handled earlier. */ + LWIP_ASSERT("timeout > 0", timeout > 0); + msectimeout = timeout; + } + waitres = sys_arch_sem_wait(SELECT_SEM_PTR(API_SELECT_CB_VAR_REF(select_cb).sem), msectimeout); +#if LWIP_NETCONN_SEM_PER_THREAD + waited = 1; +#endif + } + + /* Decrease select_waiting for each socket we are interested in, + and check which events occurred while we waited. */ + nready = lwip_pollscan(fds, nfds, LWIP_POLLSCAN_DEC_WAIT); + + lwip_unlink_select_cb(&API_SELECT_CB_VAR_REF(select_cb)); + +#if LWIP_NETCONN_SEM_PER_THREAD + if (select_cb.sem_signalled && (!waited || (waitres == SYS_ARCH_TIMEOUT))) { + /* don't leave the thread-local semaphore signalled */ + sys_arch_sem_wait(API_SELECT_CB_VAR_REF(select_cb).sem, 1); + } +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + sys_sem_free(&API_SELECT_CB_VAR_REF(select_cb).sem); +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + API_SELECT_CB_VAR_FREE(select_cb); + + if (nready < 0) { + /* This happens when a socket got closed while waiting */ + lwip_poll_dec_sockets_used(fds, nfds); + return -1; + } + + if (waitres == SYS_ARCH_TIMEOUT) { + /* Timeout */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll: timeout expired\n")); + goto return_success; + } + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_poll: nready=%d\n", nready)); +return_success: + lwip_poll_dec_sockets_used(fds, nfds); + set_errno(0); + return nready; +} + +/** + * Check whether event_callback should wake up a thread waiting in + * lwip_poll. + */ +static int +lwip_poll_should_wake(const struct lwip_select_cb *scb, int fd, int has_recvevent, int has_sendevent, int has_errevent) +{ + nfds_t fdi; + for (fdi = 0; fdi < scb->poll_nfds; fdi++) { + const struct pollfd *pollfd = &scb->poll_fds[fdi]; + if (pollfd->fd == fd) { + /* Do not update pollfd->revents right here; + that would be a data race because lwip_pollscan + accesses revents without protecting. */ + if (has_recvevent && (pollfd->events & POLLIN) != 0) { + return 1; + } + if (has_sendevent && (pollfd->events & POLLOUT) != 0) { + return 1; + } + if (has_errevent) { + /* POLLERR is output only. */ + return 1; + } + } + } + return 0; +} +#endif /* LWIP_SOCKET_POLL */ + +#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL +/** + * Callback registered in the netconn layer for each socket-netconn. + * Processes recvevent (data available) and wakes up tasks waiting for select. + * + * @note for LWIP_TCPIP_CORE_LOCKING any caller of this function + * must have the core lock held when signaling the following events + * as they might cause select_list_cb to be checked: + * NETCONN_EVT_RCVPLUS + * NETCONN_EVT_SENDPLUS + * NETCONN_EVT_ERROR + * This requirement will be asserted in select_check_waiters() + */ +static void +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) +{ + int s, check_waiters; + struct lwip_sock *sock; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_UNUSED_ARG(len); + + /* Get socket */ + if (conn) { + s = conn->socket; + if (s < 0) { + /* Data comes in right away after an accept, even though + * the server task might not have created a new socket yet. + * Just count down (or up) if that's the case and we + * will use the data later. Note that only receive events + * can happen before the new socket is set up. */ + SYS_ARCH_PROTECT(lev); + if (conn->socket < 0) { + if (evt == NETCONN_EVT_RCVPLUS) { + /* conn->socket is -1 on initialization + lwip_accept adjusts sock->recvevent if conn->socket < -1 */ + conn->socket--; + } + SYS_ARCH_UNPROTECT(lev); + return; + } + s = conn->socket; + SYS_ARCH_UNPROTECT(lev); + } + + sock = get_socket(s); + if (!sock) { + return; + } + } else { + return; + } + + check_waiters = 1; + SYS_ARCH_PROTECT(lev); + /* Set event as required */ + switch (evt) { + case NETCONN_EVT_RCVPLUS: + sock->rcvevent++; + if (sock->rcvevent > 1) { + check_waiters = 0; + } + break; + case NETCONN_EVT_RCVMINUS: + sock->rcvevent--; + check_waiters = 0; + break; + case NETCONN_EVT_SENDPLUS: + if (sock->sendevent) { + check_waiters = 0; + } + sock->sendevent = 1; + break; + case NETCONN_EVT_SENDMINUS: + sock->sendevent = 0; + check_waiters = 0; + break; + case NETCONN_EVT_ERROR: + sock->errevent = 1; + break; + default: + LWIP_ASSERT("unknown event", 0); + break; + } + + if (sock->select_waiting && check_waiters) { + /* Save which events are active */ + int has_recvevent, has_sendevent, has_errevent; + has_recvevent = sock->rcvevent > 0; + has_sendevent = sock->sendevent != 0; + has_errevent = sock->errevent != 0; + SYS_ARCH_UNPROTECT(lev); + /* Check any select calls waiting on this socket */ + select_check_waiters(s, has_recvevent, has_sendevent, has_errevent); + } else { + SYS_ARCH_UNPROTECT(lev); + } + done_socket(sock); +} + +/** + * Check if any select waiters are waiting on this socket and its events + * + * @note on synchronization of select_cb_list: + * LWIP_TCPIP_CORE_LOCKING: the select_cb_list must only be accessed while holding + * the core lock. We do a single pass through the list and signal any waiters. + * Core lock should already be held when calling here!!!! + + * !LWIP_TCPIP_CORE_LOCKING: we use SYS_ARCH_PROTECT but unlock on each iteration + * of the loop, thus creating a possibility where a thread could modify the + * select_cb_list during our UNPROTECT/PROTECT. We use a generational counter to + * detect this change and restart the list walk. The list is expected to be small + */ +static void select_check_waiters(int s, int has_recvevent, int has_sendevent, int has_errevent) +{ + struct lwip_select_cb *scb; +#if !LWIP_TCPIP_CORE_LOCKING + int last_select_cb_ctr; + SYS_ARCH_DECL_PROTECT(lev); +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + + LWIP_ASSERT_CORE_LOCKED(); + +#if !LWIP_TCPIP_CORE_LOCKING + SYS_ARCH_PROTECT(lev); +again: + /* remember the state of select_cb_list to detect changes */ + last_select_cb_ctr = select_cb_ctr; +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + for (scb = select_cb_list; scb != NULL; scb = scb->next) { + if (scb->sem_signalled == 0) { + /* semaphore not signalled yet */ + int do_signal = 0; +#if LWIP_SOCKET_POLL + if (scb->poll_fds != NULL) { + do_signal = lwip_poll_should_wake(scb, s, has_recvevent, has_sendevent, has_errevent); + } +#endif /* LWIP_SOCKET_POLL */ +#if LWIP_SOCKET_SELECT && LWIP_SOCKET_POLL + else +#endif /* LWIP_SOCKET_SELECT && LWIP_SOCKET_POLL */ +#if LWIP_SOCKET_SELECT + { + /* Test this select call for our socket */ + if (has_recvevent) { + if (scb->readset && FD_ISSET(s, scb->readset)) { + do_signal = 1; + } + } + if (has_sendevent) { + if (!do_signal && scb->writeset && FD_ISSET(s, scb->writeset)) { + do_signal = 1; + } + } + if (has_errevent) { + if (!do_signal && scb->exceptset && FD_ISSET(s, scb->exceptset)) { + do_signal = 1; + } + } + } +#endif /* LWIP_SOCKET_SELECT */ + if (do_signal) { + scb->sem_signalled = 1; + /* For !LWIP_TCPIP_CORE_LOCKING, we don't call SYS_ARCH_UNPROTECT() before signaling + the semaphore, as this might lead to the select thread taking itself off the list, + invalidating the semaphore. */ + sys_sem_signal(SELECT_SEM_PTR(scb->sem)); + } + } +#if LWIP_TCPIP_CORE_LOCKING + } +#else + /* unlock interrupts with each step */ + SYS_ARCH_UNPROTECT(lev); + /* this makes sure interrupt protection time is short */ + SYS_ARCH_PROTECT(lev); + if (last_select_cb_ctr != select_cb_ctr) { + /* someone has changed select_cb_list, restart at the beginning */ + goto again; + } + /* remember the state of select_cb_list to detect changes */ + last_select_cb_ctr = select_cb_ctr; + } + SYS_ARCH_UNPROTECT(lev); +#endif +} +#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */ + +/** + * Close one end of a full-duplex connection. + */ +int +lwip_shutdown(int s, int how) +{ + struct lwip_sock *sock; + err_t err; + u8_t shut_rx = 0, shut_tx = 0; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn != NULL) { + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + done_socket(sock); + return -1; + } + } else { + sock_set_errno(sock, ENOTCONN); + done_socket(sock); + return -1; + } + + if (how == SHUT_RD) { + shut_rx = 1; + } else if (how == SHUT_WR) { + shut_tx = 1; + } else if (how == SHUT_RDWR) { + shut_rx = 1; + shut_tx = 1; + } else { + sock_set_errno(sock, EINVAL); + done_socket(sock); + return -1; + } + err = netconn_shutdown(sock->conn, shut_rx, shut_tx); + + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return (err == ERR_OK ? 0 : -1); +} + +static int +lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local) +{ + struct lwip_sock *sock; + union sockaddr_aligned saddr; + ip_addr_t naddr; + u16_t port; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* get the IP address and port */ + err = netconn_getaddr(sock->conn, &naddr, &port, local); + if (err != ERR_OK) { + sock_set_errno(sock, err_to_errno(err)); + done_socket(sock); + return -1; + } + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ + if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) && + IP_IS_V4_VAL(naddr)) { + ip4_2_ipv4_mapped_ipv6(ip_2_ip6(&naddr), ip_2_ip4(&naddr)); + IP_SET_TYPE_VAL(naddr, IPADDR_TYPE_V6); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + IPADDR_PORT_TO_SOCKADDR(&saddr, &naddr, port); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", port)); + + if (*namelen > saddr.sa.sa_len) { + *namelen = saddr.sa.sa_len; + } + MEMCPY(name, &saddr, *namelen); + + sock_set_errno(sock, 0); + done_socket(sock); + return 0; +} + +int +lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 0); +} + +int +lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 1); +} + +int +lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + int err; + struct lwip_sock *sock = get_socket(s); +#if !LWIP_TCPIP_CORE_LOCKING + err_t cberr; + LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + + if (!sock) { + return -1; + } + + if ((NULL == optval) || (NULL == optlen)) { + sock_set_errno(sock, EFAULT); + done_socket(sock); + return -1; + } + +#if LWIP_TCPIP_CORE_LOCKING + /* core-locking can just call the -impl function */ + LOCK_TCPIP_CORE(); + err = lwip_getsockopt_impl(s, level, optname, optval, optlen); + UNLOCK_TCPIP_CORE(); + +#else /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_MPU_COMPATIBLE + /* MPU_COMPATIBLE copies the optval data, so check for max size here */ + if (*optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { + sock_set_errno(sock, ENOBUFS); + done_socket(sock); + return -1; + } +#endif /* LWIP_MPU_COMPATIBLE */ + + LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = *optlen; +#if !LWIP_MPU_COMPATIBLE + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.p = optval; +#endif /* !LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; +#endif + cberr = tcpip_callback(lwip_getsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); + if (cberr != ERR_OK) { + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); + sock_set_errno(sock, err_to_errno(cberr)); + done_socket(sock); + return -1; + } + sys_arch_sem_wait((sys_sem_t *)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); + + /* write back optlen and optval */ + *optlen = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen; +#if LWIP_MPU_COMPATIBLE + MEMCPY(optval, LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen); +#endif /* LWIP_MPU_COMPATIBLE */ + + /* maybe lwip_getsockopt_internal has changed err */ + err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sock_set_errno(sock, err); + done_socket(sock); + return err ? -1 : 0; +} + +#if !LWIP_TCPIP_CORE_LOCKING +/** lwip_getsockopt_callback: only used without CORE_LOCKING + * to get into the tcpip_thread + */ +static void +lwip_getsockopt_callback(void *arg) +{ + struct lwip_setgetsockopt_data *data; + LWIP_ASSERT("arg != NULL", arg != NULL); + data = (struct lwip_setgetsockopt_data *)arg; + + data->err = lwip_getsockopt_impl(data->s, data->level, data->optname, +#if LWIP_MPU_COMPATIBLE + data->optval, +#else /* LWIP_MPU_COMPATIBLE */ + data->optval.p, +#endif /* LWIP_MPU_COMPATIBLE */ + &data->optlen); + + sys_sem_signal((sys_sem_t *)(data->completed_sem)); +} +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +static int +lwip_sockopt_to_ipopt(int optname) +{ + /* Map SO_* values to our internal SOF_* values + * We should not rely on #defines in socket.h + * being in sync with ip.h. + */ + switch (optname) { + case SO_BROADCAST: + return SOF_BROADCAST; + case SO_KEEPALIVE: + return SOF_KEEPALIVE; + case SO_REUSEADDR: + return SOF_REUSEADDR; + default: + LWIP_ASSERT("Unknown socket option", 0); + return 0; + } +} + +/** lwip_getsockopt_impl: the actual implementation of getsockopt: + * same argument as lwip_getsockopt, either called directly or through callback + */ +static int +lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + int err = 0; + struct lwip_sock *sock = tryget_socket(s); + if (!sock) { + return EBADF; + } + +#ifdef LWIP_HOOK_SOCKETS_GETSOCKOPT + if (LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, &err)) { + return err; + } +#endif + + switch (level) { + + /* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + +#if LWIP_TCP + case SO_ACCEPTCONN: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_TCP) { + done_socket(sock); + return ENOPROTOOPT; + } + if ((sock->conn->pcb.tcp != NULL) && (sock->conn->pcb.tcp->state == LISTEN)) { + *(int *)optval = 1; + } else { + *(int *)optval = 0; + } + break; +#endif /* LWIP_TCP */ + + /* The option flags */ + case SO_BROADCAST: + case SO_KEEPALIVE: +#if SO_REUSE + case SO_REUSEADDR: +#endif /* SO_REUSE */ + if ((optname == SO_BROADCAST) && + (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP)) { + done_socket(sock); + return ENOPROTOOPT; + } + + optname = lwip_sockopt_to_ipopt(optname); + + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int *)optval = ip_get_option(sock->conn->pcb.ip, optname); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", + s, optname, (*(int *)optval ? "on" : "off"))); + break; + + case SO_TYPE: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + switch (NETCONNTYPE_GROUP(netconn_type(sock->conn))) { + case NETCONN_RAW: + *(int *)optval = SOCK_RAW; + break; + case NETCONN_TCP: + *(int *)optval = SOCK_STREAM; + break; + case NETCONN_UDP: + *(int *)optval = SOCK_DGRAM; + break; + default: /* unrecognized socket type */ + *(int *)optval = netconn_type(sock->conn); + LWIP_DEBUGF(SOCKETS_DEBUG, + ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", + s, *(int *)optval)); + } /* switch (netconn_type(sock->conn)) */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", + s, *(int *)optval)); + break; + + case SO_ERROR: + LWIP_SOCKOPT_CHECK_OPTLEN(sock, *optlen, int); + *(int *)optval = err_to_errno(netconn_err(sock->conn)); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_SO_SNDTIMEO + case SO_SNDTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_sendtimeout(sock->conn)); + break; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_recvtimeout(sock->conn)); + break; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + *(int *)optval = netconn_get_recvbufsize(sock->conn); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + case SO_LINGER: { + s16_t conn_linger; + struct linger *linger = (struct linger *)optval; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, struct linger); + conn_linger = sock->conn->linger; + if (conn_linger >= 0) { + linger->l_onoff = 1; + linger->l_linger = (int)conn_linger; + } else { + linger->l_onoff = 0; + linger->l_linger = 0; + } + } + break; +#endif /* LWIP_SO_LINGER */ +#if LWIP_UDP + case SO_NO_CHECK: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_UDP); +#if LWIP_UDPLITE + if (udp_is_flag_set(sock->conn->pcb.udp, UDP_FLAGS_UDPLITE)) { + /* this flag is only available for UDP, not for UDP lite */ + done_socket(sock); + return EAFNOSUPPORT; + } +#endif /* LWIP_UDPLITE */ + *(int *)optval = udp_is_flag_set(sock->conn->pcb.udp, UDP_FLAGS_NOCHKSUM) ? 1 : 0; + break; +#endif /* LWIP_UDP*/ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + + /* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int *)optval = sock->conn->pcb.ip->ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_TOS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int *)optval = sock->conn->pcb.ip->tos; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", + s, *(int *)optval)); + break; +#if LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP + case IP_MULTICAST_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + done_socket(sock); + return ENOPROTOOPT; + } + *(u8_t *)optval = udp_get_multicast_ttl(sock->conn->pcb.udp); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_MULTICAST_IF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, struct in_addr); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + done_socket(sock); + return ENOPROTOOPT; + } + inet_addr_from_ip4addr((struct in_addr *)optval, udp_get_multicast_netif_addr(sock->conn->pcb.udp)); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n", + s, *(u32_t *)optval)); + break; + case IP_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) { + *(u8_t *)optval = 1; + } else { + *(u8_t *)optval = 0; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_LOOP) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP + /* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + /* Special case: all IPPROTO_TCP option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_TCP); + if (sock->conn->pcb.tcp->state == LISTEN) { + done_socket(sock); + return EINVAL; + } + switch (optname) { + case TCP_NODELAY: + *(int *)optval = tcp_nagle_disabled(sock->conn->pcb.tcp); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", + s, (*(int *)optval) ? "on" : "off") ); + break; + case TCP_KEEPALIVE: + *(int *)optval = (int)sock->conn->pcb.tcp->keep_idle; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + *(int *)optval = (int)(sock->conn->pcb.tcp->keep_idle / 1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPINTVL: + *(int *)optval = (int)(sock->conn->pcb.tcp->keep_intvl / 1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPCNT: + *(int *)optval = (int)sock->conn->pcb.tcp->keep_cnt; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP */ + +#if LWIP_IPV6 + /* Level: IPPROTO_IPV6 */ + case IPPROTO_IPV6: + switch (optname) { + case IPV6_V6ONLY: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + *(int *)optval = (netconn_get_ipv6only(sock->conn) ? 1 : 0); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY) = %d\n", + s, *(int *)optval)); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_IPV6 */ + +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + /* Special case: all IPPROTO_UDPLITE option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + /* If this is no UDP lite socket, ignore any options. */ + if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { + done_socket(sock); + return ENOPROTOOPT; + } + switch (optname) { + case UDPLITE_SEND_CSCOV: + *(int *)optval = sock->conn->pcb.udp->chksum_len_tx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n", + s, (*(int *)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + *(int *)optval = sock->conn->pcb.udp->chksum_len_rx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n", + s, (*(int *)optval)) ); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + /* Level: IPPROTO_RAW */ + case IPPROTO_RAW: + switch (optname) { +#if LWIP_IPV6 && LWIP_RAW + case IPV6_CHECKSUM: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_RAW); + if (sock->conn->pcb.raw->chksum_reqd == 0) { + *(int *)optval = -1; + } else { + *(int *)optval = sock->conn->pcb.raw->chksum_offset; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM) = %d\n", + s, (*(int *)optval)) ); + break; +#endif /* LWIP_IPV6 && LWIP_RAW */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + break; + } /* switch (level) */ + + done_socket(sock); + return err; +} + +int +lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + int err = 0; + struct lwip_sock *sock = get_socket(s); +#if !LWIP_TCPIP_CORE_LOCKING + err_t cberr; + LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + + if (!sock) { + return -1; + } + + if (NULL == optval) { + sock_set_errno(sock, EFAULT); + done_socket(sock); + return -1; + } + +#if LWIP_TCPIP_CORE_LOCKING + /* core-locking can just call the -impl function */ + LOCK_TCPIP_CORE(); + err = lwip_setsockopt_impl(s, level, optname, optval, optlen); + UNLOCK_TCPIP_CORE(); + +#else /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_MPU_COMPATIBLE + /* MPU_COMPATIBLE copies the optval data, so check for max size here */ + if (optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { + sock_set_errno(sock, ENOBUFS); + done_socket(sock); + return -1; + } +#endif /* LWIP_MPU_COMPATIBLE */ + + LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = optlen; +#if LWIP_MPU_COMPATIBLE + MEMCPY(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, optval, optlen); +#else /* LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.pc = (const void *)optval; +#endif /* LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; +#endif + cberr = tcpip_callback(lwip_setsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); + if (cberr != ERR_OK) { + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); + sock_set_errno(sock, err_to_errno(cberr)); + done_socket(sock); + return -1; + } + sys_arch_sem_wait((sys_sem_t *)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); + + /* maybe lwip_getsockopt_internal has changed err */ + err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sock_set_errno(sock, err); + done_socket(sock); + return err ? -1 : 0; +} + +#if !LWIP_TCPIP_CORE_LOCKING +/** lwip_setsockopt_callback: only used without CORE_LOCKING + * to get into the tcpip_thread + */ +static void +lwip_setsockopt_callback(void *arg) +{ + struct lwip_setgetsockopt_data *data; + LWIP_ASSERT("arg != NULL", arg != NULL); + data = (struct lwip_setgetsockopt_data *)arg; + + data->err = lwip_setsockopt_impl(data->s, data->level, data->optname, +#if LWIP_MPU_COMPATIBLE + data->optval, +#else /* LWIP_MPU_COMPATIBLE */ + data->optval.pc, +#endif /* LWIP_MPU_COMPATIBLE */ + data->optlen); + + sys_sem_signal((sys_sem_t *)(data->completed_sem)); +} +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +/** lwip_setsockopt_impl: the actual implementation of setsockopt: + * same argument as lwip_setsockopt, either called directly or through callback + */ +static int +lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + int err = 0; + struct lwip_sock *sock = tryget_socket(s); + if (!sock) { + return EBADF; + } + +#ifdef LWIP_HOOK_SOCKETS_SETSOCKOPT + if (LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, &err)) { + return err; + } +#endif + + switch (level) { + + /* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + + /* SO_ACCEPTCONN is get-only */ + + /* The option flags */ + case SO_BROADCAST: + case SO_KEEPALIVE: +#if SO_REUSE + case SO_REUSEADDR: +#endif /* SO_REUSE */ + if ((optname == SO_BROADCAST) && + (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_UDP)) { + done_socket(sock); + return ENOPROTOOPT; + } + + optname = lwip_sockopt_to_ipopt(optname); + + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + if (*(const int *)optval) { + ip_set_option(sock->conn->pcb.ip, optname); + } else { + ip_reset_option(sock->conn->pcb.ip, optname); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", + s, optname, (*(const int *)optval ? "on" : "off"))); + break; + + /* SO_TYPE is get-only */ + /* SO_ERROR is get-only */ + +#if LWIP_SO_SNDTIMEO + case SO_SNDTIMEO: { + long ms_long; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + ms_long = LWIP_SO_SNDRCVTIMEO_GET_MS(optval); + if (ms_long < 0) { + done_socket(sock); + return EINVAL; + } + netconn_set_sendtimeout(sock->conn, ms_long); + break; + } +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: { + long ms_long; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + ms_long = LWIP_SO_SNDRCVTIMEO_GET_MS(optval); + if (ms_long < 0) { + done_socket(sock); + return EINVAL; + } + netconn_set_recvtimeout(sock->conn, (u32_t)ms_long); + break; + } +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, int); + netconn_set_recvbufsize(sock->conn, *(const int *)optval); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + case SO_LINGER: { + const struct linger *linger = (const struct linger *)optval; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, struct linger); + if (linger->l_onoff) { + int lingersec = linger->l_linger; + if (lingersec < 0) { + done_socket(sock); + return EINVAL; + } + if (lingersec > 0xFFFF) { + lingersec = 0xFFFF; + } + sock->conn->linger = (s16_t)lingersec; + } else { + sock->conn->linger = -1; + } + } + break; +#endif /* LWIP_SO_LINGER */ +#if LWIP_UDP + case SO_NO_CHECK: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_UDP); +#if LWIP_UDPLITE + if (udp_is_flag_set(sock->conn->pcb.udp, UDP_FLAGS_UDPLITE)) { + /* this flag is only available for UDP, not for UDP lite */ + done_socket(sock); + return EAFNOSUPPORT; + } +#endif /* LWIP_UDPLITE */ + if (*(const int *)optval) { + udp_set_flags(sock->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + } else { + udp_clear_flags(sock->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + } + break; +#endif /* LWIP_UDP */ + case SO_BINDTODEVICE: { + const struct ifreq *iface; + struct netif *n = NULL; + + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, struct ifreq); + + iface = (const struct ifreq *)optval; + if (iface->ifr_name[0] != 0) { + n = netif_find(iface->ifr_name); + if (n == NULL) { + done_socket(sock); + return ENODEV; + } + } + + switch (NETCONNTYPE_GROUP(netconn_type(sock->conn))) { +#if LWIP_TCP + case NETCONN_TCP: + tcp_bind_netif(sock->conn->pcb.tcp, n); + break; +#endif +#if LWIP_UDP + case NETCONN_UDP: + udp_bind_netif(sock->conn->pcb.udp, n); + break; +#endif +#if LWIP_RAW + case NETCONN_RAW: + raw_bind_netif(sock->conn->pcb.raw, n); + break; +#endif + default: + LWIP_ASSERT("Unhandled netconn type in SO_BINDTODEVICE", 0); + break; + } + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + + /* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + sock->conn->pcb.ip->ttl = (u8_t)(*(const int *)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n", + s, sock->conn->pcb.ip->ttl)); + break; + case IP_TOS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + sock->conn->pcb.ip->tos = (u8_t)(*(const int *)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n", + s, sock->conn->pcb.ip->tos)); + break; +#if LWIP_NETBUF_RECVINFO + case IP_PKTINFO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_UDP); + if (*(const int *)optval) { + sock->conn->flags |= NETCONN_FLAG_PKTINFO; + } else { + sock->conn->flags &= ~NETCONN_FLAG_PKTINFO; + } + break; +#endif /* LWIP_NETBUF_RECVINFO */ +#if LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP + case IP_MULTICAST_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + udp_set_multicast_ttl(sock->conn->pcb.udp, (u8_t)(*(const u8_t *)optval)); + break; + case IP_MULTICAST_IF: { + ip4_addr_t if_addr; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct in_addr, NETCONN_UDP); + inet_addr_to_ip4addr(&if_addr, (const struct in_addr *)optval); + udp_set_multicast_netif_addr(sock->conn->pcb.udp, &if_addr); + } + break; + case IP_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + if (*(const u8_t *)optval) { + udp_set_flags(sock->conn->pcb.udp, UDP_FLAGS_MULTICAST_LOOP); + } else { + udp_clear_flags(sock->conn->pcb.udp, UDP_FLAGS_MULTICAST_LOOP); + } + break; +#endif /* LWIP_IPV4 && LWIP_MULTICAST_TX_OPTIONS && LWIP_UDP */ +#if LWIP_IGMP + case IP_ADD_MEMBERSHIP: + case IP_DROP_MEMBERSHIP: { + /* If this is a TCP or a RAW socket, ignore these options. */ + err_t igmp_err; + const struct ip_mreq *imr = (const struct ip_mreq *)optval; + ip4_addr_t if_addr; + ip4_addr_t multi_addr; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ip_mreq, NETCONN_UDP); + inet_addr_to_ip4addr(&if_addr, &imr->imr_interface); + inet_addr_to_ip4addr(&multi_addr, &imr->imr_multiaddr); + if (optname == IP_ADD_MEMBERSHIP) { + if (!lwip_socket_register_membership(s, &if_addr, &multi_addr)) { + /* cannot track membership (out of memory) */ + err = ENOMEM; + igmp_err = ERR_OK; + } else { + igmp_err = igmp_joingroup(&if_addr, &multi_addr); + } + } else { + igmp_err = igmp_leavegroup(&if_addr, &multi_addr); + lwip_socket_unregister_membership(s, &if_addr, &multi_addr); + } + if (igmp_err != ERR_OK) { + err = EADDRNOTAVAIL; + } + } + break; +#endif /* LWIP_IGMP */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP + /* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + /* Special case: all IPPROTO_TCP option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP); + if (sock->conn->pcb.tcp->state == LISTEN) { + done_socket(sock); + return EINVAL; + } + switch (optname) { + case TCP_NODELAY: + if (*(const int *)optval) { + tcp_nagle_disable(sock->conn->pcb.tcp); + } else { + tcp_nagle_enable(sock->conn->pcb.tcp); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", + s, (*(const int *)optval) ? "on" : "off") ); + break; + case TCP_KEEPALIVE: + sock->conn->pcb.tcp->keep_idle = (u32_t)(*(const int *)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + sock->conn->pcb.tcp->keep_idle = 1000 * (u32_t)(*(const int *)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + case TCP_KEEPINTVL: + sock->conn->pcb.tcp->keep_intvl = 1000 * (u32_t)(*(const int *)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_intvl)); + break; + case TCP_KEEPCNT: + sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(const int *)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_cnt)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP*/ + +#if LWIP_IPV6 + /* Level: IPPROTO_IPV6 */ + case IPPROTO_IPV6: + switch (optname) { + case IPV6_V6ONLY: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + if (*(const int *)optval) { + netconn_set_ipv6only(sock->conn, 1); + } else { + netconn_set_ipv6only(sock->conn, 0); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY, ..) -> %d\n", + s, (netconn_get_ipv6only(sock->conn) ? 1 : 0))); + break; +#if LWIP_IPV6_MLD + case IPV6_JOIN_GROUP: + case IPV6_LEAVE_GROUP: { + /* If this is a TCP or a RAW socket, ignore these options. */ + err_t mld6_err; + struct netif *netif; + ip6_addr_t multi_addr; + const struct ipv6_mreq *imr = (const struct ipv6_mreq *)optval; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ipv6_mreq, NETCONN_UDP); + inet6_addr_to_ip6addr(&multi_addr, &imr->ipv6mr_multiaddr); + LWIP_ASSERT("Invalid netif index", imr->ipv6mr_interface <= 0xFFu); + netif = netif_get_by_index((u8_t)imr->ipv6mr_interface); + if (netif == NULL) { + err = EADDRNOTAVAIL; + break; + } + + if (optname == IPV6_JOIN_GROUP) { + if (!lwip_socket_register_mld6_membership(s, imr->ipv6mr_interface, &multi_addr)) { + /* cannot track membership (out of memory) */ + err = ENOMEM; + mld6_err = ERR_OK; + } else { + mld6_err = mld6_joingroup_netif(netif, &multi_addr); + } + } else { + mld6_err = mld6_leavegroup_netif(netif, &multi_addr); + lwip_socket_unregister_mld6_membership(s, imr->ipv6mr_interface, &multi_addr); + } + if (mld6_err != ERR_OK) { + err = EADDRNOTAVAIL; + } + } + break; +#endif /* LWIP_IPV6_MLD */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_IPV6 */ + +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + /* Special case: all IPPROTO_UDPLITE option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + /* If this is no UDP lite socket, ignore any options. */ + if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { + done_socket(sock); + return ENOPROTOOPT; + } + switch (optname) { + case UDPLITE_SEND_CSCOV: + if ((*(const int *)optval != 0) && ((*(const int *)optval < 8) || (*(const int *)optval > 0xffff))) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_tx = 8; + } else { + sock->conn->pcb.udp->chksum_len_tx = (u16_t) * (const int *)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n", + s, (*(const int *)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + if ((*(const int *)optval != 0) && ((*(const int *)optval < 8) || (*(const int *)optval > 0xffff))) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_rx = 8; + } else { + sock->conn->pcb.udp->chksum_len_rx = (u16_t) * (const int *)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n", + s, (*(const int *)optval)) ); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + /* Level: IPPROTO_RAW */ + case IPPROTO_RAW: + switch (optname) { +#if LWIP_IPV6 && LWIP_RAW + case IPV6_CHECKSUM: + /* It should not be possible to disable the checksum generation with ICMPv6 + * as per RFC 3542 chapter 3.1 */ + if (sock->conn->pcb.raw->protocol == IPPROTO_ICMPV6) { + done_socket(sock); + return EINVAL; + } + + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_RAW); + if (*(const int *)optval < 0) { + sock->conn->pcb.raw->chksum_reqd = 0; + } else if (*(const int *)optval & 1) { + /* Per RFC3542, odd offsets are not allowed */ + done_socket(sock); + return EINVAL; + } else { + sock->conn->pcb.raw->chksum_reqd = 1; + sock->conn->pcb.raw->chksum_offset = (u16_t) * (const int *)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM, ..) -> %d\n", + s, sock->conn->pcb.raw->chksum_reqd)); + break; +#endif /* LWIP_IPV6 && LWIP_RAW */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + break; + } /* switch (level) */ + + done_socket(sock); + return err; +} + +int +lwip_ioctl(int s, long cmd, void *argp) +{ + struct lwip_sock *sock = get_socket(s); + u8_t val; +#if LWIP_SO_RCVBUF + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + if (!sock) { + return -1; + } + + switch (cmd) { +#if LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE + case FIONREAD: + if (!argp) { + sock_set_errno(sock, EINVAL); + done_socket(sock); + return -1; + } +#if LWIP_FIONREAD_LINUXMODE + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + struct netbuf *nb; + if (sock->lastdata.netbuf) { + nb = sock->lastdata.netbuf; + *((int *)argp) = nb->p->tot_len; + } else { + struct netbuf *rxbuf; + err_t err = netconn_recv_udp_raw_netbuf_flags(sock->conn, &rxbuf, NETCONN_DONTBLOCK); + if (err != ERR_OK) { + *((int *)argp) = 0; + } else { + sock->lastdata.netbuf = rxbuf; + *((int *)argp) = rxbuf->p->tot_len; + } + } + done_socket(sock); + return 0; + } +#endif /* LWIP_FIONREAD_LINUXMODE */ + +#if LWIP_SO_RCVBUF + /* we come here if either LWIP_FIONREAD_LINUXMODE==0 or this is a TCP socket */ + SYS_ARCH_GET(sock->conn->recv_avail, recv_avail); + if (recv_avail < 0) { + recv_avail = 0; + } + + /* Check if there is data left from the last recv operation. /maq 041215 */ + if (sock->lastdata.netbuf) { + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + recv_avail += sock->lastdata.pbuf->tot_len; + } else { + recv_avail += sock->lastdata.netbuf->p->tot_len; + } + } + *((int *)argp) = recv_avail; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t *)argp))); + sock_set_errno(sock, 0); + done_socket(sock); + return 0; +#else /* LWIP_SO_RCVBUF */ + break; +#endif /* LWIP_SO_RCVBUF */ +#endif /* LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE */ + + case (long)FIONBIO: + val = 0; + if (argp && *(int *)argp) { + val = 1; + } + netconn_set_nonblocking(sock->conn, val); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, val)); + sock_set_errno(sock, 0); + done_socket(sock); + return 0; + + default: + break; + } /* switch (cmd) */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + done_socket(sock); + return -1; +} + +/** A minimal implementation of fcntl. + * Currently only the commands F_GETFL and F_SETFL are implemented. + * The flag O_NONBLOCK and access modes are supported for F_GETFL, only + * the flag O_NONBLOCK is implemented for F_SETFL. + */ +int +lwip_fcntl(int s, int cmd, int val) +{ + struct lwip_sock *sock = get_socket(s); + int ret = -1; + int op_mode = 0; + + if (!sock) { + return -1; + } + + switch (cmd) { + case F_GETFL: + ret = netconn_is_nonblocking(sock->conn) ? O_NONBLOCK : 0; + sock_set_errno(sock, 0); + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCPIP_CORE_LOCKING + LOCK_TCPIP_CORE(); +#else + SYS_ARCH_DECL_PROTECT(lev); + /* the proper thing to do here would be to get into the tcpip_thread, + but locking should be OK as well since we only *read* some flags */ + SYS_ARCH_PROTECT(lev); +#endif +#if LWIP_TCP + if (sock->conn->pcb.tcp) { + if (!(sock->conn->pcb.tcp->flags & TF_RXCLOSED)) { + op_mode |= O_RDONLY; + } + if (!(sock->conn->pcb.tcp->flags & TF_FIN)) { + op_mode |= O_WRONLY; + } + } +#endif +#if LWIP_TCPIP_CORE_LOCKING + UNLOCK_TCPIP_CORE(); +#else + SYS_ARCH_UNPROTECT(lev); +#endif + } else { + op_mode |= O_RDWR; + } + + /* ensure O_RDWR for (O_RDONLY|O_WRONLY) != O_RDWR cases */ + ret |= (op_mode == (O_RDONLY | O_WRONLY)) ? O_RDWR : op_mode; + + break; + case F_SETFL: + /* Bits corresponding to the file access mode and the file creation flags [..] that are set in arg shall be ignored */ + val &= ~(O_RDONLY | O_WRONLY | O_RDWR); + if ((val & ~O_NONBLOCK) == 0) { + /* only O_NONBLOCK, all other bits are zero */ + netconn_set_nonblocking(sock->conn, val & O_NONBLOCK); + ret = 0; + sock_set_errno(sock, 0); + } else { + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_fcntl(%d, UNIMPL: %d, %d)\n", s, cmd, val)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + break; + } + done_socket(sock); + return ret; +} + +#if LWIP_COMPAT_SOCKETS == 2 && LWIP_POSIX_SOCKETS_IO_NAMES +int +fcntl(int s, int cmd, ...) +{ + va_list ap; + int val; + + va_start(ap, cmd); + val = va_arg(ap, int); + va_end(ap); + return lwip_fcntl(s, cmd, val); +} +#endif + +const char * +lwip_inet_ntop(int af, const void *src, char *dst, socklen_t size) +{ + const char *ret = NULL; + int size_int = (int)size; + if (size_int < 0) { + set_errno(ENOSPC); + return NULL; + } + switch (af) { +#if LWIP_IPV4 + case AF_INET: + ret = ip4addr_ntoa_r((const ip4_addr_t *)src, dst, size_int); + if (ret == NULL) { + set_errno(ENOSPC); + } + break; +#endif +#if LWIP_IPV6 + case AF_INET6: + ret = ip6addr_ntoa_r((const ip6_addr_t *)src, dst, size_int); + if (ret == NULL) { + set_errno(ENOSPC); + } + break; +#endif + default: + set_errno(EAFNOSUPPORT); + break; + } + return ret; +} + +int +lwip_inet_pton(int af, const char *src, void *dst) +{ + int err; + switch (af) { +#if LWIP_IPV4 + case AF_INET: + err = ip4addr_aton(src, (ip4_addr_t *)dst); + break; +#endif +#if LWIP_IPV6 + case AF_INET6: { + /* convert into temporary variable since ip6_addr_t might be larger + than in6_addr when scopes are enabled */ + ip6_addr_t addr; + err = ip6addr_aton(src, &addr); + if (err) { + memcpy(dst, &addr.addr, sizeof(addr.addr)); + } + break; + } +#endif + default: + err = -1; + set_errno(EAFNOSUPPORT); + break; + } + return err; +} + +#if LWIP_IGMP +/** Register a new IGMP membership. On socket close, the membership is dropped automatically. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + * + * @return 1 on success, 0 on failure + */ +static int +lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return 0; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv4_multicast_memberships[i].sock == NULL) { + socket_ipv4_multicast_memberships[i].sock = sock; + ip4_addr_copy(socket_ipv4_multicast_memberships[i].if_addr, *if_addr); + ip4_addr_copy(socket_ipv4_multicast_memberships[i].multi_addr, *multi_addr); + done_socket(sock); + return 1; + } + } + done_socket(sock); + return 0; +} + +/** Unregister a previously registered membership. This prevents dropping the membership + * on socket close. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if ((socket_ipv4_multicast_memberships[i].sock == sock) && + ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].if_addr, if_addr) && + ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].multi_addr, multi_addr)) { + socket_ipv4_multicast_memberships[i].sock = NULL; + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); + break; + } + } + done_socket(sock); +} + +/** Drop all memberships of a socket that were not dropped explicitly via setsockopt. + * + * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_drop_registered_memberships(int s) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv4_multicast_memberships[i].sock == sock) { + ip_addr_t multi_addr, if_addr; + ip_addr_copy_from_ip4(multi_addr, socket_ipv4_multicast_memberships[i].multi_addr); + ip_addr_copy_from_ip4(if_addr, socket_ipv4_multicast_memberships[i].if_addr); + socket_ipv4_multicast_memberships[i].sock = NULL; + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); + + netconn_join_leave_group(sock->conn, &multi_addr, &if_addr, NETCONN_LEAVE); + } + } + done_socket(sock); +} +#endif /* LWIP_IGMP */ + +#if LWIP_IPV6_MLD +/** Register a new MLD6 membership. On socket close, the membership is dropped automatically. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + * + * @return 1 on success, 0 on failure + */ +static int +lwip_socket_register_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return 0; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv6_multicast_memberships[i].sock == NULL) { + socket_ipv6_multicast_memberships[i].sock = sock; + socket_ipv6_multicast_memberships[i].if_idx = (u8_t)if_idx; + ip6_addr_copy(socket_ipv6_multicast_memberships[i].multi_addr, *multi_addr); + done_socket(sock); + return 1; + } + } + done_socket(sock); + return 0; +} + +/** Unregister a previously registered MLD6 membership. This prevents dropping the membership + * on socket close. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_unregister_mld6_membership(int s, unsigned int if_idx, const ip6_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if ((socket_ipv6_multicast_memberships[i].sock == sock) && + (socket_ipv6_multicast_memberships[i].if_idx == if_idx) && + ip6_addr_cmp(&socket_ipv6_multicast_memberships[i].multi_addr, multi_addr)) { + socket_ipv6_multicast_memberships[i].sock = NULL; + socket_ipv6_multicast_memberships[i].if_idx = NETIF_NO_INDEX; + ip6_addr_set_zero(&socket_ipv6_multicast_memberships[i].multi_addr); + break; + } + } + done_socket(sock); +} + +/** Drop all MLD6 memberships of a socket that were not dropped explicitly via setsockopt. + * + * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_drop_registered_mld6_memberships(int s) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv6_multicast_memberships[i].sock == sock) { + ip_addr_t multi_addr; + u8_t if_idx; + + ip_addr_copy_from_ip6(multi_addr, socket_ipv6_multicast_memberships[i].multi_addr); + if_idx = socket_ipv6_multicast_memberships[i].if_idx; + + socket_ipv6_multicast_memberships[i].sock = NULL; + socket_ipv6_multicast_memberships[i].if_idx = NETIF_NO_INDEX; + ip6_addr_set_zero(&socket_ipv6_multicast_memberships[i].multi_addr); + + netconn_join_leave_group_netif(sock->conn, &multi_addr, if_idx, NETCONN_LEAVE); + } + } + done_socket(sock); +} +#endif /* LWIP_IPV6_MLD */ + +#endif /* LWIP_SOCKET */ diff --git a/Middlewares/Third_Party/LwIP/src/api/tcpip.c b/Middlewares/Third_Party/LwIP/src/api/tcpip.c new file mode 100644 index 0000000..743553a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/api/tcpip.c @@ -0,0 +1,658 @@ +/** + * @file + * Sequential API Main thread module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/priv/tcpip_priv.h" +#include "lwip/sys.h" +#include "lwip/memp.h" +#include "lwip/mem.h" +#include "lwip/init.h" +#include "lwip/ip.h" +#include "lwip/pbuf.h" +#include "lwip/etharp.h" +#include "netif/ethernet.h" + +#define TCPIP_MSG_VAR_REF(name) API_VAR_REF(name) +#define TCPIP_MSG_VAR_DECLARE(name) API_VAR_DECLARE(struct tcpip_msg, name) +#define TCPIP_MSG_VAR_ALLOC(name) API_VAR_ALLOC(struct tcpip_msg, MEMP_TCPIP_MSG_API, name, ERR_MEM) +#define TCPIP_MSG_VAR_FREE(name) API_VAR_FREE(MEMP_TCPIP_MSG_API, name) + +/* global variables */ +static tcpip_init_done_fn tcpip_init_done; +static void *tcpip_init_done_arg; +static sys_mbox_t tcpip_mbox; + +#if LWIP_TCPIP_CORE_LOCKING +/** The global semaphore to lock the stack. */ +sys_mutex_t lock_tcpip_core; +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +static void tcpip_thread_handle_msg(struct tcpip_msg *msg); + +#if !LWIP_TIMERS +/* wait for a message with timers disabled (e.g. pass a timer-check trigger into tcpip_thread) */ +#define TCPIP_MBOX_FETCH(mbox, msg) sys_mbox_fetch(mbox, msg) +#else /* !LWIP_TIMERS */ +/* wait for a message, timeouts are processed while waiting */ +#define TCPIP_MBOX_FETCH(mbox, msg) tcpip_timeouts_mbox_fetch(mbox, msg) +/** + * Wait (forever) for a message to arrive in an mbox. + * While waiting, timeouts are processed. + * + * @param mbox the mbox to fetch the message from + * @param msg the place to store the message + */ +static void +tcpip_timeouts_mbox_fetch(sys_mbox_t *mbox, void **msg) +{ + u32_t sleeptime, res; + +again: + LWIP_ASSERT_CORE_LOCKED(); + + sleeptime = sys_timeouts_sleeptime(); + if (sleeptime == SYS_TIMEOUTS_SLEEPTIME_INFINITE) { + UNLOCK_TCPIP_CORE(); + sys_arch_mbox_fetch(mbox, msg, 0); + LOCK_TCPIP_CORE(); + return; + } else if (sleeptime == 0) { + sys_check_timeouts(); + /* We try again to fetch a message from the mbox. */ + goto again; + } + + UNLOCK_TCPIP_CORE(); + res = sys_arch_mbox_fetch(mbox, msg, sleeptime); + LOCK_TCPIP_CORE(); + if (res == SYS_ARCH_TIMEOUT) { + /* If a SYS_ARCH_TIMEOUT value is returned, a timeout occurred + before a message could be fetched. */ + sys_check_timeouts(); + /* We try again to fetch a message from the mbox. */ + goto again; + } +} +#endif /* !LWIP_TIMERS */ + +/** + * The main lwIP thread. This thread has exclusive access to lwIP core functions + * (unless access to them is not locked). Other threads communicate with this + * thread using message boxes. + * + * It also starts all the timers to make sure they are running in the right + * thread context. + * + * @param arg unused argument + */ +static void +tcpip_thread(void *arg) +{ + struct tcpip_msg *msg; + LWIP_UNUSED_ARG(arg); + + LWIP_MARK_TCPIP_THREAD(); + + LOCK_TCPIP_CORE(); + if (tcpip_init_done != NULL) { + tcpip_init_done(tcpip_init_done_arg); + } + + while (1) { /* MAIN Loop */ + LWIP_TCPIP_THREAD_ALIVE(); + /* wait for a message, timeouts are processed while waiting */ + TCPIP_MBOX_FETCH(&tcpip_mbox, (void **)&msg); + if (msg == NULL) { + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: NULL\n")); + LWIP_ASSERT("tcpip_thread: invalid message", 0); + continue; + } + tcpip_thread_handle_msg(msg); + } +} + +/* Handle a single tcpip_msg + * This is in its own function for access by tests only. + */ +static void +tcpip_thread_handle_msg(struct tcpip_msg *msg) +{ + switch (msg->type) { +#if !LWIP_TCPIP_CORE_LOCKING + case TCPIP_MSG_API: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API message %p\n", (void *)msg)); + msg->msg.api_msg.function(msg->msg.api_msg.msg); + break; + case TCPIP_MSG_API_CALL: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: API CALL message %p\n", (void *)msg)); + msg->msg.api_call.arg->err = msg->msg.api_call.function(msg->msg.api_call.arg); + sys_sem_signal(msg->msg.api_call.sem); + break; +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + +#if !LWIP_TCPIP_CORE_LOCKING_INPUT + case TCPIP_MSG_INPKT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: PACKET %p\n", (void *)msg)); + if (msg->msg.inp.input_fn(msg->msg.inp.p, msg->msg.inp.netif) != ERR_OK) { + pbuf_free(msg->msg.inp.p); + } + memp_free(MEMP_TCPIP_MSG_INPKT, msg); + break; +#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ + +#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS + case TCPIP_MSG_TIMEOUT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: TIMEOUT %p\n", (void *)msg)); + sys_timeout(msg->msg.tmo.msecs, msg->msg.tmo.h, msg->msg.tmo.arg); + memp_free(MEMP_TCPIP_MSG_API, msg); + break; + case TCPIP_MSG_UNTIMEOUT: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: UNTIMEOUT %p\n", (void *)msg)); + sys_untimeout(msg->msg.tmo.h, msg->msg.tmo.arg); + memp_free(MEMP_TCPIP_MSG_API, msg); + break; +#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ + + case TCPIP_MSG_CALLBACK: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK %p\n", (void *)msg)); + msg->msg.cb.function(msg->msg.cb.ctx); + memp_free(MEMP_TCPIP_MSG_API, msg); + break; + + case TCPIP_MSG_CALLBACK_STATIC: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: CALLBACK_STATIC %p\n", (void *)msg)); + msg->msg.cb.function(msg->msg.cb.ctx); + break; + + default: + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_thread: invalid message: %d\n", msg->type)); + LWIP_ASSERT("tcpip_thread: invalid message", 0); + break; + } +} + +#ifdef TCPIP_THREAD_TEST +/** Work on queued items in single-threaded test mode */ +int +tcpip_thread_poll_one(void) +{ + int ret = 0; + struct tcpip_msg *msg; + + if (sys_arch_mbox_tryfetch(&tcpip_mbox, (void **)&msg) != SYS_ARCH_TIMEOUT) { + LOCK_TCPIP_CORE(); + if (msg != NULL) { + tcpip_thread_handle_msg(msg); + ret = 1; + } + UNLOCK_TCPIP_CORE(); + } + return ret; +} +#endif + +/** + * Pass a received packet to tcpip_thread for input processing + * + * @param p the received packet + * @param inp the network interface on which the packet was received + * @param input_fn input function to call + */ +err_t +tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn) +{ +#if LWIP_TCPIP_CORE_LOCKING_INPUT + err_t ret; + LWIP_DEBUGF(TCPIP_DEBUG, ("tcpip_inpkt: PACKET %p/%p\n", (void *)p, (void *)inp)); + LOCK_TCPIP_CORE(); + ret = input_fn(p, inp); + UNLOCK_TCPIP_CORE(); + return ret; +#else /* LWIP_TCPIP_CORE_LOCKING_INPUT */ + struct tcpip_msg *msg; + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_INPKT); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_INPKT; + msg->msg.inp.p = p; + msg->msg.inp.netif = inp; + msg->msg.inp.input_fn = input_fn; + if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) { + memp_free(MEMP_TCPIP_MSG_INPKT, msg); + return ERR_MEM; + } + return ERR_OK; +#endif /* LWIP_TCPIP_CORE_LOCKING_INPUT */ +} + +/** + * @ingroup lwip_os + * Pass a received packet to tcpip_thread for input processing with + * ethernet_input or ip_input. Don't call directly, pass to netif_add() + * and call netif->input(). + * + * @param p the received packet, p->payload pointing to the Ethernet header or + * to an IP header (if inp doesn't have NETIF_FLAG_ETHARP or + * NETIF_FLAG_ETHERNET flags) + * @param inp the network interface on which the packet was received + */ +err_t +tcpip_input(struct pbuf *p, struct netif *inp) +{ +#if LWIP_ETHERNET + if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { + return tcpip_inpkt(p, inp, ethernet_input); + } else +#endif /* LWIP_ETHERNET */ + return tcpip_inpkt(p, inp, ip_input); +} + +/** + * @ingroup lwip_os + * Call a specific function in the thread context of + * tcpip_thread for easy access synchronization. + * A function called in that way may access lwIP core code + * without fearing concurrent access. + * Blocks until the request is posted. + * Must not be called from interrupt context! + * + * @param function the function to call + * @param ctx parameter passed to f + * @return ERR_OK if the function was called, another err_t if not + * + * @see tcpip_try_callback + */ +err_t +tcpip_callback(tcpip_callback_fn function, void *ctx) +{ + struct tcpip_msg *msg; + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_CALLBACK; + msg->msg.cb.function = function; + msg->msg.cb.ctx = ctx; + + sys_mbox_post(&tcpip_mbox, msg); + return ERR_OK; +} + +/** + * @ingroup lwip_os + * Call a specific function in the thread context of + * tcpip_thread for easy access synchronization. + * A function called in that way may access lwIP core code + * without fearing concurrent access. + * Does NOT block when the request cannot be posted because the + * tcpip_mbox is full, but returns ERR_MEM instead. + * Can be called from interrupt context. + * + * @param function the function to call + * @param ctx parameter passed to f + * @return ERR_OK if the function was called, another err_t if not + * + * @see tcpip_callback + */ +err_t +tcpip_try_callback(tcpip_callback_fn function, void *ctx) +{ + struct tcpip_msg *msg; + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_CALLBACK; + msg->msg.cb.function = function; + msg->msg.cb.ctx = ctx; + + if (sys_mbox_trypost(&tcpip_mbox, msg) != ERR_OK) { + memp_free(MEMP_TCPIP_MSG_API, msg); + return ERR_MEM; + } + return ERR_OK; +} + +#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS +/** + * call sys_timeout in tcpip_thread + * + * @param msecs time in milliseconds for timeout + * @param h function to be called on timeout + * @param arg argument to pass to timeout function h + * @return ERR_MEM on memory error, ERR_OK otherwise + */ +err_t +tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg) +{ + struct tcpip_msg *msg; + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_TIMEOUT; + msg->msg.tmo.msecs = msecs; + msg->msg.tmo.h = h; + msg->msg.tmo.arg = arg; + sys_mbox_post(&tcpip_mbox, msg); + return ERR_OK; +} + +/** + * call sys_untimeout in tcpip_thread + * + * @param h function to be called on timeout + * @param arg argument to pass to timeout function h + * @return ERR_MEM on memory error, ERR_OK otherwise + */ +err_t +tcpip_untimeout(sys_timeout_handler h, void *arg) +{ + struct tcpip_msg *msg; + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + + msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return ERR_MEM; + } + + msg->type = TCPIP_MSG_UNTIMEOUT; + msg->msg.tmo.h = h; + msg->msg.tmo.arg = arg; + sys_mbox_post(&tcpip_mbox, msg); + return ERR_OK; +} +#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ + + +/** + * Sends a message to TCPIP thread to call a function. Caller thread blocks on + * on a provided semaphore, which ist NOT automatically signalled by TCPIP thread, + * this has to be done by the user. + * It is recommended to use LWIP_TCPIP_CORE_LOCKING since this is the way + * with least runtime overhead. + * + * @param fn function to be called from TCPIP thread + * @param apimsg argument to API function + * @param sem semaphore to wait on + * @return ERR_OK if the function was called, another err_t if not + */ +err_t +tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t *sem) +{ +#if LWIP_TCPIP_CORE_LOCKING + LWIP_UNUSED_ARG(sem); + LOCK_TCPIP_CORE(); + fn(apimsg); + UNLOCK_TCPIP_CORE(); + return ERR_OK; +#else /* LWIP_TCPIP_CORE_LOCKING */ + TCPIP_MSG_VAR_DECLARE(msg); + + LWIP_ASSERT("semaphore not initialized", sys_sem_valid(sem)); + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + + TCPIP_MSG_VAR_ALLOC(msg); + TCPIP_MSG_VAR_REF(msg).type = TCPIP_MSG_API; + TCPIP_MSG_VAR_REF(msg).msg.api_msg.function = fn; + TCPIP_MSG_VAR_REF(msg).msg.api_msg.msg = apimsg; + sys_mbox_post(&tcpip_mbox, &TCPIP_MSG_VAR_REF(msg)); + sys_arch_sem_wait(sem, 0); + TCPIP_MSG_VAR_FREE(msg); + return ERR_OK; +#endif /* LWIP_TCPIP_CORE_LOCKING */ +} + +/** + * Synchronously calls function in TCPIP thread and waits for its completion. + * It is recommended to use LWIP_TCPIP_CORE_LOCKING (preferred) or + * LWIP_NETCONN_SEM_PER_THREAD. + * If not, a semaphore is created and destroyed on every call which is usually + * an expensive/slow operation. + * @param fn Function to call + * @param call Call parameters + * @return Return value from tcpip_api_call_fn + */ +err_t +tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call) +{ +#if LWIP_TCPIP_CORE_LOCKING + err_t err; + LOCK_TCPIP_CORE(); + err = fn(call); + UNLOCK_TCPIP_CORE(); + return err; +#else /* LWIP_TCPIP_CORE_LOCKING */ + TCPIP_MSG_VAR_DECLARE(msg); + +#if !LWIP_NETCONN_SEM_PER_THREAD + err_t err = sys_sem_new(&call->sem, 0); + if (err != ERR_OK) { + return err; + } +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + + TCPIP_MSG_VAR_ALLOC(msg); + TCPIP_MSG_VAR_REF(msg).type = TCPIP_MSG_API_CALL; + TCPIP_MSG_VAR_REF(msg).msg.api_call.arg = call; + TCPIP_MSG_VAR_REF(msg).msg.api_call.function = fn; +#if LWIP_NETCONN_SEM_PER_THREAD + TCPIP_MSG_VAR_REF(msg).msg.api_call.sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + TCPIP_MSG_VAR_REF(msg).msg.api_call.sem = &call->sem; +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + sys_mbox_post(&tcpip_mbox, &TCPIP_MSG_VAR_REF(msg)); + sys_arch_sem_wait(TCPIP_MSG_VAR_REF(msg).msg.api_call.sem, 0); + TCPIP_MSG_VAR_FREE(msg); + +#if !LWIP_NETCONN_SEM_PER_THREAD + sys_sem_free(&call->sem); +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + return call->err; +#endif /* LWIP_TCPIP_CORE_LOCKING */ +} + +/** + * @ingroup lwip_os + * Allocate a structure for a static callback message and initialize it. + * The message has a special type such that lwIP never frees it. + * This is intended to be used to send "static" messages from interrupt context, + * e.g. the message is allocated once and posted several times from an IRQ + * using tcpip_callbackmsg_trycallback(). + * Example usage: Trigger execution of an ethernet IRQ DPC routine in lwIP thread context. + * + * @param function the function to call + * @param ctx parameter passed to function + * @return a struct pointer to pass to tcpip_callbackmsg_trycallback(). + * + * @see tcpip_callbackmsg_trycallback() + * @see tcpip_callbackmsg_delete() + */ +struct tcpip_callback_msg * +tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx) +{ + struct tcpip_msg *msg = (struct tcpip_msg *)memp_malloc(MEMP_TCPIP_MSG_API); + if (msg == NULL) { + return NULL; + } + msg->type = TCPIP_MSG_CALLBACK_STATIC; + msg->msg.cb.function = function; + msg->msg.cb.ctx = ctx; + return (struct tcpip_callback_msg *)msg; +} + +/** + * @ingroup lwip_os + * Free a callback message allocated by tcpip_callbackmsg_new(). + * + * @param msg the message to free + * + * @see tcpip_callbackmsg_new() + */ +void +tcpip_callbackmsg_delete(struct tcpip_callback_msg *msg) +{ + memp_free(MEMP_TCPIP_MSG_API, msg); +} + +/** + * @ingroup lwip_os + * Try to post a callback-message to the tcpip_thread tcpip_mbox. + * + * @param msg pointer to the message to post + * @return sys_mbox_trypost() return code + * + * @see tcpip_callbackmsg_new() + */ +err_t +tcpip_callbackmsg_trycallback(struct tcpip_callback_msg *msg) +{ + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + return sys_mbox_trypost(&tcpip_mbox, msg); +} + +/** + * @ingroup lwip_os + * Try to post a callback-message to the tcpip_thread mbox. + * Same as @ref tcpip_callbackmsg_trycallback but calls sys_mbox_trypost_fromisr(), + * mainly to help FreeRTOS, where calls differ between task level and ISR level. + * + * @param msg pointer to the message to post + * @return sys_mbox_trypost_fromisr() return code (without change, so this + * knowledge can be used to e.g. propagate "bool needs_scheduling") + * + * @see tcpip_callbackmsg_new() + */ +err_t +tcpip_callbackmsg_trycallback_fromisr(struct tcpip_callback_msg *msg) +{ + LWIP_ASSERT("Invalid mbox", sys_mbox_valid_val(tcpip_mbox)); + return sys_mbox_trypost_fromisr(&tcpip_mbox, msg); +} + +/** + * @ingroup lwip_os + * Initialize this module: + * - initialize all sub modules + * - start the tcpip_thread + * + * @param initfunc a function to call when tcpip_thread is running and finished initializing + * @param arg argument to pass to initfunc + */ +void +tcpip_init(tcpip_init_done_fn initfunc, void *arg) +{ + lwip_init(); + + tcpip_init_done = initfunc; + tcpip_init_done_arg = arg; + if (sys_mbox_new(&tcpip_mbox, TCPIP_MBOX_SIZE) != ERR_OK) { + LWIP_ASSERT("failed to create tcpip_thread mbox", 0); + } +#if LWIP_TCPIP_CORE_LOCKING + if (sys_mutex_new(&lock_tcpip_core) != ERR_OK) { + LWIP_ASSERT("failed to create lock_tcpip_core", 0); + } +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sys_thread_new(TCPIP_THREAD_NAME, tcpip_thread, NULL, TCPIP_THREAD_STACKSIZE, TCPIP_THREAD_PRIO); +} + +/** + * Simple callback function used with tcpip_callback to free a pbuf + * (pbuf_free has a wrong signature for tcpip_callback) + * + * @param p The pbuf (chain) to be dereferenced. + */ +static void +pbuf_free_int(void *p) +{ + struct pbuf *q = (struct pbuf *)p; + pbuf_free(q); +} + +/** + * A simple wrapper function that allows you to free a pbuf from interrupt context. + * + * @param p The pbuf (chain) to be dereferenced. + * @return ERR_OK if callback could be enqueued, an err_t if not + */ +err_t +pbuf_free_callback(struct pbuf *p) +{ + return tcpip_try_callback(pbuf_free_int, p); +} + +/** + * A simple wrapper function that allows you to free heap memory from + * interrupt context. + * + * @param m the heap memory to free + * @return ERR_OK if callback could be enqueued, an err_t if not + */ +err_t +mem_free_callback(void *m) +{ + return tcpip_try_callback(mem_free, m); +} + +#endif /* !NO_SYS */ diff --git a/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c b/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c new file mode 100644 index 0000000..269f4a4 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/apps/mqtt/mqtt.c @@ -0,0 +1,1463 @@ +/** + * @file + * MQTT client + * + * @defgroup mqtt MQTT client + * @ingroup apps + * @verbinclude mqtt_client.txt + */ + +/* + * Copyright (c) 2016 Erik Andersson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack + * + * Author: Erik Andersson + * + * + * @todo: + * - Handle large outgoing payloads for PUBLISH messages + * - Fix restriction of a single topic in each (UN)SUBSCRIBE message (protocol has support for multiple topics) + * - Add support for legacy MQTT protocol version + * + * Please coordinate changes and requests with Erik Andersson + * Erik Andersson + * + */ +#include "lwip/apps/mqtt.h" +#include "lwip/apps/mqtt_priv.h" +#include "lwip/timeouts.h" +#include "lwip/ip_addr.h" +#include "lwip/mem.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/altcp.h" +#include "lwip/altcp_tcp.h" +#include "lwip/altcp_tls.h" +#include + +#if LWIP_TCP && LWIP_CALLBACK_API + +/** + * MQTT_DEBUG: Default is off. + */ +#if !defined MQTT_DEBUG || defined __DOXYGEN__ +#define MQTT_DEBUG LWIP_DBG_OFF +#endif + +#define MQTT_DEBUG_TRACE (MQTT_DEBUG | LWIP_DBG_TRACE) +#define MQTT_DEBUG_STATE (MQTT_DEBUG | LWIP_DBG_STATE) +#define MQTT_DEBUG_WARN (MQTT_DEBUG | LWIP_DBG_LEVEL_WARNING) +#define MQTT_DEBUG_WARN_STATE (MQTT_DEBUG | LWIP_DBG_LEVEL_WARNING | LWIP_DBG_STATE) +#define MQTT_DEBUG_SERIOUS (MQTT_DEBUG | LWIP_DBG_LEVEL_SERIOUS) + + + +/** + * MQTT client connection states + */ +enum { + TCP_DISCONNECTED, + TCP_CONNECTING, + MQTT_CONNECTING, + MQTT_CONNECTED +}; + +/** + * MQTT control message types + */ +enum mqtt_message_type { + MQTT_MSG_TYPE_CONNECT = 1, + MQTT_MSG_TYPE_CONNACK = 2, + MQTT_MSG_TYPE_PUBLISH = 3, + MQTT_MSG_TYPE_PUBACK = 4, + MQTT_MSG_TYPE_PUBREC = 5, + MQTT_MSG_TYPE_PUBREL = 6, + MQTT_MSG_TYPE_PUBCOMP = 7, + MQTT_MSG_TYPE_SUBSCRIBE = 8, + MQTT_MSG_TYPE_SUBACK = 9, + MQTT_MSG_TYPE_UNSUBSCRIBE = 10, + MQTT_MSG_TYPE_UNSUBACK = 11, + MQTT_MSG_TYPE_PINGREQ = 12, + MQTT_MSG_TYPE_PINGRESP = 13, + MQTT_MSG_TYPE_DISCONNECT = 14 +}; + +/** Helpers to extract control packet type and qos from first byte in fixed header */ +#define MQTT_CTL_PACKET_TYPE(fixed_hdr_byte0) ((fixed_hdr_byte0 & 0xf0) >> 4) +#define MQTT_CTL_PACKET_QOS(fixed_hdr_byte0) ((fixed_hdr_byte0 & 0x6) >> 1) + +/** + * MQTT connect flags, only used in CONNECT message + */ +enum mqtt_connect_flag { + MQTT_CONNECT_FLAG_USERNAME = 1 << 7, + MQTT_CONNECT_FLAG_PASSWORD = 1 << 6, + MQTT_CONNECT_FLAG_WILL_RETAIN = 1 << 5, + MQTT_CONNECT_FLAG_WILL = 1 << 2, + MQTT_CONNECT_FLAG_CLEAN_SESSION = 1 << 1 +}; + + +static void mqtt_cyclic_timer(void *arg); + +#if defined(LWIP_DEBUG) +static const char *const mqtt_message_type_str[15] = { + "UNDEFINED", + "CONNECT", + "CONNACK", + "PUBLISH", + "PUBACK", + "PUBREC", + "PUBREL", + "PUBCOMP", + "SUBSCRIBE", + "SUBACK", + "UNSUBSCRIBE", + "UNSUBACK", + "PINGREQ", + "PINGRESP", + "DISCONNECT" +}; + +/** + * Message type value to string + * @param msg_type see enum mqtt_message_type + * + * @return Control message type text string + */ +static const char * +mqtt_msg_type_to_str(u8_t msg_type) +{ + if (msg_type >= LWIP_ARRAYSIZE(mqtt_message_type_str)) { + msg_type = 0; + } + return mqtt_message_type_str[msg_type]; +} + +#endif + + +/** + * Generate MQTT packet identifier + * @param client MQTT client + * @return New packet identifier, range 1 to 65535 + */ +static u16_t +msg_generate_packet_id(mqtt_client_t *client) +{ + client->pkt_id_seq++; + if (client->pkt_id_seq == 0) { + client->pkt_id_seq++; + } + return client->pkt_id_seq; +} + +/*--------------------------------------------------------------------------------------------------------------------- */ +/* Output ring buffer */ + +/** Add single item to ring buffer */ +static void +mqtt_ringbuf_put(struct mqtt_ringbuf_t *rb, u8_t item) +{ + rb->buf[rb->put] = item; + rb->put++; + if (rb->put >= MQTT_OUTPUT_RINGBUF_SIZE) { + rb->put = 0; + } +} + +/** Return pointer to ring buffer get position */ +static u8_t * +mqtt_ringbuf_get_ptr(struct mqtt_ringbuf_t *rb) +{ + return &rb->buf[rb->get]; +} + +static void +mqtt_ringbuf_advance_get_idx(struct mqtt_ringbuf_t *rb, u16_t len) +{ + LWIP_ASSERT("mqtt_ringbuf_advance_get_idx: len < MQTT_OUTPUT_RINGBUF_SIZE", len < MQTT_OUTPUT_RINGBUF_SIZE); + + rb->get += len; + if (rb->get >= MQTT_OUTPUT_RINGBUF_SIZE) { + rb->get = rb->get - MQTT_OUTPUT_RINGBUF_SIZE; + } +} + +/** Return number of bytes in ring buffer */ +static u16_t +mqtt_ringbuf_len(struct mqtt_ringbuf_t *rb) +{ + u32_t len = rb->put - rb->get; + if (len > 0xFFFF) { + len += MQTT_OUTPUT_RINGBUF_SIZE; + } + return (u16_t)len; +} + +/** Return number of bytes free in ring buffer */ +#define mqtt_ringbuf_free(rb) (MQTT_OUTPUT_RINGBUF_SIZE - mqtt_ringbuf_len(rb)) + +/** Return number of bytes possible to read without wrapping around */ +#define mqtt_ringbuf_linear_read_length(rb) LWIP_MIN(mqtt_ringbuf_len(rb), (MQTT_OUTPUT_RINGBUF_SIZE - (rb)->get)) + +/** + * Try send as many bytes as possible from output ring buffer + * @param rb Output ring buffer + * @param tpcb TCP connection handle + */ +static void +mqtt_output_send(struct mqtt_ringbuf_t *rb, struct altcp_pcb *tpcb) +{ + err_t err; + u8_t wrap = 0; + u16_t ringbuf_lin_len = mqtt_ringbuf_linear_read_length(rb); + u16_t send_len = altcp_sndbuf(tpcb); + LWIP_ASSERT("mqtt_output_send: tpcb != NULL", tpcb != NULL); + + if (send_len == 0 || ringbuf_lin_len == 0) { + return; + } + + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_output_send: tcp_sndbuf: %d bytes, ringbuf_linear_available: %d, get %d, put %d\n", + send_len, ringbuf_lin_len, rb->get, rb->put)); + + if (send_len > ringbuf_lin_len) { + /* Space in TCP output buffer is larger than available in ring buffer linear portion */ + send_len = ringbuf_lin_len; + /* Wrap around if more data in ring buffer after linear portion */ + wrap = (mqtt_ringbuf_len(rb) > ringbuf_lin_len); + } + err = altcp_write(tpcb, mqtt_ringbuf_get_ptr(rb), send_len, TCP_WRITE_FLAG_COPY | (wrap ? TCP_WRITE_FLAG_MORE : 0)); + if ((err == ERR_OK) && wrap) { + mqtt_ringbuf_advance_get_idx(rb, send_len); + /* Use the lesser one of ring buffer linear length and TCP send buffer size */ + send_len = LWIP_MIN(altcp_sndbuf(tpcb), mqtt_ringbuf_linear_read_length(rb)); + err = altcp_write(tpcb, mqtt_ringbuf_get_ptr(rb), send_len, TCP_WRITE_FLAG_COPY); + } + + if (err == ERR_OK) { + mqtt_ringbuf_advance_get_idx(rb, send_len); + /* Flush */ + altcp_output(tpcb); + } else { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_output_send: Send failed with err %d (\"%s\")\n", err, lwip_strerr(err))); + } +} + + + +/*--------------------------------------------------------------------------------------------------------------------- */ +/* Request queue */ + +/** + * Create request item + * @param r_objs Pointer to request objects + * @param r_objs_len Number of array entries + * @param pkt_id Packet identifier of request + * @param cb Packet callback to call when requests lifetime ends + * @param arg Parameter following callback + * @return Request or NULL if failed to create + */ +static struct mqtt_request_t * +mqtt_create_request(struct mqtt_request_t *r_objs, size_t r_objs_len, u16_t pkt_id, mqtt_request_cb_t cb, void *arg) +{ + struct mqtt_request_t *r = NULL; + u8_t n; + LWIP_ASSERT("mqtt_create_request: r_objs != NULL", r_objs != NULL); + for (n = 0; n < r_objs_len; n++) { + /* Item point to itself if not in use */ + if (r_objs[n].next == &r_objs[n]) { + r = &r_objs[n]; + r->next = NULL; + r->cb = cb; + r->arg = arg; + r->pkt_id = pkt_id; + break; + } + } + return r; +} + + +/** + * Append request to pending request queue + * @param tail Pointer to request queue tail pointer + * @param r Request to append + */ +static void +mqtt_append_request(struct mqtt_request_t **tail, struct mqtt_request_t *r) +{ + struct mqtt_request_t *head = NULL; + s16_t time_before = 0; + struct mqtt_request_t *iter; + + LWIP_ASSERT("mqtt_append_request: tail != NULL", tail != NULL); + + /* Iterate trough queue to find head, and count total timeout time */ + for (iter = *tail; iter != NULL; iter = iter->next) { + time_before += iter->timeout_diff; + head = iter; + } + + LWIP_ASSERT("mqtt_append_request: time_before <= MQTT_REQ_TIMEOUT", time_before <= MQTT_REQ_TIMEOUT); + r->timeout_diff = MQTT_REQ_TIMEOUT - time_before; + if (head == NULL) { + *tail = r; + } else { + head->next = r; + } +} + + +/** + * Delete request item + * @param r Request item to delete + */ +static void +mqtt_delete_request(struct mqtt_request_t *r) +{ + if (r != NULL) { + r->next = r; + } +} + +/** + * Remove a request item with a specific packet identifier from request queue + * @param tail Pointer to request queue tail pointer + * @param pkt_id Packet identifier of request to take + * @return Request item if found, NULL if not + */ +static struct mqtt_request_t * +mqtt_take_request(struct mqtt_request_t **tail, u16_t pkt_id) +{ + struct mqtt_request_t *iter = NULL, *prev = NULL; + LWIP_ASSERT("mqtt_take_request: tail != NULL", tail != NULL); + /* Search all request for pkt_id */ + for (iter = *tail; iter != NULL; iter = iter->next) { + if (iter->pkt_id == pkt_id) { + break; + } + prev = iter; + } + + /* If request was found */ + if (iter != NULL) { + /* unchain */ + if (prev == NULL) { + *tail = iter->next; + } else { + prev->next = iter->next; + } + /* If exists, add remaining timeout time for the request to next */ + if (iter->next != NULL) { + iter->next->timeout_diff += iter->timeout_diff; + } + iter->next = NULL; + } + return iter; +} + +/** + * Handle requests timeout + * @param tail Pointer to request queue tail pointer + * @param t Time since last call in seconds + */ +static void +mqtt_request_time_elapsed(struct mqtt_request_t **tail, u8_t t) +{ + struct mqtt_request_t *r; + LWIP_ASSERT("mqtt_request_time_elapsed: tail != NULL", tail != NULL); + r = *tail; + while (t > 0 && r != NULL) { + if (t >= r->timeout_diff) { + t -= (u8_t)r->timeout_diff; + /* Unchain */ + *tail = r->next; + /* Notify upper layer about timeout */ + if (r->cb != NULL) { + r->cb(r->arg, ERR_TIMEOUT); + } + mqtt_delete_request(r); + /* Tail might be be modified in callback, so re-read it in every iteration */ + r = *(struct mqtt_request_t *const volatile *)tail; + } else { + r->timeout_diff -= t; + t = 0; + } + } +} + +/** + * Free all request items + * @param tail Pointer to request queue tail pointer + */ +static void +mqtt_clear_requests(struct mqtt_request_t **tail) +{ + struct mqtt_request_t *iter, *next; + LWIP_ASSERT("mqtt_clear_requests: tail != NULL", tail != NULL); + for (iter = *tail; iter != NULL; iter = next) { + next = iter->next; + mqtt_delete_request(iter); + } + *tail = NULL; +} +/** + * Initialize all request items + * @param r_objs Pointer to request objects + * @param r_objs_len Number of array entries + */ +static void +mqtt_init_requests(struct mqtt_request_t *r_objs, size_t r_objs_len) +{ + u8_t n; + LWIP_ASSERT("mqtt_init_requests: r_objs != NULL", r_objs != NULL); + for (n = 0; n < r_objs_len; n++) { + /* Item pointing to itself indicates unused */ + r_objs[n].next = &r_objs[n]; + } +} + +/*--------------------------------------------------------------------------------------------------------------------- */ +/* Output message build helpers */ + + +static void +mqtt_output_append_u8(struct mqtt_ringbuf_t *rb, u8_t value) +{ + mqtt_ringbuf_put(rb, value); +} + +static +void mqtt_output_append_u16(struct mqtt_ringbuf_t *rb, u16_t value) +{ + mqtt_ringbuf_put(rb, value >> 8); + mqtt_ringbuf_put(rb, value & 0xff); +} + +static void +mqtt_output_append_buf(struct mqtt_ringbuf_t *rb, const void *data, u16_t length) +{ + u16_t n; + for (n = 0; n < length; n++) { + mqtt_ringbuf_put(rb, ((const u8_t *)data)[n]); + } +} + +static void +mqtt_output_append_string(struct mqtt_ringbuf_t *rb, const char *str, u16_t length) +{ + u16_t n; + mqtt_ringbuf_put(rb, length >> 8); + mqtt_ringbuf_put(rb, length & 0xff); + for (n = 0; n < length; n++) { + mqtt_ringbuf_put(rb, str[n]); + } +} + +/** + * Append fixed header + * @param rb Output ring buffer + * @param msg_type see enum mqtt_message_type + * @param fdup MQTT DUP flag + * @param fqos MQTT QoS field + * @param fretain MQTT retain flag + * @param r_length Remaining length after fixed header + */ + +static void +mqtt_output_append_fixed_header(struct mqtt_ringbuf_t *rb, u8_t msg_type, u8_t fdup, + u8_t fqos, u8_t fretain, u16_t r_length) +{ + /* Start with control byte */ + mqtt_output_append_u8(rb, (((msg_type & 0x0f) << 4) | ((fdup & 1) << 3) | ((fqos & 3) << 1) | (fretain & 1))); + /* Encode remaining length field */ + do { + mqtt_output_append_u8(rb, (r_length & 0x7f) | (r_length >= 128 ? 0x80 : 0)); + r_length >>= 7; + } while (r_length > 0); +} + + +/** + * Check output buffer space + * @param rb Output ring buffer + * @param r_length Remaining length after fixed header + * @return 1 if message will fit, 0 if not enough buffer space + */ +static u8_t +mqtt_output_check_space(struct mqtt_ringbuf_t *rb, u16_t r_length) +{ + /* Start with length of type byte + remaining length */ + u16_t total_len = 1 + r_length; + + LWIP_ASSERT("mqtt_output_check_space: rb != NULL", rb != NULL); + + /* Calculate number of required bytes to contain the remaining bytes field and add to total*/ + do { + total_len++; + r_length >>= 7; + } while (r_length > 0); + + return (total_len <= mqtt_ringbuf_free(rb)); +} + + +/** + * Close connection to server + * @param client MQTT client + * @param reason Reason for disconnection + */ +static void +mqtt_close(mqtt_client_t *client, mqtt_connection_status_t reason) +{ + LWIP_ASSERT("mqtt_close: client != NULL", client != NULL); + + /* Bring down TCP connection if not already done */ + if (client->conn != NULL) { + err_t res; + altcp_recv(client->conn, NULL); + altcp_err(client->conn, NULL); + altcp_sent(client->conn, NULL); + res = altcp_close(client->conn); + if (res != ERR_OK) { + altcp_abort(client->conn); + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_close: Close err=%s\n", lwip_strerr(res))); + } + client->conn = NULL; + } + + /* Remove all pending requests */ + mqtt_clear_requests(&client->pend_req_queue); + /* Stop cyclic timer */ + sys_untimeout(mqtt_cyclic_timer, client); + + /* Notify upper layer of disconnection if changed state */ + if (client->conn_state != TCP_DISCONNECTED) { + + client->conn_state = TCP_DISCONNECTED; + if (client->connect_cb != NULL) { + client->connect_cb(client, client->connect_arg, reason); + } + } +} + + +/** + * Interval timer, called every MQTT_CYCLIC_TIMER_INTERVAL seconds in MQTT_CONNECTING and MQTT_CONNECTED states + * @param arg MQTT client + */ +static void +mqtt_cyclic_timer(void *arg) +{ + u8_t restart_timer = 1; + mqtt_client_t *client = (mqtt_client_t *)arg; + LWIP_ASSERT("mqtt_cyclic_timer: client != NULL", client != NULL); + + if (client->conn_state == MQTT_CONNECTING) { + client->cyclic_tick++; + if ((client->cyclic_tick * MQTT_CYCLIC_TIMER_INTERVAL) >= MQTT_CONNECT_TIMOUT) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_cyclic_timer: CONNECT attempt to server timed out\n")); + /* Disconnect TCP */ + mqtt_close(client, MQTT_CONNECT_TIMEOUT); + restart_timer = 0; + } + } else if (client->conn_state == MQTT_CONNECTED) { + /* Handle timeout for pending requests */ + mqtt_request_time_elapsed(&client->pend_req_queue, MQTT_CYCLIC_TIMER_INTERVAL); + + /* keep_alive > 0 means keep alive functionality shall be used */ + if (client->keep_alive > 0) { + + client->server_watchdog++; + /* If reception from server has been idle for 1.5*keep_alive time, server is considered unresponsive */ + if ((client->server_watchdog * MQTT_CYCLIC_TIMER_INTERVAL) > (client->keep_alive + client->keep_alive / 2)) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_cyclic_timer: Server incoming keep-alive timeout\n")); + mqtt_close(client, MQTT_CONNECT_TIMEOUT); + restart_timer = 0; + } + + /* If time for a keep alive message to be sent, transmission has been idle for keep_alive time */ + if ((client->cyclic_tick * MQTT_CYCLIC_TIMER_INTERVAL) >= client->keep_alive) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_cyclic_timer: Sending keep-alive message to server\n")); + if (mqtt_output_check_space(&client->output, 0) != 0) { + mqtt_output_append_fixed_header(&client->output, MQTT_MSG_TYPE_PINGREQ, 0, 0, 0, 0); + client->cyclic_tick = 0; + } + } else { + client->cyclic_tick++; + } + } + } else { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_cyclic_timer: Timer should not be running in state %d\n", client->conn_state)); + restart_timer = 0; + } + if (restart_timer) { + sys_timeout(MQTT_CYCLIC_TIMER_INTERVAL * 1000, mqtt_cyclic_timer, arg); + } +} + + +/** + * Send PUBACK, PUBREC or PUBREL response message + * @param client MQTT client + * @param msg PUBACK, PUBREC or PUBREL + * @param pkt_id Packet identifier + * @param qos QoS value + * @return ERR_OK if successful, ERR_MEM if out of memory + */ +static err_t +pub_ack_rec_rel_response(mqtt_client_t *client, u8_t msg, u16_t pkt_id, u8_t qos) +{ + err_t err = ERR_OK; + if (mqtt_output_check_space(&client->output, 2)) { + mqtt_output_append_fixed_header(&client->output, msg, 0, qos, 0, 2); + mqtt_output_append_u16(&client->output, pkt_id); + mqtt_output_send(&client->output, client->conn); + } else { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("pub_ack_rec_rel_response: OOM creating response: %s with pkt_id: %d\n", + mqtt_msg_type_to_str(msg), pkt_id)); + err = ERR_MEM; + } + return err; +} + +/** + * Subscribe response from server + * @param r Matching request + * @param result Result code from server + */ +static void +mqtt_incomming_suback(struct mqtt_request_t *r, u8_t result) +{ + if (r->cb != NULL) { + r->cb(r->arg, result < 3 ? ERR_OK : ERR_ABRT); + } +} + + +/** + * Complete MQTT message received or buffer full + * @param client MQTT client + * @param fixed_hdr_idx header index + * @param length length received part + * @param remaining_length Remaining length of complete message + */ +static mqtt_connection_status_t +mqtt_message_received(mqtt_client_t *client, u8_t fixed_hdr_idx, u16_t length, u32_t remaining_length) +{ + mqtt_connection_status_t res = MQTT_CONNECT_ACCEPTED; + + u8_t *var_hdr_payload = client->rx_buffer + fixed_hdr_idx; + size_t var_hdr_payload_bufsize = sizeof(client->rx_buffer) - fixed_hdr_idx; + + /* Control packet type */ + u8_t pkt_type = MQTT_CTL_PACKET_TYPE(client->rx_buffer[0]); + u16_t pkt_id = 0; + + LWIP_ASSERT("client->msg_idx < MQTT_VAR_HEADER_BUFFER_LEN", client->msg_idx < MQTT_VAR_HEADER_BUFFER_LEN); + LWIP_ASSERT("fixed_hdr_idx <= client->msg_idx", fixed_hdr_idx <= client->msg_idx); + LWIP_ERROR("buffer length mismatch", fixed_hdr_idx + length <= MQTT_VAR_HEADER_BUFFER_LEN, + return MQTT_CONNECT_DISCONNECTED); + + if (pkt_type == MQTT_MSG_TYPE_CONNACK) { + if (client->conn_state == MQTT_CONNECTING) { + if (length < 2) { + LWIP_DEBUGF(MQTT_DEBUG_WARN,( "mqtt_message_received: Received short CONNACK message\n")); + goto out_disconnect; + } + /* Get result code from CONNACK */ + res = (mqtt_connection_status_t)var_hdr_payload[1]; + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_message_received: Connect response code %d\n", res)); + if (res == MQTT_CONNECT_ACCEPTED) { + /* Reset cyclic_tick when changing to connected state */ + client->cyclic_tick = 0; + client->conn_state = MQTT_CONNECTED; + /* Notify upper layer */ + if (client->connect_cb != 0) { + client->connect_cb(client, client->connect_arg, res); + } + } + } else { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_message_received: Received CONNACK in connected state\n")); + } + } else if (pkt_type == MQTT_MSG_TYPE_PINGRESP) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ( "mqtt_message_received: Received PINGRESP from server\n")); + + } else if (pkt_type == MQTT_MSG_TYPE_PUBLISH) { + u16_t payload_offset = 0; + u16_t payload_length = length; + u8_t qos = MQTT_CTL_PACKET_QOS(client->rx_buffer[0]); + + if (client->msg_idx <= MQTT_VAR_HEADER_BUFFER_LEN) { + /* Should have topic and pkt id*/ + u8_t *topic; + u16_t after_topic; + u8_t bkp; + u16_t topic_len; + u16_t qos_len = (qos ? 2U : 0U); + if (length < 2 + qos_len) { + LWIP_DEBUGF(MQTT_DEBUG_WARN,( "mqtt_message_received: Received short PUBLISH packet\n")); + goto out_disconnect; + } + topic_len = var_hdr_payload[0]; + topic_len = (topic_len << 8) + (u16_t)(var_hdr_payload[1]); + if ((topic_len > length - (2 + qos_len)) || + (topic_len > var_hdr_payload_bufsize - (2 + qos_len))) { + LWIP_DEBUGF(MQTT_DEBUG_WARN,( "mqtt_message_received: Received short PUBLISH packet (topic)\n")); + goto out_disconnect; + } + + topic = var_hdr_payload + 2; + after_topic = 2 + topic_len; + /* Check buffer length, add one byte even for QoS 0 so that zero termination will fit */ + if ((after_topic + (qos ? 2U : 1U)) > var_hdr_payload_bufsize) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_message_received: Receive buffer can not fit topic + pkt_id\n")); + goto out_disconnect; + } + + /* id for QoS 1 and 2 */ + if (qos > 0) { + if (length < after_topic + 2U) { + LWIP_DEBUGF(MQTT_DEBUG_WARN,( "mqtt_message_received: Received short PUBLISH packet (after_topic)\n")); + goto out_disconnect; + } + client->inpub_pkt_id = ((u16_t)var_hdr_payload[after_topic] << 8) + (u16_t)var_hdr_payload[after_topic + 1]; + after_topic += 2; + } else { + client->inpub_pkt_id = 0; + } + /* Take backup of byte after topic */ + bkp = topic[topic_len]; + /* Zero terminate string */ + topic[topic_len] = 0; + /* Payload data remaining in receive buffer */ + payload_length = length - after_topic; + payload_offset = after_topic; + + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_incomming_publish: Received message with QoS %d at topic: %s, payload length %"U32_F"\n", + qos, topic, remaining_length + payload_length)); + if (client->pub_cb != NULL) { + client->pub_cb(client->inpub_arg, (const char *)topic, remaining_length + payload_length); + } + /* Restore byte after topic */ + topic[topic_len] = bkp; + } + if (payload_length > 0 || remaining_length == 0) { + if (length < (size_t)(payload_offset + payload_length)) { + LWIP_DEBUGF(MQTT_DEBUG_WARN,( "mqtt_message_received: Received short packet (payload)\n")); + goto out_disconnect; + } + client->data_cb(client->inpub_arg, var_hdr_payload + payload_offset, payload_length, remaining_length == 0 ? MQTT_DATA_FLAG_LAST : 0); + /* Reply if QoS > 0 */ + if (remaining_length == 0 && qos > 0) { + /* Send PUBACK for QoS 1 or PUBREC for QoS 2 */ + u8_t resp_msg = (qos == 1) ? MQTT_MSG_TYPE_PUBACK : MQTT_MSG_TYPE_PUBREC; + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_incomming_publish: Sending publish response: %s with pkt_id: %d\n", + mqtt_msg_type_to_str(resp_msg), client->inpub_pkt_id)); + pub_ack_rec_rel_response(client, resp_msg, client->inpub_pkt_id, 0); + } + } + } else { + /* Get packet identifier */ + pkt_id = (u16_t)var_hdr_payload[0] << 8; + pkt_id |= (u16_t)var_hdr_payload[1]; + if (pkt_id == 0) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_message_received: Got message with illegal packet identifier: 0\n")); + goto out_disconnect; + } + if (pkt_type == MQTT_MSG_TYPE_PUBREC) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_message_received: PUBREC, sending PUBREL with pkt_id: %d\n", pkt_id)); + pub_ack_rec_rel_response(client, MQTT_MSG_TYPE_PUBREL, pkt_id, 1); + + } else if (pkt_type == MQTT_MSG_TYPE_PUBREL) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_message_received: PUBREL, sending PUBCOMP response with pkt_id: %d\n", pkt_id)); + pub_ack_rec_rel_response(client, MQTT_MSG_TYPE_PUBCOMP, pkt_id, 0); + + } else if (pkt_type == MQTT_MSG_TYPE_SUBACK || pkt_type == MQTT_MSG_TYPE_UNSUBACK || + pkt_type == MQTT_MSG_TYPE_PUBCOMP || pkt_type == MQTT_MSG_TYPE_PUBACK) { + struct mqtt_request_t *r = mqtt_take_request(&client->pend_req_queue, pkt_id); + if (r != NULL) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_message_received: %s response with id %d\n", mqtt_msg_type_to_str(pkt_type), pkt_id)); + if (pkt_type == MQTT_MSG_TYPE_SUBACK) { + if (length < 3) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_message_received: To small SUBACK packet\n")); + goto out_disconnect; + } else { + mqtt_incomming_suback(r, var_hdr_payload[2]); + } + } else if (r->cb != NULL) { + r->cb(r->arg, ERR_OK); + } + mqtt_delete_request(r); + } else { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ( "mqtt_message_received: Received %s reply, with wrong pkt_id: %d\n", mqtt_msg_type_to_str(pkt_type), pkt_id)); + } + } else { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ( "mqtt_message_received: Received unknown message type: %d\n", pkt_type)); + goto out_disconnect; + } + } + return res; +out_disconnect: + return MQTT_CONNECT_DISCONNECTED; +} + + +/** + * MQTT incoming message parser + * @param client MQTT client + * @param p PBUF chain of received data + * @return Connection status + */ +static mqtt_connection_status_t +mqtt_parse_incoming(mqtt_client_t *client, struct pbuf *p) +{ + u16_t in_offset = 0; + u32_t msg_rem_len = 0; + u8_t fixed_hdr_idx = 0; + u8_t b = 0; + + while (p->tot_len > in_offset) { + /* We ALWAYS parse the header here first. Even if the header was not + included in this segment, we re-parse it here by buffering it in + client->rx_buffer. client->msg_idx keeps track of this. */ + if ((fixed_hdr_idx < 2) || ((b & 0x80) != 0)) { + + if (fixed_hdr_idx < client->msg_idx) { + /* parse header from old pbuf (buffered in client->rx_buffer) */ + b = client->rx_buffer[fixed_hdr_idx]; + } else { + /* parse header from this pbuf and save it in client->rx_buffer in case + it comes in segmented */ + b = pbuf_get_at(p, in_offset++); + client->rx_buffer[client->msg_idx++] = b; + } + fixed_hdr_idx++; + + if (fixed_hdr_idx >= 2) { + /* fixed header contains at least 2 bytes but can contain more, depending on + 'remaining length'. All bytes but the last of this have 0x80 set to + indicate more bytes are coming. */ + msg_rem_len |= (u32_t)(b & 0x7f) << ((fixed_hdr_idx - 2) * 7); + if ((b & 0x80) == 0) { + /* fixed header is done */ + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_parse_incoming: Remaining length after fixed header: %"U32_F"\n", msg_rem_len)); + if (msg_rem_len == 0) { + /* Complete message with no extra headers of payload received */ + mqtt_message_received(client, fixed_hdr_idx, 0, 0); + client->msg_idx = 0; + fixed_hdr_idx = 0; + } else { + /* Bytes remaining in message (changes remaining length if this is + not the first segment of this message) */ + msg_rem_len = (msg_rem_len + fixed_hdr_idx) - client->msg_idx; + } + } + } + } else { + /* Fixed header has been parsed, parse variable header */ + u16_t cpy_len, cpy_start, buffer_space; + + cpy_start = (client->msg_idx - fixed_hdr_idx) % (MQTT_VAR_HEADER_BUFFER_LEN - fixed_hdr_idx) + fixed_hdr_idx; + + /* Allow to copy the lesser one of available length in input data or bytes remaining in message */ + cpy_len = (u16_t)LWIP_MIN((u16_t)(p->tot_len - in_offset), msg_rem_len); + + /* Limit to available space in buffer */ + buffer_space = MQTT_VAR_HEADER_BUFFER_LEN - cpy_start; + if (cpy_len > buffer_space) { + cpy_len = buffer_space; + } + pbuf_copy_partial(p, client->rx_buffer + cpy_start, cpy_len, in_offset); + + /* Advance get and put indexes */ + client->msg_idx += cpy_len; + in_offset += cpy_len; + msg_rem_len -= cpy_len; + + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_parse_incoming: msg_idx: %"U32_F", cpy_len: %"U16_F", remaining %"U32_F"\n", client->msg_idx, cpy_len, msg_rem_len)); + if ((msg_rem_len == 0) || (cpy_len == buffer_space)) { + /* Whole message received or buffer is full */ + mqtt_connection_status_t res = mqtt_message_received(client, fixed_hdr_idx, (cpy_start + cpy_len) - fixed_hdr_idx, msg_rem_len); + if (res != MQTT_CONNECT_ACCEPTED) { + return res; + } + if (msg_rem_len == 0) { + /* Reset parser state */ + client->msg_idx = 0; + /* msg_tot_len = 0; */ + fixed_hdr_idx = 0; + } + } + } + } + return MQTT_CONNECT_ACCEPTED; +} + + +/** + * TCP received callback function. @see tcp_recv_fn + * @param arg MQTT client + * @param p PBUF chain of received data + * @param err Passed as return value if not ERR_OK + * @return ERR_OK or err passed into callback + */ +static err_t +mqtt_tcp_recv_cb(void *arg, struct altcp_pcb *pcb, struct pbuf *p, err_t err) +{ + mqtt_client_t *client = (mqtt_client_t *)arg; + LWIP_ASSERT("mqtt_tcp_recv_cb: client != NULL", client != NULL); + LWIP_ASSERT("mqtt_tcp_recv_cb: client->conn == pcb", client->conn == pcb); + + if (p == NULL) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_tcp_recv_cb: Recv pbuf=NULL, remote has closed connection\n")); + mqtt_close(client, MQTT_CONNECT_DISCONNECTED); + } else { + mqtt_connection_status_t res; + if (err != ERR_OK) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_tcp_recv_cb: Recv err=%d\n", err)); + pbuf_free(p); + return err; + } + + /* Tell remote that data has been received */ + altcp_recved(pcb, p->tot_len); + res = mqtt_parse_incoming(client, p); + pbuf_free(p); + + if (res != MQTT_CONNECT_ACCEPTED) { + mqtt_close(client, res); + } + /* If keep alive functionality is used */ + if (client->keep_alive != 0) { + /* Reset server alive watchdog */ + client->server_watchdog = 0; + } + + } + return ERR_OK; +} + + +/** + * TCP data sent callback function. @see tcp_sent_fn + * @param arg MQTT client + * @param tpcb TCP connection handle + * @param len Number of bytes sent + * @return ERR_OK + */ +static err_t +mqtt_tcp_sent_cb(void *arg, struct altcp_pcb *tpcb, u16_t len) +{ + mqtt_client_t *client = (mqtt_client_t *)arg; + + LWIP_UNUSED_ARG(tpcb); + LWIP_UNUSED_ARG(len); + + if (client->conn_state == MQTT_CONNECTED) { + struct mqtt_request_t *r; + + /* Reset keep-alive send timer and server watchdog */ + client->cyclic_tick = 0; + client->server_watchdog = 0; + /* QoS 0 publish has no response from server, so call its callbacks here */ + while ((r = mqtt_take_request(&client->pend_req_queue, 0)) != NULL) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_tcp_sent_cb: Calling QoS 0 publish complete callback\n")); + if (r->cb != NULL) { + r->cb(r->arg, ERR_OK); + } + mqtt_delete_request(r); + } + /* Try send any remaining buffers from output queue */ + mqtt_output_send(&client->output, client->conn); + } + return ERR_OK; +} + +/** + * TCP error callback function. @see tcp_err_fn + * @param arg MQTT client + * @param err Error encountered + */ +static void +mqtt_tcp_err_cb(void *arg, err_t err) +{ + mqtt_client_t *client = (mqtt_client_t *)arg; + LWIP_UNUSED_ARG(err); /* only used for debug output */ + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_tcp_err_cb: TCP error callback: error %d, arg: %p\n", err, arg)); + LWIP_ASSERT("mqtt_tcp_err_cb: client != NULL", client != NULL); + /* Set conn to null before calling close as pcb is already deallocated*/ + client->conn = 0; + mqtt_close(client, MQTT_CONNECT_DISCONNECTED); +} + +/** + * TCP poll callback function. @see tcp_poll_fn + * @param arg MQTT client + * @param tpcb TCP connection handle + * @return err ERR_OK + */ +static err_t +mqtt_tcp_poll_cb(void *arg, struct altcp_pcb *tpcb) +{ + mqtt_client_t *client = (mqtt_client_t *)arg; + if (client->conn_state == MQTT_CONNECTED) { + /* Try send any remaining buffers from output queue */ + mqtt_output_send(&client->output, tpcb); + } + return ERR_OK; +} + +/** + * TCP connect callback function. @see tcp_connected_fn + * @param arg MQTT client + * @param err Always ERR_OK, mqtt_tcp_err_cb is called in case of error + * @return ERR_OK + */ +static err_t +mqtt_tcp_connect_cb(void *arg, struct altcp_pcb *tpcb, err_t err) +{ + mqtt_client_t *client = (mqtt_client_t *)arg; + + if (err != ERR_OK) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_tcp_connect_cb: TCP connect error %d\n", err)); + return err; + } + + /* Initiate receiver state */ + client->msg_idx = 0; + + /* Setup TCP callbacks */ + altcp_recv(tpcb, mqtt_tcp_recv_cb); + altcp_sent(tpcb, mqtt_tcp_sent_cb); + altcp_poll(tpcb, mqtt_tcp_poll_cb, 2); + + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_tcp_connect_cb: TCP connection established to server\n")); + /* Enter MQTT connect state */ + client->conn_state = MQTT_CONNECTING; + + /* Start cyclic timer */ + sys_timeout(MQTT_CYCLIC_TIMER_INTERVAL * 1000, mqtt_cyclic_timer, client); + client->cyclic_tick = 0; + + /* Start transmission from output queue, connect message is the first one out*/ + mqtt_output_send(&client->output, client->conn); + + return ERR_OK; +} + + + +/*---------------------------------------------------------------------------------------------------- */ +/* Public API */ + + +/** + * @ingroup mqtt + * MQTT publish function. + * @param client MQTT client + * @param topic Publish topic string + * @param payload Data to publish (NULL is allowed) + * @param payload_length Length of payload (0 is allowed) + * @param qos Quality of service, 0 1 or 2 + * @param retain MQTT retain flag + * @param cb Callback to call when publish is complete or has timed out + * @param arg User supplied argument to publish callback + * @return ERR_OK if successful + * ERR_CONN if client is disconnected + * ERR_MEM if short on memory + */ +err_t +mqtt_publish(mqtt_client_t *client, const char *topic, const void *payload, u16_t payload_length, u8_t qos, u8_t retain, + mqtt_request_cb_t cb, void *arg) +{ + struct mqtt_request_t *r; + u16_t pkt_id; + size_t topic_strlen; + size_t total_len; + u16_t topic_len; + u16_t remaining_length; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("mqtt_publish: client != NULL", client); + LWIP_ASSERT("mqtt_publish: topic != NULL", topic); + LWIP_ERROR("mqtt_publish: TCP disconnected", (client->conn_state != TCP_DISCONNECTED), return ERR_CONN); + + topic_strlen = strlen(topic); + LWIP_ERROR("mqtt_publish: topic length overflow", (topic_strlen <= (0xFFFF - 2)), return ERR_ARG); + topic_len = (u16_t)topic_strlen; + total_len = 2 + topic_len + payload_length; + + if (qos > 0) { + total_len += 2; + /* Generate pkt_id id for QoS1 and 2 */ + pkt_id = msg_generate_packet_id(client); + } else { + /* Use reserved value pkt_id 0 for QoS 0 in request handle */ + pkt_id = 0; + } + LWIP_ERROR("mqtt_publish: total length overflow", (total_len <= 0xFFFF), return ERR_ARG); + remaining_length = (u16_t)total_len; + + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_publish: Publish with payload length %d to topic \"%s\"\n", payload_length, topic)); + + r = mqtt_create_request(client->req_list, LWIP_ARRAYSIZE(client->req_list), pkt_id, cb, arg); + if (r == NULL) { + return ERR_MEM; + } + + if (mqtt_output_check_space(&client->output, remaining_length) == 0) { + mqtt_delete_request(r); + return ERR_MEM; + } + /* Append fixed header */ + mqtt_output_append_fixed_header(&client->output, MQTT_MSG_TYPE_PUBLISH, 0, qos, retain, remaining_length); + + /* Append Topic */ + mqtt_output_append_string(&client->output, topic, topic_len); + + /* Append packet if for QoS 1 and 2*/ + if (qos > 0) { + mqtt_output_append_u16(&client->output, pkt_id); + } + + /* Append optional publish payload */ + if ((payload != NULL) && (payload_length > 0)) { + mqtt_output_append_buf(&client->output, payload, payload_length); + } + + mqtt_append_request(&client->pend_req_queue, r); + mqtt_output_send(&client->output, client->conn); + return ERR_OK; +} + + +/** + * @ingroup mqtt + * MQTT subscribe/unsubscribe function. + * @param client MQTT client + * @param topic topic to subscribe to + * @param qos Quality of service, 0 1 or 2 (only used for subscribe) + * @param cb Callback to call when subscribe/unsubscribe reponse is received + * @param arg User supplied argument to publish callback + * @param sub 1 for subscribe, 0 for unsubscribe + * @return ERR_OK if successful, @see err_t enum for other results + */ +err_t +mqtt_sub_unsub(mqtt_client_t *client, const char *topic, u8_t qos, mqtt_request_cb_t cb, void *arg, u8_t sub) +{ + size_t topic_strlen; + size_t total_len; + u16_t topic_len; + u16_t remaining_length; + u16_t pkt_id; + struct mqtt_request_t *r; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("mqtt_sub_unsub: client != NULL", client); + LWIP_ASSERT("mqtt_sub_unsub: topic != NULL", topic); + + topic_strlen = strlen(topic); + LWIP_ERROR("mqtt_sub_unsub: topic length overflow", (topic_strlen <= (0xFFFF - 2)), return ERR_ARG); + topic_len = (u16_t)topic_strlen; + /* Topic string, pkt_id, qos for subscribe */ + total_len = topic_len + 2 + 2 + (sub != 0); + LWIP_ERROR("mqtt_sub_unsub: total length overflow", (total_len <= 0xFFFF), return ERR_ARG); + remaining_length = (u16_t)total_len; + + LWIP_ASSERT("mqtt_sub_unsub: qos < 3", qos < 3); + if (client->conn_state == TCP_DISCONNECTED) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_sub_unsub: Can not (un)subscribe in disconnected state\n")); + return ERR_CONN; + } + + pkt_id = msg_generate_packet_id(client); + r = mqtt_create_request(client->req_list, LWIP_ARRAYSIZE(client->req_list), pkt_id, cb, arg); + if (r == NULL) { + return ERR_MEM; + } + + if (mqtt_output_check_space(&client->output, remaining_length) == 0) { + mqtt_delete_request(r); + return ERR_MEM; + } + + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_sub_unsub: Client (un)subscribe to topic \"%s\", id: %d\n", topic, pkt_id)); + + mqtt_output_append_fixed_header(&client->output, sub ? MQTT_MSG_TYPE_SUBSCRIBE : MQTT_MSG_TYPE_UNSUBSCRIBE, 0, 1, 0, remaining_length); + /* Packet id */ + mqtt_output_append_u16(&client->output, pkt_id); + /* Topic */ + mqtt_output_append_string(&client->output, topic, topic_len); + /* QoS */ + if (sub != 0) { + mqtt_output_append_u8(&client->output, LWIP_MIN(qos, 2)); + } + + mqtt_append_request(&client->pend_req_queue, r); + mqtt_output_send(&client->output, client->conn); + return ERR_OK; +} + + +/** + * @ingroup mqtt + * Set callback to handle incoming publish requests from server + * @param client MQTT client + * @param pub_cb Callback invoked when publish starts, contain topic and total length of payload + * @param data_cb Callback for each fragment of payload that arrives + * @param arg User supplied argument to both callbacks + */ +void +mqtt_set_inpub_callback(mqtt_client_t *client, mqtt_incoming_publish_cb_t pub_cb, + mqtt_incoming_data_cb_t data_cb, void *arg) +{ + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("mqtt_set_inpub_callback: client != NULL", client != NULL); + client->data_cb = data_cb; + client->pub_cb = pub_cb; + client->inpub_arg = arg; +} + +/** + * @ingroup mqtt + * Create a new MQTT client instance + * @return Pointer to instance on success, NULL otherwise + */ +mqtt_client_t * +mqtt_client_new(void) +{ + LWIP_ASSERT_CORE_LOCKED(); + return (mqtt_client_t *)mem_calloc(1, sizeof(mqtt_client_t)); +} + +/** + * @ingroup mqtt + * Free MQTT client instance + * @param client Pointer to instance to be freed + */ +void +mqtt_client_free(mqtt_client_t *client) +{ + mem_free(client); +} + +/** + * @ingroup mqtt + * Connect to MQTT server + * @param client MQTT client + * @param ip_addr Server IP + * @param port Server port + * @param cb Connection state change callback + * @param arg User supplied argument to connection callback + * @param client_info Client identification and connection options + * @return ERR_OK if successful, @see err_t enum for other results + */ +err_t +mqtt_client_connect(mqtt_client_t *client, const ip_addr_t *ip_addr, u16_t port, mqtt_connection_cb_t cb, void *arg, + const struct mqtt_connect_client_info_t *client_info) +{ + err_t err; + size_t len; + u16_t client_id_length; + /* Length is the sum of 2+"MQTT", protocol level, flags and keep alive */ + u16_t remaining_length = 2 + 4 + 1 + 1 + 2; + u8_t flags = 0, will_topic_len = 0, will_msg_len = 0; + u16_t client_user_len = 0, client_pass_len = 0; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("mqtt_client_connect: client != NULL", client != NULL); + LWIP_ASSERT("mqtt_client_connect: ip_addr != NULL", ip_addr != NULL); + LWIP_ASSERT("mqtt_client_connect: client_info != NULL", client_info != NULL); + LWIP_ASSERT("mqtt_client_connect: client_info->client_id != NULL", client_info->client_id != NULL); + + if (client->conn_state != TCP_DISCONNECTED) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_client_connect: Already connected\n")); + return ERR_ISCONN; + } + + /* Wipe clean */ + memset(client, 0, sizeof(mqtt_client_t)); + client->connect_arg = arg; + client->connect_cb = cb; + client->keep_alive = client_info->keep_alive; + mqtt_init_requests(client->req_list, LWIP_ARRAYSIZE(client->req_list)); + + /* Build connect message */ + if (client_info->will_topic != NULL && client_info->will_msg != NULL) { + flags |= MQTT_CONNECT_FLAG_WILL; + flags |= (client_info->will_qos & 3) << 3; + if (client_info->will_retain) { + flags |= MQTT_CONNECT_FLAG_WILL_RETAIN; + } + len = strlen(client_info->will_topic); + LWIP_ERROR("mqtt_client_connect: client_info->will_topic length overflow", len <= 0xFF, return ERR_VAL); + LWIP_ERROR("mqtt_client_connect: client_info->will_topic length must be > 0", len > 0, return ERR_VAL); + will_topic_len = (u8_t)len; + len = strlen(client_info->will_msg); + LWIP_ERROR("mqtt_client_connect: client_info->will_msg length overflow", len <= 0xFF, return ERR_VAL); + will_msg_len = (u8_t)len; + len = remaining_length + 2 + will_topic_len + 2 + will_msg_len; + LWIP_ERROR("mqtt_client_connect: remaining_length overflow", len <= 0xFFFF, return ERR_VAL); + remaining_length = (u16_t)len; + } + if (client_info->client_user != NULL) { + flags |= MQTT_CONNECT_FLAG_USERNAME; + len = strlen(client_info->client_user); + LWIP_ERROR("mqtt_client_connect: client_info->client_user length overflow", len <= 0xFFFF, return ERR_VAL); + LWIP_ERROR("mqtt_client_connect: client_info->client_user length must be > 0", len > 0, return ERR_VAL); + client_user_len = (u16_t)len; + len = remaining_length + 2 + client_user_len; + LWIP_ERROR("mqtt_client_connect: remaining_length overflow", len <= 0xFFFF, return ERR_VAL); + remaining_length = (u16_t)len; + } + if (client_info->client_pass != NULL) { + flags |= MQTT_CONNECT_FLAG_PASSWORD; + len = strlen(client_info->client_pass); + LWIP_ERROR("mqtt_client_connect: client_info->client_pass length overflow", len <= 0xFFFF, return ERR_VAL); + LWIP_ERROR("mqtt_client_connect: client_info->client_pass length must be > 0", len > 0, return ERR_VAL); + client_pass_len = (u16_t)len; + len = remaining_length + 2 + client_pass_len; + LWIP_ERROR("mqtt_client_connect: remaining_length overflow", len <= 0xFFFF, return ERR_VAL); + remaining_length = (u16_t)len; + } + + /* Don't complicate things, always connect using clean session */ + flags |= MQTT_CONNECT_FLAG_CLEAN_SESSION; + + len = strlen(client_info->client_id); + LWIP_ERROR("mqtt_client_connect: client_info->client_id length overflow", len <= 0xFFFF, return ERR_VAL); + client_id_length = (u16_t)len; + len = remaining_length + 2 + client_id_length; + LWIP_ERROR("mqtt_client_connect: remaining_length overflow", len <= 0xFFFF, return ERR_VAL); + remaining_length = (u16_t)len; + + if (mqtt_output_check_space(&client->output, remaining_length) == 0) { + return ERR_MEM; + } + +#if LWIP_ALTCP && LWIP_ALTCP_TLS + if (client_info->tls_config) { + client->conn = altcp_tls_new(client_info->tls_config, IP_GET_TYPE(ip_addr)); + } else +#endif + { + client->conn = altcp_tcp_new_ip_type(IP_GET_TYPE(ip_addr)); + } + if (client->conn == NULL) { + return ERR_MEM; + } + + /* Set arg pointer for callbacks */ + altcp_arg(client->conn, client); + /* Any local address, pick random local port number */ + err = altcp_bind(client->conn, IP_ADDR_ANY, 0); + if (err != ERR_OK) { + LWIP_DEBUGF(MQTT_DEBUG_WARN, ("mqtt_client_connect: Error binding to local ip/port, %d\n", err)); + goto tcp_fail; + } + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_client_connect: Connecting to host: %s at port:%"U16_F"\n", ipaddr_ntoa(ip_addr), port)); + + /* Connect to server */ + err = altcp_connect(client->conn, ip_addr, port, mqtt_tcp_connect_cb); + if (err != ERR_OK) { + LWIP_DEBUGF(MQTT_DEBUG_TRACE, ("mqtt_client_connect: Error connecting to remote ip/port, %d\n", err)); + goto tcp_fail; + } + /* Set error callback */ + altcp_err(client->conn, mqtt_tcp_err_cb); + client->conn_state = TCP_CONNECTING; + + /* Append fixed header */ + mqtt_output_append_fixed_header(&client->output, MQTT_MSG_TYPE_CONNECT, 0, 0, 0, remaining_length); + /* Append Protocol string */ + mqtt_output_append_string(&client->output, "MQTT", 4); + /* Append Protocol level */ + mqtt_output_append_u8(&client->output, 4); + /* Append connect flags */ + mqtt_output_append_u8(&client->output, flags); + /* Append keep-alive */ + mqtt_output_append_u16(&client->output, client_info->keep_alive); + /* Append client id */ + mqtt_output_append_string(&client->output, client_info->client_id, client_id_length); + /* Append will message if used */ + if ((flags & MQTT_CONNECT_FLAG_WILL) != 0) { + mqtt_output_append_string(&client->output, client_info->will_topic, will_topic_len); + mqtt_output_append_string(&client->output, client_info->will_msg, will_msg_len); + } + /* Append user name if given */ + if ((flags & MQTT_CONNECT_FLAG_USERNAME) != 0) { + mqtt_output_append_string(&client->output, client_info->client_user, client_user_len); + } + /* Append password if given */ + if ((flags & MQTT_CONNECT_FLAG_PASSWORD) != 0) { + mqtt_output_append_string(&client->output, client_info->client_pass, client_pass_len); + } + return ERR_OK; + +tcp_fail: + altcp_abort(client->conn); + client->conn = NULL; + return err; +} + + +/** + * @ingroup mqtt + * Disconnect from MQTT server + * @param client MQTT client + */ +void +mqtt_disconnect(mqtt_client_t *client) +{ + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("mqtt_disconnect: client != NULL", client); + /* If connection in not already closed */ + if (client->conn_state != TCP_DISCONNECTED) { + /* Set conn_state before calling mqtt_close to prevent callback from being called */ + client->conn_state = TCP_DISCONNECTED; + mqtt_close(client, (mqtt_connection_status_t)0); + } +} + +/** + * @ingroup mqtt + * Check connection with server + * @param client MQTT client + * @return 1 if connected to server, 0 otherwise + */ +u8_t +mqtt_client_is_connected(mqtt_client_t *client) +{ + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("mqtt_client_is_connected: client != NULL", client); + return client->conn_state == MQTT_CONNECTED; +} + +#endif /* LWIP_TCP && LWIP_CALLBACK_API */ diff --git a/Middlewares/Third_Party/LwIP/src/core/altcp.c b/Middlewares/Third_Party/LwIP/src/core/altcp.c new file mode 100644 index 0000000..d46d6cd --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/altcp.c @@ -0,0 +1,681 @@ +/** + * @file + * @defgroup altcp Application layered TCP Functions + * @ingroup altcp_api + * + * This file contains the common functions for altcp to work. + * For more details see @ref altcp_api. + */ + +/** + * @defgroup altcp_api Application layered TCP Introduction + * @ingroup callbackstyle_api + * + * Overview + * -------- + * altcp (application layered TCP connection API; to be used from TCPIP thread) + * is an abstraction layer that prevents applications linking hard against the + * @ref tcp.h functions while providing the same functionality. It is used to + * e.g. add SSL/TLS (see LWIP_ALTCP_TLS) or proxy-connect support to an application + * written for the tcp callback API without that application knowing the + * protocol details. + * + * * This interface mimics the tcp callback API to the application while preventing + * direct linking (much like virtual functions). + * * This way, an application can make use of other application layer protocols + * on top of TCP without knowing the details (e.g. TLS, proxy connection). + * * This is achieved by simply including "lwip/altcp.h" instead of "lwip/tcp.h", + * replacing "struct tcp_pcb" with "struct altcp_pcb" and prefixing all functions + * with "altcp_" instead of "tcp_". + * + * With altcp support disabled (LWIP_ALTCP==0), applications written against the + * altcp API can still be compiled but are directly linked against the tcp.h + * callback API and then cannot use layered protocols. To minimize code changes + * in this case, the use of altcp_allocators is strongly suggested. + * + * Usage + * ----- + * To make use of this API from an existing tcp raw API application: + * * Include "lwip/altcp.h" instead of "lwip/tcp.h" + * * Replace "struct tcp_pcb" with "struct altcp_pcb" + * * Prefix all called tcp API functions with "altcp_" instead of "tcp_" to link + * against the altcp functions + * * @ref altcp_new (and @ref altcp_new_ip_type/@ref altcp_new_ip6) take + * an @ref altcp_allocator_t as an argument, whereas the original tcp API + * functions take no arguments. + * * An @ref altcp_allocator_t allocator is an object that holds a pointer to an + * allocator object and a corresponding state (e.g. for TLS, the corresponding + * state may hold certificates or keys). This way, the application does not + * even need to know if it uses TLS or pure TCP, this is handled at runtime + * by passing a specific allocator. + * * An application can alternatively bind hard to the altcp_tls API by calling + * @ref altcp_tls_new or @ref altcp_tls_wrap. + * * The TLS layer is not directly implemented by lwIP, but a port to mbedTLS is + * provided. + * * Another altcp layer is proxy-connect to use TLS behind a HTTP proxy (see + * @ref altcp_proxyconnect.h) + * + * altcp_allocator_t + * ----------------- + * An altcp allocator is created by the application by combining an allocator + * callback function and a corresponding state, e.g.:\code{.c} + * static const unsigned char cert[] = {0x2D, ... (see mbedTLS doc for how to create this)}; + * struct altcp_tls_config * conf = altcp_tls_create_config_client(cert, sizeof(cert)); + * altcp_allocator_t tls_allocator = { + * altcp_tls_alloc, conf + * }; + * \endcode + * + * + * struct altcp_tls_config + * ----------------------- + * The struct altcp_tls_config holds state that is needed to create new TLS client + * or server connections (e.g. certificates and private keys). + * + * It is not defined by lwIP itself but by the TLS port (e.g. altcp_tls to mbedTLS + * adaption). However, the parameters used to create it are defined in @ref + * altcp_tls.h (see @ref altcp_tls_create_config_server_privkey_cert for servers + * and @ref altcp_tls_create_config_client/@ref altcp_tls_create_config_client_2wayauth + * for clients). + * + * For mbedTLS, ensure that certificates can be parsed by 'mbedtls_x509_crt_parse()' and + * private keys can be parsed by 'mbedtls_pk_parse_key()'. + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/altcp.h" +#include "lwip/priv/altcp_priv.h" +#include "lwip/altcp_tcp.h" +#include "lwip/tcp.h" +#include "lwip/mem.h" + +#include + +extern const struct altcp_functions altcp_tcp_functions; + +/** + * For altcp layer implementations only: allocate a new struct altcp_pcb from the pool + * and zero the memory + */ +struct altcp_pcb * +altcp_alloc(void) +{ + struct altcp_pcb *ret = (struct altcp_pcb *)memp_malloc(MEMP_ALTCP_PCB); + if (ret != NULL) { + memset(ret, 0, sizeof(struct altcp_pcb)); + } + return ret; +} + +/** + * For altcp layer implementations only: return a struct altcp_pcb to the pool + */ +void +altcp_free(struct altcp_pcb *conn) +{ + if (conn) { + if (conn->fns && conn->fns->dealloc) { + conn->fns->dealloc(conn); + } + memp_free(MEMP_ALTCP_PCB, conn); + } +} + +/** + * @ingroup altcp + * altcp_new_ip6: @ref altcp_new for IPv6 + */ +struct altcp_pcb * +altcp_new_ip6(altcp_allocator_t *allocator) +{ + return altcp_new_ip_type(allocator, IPADDR_TYPE_V6); +} + +/** + * @ingroup altcp + * altcp_new: @ref altcp_new for IPv4 + */ +struct altcp_pcb * +altcp_new(altcp_allocator_t *allocator) +{ + return altcp_new_ip_type(allocator, IPADDR_TYPE_V4); +} + +/** + * @ingroup altcp + * altcp_new_ip_type: called by applications to allocate a new pcb with the help of an + * allocator function. + * + * @param allocator allocator function and argument + * @param ip_type IP version of the pcb (@ref lwip_ip_addr_type) + * @return a new altcp_pcb or NULL on error + */ +struct altcp_pcb * +altcp_new_ip_type(altcp_allocator_t *allocator, u8_t ip_type) +{ + struct altcp_pcb *conn; + if (allocator == NULL) { + /* no allocator given, create a simple TCP connection */ + return altcp_tcp_new_ip_type(ip_type); + } + if (allocator->alloc == NULL) { + /* illegal allocator */ + return NULL; + } + conn = allocator->alloc(allocator->arg, ip_type); + if (conn == NULL) { + /* allocation failed */ + return NULL; + } + return conn; +} + +/** + * @ingroup altcp + * @see tcp_arg() + */ +void +altcp_arg(struct altcp_pcb *conn, void *arg) +{ + if (conn) { + conn->arg = arg; + } +} + +/** + * @ingroup altcp + * @see tcp_accept() + */ +void +altcp_accept(struct altcp_pcb *conn, altcp_accept_fn accept) +{ + if (conn != NULL) { + conn->accept = accept; + } +} + +/** + * @ingroup altcp + * @see tcp_recv() + */ +void +altcp_recv(struct altcp_pcb *conn, altcp_recv_fn recv) +{ + if (conn) { + conn->recv = recv; + } +} + +/** + * @ingroup altcp + * @see tcp_sent() + */ +void +altcp_sent(struct altcp_pcb *conn, altcp_sent_fn sent) +{ + if (conn) { + conn->sent = sent; + } +} + +/** + * @ingroup altcp + * @see tcp_poll() + */ +void +altcp_poll(struct altcp_pcb *conn, altcp_poll_fn poll, u8_t interval) +{ + if (conn) { + conn->poll = poll; + conn->pollinterval = interval; + if (conn->fns && conn->fns->set_poll) { + conn->fns->set_poll(conn, interval); + } + } +} + +/** + * @ingroup altcp + * @see tcp_err() + */ +void +altcp_err(struct altcp_pcb *conn, altcp_err_fn err) +{ + if (conn) { + conn->err = err; + } +} + +/* Generic functions calling the "virtual" ones */ + +/** + * @ingroup altcp + * @see tcp_recved() + */ +void +altcp_recved(struct altcp_pcb *conn, u16_t len) +{ + if (conn && conn->fns && conn->fns->recved) { + conn->fns->recved(conn, len); + } +} + +/** + * @ingroup altcp + * @see tcp_bind() + */ +err_t +altcp_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port) +{ + if (conn && conn->fns && conn->fns->bind) { + return conn->fns->bind(conn, ipaddr, port); + } + return ERR_VAL; +} + +/** + * @ingroup altcp + * @see tcp_connect() + */ +err_t +altcp_connect(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected) +{ + if (conn && conn->fns && conn->fns->connect) { + return conn->fns->connect(conn, ipaddr, port, connected); + } + return ERR_VAL; +} + +/** + * @ingroup altcp + * @see tcp_listen_with_backlog_and_err() + */ +struct altcp_pcb * +altcp_listen_with_backlog_and_err(struct altcp_pcb *conn, u8_t backlog, err_t *err) +{ + if (conn && conn->fns && conn->fns->listen) { + return conn->fns->listen(conn, backlog, err); + } + return NULL; +} + +/** + * @ingroup altcp + * @see tcp_abort() + */ +void +altcp_abort(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->abort) { + conn->fns->abort(conn); + } +} + +/** + * @ingroup altcp + * @see tcp_close() + */ +err_t +altcp_close(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->close) { + return conn->fns->close(conn); + } + return ERR_VAL; +} + +/** + * @ingroup altcp + * @see tcp_shutdown() + */ +err_t +altcp_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx) +{ + if (conn && conn->fns && conn->fns->shutdown) { + return conn->fns->shutdown(conn, shut_rx, shut_tx); + } + return ERR_VAL; +} + +/** + * @ingroup altcp + * @see tcp_write() + */ +err_t +altcp_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags) +{ + if (conn && conn->fns && conn->fns->write) { + return conn->fns->write(conn, dataptr, len, apiflags); + } + return ERR_VAL; +} + +/** + * @ingroup altcp + * @see tcp_output() + */ +err_t +altcp_output(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->output) { + return conn->fns->output(conn); + } + return ERR_VAL; +} + +/** + * @ingroup altcp + * @see tcp_mss() + */ +u16_t +altcp_mss(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->mss) { + return conn->fns->mss(conn); + } + return 0; +} + +/** + * @ingroup altcp + * @see tcp_sndbuf() + */ +u16_t +altcp_sndbuf(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->sndbuf) { + return conn->fns->sndbuf(conn); + } + return 0; +} + +/** + * @ingroup altcp + * @see tcp_sndqueuelen() + */ +u16_t +altcp_sndqueuelen(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->sndqueuelen) { + return conn->fns->sndqueuelen(conn); + } + return 0; +} + +void +altcp_nagle_disable(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->nagle_disable) { + conn->fns->nagle_disable(conn); + } +} + +void +altcp_nagle_enable(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->nagle_enable) { + conn->fns->nagle_enable(conn); + } +} + +int +altcp_nagle_disabled(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->nagle_disabled) { + return conn->fns->nagle_disabled(conn); + } + return 0; +} + +/** + * @ingroup altcp + * @see tcp_setprio() + */ +void +altcp_setprio(struct altcp_pcb *conn, u8_t prio) +{ + if (conn && conn->fns && conn->fns->setprio) { + conn->fns->setprio(conn, prio); + } +} + +err_t +altcp_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port) +{ + if (conn && conn->fns && conn->fns->addrinfo) { + return conn->fns->addrinfo(conn, local, addr, port); + } + return ERR_VAL; +} + +ip_addr_t * +altcp_get_ip(struct altcp_pcb *conn, int local) +{ + if (conn && conn->fns && conn->fns->getip) { + return conn->fns->getip(conn, local); + } + return NULL; +} + +u16_t +altcp_get_port(struct altcp_pcb *conn, int local) +{ + if (conn && conn->fns && conn->fns->getport) { + return conn->fns->getport(conn, local); + } + return 0; +} + +#ifdef LWIP_DEBUG +enum tcp_state +altcp_dbg_get_tcp_state(struct altcp_pcb *conn) +{ + if (conn && conn->fns && conn->fns->dbg_get_tcp_state) { + return conn->fns->dbg_get_tcp_state(conn); + } + return CLOSED; +} +#endif + +/* Default implementations for the "virtual" functions */ + +void +altcp_default_set_poll(struct altcp_pcb *conn, u8_t interval) +{ + if (conn && conn->inner_conn) { + altcp_poll(conn->inner_conn, conn->poll, interval); + } +} + +void +altcp_default_recved(struct altcp_pcb *conn, u16_t len) +{ + if (conn && conn->inner_conn) { + altcp_recved(conn->inner_conn, len); + } +} + +err_t +altcp_default_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port) +{ + if (conn && conn->inner_conn) { + return altcp_bind(conn->inner_conn, ipaddr, port); + } + return ERR_VAL; +} + +err_t +altcp_default_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx) +{ + if (conn) { + if (shut_rx && shut_tx && conn->fns && conn->fns->close) { + /* default shutdown for both sides is close */ + return conn->fns->close(conn); + } + if (conn->inner_conn) { + return altcp_shutdown(conn->inner_conn, shut_rx, shut_tx); + } + } + return ERR_VAL; +} + +err_t +altcp_default_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags) +{ + if (conn && conn->inner_conn) { + return altcp_write(conn->inner_conn, dataptr, len, apiflags); + } + return ERR_VAL; +} + +err_t +altcp_default_output(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + return altcp_output(conn->inner_conn); + } + return ERR_VAL; +} + +u16_t +altcp_default_mss(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + return altcp_mss(conn->inner_conn); + } + return 0; +} + +u16_t +altcp_default_sndbuf(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + return altcp_sndbuf(conn->inner_conn); + } + return 0; +} + +u16_t +altcp_default_sndqueuelen(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + return altcp_sndqueuelen(conn->inner_conn); + } + return 0; +} + +void +altcp_default_nagle_disable(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + altcp_nagle_disable(conn->inner_conn); + } +} + +void +altcp_default_nagle_enable(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + altcp_nagle_enable(conn->inner_conn); + } +} + +int +altcp_default_nagle_disabled(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + return altcp_nagle_disabled(conn->inner_conn); + } + return 0; +} + +void +altcp_default_setprio(struct altcp_pcb *conn, u8_t prio) +{ + if (conn && conn->inner_conn) { + altcp_setprio(conn->inner_conn, prio); + } +} + +void +altcp_default_dealloc(struct altcp_pcb *conn) +{ + LWIP_UNUSED_ARG(conn); + /* nothing to do */ +} + +err_t +altcp_default_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port) +{ + if (conn && conn->inner_conn) { + return altcp_get_tcp_addrinfo(conn->inner_conn, local, addr, port); + } + return ERR_VAL; +} + +ip_addr_t * +altcp_default_get_ip(struct altcp_pcb *conn, int local) +{ + if (conn && conn->inner_conn) { + return altcp_get_ip(conn->inner_conn, local); + } + return NULL; +} + +u16_t +altcp_default_get_port(struct altcp_pcb *conn, int local) +{ + if (conn && conn->inner_conn) { + return altcp_get_port(conn->inner_conn, local); + } + return 0; +} + +#ifdef LWIP_DEBUG +enum tcp_state +altcp_default_dbg_get_tcp_state(struct altcp_pcb *conn) +{ + if (conn && conn->inner_conn) { + return altcp_dbg_get_tcp_state(conn->inner_conn); + } + return CLOSED; +} +#endif + + +#endif /* LWIP_ALTCP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c b/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c new file mode 100644 index 0000000..cd619bc --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/altcp_alloc.c @@ -0,0 +1,87 @@ +/** + * @file + * Application layered TCP connection API (to be used from TCPIP thread)\n + * This interface mimics the tcp callback API to the application while preventing + * direct linking (much like virtual functions). + * This way, an application can make use of other application layer protocols + * on top of TCP without knowing the details (e.g. TLS, proxy connection). + * + * This file contains allocation implementation that combine several layers. + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/altcp.h" +#include "lwip/altcp_tcp.h" +#include "lwip/altcp_tls.h" +#include "lwip/priv/altcp_priv.h" +#include "lwip/mem.h" + +#include + +#if LWIP_ALTCP_TLS + +/** This standard allocator function creates an altcp pcb for + * TLS over TCP */ +struct altcp_pcb * +altcp_tls_new(struct altcp_tls_config *config, u8_t ip_type) +{ + struct altcp_pcb *inner_conn, *ret; + LWIP_UNUSED_ARG(ip_type); + + inner_conn = altcp_tcp_new_ip_type(ip_type); + if (inner_conn == NULL) { + return NULL; + } + ret = altcp_tls_wrap(config, inner_conn); + if (ret == NULL) { + altcp_close(inner_conn); + } + return ret; +} + +/** This standard allocator function creates an altcp pcb for + * TLS over TCP */ +struct altcp_pcb * +altcp_tls_alloc(void *arg, u8_t ip_type) +{ + return altcp_tls_new((struct altcp_tls_config *)arg, ip_type); +} + +#endif /* LWIP_ALTCP_TLS */ + +#endif /* LWIP_ALTCP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c b/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c new file mode 100644 index 0000000..b715f04 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/altcp_tcp.c @@ -0,0 +1,543 @@ +/** + * @file + * Application layered TCP connection API (to be used from TCPIP thread)\n + * This interface mimics the tcp callback API to the application while preventing + * direct linking (much like virtual functions). + * This way, an application can make use of other application layer protocols + * on top of TCP without knowing the details (e.g. TLS, proxy connection). + * + * This file contains the base implementation calling into tcp. + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/altcp.h" +#include "lwip/altcp_tcp.h" +#include "lwip/priv/altcp_priv.h" +#include "lwip/tcp.h" +#include "lwip/mem.h" + +#include + +#define ALTCP_TCP_ASSERT_CONN(conn) do { \ + LWIP_ASSERT("conn->inner_conn == NULL", (conn)->inner_conn == NULL); \ + LWIP_UNUSED_ARG(conn); /* for LWIP_NOASSERT */ } while(0) +#define ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb) do { \ + LWIP_ASSERT("pcb mismatch", (conn)->state == tpcb); \ + LWIP_UNUSED_ARG(tpcb); /* for LWIP_NOASSERT */ \ + ALTCP_TCP_ASSERT_CONN(conn); } while(0) + + +/* Variable prototype, the actual declaration is at the end of this file + since it contains pointers to static functions declared here */ +extern const struct altcp_functions altcp_tcp_functions; + +static void altcp_tcp_setup(struct altcp_pcb *conn, struct tcp_pcb *tpcb); + +/* callback functions for TCP */ +static err_t +altcp_tcp_accept(void *arg, struct tcp_pcb *new_tpcb, err_t err) +{ + struct altcp_pcb *listen_conn = (struct altcp_pcb *)arg; + if (listen_conn && listen_conn->accept) { + /* create a new altcp_conn to pass to the next 'accept' callback */ + struct altcp_pcb *new_conn = altcp_alloc(); + if (new_conn == NULL) { + return ERR_MEM; + } + altcp_tcp_setup(new_conn, new_tpcb); + return listen_conn->accept(listen_conn->arg, new_conn, err); + } + return ERR_ARG; +} + +static err_t +altcp_tcp_connected(void *arg, struct tcp_pcb *tpcb, err_t err) +{ + struct altcp_pcb *conn = (struct altcp_pcb *)arg; + if (conn) { + ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb); + if (conn->connected) { + return conn->connected(conn->arg, conn, err); + } + } + return ERR_OK; +} + +static err_t +altcp_tcp_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) +{ + struct altcp_pcb *conn = (struct altcp_pcb *)arg; + if (conn) { + ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb); + if (conn->recv) { + return conn->recv(conn->arg, conn, p, err); + } + } + if (p != NULL) { + /* prevent memory leaks */ + pbuf_free(p); + } + return ERR_OK; +} + +static err_t +altcp_tcp_sent(void *arg, struct tcp_pcb *tpcb, u16_t len) +{ + struct altcp_pcb *conn = (struct altcp_pcb *)arg; + if (conn) { + ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb); + if (conn->sent) { + return conn->sent(conn->arg, conn, len); + } + } + return ERR_OK; +} + +static err_t +altcp_tcp_poll(void *arg, struct tcp_pcb *tpcb) +{ + struct altcp_pcb *conn = (struct altcp_pcb *)arg; + if (conn) { + ALTCP_TCP_ASSERT_CONN_PCB(conn, tpcb); + if (conn->poll) { + return conn->poll(conn->arg, conn); + } + } + return ERR_OK; +} + +static void +altcp_tcp_err(void *arg, err_t err) +{ + struct altcp_pcb *conn = (struct altcp_pcb *)arg; + if (conn) { + conn->state = NULL; /* already freed */ + if (conn->err) { + conn->err(conn->arg, err); + } + altcp_free(conn); + } +} + +/* setup functions */ + +static void +altcp_tcp_remove_callbacks(struct tcp_pcb *tpcb) +{ + tcp_arg(tpcb, NULL); + tcp_recv(tpcb, NULL); + tcp_sent(tpcb, NULL); + tcp_err(tpcb, NULL); + tcp_poll(tpcb, NULL, tpcb->pollinterval); +} + +static void +altcp_tcp_setup_callbacks(struct altcp_pcb *conn, struct tcp_pcb *tpcb) +{ + tcp_arg(tpcb, conn); + tcp_recv(tpcb, altcp_tcp_recv); + tcp_sent(tpcb, altcp_tcp_sent); + tcp_err(tpcb, altcp_tcp_err); + /* tcp_poll is set when interval is set by application */ + /* listen is set totally different :-) */ +} + +static void +altcp_tcp_setup(struct altcp_pcb *conn, struct tcp_pcb *tpcb) +{ + altcp_tcp_setup_callbacks(conn, tpcb); + conn->state = tpcb; + conn->fns = &altcp_tcp_functions; +} + +struct altcp_pcb * +altcp_tcp_new_ip_type(u8_t ip_type) +{ + /* Allocate the tcp pcb first to invoke the priority handling code + if we're out of pcbs */ + struct tcp_pcb *tpcb = tcp_new_ip_type(ip_type); + if (tpcb != NULL) { + struct altcp_pcb *ret = altcp_alloc(); + if (ret != NULL) { + altcp_tcp_setup(ret, tpcb); + return ret; + } else { + /* altcp_pcb allocation failed -> free the tcp_pcb too */ + tcp_close(tpcb); + } + } + return NULL; +} + +/** altcp_tcp allocator function fitting to @ref altcp_allocator_t / @ref altcp_new. +* +* arg pointer is not used for TCP. +*/ +struct altcp_pcb * +altcp_tcp_alloc(void *arg, u8_t ip_type) +{ + LWIP_UNUSED_ARG(arg); + return altcp_tcp_new_ip_type(ip_type); +} + +struct altcp_pcb * +altcp_tcp_wrap(struct tcp_pcb *tpcb) +{ + if (tpcb != NULL) { + struct altcp_pcb *ret = altcp_alloc(); + if (ret != NULL) { + altcp_tcp_setup(ret, tpcb); + return ret; + } + } + return NULL; +} + + +/* "virtual" functions calling into tcp */ +static void +altcp_tcp_set_poll(struct altcp_pcb *conn, u8_t interval) +{ + if (conn != NULL) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + tcp_poll(pcb, altcp_tcp_poll, interval); + } +} + +static void +altcp_tcp_recved(struct altcp_pcb *conn, u16_t len) +{ + if (conn != NULL) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + tcp_recved(pcb, len); + } +} + +static err_t +altcp_tcp_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return ERR_VAL; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + return tcp_bind(pcb, ipaddr, port); +} + +static err_t +altcp_tcp_connect(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return ERR_VAL; + } + ALTCP_TCP_ASSERT_CONN(conn); + conn->connected = connected; + pcb = (struct tcp_pcb *)conn->state; + return tcp_connect(pcb, ipaddr, port, altcp_tcp_connected); +} + +static struct altcp_pcb * +altcp_tcp_listen(struct altcp_pcb *conn, u8_t backlog, err_t *err) +{ + struct tcp_pcb *pcb; + struct tcp_pcb *lpcb; + if (conn == NULL) { + return NULL; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + lpcb = tcp_listen_with_backlog_and_err(pcb, backlog, err); + if (lpcb != NULL) { + conn->state = lpcb; + tcp_accept(lpcb, altcp_tcp_accept); + return conn; + } + return NULL; +} + +static void +altcp_tcp_abort(struct altcp_pcb *conn) +{ + if (conn != NULL) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + if (pcb) { + tcp_abort(pcb); + } + } +} + +static err_t +altcp_tcp_close(struct altcp_pcb *conn) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return ERR_VAL; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + if (pcb) { + err_t err; + tcp_poll_fn oldpoll = pcb->poll; + altcp_tcp_remove_callbacks(pcb); + err = tcp_close(pcb); + if (err != ERR_OK) { + /* not closed, set up all callbacks again */ + altcp_tcp_setup_callbacks(conn, pcb); + /* poll callback is not included in the above */ + tcp_poll(pcb, oldpoll, pcb->pollinterval); + return err; + } + conn->state = NULL; /* unsafe to reference pcb after tcp_close(). */ + } + altcp_free(conn); + return ERR_OK; +} + +static err_t +altcp_tcp_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return ERR_VAL; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + return tcp_shutdown(pcb, shut_rx, shut_tx); +} + +static err_t +altcp_tcp_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return ERR_VAL; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + return tcp_write(pcb, dataptr, len, apiflags); +} + +static err_t +altcp_tcp_output(struct altcp_pcb *conn) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return ERR_VAL; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + return tcp_output(pcb); +} + +static u16_t +altcp_tcp_mss(struct altcp_pcb *conn) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return 0; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + return tcp_mss(pcb); +} + +static u16_t +altcp_tcp_sndbuf(struct altcp_pcb *conn) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return 0; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + return tcp_sndbuf(pcb); +} + +static u16_t +altcp_tcp_sndqueuelen(struct altcp_pcb *conn) +{ + struct tcp_pcb *pcb; + if (conn == NULL) { + return 0; + } + ALTCP_TCP_ASSERT_CONN(conn); + pcb = (struct tcp_pcb *)conn->state; + return tcp_sndqueuelen(pcb); +} + +static void +altcp_tcp_nagle_disable(struct altcp_pcb *conn) +{ + if (conn && conn->state) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + tcp_nagle_disable(pcb); + } +} + +static void +altcp_tcp_nagle_enable(struct altcp_pcb *conn) +{ + if (conn && conn->state) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + tcp_nagle_enable(pcb); + } +} + +static int +altcp_tcp_nagle_disabled(struct altcp_pcb *conn) +{ + if (conn && conn->state) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + return tcp_nagle_disabled(pcb); + } + return 0; +} + +static void +altcp_tcp_setprio(struct altcp_pcb *conn, u8_t prio) +{ + if (conn != NULL) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + tcp_setprio(pcb, prio); + } +} + +static void +altcp_tcp_dealloc(struct altcp_pcb *conn) +{ + LWIP_UNUSED_ARG(conn); + ALTCP_TCP_ASSERT_CONN(conn); + /* no private state to clean up */ +} + +static err_t +altcp_tcp_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port) +{ + if (conn) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + return tcp_tcp_get_tcp_addrinfo(pcb, local, addr, port); + } + return ERR_VAL; +} + +static ip_addr_t * +altcp_tcp_get_ip(struct altcp_pcb *conn, int local) +{ + if (conn) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + if (pcb) { + if (local) { + return &pcb->local_ip; + } else { + return &pcb->remote_ip; + } + } + } + return NULL; +} + +static u16_t +altcp_tcp_get_port(struct altcp_pcb *conn, int local) +{ + if (conn) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + if (pcb) { + if (local) { + return pcb->local_port; + } else { + return pcb->remote_port; + } + } + } + return 0; +} + +#ifdef LWIP_DEBUG +static enum tcp_state +altcp_tcp_dbg_get_tcp_state(struct altcp_pcb *conn) +{ + if (conn) { + struct tcp_pcb *pcb = (struct tcp_pcb *)conn->state; + ALTCP_TCP_ASSERT_CONN(conn); + if (pcb) { + return pcb->state; + } + } + return CLOSED; +} +#endif +const struct altcp_functions altcp_tcp_functions = { + altcp_tcp_set_poll, + altcp_tcp_recved, + altcp_tcp_bind, + altcp_tcp_connect, + altcp_tcp_listen, + altcp_tcp_abort, + altcp_tcp_close, + altcp_tcp_shutdown, + altcp_tcp_write, + altcp_tcp_output, + altcp_tcp_mss, + altcp_tcp_sndbuf, + altcp_tcp_sndqueuelen, + altcp_tcp_nagle_disable, + altcp_tcp_nagle_enable, + altcp_tcp_nagle_disabled, + altcp_tcp_setprio, + altcp_tcp_dealloc, + altcp_tcp_get_tcp_addrinfo, + altcp_tcp_get_ip, + altcp_tcp_get_port +#ifdef LWIP_DEBUG + , altcp_tcp_dbg_get_tcp_state +#endif +}; + +#endif /* LWIP_ALTCP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/def.c b/Middlewares/Third_Party/LwIP/src/core/def.c new file mode 100644 index 0000000..9da36fe --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/def.c @@ -0,0 +1,240 @@ +/** + * @file + * Common functions used throughout the stack. + * + * These are reference implementations of the byte swapping functions. + * Again with the aim of being simple, correct and fully portable. + * Byte swapping is the second thing you would want to optimize. You will + * need to port it to your architecture and in your cc.h: + * + * \#define lwip_htons(x) your_htons + * \#define lwip_htonl(x) your_htonl + * + * Note lwip_ntohs() and lwip_ntohl() are merely references to the htonx counterparts. + * + * If you \#define them to htons() and htonl(), you should + * \#define LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS to prevent lwIP from + * defining htonx/ntohx compatibility macros. + + * @defgroup sys_nonstandard Non-standard functions + * @ingroup sys_layer + * lwIP provides default implementations for non-standard functions. + * These can be mapped to OS functions to reduce code footprint if desired. + * All defines related to this section must not be placed in lwipopts.h, + * but in arch/cc.h! + * These options cannot be \#defined in lwipopts.h since they are not options + * of lwIP itself, but options of the lwIP port to your system. + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "lwip/opt.h" +#include "lwip/def.h" + +#include + +#if BYTE_ORDER == LITTLE_ENDIAN + +#if !defined(lwip_htons) +/** + * Convert an u16_t from host- to network byte order. + * + * @param n u16_t in host byte order + * @return n in network byte order + */ +u16_t +lwip_htons(u16_t n) +{ + return PP_HTONS(n); +} +#endif /* lwip_htons */ + +#if !defined(lwip_htonl) +/** + * Convert an u32_t from host- to network byte order. + * + * @param n u32_t in host byte order + * @return n in network byte order + */ +u32_t +lwip_htonl(u32_t n) +{ + return PP_HTONL(n); +} +#endif /* lwip_htonl */ + +#endif /* BYTE_ORDER == LITTLE_ENDIAN */ + +#ifndef lwip_strnstr +/** + * @ingroup sys_nonstandard + * lwIP default implementation for strnstr() non-standard function. + * This can be \#defined to strnstr() depending on your platform port. + */ +char * +lwip_strnstr(const char *buffer, const char *token, size_t n) +{ + const char *p; + size_t tokenlen = strlen(token); + if (tokenlen == 0) { + return LWIP_CONST_CAST(char *, buffer); + } + for (p = buffer; *p && (p + tokenlen <= buffer + n); p++) { + if ((*p == *token) && (strncmp(p, token, tokenlen) == 0)) { + return LWIP_CONST_CAST(char *, p); + } + } + return NULL; +} +#endif + +#ifndef lwip_stricmp +/** + * @ingroup sys_nonstandard + * lwIP default implementation for stricmp() non-standard function. + * This can be \#defined to stricmp() depending on your platform port. + */ +int +lwip_stricmp(const char *str1, const char *str2) +{ + char c1, c2; + + do { + c1 = *str1++; + c2 = *str2++; + if (c1 != c2) { + char c1_upc = c1 | 0x20; + if ((c1_upc >= 'a') && (c1_upc <= 'z')) { + /* characters are not equal an one is in the alphabet range: + downcase both chars and check again */ + char c2_upc = c2 | 0x20; + if (c1_upc != c2_upc) { + /* still not equal */ + /* don't care for < or > */ + return 1; + } + } else { + /* characters are not equal but none is in the alphabet range */ + return 1; + } + } + } while (c1 != 0); + return 0; +} +#endif + +#ifndef lwip_strnicmp +/** + * @ingroup sys_nonstandard + * lwIP default implementation for strnicmp() non-standard function. + * This can be \#defined to strnicmp() depending on your platform port. + */ +int +lwip_strnicmp(const char *str1, const char *str2, size_t len) +{ + char c1, c2; + + do { + c1 = *str1++; + c2 = *str2++; + if (c1 != c2) { + char c1_upc = c1 | 0x20; + if ((c1_upc >= 'a') && (c1_upc <= 'z')) { + /* characters are not equal an one is in the alphabet range: + downcase both chars and check again */ + char c2_upc = c2 | 0x20; + if (c1_upc != c2_upc) { + /* still not equal */ + /* don't care for < or > */ + return 1; + } + } else { + /* characters are not equal but none is in the alphabet range */ + return 1; + } + } + len--; + } while ((len != 0) && (c1 != 0)); + return 0; +} +#endif + +#ifndef lwip_itoa +/** + * @ingroup sys_nonstandard + * lwIP default implementation for itoa() non-standard function. + * This can be \#defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform port. + */ +void +lwip_itoa(char *result, size_t bufsize, int number) +{ + char *res = result; + char *tmp = result + bufsize - 1; + int n = (number >= 0) ? number : -number; + + /* handle invalid bufsize */ + if (bufsize < 2) { + if (bufsize == 1) { + *result = 0; + } + return; + } + + /* First, add sign */ + if (number < 0) { + *res++ = '-'; + } + /* Then create the string from the end and stop if buffer full, + and ensure output string is zero terminated */ + *tmp = 0; + while ((n != 0) && (tmp > res)) { + char val = (char)('0' + (n % 10)); + tmp--; + *tmp = val; + n = n / 10; + } + if (n) { + /* buffer is too small */ + *result = 0; + return; + } + if (*tmp == 0) { + /* Nothing added? */ + *res++ = '0'; + *res++ = 0; + return; + } + /* move from temporary buffer to output buffer (sign is not moved) */ + memmove(res, tmp, (size_t)((result + bufsize) - tmp)); +} +#endif diff --git a/Middlewares/Third_Party/LwIP/src/core/dns.c b/Middlewares/Third_Party/LwIP/src/core/dns.c new file mode 100644 index 0000000..9d2f61e --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/dns.c @@ -0,0 +1,1631 @@ +/** + * @file + * DNS - host name to IP address resolver. + * + * @defgroup dns DNS + * @ingroup callbackstyle_api + * + * Implements a DNS host name to IP address resolver. + * + * The lwIP DNS resolver functions are used to lookup a host name and + * map it to a numerical IP address. It maintains a list of resolved + * hostnames that can be queried with the dns_lookup() function. + * New hostnames can be resolved using the dns_query() function. + * + * The lwIP version of the resolver also adds a non-blocking version of + * gethostbyname() that will work with a raw API application. This function + * checks for an IP address string first and converts it if it is valid. + * gethostbyname() then does a dns_lookup() to see if the name is + * already in the table. If so, the IP is returned. If not, a query is + * issued and the function returns with a ERR_INPROGRESS status. The app + * using the dns client must then go into a waiting state. + * + * Once a hostname has been resolved (or found to be non-existent), + * the resolver code calls a specified callback function (which + * must be implemented by the module that uses the resolver). + * + * Multicast DNS queries are supported for names ending on ".local". + * However, only "One-Shot Multicast DNS Queries" are supported (RFC 6762 + * chapter 5.1), this is not a fully compliant implementation of continuous + * mDNS querying! + * + * All functions must be called from TCPIP thread. + * + * @see DNS_MAX_SERVERS + * @see LWIP_DHCP_MAX_DNS_SERVERS + * @see @ref netconn_common for thread-safe access. + */ + +/* + * Port to lwIP from uIP + * by Jim Pettinato April 2007 + * + * security fixes and more by Simon Goldschmidt + * + * uIP version Copyright (c) 2002-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/*----------------------------------------------------------------------------- + * RFC 1035 - Domain names - implementation and specification + * RFC 2181 - Clarifications to the DNS Specification + *----------------------------------------------------------------------------*/ + +/** @todo: define good default values (rfc compliance) */ +/** @todo: improve answer parsing, more checkings... */ +/** @todo: check RFC1035 - 7.3. Processing responses */ +/** @todo: one-shot mDNS: dual-stack fallback to another IP version */ + +/*----------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "lwip/opt.h" + +#if LWIP_DNS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/udp.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/dns.h" +#include "lwip/prot/dns.h" + +#include + +/** Random generator function to create random TXIDs and source ports for queries */ +#ifndef DNS_RAND_TXID +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_XID) != 0) +#define DNS_RAND_TXID LWIP_RAND +#else +static u16_t dns_txid; +#define DNS_RAND_TXID() (++dns_txid) +#endif +#endif + +/** Limits the source port to be >= 1024 by default */ +#ifndef DNS_PORT_ALLOWED +#define DNS_PORT_ALLOWED(port) ((port) >= 1024) +#endif + +/** DNS resource record max. TTL (one week as default) */ +#ifndef DNS_MAX_TTL +#define DNS_MAX_TTL 604800 +#elif DNS_MAX_TTL > 0x7FFFFFFF +#error DNS_MAX_TTL must be a positive 32-bit value +#endif + +#if DNS_TABLE_SIZE > 255 +#error DNS_TABLE_SIZE must fit into an u8_t +#endif +#if DNS_MAX_SERVERS > 255 +#error DNS_MAX_SERVERS must fit into an u8_t +#endif + +/* The number of parallel requests (i.e. calls to dns_gethostbyname + * that cannot be answered from the DNS table. + * This is set to the table size by default. + */ +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) +#ifndef DNS_MAX_REQUESTS +#define DNS_MAX_REQUESTS DNS_TABLE_SIZE +#else +#if DNS_MAX_REQUESTS > 255 +#error DNS_MAX_REQUESTS must fit into an u8_t +#endif +#endif +#else +/* In this configuration, both arrays have to have the same size and are used + * like one entry (used/free) */ +#define DNS_MAX_REQUESTS DNS_TABLE_SIZE +#endif + +/* The number of UDP source ports used in parallel */ +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) +#ifndef DNS_MAX_SOURCE_PORTS +#define DNS_MAX_SOURCE_PORTS DNS_MAX_REQUESTS +#else +#if DNS_MAX_SOURCE_PORTS > 255 +#error DNS_MAX_SOURCE_PORTS must fit into an u8_t +#endif +#endif +#else +#ifdef DNS_MAX_SOURCE_PORTS +#undef DNS_MAX_SOURCE_PORTS +#endif +#define DNS_MAX_SOURCE_PORTS 1 +#endif + +#if LWIP_IPV4 && LWIP_IPV6 +#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) (((t) == LWIP_DNS_ADDRTYPE_IPV6_IPV4) || ((t) == LWIP_DNS_ADDRTYPE_IPV6)) +#define LWIP_DNS_ADDRTYPE_MATCH_IP(t, ip) (IP_IS_V6_VAL(ip) ? LWIP_DNS_ADDRTYPE_IS_IPV6(t) : (!LWIP_DNS_ADDRTYPE_IS_IPV6(t))) +#define LWIP_DNS_ADDRTYPE_ARG(x) , x +#define LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(x) x +#define LWIP_DNS_SET_ADDRTYPE(x, y) do { x = y; } while(0) +#else +#if LWIP_IPV6 +#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) 1 +#else +#define LWIP_DNS_ADDRTYPE_IS_IPV6(t) 0 +#endif +#define LWIP_DNS_ADDRTYPE_MATCH_IP(t, ip) 1 +#define LWIP_DNS_ADDRTYPE_ARG(x) +#define LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(x) 0 +#define LWIP_DNS_SET_ADDRTYPE(x, y) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +#if LWIP_DNS_SUPPORT_MDNS_QUERIES +#define LWIP_DNS_ISMDNS_ARG(x) , x +#else +#define LWIP_DNS_ISMDNS_ARG(x) +#endif + +/** DNS query message structure. + No packing needed: only used locally on the stack. */ +struct dns_query { + /* DNS query record starts with either a domain name or a pointer + to a name already present somewhere in the packet. */ + u16_t type; + u16_t cls; +}; +#define SIZEOF_DNS_QUERY 4 + +/** DNS answer message structure. + No packing needed: only used locally on the stack. */ +struct dns_answer { + /* DNS answer record starts with either a domain name or a pointer + to a name already present somewhere in the packet. */ + u16_t type; + u16_t cls; + u32_t ttl; + u16_t len; +}; +#define SIZEOF_DNS_ANSWER 10 +/* maximum allowed size for the struct due to non-packed */ +#define SIZEOF_DNS_ANSWER_ASSERT 12 + +/* DNS table entry states */ +typedef enum { + DNS_STATE_UNUSED = 0, + DNS_STATE_NEW = 1, + DNS_STATE_ASKING = 2, + DNS_STATE_DONE = 3 +} dns_state_enum_t; + +/** DNS table entry */ +struct dns_table_entry { + u32_t ttl; + ip_addr_t ipaddr; + u16_t txid; + u8_t state; + u8_t server_idx; + u8_t tmr; + u8_t retries; + u8_t seqno; +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) + u8_t pcb_idx; +#endif + char name[DNS_MAX_NAME_LENGTH]; +#if LWIP_IPV4 && LWIP_IPV6 + u8_t reqaddrtype; +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + u8_t is_mdns; +#endif +}; + +/** DNS request table entry: used when dns_gehostbyname cannot answer the + * request from the DNS table */ +struct dns_req_entry { + /* pointer to callback on DNS query done */ + dns_found_callback found; + /* argument passed to the callback function */ + void *arg; +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) + u8_t dns_table_idx; +#endif +#if LWIP_IPV4 && LWIP_IPV6 + u8_t reqaddrtype; +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +}; + +#if DNS_LOCAL_HOSTLIST + +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +/** Local host-list. For hostnames in this list, no + * external name resolution is performed */ +static struct local_hostlist_entry *local_hostlist_dynamic; +#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/** Defining this allows the local_hostlist_static to be placed in a different + * linker section (e.g. FLASH) */ +#ifndef DNS_LOCAL_HOSTLIST_STORAGE_PRE +#define DNS_LOCAL_HOSTLIST_STORAGE_PRE static +#endif /* DNS_LOCAL_HOSTLIST_STORAGE_PRE */ +/** Defining this allows the local_hostlist_static to be placed in a different + * linker section (e.g. FLASH) */ +#ifndef DNS_LOCAL_HOSTLIST_STORAGE_POST +#define DNS_LOCAL_HOSTLIST_STORAGE_POST +#endif /* DNS_LOCAL_HOSTLIST_STORAGE_POST */ +DNS_LOCAL_HOSTLIST_STORAGE_PRE struct local_hostlist_entry local_hostlist_static[] + DNS_LOCAL_HOSTLIST_STORAGE_POST = DNS_LOCAL_HOSTLIST_INIT; + +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +static void dns_init_local(void); +static err_t dns_lookup_local(const char *hostname, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype)); +#endif /* DNS_LOCAL_HOSTLIST */ + + +/* forward declarations */ +static void dns_recv(void *s, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port); +static void dns_check_entries(void); +static void dns_call_found(u8_t idx, ip_addr_t *addr); + +/*----------------------------------------------------------------------------- + * Globals + *----------------------------------------------------------------------------*/ + +/* DNS variables */ +static struct udp_pcb *dns_pcbs[DNS_MAX_SOURCE_PORTS]; +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) +static u8_t dns_last_pcb_idx; +#endif +static u8_t dns_seqno; +static struct dns_table_entry dns_table[DNS_TABLE_SIZE]; +static struct dns_req_entry dns_requests[DNS_MAX_REQUESTS]; +static ip_addr_t dns_servers[DNS_MAX_SERVERS]; + +#if LWIP_IPV4 +const ip_addr_t dns_mquery_v4group = DNS_MQUERY_IPV4_GROUP_INIT; +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 +const ip_addr_t dns_mquery_v6group = DNS_MQUERY_IPV6_GROUP_INIT; +#endif /* LWIP_IPV6 */ + +/** + * Initialize the resolver: set up the UDP pcb and configure the default server + * (if DNS_SERVER_ADDRESS is set). + */ +void +dns_init(void) +{ +#ifdef DNS_SERVER_ADDRESS + /* initialize default DNS server address */ + ip_addr_t dnsserver; + DNS_SERVER_ADDRESS(&dnsserver); + dns_setserver(0, &dnsserver); +#endif /* DNS_SERVER_ADDRESS */ + + LWIP_ASSERT("sanity check SIZEOF_DNS_QUERY", + sizeof(struct dns_query) == SIZEOF_DNS_QUERY); + LWIP_ASSERT("sanity check SIZEOF_DNS_ANSWER", + sizeof(struct dns_answer) <= SIZEOF_DNS_ANSWER_ASSERT); + + LWIP_DEBUGF(DNS_DEBUG, ("dns_init: initializing\n")); + + /* if dns client not yet initialized... */ +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) == 0) + if (dns_pcbs[0] == NULL) { + dns_pcbs[0] = udp_new_ip_type(IPADDR_TYPE_ANY); + LWIP_ASSERT("dns_pcbs[0] != NULL", dns_pcbs[0] != NULL); + + /* initialize DNS table not needed (initialized to zero since it is a + * global variable) */ + LWIP_ASSERT("For implicit initialization to work, DNS_STATE_UNUSED needs to be 0", + DNS_STATE_UNUSED == 0); + + /* initialize DNS client */ + udp_bind(dns_pcbs[0], IP_ANY_TYPE, 0); + udp_recv(dns_pcbs[0], dns_recv, NULL); + } +#endif + +#if DNS_LOCAL_HOSTLIST + dns_init_local(); +#endif +} + +/** + * @ingroup dns + * Initialize one of the DNS servers. + * + * @param numdns the index of the DNS server to set must be < DNS_MAX_SERVERS + * @param dnsserver IP address of the DNS server to set + */ +void +dns_setserver(u8_t numdns, const ip_addr_t *dnsserver) +{ + if (numdns < DNS_MAX_SERVERS) { + if (dnsserver != NULL) { + dns_servers[numdns] = (*dnsserver); + } else { + dns_servers[numdns] = *IP_ADDR_ANY; + } + } +} + +/** + * @ingroup dns + * Obtain one of the currently configured DNS server. + * + * @param numdns the index of the DNS server + * @return IP address of the indexed DNS server or "ip_addr_any" if the DNS + * server has not been configured. + */ +const ip_addr_t * +dns_getserver(u8_t numdns) +{ + if (numdns < DNS_MAX_SERVERS) { + return &dns_servers[numdns]; + } else { + return IP_ADDR_ANY; + } +} + +/** + * The DNS resolver client timer - handle retries and timeouts and should + * be called every DNS_TMR_INTERVAL milliseconds (every second by default). + */ +void +dns_tmr(void) +{ + LWIP_DEBUGF(DNS_DEBUG, ("dns_tmr: dns_check_entries\n")); + dns_check_entries(); +} + +#if DNS_LOCAL_HOSTLIST +static void +dns_init_local(void) +{ +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) + size_t i; + struct local_hostlist_entry *entry; + /* Dynamic: copy entries from DNS_LOCAL_HOSTLIST_INIT to list */ + struct local_hostlist_entry local_hostlist_init[] = DNS_LOCAL_HOSTLIST_INIT; + size_t namelen; + for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_init); i++) { + struct local_hostlist_entry *init_entry = &local_hostlist_init[i]; + LWIP_ASSERT("invalid host name (NULL)", init_entry->name != NULL); + namelen = strlen(init_entry->name); + LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN); + entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST); + LWIP_ASSERT("mem-error in dns_init_local", entry != NULL); + if (entry != NULL) { + char *entry_name = (char *)entry + sizeof(struct local_hostlist_entry); + MEMCPY(entry_name, init_entry->name, namelen); + entry_name[namelen] = 0; + entry->name = entry_name; + entry->addr = init_entry->addr; + entry->next = local_hostlist_dynamic; + local_hostlist_dynamic = entry; + } + } +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC && defined(DNS_LOCAL_HOSTLIST_INIT) */ +} + +/** + * @ingroup dns + * Iterate the local host-list for a hostname. + * + * @param iterator_fn a function that is called for every entry in the local host-list + * @param iterator_arg 3rd argument passed to iterator_fn + * @return the number of entries in the local host-list + */ +size_t +dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg) +{ + size_t i; +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC + struct local_hostlist_entry *entry = local_hostlist_dynamic; + i = 0; + while (entry != NULL) { + if (iterator_fn != NULL) { + iterator_fn(entry->name, &entry->addr, iterator_arg); + } + i++; + entry = entry->next; + } +#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_static); i++) { + if (iterator_fn != NULL) { + iterator_fn(local_hostlist_static[i].name, &local_hostlist_static[i].addr, iterator_arg); + } + } +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + return i; +} + +/** + * @ingroup dns + * Scans the local host-list for a hostname. + * + * @param hostname Hostname to look for in the local host-list + * @param addr the first IP address for the hostname in the local host-list or + * IPADDR_NONE if not found. + * @param dns_addrtype - LWIP_DNS_ADDRTYPE_IPV4_IPV6: try to resolve IPv4 (ATTENTION: no fallback here!) + * - LWIP_DNS_ADDRTYPE_IPV6_IPV4: try to resolve IPv6 (ATTENTION: no fallback here!) + * - LWIP_DNS_ADDRTYPE_IPV4: try to resolve IPv4 only + * - LWIP_DNS_ADDRTYPE_IPV6: try to resolve IPv6 only + * @return ERR_OK if found, ERR_ARG if not found + */ +err_t +dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype) +{ + LWIP_UNUSED_ARG(dns_addrtype); + return dns_lookup_local(hostname, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)); +} + +/* Internal implementation for dns_local_lookup and dns_lookup */ +static err_t +dns_lookup_local(const char *hostname, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype)) +{ +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC + struct local_hostlist_entry *entry = local_hostlist_dynamic; + while (entry != NULL) { + if ((lwip_stricmp(entry->name, hostname) == 0) && + LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, entry->addr)) { + if (addr) { + ip_addr_copy(*addr, entry->addr); + } + return ERR_OK; + } + entry = entry->next; + } +#else /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + size_t i; + for (i = 0; i < LWIP_ARRAYSIZE(local_hostlist_static); i++) { + if ((lwip_stricmp(local_hostlist_static[i].name, hostname) == 0) && + LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, local_hostlist_static[i].addr)) { + if (addr) { + ip_addr_copy(*addr, local_hostlist_static[i].addr); + } + return ERR_OK; + } + } +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + return ERR_ARG; +} + +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +/** + * @ingroup dns + * Remove all entries from the local host-list for a specific hostname + * and/or IP address + * + * @param hostname hostname for which entries shall be removed from the local + * host-list + * @param addr address for which entries shall be removed from the local host-list + * @return the number of removed entries + */ +int +dns_local_removehost(const char *hostname, const ip_addr_t *addr) +{ + int removed = 0; + struct local_hostlist_entry *entry = local_hostlist_dynamic; + struct local_hostlist_entry *last_entry = NULL; + while (entry != NULL) { + if (((hostname == NULL) || !lwip_stricmp(entry->name, hostname)) && + ((addr == NULL) || ip_addr_cmp(&entry->addr, addr))) { + struct local_hostlist_entry *free_entry; + if (last_entry != NULL) { + last_entry->next = entry->next; + } else { + local_hostlist_dynamic = entry->next; + } + free_entry = entry; + entry = entry->next; + memp_free(MEMP_LOCALHOSTLIST, free_entry); + removed++; + } else { + last_entry = entry; + entry = entry->next; + } + } + return removed; +} + +/** + * @ingroup dns + * Add a hostname/IP address pair to the local host-list. + * Duplicates are not checked. + * + * @param hostname hostname of the new entry + * @param addr IP address of the new entry + * @return ERR_OK if succeeded or ERR_MEM on memory error + */ +err_t +dns_local_addhost(const char *hostname, const ip_addr_t *addr) +{ + struct local_hostlist_entry *entry; + size_t namelen; + char *entry_name; + LWIP_ASSERT("invalid host name (NULL)", hostname != NULL); + namelen = strlen(hostname); + LWIP_ASSERT("namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN", namelen <= DNS_LOCAL_HOSTLIST_MAX_NAMELEN); + entry = (struct local_hostlist_entry *)memp_malloc(MEMP_LOCALHOSTLIST); + if (entry == NULL) { + return ERR_MEM; + } + entry_name = (char *)entry + sizeof(struct local_hostlist_entry); + MEMCPY(entry_name, hostname, namelen); + entry_name[namelen] = 0; + entry->name = entry_name; + ip_addr_copy(entry->addr, *addr); + entry->next = local_hostlist_dynamic; + local_hostlist_dynamic = entry; + return ERR_OK; +} +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC*/ +#endif /* DNS_LOCAL_HOSTLIST */ + +/** + * @ingroup dns + * Look up a hostname in the array of known hostnames. + * + * @note This function only looks in the internal array of known + * hostnames, it does not send out a query for the hostname if none + * was found. The function dns_enqueue() can be used to send a query + * for a hostname. + * + * @param name the hostname to look up + * @param addr the hostname's IP address, as u32_t (instead of ip_addr_t to + * better check for failure: != IPADDR_NONE) or IPADDR_NONE if the hostname + * was not found in the cached dns_table. + * @return ERR_OK if found, ERR_ARG if not found + */ +static err_t +dns_lookup(const char *name, ip_addr_t *addr LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype)) +{ + u8_t i; +#if DNS_LOCAL_HOSTLIST + if (dns_lookup_local(name, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)) == ERR_OK) { + return ERR_OK; + } +#endif /* DNS_LOCAL_HOSTLIST */ +#ifdef DNS_LOOKUP_LOCAL_EXTERN + if (DNS_LOOKUP_LOCAL_EXTERN(name, addr, LWIP_DNS_ADDRTYPE_ARG_OR_ZERO(dns_addrtype)) == ERR_OK) { + return ERR_OK; + } +#endif /* DNS_LOOKUP_LOCAL_EXTERN */ + + /* Walk through name list, return entry if found. If not, return NULL. */ + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + if ((dns_table[i].state == DNS_STATE_DONE) && + (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0) && + LWIP_DNS_ADDRTYPE_MATCH_IP(dns_addrtype, dns_table[i].ipaddr)) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_lookup: \"%s\": found = ", name)); + ip_addr_debug_print_val(DNS_DEBUG, dns_table[i].ipaddr); + LWIP_DEBUGF(DNS_DEBUG, ("\n")); + if (addr) { + ip_addr_copy(*addr, dns_table[i].ipaddr); + } + return ERR_OK; + } + } + + return ERR_ARG; +} + +/** + * Compare the "dotted" name "query" with the encoded name "response" + * to make sure an answer from the DNS server matches the current dns_table + * entry (otherwise, answers might arrive late for hostname not on the list + * any more). + * + * For now, this function compares case-insensitive to cope with all kinds of + * servers. This also means that "dns 0x20 bit encoding" must be checked + * externally, if we want to implement it. + * Currently, the request is sent exactly as passed in by he user request. + * + * @param query hostname (not encoded) from the dns_table + * @param p pbuf containing the encoded hostname in the DNS response + * @param start_offset offset into p where the name starts + * @return 0xFFFF: names differ, other: names equal -> offset behind name + */ +static u16_t +dns_compare_name(const char *query, struct pbuf *p, u16_t start_offset) +{ + int n; + u16_t response_offset = start_offset; + + do { + n = pbuf_try_get_at(p, response_offset); + if ((n < 0) || (response_offset == 0xFFFF)) { + /* error or overflow */ + return 0xFFFF; + } + response_offset++; + /** @see RFC 1035 - 4.1.4. Message compression */ + if ((n & 0xc0) == 0xc0) { + /* Compressed name: cannot be equal since we don't send them */ + return 0xFFFF; + } else { + /* Not compressed name */ + while (n > 0) { + int c = pbuf_try_get_at(p, response_offset); + if (c < 0) { + return 0xFFFF; + } + if (lwip_tolower((*query)) != lwip_tolower((u8_t)c)) { + return 0xFFFF; + } + if (response_offset == 0xFFFF) { + /* would overflow */ + return 0xFFFF; + } + response_offset++; + ++query; + --n; + } + ++query; + } + n = pbuf_try_get_at(p, response_offset); + if (n < 0) { + return 0xFFFF; + } + } while (n != 0); + + if (response_offset == 0xFFFF) { + /* would overflow */ + return 0xFFFF; + } + return (u16_t)(response_offset + 1); +} + +/** + * Walk through a compact encoded DNS name and return the end of the name. + * + * @param p pbuf containing the name + * @param query_idx start index into p pointing to encoded DNS name in the DNS server response + * @return index to end of the name + */ +static u16_t +dns_skip_name(struct pbuf *p, u16_t query_idx) +{ + int n; + u16_t offset = query_idx; + + do { + n = pbuf_try_get_at(p, offset++); + if ((n < 0) || (offset == 0)) { + return 0xFFFF; + } + /** @see RFC 1035 - 4.1.4. Message compression */ + if ((n & 0xc0) == 0xc0) { + /* Compressed name: since we only want to skip it (not check it), stop here */ + break; + } else { + /* Not compressed name */ + if (offset + n >= p->tot_len) { + return 0xFFFF; + } + offset = (u16_t)(offset + n); + } + n = pbuf_try_get_at(p, offset); + if (n < 0) { + return 0xFFFF; + } + } while (n != 0); + + if (offset == 0xFFFF) { + return 0xFFFF; + } + return (u16_t)(offset + 1); +} + +/** + * Send a DNS query packet. + * + * @param idx the DNS table entry index for which to send a request + * @return ERR_OK if packet is sent; an err_t indicating the problem otherwise + */ +static err_t +dns_send(u8_t idx) +{ + err_t err; + struct dns_hdr hdr; + struct dns_query qry; + struct pbuf *p; + u16_t query_idx, copy_len; + const char *hostname, *hostname_part; + u8_t n; + u8_t pcb_idx; + struct dns_table_entry *entry = &dns_table[idx]; + + LWIP_DEBUGF(DNS_DEBUG, ("dns_send: dns_servers[%"U16_F"] \"%s\": request\n", + (u16_t)(entry->server_idx), entry->name)); + LWIP_ASSERT("dns server out of array", entry->server_idx < DNS_MAX_SERVERS); + if (ip_addr_isany_val(dns_servers[entry->server_idx]) +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + && !entry->is_mdns +#endif + ) { + /* DNS server not valid anymore, e.g. PPP netif has been shut down */ + /* call specified callback function if provided */ + dns_call_found(idx, NULL); + /* flush this entry */ + entry->state = DNS_STATE_UNUSED; + return ERR_OK; + } + + /* if here, we have either a new query or a retry on a previous query to process */ + p = pbuf_alloc(PBUF_TRANSPORT, (u16_t)(SIZEOF_DNS_HDR + strlen(entry->name) + 2 + + SIZEOF_DNS_QUERY), PBUF_RAM); + if (p != NULL) { + const ip_addr_t *dst; + u16_t dst_port; + /* fill dns header */ + memset(&hdr, 0, SIZEOF_DNS_HDR); + hdr.id = lwip_htons(entry->txid); + hdr.flags1 = DNS_FLAG1_RD; + hdr.numquestions = PP_HTONS(1); + pbuf_take(p, &hdr, SIZEOF_DNS_HDR); + hostname = entry->name; + --hostname; + + /* convert hostname into suitable query format. */ + query_idx = SIZEOF_DNS_HDR; + do { + ++hostname; + hostname_part = hostname; + for (n = 0; *hostname != '.' && *hostname != 0; ++hostname) { + ++n; + } + copy_len = (u16_t)(hostname - hostname_part); + if (query_idx + n + 1 > 0xFFFF) { + /* u16_t overflow */ + goto overflow_return; + } + pbuf_put_at(p, query_idx, n); + pbuf_take_at(p, hostname_part, copy_len, (u16_t)(query_idx + 1)); + query_idx = (u16_t)(query_idx + n + 1); + } while (*hostname != 0); + pbuf_put_at(p, query_idx, 0); + query_idx++; + + /* fill dns query */ + if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) { + qry.type = PP_HTONS(DNS_RRTYPE_AAAA); + } else { + qry.type = PP_HTONS(DNS_RRTYPE_A); + } + qry.cls = PP_HTONS(DNS_RRCLASS_IN); + pbuf_take_at(p, &qry, SIZEOF_DNS_QUERY, query_idx); + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) + pcb_idx = entry->pcb_idx; +#else + pcb_idx = 0; +#endif + /* send dns packet */ + LWIP_DEBUGF(DNS_DEBUG, ("sending DNS request ID %d for name \"%s\" to server %d\r\n", + entry->txid, entry->name, entry->server_idx)); +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + if (entry->is_mdns) { + dst_port = DNS_MQUERY_PORT; +#if LWIP_IPV6 + if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) { + dst = &dns_mquery_v6group; + } +#endif +#if LWIP_IPV4 && LWIP_IPV6 + else +#endif +#if LWIP_IPV4 + { + dst = &dns_mquery_v4group; + } +#endif + } else +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + { + dst_port = DNS_SERVER_PORT; + dst = &dns_servers[entry->server_idx]; + } + err = udp_sendto(dns_pcbs[pcb_idx], p, dst, dst_port); + + /* free pbuf */ + pbuf_free(p); + } else { + err = ERR_MEM; + } + + return err; +overflow_return: + pbuf_free(p); + return ERR_VAL; +} + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) +static struct udp_pcb * +dns_alloc_random_port(void) +{ + err_t err; + struct udp_pcb *pcb; + + pcb = udp_new_ip_type(IPADDR_TYPE_ANY); + if (pcb == NULL) { + /* out of memory, have to reuse an existing pcb */ + return NULL; + } + do { + u16_t port = (u16_t)DNS_RAND_TXID(); + if (DNS_PORT_ALLOWED(port)) { + err = udp_bind(pcb, IP_ANY_TYPE, port); + } else { + /* this port is not allowed, try again */ + err = ERR_USE; + } + } while (err == ERR_USE); + if (err != ERR_OK) { + udp_remove(pcb); + return NULL; + } + udp_recv(pcb, dns_recv, NULL); + return pcb; +} + +/** + * dns_alloc_pcb() - allocates a new pcb (or reuses an existing one) to be used + * for sending a request + * + * @return an index into dns_pcbs + */ +static u8_t +dns_alloc_pcb(void) +{ + u8_t i; + u8_t idx; + + for (i = 0; i < DNS_MAX_SOURCE_PORTS; i++) { + if (dns_pcbs[i] == NULL) { + break; + } + } + if (i < DNS_MAX_SOURCE_PORTS) { + dns_pcbs[i] = dns_alloc_random_port(); + if (dns_pcbs[i] != NULL) { + /* succeeded */ + dns_last_pcb_idx = i; + return i; + } + } + /* if we come here, creating a new UDP pcb failed, so we have to use + an already existing one (so overflow is no issue) */ + for (i = 0, idx = (u8_t)(dns_last_pcb_idx + 1); i < DNS_MAX_SOURCE_PORTS; i++, idx++) { + if (idx >= DNS_MAX_SOURCE_PORTS) { + idx = 0; + } + if (dns_pcbs[idx] != NULL) { + dns_last_pcb_idx = idx; + return idx; + } + } + return DNS_MAX_SOURCE_PORTS; +} +#endif /* ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) */ + +/** + * dns_call_found() - call the found callback and check if there are duplicate + * entries for the given hostname. If there are any, their found callback will + * be called and they will be removed. + * + * @param idx dns table index of the entry that is resolved or removed + * @param addr IP address for the hostname (or NULL on error or memory shortage) + */ +static void +dns_call_found(u8_t idx, ip_addr_t *addr) +{ +#if ((LWIP_DNS_SECURE & (LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT)) != 0) + u8_t i; +#endif + +#if LWIP_IPV4 && LWIP_IPV6 + if (addr != NULL) { + /* check that address type matches the request and adapt the table entry */ + if (IP_IS_V6_VAL(*addr)) { + LWIP_ASSERT("invalid response", LWIP_DNS_ADDRTYPE_IS_IPV6(dns_table[idx].reqaddrtype)); + dns_table[idx].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV6; + } else { + LWIP_ASSERT("invalid response", !LWIP_DNS_ADDRTYPE_IS_IPV6(dns_table[idx].reqaddrtype)); + dns_table[idx].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV4; + } + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) + for (i = 0; i < DNS_MAX_REQUESTS; i++) { + if (dns_requests[i].found && (dns_requests[i].dns_table_idx == idx)) { + (*dns_requests[i].found)(dns_table[idx].name, addr, dns_requests[i].arg); + /* flush this entry */ + dns_requests[i].found = NULL; + } + } +#else + if (dns_requests[idx].found) { + (*dns_requests[idx].found)(dns_table[idx].name, addr, dns_requests[idx].arg); + } + dns_requests[idx].found = NULL; +#endif +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) + /* close the pcb used unless other request are using it */ + for (i = 0; i < DNS_MAX_REQUESTS; i++) { + if (i == idx) { + continue; /* only check other requests */ + } + if (dns_table[i].state == DNS_STATE_ASKING) { + if (dns_table[i].pcb_idx == dns_table[idx].pcb_idx) { + /* another request is still using the same pcb */ + dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS; + break; + } + } + } + if (dns_table[idx].pcb_idx < DNS_MAX_SOURCE_PORTS) { + /* if we come here, the pcb is not used any more and can be removed */ + udp_remove(dns_pcbs[dns_table[idx].pcb_idx]); + dns_pcbs[dns_table[idx].pcb_idx] = NULL; + dns_table[idx].pcb_idx = DNS_MAX_SOURCE_PORTS; + } +#endif +} + +/* Create a query transmission ID that is unique for all outstanding queries */ +static u16_t +dns_create_txid(void) +{ + u16_t txid; + u8_t i; + +again: + txid = (u16_t)DNS_RAND_TXID(); + + /* check whether the ID is unique */ + for (i = 0; i < DNS_TABLE_SIZE; i++) { + if ((dns_table[i].state == DNS_STATE_ASKING) && + (dns_table[i].txid == txid)) { + /* ID already used by another pending query */ + goto again; + } + } + + return txid; +} + +/** + * Check whether there are other backup DNS servers available to try + */ +static u8_t +dns_backupserver_available(struct dns_table_entry *pentry) +{ + u8_t ret = 0; + + if (pentry) { + if ((pentry->server_idx + 1 < DNS_MAX_SERVERS) && !ip_addr_isany_val(dns_servers[pentry->server_idx + 1])) { + ret = 1; + } + } + + return ret; +} + +/** + * dns_check_entry() - see if entry has not yet been queried and, if so, sends out a query. + * Check an entry in the dns_table: + * - send out query for new entries + * - retry old pending entries on timeout (also with different servers) + * - remove completed entries from the table if their TTL has expired + * + * @param i index of the dns_table entry to check + */ +static void +dns_check_entry(u8_t i) +{ + err_t err; + struct dns_table_entry *entry = &dns_table[i]; + + LWIP_ASSERT("array index out of bounds", i < DNS_TABLE_SIZE); + + switch (entry->state) { + case DNS_STATE_NEW: + /* initialize new entry */ + entry->txid = dns_create_txid(); + entry->state = DNS_STATE_ASKING; + entry->server_idx = 0; + entry->tmr = 1; + entry->retries = 0; + + /* send DNS packet for this entry */ + err = dns_send(i); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("dns_send returned error: %s\n", lwip_strerr(err))); + } + break; + case DNS_STATE_ASKING: + if (--entry->tmr == 0) { + if (++entry->retries == DNS_MAX_RETRIES) { + if (dns_backupserver_available(entry) +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + && !entry->is_mdns +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + ) { + /* change of server */ + entry->server_idx++; + entry->tmr = 1; + entry->retries = 0; + } else { + LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": timeout\n", entry->name)); + /* call specified callback function if provided */ + dns_call_found(i, NULL); + /* flush this entry */ + entry->state = DNS_STATE_UNUSED; + break; + } + } else { + /* wait longer for the next retry */ + entry->tmr = entry->retries; + } + + /* send DNS packet for this entry */ + err = dns_send(i); + if (err != ERR_OK) { + LWIP_DEBUGF(DNS_DEBUG | LWIP_DBG_LEVEL_WARNING, + ("dns_send returned error: %s\n", lwip_strerr(err))); + } + } + break; + case DNS_STATE_DONE: + /* if the time to live is nul */ + if ((entry->ttl == 0) || (--entry->ttl == 0)) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_check_entry: \"%s\": flush\n", entry->name)); + /* flush this entry, there cannot be any related pending entries in this state */ + entry->state = DNS_STATE_UNUSED; + } + break; + case DNS_STATE_UNUSED: + /* nothing to do */ + break; + default: + LWIP_ASSERT("unknown dns_table entry state:", 0); + break; + } +} + +/** + * Call dns_check_entry for each entry in dns_table - check all entries. + */ +static void +dns_check_entries(void) +{ + u8_t i; + + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + dns_check_entry(i); + } +} + +/** + * Save TTL and call dns_call_found for correct response. + */ +static void +dns_correct_response(u8_t idx, u32_t ttl) +{ + struct dns_table_entry *entry = &dns_table[idx]; + + entry->state = DNS_STATE_DONE; + + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response = ", entry->name)); + ip_addr_debug_print_val(DNS_DEBUG, entry->ipaddr); + LWIP_DEBUGF(DNS_DEBUG, ("\n")); + + /* read the answer resource record's TTL, and maximize it if needed */ + entry->ttl = ttl; + if (entry->ttl > DNS_MAX_TTL) { + entry->ttl = DNS_MAX_TTL; + } + dns_call_found(idx, &entry->ipaddr); + + if (entry->ttl == 0) { + /* RFC 883, page 29: "Zero values are + interpreted to mean that the RR can only be used for the + transaction in progress, and should not be cached." + -> flush this entry now */ + /* entry reused during callback? */ + if (entry->state == DNS_STATE_DONE) { + entry->state = DNS_STATE_UNUSED; + } + } +} + +/** + * Receive input function for DNS response packets arriving for the dns UDP pcb. + */ +static void +dns_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) +{ + u8_t i; + u16_t txid; + u16_t res_idx; + struct dns_hdr hdr; + struct dns_answer ans; + struct dns_query qry; + u16_t nquestions, nanswers; + + LWIP_UNUSED_ARG(arg); + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(port); + + /* is the dns message big enough ? */ + if (p->tot_len < (SIZEOF_DNS_HDR + SIZEOF_DNS_QUERY)) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: pbuf too small\n")); + /* free pbuf and return */ + goto ignore_packet; + } + + /* copy dns payload inside static buffer for processing */ + if (pbuf_copy_partial(p, &hdr, SIZEOF_DNS_HDR, 0) == SIZEOF_DNS_HDR) { + /* Match the ID in the DNS header with the name table. */ + txid = lwip_htons(hdr.id); + for (i = 0; i < DNS_TABLE_SIZE; i++) { + struct dns_table_entry *entry = &dns_table[i]; + if ((entry->state == DNS_STATE_ASKING) && + (entry->txid == txid)) { + + /* We only care about the question(s) and the answers. The authrr + and the extrarr are simply discarded. */ + nquestions = lwip_htons(hdr.numquestions); + nanswers = lwip_htons(hdr.numanswers); + + /* Check for correct response. */ + if ((hdr.flags1 & DNS_FLAG1_RESPONSE) == 0) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": not a response\n", entry->name)); + goto ignore_packet; /* ignore this packet */ + } + if (nquestions != 1) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); + goto ignore_packet; /* ignore this packet */ + } + +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + if (!entry->is_mdns) +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + { + /* Check whether response comes from the same network address to which the + question was sent. (RFC 5452) */ + if (!ip_addr_cmp(addr, &dns_servers[entry->server_idx])) { + goto ignore_packet; /* ignore this packet */ + } + } + + /* Check if the name in the "question" part match with the name in the entry and + skip it if equal. */ + res_idx = dns_compare_name(entry->name, p, SIZEOF_DNS_HDR); + if (res_idx == 0xFFFF) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); + goto ignore_packet; /* ignore this packet */ + } + + /* check if "question" part matches the request */ + if (pbuf_copy_partial(p, &qry, SIZEOF_DNS_QUERY, res_idx) != SIZEOF_DNS_QUERY) { + goto ignore_packet; /* ignore this packet */ + } + if ((qry.cls != PP_HTONS(DNS_RRCLASS_IN)) || + (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_AAAA))) || + (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype) && (qry.type != PP_HTONS(DNS_RRTYPE_A)))) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": response not match to query\n", entry->name)); + goto ignore_packet; /* ignore this packet */ + } + /* skip the rest of the "question" part */ + if (res_idx + SIZEOF_DNS_QUERY > 0xFFFF) { + goto ignore_packet; + } + res_idx = (u16_t)(res_idx + SIZEOF_DNS_QUERY); + + /* Check for error. If so, call callback to inform. */ + if (hdr.flags2 & DNS_FLAG2_ERR_MASK) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in flags\n", entry->name)); + + /* if there is another backup DNS server to try + * then don't stop the DNS request + */ + if (dns_backupserver_available(entry)) { + /* avoid retrying the same server */ + entry->retries = DNS_MAX_RETRIES-1; + entry->tmr = 1; + + /* contact next available server for this entry */ + dns_check_entry(i); + + goto ignore_packet; + } + } else { + while ((nanswers > 0) && (res_idx < p->tot_len)) { + /* skip answer resource record's host name */ + res_idx = dns_skip_name(p, res_idx); + if (res_idx == 0xFFFF) { + goto ignore_packet; /* ignore this packet */ + } + + /* Check for IP address type and Internet class. Others are discarded. */ + if (pbuf_copy_partial(p, &ans, SIZEOF_DNS_ANSWER, res_idx) != SIZEOF_DNS_ANSWER) { + goto ignore_packet; /* ignore this packet */ + } + if (res_idx + SIZEOF_DNS_ANSWER > 0xFFFF) { + goto ignore_packet; + } + res_idx = (u16_t)(res_idx + SIZEOF_DNS_ANSWER); + + if (ans.cls == PP_HTONS(DNS_RRCLASS_IN)) { +#if LWIP_IPV4 + if ((ans.type == PP_HTONS(DNS_RRTYPE_A)) && (ans.len == PP_HTONS(sizeof(ip4_addr_t)))) { +#if LWIP_IPV4 && LWIP_IPV6 + if (!LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + { + ip4_addr_t ip4addr; + /* read the IP address after answer resource record's header */ + if (pbuf_copy_partial(p, &ip4addr, sizeof(ip4_addr_t), res_idx) != sizeof(ip4_addr_t)) { + goto ignore_packet; /* ignore this packet */ + } + ip_addr_copy_from_ip4(dns_table[i].ipaddr, ip4addr); + pbuf_free(p); + /* handle correct response */ + dns_correct_response(i, lwip_ntohl(ans.ttl)); + return; + } + } +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 + if ((ans.type == PP_HTONS(DNS_RRTYPE_AAAA)) && (ans.len == PP_HTONS(sizeof(ip6_addr_p_t)))) { +#if LWIP_IPV4 && LWIP_IPV6 + if (LWIP_DNS_ADDRTYPE_IS_IPV6(entry->reqaddrtype)) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + { + ip6_addr_p_t ip6addr; + /* read the IP address after answer resource record's header */ + if (pbuf_copy_partial(p, &ip6addr, sizeof(ip6_addr_p_t), res_idx) != sizeof(ip6_addr_p_t)) { + goto ignore_packet; /* ignore this packet */ + } + /* @todo: scope ip6addr? Might be required for link-local addresses at least? */ + ip_addr_copy_from_ip6_packed(dns_table[i].ipaddr, ip6addr); + pbuf_free(p); + /* handle correct response */ + dns_correct_response(i, lwip_ntohl(ans.ttl)); + return; + } + } +#endif /* LWIP_IPV6 */ + } + /* skip this answer */ + if ((int)(res_idx + lwip_htons(ans.len)) > 0xFFFF) { + goto ignore_packet; /* ignore this packet */ + } + res_idx = (u16_t)(res_idx + lwip_htons(ans.len)); + --nanswers; + } +#if LWIP_IPV4 && LWIP_IPV6 + if ((entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) || + (entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV6_IPV4)) { + if (entry->reqaddrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) { + /* IPv4 failed, try IPv6 */ + dns_table[i].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV6; + } else { + /* IPv6 failed, try IPv4 */ + dns_table[i].reqaddrtype = LWIP_DNS_ADDRTYPE_IPV4; + } + pbuf_free(p); + dns_table[i].state = DNS_STATE_NEW; + dns_check_entry(i); + return; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_recv: \"%s\": error in response\n", entry->name)); + } + /* call callback to indicate error, clean up memory and return */ + pbuf_free(p); + dns_call_found(i, NULL); + dns_table[i].state = DNS_STATE_UNUSED; + return; + } + } + } + +ignore_packet: + /* deallocate memory and return */ + pbuf_free(p); + return; +} + +/** + * Queues a new hostname to resolve and sends out a DNS query for that hostname + * + * @param name the hostname that is to be queried + * @param hostnamelen length of the hostname + * @param found a callback function to be called on success, failure or timeout + * @param callback_arg argument to pass to the callback function + * @return err_t return code. + */ +static err_t +dns_enqueue(const char *name, size_t hostnamelen, dns_found_callback found, + void *callback_arg LWIP_DNS_ADDRTYPE_ARG(u8_t dns_addrtype) LWIP_DNS_ISMDNS_ARG(u8_t is_mdns)) +{ + u8_t i; + u8_t lseq, lseqi; + struct dns_table_entry *entry = NULL; + size_t namelen; + struct dns_req_entry *req; + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) + u8_t r; + /* check for duplicate entries */ + for (i = 0; i < DNS_TABLE_SIZE; i++) { + if ((dns_table[i].state == DNS_STATE_ASKING) && + (lwip_strnicmp(name, dns_table[i].name, sizeof(dns_table[i].name)) == 0)) { +#if LWIP_IPV4 && LWIP_IPV6 + if (dns_table[i].reqaddrtype != dns_addrtype) { + /* requested address types don't match + this can lead to 2 concurrent requests, but mixing the address types + for the same host should not be that common */ + continue; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + /* this is a duplicate entry, find a free request entry */ + for (r = 0; r < DNS_MAX_REQUESTS; r++) { + if (dns_requests[r].found == 0) { + dns_requests[r].found = found; + dns_requests[r].arg = callback_arg; + dns_requests[r].dns_table_idx = i; + LWIP_DNS_SET_ADDRTYPE(dns_requests[r].reqaddrtype, dns_addrtype); + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": duplicate request\n", name)); + return ERR_INPROGRESS; + } + } + } + } + /* no duplicate entries found */ +#endif + + /* search an unused entry, or the oldest one */ + lseq = 0; + lseqi = DNS_TABLE_SIZE; + for (i = 0; i < DNS_TABLE_SIZE; ++i) { + entry = &dns_table[i]; + /* is it an unused entry ? */ + if (entry->state == DNS_STATE_UNUSED) { + break; + } + /* check if this is the oldest completed entry */ + if (entry->state == DNS_STATE_DONE) { + u8_t age = (u8_t)(dns_seqno - entry->seqno); + if (age > lseq) { + lseq = age; + lseqi = i; + } + } + } + + /* if we don't have found an unused entry, use the oldest completed one */ + if (i == DNS_TABLE_SIZE) { + if ((lseqi >= DNS_TABLE_SIZE) || (dns_table[lseqi].state != DNS_STATE_DONE)) { + /* no entry can be used now, table is full */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS entries table is full\n", name)); + return ERR_MEM; + } else { + /* use the oldest completed one */ + i = lseqi; + entry = &dns_table[i]; + } + } + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING) != 0) + /* find a free request entry */ + req = NULL; + for (r = 0; r < DNS_MAX_REQUESTS; r++) { + if (dns_requests[r].found == NULL) { + req = &dns_requests[r]; + break; + } + } + if (req == NULL) { + /* no request entry can be used now, table is full */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": DNS request entries table is full\n", name)); + return ERR_MEM; + } + req->dns_table_idx = i; +#else + /* in this configuration, the entry index is the same as the request index */ + req = &dns_requests[i]; +#endif + + /* use this entry */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS entry %"U16_F"\n", name, (u16_t)(i))); + + /* fill the entry */ + entry->state = DNS_STATE_NEW; + entry->seqno = dns_seqno; + LWIP_DNS_SET_ADDRTYPE(entry->reqaddrtype, dns_addrtype); + LWIP_DNS_SET_ADDRTYPE(req->reqaddrtype, dns_addrtype); + req->found = found; + req->arg = callback_arg; + namelen = LWIP_MIN(hostnamelen, DNS_MAX_NAME_LENGTH - 1); + MEMCPY(entry->name, name, namelen); + entry->name[namelen] = 0; + +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) != 0) + entry->pcb_idx = dns_alloc_pcb(); + if (entry->pcb_idx >= DNS_MAX_SOURCE_PORTS) { + /* failed to get a UDP pcb */ + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": failed to allocate a pcb\n", name)); + entry->state = DNS_STATE_UNUSED; + req->found = NULL; + return ERR_MEM; + } + LWIP_DEBUGF(DNS_DEBUG, ("dns_enqueue: \"%s\": use DNS pcb %"U16_F"\n", name, (u16_t)(entry->pcb_idx))); +#endif + +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + entry->is_mdns = is_mdns; +#endif + + dns_seqno++; + + /* force to send query without waiting timer */ + dns_check_entry(i); + + /* dns query is enqueued */ + return ERR_INPROGRESS; +} + +/** + * @ingroup dns + * Resolve a hostname (string) into an IP address. + * NON-BLOCKING callback version for use with raw API!!! + * + * Returns immediately with one of err_t return codes: + * - ERR_OK if hostname is a valid IP address string or the host + * name is already in the local names table. + * - ERR_INPROGRESS enqueue a request to be sent to the DNS server + * for resolution if no errors are present. + * - ERR_ARG: dns client not initialized or invalid hostname + * + * @param hostname the hostname that is to be queried + * @param addr pointer to a ip_addr_t where to store the address if it is already + * cached in the dns_table (only valid if ERR_OK is returned!) + * @param found a callback function to be called on success, failure or timeout (only if + * ERR_INPROGRESS is returned!) + * @param callback_arg argument to pass to the callback function + * @return a err_t return code. + */ +err_t +dns_gethostbyname(const char *hostname, ip_addr_t *addr, dns_found_callback found, + void *callback_arg) +{ + return dns_gethostbyname_addrtype(hostname, addr, found, callback_arg, LWIP_DNS_ADDRTYPE_DEFAULT); +} + +/** + * @ingroup dns + * Like dns_gethostbyname, but returned address type can be controlled: + * @param hostname the hostname that is to be queried + * @param addr pointer to a ip_addr_t where to store the address if it is already + * cached in the dns_table (only valid if ERR_OK is returned!) + * @param found a callback function to be called on success, failure or timeout (only if + * ERR_INPROGRESS is returned!) + * @param callback_arg argument to pass to the callback function + * @param dns_addrtype - LWIP_DNS_ADDRTYPE_IPV4_IPV6: try to resolve IPv4 first, try IPv6 if IPv4 fails only + * - LWIP_DNS_ADDRTYPE_IPV6_IPV4: try to resolve IPv6 first, try IPv4 if IPv6 fails only + * - LWIP_DNS_ADDRTYPE_IPV4: try to resolve IPv4 only + * - LWIP_DNS_ADDRTYPE_IPV6: try to resolve IPv6 only + */ +err_t +dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr, dns_found_callback found, + void *callback_arg, u8_t dns_addrtype) +{ + size_t hostnamelen; +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + u8_t is_mdns; +#endif + /* not initialized or no valid server yet, or invalid addr pointer + * or invalid hostname or invalid hostname length */ + if ((addr == NULL) || + (!hostname) || (!hostname[0])) { + return ERR_ARG; + } +#if ((LWIP_DNS_SECURE & LWIP_DNS_SECURE_RAND_SRC_PORT) == 0) + if (dns_pcbs[0] == NULL) { + return ERR_ARG; + } +#endif + hostnamelen = strlen(hostname); + if (hostnamelen >= DNS_MAX_NAME_LENGTH) { + LWIP_DEBUGF(DNS_DEBUG, ("dns_gethostbyname: name too long to resolve")); + return ERR_ARG; + } + + +#if LWIP_HAVE_LOOPIF + if (strcmp(hostname, "localhost") == 0) { + ip_addr_set_loopback(LWIP_DNS_ADDRTYPE_IS_IPV6(dns_addrtype), addr); + return ERR_OK; + } +#endif /* LWIP_HAVE_LOOPIF */ + + /* host name already in octet notation? set ip addr and return ERR_OK */ + if (ipaddr_aton(hostname, addr)) { +#if LWIP_IPV4 && LWIP_IPV6 + if ((IP_IS_V6(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV4)) || + (IP_IS_V4(addr) && (dns_addrtype != LWIP_DNS_ADDRTYPE_IPV6))) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + { + return ERR_OK; + } + } + /* already have this address cached? */ + if (dns_lookup(hostname, addr LWIP_DNS_ADDRTYPE_ARG(dns_addrtype)) == ERR_OK) { + return ERR_OK; + } +#if LWIP_IPV4 && LWIP_IPV6 + if ((dns_addrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) || (dns_addrtype == LWIP_DNS_ADDRTYPE_IPV6_IPV4)) { + /* fallback to 2nd IP type and try again to lookup */ + u8_t fallback; + if (dns_addrtype == LWIP_DNS_ADDRTYPE_IPV4_IPV6) { + fallback = LWIP_DNS_ADDRTYPE_IPV6; + } else { + fallback = LWIP_DNS_ADDRTYPE_IPV4; + } + if (dns_lookup(hostname, addr LWIP_DNS_ADDRTYPE_ARG(fallback)) == ERR_OK) { + return ERR_OK; + } + } +#else /* LWIP_IPV4 && LWIP_IPV6 */ + LWIP_UNUSED_ARG(dns_addrtype); +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +#if LWIP_DNS_SUPPORT_MDNS_QUERIES + if (strstr(hostname, ".local") == &hostname[hostnamelen] - 6) { + is_mdns = 1; + } else { + is_mdns = 0; + } + + if (!is_mdns) +#endif /* LWIP_DNS_SUPPORT_MDNS_QUERIES */ + { + /* prevent calling found callback if no server is set, return error instead */ + if (ip_addr_isany_val(dns_servers[0])) { + return ERR_VAL; + } + } + + /* queue query with specified callback */ + return dns_enqueue(hostname, hostnamelen, found, callback_arg LWIP_DNS_ADDRTYPE_ARG(dns_addrtype) + LWIP_DNS_ISMDNS_ARG(is_mdns)); +} + +#endif /* LWIP_DNS */ diff --git a/Middlewares/Third_Party/LwIP/src/core/inet_chksum.c b/Middlewares/Third_Party/LwIP/src/core/inet_chksum.c new file mode 100644 index 0000000..818c68f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/inet_chksum.c @@ -0,0 +1,608 @@ +/** + * @file + * Internet checksum functions.\n + * + * These are some reference implementations of the checksum algorithm, with the + * aim of being simple, correct and fully portable. Checksumming is the + * first thing you would want to optimize for your platform. If you create + * your own version, link it in and in your cc.h put: + * + * \#define LWIP_CHKSUM your_checksum_routine + * + * Or you can select from the implementations below by defining + * LWIP_CHKSUM_ALGORITHM to 1, 2 or 3. + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/inet_chksum.h" +#include "lwip/def.h" +#include "lwip/ip_addr.h" + +#include + +#ifndef LWIP_CHKSUM +# define LWIP_CHKSUM lwip_standard_chksum +# ifndef LWIP_CHKSUM_ALGORITHM +# define LWIP_CHKSUM_ALGORITHM 2 +# endif +u16_t lwip_standard_chksum(const void *dataptr, int len); +#endif +/* If none set: */ +#ifndef LWIP_CHKSUM_ALGORITHM +# define LWIP_CHKSUM_ALGORITHM 0 +#endif + +#if (LWIP_CHKSUM_ALGORITHM == 1) /* Version #1 */ +/** + * lwip checksum + * + * @param dataptr points to start of data to be summed at any boundary + * @param len length of data to be summed + * @return host order (!) lwip checksum (non-inverted Internet sum) + * + * @note accumulator size limits summable length to 64k + * @note host endianess is irrelevant (p3 RFC1071) + */ +u16_t +lwip_standard_chksum(const void *dataptr, int len) +{ + u32_t acc; + u16_t src; + const u8_t *octetptr; + + acc = 0; + /* dataptr may be at odd or even addresses */ + octetptr = (const u8_t *)dataptr; + while (len > 1) { + /* declare first octet as most significant + thus assume network order, ignoring host order */ + src = (*octetptr) << 8; + octetptr++; + /* declare second octet as least significant */ + src |= (*octetptr); + octetptr++; + acc += src; + len -= 2; + } + if (len > 0) { + /* accumulate remaining octet */ + src = (*octetptr) << 8; + acc += src; + } + /* add deferred carry bits */ + acc = (acc >> 16) + (acc & 0x0000ffffUL); + if ((acc & 0xffff0000UL) != 0) { + acc = (acc >> 16) + (acc & 0x0000ffffUL); + } + /* This maybe a little confusing: reorder sum using lwip_htons() + instead of lwip_ntohs() since it has a little less call overhead. + The caller must invert bits for Internet sum ! */ + return lwip_htons((u16_t)acc); +} +#endif + +#if (LWIP_CHKSUM_ALGORITHM == 2) /* Alternative version #2 */ +/* + * Curt McDowell + * Broadcom Corp. + * csm@broadcom.com + * + * IP checksum two bytes at a time with support for + * unaligned buffer. + * Works for len up to and including 0x20000. + * by Curt McDowell, Broadcom Corp. 12/08/2005 + * + * @param dataptr points to start of data to be summed at any boundary + * @param len length of data to be summed + * @return host order (!) lwip checksum (non-inverted Internet sum) + */ +u16_t +lwip_standard_chksum(const void *dataptr, int len) +{ + const u8_t *pb = (const u8_t *)dataptr; + const u16_t *ps; + u16_t t = 0; + u32_t sum = 0; + int odd = ((mem_ptr_t)pb & 1); + + /* Get aligned to u16_t */ + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + /* Add the bulk of the data */ + ps = (const u16_t *)(const void *)pb; + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* Consume left-over byte, if any */ + if (len > 0) { + ((u8_t *)&t)[0] = *(const u8_t *)ps; + } + + /* Add end bytes */ + sum += t; + + /* Fold 32-bit sum to 16 bits + calling this twice is probably faster than if statements... */ + sum = FOLD_U32T(sum); + sum = FOLD_U32T(sum); + + /* Swap if alignment was odd */ + if (odd) { + sum = SWAP_BYTES_IN_WORD(sum); + } + + return (u16_t)sum; +} +#endif + +#if (LWIP_CHKSUM_ALGORITHM == 3) /* Alternative version #3 */ +/** + * An optimized checksum routine. Basically, it uses loop-unrolling on + * the checksum loop, treating the head and tail bytes specially, whereas + * the inner loop acts on 8 bytes at a time. + * + * @arg start of buffer to be checksummed. May be an odd byte address. + * @len number of bytes in the buffer to be checksummed. + * @return host order (!) lwip checksum (non-inverted Internet sum) + * + * by Curt McDowell, Broadcom Corp. December 8th, 2005 + */ +u16_t +lwip_standard_chksum(const void *dataptr, int len) +{ + const u8_t *pb = (const u8_t *)dataptr; + const u16_t *ps; + u16_t t = 0; + const u32_t *pl; + u32_t sum = 0, tmp; + /* starts at odd byte address? */ + int odd = ((mem_ptr_t)pb & 1); + + if (odd && len > 0) { + ((u8_t *)&t)[1] = *pb++; + len--; + } + + ps = (const u16_t *)(const void *)pb; + + if (((mem_ptr_t)ps & 3) && len > 1) { + sum += *ps++; + len -= 2; + } + + pl = (const u32_t *)(const void *)ps; + + while (len > 7) { + tmp = sum + *pl++; /* ping */ + if (tmp < sum) { + tmp++; /* add back carry */ + } + + sum = tmp + *pl++; /* pong */ + if (sum < tmp) { + sum++; /* add back carry */ + } + + len -= 8; + } + + /* make room in upper bits */ + sum = FOLD_U32T(sum); + + ps = (const u16_t *)pl; + + /* 16-bit aligned word remaining? */ + while (len > 1) { + sum += *ps++; + len -= 2; + } + + /* dangling tail byte remaining? */ + if (len > 0) { /* include odd byte */ + ((u8_t *)&t)[0] = *(const u8_t *)ps; + } + + sum += t; /* add end bytes */ + + /* Fold 32-bit sum to 16 bits + calling this twice is probably faster than if statements... */ + sum = FOLD_U32T(sum); + sum = FOLD_U32T(sum); + + if (odd) { + sum = SWAP_BYTES_IN_WORD(sum); + } + + return (u16_t)sum; +} +#endif + +/** Parts of the pseudo checksum which are common to IPv4 and IPv6 */ +static u16_t +inet_cksum_pseudo_base(struct pbuf *p, u8_t proto, u16_t proto_len, u32_t acc) +{ + struct pbuf *q; + int swapped = 0; + + /* iterate through all pbuf in chain */ + for (q = p; q != NULL; q = q->next) { + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", + (void *)q, (void *)q->next)); + acc += LWIP_CHKSUM(q->payload, q->len); + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ + /* just executing this next line is probably faster that the if statement needed + to check whether we really need to execute it, and does no harm */ + acc = FOLD_U32T(acc); + if (q->len % 2 != 0) { + swapped = !swapped; + acc = SWAP_BYTES_IN_WORD(acc); + } + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ + } + + if (swapped) { + acc = SWAP_BYTES_IN_WORD(acc); + } + + acc += (u32_t)lwip_htons((u16_t)proto); + acc += (u32_t)lwip_htons(proto_len); + + /* Fold 32-bit sum to 16 bits + calling this twice is probably faster than if statements... */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); + return (u16_t)~(acc & 0xffffUL); +} + +#if LWIP_IPV4 +/* inet_chksum_pseudo: + * + * Calculates the IPv4 pseudo Internet checksum used by TCP and UDP for a pbuf chain. + * IP addresses are expected to be in network byte order. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param src source ip address (used for checksum of pseudo header) + * @param dst destination ip address (used for checksum of pseudo header) + * @param proto ip protocol (used for checksum of pseudo header) + * @param proto_len length of the ip data part (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, + const ip4_addr_t *src, const ip4_addr_t *dest) +{ + u32_t acc; + u32_t addr; + + addr = ip4_addr_get_u32(src); + acc = (addr & 0xffffUL); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + addr = ip4_addr_get_u32(dest); + acc = (u32_t)(acc + (addr & 0xffffUL)); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + /* fold down to 16 bits */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + + return inet_cksum_pseudo_base(p, proto, proto_len, acc); +} +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +/** + * Calculates the checksum with IPv6 pseudo header used by TCP and UDP for a pbuf chain. + * IPv6 addresses are expected to be in network byte order. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param proto ipv6 protocol/next header (used for checksum of pseudo header) + * @param proto_len length of the ipv6 payload (used for checksum of pseudo header) + * @param src source ipv6 address (used for checksum of pseudo header) + * @param dest destination ipv6 address (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, + const ip6_addr_t *src, const ip6_addr_t *dest) +{ + u32_t acc = 0; + u32_t addr; + u8_t addr_part; + + for (addr_part = 0; addr_part < 4; addr_part++) { + addr = src->addr[addr_part]; + acc = (u32_t)(acc + (addr & 0xffffUL)); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + addr = dest->addr[addr_part]; + acc = (u32_t)(acc + (addr & 0xffffUL)); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + } + /* fold down to 16 bits */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + + return inet_cksum_pseudo_base(p, proto, proto_len, acc); +} +#endif /* LWIP_IPV6 */ + +/* ip_chksum_pseudo: + * + * Calculates the IPv4 or IPv6 pseudo Internet checksum used by TCP and UDP for a pbuf chain. + * IP addresses are expected to be in network byte order. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param src source ip address (used for checksum of pseudo header) + * @param dst destination ip address (used for checksum of pseudo header) + * @param proto ip protocol (used for checksum of pseudo header) + * @param proto_len length of the ip data part (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, + const ip_addr_t *src, const ip_addr_t *dest) +{ +#if LWIP_IPV6 + if (IP_IS_V6(dest)) { + return ip6_chksum_pseudo(p, proto, proto_len, ip_2_ip6(src), ip_2_ip6(dest)); + } +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 && LWIP_IPV6 + else +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#if LWIP_IPV4 + { + return inet_chksum_pseudo(p, proto, proto_len, ip_2_ip4(src), ip_2_ip4(dest)); + } +#endif /* LWIP_IPV4 */ +} + +/** Parts of the pseudo checksum which are common to IPv4 and IPv6 */ +static u16_t +inet_cksum_pseudo_partial_base(struct pbuf *p, u8_t proto, u16_t proto_len, + u16_t chksum_len, u32_t acc) +{ + struct pbuf *q; + int swapped = 0; + u16_t chklen; + + /* iterate through all pbuf in chain */ + for (q = p; (q != NULL) && (chksum_len > 0); q = q->next) { + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): checksumming pbuf %p (has next %p) \n", + (void *)q, (void *)q->next)); + chklen = q->len; + if (chklen > chksum_len) { + chklen = chksum_len; + } + acc += LWIP_CHKSUM(q->payload, chklen); + chksum_len = (u16_t)(chksum_len - chklen); + LWIP_ASSERT("delete me", chksum_len < 0x7fff); + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): unwrapped lwip_chksum()=%"X32_F" \n", acc));*/ + /* fold the upper bit down */ + acc = FOLD_U32T(acc); + if (q->len % 2 != 0) { + swapped = !swapped; + acc = SWAP_BYTES_IN_WORD(acc); + } + /*LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): wrapped lwip_chksum()=%"X32_F" \n", acc));*/ + } + + if (swapped) { + acc = SWAP_BYTES_IN_WORD(acc); + } + + acc += (u32_t)lwip_htons((u16_t)proto); + acc += (u32_t)lwip_htons(proto_len); + + /* Fold 32-bit sum to 16 bits + calling this twice is probably faster than if statements... */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + LWIP_DEBUGF(INET_DEBUG, ("inet_chksum_pseudo(): pbuf chain lwip_chksum()=%"X32_F"\n", acc)); + return (u16_t)~(acc & 0xffffUL); +} + +#if LWIP_IPV4 +/* inet_chksum_pseudo_partial: + * + * Calculates the IPv4 pseudo Internet checksum used by TCP and UDP for a pbuf chain. + * IP addresses are expected to be in network byte order. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param src source ip address (used for checksum of pseudo header) + * @param dst destination ip address (used for checksum of pseudo header) + * @param proto ip protocol (used for checksum of pseudo header) + * @param proto_len length of the ip data part (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, + u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest) +{ + u32_t acc; + u32_t addr; + + addr = ip4_addr_get_u32(src); + acc = (addr & 0xffffUL); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + addr = ip4_addr_get_u32(dest); + acc = (u32_t)(acc + (addr & 0xffffUL)); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + /* fold down to 16 bits */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + + return inet_cksum_pseudo_partial_base(p, proto, proto_len, chksum_len, acc); +} +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +/** + * Calculates the checksum with IPv6 pseudo header used by TCP and UDP for a pbuf chain. + * IPv6 addresses are expected to be in network byte order. Will only compute for a + * portion of the payload. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param proto ipv6 protocol/next header (used for checksum of pseudo header) + * @param proto_len length of the ipv6 payload (used for checksum of pseudo header) + * @param chksum_len number of payload bytes used to compute chksum + * @param src source ipv6 address (used for checksum of pseudo header) + * @param dest destination ipv6 address (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, + u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest) +{ + u32_t acc = 0; + u32_t addr; + u8_t addr_part; + + for (addr_part = 0; addr_part < 4; addr_part++) { + addr = src->addr[addr_part]; + acc = (u32_t)(acc + (addr & 0xffffUL)); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + addr = dest->addr[addr_part]; + acc = (u32_t)(acc + (addr & 0xffffUL)); + acc = (u32_t)(acc + ((addr >> 16) & 0xffffUL)); + } + /* fold down to 16 bits */ + acc = FOLD_U32T(acc); + acc = FOLD_U32T(acc); + + return inet_cksum_pseudo_partial_base(p, proto, proto_len, chksum_len, acc); +} +#endif /* LWIP_IPV6 */ + +/* ip_chksum_pseudo_partial: + * + * Calculates the IPv4 or IPv6 pseudo Internet checksum used by TCP and UDP for a pbuf chain. + * + * @param p chain of pbufs over that a checksum should be calculated (ip data part) + * @param src source ip address (used for checksum of pseudo header) + * @param dst destination ip address (used for checksum of pseudo header) + * @param proto ip protocol (used for checksum of pseudo header) + * @param proto_len length of the ip data part (used for checksum of pseudo header) + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, + u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest) +{ +#if LWIP_IPV6 + if (IP_IS_V6(dest)) { + return ip6_chksum_pseudo_partial(p, proto, proto_len, chksum_len, ip_2_ip6(src), ip_2_ip6(dest)); + } +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 && LWIP_IPV6 + else +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#if LWIP_IPV4 + { + return inet_chksum_pseudo_partial(p, proto, proto_len, chksum_len, ip_2_ip4(src), ip_2_ip4(dest)); + } +#endif /* LWIP_IPV4 */ +} + +/* inet_chksum: + * + * Calculates the Internet checksum over a portion of memory. Used primarily for IP + * and ICMP. + * + * @param dataptr start of the buffer to calculate the checksum (no alignment needed) + * @param len length of the buffer to calculate the checksum + * @return checksum (as u16_t) to be saved directly in the protocol header + */ + +u16_t +inet_chksum(const void *dataptr, u16_t len) +{ + return (u16_t)~(unsigned int)LWIP_CHKSUM(dataptr, len); +} + +/** + * Calculate a checksum over a chain of pbufs (without pseudo-header, much like + * inet_chksum only pbufs are used). + * + * @param p pbuf chain over that the checksum should be calculated + * @return checksum (as u16_t) to be saved directly in the protocol header + */ +u16_t +inet_chksum_pbuf(struct pbuf *p) +{ + u32_t acc; + struct pbuf *q; + int swapped = 0; + + acc = 0; + for (q = p; q != NULL; q = q->next) { + acc += LWIP_CHKSUM(q->payload, q->len); + acc = FOLD_U32T(acc); + if (q->len % 2 != 0) { + swapped = !swapped; + acc = SWAP_BYTES_IN_WORD(acc); + } + } + + if (swapped) { + acc = SWAP_BYTES_IN_WORD(acc); + } + return (u16_t)~(acc & 0xffffUL); +} + +/* These are some implementations for LWIP_CHKSUM_COPY, which copies data + * like MEMCPY but generates a checksum at the same time. Since this is a + * performance-sensitive function, you might want to create your own version + * in assembly targeted at your hardware by defining it in lwipopts.h: + * #define LWIP_CHKSUM_COPY(dst, src, len) your_chksum_copy(dst, src, len) + */ + +#if (LWIP_CHKSUM_COPY_ALGORITHM == 1) /* Version #1 */ +/** Safe but slow: first call MEMCPY, then call LWIP_CHKSUM. + * For architectures with big caches, data might still be in cache when + * generating the checksum after copying. + */ +u16_t +lwip_chksum_copy(void *dst, const void *src, u16_t len) +{ + MEMCPY(dst, src, len); + return LWIP_CHKSUM(dst, len); +} +#endif /* (LWIP_CHKSUM_COPY_ALGORITHM == 1) */ diff --git a/Middlewares/Third_Party/LwIP/src/core/init.c b/Middlewares/Third_Party/LwIP/src/core/init.c new file mode 100644 index 0000000..b3737a3 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/init.c @@ -0,0 +1,380 @@ +/** + * @file + * Modules initialization + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + */ + +#include "lwip/opt.h" + +#include "lwip/init.h" +#include "lwip/stats.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/sockets.h" +#include "lwip/ip.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/priv/tcp_priv.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" +#include "lwip/timeouts.h" +#include "lwip/etharp.h" +#include "lwip/ip6.h" +#include "lwip/nd6.h" +#include "lwip/mld6.h" +#include "lwip/api.h" + +#include "netif/ppp/ppp_opts.h" +#include "netif/ppp/ppp_impl.h" + +#ifndef LWIP_SKIP_PACKING_CHECK + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct packed_struct_test { + PACK_STRUCT_FLD_8(u8_t dummy1); + PACK_STRUCT_FIELD(u32_t dummy2); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define PACKED_STRUCT_TEST_EXPECTED_SIZE 5 + +#endif + +/* Compile-time sanity checks for configuration errors. + * These can be done independently of LWIP_DEBUG, without penalty. + */ +#ifndef BYTE_ORDER +#error "BYTE_ORDER is not defined, you have to define it in your cc.h" +#endif +#if (!IP_SOF_BROADCAST && IP_SOF_BROADCAST_RECV) +#error "If you want to use broadcast filter per pcb on recv operations, you have to define IP_SOF_BROADCAST=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_UDPLITE) +#error "If you want to use UDP Lite, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_DHCP) +#error "If you want to use DHCP, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && !LWIP_RAW && LWIP_MULTICAST_TX_OPTIONS) +#error "If you want to use LWIP_MULTICAST_TX_OPTIONS, you have to define LWIP_UDP=1 and/or LWIP_RAW=1 in your lwipopts.h" +#endif +#if (!LWIP_UDP && LWIP_DNS) +#error "If you want to use DNS, you have to define LWIP_UDP=1 in your lwipopts.h" +#endif +#if !MEMP_MEM_MALLOC /* MEMP_NUM_* checks are disabled when not using the pool allocator */ +#if (LWIP_ARP && ARP_QUEUEING && (MEMP_NUM_ARP_QUEUE<=0)) +#error "If you want to use ARP Queueing, you have to define MEMP_NUM_ARP_QUEUE>=1 in your lwipopts.h" +#endif +#if (LWIP_RAW && (MEMP_NUM_RAW_PCB<=0)) +#error "If you want to use RAW, you have to define MEMP_NUM_RAW_PCB>=1 in your lwipopts.h" +#endif +#if (LWIP_UDP && (MEMP_NUM_UDP_PCB<=0)) +#error "If you want to use UDP, you have to define MEMP_NUM_UDP_PCB>=1 in your lwipopts.h" +#endif +#if (LWIP_TCP && (MEMP_NUM_TCP_PCB<=0)) +#error "If you want to use TCP, you have to define MEMP_NUM_TCP_PCB>=1 in your lwipopts.h" +#endif +#if (LWIP_IGMP && (MEMP_NUM_IGMP_GROUP<=1)) +#error "If you want to use IGMP, you have to define MEMP_NUM_IGMP_GROUP>1 in your lwipopts.h" +#endif +#if (LWIP_IGMP && !LWIP_MULTICAST_TX_OPTIONS) +#error "If you want to use IGMP, you have to define LWIP_MULTICAST_TX_OPTIONS==1 in your lwipopts.h" +#endif +#if (LWIP_IGMP && !LWIP_IPV4) +#error "IGMP needs LWIP_IPV4 enabled in your lwipopts.h" +#endif +#if ((LWIP_NETCONN || LWIP_SOCKET) && (MEMP_NUM_TCPIP_MSG_API<=0)) +#error "If you want to use Sequential API, you have to define MEMP_NUM_TCPIP_MSG_API>=1 in your lwipopts.h" +#endif +/* There must be sufficient timeouts, taking into account requirements of the subsystems. */ +#if LWIP_TIMERS && (MEMP_NUM_SYS_TIMEOUT < LWIP_NUM_SYS_TIMEOUT_INTERNAL) +#error "MEMP_NUM_SYS_TIMEOUT is too low to accomodate all required timeouts" +#endif +#if (IP_REASSEMBLY && (MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS)) +#error "MEMP_NUM_REASSDATA > IP_REASS_MAX_PBUFS doesn't make sense since each struct ip_reassdata must hold 2 pbufs at least!" +#endif +#endif /* !MEMP_MEM_MALLOC */ +#if LWIP_WND_SCALE +#if (LWIP_TCP && (TCP_WND > 0xffffffff)) +#error "If you want to use TCP, TCP_WND must fit in an u32_t, so, you have to reduce it in your lwipopts.h" +#endif +#if (LWIP_TCP && (TCP_RCV_SCALE > 14)) +#error "The maximum valid window scale value is 14!" +#endif +#if (LWIP_TCP && (TCP_WND > (0xFFFFU << TCP_RCV_SCALE))) +#error "TCP_WND is bigger than the configured LWIP_WND_SCALE allows!" +#endif +#if (LWIP_TCP && ((TCP_WND >> TCP_RCV_SCALE) == 0)) +#error "TCP_WND is too small for the configured LWIP_WND_SCALE (results in zero window)!" +#endif +#else /* LWIP_WND_SCALE */ +#if (LWIP_TCP && (TCP_WND > 0xffff)) +#error "If you want to use TCP, TCP_WND must fit in an u16_t, so, you have to reduce it in your lwipopts.h (or enable window scaling)" +#endif +#endif /* LWIP_WND_SCALE */ +#if (LWIP_TCP && (TCP_SND_QUEUELEN > 0xffff)) +#error "If you want to use TCP, TCP_SND_QUEUELEN must fit in an u16_t, so, you have to reduce it in your lwipopts.h" +#endif +#if (LWIP_TCP && (TCP_SND_QUEUELEN < 2)) +#error "TCP_SND_QUEUELEN must be at least 2 for no-copy TCP writes to work" +#endif +#if (LWIP_TCP && ((TCP_MAXRTX > 12) || (TCP_SYNMAXRTX > 12))) +#error "If you want to use TCP, TCP_MAXRTX and TCP_SYNMAXRTX must less or equal to 12 (due to tcp_backoff table), so, you have to reduce them in your lwipopts.h" +#endif +#if (LWIP_TCP && TCP_LISTEN_BACKLOG && ((TCP_DEFAULT_LISTEN_BACKLOG < 0) || (TCP_DEFAULT_LISTEN_BACKLOG > 0xff))) +#error "If you want to use TCP backlog, TCP_DEFAULT_LISTEN_BACKLOG must fit into an u8_t" +#endif +#if (LWIP_TCP && LWIP_TCP_SACK_OUT && !TCP_QUEUE_OOSEQ) +#error "To use LWIP_TCP_SACK_OUT, TCP_QUEUE_OOSEQ needs to be enabled" +#endif +#if (LWIP_TCP && LWIP_TCP_SACK_OUT && (LWIP_TCP_MAX_SACK_NUM < 1)) +#error "LWIP_TCP_MAX_SACK_NUM must be greater than 0" +#endif +#if (LWIP_NETIF_API && (NO_SYS==1)) +#error "If you want to use NETIF API, you have to define NO_SYS=0 in your lwipopts.h" +#endif +#if ((LWIP_SOCKET || LWIP_NETCONN) && (NO_SYS==1)) +#error "If you want to use Sequential API, you have to define NO_SYS=0 in your lwipopts.h" +#endif +#if (LWIP_PPP_API && (NO_SYS==1)) +#error "If you want to use PPP API, you have to define NO_SYS=0 in your lwipopts.h" +#endif +#if (LWIP_PPP_API && (PPP_SUPPORT==0)) +#error "If you want to use PPP API, you have to enable PPP_SUPPORT in your lwipopts.h" +#endif +#if (((!LWIP_DHCP) || (!LWIP_AUTOIP)) && LWIP_DHCP_AUTOIP_COOP) +#error "If you want to use DHCP/AUTOIP cooperation mode, you have to define LWIP_DHCP=1 and LWIP_AUTOIP=1 in your lwipopts.h" +#endif +#if (((!LWIP_DHCP) || (!LWIP_ARP)) && DHCP_DOES_ARP_CHECK) +#error "If you want to use DHCP ARP checking, you have to define LWIP_DHCP=1 and LWIP_ARP=1 in your lwipopts.h" +#endif +#if (!LWIP_ARP && LWIP_AUTOIP) +#error "If you want to use AUTOIP, you have to define LWIP_ARP=1 in your lwipopts.h" +#endif +#if (LWIP_TCP && ((LWIP_EVENT_API && LWIP_CALLBACK_API) || (!LWIP_EVENT_API && !LWIP_CALLBACK_API))) +#error "One and exactly one of LWIP_EVENT_API and LWIP_CALLBACK_API has to be enabled in your lwipopts.h" +#endif +#if (LWIP_ALTCP && LWIP_EVENT_API) +#error "The application layered tcp API does not work with LWIP_EVENT_API" +#endif +#if (MEM_LIBC_MALLOC && MEM_USE_POOLS) +#error "MEM_LIBC_MALLOC and MEM_USE_POOLS may not both be simultaneously enabled in your lwipopts.h" +#endif +#if (MEM_USE_POOLS && !MEMP_USE_CUSTOM_POOLS) +#error "MEM_USE_POOLS requires custom pools (MEMP_USE_CUSTOM_POOLS) to be enabled in your lwipopts.h" +#endif +#if (PBUF_POOL_BUFSIZE <= MEM_ALIGNMENT) +#error "PBUF_POOL_BUFSIZE must be greater than MEM_ALIGNMENT or the offset may take the full first pbuf" +#endif +#if (DNS_LOCAL_HOSTLIST && !DNS_LOCAL_HOSTLIST_IS_DYNAMIC && !(defined(DNS_LOCAL_HOSTLIST_INIT))) +#error "you have to define define DNS_LOCAL_HOSTLIST_INIT {{'host1', 0x123}, {'host2', 0x234}} to initialize DNS_LOCAL_HOSTLIST" +#endif +#if PPP_SUPPORT && !PPPOS_SUPPORT && !PPPOE_SUPPORT && !PPPOL2TP_SUPPORT +#error "PPP_SUPPORT needs at least one of PPPOS_SUPPORT, PPPOE_SUPPORT or PPPOL2TP_SUPPORT turned on" +#endif +#if PPP_SUPPORT && !PPP_IPV4_SUPPORT && !PPP_IPV6_SUPPORT +#error "PPP_SUPPORT needs PPP_IPV4_SUPPORT and/or PPP_IPV6_SUPPORT turned on" +#endif +#if PPP_SUPPORT && PPP_IPV4_SUPPORT && !LWIP_IPV4 +#error "PPP_IPV4_SUPPORT needs LWIP_IPV4 turned on" +#endif +#if PPP_SUPPORT && PPP_IPV6_SUPPORT && !LWIP_IPV6 +#error "PPP_IPV6_SUPPORT needs LWIP_IPV6 turned on" +#endif +#if !LWIP_ETHERNET && (LWIP_ARP || PPPOE_SUPPORT) +#error "LWIP_ETHERNET needs to be turned on for LWIP_ARP or PPPOE_SUPPORT" +#endif +#if LWIP_TCPIP_CORE_LOCKING_INPUT && !LWIP_TCPIP_CORE_LOCKING +#error "When using LWIP_TCPIP_CORE_LOCKING_INPUT, LWIP_TCPIP_CORE_LOCKING must be enabled, too" +#endif +#if LWIP_TCP && LWIP_NETIF_TX_SINGLE_PBUF && !TCP_OVERSIZE +#error "LWIP_NETIF_TX_SINGLE_PBUF needs TCP_OVERSIZE enabled to create single-pbuf TCP packets" +#endif +#if LWIP_NETCONN && LWIP_TCP +#if NETCONN_COPY != TCP_WRITE_FLAG_COPY +#error "NETCONN_COPY != TCP_WRITE_FLAG_COPY" +#endif +#if NETCONN_MORE != TCP_WRITE_FLAG_MORE +#error "NETCONN_MORE != TCP_WRITE_FLAG_MORE" +#endif +#endif /* LWIP_NETCONN && LWIP_TCP */ +#if LWIP_SOCKET +#endif /* LWIP_SOCKET */ + + +/* Compile-time checks for deprecated options. + */ +#ifdef MEMP_NUM_TCPIP_MSG +#error "MEMP_NUM_TCPIP_MSG option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef TCP_REXMIT_DEBUG +#error "TCP_REXMIT_DEBUG option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef RAW_STATS +#error "RAW_STATS option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef ETHARP_QUEUE_FIRST +#error "ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h." +#endif +#ifdef ETHARP_ALWAYS_INSERT +#error "ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h." +#endif +#if !NO_SYS && LWIP_TCPIP_CORE_LOCKING && LWIP_COMPAT_MUTEX && !defined(LWIP_COMPAT_MUTEX_ALLOWED) +#error "LWIP_COMPAT_MUTEX cannot prevent priority inversion. It is recommended to implement priority-aware mutexes. (Define LWIP_COMPAT_MUTEX_ALLOWED to disable this error.)" +#endif + +#ifndef LWIP_DISABLE_TCP_SANITY_CHECKS +#define LWIP_DISABLE_TCP_SANITY_CHECKS 0 +#endif +#ifndef LWIP_DISABLE_MEMP_SANITY_CHECKS +#define LWIP_DISABLE_MEMP_SANITY_CHECKS 0 +#endif + +/* MEMP sanity checks */ +#if MEMP_MEM_MALLOC +#if !LWIP_DISABLE_MEMP_SANITY_CHECKS +#if LWIP_NETCONN || LWIP_SOCKET +#if !MEMP_NUM_NETCONN && LWIP_SOCKET +#error "lwip_sanity_check: WARNING: MEMP_NUM_NETCONN cannot be 0 when using sockets!" +#endif +#else /* MEMP_MEM_MALLOC */ +#if MEMP_NUM_NETCONN > (MEMP_NUM_TCP_PCB+MEMP_NUM_TCP_PCB_LISTEN+MEMP_NUM_UDP_PCB+MEMP_NUM_RAW_PCB) +#error "lwip_sanity_check: WARNING: MEMP_NUM_NETCONN should be less than the sum of MEMP_NUM_{TCP,RAW,UDP}_PCB+MEMP_NUM_TCP_PCB_LISTEN. If you know what you are doing, define LWIP_DISABLE_MEMP_SANITY_CHECKS to 1 to disable this error." +#endif +#endif /* LWIP_NETCONN || LWIP_SOCKET */ +#endif /* !LWIP_DISABLE_MEMP_SANITY_CHECKS */ +#if MEM_USE_POOLS +#error "MEMP_MEM_MALLOC and MEM_USE_POOLS cannot be enabled at the same time" +#endif +#ifdef LWIP_HOOK_MEMP_AVAILABLE +#error "LWIP_HOOK_MEMP_AVAILABLE doesn't make sense with MEMP_MEM_MALLOC" +#endif +#endif /* MEMP_MEM_MALLOC */ + +/* TCP sanity checks */ +#if !LWIP_DISABLE_TCP_SANITY_CHECKS +#if LWIP_TCP +#if !MEMP_MEM_MALLOC && (MEMP_NUM_TCP_SEG < TCP_SND_QUEUELEN) +#error "lwip_sanity_check: WARNING: MEMP_NUM_TCP_SEG should be at least as big as TCP_SND_QUEUELEN. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#if TCP_SND_BUF < (2 * TCP_MSS) +#error "lwip_sanity_check: WARNING: TCP_SND_BUF must be at least as much as (2 * TCP_MSS) for things to work smoothly. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#if TCP_SND_QUEUELEN < (2 * (TCP_SND_BUF / TCP_MSS)) +#error "lwip_sanity_check: WARNING: TCP_SND_QUEUELEN must be at least as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#if TCP_SNDLOWAT >= TCP_SND_BUF +#error "lwip_sanity_check: WARNING: TCP_SNDLOWAT must be less than TCP_SND_BUF. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#if TCP_SNDLOWAT >= (0xFFFF - (4 * TCP_MSS)) +#error "lwip_sanity_check: WARNING: TCP_SNDLOWAT must at least be 4*MSS below u16_t overflow!" +#endif +#if TCP_SNDQUEUELOWAT >= TCP_SND_QUEUELEN +#error "lwip_sanity_check: WARNING: TCP_SNDQUEUELOWAT must be less than TCP_SND_QUEUELEN. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#if !MEMP_MEM_MALLOC && PBUF_POOL_SIZE && (PBUF_POOL_BUFSIZE <= (PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)) +#error "lwip_sanity_check: WARNING: PBUF_POOL_BUFSIZE does not provide enough space for protocol headers. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#if !MEMP_MEM_MALLOC && PBUF_POOL_SIZE && (TCP_WND > (PBUF_POOL_SIZE * (PBUF_POOL_BUFSIZE - (PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN)))) +#error "lwip_sanity_check: WARNING: TCP_WND is larger than space provided by PBUF_POOL_SIZE * (PBUF_POOL_BUFSIZE - protocol headers). If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#if TCP_WND < TCP_MSS +#error "lwip_sanity_check: WARNING: TCP_WND is smaller than MSS. If you know what you are doing, define LWIP_DISABLE_TCP_SANITY_CHECKS to 1 to disable this error." +#endif +#endif /* LWIP_TCP */ +#endif /* !LWIP_DISABLE_TCP_SANITY_CHECKS */ + +/** + * @ingroup lwip_nosys + * Initialize all modules. + * Use this in NO_SYS mode. Use tcpip_init() otherwise. + */ +void +lwip_init(void) +{ +#ifndef LWIP_SKIP_CONST_CHECK + int a = 0; + LWIP_UNUSED_ARG(a); + LWIP_ASSERT("LWIP_CONST_CAST not implemented correctly. Check your lwIP port.", LWIP_CONST_CAST(void *, &a) == &a); +#endif +#ifndef LWIP_SKIP_PACKING_CHECK + LWIP_ASSERT("Struct packing not implemented correctly. Check your lwIP port.", sizeof(struct packed_struct_test) == PACKED_STRUCT_TEST_EXPECTED_SIZE); +#endif + + /* Modules initialization */ + stats_init(); +#if !NO_SYS + sys_init(); +#endif /* !NO_SYS */ + mem_init(); + memp_init(); + pbuf_init(); + netif_init(); +#if LWIP_IPV4 + ip_init(); +#if LWIP_ARP + etharp_init(); +#endif /* LWIP_ARP */ +#endif /* LWIP_IPV4 */ +#if LWIP_RAW + raw_init(); +#endif /* LWIP_RAW */ +#if LWIP_UDP + udp_init(); +#endif /* LWIP_UDP */ +#if LWIP_TCP + tcp_init(); +#endif /* LWIP_TCP */ +#if LWIP_IGMP + igmp_init(); +#endif /* LWIP_IGMP */ +#if LWIP_DNS + dns_init(); +#endif /* LWIP_DNS */ +#if PPP_SUPPORT + ppp_init(); +#endif + +#if LWIP_TIMERS + sys_timeouts_init(); +#endif /* LWIP_TIMERS */ +} diff --git a/Middlewares/Third_Party/LwIP/src/core/ip.c b/Middlewares/Third_Party/LwIP/src/core/ip.c new file mode 100644 index 0000000..18514cf --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ip.c @@ -0,0 +1,167 @@ +/** + * @file + * Common IPv4 and IPv6 code + * + * @defgroup ip IP + * @ingroup callbackstyle_api + * + * @defgroup ip4 IPv4 + * @ingroup ip + * + * @defgroup ip6 IPv6 + * @ingroup ip + * + * @defgroup ipaddr IP address handling + * @ingroup infrastructure + * + * @defgroup ip4addr IPv4 only + * @ingroup ipaddr + * + * @defgroup ip6addr IPv6 only + * @ingroup ipaddr + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 || LWIP_IPV6 + +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +/** Global data for both IPv4 and IPv6 */ +struct ip_globals ip_data; + +#if LWIP_IPV4 && LWIP_IPV6 + +const ip_addr_t ip_addr_any_type = IPADDR_ANY_TYPE_INIT; + +/** + * @ingroup ipaddr + * Convert numeric IP address (both versions) into ASCII representation. + * returns ptr to static buffer; not reentrant! + * + * @param addr ip address in network order to convert + * @return pointer to a global static (!) buffer that holds the ASCII + * representation of addr + */ +char *ipaddr_ntoa(const ip_addr_t *addr) +{ + if (addr == NULL) { + return NULL; + } + if (IP_IS_V6(addr)) { + return ip6addr_ntoa(ip_2_ip6(addr)); + } else { + return ip4addr_ntoa(ip_2_ip4(addr)); + } +} + +/** + * @ingroup ipaddr + * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used. + * + * @param addr ip address in network order to convert + * @param buf target buffer where the string is stored + * @param buflen length of buf + * @return either pointer to buf which now holds the ASCII + * representation of addr or NULL if buf was too small + */ +char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen) +{ + if (addr == NULL) { + return NULL; + } + if (IP_IS_V6(addr)) { + return ip6addr_ntoa_r(ip_2_ip6(addr), buf, buflen); + } else { + return ip4addr_ntoa_r(ip_2_ip4(addr), buf, buflen); + } +} + +/** + * @ingroup ipaddr + * Convert IP address string (both versions) to numeric. + * The version is auto-detected from the string. + * + * @param cp IP address string to convert + * @param addr conversion result is stored here + * @return 1 on success, 0 on error + */ +int +ipaddr_aton(const char *cp, ip_addr_t *addr) +{ + if (cp != NULL) { + const char *c; + for (c = cp; *c != 0; c++) { + if (*c == ':') { + /* contains a colon: IPv6 address */ + if (addr) { + IP_SET_TYPE_VAL(*addr, IPADDR_TYPE_V6); + } + return ip6addr_aton(cp, ip_2_ip6(addr)); + } else if (*c == '.') { + /* contains a dot: IPv4 address */ + break; + } + } + /* call ip4addr_aton as fallback or if IPv4 was found */ + if (addr) { + IP_SET_TYPE_VAL(*addr, IPADDR_TYPE_V4); + } + return ip4addr_aton(cp, ip_2_ip4(addr)); + } + return 0; +} + +/** + * @ingroup lwip_nosys + * If both IP versions are enabled, this function can dispatch packets to the correct one. + * Don't call directly, pass to netif_add() and call netif->input(). + */ +err_t +ip_input(struct pbuf *p, struct netif *inp) +{ + if (p != NULL) { + if (IP_HDR_GET_VERSION(p->payload) == 6) { + return ip6_input(p, inp); + } + return ip4_input(p, inp); + } + return ERR_VAL; +} + +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +#endif /* LWIP_IPV4 || LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c new file mode 100644 index 0000000..9f7139b --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/autoip.c @@ -0,0 +1,527 @@ +/** + * @file + * AutoIP Automatic LinkLocal IP Configuration + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + * @defgroup autoip AUTOIP + * @ingroup ip4 + * AUTOIP related functions + * USAGE: + * + * define @ref LWIP_AUTOIP 1 in your lwipopts.h + * Options: + * AUTOIP_TMR_INTERVAL msecs, + * I recommend a value of 100. The value must divide 1000 with a remainder almost 0. + * Possible values are 1000, 500, 333, 250, 200, 166, 142, 125, 111, 100 .... + * + * Without DHCP: + * - Call autoip_start() after netif_add(). + * + * With DHCP: + * - define @ref LWIP_DHCP_AUTOIP_COOP 1 in your lwipopts.h. + * - Configure your DHCP Client. + * + * @see netifapi_autoip + */ + +/* + * + * Copyright (c) 2007 Dominik Spies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies + */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 && LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/mem.h" +/* #include "lwip/udp.h" */ +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/autoip.h" +#include "lwip/etharp.h" +#include "lwip/prot/autoip.h" + +#include + +/** Pseudo random macro based on netif informations. + * You could use "rand()" from the C Library if you define LWIP_AUTOIP_RAND in lwipopts.h */ +#ifndef LWIP_AUTOIP_RAND +#define LWIP_AUTOIP_RAND(netif) ( (((u32_t)((netif->hwaddr[5]) & 0xff) << 24) | \ + ((u32_t)((netif->hwaddr[3]) & 0xff) << 16) | \ + ((u32_t)((netif->hwaddr[2]) & 0xff) << 8) | \ + ((u32_t)((netif->hwaddr[4]) & 0xff))) + \ + (netif_autoip_data(netif)? netif_autoip_data(netif)->tried_llipaddr : 0)) +#endif /* LWIP_AUTOIP_RAND */ + +/** + * Macro that generates the initial IP address to be tried by AUTOIP. + * If you want to override this, define it to something else in lwipopts.h. + */ +#ifndef LWIP_AUTOIP_CREATE_SEED_ADDR +#define LWIP_AUTOIP_CREATE_SEED_ADDR(netif) \ + lwip_htonl(AUTOIP_RANGE_START + ((u32_t)(((u8_t)(netif->hwaddr[4])) | \ + ((u32_t)((u8_t)(netif->hwaddr[5]))) << 8))) +#endif /* LWIP_AUTOIP_CREATE_SEED_ADDR */ + +/* static functions */ +static err_t autoip_arp_announce(struct netif *netif); +static void autoip_start_probing(struct netif *netif); + +/** + * @ingroup autoip + * Set a statically allocated struct autoip to work with. + * Using this prevents autoip_start to allocate it using mem_malloc. + * + * @param netif the netif for which to set the struct autoip + * @param autoip (uninitialised) autoip struct allocated by the application + */ +void +autoip_set_struct(struct netif *netif, struct autoip *autoip) +{ + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("autoip != NULL", autoip != NULL); + LWIP_ASSERT("netif already has a struct autoip set", + netif_autoip_data(netif) == NULL); + + /* clear data structure */ + memset(autoip, 0, sizeof(struct autoip)); + /* autoip->state = AUTOIP_STATE_OFF; */ + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP, autoip); +} + +/** Restart AutoIP client and check the next address (conflict detected) + * + * @param netif The netif under AutoIP control + */ +static void +autoip_restart(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + autoip->tried_llipaddr++; + autoip_start(netif); +} + +/** + * Handle a IP address conflict after an ARP conflict detection + */ +static void +autoip_handle_arp_conflict(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + + /* RFC3927, 2.5 "Conflict Detection and Defense" allows two options where + a) means retreat on the first conflict and + b) allows to keep an already configured address when having only one + conflict in 10 seconds + We use option b) since it helps to improve the chance that one of the two + conflicting hosts may be able to retain its address. */ + + if (autoip->lastconflict > 0) { + /* retreat, there was a conflicting ARP in the last DEFEND_INTERVAL seconds */ + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_handle_arp_conflict(): we are defending, but in DEFEND_INTERVAL, retreating\n")); + + /* Active TCP sessions are aborted when removing the ip addresss */ + autoip_restart(netif); + } else { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_handle_arp_conflict(): we are defend, send ARP Announce\n")); + autoip_arp_announce(netif); + autoip->lastconflict = DEFEND_INTERVAL * AUTOIP_TICKS_PER_SECOND; + } +} + +/** + * Create an IP-Address out of range 169.254.1.0 to 169.254.254.255 + * + * @param netif network interface on which create the IP-Address + * @param ipaddr ip address to initialize + */ +static void +autoip_create_addr(struct netif *netif, ip4_addr_t *ipaddr) +{ + struct autoip *autoip = netif_autoip_data(netif); + + /* Here we create an IP-Address out of range 169.254.1.0 to 169.254.254.255 + * compliant to RFC 3927 Section 2.1 + * We have 254 * 256 possibilities */ + + u32_t addr = lwip_ntohl(LWIP_AUTOIP_CREATE_SEED_ADDR(netif)); + addr += autoip->tried_llipaddr; + addr = AUTOIP_NET | (addr & 0xffff); + /* Now, 169.254.0.0 <= addr <= 169.254.255.255 */ + + if (addr < AUTOIP_RANGE_START) { + addr += AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1; + } + if (addr > AUTOIP_RANGE_END) { + addr -= AUTOIP_RANGE_END - AUTOIP_RANGE_START + 1; + } + LWIP_ASSERT("AUTOIP address not in range", (addr >= AUTOIP_RANGE_START) && + (addr <= AUTOIP_RANGE_END)); + ip4_addr_set_u32(ipaddr, lwip_htonl(addr)); + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_create_addr(): tried_llipaddr=%"U16_F", %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + (u16_t)(autoip->tried_llipaddr), ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), + ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr))); +} + +/** + * Sends an ARP probe from a network interface + * + * @param netif network interface used to send the probe + */ +static err_t +autoip_arp_probe(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + /* this works because netif->ip_addr is ANY */ + return etharp_request(netif, &autoip->llipaddr); +} + +/** + * Sends an ARP announce from a network interface + * + * @param netif network interface used to send the announce + */ +static err_t +autoip_arp_announce(struct netif *netif) +{ + return etharp_gratuitous(netif); +} + +/** + * Configure interface for use with current LL IP-Address + * + * @param netif network interface to configure with current LL IP-Address + */ +static err_t +autoip_bind(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + ip4_addr_t sn_mask, gw_addr; + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_bind(netif=%p) %c%c%"U16_F" %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num, + ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr), + ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr))); + + IP4_ADDR(&sn_mask, 255, 255, 0, 0); + IP4_ADDR(&gw_addr, 0, 0, 0, 0); + + netif_set_addr(netif, &autoip->llipaddr, &sn_mask, &gw_addr); + /* interface is used by routing now that an address is set */ + + return ERR_OK; +} + +/** + * @ingroup autoip + * Start AutoIP client + * + * @param netif network interface on which start the AutoIP client + */ +err_t +autoip_start(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + err_t result = ERR_OK; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;); + + /* Set IP-Address, Netmask and Gateway to 0 to make sure that + * ARP Packets are formed correctly + */ + netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], + netif->name[1], (u16_t)netif->num)); + if (autoip == NULL) { + /* no AutoIP client attached yet? */ + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_start(): starting new AUTOIP client\n")); + autoip = (struct autoip *)mem_calloc(1, sizeof(struct autoip)); + if (autoip == NULL) { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_start(): could not allocate autoip\n")); + return ERR_MEM; + } + /* store this AutoIP client in the netif */ + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP, autoip); + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_start(): allocated autoip")); + } else { + autoip->state = AUTOIP_STATE_OFF; + autoip->ttw = 0; + autoip->sent_num = 0; + ip4_addr_set_zero(&autoip->llipaddr); + autoip->lastconflict = 0; + } + + autoip_create_addr(netif, &(autoip->llipaddr)); + autoip_start_probing(netif); + + return result; +} + +static void +autoip_start_probing(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + + autoip->state = AUTOIP_STATE_PROBING; + autoip->sent_num = 0; + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_start_probing(): changing state to PROBING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr), + ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr))); + + /* time to wait to first probe, this is randomly + * chosen out of 0 to PROBE_WAIT seconds. + * compliant to RFC 3927 Section 2.2.1 + */ + autoip->ttw = (u16_t)(LWIP_AUTOIP_RAND(netif) % (PROBE_WAIT * AUTOIP_TICKS_PER_SECOND)); + + /* + * if we tried more then MAX_CONFLICTS we must limit our rate for + * acquiring and probing address + * compliant to RFC 3927 Section 2.2.1 + */ + if (autoip->tried_llipaddr > MAX_CONFLICTS) { + autoip->ttw = RATE_LIMIT_INTERVAL * AUTOIP_TICKS_PER_SECOND; + } +} + +/** + * Handle a possible change in the network configuration. + * + * If there is an AutoIP address configured, take the interface down + * and begin probing with the same address. + */ +void +autoip_network_changed(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + + if (autoip && (autoip->state != AUTOIP_STATE_OFF)) { + autoip_start_probing(netif); + } +} + +/** + * @ingroup autoip + * Stop AutoIP client + * + * @param netif network interface on which stop the AutoIP client + */ +err_t +autoip_stop(struct netif *netif) +{ + struct autoip *autoip = netif_autoip_data(netif); + + LWIP_ASSERT_CORE_LOCKED(); + if (autoip != NULL) { + autoip->state = AUTOIP_STATE_OFF; + if (ip4_addr_islinklocal(netif_ip4_addr(netif))) { + netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); + } + } + return ERR_OK; +} + +/** + * Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds + */ +void +autoip_tmr(void) +{ + struct netif *netif; + /* loop through netif's */ + NETIF_FOREACH(netif) { + struct autoip *autoip = netif_autoip_data(netif); + /* only act on AutoIP configured interfaces */ + if (autoip != NULL) { + if (autoip->lastconflict > 0) { + autoip->lastconflict--; + } + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, + ("autoip_tmr() AutoIP-State: %"U16_F", ttw=%"U16_F"\n", + (u16_t)(autoip->state), autoip->ttw)); + + if (autoip->ttw > 0) { + autoip->ttw--; + } + + switch (autoip->state) { + case AUTOIP_STATE_PROBING: + if (autoip->ttw == 0) { + if (autoip->sent_num >= PROBE_NUM) { + /* Switch to ANNOUNCING: now we can bind to an IP address and use it */ + autoip->state = AUTOIP_STATE_ANNOUNCING; + autoip_bind(netif); + /* autoip_bind() calls netif_set_addr(): this triggers a gratuitous ARP + which counts as an announcement */ + autoip->sent_num = 1; + autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND; + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_tmr(): changing state to ANNOUNCING: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr), + ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr))); + } else { + autoip_arp_probe(netif); + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_tmr() PROBING Sent Probe\n")); + autoip->sent_num++; + if (autoip->sent_num == PROBE_NUM) { + /* calculate time to wait to for announce */ + autoip->ttw = ANNOUNCE_WAIT * AUTOIP_TICKS_PER_SECOND; + } else { + /* calculate time to wait to next probe */ + autoip->ttw = (u16_t)((LWIP_AUTOIP_RAND(netif) % + ((PROBE_MAX - PROBE_MIN) * AUTOIP_TICKS_PER_SECOND) ) + + PROBE_MIN * AUTOIP_TICKS_PER_SECOND); + } + } + } + break; + + case AUTOIP_STATE_ANNOUNCING: + if (autoip->ttw == 0) { + autoip_arp_announce(netif); + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_tmr() ANNOUNCING Sent Announce\n")); + autoip->ttw = ANNOUNCE_INTERVAL * AUTOIP_TICKS_PER_SECOND; + autoip->sent_num++; + + if (autoip->sent_num >= ANNOUNCE_NUM) { + autoip->state = AUTOIP_STATE_BOUND; + autoip->sent_num = 0; + autoip->ttw = 0; + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("autoip_tmr(): changing state to BOUND: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(&autoip->llipaddr), ip4_addr2_16(&autoip->llipaddr), + ip4_addr3_16(&autoip->llipaddr), ip4_addr4_16(&autoip->llipaddr))); + } + } + break; + + default: + /* nothing to do in other states */ + break; + } + } + } +} + +/** + * Handles every incoming ARP Packet, called by etharp_input(). + * + * @param netif network interface to use for autoip processing + * @param hdr Incoming ARP packet + */ +void +autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr) +{ + struct autoip *autoip = netif_autoip_data(netif); + + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE, ("autoip_arp_reply()\n")); + if ((autoip != NULL) && (autoip->state != AUTOIP_STATE_OFF)) { + /* when ip.src == llipaddr && hw.src != netif->hwaddr + * + * when probing ip.dst == llipaddr && hw.src != netif->hwaddr + * we have a conflict and must solve it + */ + ip4_addr_t sipaddr, dipaddr; + struct eth_addr netifaddr; + SMEMCPY(netifaddr.addr, netif->hwaddr, ETH_HWADDR_LEN); + + /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). + */ + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr); + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr); + + if (autoip->state == AUTOIP_STATE_PROBING) { + /* RFC 3927 Section 2.2.1: + * from beginning to after ANNOUNCE_WAIT + * seconds we have a conflict if + * ip.src == llipaddr OR + * ip.dst == llipaddr && hw.src != own hwaddr + */ + if ((ip4_addr_cmp(&sipaddr, &autoip->llipaddr)) || + (ip4_addr_isany_val(sipaddr) && + ip4_addr_cmp(&dipaddr, &autoip->llipaddr) && + !eth_addr_cmp(&netifaddr, &hdr->shwaddr))) { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, + ("autoip_arp_reply(): Probe Conflict detected\n")); + autoip_restart(netif); + } + } else { + /* RFC 3927 Section 2.5: + * in any state we have a conflict if + * ip.src == llipaddr && hw.src != own hwaddr + */ + if (ip4_addr_cmp(&sipaddr, &autoip->llipaddr) && + !eth_addr_cmp(&netifaddr, &hdr->shwaddr)) { + LWIP_DEBUGF(AUTOIP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, + ("autoip_arp_reply(): Conflicting ARP-Packet detected\n")); + autoip_handle_arp_conflict(netif); + } + } + } +} + +/** check if AutoIP supplied netif->ip_addr + * + * @param netif the netif to check + * @return 1 if AutoIP supplied netif->ip_addr (state BOUND or ANNOUNCING), + * 0 otherwise + */ +u8_t +autoip_supplied_address(const struct netif *netif) +{ + if ((netif != NULL) && (netif_autoip_data(netif) != NULL)) { + struct autoip *autoip = netif_autoip_data(netif); + return (autoip->state == AUTOIP_STATE_BOUND) || (autoip->state == AUTOIP_STATE_ANNOUNCING); + } + return 0; +} + +u8_t +autoip_accept_packet(struct netif *netif, const ip4_addr_t *addr) +{ + struct autoip *autoip = netif_autoip_data(netif); + return (autoip != NULL) && ip4_addr_cmp(addr, &(autoip->llipaddr)); +} + +#endif /* LWIP_IPV4 && LWIP_AUTOIP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c new file mode 100644 index 0000000..534574f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/dhcp.c @@ -0,0 +1,1990 @@ +/** + * @file + * Dynamic Host Configuration Protocol client + * + * @defgroup dhcp4 DHCPv4 + * @ingroup ip4 + * DHCP (IPv4) related functions + * This is a DHCP client for the lwIP TCP/IP stack. It aims to conform + * with RFC 2131 and RFC 2132. + * + * @todo: + * - Support for interfaces other than Ethernet (SLIP, PPP, ...) + * + * Options: + * @ref DHCP_COARSE_TIMER_SECS (recommended 60 which is a minute) + * @ref DHCP_FINE_TIMER_MSECS (recommended 500 which equals TCP coarse timer) + * + * dhcp_start() starts a DHCP client instance which + * configures the interface by obtaining an IP address lease and maintaining it. + * + * Use dhcp_release() to end the lease and use dhcp_stop() + * to remove the DHCP client. + * + * @see LWIP_HOOK_DHCP_APPEND_OPTIONS + * @see LWIP_HOOK_DHCP_PARSE_OPTION + * + * @see netifapi_dhcp4 + */ + +/* + * Copyright (c) 2001-2004 Leon Woestenberg + * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. + * + * Author: Leon Woestenberg + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 && LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/def.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "lwip/dns.h" +#include "lwip/etharp.h" +#include "lwip/prot/dhcp.h" +#include "lwip/prot/iana.h" + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif +#ifndef LWIP_HOOK_DHCP_APPEND_OPTIONS +#define LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr) +#endif +#ifndef LWIP_HOOK_DHCP_PARSE_OPTION +#define LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, offset) do { LWIP_UNUSED_ARG(msg); } while(0) +#endif + +/** DHCP_CREATE_RAND_XID: if this is set to 1, the xid is created using + * LWIP_RAND() (this overrides DHCP_GLOBAL_XID) + */ +#ifndef DHCP_CREATE_RAND_XID +#define DHCP_CREATE_RAND_XID 1 +#endif + +/** Default for DHCP_GLOBAL_XID is 0xABCD0000 + * This can be changed by defining DHCP_GLOBAL_XID and DHCP_GLOBAL_XID_HEADER, e.g. + * \#define DHCP_GLOBAL_XID_HEADER "stdlib.h" + * \#define DHCP_GLOBAL_XID rand() + */ +#ifdef DHCP_GLOBAL_XID_HEADER +#include DHCP_GLOBAL_XID_HEADER /* include optional starting XID generation prototypes */ +#endif + +/** DHCP_OPTION_MAX_MSG_SIZE is set to the MTU + * MTU is checked to be big enough in dhcp_start */ +#define DHCP_MAX_MSG_LEN(netif) (netif->mtu) +#define DHCP_MAX_MSG_LEN_MIN_REQUIRED 576 +/** Minimum length for reply before packet is parsed */ +#define DHCP_MIN_REPLY_LEN 44 + +#define REBOOT_TRIES 2 + +#if LWIP_DNS && LWIP_DHCP_MAX_DNS_SERVERS +#if DNS_MAX_SERVERS > LWIP_DHCP_MAX_DNS_SERVERS +#define LWIP_DHCP_PROVIDE_DNS_SERVERS LWIP_DHCP_MAX_DNS_SERVERS +#else +#define LWIP_DHCP_PROVIDE_DNS_SERVERS DNS_MAX_SERVERS +#endif +#else +#define LWIP_DHCP_PROVIDE_DNS_SERVERS 0 +#endif + +/** Option handling: options are parsed in dhcp_parse_reply + * and saved in an array where other functions can load them from. + * This might be moved into the struct dhcp (not necessarily since + * lwIP is single-threaded and the array is only used while in recv + * callback). */ +enum dhcp_option_idx { + DHCP_OPTION_IDX_OVERLOAD = 0, + DHCP_OPTION_IDX_MSG_TYPE, + DHCP_OPTION_IDX_SERVER_ID, + DHCP_OPTION_IDX_LEASE_TIME, + DHCP_OPTION_IDX_T1, + DHCP_OPTION_IDX_T2, + DHCP_OPTION_IDX_SUBNET_MASK, + DHCP_OPTION_IDX_ROUTER, +#if LWIP_DHCP_PROVIDE_DNS_SERVERS + DHCP_OPTION_IDX_DNS_SERVER, + DHCP_OPTION_IDX_DNS_SERVER_LAST = DHCP_OPTION_IDX_DNS_SERVER + LWIP_DHCP_PROVIDE_DNS_SERVERS - 1, +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ +#if LWIP_DHCP_GET_NTP_SRV + DHCP_OPTION_IDX_NTP_SERVER, + DHCP_OPTION_IDX_NTP_SERVER_LAST = DHCP_OPTION_IDX_NTP_SERVER + LWIP_DHCP_MAX_NTP_SERVERS - 1, +#endif /* LWIP_DHCP_GET_NTP_SRV */ + DHCP_OPTION_IDX_MAX +}; + +/** Holds the decoded option values, only valid while in dhcp_recv. + @todo: move this into struct dhcp? */ +u32_t dhcp_rx_options_val[DHCP_OPTION_IDX_MAX]; +/** Holds a flag which option was received and is contained in dhcp_rx_options_val, + only valid while in dhcp_recv. + @todo: move this into struct dhcp? */ +u8_t dhcp_rx_options_given[DHCP_OPTION_IDX_MAX]; + +static u8_t dhcp_discover_request_options[] = { + DHCP_OPTION_SUBNET_MASK, + DHCP_OPTION_ROUTER, + DHCP_OPTION_BROADCAST +#if LWIP_DHCP_PROVIDE_DNS_SERVERS + , DHCP_OPTION_DNS_SERVER +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ +#if LWIP_DHCP_GET_NTP_SRV + , DHCP_OPTION_NTP +#endif /* LWIP_DHCP_GET_NTP_SRV */ +}; + +#ifdef DHCP_GLOBAL_XID +static u32_t xid; +static u8_t xid_initialised; +#endif /* DHCP_GLOBAL_XID */ + +#define dhcp_option_given(dhcp, idx) (dhcp_rx_options_given[idx] != 0) +#define dhcp_got_option(dhcp, idx) (dhcp_rx_options_given[idx] = 1) +#define dhcp_clear_option(dhcp, idx) (dhcp_rx_options_given[idx] = 0) +#define dhcp_clear_all_options(dhcp) (memset(dhcp_rx_options_given, 0, sizeof(dhcp_rx_options_given))) +#define dhcp_get_option_value(dhcp, idx) (dhcp_rx_options_val[idx]) +#define dhcp_set_option_value(dhcp, idx, val) (dhcp_rx_options_val[idx] = (val)) + +static struct udp_pcb *dhcp_pcb; +static u8_t dhcp_pcb_refcount; + +/* DHCP client state machine functions */ +static err_t dhcp_discover(struct netif *netif); +static err_t dhcp_select(struct netif *netif); +static void dhcp_bind(struct netif *netif); +#if DHCP_DOES_ARP_CHECK +static err_t dhcp_decline(struct netif *netif); +#endif /* DHCP_DOES_ARP_CHECK */ +static err_t dhcp_rebind(struct netif *netif); +static err_t dhcp_reboot(struct netif *netif); +static void dhcp_set_state(struct dhcp *dhcp, u8_t new_state); + +/* receive, unfold, parse and free incoming messages */ +static void dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port); + +/* set the DHCP timers */ +static void dhcp_timeout(struct netif *netif); +static void dhcp_t1_timeout(struct netif *netif); +static void dhcp_t2_timeout(struct netif *netif); + +/* build outgoing messages */ +/* create a DHCP message, fill in common headers */ +static struct pbuf *dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len); +/* add a DHCP option (type, then length in bytes) */ +static u16_t dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len); +/* add option values */ +static u16_t dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value); +static u16_t dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value); +static u16_t dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value); +#if LWIP_NETIF_HOSTNAME +static u16_t dhcp_option_hostname(u16_t options_out_len, u8_t *options, struct netif *netif); +#endif /* LWIP_NETIF_HOSTNAME */ +/* always add the DHCP options trailer to end and pad */ +static void dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out); + +/** Ensure DHCP PCB is allocated and bound */ +static err_t +dhcp_inc_pcb_refcount(void) +{ + if (dhcp_pcb_refcount == 0) { + LWIP_ASSERT("dhcp_inc_pcb_refcount(): memory leak", dhcp_pcb == NULL); + + /* allocate UDP PCB */ + dhcp_pcb = udp_new(); + + if (dhcp_pcb == NULL) { + return ERR_MEM; + } + + ip_set_option(dhcp_pcb, SOF_BROADCAST); + + /* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */ + udp_bind(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_CLIENT); + udp_connect(dhcp_pcb, IP4_ADDR_ANY, LWIP_IANA_PORT_DHCP_SERVER); + udp_recv(dhcp_pcb, dhcp_recv, NULL); + } + + dhcp_pcb_refcount++; + + return ERR_OK; +} + +/** Free DHCP PCB if the last netif stops using it */ +static void +dhcp_dec_pcb_refcount(void) +{ + LWIP_ASSERT("dhcp_pcb_refcount(): refcount error", (dhcp_pcb_refcount > 0)); + dhcp_pcb_refcount--; + + if (dhcp_pcb_refcount == 0) { + udp_remove(dhcp_pcb); + dhcp_pcb = NULL; + } +} + +/** + * Back-off the DHCP client (because of a received NAK response). + * + * Back-off the DHCP client because of a received NAK. Receiving a + * NAK means the client asked for something non-sensible, for + * example when it tries to renew a lease obtained on another network. + * + * We clear any existing set IP address and restart DHCP negotiation + * afresh (as per RFC2131 3.2.3). + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_nak(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_nak(netif=%p) %c%c%"U16_F"\n", + (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + /* Change to a defined state - set this before assigning the address + to ensure the callback can use dhcp_supplied_address() */ + dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF); + /* remove IP address from interface (must no longer be used, as per RFC2131) */ + netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); + /* We can immediately restart discovery */ + dhcp_discover(netif); +} + +#if DHCP_DOES_ARP_CHECK +/** + * Checks if the offered IP address is already in use. + * + * It does so by sending an ARP request for the offered address and + * entering CHECKING state. If no ARP reply is received within a small + * interval, the address is assumed to be free for use by us. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_check(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + err_t result; + u16_t msecs; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_check(netif=%p) %c%c\n", (void *)netif, (s16_t)netif->name[0], + (s16_t)netif->name[1])); + dhcp_set_state(dhcp, DHCP_STATE_CHECKING); + /* create an ARP query for the offered IP address, expecting that no host + responds, as the IP address should not be in use. */ + result = etharp_query(netif, &dhcp->offered_ip_addr, NULL); + if (result != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_check: could not perform ARP query\n")); + } + if (dhcp->tries < 255) { + dhcp->tries++; + } + msecs = 500; + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_check(): set request timeout %"U16_F" msecs\n", msecs)); +} +#endif /* DHCP_DOES_ARP_CHECK */ + +/** + * Remember the configuration offered by a DHCP server. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_offer(struct netif *netif, struct dhcp_msg *msg_in) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_handle_offer(netif=%p) %c%c%"U16_F"\n", + (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + /* obtain the server address */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SERVER_ID)) { + dhcp->request_timeout = 0; /* stop timer */ + + ip_addr_set_ip4_u32(&dhcp->server_ip_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SERVER_ID))); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): server 0x%08"X32_F"\n", + ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr)))); + /* remember offered address */ + ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_handle_offer(): offer for 0x%08"X32_F"\n", + ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + dhcp_select(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_handle_offer(netif=%p) did not get server ID!\n", (void *)netif)); + } +} + +/** + * Select a DHCP server offer out of all offers. + * + * Simply select the first offer received. + * + * @param netif the netif under DHCP control + * @return lwIP specific error (see error.h) + */ +static err_t +dhcp_select(struct netif *netif) +{ + struct dhcp *dhcp; + err_t result; + u16_t msecs; + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_ERROR("dhcp_select: netif != NULL", (netif != NULL), return ERR_ARG;); + dhcp = netif_dhcp_data(netif); + LWIP_ERROR("dhcp_select: dhcp != NULL", (dhcp != NULL), return ERR_VAL;); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_select(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + dhcp_set_state(dhcp, DHCP_STATE_REQUESTING); + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + + /* MUST request the offered IP address */ + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4); + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4); + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&dhcp->server_ip_addr)))); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + } + +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REQUESTING, msg_out, DHCP_REQUEST, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + /* send broadcast to any DHCP server */ + result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY); + pbuf_free(p_out); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_select: REQUESTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("dhcp_select: could not allocate DHCP request\n")); + result = ERR_MEM; + } + if (dhcp->tries < 255) { + dhcp->tries++; + } + msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000); + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_select(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * The DHCP timer that checks for lease renewal/rebind timeouts. + * Must be called once a minute (see @ref DHCP_COARSE_TIMER_SECS). + */ +void +dhcp_coarse_tmr(void) +{ + struct netif *netif; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_coarse_tmr()\n")); + /* iterate through all network interfaces */ + NETIF_FOREACH(netif) { + /* only act on DHCP configured interfaces */ + struct dhcp *dhcp = netif_dhcp_data(netif); + if ((dhcp != NULL) && (dhcp->state != DHCP_STATE_OFF)) { + /* compare lease time to expire timeout */ + if (dhcp->t0_timeout && (++dhcp->lease_used == dhcp->t0_timeout)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t0 timeout\n")); + /* this clients' lease time has expired */ + dhcp_release_and_stop(netif); + dhcp_start(netif); + /* timer is active (non zero), and triggers (zeroes) now? */ + } else if (dhcp->t2_rebind_time && (dhcp->t2_rebind_time-- == 1)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t2 timeout\n")); + /* this clients' rebind timeout triggered */ + dhcp_t2_timeout(netif); + /* timer is active (non zero), and triggers (zeroes) now */ + } else if (dhcp->t1_renew_time && (dhcp->t1_renew_time-- == 1)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_coarse_tmr(): t1 timeout\n")); + /* this clients' renewal timeout triggered */ + dhcp_t1_timeout(netif); + } + } + } +} + +/** + * DHCP transaction timeout handling (this function must be called every 500ms, + * see @ref DHCP_FINE_TIMER_MSECS). + * + * A DHCP server is expected to respond within a short period of time. + * This timer checks whether an outstanding DHCP request is timed out. + */ +void +dhcp_fine_tmr(void) +{ + struct netif *netif; + /* loop through netif's */ + NETIF_FOREACH(netif) { + struct dhcp *dhcp = netif_dhcp_data(netif); + /* only act on DHCP configured interfaces */ + if (dhcp != NULL) { + /* timer is active (non zero), and is about to trigger now */ + if (dhcp->request_timeout > 1) { + dhcp->request_timeout--; + } else if (dhcp->request_timeout == 1) { + dhcp->request_timeout--; + /* { dhcp->request_timeout == 0 } */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_fine_tmr(): request timeout\n")); + /* this client's request timeout triggered */ + dhcp_timeout(netif); + } + } + } +} + +/** + * A DHCP negotiation transaction, or ARP request, has timed out. + * + * The timer that was started with the DHCP or ARP request has + * timed out, indicating no response was received in time. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout()\n")); + /* back-off period has passed, or server selection timed out */ + if ((dhcp->state == DHCP_STATE_BACKING_OFF) || (dhcp->state == DHCP_STATE_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_timeout(): restarting discovery\n")); + dhcp_discover(netif); + /* receiving the requested lease timed out */ + } else if (dhcp->state == DHCP_STATE_REQUESTING) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, DHCP request timed out\n")); + if (dhcp->tries <= 5) { + dhcp_select(netif); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): REQUESTING, releasing, restarting\n")); + dhcp_release_and_stop(netif); + dhcp_start(netif); + } +#if DHCP_DOES_ARP_CHECK + /* received no ARP reply for the offered address (which is good) */ + } else if (dhcp->state == DHCP_STATE_CHECKING) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_timeout(): CHECKING, ARP request timed out\n")); + if (dhcp->tries <= 1) { + dhcp_check(netif); + /* no ARP replies on the offered address, + looks like the IP address is indeed free */ + } else { + /* bind the interface to the offered address */ + dhcp_bind(netif); + } +#endif /* DHCP_DOES_ARP_CHECK */ + } else if (dhcp->state == DHCP_STATE_REBOOTING) { + if (dhcp->tries < REBOOT_TRIES) { + dhcp_reboot(netif); + } else { + dhcp_discover(netif); + } + } +} + +/** + * The renewal period has timed out. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_t1_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_t1_timeout()\n")); + if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || + (dhcp->state == DHCP_STATE_RENEWING)) { + /* just retry to renew - note that the rebind timer (t2) will + * eventually time-out if renew tries fail. */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("dhcp_t1_timeout(): must renew\n")); + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_STATE_RENEWING, not DHCP_STATE_BOUND */ + dhcp_renew(netif); + /* Calculate next timeout */ + if (((dhcp->t2_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) { + dhcp->t1_renew_time = (u16_t)((dhcp->t2_timeout - dhcp->lease_used) / 2); + } + } +} + +/** + * The rebind period has timed out. + * + * @param netif the netif under DHCP control + */ +static void +dhcp_t2_timeout(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_t2_timeout()\n")); + if ((dhcp->state == DHCP_STATE_REQUESTING) || (dhcp->state == DHCP_STATE_BOUND) || + (dhcp->state == DHCP_STATE_RENEWING) || (dhcp->state == DHCP_STATE_REBINDING)) { + /* just retry to rebind */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + ("dhcp_t2_timeout(): must rebind\n")); + /* This slightly different to RFC2131: DHCPREQUEST will be sent from state + DHCP_STATE_REBINDING, not DHCP_STATE_BOUND */ + dhcp_rebind(netif); + /* Calculate next timeout */ + if (((dhcp->t0_timeout - dhcp->lease_used) / 2) >= ((60 + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS)) { + dhcp->t2_rebind_time = (u16_t)((dhcp->t0_timeout - dhcp->lease_used) / 2); + } + } +} + +/** + * Handle a DHCP ACK packet + * + * @param netif the netif under DHCP control + */ +static void +dhcp_handle_ack(struct netif *netif, struct dhcp_msg *msg_in) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + +#if LWIP_DHCP_PROVIDE_DNS_SERVERS || LWIP_DHCP_GET_NTP_SRV + u8_t n; +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS || LWIP_DHCP_GET_NTP_SRV */ +#if LWIP_DHCP_GET_NTP_SRV + ip4_addr_t ntp_server_addrs[LWIP_DHCP_MAX_NTP_SERVERS]; +#endif + + /* clear options we might not get from the ACK */ + ip4_addr_set_zero(&dhcp->offered_sn_mask); + ip4_addr_set_zero(&dhcp->offered_gw_addr); +#if LWIP_DHCP_BOOTP_FILE + ip4_addr_set_zero(&dhcp->offered_si_addr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* lease time given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_LEASE_TIME)) { + /* remember offered lease time */ + dhcp->offered_t0_lease = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_LEASE_TIME); + } + /* renewal period given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T1)) { + /* remember given renewal period */ + dhcp->offered_t1_renew = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T1); + } else { + /* calculate safe periods for renewal */ + dhcp->offered_t1_renew = dhcp->offered_t0_lease / 2; + } + + /* renewal period given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_T2)) { + /* remember given rebind period */ + dhcp->offered_t2_rebind = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_T2); + } else { + /* calculate safe periods for rebinding (offered_t0_lease * 0.875 -> 87.5%)*/ + dhcp->offered_t2_rebind = (dhcp->offered_t0_lease * 7U) / 8U; + } + + /* (y)our internet address */ + ip4_addr_copy(dhcp->offered_ip_addr, msg_in->yiaddr); + +#if LWIP_DHCP_BOOTP_FILE + /* copy boot server address, + boot file name copied in dhcp_parse_reply if not overloaded */ + ip4_addr_copy(dhcp->offered_si_addr, msg_in->siaddr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* subnet mask given? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_SUBNET_MASK)) { + /* remember given subnet mask */ + ip4_addr_set_u32(&dhcp->offered_sn_mask, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_SUBNET_MASK))); + dhcp->subnet_mask_given = 1; + } else { + dhcp->subnet_mask_given = 0; + } + + /* gateway router */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_ROUTER)) { + ip4_addr_set_u32(&dhcp->offered_gw_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_ROUTER))); + } + +#if LWIP_DHCP_GET_NTP_SRV + /* NTP servers */ + for (n = 0; (n < LWIP_DHCP_MAX_NTP_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n); n++) { + ip4_addr_set_u32(&ntp_server_addrs[n], lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_NTP_SERVER + n))); + } + dhcp_set_ntp_servers(n, ntp_server_addrs); +#endif /* LWIP_DHCP_GET_NTP_SRV */ + +#if LWIP_DHCP_PROVIDE_DNS_SERVERS + /* DNS servers */ + for (n = 0; (n < LWIP_DHCP_PROVIDE_DNS_SERVERS) && dhcp_option_given(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n); n++) { + ip_addr_t dns_addr; + ip_addr_set_ip4_u32_val(dns_addr, lwip_htonl(dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_DNS_SERVER + n))); + dns_setserver(n, &dns_addr); + } +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ +} + +/** + * @ingroup dhcp4 + * Set a statically allocated struct dhcp to work with. + * Using this prevents dhcp_start to allocate it using mem_malloc. + * + * @param netif the netif for which to set the struct dhcp + * @param dhcp (uninitialised) dhcp struct allocated by the application + */ +void +dhcp_set_struct(struct netif *netif, struct dhcp *dhcp) +{ + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("dhcp != NULL", dhcp != NULL); + LWIP_ASSERT("netif already has a struct dhcp set", netif_dhcp_data(netif) == NULL); + + /* clear data structure */ + memset(dhcp, 0, sizeof(struct dhcp)); + /* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */ + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp); +} + +/** + * @ingroup dhcp4 + * Removes a struct dhcp from a netif. + * + * ATTENTION: Only use this when not using dhcp_set_struct() to allocate the + * struct dhcp since the memory is passed back to the heap. + * + * @param netif the netif from which to remove the struct dhcp + */ +void dhcp_cleanup(struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + + if (netif_dhcp_data(netif) != NULL) { + mem_free(netif_dhcp_data(netif)); + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, NULL); + } +} + +/** + * @ingroup dhcp4 + * Start DHCP negotiation for a network interface. + * + * If no DHCP client instance was attached to this interface, + * a new client is created first. If a DHCP client instance + * was already present, it restarts negotiation. + * + * @param netif The lwIP network interface + * @return lwIP error code + * - ERR_OK - No error + * - ERR_MEM - Out of memory + */ +err_t +dhcp_start(struct netif *netif) +{ + struct dhcp *dhcp; + err_t result; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ERROR("netif != NULL", (netif != NULL), return ERR_ARG;); + LWIP_ERROR("netif is not up, old style port?", netif_is_up(netif), return ERR_ARG;); + dhcp = netif_dhcp_data(netif); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* check MTU of the netif */ + if (netif->mtu < DHCP_MAX_MSG_LEN_MIN_REQUIRED) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): Cannot use this netif with DHCP: MTU is too small\n")); + return ERR_MEM; + } + + /* no DHCP client attached yet? */ + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): mallocing new DHCP client\n")); + dhcp = (struct dhcp *)mem_malloc(sizeof(struct dhcp)); + if (dhcp == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): could not allocate dhcp\n")); + return ERR_MEM; + } + + /* store this dhcp client in the netif */ + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, dhcp); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): allocated dhcp")); + /* already has DHCP client attached */ + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_start(): restarting DHCP configuration\n")); + + if (dhcp->pcb_allocated != 0) { + dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */ + } + /* dhcp is cleared below, no need to reset flag*/ + } + + /* clear data structure */ + memset(dhcp, 0, sizeof(struct dhcp)); + /* dhcp_set_state(&dhcp, DHCP_STATE_OFF); */ + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_start(): starting DHCP configuration\n")); + + if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */ + return ERR_MEM; + } + dhcp->pcb_allocated = 1; + + if (!netif_is_link_up(netif)) { + /* set state INIT and wait for dhcp_network_changed() to call dhcp_discover() */ + dhcp_set_state(dhcp, DHCP_STATE_INIT); + return ERR_OK; + } + + /* (re)start the DHCP negotiation */ + result = dhcp_discover(netif); + if (result != ERR_OK) { + /* free resources allocated above */ + dhcp_release_and_stop(netif); + return ERR_MEM; + } + return result; +} + +/** + * @ingroup dhcp4 + * Inform a DHCP server of our manual configuration. + * + * This informs DHCP servers of our fixed IP address configuration + * by sending an INFORM message. It does not involve DHCP address + * configuration, it is just here to be nice to the network. + * + * @param netif The lwIP network interface + */ +void +dhcp_inform(struct netif *netif) +{ + struct dhcp dhcp; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + + if (dhcp_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP PCB is allocated */ + return; + } + + memset(&dhcp, 0, sizeof(struct dhcp)); + dhcp_set_state(&dhcp, DHCP_STATE_INFORMING); + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, &dhcp, DHCP_INFORM, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, &dhcp, DHCP_STATE_INFORMING, msg_out, DHCP_INFORM, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_inform: INFORMING\n")); + + udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif); + + pbuf_free(p_out); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_inform: could not allocate DHCP request\n")); + } + + dhcp_dec_pcb_refcount(); /* delete DHCP PCB if not needed any more */ +} + +/** Handle a possible change in the network configuration. + * + * This enters the REBOOTING state to verify that the currently bound + * address is still valid. + */ +void +dhcp_network_changed(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + + if (!dhcp) { + return; + } + switch (dhcp->state) { + case DHCP_STATE_REBINDING: + case DHCP_STATE_RENEWING: + case DHCP_STATE_BOUND: + case DHCP_STATE_REBOOTING: + dhcp->tries = 0; + dhcp_reboot(netif); + break; + case DHCP_STATE_OFF: + /* stay off */ + break; + default: + LWIP_ASSERT("invalid dhcp->state", dhcp->state <= DHCP_STATE_BACKING_OFF); + /* INIT/REQUESTING/CHECKING/BACKING_OFF restart with new 'rid' because the + state changes, SELECTING: continue with current 'rid' as we stay in the + same state */ +#if LWIP_DHCP_AUTOIP_COOP + if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + /* ensure we start with short timeouts, even if already discovering */ + dhcp->tries = 0; + dhcp_discover(netif); + break; + } +} + +#if DHCP_DOES_ARP_CHECK +/** + * Match an ARP reply with the offered IP address: + * check whether the offered IP address is not in use using ARP + * + * @param netif the network interface on which the reply was received + * @param addr The IP address we received a reply from + */ +void +dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr) +{ + struct dhcp *dhcp; + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + dhcp = netif_dhcp_data(netif); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_arp_reply()\n")); + /* is a DHCP client doing an ARP check? */ + if ((dhcp != NULL) && (dhcp->state == DHCP_STATE_CHECKING)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_arp_reply(): CHECKING, arp reply for 0x%08"X32_F"\n", + ip4_addr_get_u32(addr))); + /* did a host respond with the address we + were offered by the DHCP server? */ + if (ip4_addr_cmp(addr, &dhcp->offered_ip_addr)) { + /* we will not accept the offered address */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE | LWIP_DBG_LEVEL_WARNING, + ("dhcp_arp_reply(): arp reply matched with offered address, declining\n")); + dhcp_decline(netif); + } + } +} + +/** + * Decline an offered lease. + * + * Tell the DHCP server we do not accept the offered address. + * One reason to decline the lease is when we find out the address + * is already in use by another host (through ARP). + * + * @param netif the netif under DHCP control + */ +static err_t +dhcp_decline(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + err_t result; + u16_t msecs; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline()\n")); + dhcp_set_state(dhcp, DHCP_STATE_BACKING_OFF); + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_DECLINE, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4); + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_BACKING_OFF, msg_out, DHCP_DECLINE, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + /* per section 4.4.4, broadcast DECLINE messages */ + result = udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY); + pbuf_free(p_out); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_decline: BACKING OFF\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_decline: could not allocate DHCP request\n")); + result = ERR_MEM; + } + if (dhcp->tries < 255) { + dhcp->tries++; + } + msecs = 10 * 1000; + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_decline(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} +#endif /* DHCP_DOES_ARP_CHECK */ + + +/** + * Start the DHCP process, discover a DHCP server. + * + * @param netif the netif under DHCP control + */ +static err_t +dhcp_discover(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + err_t result = ERR_OK; + u16_t msecs; + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover()\n")); + + ip4_addr_set_any(&dhcp->offered_ip_addr); + dhcp_set_state(dhcp, DHCP_STATE_SELECTING); + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_DISCOVER, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: making request\n")); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + } + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_SELECTING, msg_out, DHCP_DISCOVER, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: sendto(DISCOVER, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER)\n")); + udp_sendto_if_src(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif, IP4_ADDR_ANY); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_discover: deleting()ing\n")); + pbuf_free(p_out); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover: SELECTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_discover: could not allocate DHCP request\n")); + } + if (dhcp->tries < 255) { + dhcp->tries++; + } +#if LWIP_DHCP_AUTOIP_COOP + if (dhcp->tries >= LWIP_DHCP_AUTOIP_COOP_TRIES && dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_OFF) { + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_ON; + autoip_start(netif); + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + msecs = (u16_t)((dhcp->tries < 6 ? 1 << dhcp->tries : 60) * 1000); + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_discover(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + + +/** + * Bind the interface to the offered IP address. + * + * @param netif network interface to bind to the offered address + */ +static void +dhcp_bind(struct netif *netif) +{ + u32_t timeout; + struct dhcp *dhcp; + ip4_addr_t sn_mask, gw_addr; + LWIP_ERROR("dhcp_bind: netif != NULL", (netif != NULL), return;); + dhcp = netif_dhcp_data(netif); + LWIP_ERROR("dhcp_bind: dhcp != NULL", (dhcp != NULL), return;); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + /* reset time used of lease */ + dhcp->lease_used = 0; + + if (dhcp->offered_t0_lease != 0xffffffffUL) { + /* set renewal period timer */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t0 renewal timer %"U32_F" secs\n", dhcp->offered_t0_lease)); + timeout = (dhcp->offered_t0_lease + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (timeout > 0xffff) { + timeout = 0xffff; + } + dhcp->t0_timeout = (u16_t)timeout; + if (dhcp->t0_timeout == 0) { + dhcp->t0_timeout = 1; + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t0_lease * 1000)); + } + + /* temporary DHCP lease? */ + if (dhcp->offered_t1_renew != 0xffffffffUL) { + /* set renewal period timer */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t1 renewal timer %"U32_F" secs\n", dhcp->offered_t1_renew)); + timeout = (dhcp->offered_t1_renew + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (timeout > 0xffff) { + timeout = 0xffff; + } + dhcp->t1_timeout = (u16_t)timeout; + if (dhcp->t1_timeout == 0) { + dhcp->t1_timeout = 1; + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t1_renew * 1000)); + dhcp->t1_renew_time = dhcp->t1_timeout; + } + /* set renewal period timer */ + if (dhcp->offered_t2_rebind != 0xffffffffUL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_bind(): t2 rebind timer %"U32_F" secs\n", dhcp->offered_t2_rebind)); + timeout = (dhcp->offered_t2_rebind + DHCP_COARSE_TIMER_SECS / 2) / DHCP_COARSE_TIMER_SECS; + if (timeout > 0xffff) { + timeout = 0xffff; + } + dhcp->t2_timeout = (u16_t)timeout; + if (dhcp->t2_timeout == 0) { + dhcp->t2_timeout = 1; + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_bind(): set request timeout %"U32_F" msecs\n", dhcp->offered_t2_rebind * 1000)); + dhcp->t2_rebind_time = dhcp->t2_timeout; + } + + /* If we have sub 1 minute lease, t2 and t1 will kick in at the same time. */ + if ((dhcp->t1_timeout >= dhcp->t2_timeout) && (dhcp->t2_timeout > 0)) { + dhcp->t1_timeout = 0; + } + + if (dhcp->subnet_mask_given) { + /* copy offered network mask */ + ip4_addr_copy(sn_mask, dhcp->offered_sn_mask); + } else { + /* subnet mask not given, choose a safe subnet mask given the network class */ + u8_t first_octet = ip4_addr1(&dhcp->offered_ip_addr); + if (first_octet <= 127) { + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xff000000UL)); + } else if (first_octet >= 192) { + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffffff00UL)); + } else { + ip4_addr_set_u32(&sn_mask, PP_HTONL(0xffff0000UL)); + } + } + + ip4_addr_copy(gw_addr, dhcp->offered_gw_addr); + /* gateway address not given? */ + if (ip4_addr_isany_val(gw_addr)) { + /* copy network address */ + ip4_addr_get_network(&gw_addr, &dhcp->offered_ip_addr, &sn_mask); + /* use first host address on network as gateway */ + ip4_addr_set_u32(&gw_addr, ip4_addr_get_u32(&gw_addr) | PP_HTONL(0x00000001UL)); + } + +#if LWIP_DHCP_AUTOIP_COOP + if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_STATE, ("dhcp_bind(): IP: 0x%08"X32_F" SN: 0x%08"X32_F" GW: 0x%08"X32_F"\n", + ip4_addr_get_u32(&dhcp->offered_ip_addr), ip4_addr_get_u32(&sn_mask), ip4_addr_get_u32(&gw_addr))); + /* netif is now bound to DHCP leased address - set this before assigning the address + to ensure the callback can use dhcp_supplied_address() */ + dhcp_set_state(dhcp, DHCP_STATE_BOUND); + + netif_set_addr(netif, &dhcp->offered_ip_addr, &sn_mask, &gw_addr); + /* interface is used by routing now that an address is set */ +} + +/** + * @ingroup dhcp4 + * Renew an existing DHCP lease at the involved DHCP server. + * + * @param netif network interface which must renew its lease + */ +err_t +dhcp_renew(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + err_t result; + u16_t msecs; + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_renew()\n")); + dhcp_set_state(dhcp, DHCP_STATE_RENEWING); + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + } + +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_RENEWING, msg_out, DHCP_REQUEST, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + result = udp_sendto_if(dhcp_pcb, p_out, &dhcp->server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif); + pbuf_free(p_out); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew: RENEWING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_renew: could not allocate DHCP request\n")); + result = ERR_MEM; + } + if (dhcp->tries < 255) { + dhcp->tries++; + } + /* back-off on retries, but to a maximum of 20 seconds */ + msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 2000 : 20 * 1000); + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_renew(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Rebind with a DHCP server for an existing DHCP lease. + * + * @param netif network interface which must rebind with a DHCP server + */ +static err_t +dhcp_rebind(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + err_t result; + u16_t msecs; + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind()\n")); + dhcp_set_state(dhcp, DHCP_STATE_REBINDING); + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN(netif)); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + } + +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBINDING, msg_out, DHCP_DISCOVER, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + /* broadcast to server */ + result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif); + pbuf_free(p_out); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind: REBINDING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_rebind: could not allocate DHCP request\n")); + result = ERR_MEM; + } + if (dhcp->tries < 255) { + dhcp->tries++; + } + msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000); + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_rebind(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * Enter REBOOTING state to verify an existing lease + * + * @param netif network interface which must reboot + */ +static err_t +dhcp_reboot(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + err_t result; + u16_t msecs; + u8_t i; + struct pbuf *p_out; + u16_t options_out_len; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot()\n")); + dhcp_set_state(dhcp, DHCP_STATE_REBOOTING); + + /* create and initialize the DHCP message header */ + p_out = dhcp_create_msg(netif, dhcp, DHCP_REQUEST, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_MAX_MSG_SIZE, DHCP_OPTION_MAX_MSG_SIZE_LEN); + options_out_len = dhcp_option_short(options_out_len, msg_out->options, DHCP_MAX_MSG_LEN_MIN_REQUIRED); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_REQUESTED_IP, 4); + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(&dhcp->offered_ip_addr))); + + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_PARAMETER_REQUEST_LIST, LWIP_ARRAYSIZE(dhcp_discover_request_options)); + for (i = 0; i < LWIP_ARRAYSIZE(dhcp_discover_request_options); i++) { + options_out_len = dhcp_option_byte(options_out_len, msg_out->options, dhcp_discover_request_options[i]); + } + +#if LWIP_NETIF_HOSTNAME + options_out_len = dhcp_option_hostname(options_out_len, msg_out->options, netif); +#endif /* LWIP_NETIF_HOSTNAME */ + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, DHCP_STATE_REBOOTING, msg_out, DHCP_REQUEST, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + /* broadcast to server */ + result = udp_sendto_if(dhcp_pcb, p_out, IP_ADDR_BROADCAST, LWIP_IANA_PORT_DHCP_SERVER, netif); + pbuf_free(p_out); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot: REBOOTING\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_reboot: could not allocate DHCP request\n")); + result = ERR_MEM; + } + if (dhcp->tries < 255) { + dhcp->tries++; + } + msecs = (u16_t)(dhcp->tries < 10 ? dhcp->tries * 1000 : 10 * 1000); + dhcp->request_timeout = (u16_t)((msecs + DHCP_FINE_TIMER_MSECS - 1) / DHCP_FINE_TIMER_MSECS); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_reboot(): set request timeout %"U16_F" msecs\n", msecs)); + return result; +} + +/** + * @ingroup dhcp4 + * Release a DHCP lease and stop DHCP statemachine (and AUTOIP if LWIP_DHCP_AUTOIP_COOP). + * + * @param netif network interface + */ +void +dhcp_release_and_stop(struct netif *netif) +{ + struct dhcp *dhcp = netif_dhcp_data(netif); + ip_addr_t server_ip_addr; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_release_and_stop()\n")); + if (dhcp == NULL) { + return; + } + + /* already off? -> nothing to do */ + if (dhcp->state == DHCP_STATE_OFF) { + return; + } + + ip_addr_copy(server_ip_addr, dhcp->server_ip_addr); + + /* clean old DHCP offer */ + ip_addr_set_zero_ip4(&dhcp->server_ip_addr); + ip4_addr_set_zero(&dhcp->offered_ip_addr); + ip4_addr_set_zero(&dhcp->offered_sn_mask); + ip4_addr_set_zero(&dhcp->offered_gw_addr); +#if LWIP_DHCP_BOOTP_FILE + ip4_addr_set_zero(&dhcp->offered_si_addr); +#endif /* LWIP_DHCP_BOOTP_FILE */ + dhcp->offered_t0_lease = dhcp->offered_t1_renew = dhcp->offered_t2_rebind = 0; + dhcp->t1_renew_time = dhcp->t2_rebind_time = dhcp->lease_used = dhcp->t0_timeout = 0; + + /* send release message when current IP was assigned via DHCP */ + if (dhcp_supplied_address(netif)) { + /* create and initialize the DHCP message header */ + struct pbuf *p_out; + u16_t options_out_len; + p_out = dhcp_create_msg(netif, dhcp, DHCP_RELEASE, &options_out_len); + if (p_out != NULL) { + struct dhcp_msg *msg_out = (struct dhcp_msg *)p_out->payload; + options_out_len = dhcp_option(options_out_len, msg_out->options, DHCP_OPTION_SERVER_ID, 4); + options_out_len = dhcp_option_long(options_out_len, msg_out->options, lwip_ntohl(ip4_addr_get_u32(ip_2_ip4(&server_ip_addr)))); + + LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, dhcp->state, msg_out, DHCP_RELEASE, &options_out_len); + dhcp_option_trailer(options_out_len, msg_out->options, p_out); + + udp_sendto_if(dhcp_pcb, p_out, &server_ip_addr, LWIP_IANA_PORT_DHCP_SERVER, netif); + pbuf_free(p_out); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp_release: RELEASED, DHCP_STATE_OFF\n")); + } else { + /* sending release failed, but that's not a problem since the correct behaviour of dhcp does not rely on release */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp_release: could not allocate DHCP request\n")); + } + } + + /* remove IP address from interface (prevents routing from selecting this interface) */ + netif_set_addr(netif, IP4_ADDR_ANY4, IP4_ADDR_ANY4, IP4_ADDR_ANY4); + +#if LWIP_DHCP_AUTOIP_COOP + if (dhcp->autoip_coop_state == DHCP_AUTOIP_COOP_STATE_ON) { + autoip_stop(netif); + dhcp->autoip_coop_state = DHCP_AUTOIP_COOP_STATE_OFF; + } +#endif /* LWIP_DHCP_AUTOIP_COOP */ + + dhcp_set_state(dhcp, DHCP_STATE_OFF); + + if (dhcp->pcb_allocated != 0) { + dhcp_dec_pcb_refcount(); /* free DHCP PCB if not needed any more */ + dhcp->pcb_allocated = 0; + } +} + +/** + * @ingroup dhcp4 + * This function calls dhcp_release_and_stop() internally. + * @deprecated Use dhcp_release_and_stop() instead. + */ +err_t +dhcp_release(struct netif *netif) +{ + dhcp_release_and_stop(netif); + return ERR_OK; +} + +/** + * @ingroup dhcp4 + * This function calls dhcp_release_and_stop() internally. + * @deprecated Use dhcp_release_and_stop() instead. + */ +void +dhcp_stop(struct netif *netif) +{ + dhcp_release_and_stop(netif); +} + +/* + * Set the DHCP state of a DHCP client. + * + * If the state changed, reset the number of tries. + */ +static void +dhcp_set_state(struct dhcp *dhcp, u8_t new_state) +{ + if (new_state != dhcp->state) { + dhcp->state = new_state; + dhcp->tries = 0; + dhcp->request_timeout = 0; + } +} + +/* + * Concatenate an option type and length field to the outgoing + * DHCP message. + * + */ +static u16_t +dhcp_option(u16_t options_out_len, u8_t *options, u8_t option_type, u8_t option_len) +{ + LWIP_ASSERT("dhcp_option: options_out_len + 2 + option_len <= DHCP_OPTIONS_LEN", options_out_len + 2U + option_len <= DHCP_OPTIONS_LEN); + options[options_out_len++] = option_type; + options[options_out_len++] = option_len; + return options_out_len; +} +/* + * Concatenate a single byte to the outgoing DHCP message. + * + */ +static u16_t +dhcp_option_byte(u16_t options_out_len, u8_t *options, u8_t value) +{ + LWIP_ASSERT("dhcp_option_byte: options_out_len < DHCP_OPTIONS_LEN", options_out_len < DHCP_OPTIONS_LEN); + options[options_out_len++] = value; + return options_out_len; +} + +static u16_t +dhcp_option_short(u16_t options_out_len, u8_t *options, u16_t value) +{ + LWIP_ASSERT("dhcp_option_short: options_out_len + 2 <= DHCP_OPTIONS_LEN", options_out_len + 2U <= DHCP_OPTIONS_LEN); + options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8); + options[options_out_len++] = (u8_t) (value & 0x00ffU); + return options_out_len; +} + +static u16_t +dhcp_option_long(u16_t options_out_len, u8_t *options, u32_t value) +{ + LWIP_ASSERT("dhcp_option_long: options_out_len + 4 <= DHCP_OPTIONS_LEN", options_out_len + 4U <= DHCP_OPTIONS_LEN); + options[options_out_len++] = (u8_t)((value & 0xff000000UL) >> 24); + options[options_out_len++] = (u8_t)((value & 0x00ff0000UL) >> 16); + options[options_out_len++] = (u8_t)((value & 0x0000ff00UL) >> 8); + options[options_out_len++] = (u8_t)((value & 0x000000ffUL)); + return options_out_len; +} + +#if LWIP_NETIF_HOSTNAME +static u16_t +dhcp_option_hostname(u16_t options_out_len, u8_t *options, struct netif *netif) +{ + if (netif->hostname != NULL) { + size_t namelen = strlen(netif->hostname); + if (namelen > 0) { + size_t len; + const char *p = netif->hostname; + /* Shrink len to available bytes (need 2 bytes for OPTION_HOSTNAME + and 1 byte for trailer) */ + size_t available = DHCP_OPTIONS_LEN - options_out_len - 3; + LWIP_ASSERT("DHCP: hostname is too long!", namelen <= available); + len = LWIP_MIN(namelen, available); + LWIP_ASSERT("DHCP: hostname is too long!", len <= 0xFF); + options_out_len = dhcp_option(options_out_len, options, DHCP_OPTION_HOSTNAME, (u8_t)len); + while (len--) { + options_out_len = dhcp_option_byte(options_out_len, options, *p++); + } + } + } + return options_out_len; +} +#endif /* LWIP_NETIF_HOSTNAME */ + +/** + * Extract the DHCP message and the DHCP options. + * + * Extract the DHCP message and the DHCP options, each into a contiguous + * piece of memory. As a DHCP message is variable sized by its options, + * and also allows overriding some fields for options, the easy approach + * is to first unfold the options into a contiguous piece of memory, and + * use that further on. + * + */ +static err_t +dhcp_parse_reply(struct pbuf *p, struct dhcp *dhcp) +{ + u8_t *options; + u16_t offset; + u16_t offset_max; + u16_t options_idx; + u16_t options_idx_max; + struct pbuf *q; + int parse_file_as_options = 0; + int parse_sname_as_options = 0; + struct dhcp_msg *msg_in; +#if LWIP_DHCP_BOOTP_FILE + int file_overloaded = 0; +#endif + + LWIP_UNUSED_ARG(dhcp); + + /* clear received options */ + dhcp_clear_all_options(dhcp); + /* check that beginning of dhcp_msg (up to and including chaddr) is in first pbuf */ + if (p->len < DHCP_SNAME_OFS) { + return ERR_BUF; + } + msg_in = (struct dhcp_msg *)p->payload; +#if LWIP_DHCP_BOOTP_FILE + /* clear boot file name */ + dhcp->boot_file_name[0] = 0; +#endif /* LWIP_DHCP_BOOTP_FILE */ + + /* parse options */ + + /* start with options field */ + options_idx = DHCP_OPTIONS_OFS; + /* parse options to the end of the received packet */ + options_idx_max = p->tot_len; +again: + q = p; + while ((q != NULL) && (options_idx >= q->len)) { + options_idx = (u16_t)(options_idx - q->len); + options_idx_max = (u16_t)(options_idx_max - q->len); + q = q->next; + } + if (q == NULL) { + return ERR_BUF; + } + offset = options_idx; + offset_max = options_idx_max; + options = (u8_t *)q->payload; + /* at least 1 byte to read and no end marker, then at least 3 bytes to read? */ + while ((q != NULL) && (offset < offset_max) && (options[offset] != DHCP_OPTION_END)) { + u8_t op = options[offset]; + u8_t len; + u8_t decode_len = 0; + int decode_idx = -1; + u16_t val_offset = (u16_t)(offset + 2); + if (val_offset < offset) { + /* overflow */ + return ERR_BUF; + } + /* len byte might be in the next pbuf */ + if ((offset + 1) < q->len) { + len = options[offset + 1]; + } else { + len = (q->next != NULL ? ((u8_t *)q->next->payload)[0] : 0); + } + /* LWIP_DEBUGF(DHCP_DEBUG, ("msg_offset=%"U16_F", q->len=%"U16_F, msg_offset, q->len)); */ + decode_len = len; + switch (op) { + /* case(DHCP_OPTION_END): handled above */ + case (DHCP_OPTION_PAD): + /* special option: no len encoded */ + decode_len = len = 0; + /* will be increased below */ + break; + case (DHCP_OPTION_SUBNET_MASK): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_SUBNET_MASK; + break; + case (DHCP_OPTION_ROUTER): + decode_len = 4; /* only copy the first given router */ + LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_ROUTER; + break; +#if LWIP_DHCP_PROVIDE_DNS_SERVERS + case (DHCP_OPTION_DNS_SERVER): + /* special case: there might be more than one server */ + LWIP_ERROR("len %% 4 == 0", len % 4 == 0, return ERR_VAL;); + /* limit number of DNS servers */ + decode_len = LWIP_MIN(len, 4 * DNS_MAX_SERVERS); + LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_DNS_SERVER; + break; +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ + case (DHCP_OPTION_LEASE_TIME): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_LEASE_TIME; + break; +#if LWIP_DHCP_GET_NTP_SRV + case (DHCP_OPTION_NTP): + /* special case: there might be more than one server */ + LWIP_ERROR("len %% 4 == 0", len % 4 == 0, return ERR_VAL;); + /* limit number of NTP servers */ + decode_len = LWIP_MIN(len, 4 * LWIP_DHCP_MAX_NTP_SERVERS); + LWIP_ERROR("len >= decode_len", len >= decode_len, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_NTP_SERVER; + break; +#endif /* LWIP_DHCP_GET_NTP_SRV*/ + case (DHCP_OPTION_OVERLOAD): + LWIP_ERROR("len == 1", len == 1, return ERR_VAL;); + /* decode overload only in options, not in file/sname: invalid packet */ + LWIP_ERROR("overload in file/sname", options_idx == DHCP_OPTIONS_OFS, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_OVERLOAD; + break; + case (DHCP_OPTION_MESSAGE_TYPE): + LWIP_ERROR("len == 1", len == 1, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_MSG_TYPE; + break; + case (DHCP_OPTION_SERVER_ID): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_SERVER_ID; + break; + case (DHCP_OPTION_T1): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_T1; + break; + case (DHCP_OPTION_T2): + LWIP_ERROR("len == 4", len == 4, return ERR_VAL;); + decode_idx = DHCP_OPTION_IDX_T2; + break; + default: + decode_len = 0; + LWIP_DEBUGF(DHCP_DEBUG, ("skipping option %"U16_F" in options\n", (u16_t)op)); + LWIP_HOOK_DHCP_PARSE_OPTION(ip_current_netif(), dhcp, dhcp->state, msg_in, + dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) ? (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) : 0, + op, len, q, val_offset); + break; + } + if (op == DHCP_OPTION_PAD) { + offset++; + } else { + if (offset + len + 2 > 0xFFFF) { + /* overflow */ + return ERR_BUF; + } + offset = (u16_t)(offset + len + 2); + if (decode_len > 0) { + u32_t value = 0; + u16_t copy_len; +decode_next: + LWIP_ASSERT("check decode_idx", decode_idx >= 0 && decode_idx < DHCP_OPTION_IDX_MAX); + if (!dhcp_option_given(dhcp, decode_idx)) { + copy_len = LWIP_MIN(decode_len, 4); + if (pbuf_copy_partial(q, &value, copy_len, val_offset) != copy_len) { + return ERR_BUF; + } + if (decode_len > 4) { + /* decode more than one u32_t */ + u16_t next_val_offset; + LWIP_ERROR("decode_len %% 4 == 0", decode_len % 4 == 0, return ERR_VAL;); + dhcp_got_option(dhcp, decode_idx); + dhcp_set_option_value(dhcp, decode_idx, lwip_htonl(value)); + decode_len = (u8_t)(decode_len - 4); + next_val_offset = (u16_t)(val_offset + 4); + if (next_val_offset < val_offset) { + /* overflow */ + return ERR_BUF; + } + val_offset = next_val_offset; + decode_idx++; + goto decode_next; + } else if (decode_len == 4) { + value = lwip_ntohl(value); + } else { + LWIP_ERROR("invalid decode_len", decode_len == 1, return ERR_VAL;); + value = ((u8_t *)&value)[0]; + } + dhcp_got_option(dhcp, decode_idx); + dhcp_set_option_value(dhcp, decode_idx, value); + } + } + } + if (offset >= q->len) { + offset = (u16_t)(offset - q->len); + offset_max = (u16_t)(offset_max - q->len); + if (offset < offset_max) { + q = q->next; + LWIP_ERROR("next pbuf was null", q != NULL, return ERR_VAL;); + options = (u8_t *)q->payload; + } else { + /* We've run out of bytes, probably no end marker. Don't proceed. */ + return ERR_BUF; + } + } + } + /* is this an overloaded message? */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_OVERLOAD)) { + u32_t overload = dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_OVERLOAD); + dhcp_clear_option(dhcp, DHCP_OPTION_IDX_OVERLOAD); + if (overload == DHCP_OVERLOAD_FILE) { + parse_file_as_options = 1; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded file field\n")); + } else if (overload == DHCP_OVERLOAD_SNAME) { + parse_sname_as_options = 1; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname field\n")); + } else if (overload == DHCP_OVERLOAD_SNAME_FILE) { + parse_sname_as_options = 1; + parse_file_as_options = 1; + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("overloaded sname and file field\n")); + } else { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("invalid overload option: %d\n", (int)overload)); + } + } + if (parse_file_as_options) { + /* if both are overloaded, parse file first and then sname (RFC 2131 ch. 4.1) */ + parse_file_as_options = 0; + options_idx = DHCP_FILE_OFS; + options_idx_max = DHCP_FILE_OFS + DHCP_FILE_LEN; +#if LWIP_DHCP_BOOTP_FILE + file_overloaded = 1; +#endif + goto again; + } else if (parse_sname_as_options) { + parse_sname_as_options = 0; + options_idx = DHCP_SNAME_OFS; + options_idx_max = DHCP_SNAME_OFS + DHCP_SNAME_LEN; + goto again; + } +#if LWIP_DHCP_BOOTP_FILE + if (!file_overloaded) { + /* only do this for ACK messages */ + if (dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE) && + (dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE) == DHCP_ACK)) + /* copy bootp file name, don't care for sname (server hostname) */ + if (pbuf_copy_partial(p, dhcp->boot_file_name, DHCP_FILE_LEN-1, DHCP_FILE_OFS) != (DHCP_FILE_LEN-1)) { + return ERR_BUF; + } + /* make sure the string is really NULL-terminated */ + dhcp->boot_file_name[DHCP_FILE_LEN-1] = 0; + } +#endif /* LWIP_DHCP_BOOTP_FILE */ + return ERR_OK; +} + +/** + * If an incoming DHCP message is in response to us, then trigger the state machine + */ +static void +dhcp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) +{ + struct netif *netif = ip_current_input_netif(); + struct dhcp *dhcp = netif_dhcp_data(netif); + struct dhcp_msg *reply_msg = (struct dhcp_msg *)p->payload; + u8_t msg_type; + u8_t i; + struct dhcp_msg *msg_in; + + LWIP_UNUSED_ARG(arg); + + /* Caught DHCP message from netif that does not have DHCP enabled? -> not interested */ + if ((dhcp == NULL) || (dhcp->pcb_allocated == 0)) { + goto free_pbuf_and_return; + } + + LWIP_ASSERT("invalid server address type", IP_IS_V4(addr)); + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp_recv(pbuf = %p) from DHCP server %"U16_F".%"U16_F".%"U16_F".%"U16_F" port %"U16_F"\n", (void *)p, + ip4_addr1_16(ip_2_ip4(addr)), ip4_addr2_16(ip_2_ip4(addr)), ip4_addr3_16(ip_2_ip4(addr)), ip4_addr4_16(ip_2_ip4(addr)), port)); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); + /* prevent warnings about unused arguments */ + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(addr); + LWIP_UNUSED_ARG(port); + + if (p->len < DHCP_MIN_REPLY_LEN) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP reply message or pbuf too short\n")); + goto free_pbuf_and_return; + } + + if (reply_msg->op != DHCP_BOOTREPLY) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("not a DHCP reply message, but type %"U16_F"\n", (u16_t)reply_msg->op)); + goto free_pbuf_and_return; + } + /* iterate through hardware address and match against DHCP message */ + for (i = 0; i < netif->hwaddr_len && i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) { + if (netif->hwaddr[i] != reply_msg->chaddr[i]) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("netif->hwaddr[%"U16_F"]==%02"X16_F" != reply_msg->chaddr[%"U16_F"]==%02"X16_F"\n", + (u16_t)i, (u16_t)netif->hwaddr[i], (u16_t)i, (u16_t)reply_msg->chaddr[i])); + goto free_pbuf_and_return; + } + } + /* match transaction ID against what we expected */ + if (lwip_ntohl(reply_msg->xid) != dhcp->xid) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("transaction id mismatch reply_msg->xid(%"X32_F")!=dhcp->xid(%"X32_F")\n", lwip_ntohl(reply_msg->xid), dhcp->xid)); + goto free_pbuf_and_return; + } + /* option fields could be unfold? */ + if (dhcp_parse_reply(p, dhcp) != ERR_OK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("problem unfolding DHCP message - too short on memory?\n")); + goto free_pbuf_and_return; + } + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("searching DHCP_OPTION_MESSAGE_TYPE\n")); + /* obtain pointer to DHCP message type */ + if (!dhcp_option_given(dhcp, DHCP_OPTION_IDX_MSG_TYPE)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCP_OPTION_MESSAGE_TYPE option not found\n")); + goto free_pbuf_and_return; + } + + msg_in = (struct dhcp_msg *)p->payload; + /* read DHCP message type */ + msg_type = (u8_t)dhcp_get_option_value(dhcp, DHCP_OPTION_IDX_MSG_TYPE); + /* message type is DHCP ACK? */ + if (msg_type == DHCP_ACK) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_ACK received\n")); + /* in requesting state? */ + if (dhcp->state == DHCP_STATE_REQUESTING) { + dhcp_handle_ack(netif, msg_in); +#if DHCP_DOES_ARP_CHECK + if ((netif->flags & NETIF_FLAG_ETHARP) != 0) { + /* check if the acknowledged lease address is already in use */ + dhcp_check(netif); + } else { + /* bind interface to the acknowledged lease address */ + dhcp_bind(netif); + } +#else + /* bind interface to the acknowledged lease address */ + dhcp_bind(netif); +#endif + } + /* already bound to the given lease address? */ + else if ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REBINDING) || + (dhcp->state == DHCP_STATE_RENEWING)) { + dhcp_handle_ack(netif, msg_in); + dhcp_bind(netif); + } + } + /* received a DHCP_NAK in appropriate state? */ + else if ((msg_type == DHCP_NAK) && + ((dhcp->state == DHCP_STATE_REBOOTING) || (dhcp->state == DHCP_STATE_REQUESTING) || + (dhcp->state == DHCP_STATE_REBINDING) || (dhcp->state == DHCP_STATE_RENEWING ))) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_NAK received\n")); + dhcp_handle_nak(netif); + } + /* received a DHCP_OFFER in DHCP_STATE_SELECTING state? */ + else if ((msg_type == DHCP_OFFER) && (dhcp->state == DHCP_STATE_SELECTING)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("DHCP_OFFER received in DHCP_STATE_SELECTING state\n")); + /* remember offered lease */ + dhcp_handle_offer(netif, msg_in); + } + +free_pbuf_and_return: + pbuf_free(p); +} + +/** + * Create a DHCP request, fill in common headers + * + * @param netif the netif under DHCP control + * @param dhcp dhcp control struct + * @param message_type message type of the request + */ +static struct pbuf * +dhcp_create_msg(struct netif *netif, struct dhcp *dhcp, u8_t message_type, u16_t *options_out_len) +{ + u16_t i; + struct pbuf *p_out; + struct dhcp_msg *msg_out; + u16_t options_out_len_loc; + +#ifndef DHCP_GLOBAL_XID + /** default global transaction identifier starting value (easy to match + * with a packet analyser). We simply increment for each new request. + * Predefine DHCP_GLOBAL_XID to a better value or a function call to generate one + * at runtime, any supporting function prototypes can be defined in DHCP_GLOBAL_XID_HEADER */ +#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND) + static u32_t xid; +#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ + static u32_t xid = 0xABCD0000; +#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ +#else + if (!xid_initialised) { + xid = DHCP_GLOBAL_XID; + xid_initialised = !xid_initialised; + } +#endif + LWIP_ERROR("dhcp_create_msg: netif != NULL", (netif != NULL), return NULL;); + LWIP_ERROR("dhcp_create_msg: dhcp != NULL", (dhcp != NULL), return NULL;); + p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp_msg), PBUF_RAM); + if (p_out == NULL) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp_create_msg(): could not allocate pbuf\n")); + return NULL; + } + LWIP_ASSERT("dhcp_create_msg: check that first pbuf can hold struct dhcp_msg", + (p_out->len >= sizeof(struct dhcp_msg))); + + /* DHCP_REQUEST should reuse 'xid' from DHCPOFFER */ + if ((message_type != DHCP_REQUEST) || (dhcp->state == DHCP_STATE_REBOOTING)) { + /* reuse transaction identifier in retransmissions */ + if (dhcp->tries == 0) { +#if DHCP_CREATE_RAND_XID && defined(LWIP_RAND) + xid = LWIP_RAND(); +#else /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ + xid++; +#endif /* DHCP_CREATE_RAND_XID && defined(LWIP_RAND) */ + } + dhcp->xid = xid; + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, + ("transaction id xid(%"X32_F")\n", xid)); + + msg_out = (struct dhcp_msg *)p_out->payload; + memset(msg_out, 0, sizeof(struct dhcp_msg)); + + msg_out->op = DHCP_BOOTREQUEST; + /* @todo: make link layer independent */ + msg_out->htype = LWIP_IANA_HWTYPE_ETHERNET; + msg_out->hlen = netif->hwaddr_len; + msg_out->xid = lwip_htonl(dhcp->xid); + /* we don't need the broadcast flag since we can receive unicast traffic + before being fully configured! */ + /* set ciaddr to netif->ip_addr based on message_type and state */ + if ((message_type == DHCP_INFORM) || (message_type == DHCP_DECLINE) || (message_type == DHCP_RELEASE) || + ((message_type == DHCP_REQUEST) && /* DHCP_STATE_BOUND not used for sending! */ + ((dhcp->state == DHCP_STATE_RENEWING) || dhcp->state == DHCP_STATE_REBINDING))) { + ip4_addr_copy(msg_out->ciaddr, *netif_ip4_addr(netif)); + } + for (i = 0; i < LWIP_MIN(DHCP_CHADDR_LEN, NETIF_MAX_HWADDR_LEN); i++) { + /* copy netif hardware address (padded with zeroes through memset already) */ + msg_out->chaddr[i] = netif->hwaddr[i]; + } + msg_out->cookie = PP_HTONL(DHCP_MAGIC_COOKIE); + /* Add option MESSAGE_TYPE */ + options_out_len_loc = dhcp_option(0, msg_out->options, DHCP_OPTION_MESSAGE_TYPE, DHCP_OPTION_MESSAGE_TYPE_LEN); + options_out_len_loc = dhcp_option_byte(options_out_len_loc, msg_out->options, message_type); + if (options_out_len) { + *options_out_len = options_out_len_loc; + } + return p_out; +} + +/** + * Add a DHCP message trailer + * + * Adds the END option to the DHCP message, and if + * necessary, up to three padding bytes. + */ +static void +dhcp_option_trailer(u16_t options_out_len, u8_t *options, struct pbuf *p_out) +{ + options[options_out_len++] = DHCP_OPTION_END; + /* packet is too small, or not 4 byte aligned? */ + while (((options_out_len < DHCP_MIN_OPTIONS_LEN) || (options_out_len & 3)) && + (options_out_len < DHCP_OPTIONS_LEN)) { + /* add a fill/padding byte */ + options[options_out_len++] = 0; + } + /* shrink the pbuf to the actual content length */ + pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp_msg) - DHCP_OPTIONS_LEN + options_out_len)); +} + +/** check if DHCP supplied netif->ip_addr + * + * @param netif the netif to check + * @return 1 if DHCP supplied netif->ip_addr (states BOUND or RENEWING), + * 0 otherwise + */ +u8_t +dhcp_supplied_address(const struct netif *netif) +{ + if ((netif != NULL) && (netif_dhcp_data(netif) != NULL)) { + struct dhcp *dhcp = netif_dhcp_data(netif); + return (dhcp->state == DHCP_STATE_BOUND) || (dhcp->state == DHCP_STATE_RENEWING) || + (dhcp->state == DHCP_STATE_REBINDING); + } + return 0; +} + +#endif /* LWIP_IPV4 && LWIP_DHCP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c new file mode 100644 index 0000000..442aac0 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/etharp.c @@ -0,0 +1,1204 @@ +/** + * @file + * Address Resolution Protocol module for IP over Ethernet + * + * Functionally, ARP is divided into two parts. The first maps an IP address + * to a physical address when sending a packet, and the second part answers + * requests from other machines for our physical address. + * + * This implementation complies with RFC 826 (Ethernet ARP). It supports + * Gratuitious ARP from RFC3220 (IP Mobility Support for IPv4) section 4.6 + * if an interface calls etharp_gratuitous(our_netif) upon address change. + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/etharp.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "lwip/prot/iana.h" +#include "netif/ethernet.h" + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +/** Re-request a used ARP entry 1 minute before it would expire to prevent + * breaking a steadily used connection because the ARP entry timed out. */ +#define ARP_AGE_REREQUEST_USED_UNICAST (ARP_MAXAGE - 30) +#define ARP_AGE_REREQUEST_USED_BROADCAST (ARP_MAXAGE - 15) + +/** the time an ARP entry stays pending after first request, + * for ARP_TMR_INTERVAL = 1000, this is + * 10 seconds. + * + * @internal Keep this number at least 2, otherwise it might + * run out instantly if the timeout occurs directly after a request. + */ +#define ARP_MAXPENDING 5 + +/** ARP states */ +enum etharp_state { + ETHARP_STATE_EMPTY = 0, + ETHARP_STATE_PENDING, + ETHARP_STATE_STABLE, + ETHARP_STATE_STABLE_REREQUESTING_1, + ETHARP_STATE_STABLE_REREQUESTING_2 +#if ETHARP_SUPPORT_STATIC_ENTRIES + , ETHARP_STATE_STATIC +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ +}; + +struct etharp_entry { +#if ARP_QUEUEING + /** Pointer to queue of pending outgoing packets on this ARP entry. */ + struct etharp_q_entry *q; +#else /* ARP_QUEUEING */ + /** Pointer to a single pending outgoing packet on this ARP entry. */ + struct pbuf *q; +#endif /* ARP_QUEUEING */ + ip4_addr_t ipaddr; + struct netif *netif; + struct eth_addr ethaddr; + u16_t ctime; + u8_t state; +}; + +static struct etharp_entry arp_table[ARP_TABLE_SIZE]; + +#if !LWIP_NETIF_HWADDRHINT +static netif_addr_idx_t etharp_cached_entry; +#endif /* !LWIP_NETIF_HWADDRHINT */ + +/** Try hard to create a new entry - we want the IP address to appear in + the cache (even if this means removing an active entry or so). */ +#define ETHARP_FLAG_TRY_HARD 1 +#define ETHARP_FLAG_FIND_ONLY 2 +#if ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_FLAG_STATIC_ENTRY 4 +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + +#if LWIP_NETIF_HWADDRHINT +#define ETHARP_SET_ADDRHINT(netif, addrhint) do { if (((netif) != NULL) && ((netif)->hints != NULL)) { \ + (netif)->hints->addr_hint = (addrhint); }} while(0) +#else /* LWIP_NETIF_HWADDRHINT */ +#define ETHARP_SET_ADDRHINT(netif, addrhint) (etharp_cached_entry = (addrhint)) +#endif /* LWIP_NETIF_HWADDRHINT */ + + +/* Check for maximum ARP_TABLE_SIZE */ +#if (ARP_TABLE_SIZE > NETIF_ADDR_IDX_MAX) +#error "ARP_TABLE_SIZE must fit in an s16_t, you have to reduce it in your lwipopts.h" +#endif + + +static err_t etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr); +static err_t etharp_raw(struct netif *netif, + const struct eth_addr *ethsrc_addr, const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr, + const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr, + const u16_t opcode); + +#if ARP_QUEUEING +/** + * Free a complete queue of etharp entries + * + * @param q a qeueue of etharp_q_entry's to free + */ +static void +free_etharp_q(struct etharp_q_entry *q) +{ + struct etharp_q_entry *r; + LWIP_ASSERT("q != NULL", q != NULL); + while (q) { + r = q; + q = q->next; + LWIP_ASSERT("r->p != NULL", (r->p != NULL)); + pbuf_free(r->p); + memp_free(MEMP_ARP_QUEUE, r); + } +} +#else /* ARP_QUEUEING */ + +/** Compatibility define: free the queued pbuf */ +#define free_etharp_q(q) pbuf_free(q) + +#endif /* ARP_QUEUEING */ + +/** Clean up ARP table entries */ +static void +etharp_free_entry(int i) +{ + /* remove from SNMP ARP index tree */ + mib2_remove_arp_entry(arp_table[i].netif, &arp_table[i].ipaddr); + /* and empty packet queue */ + if (arp_table[i].q != NULL) { + /* remove all queued packets */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_free_entry: freeing entry %"U16_F", packet queue %p.\n", (u16_t)i, (void *)(arp_table[i].q))); + free_etharp_q(arp_table[i].q); + arp_table[i].q = NULL; + } + /* recycle entry for re-use */ + arp_table[i].state = ETHARP_STATE_EMPTY; +#ifdef LWIP_DEBUG + /* for debugging, clean out the complete entry */ + arp_table[i].ctime = 0; + arp_table[i].netif = NULL; + ip4_addr_set_zero(&arp_table[i].ipaddr); + arp_table[i].ethaddr = ethzero; +#endif /* LWIP_DEBUG */ +} + +/** + * Clears expired entries in the ARP table. + * + * This function should be called every ARP_TMR_INTERVAL milliseconds (1 second), + * in order to expire entries in the ARP table. + */ +void +etharp_tmr(void) +{ + int i; + + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer\n")); + /* remove expired entries from the ARP table */ + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + u8_t state = arp_table[i].state; + if (state != ETHARP_STATE_EMPTY +#if ETHARP_SUPPORT_STATIC_ENTRIES + && (state != ETHARP_STATE_STATIC) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + ) { + arp_table[i].ctime++; + if ((arp_table[i].ctime >= ARP_MAXAGE) || + ((arp_table[i].state == ETHARP_STATE_PENDING) && + (arp_table[i].ctime >= ARP_MAXPENDING))) { + /* pending or stable entry has become old! */ + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_timer: expired %s entry %d.\n", + arp_table[i].state >= ETHARP_STATE_STABLE ? "stable" : "pending", i)); + /* clean up entries that have just been expired */ + etharp_free_entry(i); + } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_1) { + /* Don't send more than one request every 2 seconds. */ + arp_table[i].state = ETHARP_STATE_STABLE_REREQUESTING_2; + } else if (arp_table[i].state == ETHARP_STATE_STABLE_REREQUESTING_2) { + /* Reset state to stable, so that the next transmitted packet will + re-send an ARP request. */ + arp_table[i].state = ETHARP_STATE_STABLE; + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* still pending, resend an ARP query */ + etharp_request(arp_table[i].netif, &arp_table[i].ipaddr); + } + } + } +} + +/** + * Search the ARP table for a matching or new entry. + * + * If an IP address is given, return a pending or stable ARP entry that matches + * the address. If no match is found, create a new entry with this address set, + * but in state ETHARP_EMPTY. The caller must check and possibly change the + * state of the returned entry. + * + * If ipaddr is NULL, return a initialized new entry in state ETHARP_EMPTY. + * + * In all cases, attempt to create new entries from an empty entry. If no + * empty entries are available and ETHARP_FLAG_TRY_HARD flag is set, recycle + * old entries. Heuristic choose the least important entry for recycling. + * + * @param ipaddr IP address to find in ARP cache, or to add if not found. + * @param flags See @ref etharp_state + * @param netif netif related to this address (used for NETIF_HWADDRHINT) + * + * @return The ARP entry index that matched or is created, ERR_MEM if no + * entry is found or could be recycled. + */ +static s16_t +etharp_find_entry(const ip4_addr_t *ipaddr, u8_t flags, struct netif *netif) +{ + s16_t old_pending = ARP_TABLE_SIZE, old_stable = ARP_TABLE_SIZE; + s16_t empty = ARP_TABLE_SIZE; + s16_t i = 0; + /* oldest entry with packets on queue */ + s16_t old_queue = ARP_TABLE_SIZE; + /* its age */ + u16_t age_queue = 0, age_pending = 0, age_stable = 0; + + LWIP_UNUSED_ARG(netif); + + /** + * a) do a search through the cache, remember candidates + * b) select candidate entry + * c) create new entry + */ + + /* a) in a single search sweep, do all of this + * 1) remember the first empty entry (if any) + * 2) remember the oldest stable entry (if any) + * 3) remember the oldest pending entry without queued packets (if any) + * 4) remember the oldest pending entry with queued packets (if any) + * 5) search for a matching IP entry, either pending or stable + * until 5 matches, or all entries are searched for. + */ + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + u8_t state = arp_table[i].state; + /* no empty entry found yet and now we do find one? */ + if ((empty == ARP_TABLE_SIZE) && (state == ETHARP_STATE_EMPTY)) { + LWIP_DEBUGF(ETHARP_DEBUG, ("etharp_find_entry: found empty entry %d\n", (int)i)); + /* remember first empty entry */ + empty = i; + } else if (state != ETHARP_STATE_EMPTY) { + LWIP_ASSERT("state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE", + state == ETHARP_STATE_PENDING || state >= ETHARP_STATE_STABLE); + /* if given, does IP address match IP address in ARP entry? */ + if (ipaddr && ip4_addr_cmp(ipaddr, &arp_table[i].ipaddr) +#if ETHARP_TABLE_MATCH_NETIF + && ((netif == NULL) || (netif == arp_table[i].netif)) +#endif /* ETHARP_TABLE_MATCH_NETIF */ + ) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: found matching entry %d\n", (int)i)); + /* found exact IP address match, simply bail out */ + return i; + } + /* pending entry? */ + if (state == ETHARP_STATE_PENDING) { + /* pending with queued packets? */ + if (arp_table[i].q != NULL) { + if (arp_table[i].ctime >= age_queue) { + old_queue = i; + age_queue = arp_table[i].ctime; + } + } else + /* pending without queued packets? */ + { + if (arp_table[i].ctime >= age_pending) { + old_pending = i; + age_pending = arp_table[i].ctime; + } + } + /* stable entry? */ + } else if (state >= ETHARP_STATE_STABLE) { +#if ETHARP_SUPPORT_STATIC_ENTRIES + /* don't record old_stable for static entries since they never expire */ + if (state < ETHARP_STATE_STATIC) +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + { + /* remember entry with oldest stable entry in oldest, its age in maxtime */ + if (arp_table[i].ctime >= age_stable) { + old_stable = i; + age_stable = arp_table[i].ctime; + } + } + } + } + } + /* { we have no match } => try to create a new entry */ + + /* don't create new entry, only search? */ + if (((flags & ETHARP_FLAG_FIND_ONLY) != 0) || + /* or no empty entry found and not allowed to recycle? */ + ((empty == ARP_TABLE_SIZE) && ((flags & ETHARP_FLAG_TRY_HARD) == 0))) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty entry found and not allowed to recycle\n")); + return (s16_t)ERR_MEM; + } + + /* b) choose the least destructive entry to recycle: + * 1) empty entry + * 2) oldest stable entry + * 3) oldest pending entry without queued packets + * 4) oldest pending entry with queued packets + * + * { ETHARP_FLAG_TRY_HARD is set at this point } + */ + + /* 1) empty entry available? */ + if (empty < ARP_TABLE_SIZE) { + i = empty; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting empty entry %d\n", (int)i)); + } else { + /* 2) found recyclable stable entry? */ + if (old_stable < ARP_TABLE_SIZE) { + /* recycle oldest stable*/ + i = old_stable; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest stable entry %d\n", (int)i)); + /* no queued packets should exist on stable entries */ + LWIP_ASSERT("arp_table[i].q == NULL", arp_table[i].q == NULL); + /* 3) found recyclable pending entry without queued packets? */ + } else if (old_pending < ARP_TABLE_SIZE) { + /* recycle oldest pending */ + i = old_pending; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d (without queue)\n", (int)i)); + /* 4) found recyclable pending entry with queued packets? */ + } else if (old_queue < ARP_TABLE_SIZE) { + /* recycle oldest pending (queued packets are free in etharp_free_entry) */ + i = old_queue; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: selecting oldest pending entry %d, freeing packet queue %p\n", (int)i, (void *)(arp_table[i].q))); + /* no empty or recyclable entries found */ + } else { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_find_entry: no empty or recyclable entries found\n")); + return (s16_t)ERR_MEM; + } + + /* { empty or recyclable entry found } */ + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + etharp_free_entry(i); + } + + LWIP_ASSERT("i < ARP_TABLE_SIZE", i < ARP_TABLE_SIZE); + LWIP_ASSERT("arp_table[i].state == ETHARP_STATE_EMPTY", + arp_table[i].state == ETHARP_STATE_EMPTY); + + /* IP address given? */ + if (ipaddr != NULL) { + /* set IP address */ + ip4_addr_copy(arp_table[i].ipaddr, *ipaddr); + } + arp_table[i].ctime = 0; +#if ETHARP_TABLE_MATCH_NETIF + arp_table[i].netif = netif; +#endif /* ETHARP_TABLE_MATCH_NETIF */ + return (s16_t)i; +} + +/** + * Update (or insert) a IP/MAC address pair in the ARP cache. + * + * If a pending entry is resolved, any queued packets will be sent + * at this point. + * + * @param netif netif related to this entry (used for NETIF_ADDRHINT) + * @param ipaddr IP address of the inserted ARP entry. + * @param ethaddr Ethernet address of the inserted ARP entry. + * @param flags See @ref etharp_state + * + * @return + * - ERR_OK Successfully updated ARP cache. + * - ERR_MEM If we could not add a new ARP entry when ETHARP_FLAG_TRY_HARD was set. + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + * @see pbuf_free() + */ +static err_t +etharp_update_arp_entry(struct netif *netif, const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, u8_t flags) +{ + s16_t i; + LWIP_ASSERT("netif->hwaddr_len == ETH_HWADDR_LEN", netif->hwaddr_len == ETH_HWADDR_LEN); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), + (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2], + (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5])); + /* non-unicast address? */ + if (ip4_addr_isany(ipaddr) || + ip4_addr_isbroadcast(ipaddr, netif) || + ip4_addr_ismulticast(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + /* find or create ARP entry */ + i = etharp_find_entry(ipaddr, flags, netif); + /* bail out if no entry could be found */ + if (i < 0) { + return (err_t)i; + } + +#if ETHARP_SUPPORT_STATIC_ENTRIES + if (flags & ETHARP_FLAG_STATIC_ENTRY) { + /* record static type */ + arp_table[i].state = ETHARP_STATE_STATIC; + } else if (arp_table[i].state == ETHARP_STATE_STATIC) { + /* found entry is a static type, don't overwrite it */ + return ERR_VAL; + } else +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + { + /* mark it stable */ + arp_table[i].state = ETHARP_STATE_STABLE; + } + + /* record network interface */ + arp_table[i].netif = netif; + /* insert in SNMP ARP index tree */ + mib2_add_arp_entry(netif, &arp_table[i].ipaddr); + + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_update_arp_entry: updating stable entry %"S16_F"\n", i)); + /* update address */ + SMEMCPY(&arp_table[i].ethaddr, ethaddr, ETH_HWADDR_LEN); + /* reset time stamp */ + arp_table[i].ctime = 0; + /* this is where we will send out queued packets! */ +#if ARP_QUEUEING + while (arp_table[i].q != NULL) { + struct pbuf *p; + /* remember remainder of queue */ + struct etharp_q_entry *q = arp_table[i].q; + /* pop first item off the queue */ + arp_table[i].q = q->next; + /* get the packet pointer */ + p = q->p; + /* now queue entry can be freed */ + memp_free(MEMP_ARP_QUEUE, q); +#else /* ARP_QUEUEING */ + if (arp_table[i].q != NULL) { + struct pbuf *p = arp_table[i].q; + arp_table[i].q = NULL; +#endif /* ARP_QUEUEING */ + /* send the queued IP packet */ + ethernet_output(netif, p, (struct eth_addr *)(netif->hwaddr), ethaddr, ETHTYPE_IP); + /* free the queued IP packet */ + pbuf_free(p); + } + return ERR_OK; +} + +#if ETHARP_SUPPORT_STATIC_ENTRIES +/** Add a new static entry to the ARP table. If an entry exists for the + * specified IP address, this entry is overwritten. + * If packets are queued for the specified IP address, they are sent out. + * + * @param ipaddr IP address for the new static entry + * @param ethaddr ethernet address for the new static entry + * @return See return values of etharp_add_static_entry + */ +err_t +etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr) +{ + struct netif *netif; + LWIP_ASSERT_CORE_LOCKED(); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_add_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F" - %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr), + (u16_t)ethaddr->addr[0], (u16_t)ethaddr->addr[1], (u16_t)ethaddr->addr[2], + (u16_t)ethaddr->addr[3], (u16_t)ethaddr->addr[4], (u16_t)ethaddr->addr[5])); + + netif = ip4_route(ipaddr); + if (netif == NULL) { + return ERR_RTE; + } + + return etharp_update_arp_entry(netif, ipaddr, ethaddr, ETHARP_FLAG_TRY_HARD | ETHARP_FLAG_STATIC_ENTRY); +} + +/** Remove a static entry from the ARP table previously added with a call to + * etharp_add_static_entry. + * + * @param ipaddr IP address of the static entry to remove + * @return ERR_OK: entry removed + * ERR_MEM: entry wasn't found + * ERR_ARG: entry wasn't a static entry but a dynamic one + */ +err_t +etharp_remove_static_entry(const ip4_addr_t *ipaddr) +{ + s16_t i; + LWIP_ASSERT_CORE_LOCKED(); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_remove_static_entry: %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(ipaddr), ip4_addr2_16(ipaddr), ip4_addr3_16(ipaddr), ip4_addr4_16(ipaddr))); + + /* find or create ARP entry */ + i = etharp_find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY, NULL); + /* bail out if no entry could be found */ + if (i < 0) { + return (err_t)i; + } + + if (arp_table[i].state != ETHARP_STATE_STATIC) { + /* entry wasn't a static entry, cannot remove it */ + return ERR_ARG; + } + /* entry found, free it */ + etharp_free_entry(i); + return ERR_OK; +} +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + +/** + * Remove all ARP table entries of the specified netif. + * + * @param netif points to a network interface + */ +void +etharp_cleanup_netif(struct netif *netif) +{ + int i; + + for (i = 0; i < ARP_TABLE_SIZE; ++i) { + u8_t state = arp_table[i].state; + if ((state != ETHARP_STATE_EMPTY) && (arp_table[i].netif == netif)) { + etharp_free_entry(i); + } + } +} + +/** + * Finds (stable) ethernet/IP address pair from ARP table + * using interface and IP address index. + * @note the addresses in the ARP table are in network order! + * + * @param netif points to interface index + * @param ipaddr points to the (network order) IP address index + * @param eth_ret points to return pointer + * @param ip_ret points to return pointer + * @return table index if found, -1 otherwise + */ +ssize_t +etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr, + struct eth_addr **eth_ret, const ip4_addr_t **ip_ret) +{ + s16_t i; + + LWIP_ASSERT("eth_ret != NULL && ip_ret != NULL", + eth_ret != NULL && ip_ret != NULL); + + LWIP_UNUSED_ARG(netif); + + i = etharp_find_entry(ipaddr, ETHARP_FLAG_FIND_ONLY, netif); + if ((i >= 0) && (arp_table[i].state >= ETHARP_STATE_STABLE)) { + *eth_ret = &arp_table[i].ethaddr; + *ip_ret = &arp_table[i].ipaddr; + return i; + } + return -1; +} + +/** + * Possibility to iterate over stable ARP table entries + * + * @param i entry number, 0 to ARP_TABLE_SIZE + * @param ipaddr return value: IP address + * @param netif return value: points to interface + * @param eth_ret return value: ETH address + * @return 1 on valid index, 0 otherwise + */ +int +etharp_get_entry(size_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret) +{ + LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL); + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("eth_ret != NULL", eth_ret != NULL); + + if ((i < ARP_TABLE_SIZE) && (arp_table[i].state >= ETHARP_STATE_STABLE)) { + *ipaddr = &arp_table[i].ipaddr; + *netif = arp_table[i].netif; + *eth_ret = &arp_table[i].ethaddr; + return 1; + } else { + return 0; + } +} + +/** + * Responds to ARP requests to us. Upon ARP replies to us, add entry to cache + * send out queued IP packets. Updates cache with snooped address pairs. + * + * Should be called for incoming ARP packets. The pbuf in the argument + * is freed by this function. + * + * @param p The ARP packet that arrived on netif. Is freed by this function. + * @param netif The lwIP network interface on which the ARP packet pbuf arrived. + * + * @see pbuf_free() + */ +void +etharp_input(struct pbuf *p, struct netif *netif) +{ + struct etharp_hdr *hdr; + /* these are aligned properly, whereas the ARP header fields might not be */ + ip4_addr_t sipaddr, dipaddr; + u8_t for_us; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif != NULL", (netif != NULL), return;); + + hdr = (struct etharp_hdr *)p->payload; + + /* RFC 826 "Packet Reception": */ + if ((hdr->hwtype != PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET)) || + (hdr->hwlen != ETH_HWADDR_LEN) || + (hdr->protolen != sizeof(ip4_addr_t)) || + (hdr->proto != PP_HTONS(ETHTYPE_IP))) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("etharp_input: packet dropped, wrong hw type, hwlen, proto, protolen or ethernet type (%"U16_F"/%"U16_F"/%"U16_F"/%"U16_F")\n", + hdr->hwtype, (u16_t)hdr->hwlen, hdr->proto, (u16_t)hdr->protolen)); + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + pbuf_free(p); + return; + } + ETHARP_STATS_INC(etharp.recv); + +#if LWIP_AUTOIP + /* We have to check if a host already has configured our random + * created link local address and continuously check if there is + * a host with this IP-address so we can detect collisions */ + autoip_arp_reply(netif, hdr); +#endif /* LWIP_AUTOIP */ + + /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without + * structure packing (not using structure copy which breaks strict-aliasing rules). */ + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&sipaddr, &hdr->sipaddr); + IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(&dipaddr, &hdr->dipaddr); + + /* this interface is not configured? */ + if (ip4_addr_isany_val(*netif_ip4_addr(netif))) { + for_us = 0; + } else { + /* ARP packet directed to us? */ + for_us = (u8_t)ip4_addr_cmp(&dipaddr, netif_ip4_addr(netif)); + } + + /* ARP message directed to us? + -> add IP address in ARP cache; assume requester wants to talk to us, + can result in directly sending the queued packets for this host. + ARP message not directed to us? + -> update the source IP address in the cache, if present */ + etharp_update_arp_entry(netif, &sipaddr, &(hdr->shwaddr), + for_us ? ETHARP_FLAG_TRY_HARD : ETHARP_FLAG_FIND_ONLY); + + /* now act on the message itself */ + switch (hdr->opcode) { + /* ARP request? */ + case PP_HTONS(ARP_REQUEST): + /* ARP request. If it asked for our address, we send out a + * reply. In any case, we time-stamp any existing ARP entry, + * and possibly send out an IP packet that was queued on it. */ + + LWIP_DEBUGF (ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: incoming ARP request\n")); + /* ARP request for our address? */ + if (for_us) { + /* send ARP response */ + etharp_raw(netif, + (struct eth_addr *)netif->hwaddr, &hdr->shwaddr, + (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), + &hdr->shwaddr, &sipaddr, + ARP_REPLY); + /* we are not configured? */ + } else if (ip4_addr_isany_val(*netif_ip4_addr(netif))) { + /* { for_us == 0 and netif->ip_addr.addr == 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: we are unconfigured, ARP request ignored.\n")); + /* request was not directed to us */ + } else { + /* { for_us == 0 and netif->ip_addr.addr != 0 } */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP request was not for us.\n")); + } + break; + case PP_HTONS(ARP_REPLY): + /* ARP reply. We already updated the ARP cache earlier. */ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: incoming ARP reply\n")); +#if (LWIP_DHCP && DHCP_DOES_ARP_CHECK) + /* DHCP wants to know about ARP replies from any host with an + * IP address also offered to us by the DHCP server. We do not + * want to take a duplicate IP address on a single network. + * @todo How should we handle redundant (fail-over) interfaces? */ + dhcp_arp_reply(netif, &sipaddr); +#endif /* (LWIP_DHCP && DHCP_DOES_ARP_CHECK) */ + break; + default: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_input: ARP unknown opcode type %"S16_F"\n", lwip_htons(hdr->opcode))); + ETHARP_STATS_INC(etharp.err); + break; + } + /* free ARP packet */ + pbuf_free(p); +} + +/** Just a small helper function that sends a pbuf to an ethernet address + * in the arp_table specified by the index 'arp_idx'. + */ +static err_t +etharp_output_to_arp_index(struct netif *netif, struct pbuf *q, netif_addr_idx_t arp_idx) +{ + LWIP_ASSERT("arp_table[arp_idx].state >= ETHARP_STATE_STABLE", + arp_table[arp_idx].state >= ETHARP_STATE_STABLE); + /* if arp table entry is about to expire: re-request it, + but only if its state is ETHARP_STATE_STABLE to prevent flooding the + network with ARP requests if this address is used frequently. */ + if (arp_table[arp_idx].state == ETHARP_STATE_STABLE) { + if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_BROADCAST) { + /* issue a standard request using broadcast */ + if (etharp_request(netif, &arp_table[arp_idx].ipaddr) == ERR_OK) { + arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; + } + } else if (arp_table[arp_idx].ctime >= ARP_AGE_REREQUEST_USED_UNICAST) { + /* issue a unicast request (for 15 seconds) to prevent unnecessary broadcast */ + if (etharp_request_dst(netif, &arp_table[arp_idx].ipaddr, &arp_table[arp_idx].ethaddr) == ERR_OK) { + arp_table[arp_idx].state = ETHARP_STATE_STABLE_REREQUESTING_1; + } + } + } + + return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), &arp_table[arp_idx].ethaddr, ETHTYPE_IP); +} + +/** + * Resolve and fill-in Ethernet address header for outgoing IP packet. + * + * For IP multicast and broadcast, corresponding Ethernet addresses + * are selected and the packet is transmitted on the link. + * + * For unicast addresses, the packet is submitted to etharp_query(). In + * case the IP address is outside the local network, the IP address of + * the gateway is used. + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param q The pbuf(s) containing the IP packet to be sent. + * @param ipaddr The IP address of the packet destination. + * + * @return + * - ERR_RTE No route to destination (no gateway to external networks), + * or the return type of either etharp_query() or ethernet_output(). + */ +err_t +etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr) +{ + const struct eth_addr *dest; + struct eth_addr mcastaddr; + const ip4_addr_t *dst_addr = ipaddr; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("q != NULL", q != NULL); + LWIP_ASSERT("ipaddr != NULL", ipaddr != NULL); + + /* Determine on destination hardware address. Broadcasts and multicasts + * are special, other IP addresses are looked up in the ARP table. */ + + /* broadcast destination IP address? */ + if (ip4_addr_isbroadcast(ipaddr, netif)) { + /* broadcast on Ethernet also */ + dest = (const struct eth_addr *)ðbroadcast; + /* multicast destination IP address? */ + } else if (ip4_addr_ismulticast(ipaddr)) { + /* Hash IP multicast address to MAC address.*/ + mcastaddr.addr[0] = LL_IP4_MULTICAST_ADDR_0; + mcastaddr.addr[1] = LL_IP4_MULTICAST_ADDR_1; + mcastaddr.addr[2] = LL_IP4_MULTICAST_ADDR_2; + mcastaddr.addr[3] = ip4_addr2(ipaddr) & 0x7f; + mcastaddr.addr[4] = ip4_addr3(ipaddr); + mcastaddr.addr[5] = ip4_addr4(ipaddr); + /* destination Ethernet address is multicast */ + dest = &mcastaddr; + /* unicast destination IP address? */ + } else { + netif_addr_idx_t i; + /* outside local network? if so, this can neither be a global broadcast nor + a subnet broadcast. */ + if (!ip4_addr_netcmp(ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) && + !ip4_addr_islinklocal(ipaddr)) { +#if LWIP_AUTOIP + struct ip_hdr *iphdr = LWIP_ALIGNMENT_CAST(struct ip_hdr *, q->payload); + /* According to RFC 3297, chapter 2.6.2 (Forwarding Rules), a packet with + a link-local source address must always be "directly to its destination + on the same physical link. The host MUST NOT send the packet to any + router for forwarding". */ + if (!ip4_addr_islinklocal(&iphdr->src)) +#endif /* LWIP_AUTOIP */ + { +#ifdef LWIP_HOOK_ETHARP_GET_GW + /* For advanced routing, a single default gateway might not be enough, so get + the IP address of the gateway to handle the current destination address. */ + dst_addr = LWIP_HOOK_ETHARP_GET_GW(netif, ipaddr); + if (dst_addr == NULL) +#endif /* LWIP_HOOK_ETHARP_GET_GW */ + { + /* interface has default gateway? */ + if (!ip4_addr_isany_val(*netif_ip4_gw(netif))) { + /* send to hardware address of default gateway IP address */ + dst_addr = netif_ip4_gw(netif); + /* no default gateway available */ + } else { + /* no route to destination error (default gateway missing) */ + return ERR_RTE; + } + } + } + } +#if LWIP_NETIF_HWADDRHINT + if (netif->hints != NULL) { + /* per-pcb cached entry was given */ + netif_addr_idx_t etharp_cached_entry = netif->hints->addr_hint; + if (etharp_cached_entry < ARP_TABLE_SIZE) { +#endif /* LWIP_NETIF_HWADDRHINT */ + if ((arp_table[etharp_cached_entry].state >= ETHARP_STATE_STABLE) && +#if ETHARP_TABLE_MATCH_NETIF + (arp_table[etharp_cached_entry].netif == netif) && +#endif + (ip4_addr_cmp(dst_addr, &arp_table[etharp_cached_entry].ipaddr))) { + /* the per-pcb-cached entry is stable and the right one! */ + ETHARP_STATS_INC(etharp.cachehit); + return etharp_output_to_arp_index(netif, q, etharp_cached_entry); + } +#if LWIP_NETIF_HWADDRHINT + } + } +#endif /* LWIP_NETIF_HWADDRHINT */ + + /* find stable entry: do this here since this is a critical path for + throughput and etharp_find_entry() is kind of slow */ + for (i = 0; i < ARP_TABLE_SIZE; i++) { + if ((arp_table[i].state >= ETHARP_STATE_STABLE) && +#if ETHARP_TABLE_MATCH_NETIF + (arp_table[i].netif == netif) && +#endif + (ip4_addr_cmp(dst_addr, &arp_table[i].ipaddr))) { + /* found an existing, stable entry */ + ETHARP_SET_ADDRHINT(netif, i); + return etharp_output_to_arp_index(netif, q, i); + } + } + /* no stable entry found, use the (slower) query function: + queue on destination Ethernet address belonging to ipaddr */ + return etharp_query(netif, dst_addr, q); + } + + /* continuation for multicast/broadcast destinations */ + /* obtain source Ethernet address of the given interface */ + /* send packet directly on the link */ + return ethernet_output(netif, q, (struct eth_addr *)(netif->hwaddr), dest, ETHTYPE_IP); +} + +/** + * Send an ARP request for the given IP address and/or queue a packet. + * + * If the IP address was not yet in the cache, a pending ARP cache entry + * is added and an ARP request is sent for the given address. The packet + * is queued on this entry. + * + * If the IP address was already pending in the cache, a new ARP request + * is sent for the given address. The packet is queued on this entry. + * + * If the IP address was already stable in the cache, and a packet is + * given, it is directly sent and no ARP request is sent out. + * + * If the IP address was already stable in the cache, and no packet is + * given, an ARP request is sent out. + * + * @param netif The lwIP network interface on which ipaddr + * must be queried for. + * @param ipaddr The IP address to be resolved. + * @param q If non-NULL, a pbuf that must be delivered to the IP address. + * q is not freed by this function. + * + * @note q must only be ONE packet, not a packet queue! + * + * @return + * - ERR_BUF Could not make room for Ethernet header. + * - ERR_MEM Hardware address unknown, and no more ARP entries available + * to query for address or queue the packet. + * - ERR_MEM Could not queue packet due to memory shortage. + * - ERR_RTE No route to destination (no gateway to external networks). + * - ERR_ARG Non-unicast address given, those will not appear in ARP cache. + * + */ +err_t +etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q) +{ + struct eth_addr *srcaddr = (struct eth_addr *)netif->hwaddr; + err_t result = ERR_MEM; + int is_new_entry = 0; + s16_t i_err; + netif_addr_idx_t i; + + /* non-unicast address? */ + if (ip4_addr_isbroadcast(ipaddr, netif) || + ip4_addr_ismulticast(ipaddr) || + ip4_addr_isany(ipaddr)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: will not add non-unicast IP address to ARP cache\n")); + return ERR_ARG; + } + + /* find entry in ARP cache, ask to create entry if queueing packet */ + i_err = etharp_find_entry(ipaddr, ETHARP_FLAG_TRY_HARD, netif); + + /* could not find or create entry? */ + if (i_err < 0) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not create ARP entry\n")); + if (q) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: packet dropped\n")); + ETHARP_STATS_INC(etharp.memerr); + } + return (err_t)i_err; + } + LWIP_ASSERT("type overflow", (size_t)i_err < NETIF_ADDR_IDX_MAX); + i = (netif_addr_idx_t)i_err; + + /* mark a fresh entry as pending (we just sent a request) */ + if (arp_table[i].state == ETHARP_STATE_EMPTY) { + is_new_entry = 1; + arp_table[i].state = ETHARP_STATE_PENDING; + /* record network interface for re-sending arp request in etharp_tmr */ + arp_table[i].netif = netif; + } + + /* { i is either a STABLE or (new or existing) PENDING entry } */ + LWIP_ASSERT("arp_table[i].state == PENDING or STABLE", + ((arp_table[i].state == ETHARP_STATE_PENDING) || + (arp_table[i].state >= ETHARP_STATE_STABLE))); + + /* do we have a new entry? or an implicit query request? */ + if (is_new_entry || (q == NULL)) { + /* try to resolve it; send out ARP request */ + result = etharp_request(netif, ipaddr); + if (result != ERR_OK) { + /* ARP request couldn't be sent */ + /* We don't re-send arp request in etharp_tmr, but we still queue packets, + since this failure could be temporary, and the next packet calling + etharp_query again could lead to sending the queued packets. */ + } + if (q == NULL) { + return result; + } + } + + /* packet given? */ + LWIP_ASSERT("q != NULL", q != NULL); + /* stable entry? */ + if (arp_table[i].state >= ETHARP_STATE_STABLE) { + /* we have a valid IP->Ethernet address mapping */ + ETHARP_SET_ADDRHINT(netif, i); + /* send the packet */ + result = ethernet_output(netif, q, srcaddr, &(arp_table[i].ethaddr), ETHTYPE_IP); + /* pending entry? (either just created or already pending */ + } else if (arp_table[i].state == ETHARP_STATE_PENDING) { + /* entry is still pending, queue the given packet 'q' */ + struct pbuf *p; + int copy_needed = 0; + /* IF q includes a pbuf that must be copied, copy the whole chain into a + * new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */ + p = q; + while (p) { + LWIP_ASSERT("no packet queues allowed!", (p->len != p->tot_len) || (p->next == 0)); + if (PBUF_NEEDS_COPY(p)) { + copy_needed = 1; + break; + } + p = p->next; + } + if (copy_needed) { + /* copy the whole packet into new pbufs */ + p = pbuf_clone(PBUF_LINK, PBUF_RAM, q); + } else { + /* referencing the old pbuf is enough */ + p = q; + pbuf_ref(p); + } + /* packet could be taken over? */ + if (p != NULL) { + /* queue packet ... */ +#if ARP_QUEUEING + struct etharp_q_entry *new_entry; + /* allocate a new arp queue entry */ + new_entry = (struct etharp_q_entry *)memp_malloc(MEMP_ARP_QUEUE); + if (new_entry != NULL) { + unsigned int qlen = 0; + new_entry->next = 0; + new_entry->p = p; + if (arp_table[i].q != NULL) { + /* queue was already existent, append the new entry to the end */ + struct etharp_q_entry *r; + r = arp_table[i].q; + qlen++; + while (r->next != NULL) { + r = r->next; + qlen++; + } + r->next = new_entry; + } else { + /* queue did not exist, first item in queue */ + arp_table[i].q = new_entry; + } +#if ARP_QUEUE_LEN + if (qlen >= ARP_QUEUE_LEN) { + struct etharp_q_entry *old; + old = arp_table[i].q; + arp_table[i].q = arp_table[i].q->next; + pbuf_free(old->p); + memp_free(MEMP_ARP_QUEUE, old); + } +#endif + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, i)); + result = ERR_OK; + } else { + /* the pool MEMP_ARP_QUEUE is empty */ + pbuf_free(p); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + } +#else /* ARP_QUEUEING */ + /* always queue one packet per ARP request only, freeing a previously queued packet */ + if (arp_table[i].q != NULL) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: dropped previously queued packet %p for ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); + pbuf_free(arp_table[i].q); + } + arp_table[i].q = p; + result = ERR_OK; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: queued packet %p on ARP entry %"U16_F"\n", (void *)q, (u16_t)i)); +#endif /* ARP_QUEUEING */ + } else { + ETHARP_STATS_INC(etharp.memerr); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_query: could not queue a copy of PBUF_REF packet %p (out of memory)\n", (void *)q)); + result = ERR_MEM; + } + } + return result; +} + +/** + * Send a raw ARP packet (opcode and all addresses can be modified) + * + * @param netif the lwip network interface on which to send the ARP packet + * @param ethsrc_addr the source MAC address for the ethernet header + * @param ethdst_addr the destination MAC address for the ethernet header + * @param hwsrc_addr the source MAC address for the ARP protocol header + * @param ipsrc_addr the source IP address for the ARP protocol header + * @param hwdst_addr the destination MAC address for the ARP protocol header + * @param ipdst_addr the destination IP address for the ARP protocol header + * @param opcode the type of the ARP packet + * @return ERR_OK if the ARP packet has been sent + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +static err_t +etharp_raw(struct netif *netif, const struct eth_addr *ethsrc_addr, + const struct eth_addr *ethdst_addr, + const struct eth_addr *hwsrc_addr, const ip4_addr_t *ipsrc_addr, + const struct eth_addr *hwdst_addr, const ip4_addr_t *ipdst_addr, + const u16_t opcode) +{ + struct pbuf *p; + err_t result = ERR_OK; + struct etharp_hdr *hdr; + + LWIP_ASSERT("netif != NULL", netif != NULL); + + /* allocate a pbuf for the outgoing ARP request packet */ + p = pbuf_alloc(PBUF_LINK, SIZEOF_ETHARP_HDR, PBUF_RAM); + /* could allocate a pbuf for an ARP request? */ + if (p == NULL) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("etharp_raw: could not allocate pbuf for ARP request.\n")); + ETHARP_STATS_INC(etharp.memerr); + return ERR_MEM; + } + LWIP_ASSERT("check that first pbuf can hold struct etharp_hdr", + (p->len >= SIZEOF_ETHARP_HDR)); + + hdr = (struct etharp_hdr *)p->payload; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_raw: sending raw ARP packet.\n")); + hdr->opcode = lwip_htons(opcode); + + LWIP_ASSERT("netif->hwaddr_len must be the same as ETH_HWADDR_LEN for etharp!", + (netif->hwaddr_len == ETH_HWADDR_LEN)); + + /* Write the ARP MAC-Addresses */ + SMEMCPY(&hdr->shwaddr, hwsrc_addr, ETH_HWADDR_LEN); + SMEMCPY(&hdr->dhwaddr, hwdst_addr, ETH_HWADDR_LEN); + /* Copy struct ip4_addr_wordaligned to aligned ip4_addr, to support compilers without + * structure packing. */ + IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->sipaddr, ipsrc_addr); + IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(&hdr->dipaddr, ipdst_addr); + + hdr->hwtype = PP_HTONS(LWIP_IANA_HWTYPE_ETHERNET); + hdr->proto = PP_HTONS(ETHTYPE_IP); + /* set hwlen and protolen */ + hdr->hwlen = ETH_HWADDR_LEN; + hdr->protolen = sizeof(ip4_addr_t); + + /* send ARP query */ +#if LWIP_AUTOIP + /* If we are using Link-Local, all ARP packets that contain a Link-Local + * 'sender IP address' MUST be sent using link-layer broadcast instead of + * link-layer unicast. (See RFC3927 Section 2.5, last paragraph) */ + if (ip4_addr_islinklocal(ipsrc_addr)) { + ethernet_output(netif, p, ethsrc_addr, ðbroadcast, ETHTYPE_ARP); + } else +#endif /* LWIP_AUTOIP */ + { + ethernet_output(netif, p, ethsrc_addr, ethdst_addr, ETHTYPE_ARP); + } + + ETHARP_STATS_INC(etharp.xmit); + /* free ARP query packet */ + pbuf_free(p); + p = NULL; + /* could not allocate pbuf for ARP request */ + + return result; +} + +/** + * Send an ARP request packet asking for ipaddr to a specific eth address. + * Used to send unicast request to refresh the ARP table just before an entry + * times out + * + * @param netif the lwip network interface on which to send the request + * @param ipaddr the IP address for which to ask + * @param hw_dst_addr the ethernet address to send this packet to + * @return ERR_OK if the request has been sent + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +static err_t +etharp_request_dst(struct netif *netif, const ip4_addr_t *ipaddr, const struct eth_addr *hw_dst_addr) +{ + return etharp_raw(netif, (struct eth_addr *)netif->hwaddr, hw_dst_addr, + (struct eth_addr *)netif->hwaddr, netif_ip4_addr(netif), ðzero, + ipaddr, ARP_REQUEST); +} + +/** + * Send an ARP request packet asking for ipaddr. + * + * @param netif the lwip network interface on which to send the request + * @param ipaddr the IP address for which to ask + * @return ERR_OK if the request has been sent + * ERR_MEM if the ARP packet couldn't be allocated + * any other err_t on failure + */ +err_t +etharp_request(struct netif *netif, const ip4_addr_t *ipaddr) +{ + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("etharp_request: sending ARP request.\n")); + return etharp_request_dst(netif, ipaddr, ðbroadcast); +} + +#endif /* LWIP_IPV4 && LWIP_ARP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c new file mode 100644 index 0000000..a462ccd --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/icmp.c @@ -0,0 +1,404 @@ +/** + * @file + * ICMP - Internet Control Message Protocol + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* Some ICMP messages should be passed to the transport protocols. This + is not implemented. */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/icmp.h" +#include "lwip/inet_chksum.h" +#include "lwip/ip.h" +#include "lwip/def.h" +#include "lwip/stats.h" + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +/** Small optimization: set to 0 if incoming PBUF_POOL pbuf always can be + * used to modify and send a response packet (and to 1 if this is not the case, + * e.g. when link header is stripped off when receiving) */ +#ifndef LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN +#define LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN 1 +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ + +/* The amount of data from the original packet to return in a dest-unreachable */ +#define ICMP_DEST_UNREACH_DATASIZE 8 + +static void icmp_send_response(struct pbuf *p, u8_t type, u8_t code); + +/** + * Processes ICMP input packets, called from ip_input(). + * + * Currently only processes icmp echo requests and sends + * out the echo response. + * + * @param p the icmp echo request packet, p->payload pointing to the icmp header + * @param inp the netif on which this packet was received + */ +void +icmp_input(struct pbuf *p, struct netif *inp) +{ + u8_t type; +#ifdef LWIP_DEBUG + u8_t code; +#endif /* LWIP_DEBUG */ + struct icmp_echo_hdr *iecho; + const struct ip_hdr *iphdr_in; + u16_t hlen; + const ip4_addr_t *src; + + ICMP_STATS_INC(icmp.recv); + MIB2_STATS_INC(mib2.icmpinmsgs); + + iphdr_in = ip4_current_header(); + hlen = IPH_HL_BYTES(iphdr_in); + if (hlen < IP_HLEN) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short IP header (%"S16_F" bytes) received\n", hlen)); + goto lenerr; + } + if (p->len < sizeof(u16_t) * 2) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: short ICMP (%"U16_F" bytes) received\n", p->tot_len)); + goto lenerr; + } + + type = *((u8_t *)p->payload); +#ifdef LWIP_DEBUG + code = *(((u8_t *)p->payload) + 1); + /* if debug is enabled but debug statement below is somehow disabled: */ + LWIP_UNUSED_ARG(code); +#endif /* LWIP_DEBUG */ + switch (type) { + case ICMP_ER: + /* This is OK, echo reply might have been parsed by a raw PCB + (as obviously, an echo request has been sent, too). */ + MIB2_STATS_INC(mib2.icmpinechoreps); + break; + case ICMP_ECHO: + MIB2_STATS_INC(mib2.icmpinechos); + src = ip4_current_dest_addr(); + /* multicast destination address? */ + if (ip4_addr_ismulticast(ip4_current_dest_addr())) { +#if LWIP_MULTICAST_PING + /* For multicast, use address of receiving interface as source address */ + src = netif_ip4_addr(inp); +#else /* LWIP_MULTICAST_PING */ + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to multicast pings\n")); + goto icmperr; +#endif /* LWIP_MULTICAST_PING */ + } + /* broadcast destination address? */ + if (ip4_addr_isbroadcast(ip4_current_dest_addr(), ip_current_netif())) { +#if LWIP_BROADCAST_PING + /* For broadcast, use address of receiving interface as source address */ + src = netif_ip4_addr(inp); +#else /* LWIP_BROADCAST_PING */ + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: Not echoing to broadcast pings\n")); + goto icmperr; +#endif /* LWIP_BROADCAST_PING */ + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ping\n")); + if (p->tot_len < sizeof(struct icmp_echo_hdr)) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: bad ICMP echo received\n")); + goto lenerr; + } +#if CHECKSUM_CHECK_ICMP + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP) { + if (inet_chksum_pbuf(p) != 0) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: checksum failed for received ICMP echo\n")); + pbuf_free(p); + ICMP_STATS_INC(icmp.chkerr); + MIB2_STATS_INC(mib2.icmpinerrors); + return; + } + } +#endif +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN + if (pbuf_add_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { + /* p is not big enough to contain link headers + * allocate a new one and copy p into it + */ + struct pbuf *r; + u16_t alloc_len = (u16_t)(p->tot_len + hlen); + if (alloc_len < p->tot_len) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed (tot_len overflow)\n")); + goto icmperr; + } + /* allocate new packet buffer with space for link headers */ + r = pbuf_alloc(PBUF_LINK, alloc_len, PBUF_RAM); + if (r == NULL) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: allocating new pbuf failed\n")); + goto icmperr; + } + if (r->len < hlen + sizeof(struct icmp_echo_hdr)) { + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("first pbuf cannot hold the ICMP header")); + pbuf_free(r); + goto icmperr; + } + /* copy the ip header */ + MEMCPY(r->payload, iphdr_in, hlen); + /* switch r->payload back to icmp header (cannot fail) */ + if (pbuf_remove_header(r, hlen)) { + LWIP_ASSERT("icmp_input: moving r->payload to icmp header failed\n", 0); + pbuf_free(r); + goto icmperr; + } + /* copy the rest of the packet without ip header */ + if (pbuf_copy(r, p) != ERR_OK) { + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("icmp_input: copying to new pbuf failed")); + pbuf_free(r); + goto icmperr; + } + /* free the original p */ + pbuf_free(p); + /* we now have an identical copy of p that has room for link headers */ + p = r; + } else { + /* restore p->payload to point to icmp header (cannot fail) */ + if (pbuf_remove_header(p, hlen + PBUF_LINK_HLEN + PBUF_LINK_ENCAPSULATION_HLEN)) { + LWIP_ASSERT("icmp_input: restoring original p->payload failed\n", 0); + goto icmperr; + } + } +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN */ + /* At this point, all checks are OK. */ + /* We generate an answer by switching the dest and src ip addresses, + * setting the icmp type to ECHO_RESPONSE and updating the checksum. */ + iecho = (struct icmp_echo_hdr *)p->payload; + if (pbuf_add_header(p, hlen)) { + LWIP_DEBUGF(ICMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Can't move over header in packet")); + } else { + err_t ret; + struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; + ip4_addr_copy(iphdr->src, *src); + ip4_addr_copy(iphdr->dest, *ip4_current_src_addr()); + ICMPH_TYPE_SET(iecho, ICMP_ER); +#if CHECKSUM_GEN_ICMP + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP) { + /* adjust the checksum */ + if (iecho->chksum > PP_HTONS(0xffffU - (ICMP_ECHO << 8))) { + iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS((u16_t)(ICMP_ECHO << 8)) + 1); + } else { + iecho->chksum = (u16_t)(iecho->chksum + PP_HTONS(ICMP_ECHO << 8)); + } + } +#if LWIP_CHECKSUM_CTRL_PER_NETIF + else { + iecho->chksum = 0; + } +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ +#else /* CHECKSUM_GEN_ICMP */ + iecho->chksum = 0; +#endif /* CHECKSUM_GEN_ICMP */ + + /* Set the correct TTL and recalculate the header checksum. */ + IPH_TTL_SET(iphdr, ICMP_TTL); + IPH_CHKSUM_SET(iphdr, 0); +#if CHECKSUM_GEN_IP + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_IP) { + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, hlen)); + } +#endif /* CHECKSUM_GEN_IP */ + + ICMP_STATS_INC(icmp.xmit); + /* increase number of messages attempted to send */ + MIB2_STATS_INC(mib2.icmpoutmsgs); + /* increase number of echo replies attempted to send */ + MIB2_STATS_INC(mib2.icmpoutechoreps); + + /* send an ICMP packet */ + ret = ip4_output_if(p, src, LWIP_IP_HDRINCL, + ICMP_TTL, 0, IP_PROTO_ICMP, inp); + if (ret != ERR_OK) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ip_output_if returned an error: %s\n", lwip_strerr(ret))); + } + } + break; + default: + if (type == ICMP_DUR) { + MIB2_STATS_INC(mib2.icmpindestunreachs); + } else if (type == ICMP_TE) { + MIB2_STATS_INC(mib2.icmpintimeexcds); + } else if (type == ICMP_PP) { + MIB2_STATS_INC(mib2.icmpinparmprobs); + } else if (type == ICMP_SQ) { + MIB2_STATS_INC(mib2.icmpinsrcquenchs); + } else if (type == ICMP_RD) { + MIB2_STATS_INC(mib2.icmpinredirects); + } else if (type == ICMP_TS) { + MIB2_STATS_INC(mib2.icmpintimestamps); + } else if (type == ICMP_TSR) { + MIB2_STATS_INC(mib2.icmpintimestampreps); + } else if (type == ICMP_AM) { + MIB2_STATS_INC(mib2.icmpinaddrmasks); + } else if (type == ICMP_AMR) { + MIB2_STATS_INC(mib2.icmpinaddrmaskreps); + } + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_input: ICMP type %"S16_F" code %"S16_F" not supported.\n", + (s16_t)type, (s16_t)code)); + ICMP_STATS_INC(icmp.proterr); + ICMP_STATS_INC(icmp.drop); + } + pbuf_free(p); + return; +lenerr: + pbuf_free(p); + ICMP_STATS_INC(icmp.lenerr); + MIB2_STATS_INC(mib2.icmpinerrors); + return; +#if LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING +icmperr: + pbuf_free(p); + ICMP_STATS_INC(icmp.err); + MIB2_STATS_INC(mib2.icmpinerrors); + return; +#endif /* LWIP_ICMP_ECHO_CHECK_INPUT_PBUF_LEN || !LWIP_MULTICAST_PING || !LWIP_BROADCAST_PING */ +} + +/** + * Send an icmp 'destination unreachable' packet, called from ip_input() if + * the transport layer protocol is unknown and from udp_input() if the local + * port is not bound. + * + * @param p the input packet for which the 'unreachable' should be sent, + * p->payload pointing to the IP header + * @param t type of the 'unreachable' packet + */ +void +icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t) +{ + MIB2_STATS_INC(mib2.icmpoutdestunreachs); + icmp_send_response(p, ICMP_DUR, t); +} + +#if IP_FORWARD || IP_REASSEMBLY +/** + * Send a 'time exceeded' packet, called from ip_forward() if TTL is 0. + * + * @param p the input packet for which the 'time exceeded' should be sent, + * p->payload pointing to the IP header + * @param t type of the 'time exceeded' packet + */ +void +icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t) +{ + MIB2_STATS_INC(mib2.icmpouttimeexcds); + icmp_send_response(p, ICMP_TE, t); +} + +#endif /* IP_FORWARD || IP_REASSEMBLY */ + +/** + * Send an icmp packet in response to an incoming packet. + * + * @param p the input packet for which the 'unreachable' should be sent, + * p->payload pointing to the IP header + * @param type Type of the ICMP header + * @param code Code of the ICMP header + */ +static void +icmp_send_response(struct pbuf *p, u8_t type, u8_t code) +{ + struct pbuf *q; + struct ip_hdr *iphdr; + /* we can use the echo header here */ + struct icmp_echo_hdr *icmphdr; + ip4_addr_t iphdr_src; + struct netif *netif; + + /* increase number of messages attempted to send */ + MIB2_STATS_INC(mib2.icmpoutmsgs); + + /* ICMP header + IP header + 8 bytes of data */ + q = pbuf_alloc(PBUF_IP, sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE, + PBUF_RAM); + if (q == NULL) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMP packet.\n")); + MIB2_STATS_INC(mib2.icmpouterrors); + return; + } + LWIP_ASSERT("check that first pbuf can hold icmp message", + (q->len >= (sizeof(struct icmp_echo_hdr) + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE))); + + iphdr = (struct ip_hdr *)p->payload; + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded from ")); + ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->src); + LWIP_DEBUGF(ICMP_DEBUG, (" to ")); + ip4_addr_debug_print_val(ICMP_DEBUG, iphdr->dest); + LWIP_DEBUGF(ICMP_DEBUG, ("\n")); + + icmphdr = (struct icmp_echo_hdr *)q->payload; + icmphdr->type = type; + icmphdr->code = code; + icmphdr->id = 0; + icmphdr->seqno = 0; + + /* copy fields from original packet */ + SMEMCPY((u8_t *)q->payload + sizeof(struct icmp_echo_hdr), (u8_t *)p->payload, + IP_HLEN + ICMP_DEST_UNREACH_DATASIZE); + + ip4_addr_copy(iphdr_src, iphdr->src); +#ifdef LWIP_HOOK_IP4_ROUTE_SRC + { + ip4_addr_t iphdr_dst; + ip4_addr_copy(iphdr_dst, iphdr->dest); + netif = ip4_route_src(&iphdr_dst, &iphdr_src); + } +#else + netif = ip4_route(&iphdr_src); +#endif + if (netif != NULL) { + /* calculate checksum */ + icmphdr->chksum = 0; +#if CHECKSUM_GEN_ICMP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP) { + icmphdr->chksum = inet_chksum(icmphdr, q->len); + } +#endif + ICMP_STATS_INC(icmp.xmit); + ip4_output_if(q, NULL, &iphdr_src, ICMP_TTL, 0, IP_PROTO_ICMP, netif); + } + pbuf_free(q); +} + +#endif /* LWIP_IPV4 && LWIP_ICMP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c new file mode 100644 index 0000000..b655aa3 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/igmp.c @@ -0,0 +1,801 @@ +/** + * @file + * IGMP - Internet Group Management Protocol + * + * @defgroup igmp IGMP + * @ingroup ip4 + * To be called from TCPIP thread + */ + +/* + * Copyright (c) 2002 CITEL Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. +*/ + +/*------------------------------------------------------------- +Note 1) +Although the rfc requires V1 AND V2 capability +we will only support v2 since now V1 is very old (August 1989) +V1 can be added if required + +a debug print and statistic have been implemented to +show this up. +------------------------------------------------------------- +------------------------------------------------------------- +Note 2) +A query for a specific group address (as opposed to ALLHOSTS) +has now been implemented as I am unsure if it is required + +a debug print and statistic have been implemented to +show this up. +------------------------------------------------------------- +------------------------------------------------------------- +Note 3) +The router alert rfc 2113 is implemented in outgoing packets +but not checked rigorously incoming +------------------------------------------------------------- +Steve Reynolds +------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- + * RFC 988 - Host extensions for IP multicasting - V0 + * RFC 1054 - Host extensions for IP multicasting - + * RFC 1112 - Host extensions for IP multicasting - V1 + * RFC 2236 - Internet Group Management Protocol, Version 2 - V2 <- this code is based on this RFC (it's the "de facto" standard) + * RFC 3376 - Internet Group Management Protocol, Version 3 - V3 + * RFC 4604 - Using Internet Group Management Protocol Version 3... - V3+ + * RFC 2113 - IP Router Alert Option - + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "lwip/opt.h" + +#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/igmp.h" +#include "lwip/debug.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/ip.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/stats.h" +#include "lwip/prot/igmp.h" + +#include + +static struct igmp_group *igmp_lookup_group(struct netif *ifp, const ip4_addr_t *addr); +static err_t igmp_remove_group(struct netif *netif, struct igmp_group *group); +static void igmp_timeout(struct netif *netif, struct igmp_group *group); +static void igmp_start_timer(struct igmp_group *group, u8_t max_time); +static void igmp_delaying_member(struct igmp_group *group, u8_t maxresp); +static err_t igmp_ip_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, struct netif *netif); +static void igmp_send(struct netif *netif, struct igmp_group *group, u8_t type); + +static ip4_addr_t allsystems; +static ip4_addr_t allrouters; + +/** + * Initialize the IGMP module + */ +void +igmp_init(void) +{ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_init: initializing\n")); + + IP4_ADDR(&allsystems, 224, 0, 0, 1); + IP4_ADDR(&allrouters, 224, 0, 0, 2); +} + +/** + * Start IGMP processing on interface + * + * @param netif network interface on which start IGMP processing + */ +err_t +igmp_start(struct netif *netif) +{ + struct igmp_group *group; + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: starting IGMP processing on if %p\n", (void *)netif)); + + group = igmp_lookup_group(netif, &allsystems); + + if (group != NULL) { + group->group_state = IGMP_GROUP_IDLE_MEMBER; + group->use++; + + /* Allow the igmp messages at the MAC level */ + if (netif->igmp_mac_filter != NULL) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_start: igmp_mac_filter(ADD ")); + ip4_addr_debug_print_val(IGMP_DEBUG, allsystems); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif)); + netif->igmp_mac_filter(netif, &allsystems, NETIF_ADD_MAC_FILTER); + } + + return ERR_OK; + } + + return ERR_MEM; +} + +/** + * Stop IGMP processing on interface + * + * @param netif network interface on which stop IGMP processing + */ +err_t +igmp_stop(struct netif *netif) +{ + struct igmp_group *group = netif_igmp_data(netif); + + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, NULL); + + while (group != NULL) { + struct igmp_group *next = group->next; /* avoid use-after-free below */ + + /* disable the group at the MAC level */ + if (netif->igmp_mac_filter != NULL) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_stop: igmp_mac_filter(DEL ")); + ip4_addr_debug_print_val(IGMP_DEBUG, group->group_address); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif)); + netif->igmp_mac_filter(netif, &(group->group_address), NETIF_DEL_MAC_FILTER); + } + + /* free group */ + memp_free(MEMP_IGMP_GROUP, group); + + /* move to "next" */ + group = next; + } + return ERR_OK; +} + +/** + * Report IGMP memberships for this interface + * + * @param netif network interface on which report IGMP memberships + */ +void +igmp_report_groups(struct netif *netif) +{ + struct igmp_group *group = netif_igmp_data(netif); + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_report_groups: sending IGMP reports on if %p\n", (void *)netif)); + + /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */ + if (group != NULL) { + group = group->next; + } + + while (group != NULL) { + igmp_delaying_member(group, IGMP_JOIN_DELAYING_MEMBER_TMR); + group = group->next; + } +} + +/** + * Search for a group in the netif's igmp group list + * + * @param ifp the network interface for which to look + * @param addr the group ip address to search for + * @return a struct igmp_group* if the group has been found, + * NULL if the group wasn't found. + */ +struct igmp_group * +igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr) +{ + struct igmp_group *group = netif_igmp_data(ifp); + + while (group != NULL) { + if (ip4_addr_cmp(&(group->group_address), addr)) { + return group; + } + group = group->next; + } + + /* to be clearer, we return NULL here instead of + * 'group' (which is also NULL at this point). + */ + return NULL; +} + +/** + * Search for a specific igmp group and create a new one if not found- + * + * @param ifp the network interface for which to look + * @param addr the group ip address to search + * @return a struct igmp_group*, + * NULL on memory error. + */ +static struct igmp_group * +igmp_lookup_group(struct netif *ifp, const ip4_addr_t *addr) +{ + struct igmp_group *group; + struct igmp_group *list_head = netif_igmp_data(ifp); + + /* Search if the group already exists */ + group = igmp_lookfor_group(ifp, addr); + if (group != NULL) { + /* Group already exists. */ + return group; + } + + /* Group doesn't exist yet, create a new one */ + group = (struct igmp_group *)memp_malloc(MEMP_IGMP_GROUP); + if (group != NULL) { + ip4_addr_set(&(group->group_address), addr); + group->timer = 0; /* Not running */ + group->group_state = IGMP_GROUP_NON_MEMBER; + group->last_reporter_flag = 0; + group->use = 0; + + /* Ensure allsystems group is always first in list */ + if (list_head == NULL) { + /* this is the first entry in linked list */ + LWIP_ASSERT("igmp_lookup_group: first group must be allsystems", + (ip4_addr_cmp(addr, &allsystems) != 0)); + group->next = NULL; + netif_set_client_data(ifp, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, group); + } else { + /* append _after_ first entry */ + LWIP_ASSERT("igmp_lookup_group: all except first group must not be allsystems", + (ip4_addr_cmp(addr, &allsystems) == 0)); + group->next = list_head->next; + list_head->next = group; + } + } + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_lookup_group: %sallocated a new group with address ", (group ? "" : "impossible to "))); + ip4_addr_debug_print(IGMP_DEBUG, addr); + LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void *)ifp)); + + return group; +} + +/** + * Remove a group from netif's igmp group list, but don't free it yet + * + * @param group the group to remove from the netif's igmp group list + * @return ERR_OK if group was removed from the list, an err_t otherwise + */ +static err_t +igmp_remove_group(struct netif *netif, struct igmp_group *group) +{ + err_t err = ERR_OK; + struct igmp_group *tmp_group; + + /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */ + for (tmp_group = netif_igmp_data(netif); tmp_group != NULL; tmp_group = tmp_group->next) { + if (tmp_group->next == group) { + tmp_group->next = group->next; + break; + } + } + /* Group not found in netif's igmp group list */ + if (tmp_group == NULL) { + err = ERR_ARG; + } + + return err; +} + +/** + * Called from ip_input() if a new IGMP packet is received. + * + * @param p received igmp packet, p->payload pointing to the igmp header + * @param inp network interface on which the packet was received + * @param dest destination ip address of the igmp packet + */ +void +igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest) +{ + struct igmp_msg *igmp; + struct igmp_group *group; + struct igmp_group *groupref; + + IGMP_STATS_INC(igmp.recv); + + /* Note that the length CAN be greater than 8 but only 8 are used - All are included in the checksum */ + if (p->len < IGMP_MINLEN) { + pbuf_free(p); + IGMP_STATS_INC(igmp.lenerr); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: length error\n")); + return; + } + + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: message from ")); + ip4_addr_debug_print_val(IGMP_DEBUG, ip4_current_header()->src); + LWIP_DEBUGF(IGMP_DEBUG, (" to address ")); + ip4_addr_debug_print_val(IGMP_DEBUG, ip4_current_header()->dest); + LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void *)inp)); + + /* Now calculate and check the checksum */ + igmp = (struct igmp_msg *)p->payload; + if (inet_chksum(igmp, p->len)) { + pbuf_free(p); + IGMP_STATS_INC(igmp.chkerr); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: checksum error\n")); + return; + } + + /* Packet is ok so find an existing group */ + group = igmp_lookfor_group(inp, dest); /* use the destination IP address of incoming packet */ + + /* If group can be found or create... */ + if (!group) { + pbuf_free(p); + IGMP_STATS_INC(igmp.drop); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP frame not for us\n")); + return; + } + + /* NOW ACT ON THE INCOMING MESSAGE TYPE... */ + switch (igmp->igmp_msgtype) { + case IGMP_MEMB_QUERY: + /* IGMP_MEMB_QUERY to the "all systems" address ? */ + if ((ip4_addr_cmp(dest, &allsystems)) && ip4_addr_isany(&igmp->igmp_group_address)) { + /* THIS IS THE GENERAL QUERY */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: General IGMP_MEMB_QUERY on \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); + + if (igmp->igmp_maxresp == 0) { + IGMP_STATS_INC(igmp.rx_v1); + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: got an all hosts query with time== 0 - this is V1 and not implemented - treat as v2\n")); + igmp->igmp_maxresp = IGMP_V1_DELAYING_MEMBER_TMR; + } else { + IGMP_STATS_INC(igmp.rx_general); + } + + groupref = netif_igmp_data(inp); + + /* Do not send messages on the all systems group address! */ + /* Skip the first group in the list, it is always the allsystems group added in igmp_start() */ + if (groupref != NULL) { + groupref = groupref->next; + } + + while (groupref) { + igmp_delaying_member(groupref, igmp->igmp_maxresp); + groupref = groupref->next; + } + } else { + /* IGMP_MEMB_QUERY to a specific group ? */ + if (!ip4_addr_isany(&igmp->igmp_group_address)) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_MEMB_QUERY to a specific group ")); + ip4_addr_debug_print_val(IGMP_DEBUG, igmp->igmp_group_address); + if (ip4_addr_cmp(dest, &allsystems)) { + ip4_addr_t groupaddr; + LWIP_DEBUGF(IGMP_DEBUG, (" using \"ALL SYSTEMS\" address (224.0.0.1) [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); + /* we first need to re-look for the group since we used dest last time */ + ip4_addr_copy(groupaddr, igmp->igmp_group_address); + group = igmp_lookfor_group(inp, &groupaddr); + } else { + LWIP_DEBUGF(IGMP_DEBUG, (" with the group address as destination [igmp_maxresp=%i]\n", (int)(igmp->igmp_maxresp))); + } + + if (group != NULL) { + IGMP_STATS_INC(igmp.rx_group); + igmp_delaying_member(group, igmp->igmp_maxresp); + } else { + IGMP_STATS_INC(igmp.drop); + } + } else { + IGMP_STATS_INC(igmp.proterr); + } + } + break; + case IGMP_V2_MEMB_REPORT: + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: IGMP_V2_MEMB_REPORT\n")); + IGMP_STATS_INC(igmp.rx_report); + if (group->group_state == IGMP_GROUP_DELAYING_MEMBER) { + /* This is on a specific group we have already looked up */ + group->timer = 0; /* stopped */ + group->group_state = IGMP_GROUP_IDLE_MEMBER; + group->last_reporter_flag = 0; + } + break; + default: + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_input: unexpected msg %d in state %d on group %p on if %p\n", + igmp->igmp_msgtype, group->group_state, (void *)&group, (void *)inp)); + IGMP_STATS_INC(igmp.proterr); + break; + } + + pbuf_free(p); + return; +} + +/** + * @ingroup igmp + * Join a group on one network interface. + * + * @param ifaddr ip address of the network interface which should join a new group + * @param groupaddr the ip address of the group which to join + * @return ERR_OK if group was joined on the netif(s), an err_t otherwise + */ +err_t +igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr) +{ + err_t err = ERR_VAL; /* no matching interface */ + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + + /* make sure it is multicast address */ + LWIP_ERROR("igmp_joingroup: attempt to join non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); + LWIP_ERROR("igmp_joingroup: attempt to join allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); + + /* loop through netif's */ + NETIF_FOREACH(netif) { + /* Should we join this interface ? */ + if ((netif->flags & NETIF_FLAG_IGMP) && ((ip4_addr_isany(ifaddr) || ip4_addr_cmp(netif_ip4_addr(netif), ifaddr)))) { + err = igmp_joingroup_netif(netif, groupaddr); + if (err != ERR_OK) { + /* Return an error even if some network interfaces are joined */ + /** @todo undo any other netif already joined */ + return err; + } + } + } + + return err; +} + +/** + * @ingroup igmp + * Join a group on one network interface. + * + * @param netif the network interface which should join a new group + * @param groupaddr the ip address of the group which to join + * @return ERR_OK if group was joined on the netif, an err_t otherwise + */ +err_t +igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr) +{ + struct igmp_group *group; + + LWIP_ASSERT_CORE_LOCKED(); + + /* make sure it is multicast address */ + LWIP_ERROR("igmp_joingroup_netif: attempt to join non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); + LWIP_ERROR("igmp_joingroup_netif: attempt to join allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); + + /* make sure it is an igmp-enabled netif */ + LWIP_ERROR("igmp_joingroup_netif: attempt to join on non-IGMP netif", netif->flags & NETIF_FLAG_IGMP, return ERR_VAL;); + + /* find group or create a new one if not found */ + group = igmp_lookup_group(netif, groupaddr); + + if (group != NULL) { + /* This should create a new group, check the state to make sure */ + if (group->group_state != IGMP_GROUP_NON_MEMBER) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: join to group not in state IGMP_GROUP_NON_MEMBER\n")); + } else { + /* OK - it was new group */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: join to new group: ")); + ip4_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, ("\n")); + + /* If first use of the group, allow the group at the MAC level */ + if ((group->use == 0) && (netif->igmp_mac_filter != NULL)) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: igmp_mac_filter(ADD ")); + ip4_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif)); + netif->igmp_mac_filter(netif, groupaddr, NETIF_ADD_MAC_FILTER); + } + + IGMP_STATS_INC(igmp.tx_join); + igmp_send(netif, group, IGMP_V2_MEMB_REPORT); + + igmp_start_timer(group, IGMP_JOIN_DELAYING_MEMBER_TMR); + + /* Need to work out where this timer comes from */ + group->group_state = IGMP_GROUP_DELAYING_MEMBER; + } + /* Increment group use */ + group->use++; + /* Join on this interface */ + return ERR_OK; + } else { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_joingroup_netif: Not enough memory to join to group\n")); + return ERR_MEM; + } +} + +/** + * @ingroup igmp + * Leave a group on one network interface. + * + * @param ifaddr ip address of the network interface which should leave a group + * @param groupaddr the ip address of the group which to leave + * @return ERR_OK if group was left on the netif(s), an err_t otherwise + */ +err_t +igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr) +{ + err_t err = ERR_VAL; /* no matching interface */ + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + + /* make sure it is multicast address */ + LWIP_ERROR("igmp_leavegroup: attempt to leave non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); + LWIP_ERROR("igmp_leavegroup: attempt to leave allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); + + /* loop through netif's */ + NETIF_FOREACH(netif) { + /* Should we leave this interface ? */ + if ((netif->flags & NETIF_FLAG_IGMP) && ((ip4_addr_isany(ifaddr) || ip4_addr_cmp(netif_ip4_addr(netif), ifaddr)))) { + err_t res = igmp_leavegroup_netif(netif, groupaddr); + if (err != ERR_OK) { + /* Store this result if we have not yet gotten a success */ + err = res; + } + } + } + + return err; +} + +/** + * @ingroup igmp + * Leave a group on one network interface. + * + * @param netif the network interface which should leave a group + * @param groupaddr the ip address of the group which to leave + * @return ERR_OK if group was left on the netif, an err_t otherwise + */ +err_t +igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr) +{ + struct igmp_group *group; + + LWIP_ASSERT_CORE_LOCKED(); + + /* make sure it is multicast address */ + LWIP_ERROR("igmp_leavegroup_netif: attempt to leave non-multicast address", ip4_addr_ismulticast(groupaddr), return ERR_VAL;); + LWIP_ERROR("igmp_leavegroup_netif: attempt to leave allsystems address", (!ip4_addr_cmp(groupaddr, &allsystems)), return ERR_VAL;); + + /* make sure it is an igmp-enabled netif */ + LWIP_ERROR("igmp_leavegroup_netif: attempt to leave on non-IGMP netif", netif->flags & NETIF_FLAG_IGMP, return ERR_VAL;); + + /* find group */ + group = igmp_lookfor_group(netif, groupaddr); + + if (group != NULL) { + /* Only send a leave if the flag is set according to the state diagram */ + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: Leaving group: ")); + ip4_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, ("\n")); + + /* If there is no other use of the group */ + if (group->use <= 1) { + /* Remove the group from the list */ + igmp_remove_group(netif, group); + + /* If we are the last reporter for this group */ + if (group->last_reporter_flag) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: sending leaving group\n")); + IGMP_STATS_INC(igmp.tx_leave); + igmp_send(netif, group, IGMP_LEAVE_GROUP); + } + + /* Disable the group at the MAC level */ + if (netif->igmp_mac_filter != NULL) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: igmp_mac_filter(DEL ")); + ip4_addr_debug_print(IGMP_DEBUG, groupaddr); + LWIP_DEBUGF(IGMP_DEBUG, (") on if %p\n", (void *)netif)); + netif->igmp_mac_filter(netif, groupaddr, NETIF_DEL_MAC_FILTER); + } + + /* Free group struct */ + memp_free(MEMP_IGMP_GROUP, group); + } else { + /* Decrement group use */ + group->use--; + } + return ERR_OK; + } else { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_leavegroup_netif: not member of group\n")); + return ERR_VAL; + } +} + +/** + * The igmp timer function (both for NO_SYS=1 and =0) + * Should be called every IGMP_TMR_INTERVAL milliseconds (100 ms is default). + */ +void +igmp_tmr(void) +{ + struct netif *netif; + + NETIF_FOREACH(netif) { + struct igmp_group *group = netif_igmp_data(netif); + + while (group != NULL) { + if (group->timer > 0) { + group->timer--; + if (group->timer == 0) { + igmp_timeout(netif, group); + } + } + group = group->next; + } + } +} + +/** + * Called if a timeout for one group is reached. + * Sends a report for this group. + * + * @param group an igmp_group for which a timeout is reached + */ +static void +igmp_timeout(struct netif *netif, struct igmp_group *group) +{ + /* If the state is IGMP_GROUP_DELAYING_MEMBER then we send a report for this group + (unless it is the allsystems group) */ + if ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && + (!(ip4_addr_cmp(&(group->group_address), &allsystems)))) { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_timeout: report membership for group with address ")); + ip4_addr_debug_print_val(IGMP_DEBUG, group->group_address); + LWIP_DEBUGF(IGMP_DEBUG, (" on if %p\n", (void *)netif)); + + group->group_state = IGMP_GROUP_IDLE_MEMBER; + + IGMP_STATS_INC(igmp.tx_report); + igmp_send(netif, group, IGMP_V2_MEMB_REPORT); + } +} + +/** + * Start a timer for an igmp group + * + * @param group the igmp_group for which to start a timer + * @param max_time the time in multiples of IGMP_TMR_INTERVAL (decrease with + * every call to igmp_tmr()) + */ +static void +igmp_start_timer(struct igmp_group *group, u8_t max_time) +{ +#ifdef LWIP_RAND + group->timer = (u16_t)(max_time > 2 ? (LWIP_RAND() % max_time) : 1); +#else /* LWIP_RAND */ + /* ATTENTION: use this only if absolutely necessary! */ + group->timer = max_time / 2; +#endif /* LWIP_RAND */ + + if (group->timer == 0) { + group->timer = 1; + } +} + +/** + * Delaying membership report for a group if necessary + * + * @param group the igmp_group for which "delaying" membership report + * @param maxresp query delay + */ +static void +igmp_delaying_member(struct igmp_group *group, u8_t maxresp) +{ + if ((group->group_state == IGMP_GROUP_IDLE_MEMBER) || + ((group->group_state == IGMP_GROUP_DELAYING_MEMBER) && + ((group->timer == 0) || (maxresp < group->timer)))) { + igmp_start_timer(group, maxresp); + group->group_state = IGMP_GROUP_DELAYING_MEMBER; + } +} + + +/** + * Sends an IP packet on a network interface. This function constructs the IP header + * and calculates the IP header checksum. If the source IP address is NULL, + * the IP address of the outgoing network interface is filled in as source address. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == LWIP_IP_HDRINCL, p already includes an + IP header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param netif the netif on which to send this packet + * @return ERR_OK if the packet was sent OK + * ERR_BUF if p doesn't have enough space for IP/LINK headers + * returns errors returned by netif->output + */ +static err_t +igmp_ip_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, struct netif *netif) +{ + /* This is the "router alert" option */ + u16_t ra[2]; + ra[0] = PP_HTONS(ROUTER_ALERT); + ra[1] = 0x0000; /* Router shall examine packet */ + IGMP_STATS_INC(igmp.xmit); + return ip4_output_if_opt(p, src, dest, IGMP_TTL, 0, IP_PROTO_IGMP, netif, ra, ROUTER_ALERTLEN); +} + +/** + * Send an igmp packet to a specific group. + * + * @param group the group to which to send the packet + * @param type the type of igmp packet to send + */ +static void +igmp_send(struct netif *netif, struct igmp_group *group, u8_t type) +{ + struct pbuf *p = NULL; + struct igmp_msg *igmp = NULL; + ip4_addr_t src = *IP4_ADDR_ANY4; + ip4_addr_t *dest = NULL; + + /* IP header + "router alert" option + IGMP header */ + p = pbuf_alloc(PBUF_TRANSPORT, IGMP_MINLEN, PBUF_RAM); + + if (p) { + igmp = (struct igmp_msg *)p->payload; + LWIP_ASSERT("igmp_send: check that first pbuf can hold struct igmp_msg", + (p->len >= sizeof(struct igmp_msg))); + ip4_addr_copy(src, *netif_ip4_addr(netif)); + + if (type == IGMP_V2_MEMB_REPORT) { + dest = &(group->group_address); + ip4_addr_copy(igmp->igmp_group_address, group->group_address); + group->last_reporter_flag = 1; /* Remember we were the last to report */ + } else { + if (type == IGMP_LEAVE_GROUP) { + dest = &allrouters; + ip4_addr_copy(igmp->igmp_group_address, group->group_address); + } + } + + if ((type == IGMP_V2_MEMB_REPORT) || (type == IGMP_LEAVE_GROUP)) { + igmp->igmp_msgtype = type; + igmp->igmp_maxresp = 0; + igmp->igmp_checksum = 0; + igmp->igmp_checksum = inet_chksum(igmp, IGMP_MINLEN); + + igmp_ip_output_if(p, &src, dest, netif); + } + + pbuf_free(p); + } else { + LWIP_DEBUGF(IGMP_DEBUG, ("igmp_send: not enough memory for igmp_send\n")); + IGMP_STATS_INC(igmp.memerr); + } +} + +#endif /* LWIP_IPV4 && LWIP_IGMP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c new file mode 100644 index 0000000..26c26a9 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4.c @@ -0,0 +1,1132 @@ +/** + * @file + * This is the IPv4 layer implementation for incoming and outgoing IP traffic. + * + * @see ip_frag.c + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 + +#include "lwip/ip.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/ip4_frag.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/igmp.h" +#include "lwip/priv/raw_priv.h" +#include "lwip/udp.h" +#include "lwip/priv/tcp_priv.h" +#include "lwip/autoip.h" +#include "lwip/stats.h" +#include "lwip/prot/iana.h" + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +/** Set this to 0 in the rare case of wanting to call an extra function to + * generate the IP checksum (in contrast to calculating it on-the-fly). */ +#ifndef LWIP_INLINE_IP_CHKSUM +#if LWIP_CHECKSUM_CTRL_PER_NETIF +#define LWIP_INLINE_IP_CHKSUM 0 +#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */ +#define LWIP_INLINE_IP_CHKSUM 1 +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ +#endif + +#if LWIP_INLINE_IP_CHKSUM && CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP_INLINE 1 +#else +#define CHECKSUM_GEN_IP_INLINE 0 +#endif + +#if LWIP_DHCP || defined(LWIP_IP_ACCEPT_UDP_PORT) +#define IP_ACCEPT_LINK_LAYER_ADDRESSING 1 + +/** Some defines for DHCP to let link-layer-addressed packets through while the + * netif is down. + * To use this in your own application/protocol, define LWIP_IP_ACCEPT_UDP_PORT(port) + * to return 1 if the port is accepted and 0 if the port is not accepted. + */ +#if LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) +/* accept DHCP client port and custom port */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (((port) == PP_NTOHS(LWIP_IANA_PORT_DHCP_CLIENT)) \ + || (LWIP_IP_ACCEPT_UDP_PORT(port))) +#elif defined(LWIP_IP_ACCEPT_UDP_PORT) /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ +/* accept custom port only */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) (LWIP_IP_ACCEPT_UDP_PORT(port)) +#else /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ +/* accept DHCP client port only */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(port) ((port) == PP_NTOHS(LWIP_IANA_PORT_DHCP_CLIENT)) +#endif /* LWIP_DHCP && defined(LWIP_IP_ACCEPT_UDP_PORT) */ + +#else /* LWIP_DHCP */ +#define IP_ACCEPT_LINK_LAYER_ADDRESSING 0 +#endif /* LWIP_DHCP */ + +/** The IP header ID of the next outgoing IP packet */ +static u16_t ip_id; + +#if LWIP_MULTICAST_TX_OPTIONS +/** The default netif used for multicast */ +static struct netif *ip4_default_multicast_netif; + +/** + * @ingroup ip4 + * Set a default netif for IPv4 multicast. */ +void +ip4_set_default_multicast_netif(struct netif *default_multicast_netif) +{ + ip4_default_multicast_netif = default_multicast_netif; +} +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + +#ifdef LWIP_HOOK_IP4_ROUTE_SRC +/** + * Source based IPv4 routing must be fully implemented in + * LWIP_HOOK_IP4_ROUTE_SRC(). This function only provides the parameters. + */ +struct netif * +ip4_route_src(const ip4_addr_t *src, const ip4_addr_t *dest) +{ + if (src != NULL) { + /* when src==NULL, the hook is called from ip4_route(dest) */ + struct netif *netif = LWIP_HOOK_IP4_ROUTE_SRC(src, dest); + if (netif != NULL) { + return netif; + } + } + return ip4_route(dest); +} +#endif /* LWIP_HOOK_IP4_ROUTE_SRC */ + +/** + * Finds the appropriate network interface for a given IP address. It + * searches the list of network interfaces linearly. A match is found + * if the masked IP address of the network interface equals the masked + * IP address given to the function. + * + * @param dest the destination IP address for which to find the route + * @return the netif on which to send to reach dest + */ +struct netif * +ip4_route(const ip4_addr_t *dest) +{ +#if !LWIP_SINGLE_NETIF + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_MULTICAST_TX_OPTIONS + /* Use administratively selected interface for multicast by default */ + if (ip4_addr_ismulticast(dest) && ip4_default_multicast_netif) { + return ip4_default_multicast_netif; + } +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + + /* bug #54569: in case LWIP_SINGLE_NETIF=1 and LWIP_DEBUGF() disabled, the following loop is optimized away */ + LWIP_UNUSED_ARG(dest); + + /* iterate through netifs */ + NETIF_FOREACH(netif) { + /* is the netif up, does it have a link and a valid address? */ + if (netif_is_up(netif) && netif_is_link_up(netif) && !ip4_addr_isany_val(*netif_ip4_addr(netif))) { + /* network mask matches? */ + if (ip4_addr_netcmp(dest, netif_ip4_addr(netif), netif_ip4_netmask(netif))) { + /* return netif on which to forward IP packet */ + return netif; + } + /* gateway matches on a non broadcast interface? (i.e. peer in a point to point interface) */ + if (((netif->flags & NETIF_FLAG_BROADCAST) == 0) && ip4_addr_cmp(dest, netif_ip4_gw(netif))) { + /* return netif on which to forward IP packet */ + return netif; + } + } + } + +#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF + /* loopif is disabled, looopback traffic is passed through any netif */ + if (ip4_addr_isloopback(dest)) { + /* don't check for link on loopback traffic */ + if (netif_default != NULL && netif_is_up(netif_default)) { + return netif_default; + } + /* default netif is not up, just use any netif for loopback traffic */ + NETIF_FOREACH(netif) { + if (netif_is_up(netif)) { + return netif; + } + } + return NULL; + } +#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ + +#ifdef LWIP_HOOK_IP4_ROUTE_SRC + netif = LWIP_HOOK_IP4_ROUTE_SRC(NULL, dest); + if (netif != NULL) { + return netif; + } +#elif defined(LWIP_HOOK_IP4_ROUTE) + netif = LWIP_HOOK_IP4_ROUTE(dest); + if (netif != NULL) { + return netif; + } +#endif +#endif /* !LWIP_SINGLE_NETIF */ + + if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default) || + ip4_addr_isany_val(*netif_ip4_addr(netif_default)) || ip4_addr_isloopback(dest)) { + /* No matching netif found and default netif is not usable. + If this is not good enough for you, use LWIP_HOOK_IP4_ROUTE() */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_route: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + MIB2_STATS_INC(mib2.ipoutnoroutes); + return NULL; + } + + return netif_default; +} + +#if IP_FORWARD +/** + * Determine whether an IP address is in a reserved set of addresses + * that may not be forwarded, or whether datagrams to that destination + * may be forwarded. + * @param p the packet to forward + * @return 1: can forward 0: discard + */ +static int +ip4_canforward(struct pbuf *p) +{ + u32_t addr = lwip_htonl(ip4_addr_get_u32(ip4_current_dest_addr())); + +#ifdef LWIP_HOOK_IP4_CANFORWARD + int ret = LWIP_HOOK_IP4_CANFORWARD(p, addr); + if (ret >= 0) { + return ret; + } +#endif /* LWIP_HOOK_IP4_CANFORWARD */ + + if (p->flags & PBUF_FLAG_LLBCAST) { + /* don't route link-layer broadcasts */ + return 0; + } + if ((p->flags & PBUF_FLAG_LLMCAST) || IP_MULTICAST(addr)) { + /* don't route link-layer multicasts (use LWIP_HOOK_IP4_CANFORWARD instead) */ + return 0; + } + if (IP_EXPERIMENTAL(addr)) { + return 0; + } + if (IP_CLASSA(addr)) { + u32_t net = addr & IP_CLASSA_NET; + if ((net == 0) || (net == ((u32_t)IP_LOOPBACKNET << IP_CLASSA_NSHIFT))) { + /* don't route loopback packets */ + return 0; + } + } + return 1; +} + +/** + * Forwards an IP packet. It finds an appropriate route for the + * packet, decrements the TTL value of the packet, adjusts the + * checksum and outputs the packet on the appropriate interface. + * + * @param p the packet to forward (p->payload points to IP header) + * @param iphdr the IP header of the input packet + * @param inp the netif on which this packet was received + */ +static void +ip4_forward(struct pbuf *p, struct ip_hdr *iphdr, struct netif *inp) +{ + struct netif *netif; + + PERF_START; + LWIP_UNUSED_ARG(inp); + + if (!ip4_canforward(p)) { + goto return_noroute; + } + + /* RFC3927 2.7: do not forward link-local addresses */ + if (ip4_addr_islinklocal(ip4_current_dest_addr())) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: not forwarding LLA %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()), + ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr()))); + goto return_noroute; + } + + /* Find network interface where to forward this IP packet to. */ + netif = ip4_route_src(ip4_current_src_addr(), ip4_current_dest_addr()); + if (netif == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: no forwarding route for %"U16_F".%"U16_F".%"U16_F".%"U16_F" found\n", + ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()), + ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr()))); + /* @todo: send ICMP_DUR_NET? */ + goto return_noroute; + } +#if !IP_FORWARD_ALLOW_TX_ON_RX_NETIF + /* Do not forward packets onto the same network interface on which + * they arrived. */ + if (netif == inp) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: not bouncing packets back on incoming interface.\n")); + goto return_noroute; + } +#endif /* IP_FORWARD_ALLOW_TX_ON_RX_NETIF */ + + /* decrement TTL */ + IPH_TTL_SET(iphdr, IPH_TTL(iphdr) - 1); + /* send ICMP if TTL == 0 */ + if (IPH_TTL(iphdr) == 0) { + MIB2_STATS_INC(mib2.ipinhdrerrors); +#if LWIP_ICMP + /* Don't send ICMP messages in response to ICMP messages */ + if (IPH_PROTO(iphdr) != IP_PROTO_ICMP) { + icmp_time_exceeded(p, ICMP_TE_TTL); + } +#endif /* LWIP_ICMP */ + return; + } + + /* Incrementally update the IP checksum. */ + if (IPH_CHKSUM(iphdr) >= PP_HTONS(0xffffU - 0x100)) { + IPH_CHKSUM_SET(iphdr, (u16_t)(IPH_CHKSUM(iphdr) + PP_HTONS(0x100) + 1)); + } else { + IPH_CHKSUM_SET(iphdr, (u16_t)(IPH_CHKSUM(iphdr) + PP_HTONS(0x100))); + } + + LWIP_DEBUGF(IP_DEBUG, ("ip4_forward: forwarding packet to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(ip4_current_dest_addr()), ip4_addr2_16(ip4_current_dest_addr()), + ip4_addr3_16(ip4_current_dest_addr()), ip4_addr4_16(ip4_current_dest_addr()))); + + IP_STATS_INC(ip.fw); + MIB2_STATS_INC(mib2.ipforwdatagrams); + IP_STATS_INC(ip.xmit); + + PERF_STOP("ip4_forward"); + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif->mtu && (p->tot_len > netif->mtu)) { + if ((IPH_OFFSET(iphdr) & PP_NTOHS(IP_DF)) == 0) { +#if IP_FRAG + ip4_frag(p, netif, ip4_current_dest_addr()); +#else /* IP_FRAG */ + /* @todo: send ICMP Destination Unreachable code 13 "Communication administratively prohibited"? */ +#endif /* IP_FRAG */ + } else { +#if LWIP_ICMP + /* send ICMP Destination Unreachable code 4: "Fragmentation Needed and DF Set" */ + icmp_dest_unreach(p, ICMP_DUR_FRAG); +#endif /* LWIP_ICMP */ + } + return; + } + /* transmit pbuf on chosen interface */ + netif->output(netif, p, ip4_current_dest_addr()); + return; +return_noroute: + MIB2_STATS_INC(mib2.ipoutnoroutes); +} +#endif /* IP_FORWARD */ + +/** Return true if the current input packet should be accepted on this netif */ +static int +ip4_input_accept(struct netif *netif) +{ + LWIP_DEBUGF(IP_DEBUG, ("ip_input: iphdr->dest 0x%"X32_F" netif->ip_addr 0x%"X32_F" (0x%"X32_F", 0x%"X32_F", 0x%"X32_F")\n", + ip4_addr_get_u32(ip4_current_dest_addr()), ip4_addr_get_u32(netif_ip4_addr(netif)), + ip4_addr_get_u32(ip4_current_dest_addr()) & ip4_addr_get_u32(netif_ip4_netmask(netif)), + ip4_addr_get_u32(netif_ip4_addr(netif)) & ip4_addr_get_u32(netif_ip4_netmask(netif)), + ip4_addr_get_u32(ip4_current_dest_addr()) & ~ip4_addr_get_u32(netif_ip4_netmask(netif)))); + + /* interface is up and configured? */ + if ((netif_is_up(netif)) && (!ip4_addr_isany_val(*netif_ip4_addr(netif)))) { + /* unicast to this interface address? */ + if (ip4_addr_cmp(ip4_current_dest_addr(), netif_ip4_addr(netif)) || + /* or broadcast on this interface network address? */ + ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) +#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF + || (ip4_addr_get_u32(ip4_current_dest_addr()) == PP_HTONL(IPADDR_LOOPBACK)) +#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ + ) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* accept on this netif */ + return 1; + } +#if LWIP_AUTOIP + /* connections to link-local addresses must persist after changing + the netif's address (RFC3927 ch. 1.9) */ + if (autoip_accept_packet(netif, ip4_current_dest_addr())) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: LLA packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + /* accept on this netif */ + return 1; + } +#endif /* LWIP_AUTOIP */ + } + return 0; +} + +/** + * This function is called by the network interface device driver when + * an IP packet is received. The function does the basic checks of the + * IP header such as packet size being at least larger than the header + * size etc. If the packet was not destined for us, the packet is + * forwarded (using ip_forward). The IP checksum is always checked. + * + * Finally, the packet is sent to the upper layer protocol input function. + * + * @param p the received IP packet (p->payload points to IP header) + * @param inp the netif on which this packet was received + * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't + * processed, but currently always returns ERR_OK) + */ +err_t +ip4_input(struct pbuf *p, struct netif *inp) +{ + const struct ip_hdr *iphdr; + struct netif *netif; + u16_t iphdr_hlen; + u16_t iphdr_len; +#if IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP + int check_ip_src = 1; +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING || LWIP_IGMP */ +#if LWIP_RAW + raw_input_state_t raw_status; +#endif /* LWIP_RAW */ + + LWIP_ASSERT_CORE_LOCKED(); + + IP_STATS_INC(ip.recv); + MIB2_STATS_INC(mib2.ipinreceives); + + /* identify the IP header */ + iphdr = (struct ip_hdr *)p->payload; + if (IPH_V(iphdr) != 4) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IP packet dropped due to bad version number %"U16_F"\n", (u16_t)IPH_V(iphdr))); + ip4_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.err); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinhdrerrors); + return ERR_OK; + } + +#ifdef LWIP_HOOK_IP4_INPUT + if (LWIP_HOOK_IP4_INPUT(p, inp)) { + /* the packet has been eaten */ + return ERR_OK; + } +#endif + + /* obtain IP header length in bytes */ + iphdr_hlen = IPH_HL_BYTES(iphdr); + /* obtain ip length in bytes */ + iphdr_len = lwip_ntohs(IPH_LEN(iphdr)); + + /* Trim pbuf. This is especially required for packets < 60 bytes. */ + if (iphdr_len < p->tot_len) { + pbuf_realloc(p, iphdr_len); + } + + /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ + if ((iphdr_hlen > p->len) || (iphdr_len > p->tot_len) || (iphdr_hlen < IP_HLEN)) { + if (iphdr_hlen < IP_HLEN) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("ip4_input: short IP header (%"U16_F" bytes) received, IP packet dropped\n", iphdr_hlen)); + } + if (iphdr_hlen > p->len) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IP header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n", + iphdr_hlen, p->len)); + } + if (iphdr_len > p->tot_len) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IP (len %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", + iphdr_len, p->tot_len)); + } + /* free (drop) packet pbufs */ + pbuf_free(p); + IP_STATS_INC(ip.lenerr); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipindiscards); + return ERR_OK; + } + + /* verify checksum */ +#if CHECKSUM_CHECK_IP + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_IP) { + if (inet_chksum(iphdr, iphdr_hlen) != 0) { + + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("Checksum (0x%"X16_F") failed, IP packet dropped.\n", inet_chksum(iphdr, iphdr_hlen))); + ip4_debug_print(p); + pbuf_free(p); + IP_STATS_INC(ip.chkerr); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinhdrerrors); + return ERR_OK; + } + } +#endif + + /* copy IP addresses to aligned ip_addr_t */ + ip_addr_copy_from_ip4(ip_data.current_iphdr_dest, iphdr->dest); + ip_addr_copy_from_ip4(ip_data.current_iphdr_src, iphdr->src); + + /* match packet against an interface, i.e. is this packet for us? */ + if (ip4_addr_ismulticast(ip4_current_dest_addr())) { +#if LWIP_IGMP + if ((inp->flags & NETIF_FLAG_IGMP) && (igmp_lookfor_group(inp, ip4_current_dest_addr()))) { + /* IGMP snooping switches need 0.0.0.0 to be allowed as source address (RFC 4541) */ + ip4_addr_t allsystems; + IP4_ADDR(&allsystems, 224, 0, 0, 1); + if (ip4_addr_cmp(ip4_current_dest_addr(), &allsystems) && + ip4_addr_isany(ip4_current_src_addr())) { + check_ip_src = 0; + } + netif = inp; + } else { + netif = NULL; + } +#else /* LWIP_IGMP */ + if ((netif_is_up(inp)) && (!ip4_addr_isany_val(*netif_ip4_addr(inp)))) { + netif = inp; + } else { + netif = NULL; + } +#endif /* LWIP_IGMP */ + } else { + /* start trying with inp. if that's not acceptable, start walking the + list of configured netifs. */ + if (ip4_input_accept(inp)) { + netif = inp; + } else { + netif = NULL; +#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF + /* Packets sent to the loopback address must not be accepted on an + * interface that does not have the loopback address assigned to it, + * unless a non-loopback interface is used for loopback traffic. */ + if (!ip4_addr_isloopback(ip4_current_dest_addr())) +#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */ + { +#if !LWIP_SINGLE_NETIF + NETIF_FOREACH(netif) { + if (netif == inp) { + /* we checked that before already */ + continue; + } + if (ip4_input_accept(netif)) { + break; + } + } +#endif /* !LWIP_SINGLE_NETIF */ + } + } + } + +#if IP_ACCEPT_LINK_LAYER_ADDRESSING + /* Pass DHCP messages regardless of destination address. DHCP traffic is addressed + * using link layer addressing (such as Ethernet MAC) so we must not filter on IP. + * According to RFC 1542 section 3.1.1, referred by RFC 2131). + * + * If you want to accept private broadcast communication while a netif is down, + * define LWIP_IP_ACCEPT_UDP_PORT(dst_port), e.g.: + * + * #define LWIP_IP_ACCEPT_UDP_PORT(dst_port) ((dst_port) == PP_NTOHS(12345)) + */ + if (netif == NULL) { + /* remote port is DHCP server? */ + if (IPH_PROTO(iphdr) == IP_PROTO_UDP) { + const struct udp_hdr *udphdr = (const struct udp_hdr *)((const u8_t *)iphdr + iphdr_hlen); + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: UDP packet to DHCP client port %"U16_F"\n", + lwip_ntohs(udphdr->dest))); + if (IP_ACCEPT_LINK_LAYER_ADDRESSED_PORT(udphdr->dest)) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: DHCP packet accepted.\n")); + netif = inp; + check_ip_src = 0; + } + } + } +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + + /* broadcast or multicast packet source address? Compliant with RFC 1122: 3.2.1.3 */ +#if LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING + if (check_ip_src +#if IP_ACCEPT_LINK_LAYER_ADDRESSING + /* DHCP servers need 0.0.0.0 to be allowed as source address (RFC 1.1.2.2: 3.2.1.3/a) */ + && !ip4_addr_isany_val(*ip4_current_src_addr()) +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ + ) +#endif /* LWIP_IGMP || IP_ACCEPT_LINK_LAYER_ADDRESSING */ + { + if ((ip4_addr_isbroadcast(ip4_current_src_addr(), inp)) || + (ip4_addr_ismulticast(ip4_current_src_addr()))) { + /* packet source is not valid */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("ip4_input: packet source is not valid.\n")); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinaddrerrors); + MIB2_STATS_INC(mib2.ipindiscards); + return ERR_OK; + } + } + + /* packet not for us? */ + if (netif == NULL) { + /* packet not for us, route or discard */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_TRACE, ("ip4_input: packet not for us.\n")); +#if IP_FORWARD + /* non-broadcast packet? */ + if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), inp)) { + /* try to forward IP packet on (other) interfaces */ + ip4_forward(p, (struct ip_hdr *)p->payload, inp); + } else +#endif /* IP_FORWARD */ + { + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinaddrerrors); + MIB2_STATS_INC(mib2.ipindiscards); + } + pbuf_free(p); + return ERR_OK; + } + /* packet consists of multiple fragments? */ + if ((IPH_OFFSET(iphdr) & PP_HTONS(IP_OFFMASK | IP_MF)) != 0) { +#if IP_REASSEMBLY /* packet fragment reassembly code present? */ + LWIP_DEBUGF(IP_DEBUG, ("IP packet is a fragment (id=0x%04"X16_F" tot_len=%"U16_F" len=%"U16_F" MF=%"U16_F" offset=%"U16_F"), calling ip4_reass()\n", + lwip_ntohs(IPH_ID(iphdr)), p->tot_len, lwip_ntohs(IPH_LEN(iphdr)), (u16_t)!!(IPH_OFFSET(iphdr) & PP_HTONS(IP_MF)), (u16_t)((lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK) * 8))); + /* reassemble the packet*/ + p = ip4_reass(p); + /* packet not fully reassembled yet? */ + if (p == NULL) { + return ERR_OK; + } + iphdr = (const struct ip_hdr *)p->payload; +#else /* IP_REASSEMBLY == 0, no packet fragment reassembly code present */ + pbuf_free(p); + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since it was fragmented (0x%"X16_F") (while IP_REASSEMBLY == 0).\n", + lwip_ntohs(IPH_OFFSET(iphdr)))); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + MIB2_STATS_INC(mib2.ipinunknownprotos); + return ERR_OK; +#endif /* IP_REASSEMBLY */ + } + +#if IP_OPTIONS_ALLOWED == 0 /* no support for IP options in the IP header? */ + +#if LWIP_IGMP + /* there is an extra "router alert" option in IGMP messages which we allow for but do not police */ + if ((iphdr_hlen > IP_HLEN) && (IPH_PROTO(iphdr) != IP_PROTO_IGMP)) { +#else + if (iphdr_hlen > IP_HLEN) { +#endif /* LWIP_IGMP */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("IP packet dropped since there were IP options (while IP_OPTIONS_ALLOWED == 0).\n")); + pbuf_free(p); + IP_STATS_INC(ip.opterr); + IP_STATS_INC(ip.drop); + /* unsupported protocol feature */ + MIB2_STATS_INC(mib2.ipinunknownprotos); + return ERR_OK; + } +#endif /* IP_OPTIONS_ALLOWED == 0 */ + + /* send to upper layers */ + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: \n")); + ip4_debug_print(p); + LWIP_DEBUGF(IP_DEBUG, ("ip4_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); + + ip_data.current_netif = netif; + ip_data.current_input_netif = inp; + ip_data.current_ip4_header = iphdr; + ip_data.current_ip_header_tot_len = IPH_HL_BYTES(iphdr); + +#if LWIP_RAW + /* raw input did not eat the packet? */ + raw_status = raw_input(p, inp); + if (raw_status != RAW_INPUT_EATEN) +#endif /* LWIP_RAW */ + { + pbuf_remove_header(p, iphdr_hlen); /* Move to payload, no check necessary. */ + + switch (IPH_PROTO(iphdr)) { +#if LWIP_UDP + case IP_PROTO_UDP: +#if LWIP_UDPLITE + case IP_PROTO_UDPLITE: +#endif /* LWIP_UDPLITE */ + MIB2_STATS_INC(mib2.ipindelivers); + udp_input(p, inp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case IP_PROTO_TCP: + MIB2_STATS_INC(mib2.ipindelivers); + tcp_input(p, inp); + break; +#endif /* LWIP_TCP */ +#if LWIP_ICMP + case IP_PROTO_ICMP: + MIB2_STATS_INC(mib2.ipindelivers); + icmp_input(p, inp); + break; +#endif /* LWIP_ICMP */ +#if LWIP_IGMP + case IP_PROTO_IGMP: + igmp_input(p, inp, ip4_current_dest_addr()); + break; +#endif /* LWIP_IGMP */ + default: +#if LWIP_RAW + if (raw_status == RAW_INPUT_DELIVERED) { + MIB2_STATS_INC(mib2.ipindelivers); + } else +#endif /* LWIP_RAW */ + { +#if LWIP_ICMP + /* send ICMP destination protocol unreachable unless is was a broadcast */ + if (!ip4_addr_isbroadcast(ip4_current_dest_addr(), netif) && + !ip4_addr_ismulticast(ip4_current_dest_addr())) { + pbuf_header_force(p, (s16_t)iphdr_hlen); /* Move to ip header, no check necessary. */ + icmp_dest_unreach(p, ICMP_DUR_PROTO); + } +#endif /* LWIP_ICMP */ + + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("Unsupported transport protocol %"U16_F"\n", (u16_t)IPH_PROTO(iphdr))); + + IP_STATS_INC(ip.proterr); + IP_STATS_INC(ip.drop); + MIB2_STATS_INC(mib2.ipinunknownprotos); + } + pbuf_free(p); + break; + } + } + + /* @todo: this is not really necessary... */ + ip_data.current_netif = NULL; + ip_data.current_input_netif = NULL; + ip_data.current_ip4_header = NULL; + ip_data.current_ip_header_tot_len = 0; + ip4_addr_set_any(ip4_current_src_addr()); + ip4_addr_set_any(ip4_current_dest_addr()); + + return ERR_OK; +} + +/** + * Sends an IP packet on a network interface. This function constructs + * the IP header and calculates the IP header checksum. If the source + * IP address is NULL, the IP address of the outgoing network + * interface is filled in as source address. + * If the destination IP address is LWIP_IP_HDRINCL, p is assumed to already + * include an IP header and p->payload points to it instead of the data. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == LWIP_IP_HDRINCL, p already includes an + IP header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param ttl the TTL value to be set in the IP header + * @param tos the TOS value to be set in the IP header + * @param proto the PROTOCOL to be set in the IP header + * @param netif the netif on which to send this packet + * @return ERR_OK if the packet was sent OK + * ERR_BUF if p doesn't have enough space for IP/LINK headers + * returns errors returned by netif->output + * + * @note ip_id: RFC791 "some host may be able to simply use + * unique identifiers independent of destination" + */ +err_t +ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ +#if IP_OPTIONS_SEND + return ip4_output_if_opt(p, src, dest, ttl, tos, proto, netif, NULL, 0); +} + +/** + * Same as ip_output_if() but with the possibility to include IP options: + * + * @ param ip_options pointer to the IP options, copied into the IP header + * @ param optlen length of ip_options + */ +err_t +ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen) +{ +#endif /* IP_OPTIONS_SEND */ + const ip4_addr_t *src_used = src; + if (dest != LWIP_IP_HDRINCL) { + if (ip4_addr_isany(src)) { + src_used = netif_ip4_addr(netif); + } + } + +#if IP_OPTIONS_SEND + return ip4_output_if_opt_src(p, src_used, dest, ttl, tos, proto, netif, + ip_options, optlen); +#else /* IP_OPTIONS_SEND */ + return ip4_output_if_src(p, src_used, dest, ttl, tos, proto, netif); +#endif /* IP_OPTIONS_SEND */ +} + +/** + * Same as ip_output_if() but 'src' address is not replaced by netif address + * when it is 'any'. + */ +err_t +ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, + u8_t proto, struct netif *netif) +{ +#if IP_OPTIONS_SEND + return ip4_output_if_opt_src(p, src, dest, ttl, tos, proto, netif, NULL, 0); +} + +/** + * Same as ip_output_if_opt() but 'src' address is not replaced by netif address + * when it is 'any'. + */ +err_t +ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen) +{ +#endif /* IP_OPTIONS_SEND */ + struct ip_hdr *iphdr; + ip4_addr_t dest_addr; +#if CHECKSUM_GEN_IP_INLINE + u32_t chk_sum = 0; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + + MIB2_STATS_INC(mib2.ipoutrequests); + + /* Should the IP header be generated or is it already included in p? */ + if (dest != LWIP_IP_HDRINCL) { + u16_t ip_hlen = IP_HLEN; +#if IP_OPTIONS_SEND + u16_t optlen_aligned = 0; + if (optlen != 0) { +#if CHECKSUM_GEN_IP_INLINE + int i; +#endif /* CHECKSUM_GEN_IP_INLINE */ + if (optlen > (IP_HLEN_MAX - IP_HLEN)) { + /* optlen too long */ + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output_if_opt: optlen too long\n")); + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_VAL; + } + /* round up to a multiple of 4 */ + optlen_aligned = (u16_t)((optlen + 3) & ~3); + ip_hlen = (u16_t)(ip_hlen + optlen_aligned); + /* First write in the IP options */ + if (pbuf_add_header(p, optlen_aligned)) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output_if_opt: not enough room for IP options in pbuf\n")); + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_BUF; + } + MEMCPY(p->payload, ip_options, optlen); + if (optlen < optlen_aligned) { + /* zero the remaining bytes */ + memset(((char *)p->payload) + optlen, 0, (size_t)(optlen_aligned - optlen)); + } +#if CHECKSUM_GEN_IP_INLINE + for (i = 0; i < optlen_aligned / 2; i++) { + chk_sum += ((u16_t *)p->payload)[i]; + } +#endif /* CHECKSUM_GEN_IP_INLINE */ + } +#endif /* IP_OPTIONS_SEND */ + /* generate IP header */ + if (pbuf_add_header(p, IP_HLEN)) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: not enough room for IP header in pbuf\n")); + + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_BUF; + } + + iphdr = (struct ip_hdr *)p->payload; + LWIP_ASSERT("check that first pbuf can hold struct ip_hdr", + (p->len >= sizeof(struct ip_hdr))); + + IPH_TTL_SET(iphdr, ttl); + IPH_PROTO_SET(iphdr, proto); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += PP_NTOHS(proto | (ttl << 8)); +#endif /* CHECKSUM_GEN_IP_INLINE */ + + /* dest cannot be NULL here */ + ip4_addr_copy(iphdr->dest, *dest); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += ip4_addr_get_u32(&iphdr->dest) & 0xFFFF; + chk_sum += ip4_addr_get_u32(&iphdr->dest) >> 16; +#endif /* CHECKSUM_GEN_IP_INLINE */ + + IPH_VHL_SET(iphdr, 4, ip_hlen / 4); + IPH_TOS_SET(iphdr, tos); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += PP_NTOHS(tos | (iphdr->_v_hl << 8)); +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_LEN_SET(iphdr, lwip_htons(p->tot_len)); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_len; +#endif /* CHECKSUM_GEN_IP_INLINE */ + IPH_OFFSET_SET(iphdr, 0); + IPH_ID_SET(iphdr, lwip_htons(ip_id)); +#if CHECKSUM_GEN_IP_INLINE + chk_sum += iphdr->_id; +#endif /* CHECKSUM_GEN_IP_INLINE */ + ++ip_id; + + if (src == NULL) { + ip4_addr_copy(iphdr->src, *IP4_ADDR_ANY4); + } else { + /* src cannot be NULL here */ + ip4_addr_copy(iphdr->src, *src); + } + +#if CHECKSUM_GEN_IP_INLINE + chk_sum += ip4_addr_get_u32(&iphdr->src) & 0xFFFF; + chk_sum += ip4_addr_get_u32(&iphdr->src) >> 16; + chk_sum = (chk_sum >> 16) + (chk_sum & 0xFFFF); + chk_sum = (chk_sum >> 16) + chk_sum; + chk_sum = ~chk_sum; + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) { + iphdr->_chksum = (u16_t)chk_sum; /* network order */ + } +#if LWIP_CHECKSUM_CTRL_PER_NETIF + else { + IPH_CHKSUM_SET(iphdr, 0); + } +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/ +#else /* CHECKSUM_GEN_IP_INLINE */ + IPH_CHKSUM_SET(iphdr, 0); +#if CHECKSUM_GEN_IP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) { + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, ip_hlen)); + } +#endif /* CHECKSUM_GEN_IP */ +#endif /* CHECKSUM_GEN_IP_INLINE */ + } else { + /* IP header already included in p */ + if (p->len < IP_HLEN) { + LWIP_DEBUGF(IP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip4_output: LWIP_IP_HDRINCL but pbuf is too short\n")); + IP_STATS_INC(ip.err); + MIB2_STATS_INC(mib2.ipoutdiscards); + return ERR_BUF; + } + iphdr = (struct ip_hdr *)p->payload; + ip4_addr_copy(dest_addr, iphdr->dest); + dest = &dest_addr; + } + + IP_STATS_INC(ip.xmit); + + LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], (u16_t)netif->num)); + ip4_debug_print(p); + +#if ENABLE_LOOPBACK + if (ip4_addr_cmp(dest, netif_ip4_addr(netif)) +#if !LWIP_HAVE_LOOPIF + || ip4_addr_isloopback(dest) +#endif /* !LWIP_HAVE_LOOPIF */ + ) { + /* Packet to self, enqueue it for loopback */ + LWIP_DEBUGF(IP_DEBUG, ("netif_loop_output()")); + return netif_loop_output(netif, p); + } +#if LWIP_MULTICAST_TX_OPTIONS + if ((p->flags & PBUF_FLAG_MCASTLOOP) != 0) { + netif_loop_output(netif, p); + } +#endif /* LWIP_MULTICAST_TX_OPTIONS */ +#endif /* ENABLE_LOOPBACK */ +#if IP_FRAG + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif->mtu && (p->tot_len > netif->mtu)) { + return ip4_frag(p, netif, dest); + } +#endif /* IP_FRAG */ + + LWIP_DEBUGF(IP_DEBUG, ("ip4_output_if: call netif->output()\n")); + return netif->output(netif, p, dest); +} + +/** + * Simple interface to ip_output_if. It finds the outgoing network + * interface and calls upon ip_output_if to do the actual work. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == LWIP_IP_HDRINCL, p already includes an + IP header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param ttl the TTL value to be set in the IP header + * @param tos the TOS value to be set in the IP header + * @param proto the PROTOCOL to be set in the IP header + * + * @return ERR_RTE if no route is found + * see ip_output_if() for more return values + */ +err_t +ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto) +{ + struct netif *netif; + + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + + if ((netif = ip4_route_src(src, dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + return ERR_RTE; + } + + return ip4_output_if(p, src, dest, ttl, tos, proto, netif); +} + +#if LWIP_NETIF_USE_HINTS +/** Like ip_output, but takes and addr_hint pointer that is passed on to netif->addr_hint + * before calling ip_output_if. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == LWIP_IP_HDRINCL, p already includes an + IP header and p->payload points to that IP header) + * @param src the source IP address to send from (if src == IP4_ADDR_ANY, the + * IP address of the netif used to send is used as source address) + * @param dest the destination IP address to send the packet to + * @param ttl the TTL value to be set in the IP header + * @param tos the TOS value to be set in the IP header + * @param proto the PROTOCOL to be set in the IP header + * @param netif_hint netif output hint pointer set to netif->hint before + * calling ip_output_if() + * + * @return ERR_RTE if no route is found + * see ip_output_if() for more return values + */ +err_t +ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif_hint *netif_hint) +{ + struct netif *netif; + err_t err; + + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + + if ((netif = ip4_route_src(src, dest)) == NULL) { + LWIP_DEBUGF(IP_DEBUG, ("ip4_output: No route to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + ip4_addr1_16(dest), ip4_addr2_16(dest), ip4_addr3_16(dest), ip4_addr4_16(dest))); + IP_STATS_INC(ip.rterr); + return ERR_RTE; + } + + NETIF_SET_HINTS(netif, netif_hint); + err = ip4_output_if(p, src, dest, ttl, tos, proto, netif); + NETIF_RESET_HINTS(netif); + + return err; +} +#endif /* LWIP_NETIF_USE_HINTS*/ + +#if IP_DEBUG +/* Print an IP header by using LWIP_DEBUGF + * @param p an IP packet, p->payload pointing to the IP header + */ +void +ip4_debug_print(struct pbuf *p) +{ + struct ip_hdr *iphdr = (struct ip_hdr *)p->payload; + + LWIP_DEBUGF(IP_DEBUG, ("IP header:\n")); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("|%2"S16_F" |%2"S16_F" | 0x%02"X16_F" | %5"U16_F" | (v, hl, tos, len)\n", + (u16_t)IPH_V(iphdr), + (u16_t)IPH_HL(iphdr), + (u16_t)IPH_TOS(iphdr), + lwip_ntohs(IPH_LEN(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %5"U16_F" |%"U16_F"%"U16_F"%"U16_F"| %4"U16_F" | (id, flags, offset)\n", + lwip_ntohs(IPH_ID(iphdr)), + (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 15 & 1), + (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 14 & 1), + (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) >> 13 & 1), + (u16_t)(lwip_ntohs(IPH_OFFSET(iphdr)) & IP_OFFMASK))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | 0x%04"X16_F" | (ttl, proto, chksum)\n", + (u16_t)IPH_TTL(iphdr), + (u16_t)IPH_PROTO(iphdr), + lwip_ntohs(IPH_CHKSUM(iphdr)))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (src)\n", + ip4_addr1_16_val(iphdr->src), + ip4_addr2_16_val(iphdr->src), + ip4_addr3_16_val(iphdr->src), + ip4_addr4_16_val(iphdr->src))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP_DEBUG, ("| %3"U16_F" | %3"U16_F" | %3"U16_F" | %3"U16_F" | (dest)\n", + ip4_addr1_16_val(iphdr->dest), + ip4_addr2_16_val(iphdr->dest), + ip4_addr3_16_val(iphdr->dest), + ip4_addr4_16_val(iphdr->dest))); + LWIP_DEBUGF(IP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* IP_DEBUG */ + +#endif /* LWIP_IPV4 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c new file mode 100644 index 0000000..33204d1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_addr.c @@ -0,0 +1,321 @@ +/** + * @file + * This is the IPv4 address tools implementation. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 + +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +/* used by IP4_ADDR_ANY and IP_ADDR_BROADCAST in ip_addr.h */ +const ip_addr_t ip_addr_any = IPADDR4_INIT(IPADDR_ANY); +const ip_addr_t ip_addr_broadcast = IPADDR4_INIT(IPADDR_BROADCAST); + +/** + * Determine if an address is a broadcast address on a network interface + * + * @param addr address to be checked + * @param netif the network interface against which the address is checked + * @return returns non-zero if the address is a broadcast address + */ +u8_t +ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif) +{ + ip4_addr_t ipaddr; + ip4_addr_set_u32(&ipaddr, addr); + + /* all ones (broadcast) or all zeroes (old skool broadcast) */ + if ((~addr == IPADDR_ANY) || + (addr == IPADDR_ANY)) { + return 1; + /* no broadcast support on this network interface? */ + } else if ((netif->flags & NETIF_FLAG_BROADCAST) == 0) { + /* the given address cannot be a broadcast address + * nor can we check against any broadcast addresses */ + return 0; + /* address matches network interface address exactly? => no broadcast */ + } else if (addr == ip4_addr_get_u32(netif_ip4_addr(netif))) { + return 0; + /* on the same (sub) network... */ + } else if (ip4_addr_netcmp(&ipaddr, netif_ip4_addr(netif), netif_ip4_netmask(netif)) + /* ...and host identifier bits are all ones? =>... */ + && ((addr & ~ip4_addr_get_u32(netif_ip4_netmask(netif))) == + (IPADDR_BROADCAST & ~ip4_addr_get_u32(netif_ip4_netmask(netif))))) { + /* => network broadcast address */ + return 1; + } else { + return 0; + } +} + +/** Checks if a netmask is valid (starting with ones, then only zeros) + * + * @param netmask the IPv4 netmask to check (in network byte order!) + * @return 1 if the netmask is valid, 0 if it is not + */ +u8_t +ip4_addr_netmask_valid(u32_t netmask) +{ + u32_t mask; + u32_t nm_hostorder = lwip_htonl(netmask); + + /* first, check for the first zero */ + for (mask = 1UL << 31 ; mask != 0; mask >>= 1) { + if ((nm_hostorder & mask) == 0) { + break; + } + } + /* then check that there is no one */ + for (; mask != 0; mask >>= 1) { + if ((nm_hostorder & mask) != 0) { + /* there is a one after the first zero -> invalid */ + return 0; + } + } + /* no one after the first zero -> valid */ + return 1; +} + +/** + * Ascii internet address interpretation routine. + * The value returned is in network order. + * + * @param cp IP address in ascii representation (e.g. "127.0.0.1") + * @return ip address in network order + */ +u32_t +ipaddr_addr(const char *cp) +{ + ip4_addr_t val; + + if (ip4addr_aton(cp, &val)) { + return ip4_addr_get_u32(&val); + } + return (IPADDR_NONE); +} + +/** + * Check whether "cp" is a valid ascii representation + * of an Internet address and convert to a binary address. + * Returns 1 if the address is valid, 0 if not. + * This replaces inet_addr, the return value from which + * cannot distinguish between failure and a local broadcast address. + * + * @param cp IP address in ascii representation (e.g. "127.0.0.1") + * @param addr pointer to which to save the ip address in network order + * @return 1 if cp could be converted to addr, 0 on failure + */ +int +ip4addr_aton(const char *cp, ip4_addr_t *addr) +{ + u32_t val; + u8_t base; + char c; + u32_t parts[4]; + u32_t *pp = parts; + + c = *cp; + for (;;) { + /* + * Collect number up to ``.''. + * Values are specified as for C: + * 0x=hex, 0=octal, 1-9=decimal. + */ + if (!lwip_isdigit(c)) { + return 0; + } + val = 0; + base = 10; + if (c == '0') { + c = *++cp; + if (c == 'x' || c == 'X') { + base = 16; + c = *++cp; + } else { + base = 8; + } + } + for (;;) { + if (lwip_isdigit(c)) { + val = (val * base) + (u32_t)(c - '0'); + c = *++cp; + } else if (base == 16 && lwip_isxdigit(c)) { + val = (val << 4) | (u32_t)(c + 10 - (lwip_islower(c) ? 'a' : 'A')); + c = *++cp; + } else { + break; + } + } + if (c == '.') { + /* + * Internet format: + * a.b.c.d + * a.b.c (with c treated as 16 bits) + * a.b (with b treated as 24 bits) + */ + if (pp >= parts + 3) { + return 0; + } + *pp++ = val; + c = *++cp; + } else { + break; + } + } + /* + * Check for trailing characters. + */ + if (c != '\0' && !lwip_isspace(c)) { + return 0; + } + /* + * Concoct the address according to + * the number of parts specified. + */ + switch (pp - parts + 1) { + + case 0: + return 0; /* initial nondigit */ + + case 1: /* a -- 32 bits */ + break; + + case 2: /* a.b -- 8.24 bits */ + if (val > 0xffffffUL) { + return 0; + } + if (parts[0] > 0xff) { + return 0; + } + val |= parts[0] << 24; + break; + + case 3: /* a.b.c -- 8.8.16 bits */ + if (val > 0xffff) { + return 0; + } + if ((parts[0] > 0xff) || (parts[1] > 0xff)) { + return 0; + } + val |= (parts[0] << 24) | (parts[1] << 16); + break; + + case 4: /* a.b.c.d -- 8.8.8.8 bits */ + if (val > 0xff) { + return 0; + } + if ((parts[0] > 0xff) || (parts[1] > 0xff) || (parts[2] > 0xff)) { + return 0; + } + val |= (parts[0] << 24) | (parts[1] << 16) | (parts[2] << 8); + break; + default: + LWIP_ASSERT("unhandled", 0); + break; + } + if (addr) { + ip4_addr_set_u32(addr, lwip_htonl(val)); + } + return 1; +} + +/** + * Convert numeric IP address into decimal dotted ASCII representation. + * returns ptr to static buffer; not reentrant! + * + * @param addr ip address in network order to convert + * @return pointer to a global static (!) buffer that holds the ASCII + * representation of addr + */ +char * +ip4addr_ntoa(const ip4_addr_t *addr) +{ + static char str[IP4ADDR_STRLEN_MAX]; + return ip4addr_ntoa_r(addr, str, IP4ADDR_STRLEN_MAX); +} + +/** + * Same as ip4addr_ntoa, but reentrant since a user-supplied buffer is used. + * + * @param addr ip address in network order to convert + * @param buf target buffer where the string is stored + * @param buflen length of buf + * @return either pointer to buf which now holds the ASCII + * representation of addr or NULL if buf was too small + */ +char * +ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen) +{ + u32_t s_addr; + char inv[3]; + char *rp; + u8_t *ap; + u8_t rem; + u8_t n; + u8_t i; + int len = 0; + + s_addr = ip4_addr_get_u32(addr); + + rp = buf; + ap = (u8_t *)&s_addr; + for (n = 0; n < 4; n++) { + i = 0; + do { + rem = *ap % (u8_t)10; + *ap /= (u8_t)10; + inv[i++] = (char)('0' + rem); + } while (*ap); + while (i--) { + if (len++ >= buflen) { + return NULL; + } + *rp++ = inv[i]; + } + if (len++ >= buflen) { + return NULL; + } + *rp++ = '.'; + ap++; + } + *--rp = 0; + return buf; +} + +#endif /* LWIP_IPV4 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c b/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c new file mode 100644 index 0000000..a445530 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv4/ip4_frag.c @@ -0,0 +1,894 @@ +/** + * @file + * This is the IPv4 packet segmentation and reassembly implementation. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * Simon Goldschmidt + * original reassembly code by Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV4 + +#include "lwip/ip4_frag.h" +#include "lwip/def.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/stats.h" +#include "lwip/icmp.h" + +#include + +#if IP_REASSEMBLY +/** + * The IP reassembly code currently has the following limitations: + * - IP header options are not supported + * - fragments must not overlap (e.g. due to different routes), + * currently, overlapping or duplicate fragments are thrown away + * if IP_REASS_CHECK_OVERLAP=1 (the default)! + * + * @todo: work with IP header options + */ + +/** Setting this to 0, you can turn off checking the fragments for overlapping + * regions. The code gets a little smaller. Only use this if you know that + * overlapping won't occur on your network! */ +#ifndef IP_REASS_CHECK_OVERLAP +#define IP_REASS_CHECK_OVERLAP 1 +#endif /* IP_REASS_CHECK_OVERLAP */ + +/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is + * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller. + * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA + * is set to 1, so one datagram can be reassembled at a time, only. */ +#ifndef IP_REASS_FREE_OLDEST +#define IP_REASS_FREE_OLDEST 1 +#endif /* IP_REASS_FREE_OLDEST */ + +#define IP_REASS_FLAG_LASTFRAG 0x01 + +#define IP_REASS_VALIDATE_TELEGRAM_FINISHED 1 +#define IP_REASS_VALIDATE_PBUF_QUEUED 0 +#define IP_REASS_VALIDATE_PBUF_DROPPED -1 + +/** This is a helper struct which holds the starting + * offset and the ending offset of this fragment to + * easily chain the fragments. + * It has the same packing requirements as the IP header, since it replaces + * the IP header in memory in incoming fragments (after copying it) to keep + * track of the various fragments. (-> If the IP header doesn't need packing, + * this struct doesn't need packing, too.) + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip_reass_helper { + PACK_STRUCT_FIELD(struct pbuf *next_pbuf); + PACK_STRUCT_FIELD(u16_t start); + PACK_STRUCT_FIELD(u16_t end); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define IP_ADDRESSES_AND_ID_MATCH(iphdrA, iphdrB) \ + (ip4_addr_cmp(&(iphdrA)->src, &(iphdrB)->src) && \ + ip4_addr_cmp(&(iphdrA)->dest, &(iphdrB)->dest) && \ + IPH_ID(iphdrA) == IPH_ID(iphdrB)) ? 1 : 0 + +/* global variables */ +static struct ip_reassdata *reassdatagrams; +static u16_t ip_reass_pbufcount; + +/* function prototypes */ +static void ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev); +static int ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev); + +/** + * Reassembly timer base function + * for both NO_SYS == 0 and 1 (!). + * + * Should be called every 1000 msec (defined by IP_TMR_INTERVAL). + */ +void +ip_reass_tmr(void) +{ + struct ip_reassdata *r, *prev = NULL; + + r = reassdatagrams; + while (r != NULL) { + /* Decrement the timer. Once it reaches 0, + * clean up the incomplete fragment assembly */ + if (r->timer > 0) { + r->timer--; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer dec %"U16_F"\n", (u16_t)r->timer)); + prev = r; + r = r->next; + } else { + /* reassembly timed out */ + struct ip_reassdata *tmp; + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_tmr: timer timed out\n")); + tmp = r; + /* get the next pointer before freeing */ + r = r->next; + /* free the helper struct and all enqueued pbufs */ + ip_reass_free_complete_datagram(tmp, prev); + } + } +} + +/** + * Free a datagram (struct ip_reassdata) and all its pbufs. + * Updates the total count of enqueued pbufs (ip_reass_pbufcount), + * SNMP counters and sends an ICMP time exceeded packet. + * + * @param ipr datagram to free + * @param prev the previous datagram in the linked list + * @return the number of pbufs freed + */ +static int +ip_reass_free_complete_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + u16_t pbufs_freed = 0; + u16_t clen; + struct pbuf *p; + struct ip_reass_helper *iprh; + + LWIP_ASSERT("prev != ipr", prev != ipr); + if (prev != NULL) { + LWIP_ASSERT("prev->next == ipr", prev->next == ipr); + } + + MIB2_STATS_INC(mib2.ipreasmfails); +#if LWIP_ICMP + iprh = (struct ip_reass_helper *)ipr->p->payload; + if (iprh->start == 0) { + /* The first fragment was received, send ICMP time exceeded. */ + /* First, de-queue the first pbuf from r->p. */ + p = ipr->p; + ipr->p = iprh->next_pbuf; + /* Then, copy the original header into it. */ + SMEMCPY(p->payload, &ipr->iphdr, IP_HLEN); + icmp_time_exceeded(p, ICMP_TE_FRAG); + clen = pbuf_clen(p); + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + pbufs_freed = (u16_t)(pbufs_freed + clen); + pbuf_free(p); + } +#endif /* LWIP_ICMP */ + + /* First, free all received pbufs. The individual pbufs need to be released + separately as they have not yet been chained */ + p = ipr->p; + while (p != NULL) { + struct pbuf *pcur; + iprh = (struct ip_reass_helper *)p->payload; + pcur = p; + /* get the next pointer before freeing */ + p = iprh->next_pbuf; + clen = pbuf_clen(pcur); + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + pbufs_freed = (u16_t)(pbufs_freed + clen); + pbuf_free(pcur); + } + /* Then, unchain the struct ip_reassdata from the list and free it. */ + ip_reass_dequeue_datagram(ipr, prev); + LWIP_ASSERT("ip_reass_pbufcount >= pbufs_freed", ip_reass_pbufcount >= pbufs_freed); + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - pbufs_freed); + + return pbufs_freed; +} + +#if IP_REASS_FREE_OLDEST +/** + * Free the oldest datagram to make room for enqueueing new fragments. + * The datagram 'fraghdr' belongs to is not freed! + * + * @param fraghdr IP header of the current fragment + * @param pbufs_needed number of pbufs needed to enqueue + * (used for freeing other datagrams if not enough space) + * @return the number of pbufs freed + */ +static int +ip_reass_remove_oldest_datagram(struct ip_hdr *fraghdr, int pbufs_needed) +{ + /* @todo Can't we simply remove the last datagram in the + * linked list behind reassdatagrams? + */ + struct ip_reassdata *r, *oldest, *prev, *oldest_prev; + int pbufs_freed = 0, pbufs_freed_current; + int other_datagrams; + + /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, + * but don't free the datagram that 'fraghdr' belongs to! */ + do { + oldest = NULL; + prev = NULL; + oldest_prev = NULL; + other_datagrams = 0; + r = reassdatagrams; + while (r != NULL) { + if (!IP_ADDRESSES_AND_ID_MATCH(&r->iphdr, fraghdr)) { + /* Not the same datagram as fraghdr */ + other_datagrams++; + if (oldest == NULL) { + oldest = r; + oldest_prev = prev; + } else if (r->timer <= oldest->timer) { + /* older than the previous oldest */ + oldest = r; + oldest_prev = prev; + } + } + if (r->next != NULL) { + prev = r; + } + r = r->next; + } + if (oldest != NULL) { + pbufs_freed_current = ip_reass_free_complete_datagram(oldest, oldest_prev); + pbufs_freed += pbufs_freed_current; + } + } while ((pbufs_freed < pbufs_needed) && (other_datagrams > 1)); + return pbufs_freed; +} +#endif /* IP_REASS_FREE_OLDEST */ + +/** + * Enqueues a new fragment into the fragment queue + * @param fraghdr points to the new fragments IP hdr + * @param clen number of pbufs needed to enqueue (used for freeing other datagrams if not enough space) + * @return A pointer to the queue location into which the fragment was enqueued + */ +static struct ip_reassdata * +ip_reass_enqueue_new_datagram(struct ip_hdr *fraghdr, int clen) +{ + struct ip_reassdata *ipr; +#if ! IP_REASS_FREE_OLDEST + LWIP_UNUSED_ARG(clen); +#endif + + /* No matching previous fragment found, allocate a new reassdata struct */ + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + if (ipr == NULL) { +#if IP_REASS_FREE_OLDEST + if (ip_reass_remove_oldest_datagram(fraghdr, clen) >= clen) { + ipr = (struct ip_reassdata *)memp_malloc(MEMP_REASSDATA); + } + if (ipr == NULL) +#endif /* IP_REASS_FREE_OLDEST */ + { + IPFRAG_STATS_INC(ip_frag.memerr); + LWIP_DEBUGF(IP_REASS_DEBUG, ("Failed to alloc reassdata struct\n")); + return NULL; + } + } + memset(ipr, 0, sizeof(struct ip_reassdata)); + ipr->timer = IP_REASS_MAXAGE; + + /* enqueue the new structure to the front of the list */ + ipr->next = reassdatagrams; + reassdatagrams = ipr; + /* copy the ip header for later tests and input */ + /* @todo: no ip options supported? */ + SMEMCPY(&(ipr->iphdr), fraghdr, IP_HLEN); + return ipr; +} + +/** + * Dequeues a datagram from the datagram queue. Doesn't deallocate the pbufs. + * @param ipr points to the queue entry to dequeue + */ +static void +ip_reass_dequeue_datagram(struct ip_reassdata *ipr, struct ip_reassdata *prev) +{ + /* dequeue the reass struct */ + if (reassdatagrams == ipr) { + /* it was the first in the list */ + reassdatagrams = ipr->next; + } else { + /* it wasn't the first, so it must have a valid 'prev' */ + LWIP_ASSERT("sanity check linked list", prev != NULL); + prev->next = ipr->next; + } + + /* now we can free the ip_reassdata struct */ + memp_free(MEMP_REASSDATA, ipr); +} + +/** + * Chain a new pbuf into the pbuf list that composes the datagram. The pbuf list + * will grow over time as new pbufs are rx. + * Also checks that the datagram passes basic continuity checks (if the last + * fragment was received at least once). + * @param ipr points to the reassembly state + * @param new_p points to the pbuf for the current fragment + * @param is_last is 1 if this pbuf has MF==0 (ipr->flags not updated yet) + * @return see IP_REASS_VALIDATE_* defines + */ +static int +ip_reass_chain_frag_into_datagram_and_validate(struct ip_reassdata *ipr, struct pbuf *new_p, int is_last) +{ + struct ip_reass_helper *iprh, *iprh_tmp, *iprh_prev = NULL; + struct pbuf *q; + u16_t offset, len; + u8_t hlen; + struct ip_hdr *fraghdr; + int valid = 1; + + /* Extract length and fragment offset from current fragment */ + fraghdr = (struct ip_hdr *)new_p->payload; + len = lwip_ntohs(IPH_LEN(fraghdr)); + hlen = IPH_HL_BYTES(fraghdr); + if (hlen > len) { + /* invalid datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + } + len = (u16_t)(len - hlen); + offset = IPH_OFFSET_BYTES(fraghdr); + + /* overwrite the fragment's ip header from the pbuf with our helper struct, + * and setup the embedded helper structure. */ + /* make sure the struct ip_reass_helper fits into the IP header */ + LWIP_ASSERT("sizeof(struct ip_reass_helper) <= IP_HLEN", + sizeof(struct ip_reass_helper) <= IP_HLEN); + iprh = (struct ip_reass_helper *)new_p->payload; + iprh->next_pbuf = NULL; + iprh->start = offset; + iprh->end = (u16_t)(offset + len); + if (iprh->end < offset) { + /* u16_t overflow, cannot handle this */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + } + + /* Iterate through until we either get to the end of the list (append), + * or we find one with a larger offset (insert). */ + for (q = ipr->p; q != NULL;) { + iprh_tmp = (struct ip_reass_helper *)q->payload; + if (iprh->start < iprh_tmp->start) { + /* the new pbuf should be inserted before this */ + iprh->next_pbuf = q; + if (iprh_prev != NULL) { + /* not the fragment with the lowest offset */ +#if IP_REASS_CHECK_OVERLAP + if ((iprh->start < iprh_prev->end) || (iprh->end > iprh_tmp->start)) { + /* fragment overlaps with previous or following, throw away */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + } +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + if (iprh_prev->end != iprh->start) { + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + } + } else { +#if IP_REASS_CHECK_OVERLAP + if (iprh->end > iprh_tmp->start) { + /* fragment overlaps with following, throw away */ + return IP_REASS_VALIDATE_PBUF_DROPPED; + } +#endif /* IP_REASS_CHECK_OVERLAP */ + /* fragment with the lowest offset */ + ipr->p = new_p; + } + break; + } else if (iprh->start == iprh_tmp->start) { + /* received the same datagram twice: no need to keep the datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; +#if IP_REASS_CHECK_OVERLAP + } else if (iprh->start < iprh_tmp->end) { + /* overlap: no need to keep the new datagram */ + return IP_REASS_VALIDATE_PBUF_DROPPED; +#endif /* IP_REASS_CHECK_OVERLAP */ + } else { + /* Check if the fragments received so far have no holes. */ + if (iprh_prev != NULL) { + if (iprh_prev->end != iprh_tmp->start) { + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + } + } + } + q = iprh_tmp->next_pbuf; + iprh_prev = iprh_tmp; + } + + /* If q is NULL, then we made it to the end of the list. Determine what to do now */ + if (q == NULL) { + if (iprh_prev != NULL) { + /* this is (for now), the fragment with the highest offset: + * chain it to the last fragment */ +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= iprh->start); +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = new_p; + if (iprh_prev->end != iprh->start) { + valid = 0; + } + } else { +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("no previous fragment, this must be the first fragment!", + ipr->p == NULL); +#endif /* IP_REASS_CHECK_OVERLAP */ + /* this is the first fragment we ever received for this ip datagram */ + ipr->p = new_p; + } + } + + /* At this point, the validation part begins: */ + /* If we already received the last fragment */ + if (is_last || ((ipr->flags & IP_REASS_FLAG_LASTFRAG) != 0)) { + /* and had no holes so far */ + if (valid) { + /* then check if the rest of the fragments is here */ + /* Check if the queue starts with the first datagram */ + if ((ipr->p == NULL) || (((struct ip_reass_helper *)ipr->p->payload)->start != 0)) { + valid = 0; + } else { + /* and check that there are no holes after this datagram */ + iprh_prev = iprh; + q = iprh->next_pbuf; + while (q != NULL) { + iprh = (struct ip_reass_helper *)q->payload; + if (iprh_prev->end != iprh->start) { + valid = 0; + break; + } + iprh_prev = iprh; + q = iprh->next_pbuf; + } + /* if still valid, all fragments are received + * (because to the MF==0 already arrived */ + if (valid) { + LWIP_ASSERT("sanity check", ipr->p != NULL); + LWIP_ASSERT("sanity check", + ((struct ip_reass_helper *)ipr->p->payload) != iprh); + LWIP_ASSERT("validate_datagram:next_pbuf!=NULL", + iprh->next_pbuf == NULL); + } + } + } + /* If valid is 0 here, there are some fragments missing in the middle + * (since MF == 0 has already arrived). Such datagrams simply time out if + * no more fragments are received... */ + return valid ? IP_REASS_VALIDATE_TELEGRAM_FINISHED : IP_REASS_VALIDATE_PBUF_QUEUED; + } + /* If we come here, not all fragments were received, yet! */ + return IP_REASS_VALIDATE_PBUF_QUEUED; /* not yet valid! */ +} + +/** + * Reassembles incoming IP fragments into an IP datagram. + * + * @param p points to a pbuf chain of the fragment + * @return NULL if reassembly is incomplete, ? otherwise + */ +struct pbuf * +ip4_reass(struct pbuf *p) +{ + struct pbuf *r; + struct ip_hdr *fraghdr; + struct ip_reassdata *ipr; + struct ip_reass_helper *iprh; + u16_t offset, len, clen; + u8_t hlen; + int valid; + int is_last; + + IPFRAG_STATS_INC(ip_frag.recv); + MIB2_STATS_INC(mib2.ipreasmreqds); + + fraghdr = (struct ip_hdr *)p->payload; + + if (IPH_HL_BYTES(fraghdr) != IP_HLEN) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: IP options currently not supported!\n")); + IPFRAG_STATS_INC(ip_frag.err); + goto nullreturn; + } + + offset = IPH_OFFSET_BYTES(fraghdr); + len = lwip_ntohs(IPH_LEN(fraghdr)); + hlen = IPH_HL_BYTES(fraghdr); + if (hlen > len) { + /* invalid datagram */ + goto nullreturn; + } + len = (u16_t)(len - hlen); + + /* Check if we are allowed to enqueue more datagrams. */ + clen = pbuf_clen(p); + if ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { +#if IP_REASS_FREE_OLDEST + if (!ip_reass_remove_oldest_datagram(fraghdr, clen) || + ((ip_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS)) +#endif /* IP_REASS_FREE_OLDEST */ + { + /* No datagram could be freed and still too many pbufs enqueued */ + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: Overflow condition: pbufct=%d, clen=%d, MAX=%d\n", + ip_reass_pbufcount, clen, IP_REASS_MAX_PBUFS)); + IPFRAG_STATS_INC(ip_frag.memerr); + /* @todo: send ICMP time exceeded here? */ + /* drop this pbuf */ + goto nullreturn; + } + } + + /* Look for the datagram the fragment belongs to in the current datagram queue, + * remembering the previous in the queue for later dequeueing. */ + for (ipr = reassdatagrams; ipr != NULL; ipr = ipr->next) { + /* Check if the incoming fragment matches the one currently present + in the reassembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if (IP_ADDRESSES_AND_ID_MATCH(&ipr->iphdr, fraghdr)) { + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: matching previous fragment ID=%"X16_F"\n", + lwip_ntohs(IPH_ID(fraghdr)))); + IPFRAG_STATS_INC(ip_frag.cachehit); + break; + } + } + + if (ipr == NULL) { + /* Enqueue a new datagram into the datagram queue */ + ipr = ip_reass_enqueue_new_datagram(fraghdr, clen); + /* Bail if unable to enqueue */ + if (ipr == NULL) { + goto nullreturn; + } + } else { + if (((lwip_ntohs(IPH_OFFSET(fraghdr)) & IP_OFFMASK) == 0) && + ((lwip_ntohs(IPH_OFFSET(&ipr->iphdr)) & IP_OFFMASK) != 0)) { + /* ipr->iphdr is not the header from the first fragment, but fraghdr is + * -> copy fraghdr into ipr->iphdr since we want to have the header + * of the first fragment (for ICMP time exceeded and later, for copying + * all options, if supported)*/ + SMEMCPY(&ipr->iphdr, fraghdr, IP_HLEN); + } + } + + /* At this point, we have either created a new entry or pointing + * to an existing one */ + + /* check for 'no more fragments', and update queue entry*/ + is_last = (IPH_OFFSET(fraghdr) & PP_NTOHS(IP_MF)) == 0; + if (is_last) { + u16_t datagram_len = (u16_t)(offset + len); + if ((datagram_len < offset) || (datagram_len > (0xFFFF - IP_HLEN))) { + /* u16_t overflow, cannot handle this */ + goto nullreturn_ipr; + } + } + /* find the right place to insert this pbuf */ + /* @todo: trim pbufs if fragments are overlapping */ + valid = ip_reass_chain_frag_into_datagram_and_validate(ipr, p, is_last); + if (valid == IP_REASS_VALIDATE_PBUF_DROPPED) { + goto nullreturn_ipr; + } + /* if we come here, the pbuf has been enqueued */ + + /* Track the current number of pbufs current 'in-flight', in order to limit + the number of fragments that may be enqueued at any one time + (overflow checked by testing against IP_REASS_MAX_PBUFS) */ + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount + clen); + if (is_last) { + u16_t datagram_len = (u16_t)(offset + len); + ipr->datagram_len = datagram_len; + ipr->flags |= IP_REASS_FLAG_LASTFRAG; + LWIP_DEBUGF(IP_REASS_DEBUG, + ("ip4_reass: last fragment seen, total len %"S16_F"\n", + ipr->datagram_len)); + } + + if (valid == IP_REASS_VALIDATE_TELEGRAM_FINISHED) { + struct ip_reassdata *ipr_prev; + /* the totally last fragment (flag more fragments = 0) was received at least + * once AND all fragments are received */ + u16_t datagram_len = (u16_t)(ipr->datagram_len + IP_HLEN); + + /* save the second pbuf before copying the header over the pointer */ + r = ((struct ip_reass_helper *)ipr->p->payload)->next_pbuf; + + /* copy the original ip header back to the first pbuf */ + fraghdr = (struct ip_hdr *)(ipr->p->payload); + SMEMCPY(fraghdr, &ipr->iphdr, IP_HLEN); + IPH_LEN_SET(fraghdr, lwip_htons(datagram_len)); + IPH_OFFSET_SET(fraghdr, 0); + IPH_CHKSUM_SET(fraghdr, 0); + /* @todo: do we need to set/calculate the correct checksum? */ +#if CHECKSUM_GEN_IP + IF__NETIF_CHECKSUM_ENABLED(ip_current_input_netif(), NETIF_CHECKSUM_GEN_IP) { + IPH_CHKSUM_SET(fraghdr, inet_chksum(fraghdr, IP_HLEN)); + } +#endif /* CHECKSUM_GEN_IP */ + + p = ipr->p; + + /* chain together the pbufs contained within the reass_data list. */ + while (r != NULL) { + iprh = (struct ip_reass_helper *)r->payload; + + /* hide the ip header for every succeeding fragment */ + pbuf_remove_header(r, IP_HLEN); + pbuf_cat(p, r); + r = iprh->next_pbuf; + } + + /* find the previous entry in the linked list */ + if (ipr == reassdatagrams) { + ipr_prev = NULL; + } else { + for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { + if (ipr_prev->next == ipr) { + break; + } + } + } + + /* release the sources allocate for the fragment queue entry */ + ip_reass_dequeue_datagram(ipr, ipr_prev); + + /* and adjust the number of pbufs currently queued for reassembly. */ + clen = pbuf_clen(p); + LWIP_ASSERT("ip_reass_pbufcount >= clen", ip_reass_pbufcount >= clen); + ip_reass_pbufcount = (u16_t)(ip_reass_pbufcount - clen); + + MIB2_STATS_INC(mib2.ipreasmoks); + + /* Return the pbuf chain */ + return p; + } + /* the datagram is not (yet?) reassembled completely */ + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip_reass_pbufcount: %d out\n", ip_reass_pbufcount)); + return NULL; + +nullreturn_ipr: + LWIP_ASSERT("ipr != NULL", ipr != NULL); + if (ipr->p == NULL) { + /* dropped pbuf after creating a new datagram entry: remove the entry, too */ + LWIP_ASSERT("not firstalthough just enqueued", ipr == reassdatagrams); + ip_reass_dequeue_datagram(ipr, NULL); + } + +nullreturn: + LWIP_DEBUGF(IP_REASS_DEBUG, ("ip4_reass: nullreturn\n")); + IPFRAG_STATS_INC(ip_frag.drop); + pbuf_free(p); + return NULL; +} +#endif /* IP_REASSEMBLY */ + +#if IP_FRAG +#if !LWIP_NETIF_TX_SINGLE_PBUF +/** Allocate a new struct pbuf_custom_ref */ +static struct pbuf_custom_ref * +ip_frag_alloc_pbuf_custom_ref(void) +{ + return (struct pbuf_custom_ref *)memp_malloc(MEMP_FRAG_PBUF); +} + +/** Free a struct pbuf_custom_ref */ +static void +ip_frag_free_pbuf_custom_ref(struct pbuf_custom_ref *p) +{ + LWIP_ASSERT("p != NULL", p != NULL); + memp_free(MEMP_FRAG_PBUF, p); +} + +/** Free-callback function to free a 'struct pbuf_custom_ref', called by + * pbuf_free. */ +static void +ipfrag_free_pbuf_custom(struct pbuf *p) +{ + struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref *)p; + LWIP_ASSERT("pcr != NULL", pcr != NULL); + LWIP_ASSERT("pcr == p", (void *)pcr == (void *)p); + if (pcr->original != NULL) { + pbuf_free(pcr->original); + } + ip_frag_free_pbuf_custom_ref(pcr); +} +#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ + +/** + * Fragment an IP datagram if too large for the netif. + * + * Chop the datagram in MTU sized chunks and send them in order + * by pointing PBUF_REFs into p. + * + * @param p ip packet to send + * @param netif the netif on which to send + * @param dest destination ip address to which to send + * + * @return ERR_OK if sent successfully, err_t otherwise + */ +err_t +ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest) +{ + struct pbuf *rambuf; +#if !LWIP_NETIF_TX_SINGLE_PBUF + struct pbuf *newpbuf; + u16_t newpbuflen = 0; + u16_t left_to_copy; +#endif + struct ip_hdr *original_iphdr; + struct ip_hdr *iphdr; + const u16_t nfb = (u16_t)((netif->mtu - IP_HLEN) / 8); + u16_t left, fragsize; + u16_t ofo; + int last; + u16_t poff = IP_HLEN; + u16_t tmp; + int mf_set; + + original_iphdr = (struct ip_hdr *)p->payload; + iphdr = original_iphdr; + if (IPH_HL_BYTES(iphdr) != IP_HLEN) { + /* ip4_frag() does not support IP options */ + return ERR_VAL; + } + LWIP_ERROR("ip4_frag(): pbuf too short", p->len >= IP_HLEN, return ERR_VAL); + + /* Save original offset */ + tmp = lwip_ntohs(IPH_OFFSET(iphdr)); + ofo = tmp & IP_OFFMASK; + /* already fragmented? if so, the last fragment we create must have MF, too */ + mf_set = tmp & IP_MF; + + left = (u16_t)(p->tot_len - IP_HLEN); + + while (left) { + /* Fill this fragment */ + fragsize = LWIP_MIN(left, (u16_t)(nfb * 8)); + +#if LWIP_NETIF_TX_SINGLE_PBUF + rambuf = pbuf_alloc(PBUF_IP, fragsize, PBUF_RAM); + if (rambuf == NULL) { + goto memerr; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL)); + poff += pbuf_copy_partial(p, rambuf->payload, fragsize, poff); + /* make room for the IP header */ + if (pbuf_add_header(rambuf, IP_HLEN)) { + pbuf_free(rambuf); + goto memerr; + } + /* fill in the IP header */ + SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); + iphdr = (struct ip_hdr *)rambuf->payload; +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + /* When not using a static buffer, create a chain of pbufs. + * The first will be a PBUF_RAM holding the link and IP header. + * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, + * but limited to the size of an mtu. + */ + rambuf = pbuf_alloc(PBUF_LINK, IP_HLEN, PBUF_RAM); + if (rambuf == NULL) { + goto memerr; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + (rambuf->len >= (IP_HLEN))); + SMEMCPY(rambuf->payload, original_iphdr, IP_HLEN); + iphdr = (struct ip_hdr *)rambuf->payload; + + left_to_copy = fragsize; + while (left_to_copy) { + struct pbuf_custom_ref *pcr; + u16_t plen = (u16_t)(p->len - poff); + LWIP_ASSERT("p->len >= poff", p->len >= poff); + newpbuflen = LWIP_MIN(left_to_copy, plen); + /* Is this pbuf already empty? */ + if (!newpbuflen) { + poff = 0; + p = p->next; + continue; + } + pcr = ip_frag_alloc_pbuf_custom_ref(); + if (pcr == NULL) { + pbuf_free(rambuf); + goto memerr; + } + /* Mirror this pbuf, although we might not need all of it. */ + newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, + (u8_t *)p->payload + poff, newpbuflen); + if (newpbuf == NULL) { + ip_frag_free_pbuf_custom_ref(pcr); + pbuf_free(rambuf); + goto memerr; + } + pbuf_ref(p); + pcr->original = p; + pcr->pc.custom_free_function = ipfrag_free_pbuf_custom; + + /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain + * so that it is removed when pbuf_dechain is later called on rambuf. + */ + pbuf_cat(rambuf, newpbuf); + left_to_copy = (u16_t)(left_to_copy - newpbuflen); + if (left_to_copy) { + poff = 0; + p = p->next; + } + } + poff = (u16_t)(poff + newpbuflen); +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + /* Correct header */ + last = (left <= netif->mtu - IP_HLEN); + + /* Set new offset and MF flag */ + tmp = (IP_OFFMASK & (ofo)); + if (!last || mf_set) { + /* the last fragment has MF set if the input frame had it */ + tmp = tmp | IP_MF; + } + IPH_OFFSET_SET(iphdr, lwip_htons(tmp)); + IPH_LEN_SET(iphdr, lwip_htons((u16_t)(fragsize + IP_HLEN))); + IPH_CHKSUM_SET(iphdr, 0); +#if CHECKSUM_GEN_IP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_IP) { + IPH_CHKSUM_SET(iphdr, inet_chksum(iphdr, IP_HLEN)); + } +#endif /* CHECKSUM_GEN_IP */ + + /* No need for separate header pbuf - we allowed room for it in rambuf + * when allocated. + */ + netif->output(netif, rambuf, dest); + IPFRAG_STATS_INC(ip_frag.xmit); + + /* Unfortunately we can't reuse rambuf - the hardware may still be + * using the buffer. Instead we free it (and the ensuing chain) and + * recreate it next time round the loop. If we're lucky the hardware + * will have already sent the packet, the free will really free, and + * there will be zero memory penalty. + */ + + pbuf_free(rambuf); + left = (u16_t)(left - fragsize); + ofo = (u16_t)(ofo + nfb); + } + MIB2_STATS_INC(mib2.ipfragoks); + return ERR_OK; +memerr: + MIB2_STATS_INC(mib2.ipfragfails); + return ERR_MEM; +} +#endif /* IP_FRAG */ + +#endif /* LWIP_IPV4 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c new file mode 100644 index 0000000..7cf98a5 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/dhcp6.c @@ -0,0 +1,812 @@ +/** + * @file + * + * @defgroup dhcp6 DHCPv6 + * @ingroup ip6 + * DHCPv6 client: IPv6 address autoconfiguration as per + * RFC 3315 (stateful DHCPv6) and + * RFC 3736 (stateless DHCPv6). + * + * For now, only stateless DHCPv6 is implemented! + * + * TODO: + * - enable/disable API to not always start when RA is received + * - stateful DHCPv6 (for now, only stateless DHCPv6 for DNS and NTP servers works) + * - create Client Identifier? + * - only start requests if a valid local address is available on the netif + * - only start information requests if required (not for every RA) + * + * dhcp6_enable_stateful() enables stateful DHCPv6 for a netif (stateless disabled)\n + * dhcp6_enable_stateless() enables stateless DHCPv6 for a netif (stateful disabled)\n + * dhcp6_disable() disable DHCPv6 for a netif + * + * When enabled, requests are only issued after receipt of RA with the + * corresponding bits set. + */ + +/* + * Copyright (c) 2018 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + */ + +#include "lwip/opt.h" + +#if LWIP_IPV6 && LWIP_IPV6_DHCP6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/dhcp6.h" +#include "lwip/prot/dhcp6.h" +#include "lwip/def.h" +#include "lwip/udp.h" +#include "lwip/dns.h" + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif +#ifndef LWIP_HOOK_DHCP6_APPEND_OPTIONS +#define LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len) +#endif +#ifndef LWIP_HOOK_DHCP6_PARSE_OPTION +#define LWIP_HOOK_DHCP6_PARSE_OPTION(netif, dhcp6, state, msg, msg_type, option, len, pbuf, offset) do { LWIP_UNUSED_ARG(msg); } while(0) +#endif + +#if LWIP_DNS && LWIP_DHCP6_MAX_DNS_SERVERS +#if DNS_MAX_SERVERS > LWIP_DHCP6_MAX_DNS_SERVERS +#define LWIP_DHCP6_PROVIDE_DNS_SERVERS LWIP_DHCP6_MAX_DNS_SERVERS +#else +#define LWIP_DHCP6_PROVIDE_DNS_SERVERS DNS_MAX_SERVERS +#endif +#else +#define LWIP_DHCP6_PROVIDE_DNS_SERVERS 0 +#endif + + +/** Option handling: options are parsed in dhcp6_parse_reply + * and saved in an array where other functions can load them from. + * This might be moved into the struct dhcp6 (not necessarily since + * lwIP is single-threaded and the array is only used while in recv + * callback). */ +enum dhcp6_option_idx { + DHCP6_OPTION_IDX_CLI_ID = 0, + DHCP6_OPTION_IDX_SERVER_ID, +#if LWIP_DHCP6_PROVIDE_DNS_SERVERS + DHCP6_OPTION_IDX_DNS_SERVER, + DHCP6_OPTION_IDX_DOMAIN_LIST, +#endif /* LWIP_DHCP_PROVIDE_DNS_SERVERS */ +#if LWIP_DHCP6_GET_NTP_SRV + DHCP6_OPTION_IDX_NTP_SERVER, +#endif /* LWIP_DHCP_GET_NTP_SRV */ + DHCP6_OPTION_IDX_MAX +}; + +struct dhcp6_option_info { + u8_t option_given; + u16_t val_start; + u16_t val_length; +}; + +/** Holds the decoded option info, only valid while in dhcp6_recv. */ +struct dhcp6_option_info dhcp6_rx_options[DHCP6_OPTION_IDX_MAX]; + +#define dhcp6_option_given(dhcp6, idx) (dhcp6_rx_options[idx].option_given != 0) +#define dhcp6_got_option(dhcp6, idx) (dhcp6_rx_options[idx].option_given = 1) +#define dhcp6_clear_option(dhcp6, idx) (dhcp6_rx_options[idx].option_given = 0) +#define dhcp6_clear_all_options(dhcp6) (memset(dhcp6_rx_options, 0, sizeof(dhcp6_rx_options))) +#define dhcp6_get_option_start(dhcp6, idx) (dhcp6_rx_options[idx].val_start) +#define dhcp6_get_option_length(dhcp6, idx) (dhcp6_rx_options[idx].val_length) +#define dhcp6_set_option(dhcp6, idx, start, len) do { dhcp6_rx_options[idx].val_start = (start); dhcp6_rx_options[idx].val_length = (len); }while(0) + + +const ip_addr_t dhcp6_All_DHCP6_Relay_Agents_and_Servers = IPADDR6_INIT_HOST(0xFF020000, 0, 0, 0x00010002); +const ip_addr_t dhcp6_All_DHCP6_Servers = IPADDR6_INIT_HOST(0xFF020000, 0, 0, 0x00010003); + +static struct udp_pcb *dhcp6_pcb; +static u8_t dhcp6_pcb_refcount; + + +/* receive, unfold, parse and free incoming messages */ +static void dhcp6_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port); + +/** Ensure DHCP PCB is allocated and bound */ +static err_t +dhcp6_inc_pcb_refcount(void) +{ + if (dhcp6_pcb_refcount == 0) { + LWIP_ASSERT("dhcp6_inc_pcb_refcount(): memory leak", dhcp6_pcb == NULL); + + /* allocate UDP PCB */ + dhcp6_pcb = udp_new_ip6(); + + if (dhcp6_pcb == NULL) { + return ERR_MEM; + } + + ip_set_option(dhcp6_pcb, SOF_BROADCAST); + + /* set up local and remote port for the pcb -> listen on all interfaces on all src/dest IPs */ + udp_bind(dhcp6_pcb, IP6_ADDR_ANY, DHCP6_CLIENT_PORT); + udp_recv(dhcp6_pcb, dhcp6_recv, NULL); + } + + dhcp6_pcb_refcount++; + + return ERR_OK; +} + +/** Free DHCP PCB if the last netif stops using it */ +static void +dhcp6_dec_pcb_refcount(void) +{ + LWIP_ASSERT("dhcp6_pcb_refcount(): refcount error", (dhcp6_pcb_refcount > 0)); + dhcp6_pcb_refcount--; + + if (dhcp6_pcb_refcount == 0) { + udp_remove(dhcp6_pcb); + dhcp6_pcb = NULL; + } +} + +/** + * @ingroup dhcp6 + * Set a statically allocated struct dhcp6 to work with. + * Using this prevents dhcp6_start to allocate it using mem_malloc. + * + * @param netif the netif for which to set the struct dhcp + * @param dhcp6 (uninitialised) dhcp6 struct allocated by the application + */ +void +dhcp6_set_struct(struct netif *netif, struct dhcp6 *dhcp6) +{ + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("dhcp6 != NULL", dhcp6 != NULL); + LWIP_ASSERT("netif already has a struct dhcp6 set", netif_dhcp6_data(netif) == NULL); + + /* clear data structure */ + memset(dhcp6, 0, sizeof(struct dhcp6)); + /* dhcp6_set_state(&dhcp, DHCP6_STATE_OFF); */ + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, dhcp6); +} + +/** + * @ingroup dhcp6 + * Removes a struct dhcp6 from a netif. + * + * ATTENTION: Only use this when not using dhcp6_set_struct() to allocate the + * struct dhcp6 since the memory is passed back to the heap. + * + * @param netif the netif from which to remove the struct dhcp + */ +void dhcp6_cleanup(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", netif != NULL); + + if (netif_dhcp6_data(netif) != NULL) { + mem_free(netif_dhcp6_data(netif)); + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, NULL); + } +} + +static struct dhcp6* +dhcp6_get_struct(struct netif *netif, const char *dbg_requester) +{ + struct dhcp6 *dhcp6 = netif_dhcp6_data(netif); + if (dhcp6 == NULL) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("%s: mallocing new DHCPv6 client\n", dbg_requester)); + dhcp6 = (struct dhcp6 *)mem_malloc(sizeof(struct dhcp6)); + if (dhcp6 == NULL) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("%s: could not allocate dhcp6\n", dbg_requester)); + return NULL; + } + + /* clear data structure, this implies DHCP6_STATE_OFF */ + memset(dhcp6, 0, sizeof(struct dhcp6)); + /* store this dhcp6 client in the netif */ + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, dhcp6); + } else { + /* already has DHCP6 client attached */ + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("%s: using existing DHCPv6 client\n", dbg_requester)); + } + + if (!dhcp6->pcb_allocated) { + if (dhcp6_inc_pcb_refcount() != ERR_OK) { /* ensure DHCP6 PCB is allocated */ + mem_free(dhcp6); + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, NULL); + return NULL; + } + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("%s: allocated dhcp6", dbg_requester)); + dhcp6->pcb_allocated = 1; + } + return dhcp6; +} + +/* + * Set the DHCPv6 state + * If the state changed, reset the number of tries. + */ +static void +dhcp6_set_state(struct dhcp6 *dhcp6, u8_t new_state, const char *dbg_caller) +{ + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("DHCPv6 state: %d -> %d (%s)\n", + dhcp6->state, new_state, dbg_caller)); + if (new_state != dhcp6->state) { + dhcp6->state = new_state; + dhcp6->tries = 0; + dhcp6->request_timeout = 0; + } +} + +static int +dhcp6_stateless_enabled(struct dhcp6 *dhcp6) +{ + if ((dhcp6->state == DHCP6_STATE_STATELESS_IDLE) || + (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG)) { + return 1; + } + return 0; +} + +/*static int +dhcp6_stateful_enabled(struct dhcp6 *dhcp6) +{ + if (dhcp6->state == DHCP6_STATE_OFF) { + return 0; + } + if (dhcp6_stateless_enabled(dhcp6)) { + return 0; + } + return 1; +}*/ + +/** + * @ingroup dhcp6 + * Enable stateful DHCPv6 on this netif + * Requests are sent on receipt of an RA message with the + * ND6_RA_FLAG_MANAGED_ADDR_CONFIG flag set. + * + * A struct dhcp6 will be allocated for this netif if not + * set via @ref dhcp6_set_struct before. + * + * @todo: stateful DHCPv6 not supported, yet + */ +err_t +dhcp6_enable_stateful(struct netif *netif) +{ + LWIP_UNUSED_ARG(netif); + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("stateful dhcp6 not implemented yet")); + return ERR_VAL; +} + +/** + * @ingroup dhcp6 + * Enable stateless DHCPv6 on this netif + * Requests are sent on receipt of an RA message with the + * ND6_RA_FLAG_OTHER_CONFIG flag set. + * + * A struct dhcp6 will be allocated for this netif if not + * set via @ref dhcp6_set_struct before. + */ +err_t +dhcp6_enable_stateless(struct netif *netif) +{ + struct dhcp6 *dhcp6; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_enable_stateless(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + dhcp6 = dhcp6_get_struct(netif, "dhcp6_enable_stateless()"); + if (dhcp6 == NULL) { + return ERR_MEM; + } + if (dhcp6_stateless_enabled(dhcp6)) { + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_enable_stateless(): stateless DHCPv6 already enabled")); + return ERR_OK; + } else if (dhcp6->state != DHCP6_STATE_OFF) { + /* stateful running */ + /* @todo: stop stateful once it is implemented */ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_enable_stateless(): switching from stateful to stateless DHCPv6")); + } + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_enable_stateless(): stateless DHCPv6 enabled\n")); + dhcp6_set_state(dhcp6, DHCP6_STATE_STATELESS_IDLE, "dhcp6_enable_stateless"); + return ERR_OK; +} + +/** + * @ingroup dhcp6 + * Disable stateful or stateless DHCPv6 on this netif + * Requests are sent on receipt of an RA message with the + * ND6_RA_FLAG_OTHER_CONFIG flag set. + */ +void +dhcp6_disable(struct netif *netif) +{ + struct dhcp6 *dhcp6; + + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_disable(netif=%p) %c%c%"U16_F"\n", (void *)netif, netif->name[0], netif->name[1], (u16_t)netif->num)); + + dhcp6 = netif_dhcp6_data(netif); + if (dhcp6 != NULL) { + if (dhcp6->state != DHCP6_STATE_OFF) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_disable(): DHCPv6 disabled (old state: %s)\n", + (dhcp6_stateless_enabled(dhcp6) ? "stateless" : "stateful"))); + dhcp6_set_state(dhcp6, DHCP6_STATE_OFF, "dhcp6_disable"); + if (dhcp6->pcb_allocated != 0) { + dhcp6_dec_pcb_refcount(); /* free DHCPv6 PCB if not needed any more */ + dhcp6->pcb_allocated = 0; + } + } + } +} + +/** + * Create a DHCPv6 request, fill in common headers + * + * @param netif the netif under DHCPv6 control + * @param dhcp6 dhcp6 control struct + * @param message_type message type of the request + * @param opt_len_alloc option length to allocate + * @param options_out_len option length on exit + * @return a pbuf for the message + */ +static struct pbuf * +dhcp6_create_msg(struct netif *netif, struct dhcp6 *dhcp6, u8_t message_type, + u16_t opt_len_alloc, u16_t *options_out_len) +{ + struct pbuf *p_out; + struct dhcp6_msg *msg_out; + + LWIP_ERROR("dhcp6_create_msg: netif != NULL", (netif != NULL), return NULL;); + LWIP_ERROR("dhcp6_create_msg: dhcp6 != NULL", (dhcp6 != NULL), return NULL;); + p_out = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct dhcp6_msg) + opt_len_alloc, PBUF_RAM); + if (p_out == NULL) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("dhcp6_create_msg(): could not allocate pbuf\n")); + return NULL; + } + LWIP_ASSERT("dhcp6_create_msg: check that first pbuf can hold struct dhcp6_msg", + (p_out->len >= sizeof(struct dhcp6_msg) + opt_len_alloc)); + + /* @todo: limit new xid for certain message types? */ + /* reuse transaction identifier in retransmissions */ + if (dhcp6->tries == 0) { + dhcp6->xid = LWIP_RAND() & 0xFFFFFF; + } + + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, + ("transaction id xid(%"X32_F")\n", dhcp6->xid)); + + msg_out = (struct dhcp6_msg *)p_out->payload; + memset(msg_out, 0, sizeof(struct dhcp6_msg) + opt_len_alloc); + + msg_out->msgtype = message_type; + msg_out->transaction_id[0] = (u8_t)(dhcp6->xid >> 16); + msg_out->transaction_id[1] = (u8_t)(dhcp6->xid >> 8); + msg_out->transaction_id[2] = (u8_t)dhcp6->xid; + *options_out_len = 0; + return p_out; +} + +static u16_t +dhcp6_option_short(u16_t options_out_len, u8_t *options, u16_t value) +{ + options[options_out_len++] = (u8_t)((value & 0xff00U) >> 8); + options[options_out_len++] = (u8_t) (value & 0x00ffU); + return options_out_len; +} + +static u16_t +dhcp6_option_optionrequest(u16_t options_out_len, u8_t *options, const u16_t *req_options, + u16_t num_req_options, u16_t max_len) +{ + size_t i; + u16_t ret; + + LWIP_ASSERT("dhcp6_option_optionrequest: options_out_len + sizeof(struct dhcp6_msg) + addlen <= max_len", + sizeof(struct dhcp6_msg) + options_out_len + 4U + (2U * num_req_options) <= max_len); + LWIP_UNUSED_ARG(max_len); + + ret = dhcp6_option_short(options_out_len, options, DHCP6_OPTION_ORO); + ret = dhcp6_option_short(ret, options, 2 * num_req_options); + for (i = 0; i < num_req_options; i++) { + ret = dhcp6_option_short(ret, options, req_options[i]); + } + return ret; +} + +/* All options are added, shrink the pbuf to the required size */ +static void +dhcp6_msg_finalize(u16_t options_out_len, struct pbuf *p_out) +{ + /* shrink the pbuf to the actual content length */ + pbuf_realloc(p_out, (u16_t)(sizeof(struct dhcp6_msg) + options_out_len)); +} + + +#if LWIP_IPV6_DHCP6_STATELESS +static void +dhcp6_information_request(struct netif *netif, struct dhcp6 *dhcp6) +{ + const u16_t requested_options[] = {DHCP6_OPTION_DNS_SERVERS, DHCP6_OPTION_DOMAIN_LIST, DHCP6_OPTION_SNTP_SERVERS}; + u16_t msecs; + struct pbuf *p_out; + u16_t options_out_len; + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_information_request()\n")); + /* create and initialize the DHCP message header */ + p_out = dhcp6_create_msg(netif, dhcp6, DHCP6_INFOREQUEST, 4 + sizeof(requested_options), &options_out_len); + if (p_out != NULL) { + err_t err; + struct dhcp6_msg *msg_out = (struct dhcp6_msg *)p_out->payload; + u8_t *options = (u8_t *)(msg_out + 1); + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_information_request: making request\n")); + + options_out_len = dhcp6_option_optionrequest(options_out_len, options, requested_options, + LWIP_ARRAYSIZE(requested_options), p_out->len); + LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, DHCP6_STATE_REQUESTING_CONFIG, msg_out, + DHCP6_INFOREQUEST, options_out_len, p_out->len); + dhcp6_msg_finalize(options_out_len, p_out); + + err = udp_sendto_if(dhcp6_pcb, p_out, &dhcp6_All_DHCP6_Relay_Agents_and_Servers, DHCP6_SERVER_PORT, netif); + pbuf_free(p_out); + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_information_request: INFOREQUESTING -> %d\n", (int)err)); + LWIP_UNUSED_ARG(err); + } else { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("dhcp6_information_request: could not allocate DHCP6 request\n")); + } + dhcp6_set_state(dhcp6, DHCP6_STATE_REQUESTING_CONFIG, "dhcp6_information_request"); + if (dhcp6->tries < 255) { + dhcp6->tries++; + } + msecs = (u16_t)((dhcp6->tries < 6 ? 1 << dhcp6->tries : 60) * 1000); + dhcp6->request_timeout = (u16_t)((msecs + DHCP6_TIMER_MSECS - 1) / DHCP6_TIMER_MSECS); + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_information_request(): set request timeout %"U16_F" msecs\n", msecs)); +} + +static err_t +dhcp6_request_config(struct netif *netif, struct dhcp6 *dhcp6) +{ + /* stateless mode enabled and no request running? */ + if (dhcp6->state == DHCP6_STATE_STATELESS_IDLE) { + /* send Information-request and wait for answer; setup receive timeout */ + dhcp6_information_request(netif, dhcp6); + } + + return ERR_OK; +} + +static void +dhcp6_abort_config_request(struct dhcp6 *dhcp6) +{ + if (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG) { + /* abort running request */ + dhcp6_set_state(dhcp6, DHCP6_STATE_STATELESS_IDLE, "dhcp6_abort_config_request"); + } +} + +/* Handle a REPLY to INFOREQUEST + * This parses DNS and NTP server addresses from the reply. + */ +static void +dhcp6_handle_config_reply(struct netif *netif, struct pbuf *p_msg_in) +{ + struct dhcp6 *dhcp6 = netif_dhcp6_data(netif); + + LWIP_UNUSED_ARG(dhcp6); + LWIP_UNUSED_ARG(p_msg_in); + +#if LWIP_DHCP6_PROVIDE_DNS_SERVERS + if (dhcp6_option_given(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER)) { + ip_addr_t dns_addr; + ip6_addr_t *dns_addr6; + u16_t op_start = dhcp6_get_option_start(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER); + u16_t op_len = dhcp6_get_option_length(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER); + u16_t idx; + u8_t n; + + memset(&dns_addr, 0, sizeof(dns_addr)); + dns_addr6 = ip_2_ip6(&dns_addr); + for (n = 0, idx = op_start; (idx < op_start + op_len) && (n < LWIP_DHCP6_PROVIDE_DNS_SERVERS); + n++, idx += sizeof(struct ip6_addr_packed)) { + u16_t copied = pbuf_copy_partial(p_msg_in, dns_addr6, sizeof(struct ip6_addr_packed), idx); + if (copied != sizeof(struct ip6_addr_packed)) { + /* pbuf length mismatch */ + return; + } + ip6_addr_assign_zone(dns_addr6, IP6_UNKNOWN, netif); + /* @todo: do we need a different offset than DHCP(v4)? */ + dns_setserver(n, &dns_addr); + } + } + /* @ todo: parse and set Domain Search List */ +#endif /* LWIP_DHCP6_PROVIDE_DNS_SERVERS */ + +#if LWIP_DHCP6_GET_NTP_SRV + if (dhcp6_option_given(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER)) { + ip_addr_t ntp_server_addrs[LWIP_DHCP6_MAX_NTP_SERVERS]; + u16_t op_start = dhcp6_get_option_start(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER); + u16_t op_len = dhcp6_get_option_length(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER); + u16_t idx; + u8_t n; + + for (n = 0, idx = op_start; (idx < op_start + op_len) && (n < LWIP_DHCP6_MAX_NTP_SERVERS); + n++, idx += sizeof(struct ip6_addr_packed)) { + u16_t copied; + ip6_addr_t *ntp_addr6 = ip_2_ip6(&ntp_server_addrs[n]); + ip_addr_set_zero_ip6(&ntp_server_addrs[n]); + copied = pbuf_copy_partial(p_msg_in, ntp_addr6, sizeof(struct ip6_addr_packed), idx); + if (copied != sizeof(struct ip6_addr_packed)) { + /* pbuf length mismatch */ + return; + } + ip6_addr_assign_zone(ntp_addr6, IP6_UNKNOWN, netif); + } + dhcp6_set_ntp_servers(n, ntp_server_addrs); + } +#endif /* LWIP_DHCP6_GET_NTP_SRV */ +} +#endif /* LWIP_IPV6_DHCP6_STATELESS */ + +/** This function is called from nd6 module when an RA messsage is received + * It triggers DHCPv6 requests (if enabled). + */ +void +dhcp6_nd6_ra_trigger(struct netif *netif, u8_t managed_addr_config, u8_t other_config) +{ + struct dhcp6 *dhcp6; + + LWIP_ASSERT("netif != NULL", netif != NULL); + dhcp6 = netif_dhcp6_data(netif); + + LWIP_UNUSED_ARG(managed_addr_config); + LWIP_UNUSED_ARG(other_config); + LWIP_UNUSED_ARG(dhcp6); + +#if LWIP_IPV6_DHCP6_STATELESS + if (dhcp6 != NULL) { + if (dhcp6_stateless_enabled(dhcp6)) { + if (other_config) { + dhcp6_request_config(netif, dhcp6); + } else { + dhcp6_abort_config_request(dhcp6); + } + } + } +#endif /* LWIP_IPV6_DHCP6_STATELESS */ +} + +/** + * Parse the DHCPv6 message and extract the DHCPv6 options. + * + * Extract the DHCPv6 options (offset + length) so that we can later easily + * check for them or extract the contents. + */ +static err_t +dhcp6_parse_reply(struct pbuf *p, struct dhcp6 *dhcp6) +{ + u16_t offset; + u16_t offset_max; + u16_t options_idx; + struct dhcp6_msg *msg_in; + + LWIP_UNUSED_ARG(dhcp6); + + /* clear received options */ + dhcp6_clear_all_options(dhcp6); + msg_in = (struct dhcp6_msg *)p->payload; + + /* parse options */ + + options_idx = sizeof(struct dhcp6_msg); + /* parse options to the end of the received packet */ + offset_max = p->tot_len; + + offset = options_idx; + /* at least 4 byte to read? */ + while ((offset + 4 <= offset_max)) { + u8_t op_len_buf[4]; + u8_t *op_len; + u16_t op; + u16_t len; + u16_t val_offset = (u16_t)(offset + 4); + if (val_offset < offset) { + /* overflow */ + return ERR_BUF; + } + /* copy option + length, might be split accross pbufs */ + op_len = (u8_t *)pbuf_get_contiguous(p, op_len_buf, 4, 4, offset); + if (op_len == NULL) { + /* failed to get option and length */ + return ERR_VAL; + } + op = (op_len[0] << 8) | op_len[1]; + len = (op_len[2] << 8) | op_len[3]; + offset = val_offset + len; + if (offset < val_offset) { + /* overflow */ + return ERR_BUF; + } + + switch (op) { + case (DHCP6_OPTION_CLIENTID): + dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_CLI_ID); + dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_CLI_ID, val_offset, len); + break; + case (DHCP6_OPTION_SERVERID): + dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_SERVER_ID); + dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_SERVER_ID, val_offset, len); + break; +#if LWIP_DHCP6_PROVIDE_DNS_SERVERS + case (DHCP6_OPTION_DNS_SERVERS): + dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER); + dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_DNS_SERVER, val_offset, len); + break; + case (DHCP6_OPTION_DOMAIN_LIST): + dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_DOMAIN_LIST); + dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_DOMAIN_LIST, val_offset, len); + break; +#endif /* LWIP_DHCP6_PROVIDE_DNS_SERVERS */ +#if LWIP_DHCP6_GET_NTP_SRV + case (DHCP6_OPTION_SNTP_SERVERS): + dhcp6_got_option(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER); + dhcp6_set_option(dhcp6, DHCP6_OPTION_IDX_NTP_SERVER, val_offset, len); + break; +#endif /* LWIP_DHCP6_GET_NTP_SRV*/ + default: + LWIP_DEBUGF(DHCP6_DEBUG, ("skipping option %"U16_F" in options\n", op)); + LWIP_HOOK_DHCP6_PARSE_OPTION(ip_current_netif(), dhcp6, dhcp6->state, msg_in, + msg_in->msgtype, op, len, q, val_offset); + break; + } + } + return ERR_OK; +} + +static void +dhcp6_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) +{ + struct netif *netif = ip_current_input_netif(); + struct dhcp6 *dhcp6 = netif_dhcp6_data(netif); + struct dhcp6_msg *reply_msg = (struct dhcp6_msg *)p->payload; + u8_t msg_type; + u32_t xid; + + LWIP_UNUSED_ARG(arg); + + /* Caught DHCPv6 message from netif that does not have DHCPv6 enabled? -> not interested */ + if ((dhcp6 == NULL) || (dhcp6->pcb_allocated == 0)) { + goto free_pbuf_and_return; + } + + LWIP_ERROR("invalid server address type", IP_IS_V6(addr), goto free_pbuf_and_return;); + + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_recv(pbuf = %p) from DHCPv6 server %s port %"U16_F"\n", (void *)p, + ipaddr_ntoa(addr), port)); + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("pbuf->len = %"U16_F"\n", p->len)); + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("pbuf->tot_len = %"U16_F"\n", p->tot_len)); + /* prevent warnings about unused arguments */ + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(addr); + LWIP_UNUSED_ARG(port); + + if (p->len < sizeof(struct dhcp6_msg)) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, ("DHCPv6 reply message or pbuf too short\n")); + goto free_pbuf_and_return; + } + + /* match transaction ID against what we expected */ + xid = reply_msg->transaction_id[0] << 16; + xid |= reply_msg->transaction_id[1] << 8; + xid |= reply_msg->transaction_id[2]; + if (xid != dhcp6->xid) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("transaction id mismatch reply_msg->xid(%"X32_F")!= dhcp6->xid(%"X32_F")\n", xid, dhcp6->xid)); + goto free_pbuf_and_return; + } + /* option fields could be unfold? */ + if (dhcp6_parse_reply(p, dhcp6) != ERR_OK) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("problem unfolding DHCPv6 message - too short on memory?\n")); + goto free_pbuf_and_return; + } + + /* read DHCP message type */ + msg_type = reply_msg->msgtype; + /* message type is DHCP6 REPLY? */ + if (msg_type == DHCP6_REPLY) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("DHCP6_REPLY received\n")); +#if LWIP_IPV6_DHCP6_STATELESS + /* in info-requesting state? */ + if (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG) { + dhcp6_set_state(dhcp6, DHCP6_STATE_STATELESS_IDLE, "dhcp6_recv"); + dhcp6_handle_config_reply(netif, p); + } else +#endif /* LWIP_IPV6_DHCP6_STATELESS */ + { + /* @todo: handle reply in other states? */ + } + } else { + /* @todo: handle other message types */ + } + +free_pbuf_and_return: + pbuf_free(p); +} + +/** + * A DHCPv6 request has timed out. + * + * The timer that was started with the DHCPv6 request has + * timed out, indicating no response was received in time. + */ +static void +dhcp6_timeout(struct netif *netif, struct dhcp6 *dhcp6) +{ + LWIP_DEBUGF(DHCP_DEBUG | LWIP_DBG_TRACE, ("dhcp6_timeout()\n")); + + LWIP_UNUSED_ARG(netif); + LWIP_UNUSED_ARG(dhcp6); + +#if LWIP_IPV6_DHCP6_STATELESS + /* back-off period has passed, or server selection timed out */ + if (dhcp6->state == DHCP6_STATE_REQUESTING_CONFIG) { + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE, ("dhcp6_timeout(): retrying information request\n")); + dhcp6_information_request(netif, dhcp6); + } +#endif /* LWIP_IPV6_DHCP6_STATELESS */ +} + +/** + * DHCPv6 timeout handling (this function must be called every 500ms, + * see @ref DHCP6_TIMER_MSECS). + * + * A DHCPv6 server is expected to respond within a short period of time. + * This timer checks whether an outstanding DHCPv6 request is timed out. + */ +void +dhcp6_tmr(void) +{ + struct netif *netif; + /* loop through netif's */ + NETIF_FOREACH(netif) { + struct dhcp6 *dhcp6 = netif_dhcp6_data(netif); + /* only act on DHCPv6 configured interfaces */ + if (dhcp6 != NULL) { + /* timer is active (non zero), and is about to trigger now */ + if (dhcp6->request_timeout > 1) { + dhcp6->request_timeout--; + } else if (dhcp6->request_timeout == 1) { + dhcp6->request_timeout--; + /* { dhcp6->request_timeout == 0 } */ + LWIP_DEBUGF(DHCP6_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("dhcp6_tmr(): request timeout\n")); + /* this client's request timeout triggered */ + dhcp6_timeout(netif, dhcp6); + } + } + } +} + +#endif /* LWIP_IPV6 && LWIP_IPV6_DHCP6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c new file mode 100644 index 0000000..fec8b28 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/ethip6.c @@ -0,0 +1,123 @@ +/** + * @file + * + * Ethernet output for IPv6. Uses ND tables for link-layer addressing. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV6 && LWIP_ETHERNET + +#include "lwip/ethip6.h" +#include "lwip/nd6.h" +#include "lwip/pbuf.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/icmp6.h" +#include "lwip/prot/ethernet.h" +#include "netif/ethernet.h" + +#include + +/** + * Resolve and fill-in Ethernet address header for outgoing IPv6 packet. + * + * For IPv6 multicast, corresponding Ethernet addresses + * are selected and the packet is transmitted on the link. + * + * For unicast addresses, ask the ND6 module what to do. It will either let us + * send the the packet right away, or queue the packet for later itself, unless + * an error occurs. + * + * @todo anycast addresses + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param q The pbuf(s) containing the IP packet to be sent. + * @param ip6addr The IP address of the packet destination. + * + * @return + * - ERR_OK or the return value of @ref nd6_get_next_hop_addr_or_queue. + */ +err_t +ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr) +{ + struct eth_addr dest; + const u8_t *hwaddr; + err_t result; + + LWIP_ASSERT_CORE_LOCKED(); + + /* The destination IP address must be properly zoned from here on down. */ + IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif); + + /* multicast destination IP address? */ + if (ip6_addr_ismulticast(ip6addr)) { + /* Hash IP multicast address to MAC address.*/ + dest.addr[0] = 0x33; + dest.addr[1] = 0x33; + dest.addr[2] = ((const u8_t *)(&(ip6addr->addr[3])))[0]; + dest.addr[3] = ((const u8_t *)(&(ip6addr->addr[3])))[1]; + dest.addr[4] = ((const u8_t *)(&(ip6addr->addr[3])))[2]; + dest.addr[5] = ((const u8_t *)(&(ip6addr->addr[3])))[3]; + + /* Send out. */ + return ethernet_output(netif, q, (const struct eth_addr*)(netif->hwaddr), &dest, ETHTYPE_IPV6); + } + + /* We have a unicast destination IP address */ + /* @todo anycast? */ + + /* Ask ND6 what to do with the packet. */ + result = nd6_get_next_hop_addr_or_queue(netif, q, ip6addr, &hwaddr); + if (result != ERR_OK) { + return result; + } + + /* If no hardware address is returned, nd6 has queued the packet for later. */ + if (hwaddr == NULL) { + return ERR_OK; + } + + /* Send out the packet using the returned hardware address. */ + SMEMCPY(dest.addr, hwaddr, 6); + return ethernet_output(netif, q, (const struct eth_addr*)(netif->hwaddr), &dest, ETHTYPE_IPV6); +} + +#endif /* LWIP_IPV6 && LWIP_ETHERNET */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c new file mode 100644 index 0000000..167738a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/icmp6.c @@ -0,0 +1,425 @@ +/** + * @file + * + * IPv6 version of ICMP, as per RFC 4443. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#include "lwip/opt.h" + +#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/icmp6.h" +#include "lwip/prot/icmp6.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/inet_chksum.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/nd6.h" +#include "lwip/mld6.h" +#include "lwip/ip.h" +#include "lwip/stats.h" + +#include + +#if LWIP_ICMP6_DATASIZE == 0 +#undef LWIP_ICMP6_DATASIZE +#define LWIP_ICMP6_DATASIZE 8 +#endif + +/* Forward declarations */ +static void icmp6_send_response(struct pbuf *p, u8_t code, u32_t data, u8_t type); +static void icmp6_send_response_with_addrs(struct pbuf *p, u8_t code, u32_t data, + u8_t type, const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr); +static void icmp6_send_response_with_addrs_and_netif(struct pbuf *p, u8_t code, u32_t data, + u8_t type, const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr, struct netif *netif); + + +/** + * Process an input ICMPv6 message. Called by ip6_input. + * + * Will generate a reply for echo requests. Other messages are forwarded + * to nd6_input, or mld6_input. + * + * @param p the mld packet, p->payload pointing to the icmpv6 header + * @param inp the netif on which this packet was received + */ +void +icmp6_input(struct pbuf *p, struct netif *inp) +{ + struct icmp6_hdr *icmp6hdr; + struct pbuf *r; + const ip6_addr_t *reply_src; + + ICMP6_STATS_INC(icmp6.recv); + + /* Check that ICMPv6 header fits in payload */ + if (p->len < sizeof(struct icmp6_hdr)) { + /* drop short packets */ + pbuf_free(p); + ICMP6_STATS_INC(icmp6.lenerr); + ICMP6_STATS_INC(icmp6.drop); + return; + } + + icmp6hdr = (struct icmp6_hdr *)p->payload; + +#if CHECKSUM_CHECK_ICMP6 + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_ICMP6) { + if (ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->tot_len, ip6_current_src_addr(), + ip6_current_dest_addr()) != 0) { + /* Checksum failed */ + pbuf_free(p); + ICMP6_STATS_INC(icmp6.chkerr); + ICMP6_STATS_INC(icmp6.drop); + return; + } + } +#endif /* CHECKSUM_CHECK_ICMP6 */ + + switch (icmp6hdr->type) { + case ICMP6_TYPE_NA: /* Neighbor advertisement */ + case ICMP6_TYPE_NS: /* Neighbor solicitation */ + case ICMP6_TYPE_RA: /* Router advertisement */ + case ICMP6_TYPE_RD: /* Redirect */ + case ICMP6_TYPE_PTB: /* Packet too big */ + nd6_input(p, inp); + return; + case ICMP6_TYPE_RS: +#if LWIP_IPV6_FORWARD + /* @todo implement router functionality */ +#endif + break; +#if LWIP_IPV6_MLD + case ICMP6_TYPE_MLQ: + case ICMP6_TYPE_MLR: + case ICMP6_TYPE_MLD: + mld6_input(p, inp); + return; +#endif + case ICMP6_TYPE_EREQ: +#if !LWIP_MULTICAST_PING + /* multicast destination address? */ + if (ip6_addr_ismulticast(ip6_current_dest_addr())) { + /* drop */ + pbuf_free(p); + ICMP6_STATS_INC(icmp6.drop); + return; + } +#endif /* LWIP_MULTICAST_PING */ + + /* Allocate reply. */ + r = pbuf_alloc(PBUF_IP, p->tot_len, PBUF_RAM); + if (r == NULL) { + /* drop */ + pbuf_free(p); + ICMP6_STATS_INC(icmp6.memerr); + return; + } + + /* Copy echo request. */ + if (pbuf_copy(r, p) != ERR_OK) { + /* drop */ + pbuf_free(p); + pbuf_free(r); + ICMP6_STATS_INC(icmp6.err); + return; + } + + /* Determine reply source IPv6 address. */ +#if LWIP_MULTICAST_PING + if (ip6_addr_ismulticast(ip6_current_dest_addr())) { + reply_src = ip_2_ip6(ip6_select_source_address(inp, ip6_current_src_addr())); + if (reply_src == NULL) { + /* drop */ + pbuf_free(p); + pbuf_free(r); + ICMP6_STATS_INC(icmp6.rterr); + return; + } + } + else +#endif /* LWIP_MULTICAST_PING */ + { + reply_src = ip6_current_dest_addr(); + } + + /* Set fields in reply. */ + ((struct icmp6_echo_hdr *)(r->payload))->type = ICMP6_TYPE_EREP; + ((struct icmp6_echo_hdr *)(r->payload))->chksum = 0; +#if CHECKSUM_GEN_ICMP6 + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_GEN_ICMP6) { + ((struct icmp6_echo_hdr *)(r->payload))->chksum = ip6_chksum_pseudo(r, + IP6_NEXTH_ICMP6, r->tot_len, reply_src, ip6_current_src_addr()); + } +#endif /* CHECKSUM_GEN_ICMP6 */ + + /* Send reply. */ + ICMP6_STATS_INC(icmp6.xmit); + ip6_output_if(r, reply_src, ip6_current_src_addr(), + LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, inp); + pbuf_free(r); + + break; + default: + ICMP6_STATS_INC(icmp6.proterr); + ICMP6_STATS_INC(icmp6.drop); + break; + } + + pbuf_free(p); +} + + +/** + * Send an icmpv6 'destination unreachable' packet. + * + * This function must be used only in direct response to a packet that is being + * received right now. Otherwise, address zones would be lost. + * + * @param p the input packet for which the 'unreachable' should be sent, + * p->payload pointing to the IPv6 header + * @param c ICMPv6 code for the unreachable type + */ +void +icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c) +{ + icmp6_send_response(p, c, 0, ICMP6_TYPE_DUR); +} + +/** + * Send an icmpv6 'packet too big' packet. + * + * This function must be used only in direct response to a packet that is being + * received right now. Otherwise, address zones would be lost. + * + * @param p the input packet for which the 'packet too big' should be sent, + * p->payload pointing to the IPv6 header + * @param mtu the maximum mtu that we can accept + */ +void +icmp6_packet_too_big(struct pbuf *p, u32_t mtu) +{ + icmp6_send_response(p, 0, mtu, ICMP6_TYPE_PTB); +} + +/** + * Send an icmpv6 'time exceeded' packet. + * + * This function must be used only in direct response to a packet that is being + * received right now. Otherwise, address zones would be lost. + * + * @param p the input packet for which the 'time exceeded' should be sent, + * p->payload pointing to the IPv6 header + * @param c ICMPv6 code for the time exceeded type + */ +void +icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c) +{ + icmp6_send_response(p, c, 0, ICMP6_TYPE_TE); +} + +/** + * Send an icmpv6 'time exceeded' packet, with explicit source and destination + * addresses. + * + * This function may be used to send a response sometime after receiving the + * packet for which this response is meant. The provided source and destination + * addresses are used primarily to retain their zone information. + * + * @param p the input packet for which the 'time exceeded' should be sent, + * p->payload pointing to the IPv6 header + * @param c ICMPv6 code for the time exceeded type + * @param src_addr source address of the original packet, with zone information + * @param dest_addr destination address of the original packet, with zone + * information + */ +void +icmp6_time_exceeded_with_addrs(struct pbuf *p, enum icmp6_te_code c, + const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr) +{ + icmp6_send_response_with_addrs(p, c, 0, ICMP6_TYPE_TE, src_addr, dest_addr); +} + +/** + * Send an icmpv6 'parameter problem' packet. + * + * This function must be used only in direct response to a packet that is being + * received right now. Otherwise, address zones would be lost and the calculated + * offset would be wrong (calculated against ip6_current_header()). + * + * @param p the input packet for which the 'param problem' should be sent, + * p->payload pointing to the IP header + * @param c ICMPv6 code for the param problem type + * @param pointer the pointer to the byte where the parameter is found + */ +void +icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, const void *pointer) +{ + u32_t pointer_u32 = (u32_t)((const u8_t *)pointer - (const u8_t *)ip6_current_header()); + icmp6_send_response(p, c, pointer_u32, ICMP6_TYPE_PP); +} + +/** + * Send an ICMPv6 packet in response to an incoming packet. + * The packet is sent *to* ip_current_src_addr() on ip_current_netif(). + * + * @param p the input packet for which the response should be sent, + * p->payload pointing to the IPv6 header + * @param code Code of the ICMPv6 header + * @param data Additional 32-bit parameter in the ICMPv6 header + * @param type Type of the ICMPv6 header + */ +static void +icmp6_send_response(struct pbuf *p, u8_t code, u32_t data, u8_t type) +{ + const struct ip6_addr *reply_src, *reply_dest; + struct netif *netif = ip_current_netif(); + + LWIP_ASSERT("icmpv6 packet not a direct response", netif != NULL); + reply_dest = ip6_current_src_addr(); + + /* Select an address to use as source. */ + reply_src = ip_2_ip6(ip6_select_source_address(netif, reply_dest)); + if (reply_src == NULL) { + ICMP6_STATS_INC(icmp6.rterr); + return; + } + icmp6_send_response_with_addrs_and_netif(p, code, data, type, reply_src, reply_dest, netif); +} + +/** + * Send an ICMPv6 packet in response to an incoming packet. + * + * Call this function if the packet is NOT sent as a direct response to an + * incoming packet, but rather sometime later (e.g. for a fragment reassembly + * timeout). The caller must provide the zoned source and destination addresses + * from the original packet with the src_addr and dest_addr parameters. The + * reason for this approach is that while the addresses themselves are part of + * the original packet, their zone information is not, thus possibly resulting + * in a link-local response being sent over the wrong link. + * + * @param p the input packet for which the response should be sent, + * p->payload pointing to the IPv6 header + * @param code Code of the ICMPv6 header + * @param data Additional 32-bit parameter in the ICMPv6 header + * @param type Type of the ICMPv6 header + * @param src_addr original source address + * @param dest_addr original destination address + */ +static void +icmp6_send_response_with_addrs(struct pbuf *p, u8_t code, u32_t data, u8_t type, + const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr) +{ + const struct ip6_addr *reply_src, *reply_dest; + struct netif *netif; + + /* Get the destination address and netif for this ICMP message. */ + LWIP_ASSERT("must provide both source and destination", src_addr != NULL); + LWIP_ASSERT("must provide both source and destination", dest_addr != NULL); + + /* Special case, as ip6_current_xxx is either NULL, or points + to a different packet than the one that expired. */ + IP6_ADDR_ZONECHECK(src_addr); + IP6_ADDR_ZONECHECK(dest_addr); + /* Swap source and destination for the reply. */ + reply_dest = src_addr; + reply_src = dest_addr; + netif = ip6_route(reply_src, reply_dest); + if (netif == NULL) { + ICMP6_STATS_INC(icmp6.rterr); + return; + } + icmp6_send_response_with_addrs_and_netif(p, code, data, type, reply_src, + reply_dest, netif); +} + +/** + * Send an ICMPv6 packet (with srd/dst address and netif given). + * + * @param p the input packet for which the response should be sent, + * p->payload pointing to the IPv6 header + * @param code Code of the ICMPv6 header + * @param data Additional 32-bit parameter in the ICMPv6 header + * @param type Type of the ICMPv6 header + * @param reply_src source address of the packet to send + * @param reply_dest destination address of the packet to send + * @param netif netif to send the packet + */ +static void +icmp6_send_response_with_addrs_and_netif(struct pbuf *p, u8_t code, u32_t data, u8_t type, + const ip6_addr_t *reply_src, const ip6_addr_t *reply_dest, struct netif *netif) +{ + struct pbuf *q; + struct icmp6_hdr *icmp6hdr; + + /* ICMPv6 header + IPv6 header + data */ + q = pbuf_alloc(PBUF_IP, sizeof(struct icmp6_hdr) + IP6_HLEN + LWIP_ICMP6_DATASIZE, + PBUF_RAM); + if (q == NULL) { + LWIP_DEBUGF(ICMP_DEBUG, ("icmp_time_exceeded: failed to allocate pbuf for ICMPv6 packet.\n")); + ICMP6_STATS_INC(icmp6.memerr); + return; + } + LWIP_ASSERT("check that first pbuf can hold icmp 6message", + (q->len >= (sizeof(struct icmp6_hdr) + IP6_HLEN + LWIP_ICMP6_DATASIZE))); + + icmp6hdr = (struct icmp6_hdr *)q->payload; + icmp6hdr->type = type; + icmp6hdr->code = code; + icmp6hdr->data = lwip_htonl(data); + + /* copy fields from original packet */ + SMEMCPY((u8_t *)q->payload + sizeof(struct icmp6_hdr), (u8_t *)p->payload, + IP6_HLEN + LWIP_ICMP6_DATASIZE); + + /* calculate checksum */ + icmp6hdr->chksum = 0; +#if CHECKSUM_GEN_ICMP6 + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { + icmp6hdr->chksum = ip6_chksum_pseudo(q, IP6_NEXTH_ICMP6, q->tot_len, + reply_src, reply_dest); + } +#endif /* CHECKSUM_GEN_ICMP6 */ + + ICMP6_STATS_INC(icmp6.xmit); + ip6_output_if(q, reply_src, reply_dest, LWIP_ICMP6_HL, 0, IP6_NEXTH_ICMP6, netif); + pbuf_free(q); +} + +#endif /* LWIP_ICMP6 && LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c new file mode 100644 index 0000000..d9a992c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/inet6.c @@ -0,0 +1,53 @@ +/** + * @file + * + * INET v6 addresses. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV6 && LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/inet.h" + +/** This variable is initialized by the system to contain the wildcard IPv6 address. + */ +const struct in6_addr in6addr_any = IN6ADDR_ANY_INIT; + +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c new file mode 100644 index 0000000..eda11dc --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6.c @@ -0,0 +1,1492 @@ +/** + * @file + * + * IPv6 layer. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/netif.h" +#include "lwip/ip.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/ip6_frag.h" +#include "lwip/icmp6.h" +#include "lwip/priv/raw_priv.h" +#include "lwip/udp.h" +#include "lwip/priv/tcp_priv.h" +#include "lwip/dhcp6.h" +#include "lwip/nd6.h" +#include "lwip/mld6.h" +#include "lwip/debug.h" +#include "lwip/stats.h" + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +/** + * Finds the appropriate network interface for a given IPv6 address. It tries to select + * a netif following a sequence of heuristics: + * 1) if there is only 1 netif, return it + * 2) if the destination is a zoned address, match its zone to a netif + * 3) if the either the source or destination address is a scoped address, + * match the source address's zone (if set) or address (if not) to a netif + * 4) tries to match the destination subnet to a configured address + * 5) tries to find a router-announced route + * 6) tries to match the (unscoped) source address to the netif + * 7) returns the default netif, if configured + * + * Note that each of the two given addresses may or may not be properly zoned. + * + * @param src the source IPv6 address, if known + * @param dest the destination IPv6 address for which to find the route + * @return the netif on which to send to reach dest + */ +struct netif * +ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest) +{ +#if LWIP_SINGLE_NETIF + LWIP_UNUSED_ARG(src); + LWIP_UNUSED_ARG(dest); +#else /* LWIP_SINGLE_NETIF */ + struct netif *netif; + s8_t i; + + LWIP_ASSERT_CORE_LOCKED(); + + /* If single netif configuration, fast return. */ + if ((netif_list != NULL) && (netif_list->next == NULL)) { + if (!netif_is_up(netif_list) || !netif_is_link_up(netif_list) || + (ip6_addr_has_zone(dest) && !ip6_addr_test_zone(dest, netif_list))) { + return NULL; + } + return netif_list; + } + +#if LWIP_IPV6_SCOPES + /* Special processing for zoned destination addresses. This includes link- + * local unicast addresses and interface/link-local multicast addresses. Use + * the zone to find a matching netif. If the address is not zoned, then there + * is technically no "wrong" netif to choose, and we leave routing to other + * rules; in most cases this should be the scoped-source rule below. */ + if (ip6_addr_has_zone(dest)) { + IP6_ADDR_ZONECHECK(dest); + /* Find a netif based on the zone. For custom mappings, one zone may map + * to multiple netifs, so find one that can actually send a packet. */ + NETIF_FOREACH(netif) { + if (ip6_addr_test_zone(dest, netif) && + netif_is_up(netif) && netif_is_link_up(netif)) { + return netif; + } + } + /* No matching netif found. Do no try to route to a different netif, + * as that would be a zone violation, resulting in any packets sent to + * that netif being dropped on output. */ + return NULL; + } +#endif /* LWIP_IPV6_SCOPES */ + + /* Special processing for scoped source and destination addresses. If we get + * here, the destination address does not have a zone, so either way we need + * to look at the source address, which may or may not have a zone. If it + * does, the zone is restrictive: there is (typically) only one matching + * netif for it, and we should avoid routing to any other netif as that would + * result in guaranteed zone violations. For scoped source addresses that do + * not have a zone, use (only) a netif that has that source address locally + * assigned. This case also applies to the loopback source address, which has + * an implied link-local scope. If only the destination address is scoped + * (but, again, not zoned), we still want to use only the source address to + * determine its zone because that's most likely what the user/application + * wants, regardless of whether the source address is scoped. Finally, some + * of this story also applies if scoping is disabled altogether. */ +#if LWIP_IPV6_SCOPES + if (ip6_addr_has_scope(dest, IP6_UNKNOWN) || + ip6_addr_has_scope(src, IP6_UNICAST) || +#else /* LWIP_IPV6_SCOPES */ + if (ip6_addr_islinklocal(dest) || ip6_addr_ismulticast_iflocal(dest) || + ip6_addr_ismulticast_linklocal(dest) || ip6_addr_islinklocal(src) || +#endif /* LWIP_IPV6_SCOPES */ + ip6_addr_isloopback(src)) { +#if LWIP_IPV6_SCOPES + if (ip6_addr_has_zone(src)) { + /* Find a netif matching the source zone (relatively cheap). */ + NETIF_FOREACH(netif) { + if (netif_is_up(netif) && netif_is_link_up(netif) && + ip6_addr_test_zone(src, netif)) { + return netif; + } + } + } else +#endif /* LWIP_IPV6_SCOPES */ + { + /* Find a netif matching the source address (relatively expensive). */ + NETIF_FOREACH(netif) { + if (!netif_is_up(netif) || !netif_is_link_up(netif)) { + continue; + } + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && + ip6_addr_cmp_zoneless(src, netif_ip6_addr(netif, i))) { + return netif; + } + } + } + } + /* Again, do not use any other netif in this case, as that could result in + * zone boundary violations. */ + return NULL; + } + + /* We come here only if neither source nor destination is scoped. */ + IP6_ADDR_ZONECHECK(src); + +#ifdef LWIP_HOOK_IP6_ROUTE + netif = LWIP_HOOK_IP6_ROUTE(src, dest); + if (netif != NULL) { + return netif; + } +#endif + + /* See if the destination subnet matches a configured address. In accordance + * with RFC 5942, dynamically configured addresses do not have an implied + * local subnet, and thus should be considered /128 assignments. However, as + * such, the destination address may still match a local address, and so we + * still need to check for exact matches here. By (lwIP) policy, statically + * configured addresses do always have an implied local /64 subnet. */ + NETIF_FOREACH(netif) { + if (!netif_is_up(netif) || !netif_is_link_up(netif)) { + continue; + } + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && + ip6_addr_netcmp(dest, netif_ip6_addr(netif, i)) && + (netif_ip6_addr_isstatic(netif, i) || + ip6_addr_nethostcmp(dest, netif_ip6_addr(netif, i)))) { + return netif; + } + } + } + + /* Get the netif for a suitable router-announced route. */ + netif = nd6_find_route(dest); + if (netif != NULL) { + return netif; + } + + /* Try with the netif that matches the source address. Given the earlier rule + * for scoped source addresses, this applies to unscoped addresses only. */ + if (!ip6_addr_isany(src)) { + NETIF_FOREACH(netif) { + if (!netif_is_up(netif) || !netif_is_link_up(netif)) { + continue; + } + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && + ip6_addr_cmp(src, netif_ip6_addr(netif, i))) { + return netif; + } + } + } + } + +#if LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF + /* loopif is disabled, loopback traffic is passed through any netif */ + if (ip6_addr_isloopback(dest)) { + /* don't check for link on loopback traffic */ + if (netif_default != NULL && netif_is_up(netif_default)) { + return netif_default; + } + /* default netif is not up, just use any netif for loopback traffic */ + NETIF_FOREACH(netif) { + if (netif_is_up(netif)) { + return netif; + } + } + return NULL; + } +#endif /* LWIP_NETIF_LOOPBACK && !LWIP_HAVE_LOOPIF */ +#endif /* !LWIP_SINGLE_NETIF */ + + /* no matching netif found, use default netif, if up */ + if ((netif_default == NULL) || !netif_is_up(netif_default) || !netif_is_link_up(netif_default)) { + return NULL; + } + return netif_default; +} + +/** + * @ingroup ip6 + * Select the best IPv6 source address for a given destination IPv6 address. + * + * This implementation follows RFC 6724 Sec. 5 to the following extent: + * - Rules 1, 2, 3: fully implemented + * - Rules 4, 5, 5.5: not applicable + * - Rule 6: not implemented + * - Rule 7: not applicable + * - Rule 8: limited to "prefer /64 subnet match over non-match" + * + * For Rule 2, we deliberately deviate from RFC 6724 Sec. 3.1 by considering + * ULAs to be of smaller scope than global addresses, to avoid that a preferred + * ULA is picked over a deprecated global address when given a global address + * as destination, as that would likely result in broken two-way communication. + * + * As long as temporary addresses are not supported (as used in Rule 7), a + * proper implementation of Rule 8 would obviate the need to implement Rule 6. + * + * @param netif the netif on which to send a packet + * @param dest the destination we are trying to reach (possibly not properly + * zoned) + * @return the most suitable source address to use, or NULL if no suitable + * source address is found + */ +const ip_addr_t * +ip6_select_source_address(struct netif *netif, const ip6_addr_t *dest) +{ + const ip_addr_t *best_addr; + const ip6_addr_t *cand_addr; + s8_t dest_scope, cand_scope; + s8_t best_scope = IP6_MULTICAST_SCOPE_RESERVED; + u8_t i, cand_pref, cand_bits; + u8_t best_pref = 0; + u8_t best_bits = 0; + + /* Start by determining the scope of the given destination address. These + * tests are hopefully (roughly) in order of likeliness to match. */ + if (ip6_addr_isglobal(dest)) { + dest_scope = IP6_MULTICAST_SCOPE_GLOBAL; + } else if (ip6_addr_islinklocal(dest) || ip6_addr_isloopback(dest)) { + dest_scope = IP6_MULTICAST_SCOPE_LINK_LOCAL; + } else if (ip6_addr_isuniquelocal(dest)) { + dest_scope = IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL; + } else if (ip6_addr_ismulticast(dest)) { + dest_scope = ip6_addr_multicast_scope(dest); + } else if (ip6_addr_issitelocal(dest)) { + dest_scope = IP6_MULTICAST_SCOPE_SITE_LOCAL; + } else { + /* no match, consider scope global */ + dest_scope = IP6_MULTICAST_SCOPE_GLOBAL; + } + + best_addr = NULL; + + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + /* Consider only valid (= preferred and deprecated) addresses. */ + if (!ip6_addr_isvalid(netif_ip6_addr_state(netif, i))) { + continue; + } + /* Determine the scope of this candidate address. Same ordering idea. */ + cand_addr = netif_ip6_addr(netif, i); + if (ip6_addr_isglobal(cand_addr)) { + cand_scope = IP6_MULTICAST_SCOPE_GLOBAL; + } else if (ip6_addr_islinklocal(cand_addr)) { + cand_scope = IP6_MULTICAST_SCOPE_LINK_LOCAL; + } else if (ip6_addr_isuniquelocal(cand_addr)) { + cand_scope = IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL; + } else if (ip6_addr_issitelocal(cand_addr)) { + cand_scope = IP6_MULTICAST_SCOPE_SITE_LOCAL; + } else { + /* no match, treat as low-priority global scope */ + cand_scope = IP6_MULTICAST_SCOPE_RESERVEDF; + } + cand_pref = ip6_addr_ispreferred(netif_ip6_addr_state(netif, i)); + /* @todo compute the actual common bits, for longest matching prefix. */ + /* We cannot count on the destination address having a proper zone + * assignment, so do not compare zones in this case. */ + cand_bits = ip6_addr_netcmp_zoneless(cand_addr, dest); /* just 1 or 0 for now */ + if (cand_bits && ip6_addr_nethostcmp(cand_addr, dest)) { + return netif_ip_addr6(netif, i); /* Rule 1 */ + } + if ((best_addr == NULL) || /* no alternative yet */ + ((cand_scope < best_scope) && (cand_scope >= dest_scope)) || + ((cand_scope > best_scope) && (best_scope < dest_scope)) || /* Rule 2 */ + ((cand_scope == best_scope) && ((cand_pref > best_pref) || /* Rule 3 */ + ((cand_pref == best_pref) && (cand_bits > best_bits))))) { /* Rule 8 */ + /* We found a new "winning" candidate. */ + best_addr = netif_ip_addr6(netif, i); + best_scope = cand_scope; + best_pref = cand_pref; + best_bits = cand_bits; + } + } + + return best_addr; /* may be NULL */ +} + +#if LWIP_IPV6_FORWARD +/** + * Forwards an IPv6 packet. It finds an appropriate route for the + * packet, decrements the HL value of the packet, and outputs + * the packet on the appropriate interface. + * + * @param p the packet to forward (p->payload points to IP header) + * @param iphdr the IPv6 header of the input packet + * @param inp the netif on which this packet was received + */ +static void +ip6_forward(struct pbuf *p, struct ip6_hdr *iphdr, struct netif *inp) +{ + struct netif *netif; + + /* do not forward link-local or loopback addresses */ + if (ip6_addr_islinklocal(ip6_current_dest_addr()) || + ip6_addr_isloopback(ip6_current_dest_addr())) { + LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not forwarding link-local address.\n")); + IP6_STATS_INC(ip6.rterr); + IP6_STATS_INC(ip6.drop); + return; + } + + /* Find network interface where to forward this IP packet to. */ + netif = ip6_route(IP6_ADDR_ANY6, ip6_current_dest_addr()); + if (netif == NULL) { + LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", + IP6_ADDR_BLOCK1(ip6_current_dest_addr()), + IP6_ADDR_BLOCK2(ip6_current_dest_addr()), + IP6_ADDR_BLOCK3(ip6_current_dest_addr()), + IP6_ADDR_BLOCK4(ip6_current_dest_addr()), + IP6_ADDR_BLOCK5(ip6_current_dest_addr()), + IP6_ADDR_BLOCK6(ip6_current_dest_addr()), + IP6_ADDR_BLOCK7(ip6_current_dest_addr()), + IP6_ADDR_BLOCK8(ip6_current_dest_addr()))); +#if LWIP_ICMP6 + /* Don't send ICMP messages in response to ICMP messages */ + if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) { + icmp6_dest_unreach(p, ICMP6_DUR_NO_ROUTE); + } +#endif /* LWIP_ICMP6 */ + IP6_STATS_INC(ip6.rterr); + IP6_STATS_INC(ip6.drop); + return; + } +#if LWIP_IPV6_SCOPES + /* Do not forward packets with a zoned (e.g., link-local) source address + * outside of their zone. We determined the zone a bit earlier, so we know + * that the address is properly zoned here, so we can safely use has_zone. + * Also skip packets with a loopback source address (link-local implied). */ + if ((ip6_addr_has_zone(ip6_current_src_addr()) && + !ip6_addr_test_zone(ip6_current_src_addr(), netif)) || + ip6_addr_isloopback(ip6_current_src_addr())) { + LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not forwarding packet beyond its source address zone.\n")); + IP6_STATS_INC(ip6.rterr); + IP6_STATS_INC(ip6.drop); + return; + } +#endif /* LWIP_IPV6_SCOPES */ + /* Do not forward packets onto the same network interface on which + * they arrived. */ + if (netif == inp) { + LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: not bouncing packets back on incoming interface.\n")); + IP6_STATS_INC(ip6.rterr); + IP6_STATS_INC(ip6.drop); + return; + } + + /* decrement HL */ + IP6H_HOPLIM_SET(iphdr, IP6H_HOPLIM(iphdr) - 1); + /* send ICMP6 if HL == 0 */ + if (IP6H_HOPLIM(iphdr) == 0) { +#if LWIP_ICMP6 + /* Don't send ICMP messages in response to ICMP messages */ + if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) { + icmp6_time_exceeded(p, ICMP6_TE_HL); + } +#endif /* LWIP_ICMP6 */ + IP6_STATS_INC(ip6.drop); + return; + } + + if (netif->mtu && (p->tot_len > netif->mtu)) { +#if LWIP_ICMP6 + /* Don't send ICMP messages in response to ICMP messages */ + if (IP6H_NEXTH(iphdr) != IP6_NEXTH_ICMP6) { + icmp6_packet_too_big(p, netif->mtu); + } +#endif /* LWIP_ICMP6 */ + IP6_STATS_INC(ip6.drop); + return; + } + + LWIP_DEBUGF(IP6_DEBUG, ("ip6_forward: forwarding packet to %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", + IP6_ADDR_BLOCK1(ip6_current_dest_addr()), + IP6_ADDR_BLOCK2(ip6_current_dest_addr()), + IP6_ADDR_BLOCK3(ip6_current_dest_addr()), + IP6_ADDR_BLOCK4(ip6_current_dest_addr()), + IP6_ADDR_BLOCK5(ip6_current_dest_addr()), + IP6_ADDR_BLOCK6(ip6_current_dest_addr()), + IP6_ADDR_BLOCK7(ip6_current_dest_addr()), + IP6_ADDR_BLOCK8(ip6_current_dest_addr()))); + + /* transmit pbuf on chosen interface */ + netif->output_ip6(netif, p, ip6_current_dest_addr()); + IP6_STATS_INC(ip6.fw); + IP6_STATS_INC(ip6.xmit); + return; +} +#endif /* LWIP_IPV6_FORWARD */ + +/** Return true if the current input packet should be accepted on this netif */ +static int +ip6_input_accept(struct netif *netif) +{ + /* interface is up? */ + if (netif_is_up(netif)) { + u8_t i; + /* unicast to this interface address? address configured? */ + /* If custom scopes are used, the destination zone will be tested as + * part of the local-address comparison, but we need to test the source + * scope as well (e.g., is this interface on the same link?). */ + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && + ip6_addr_cmp(ip6_current_dest_addr(), netif_ip6_addr(netif, i)) +#if IPV6_CUSTOM_SCOPES + && (!ip6_addr_has_zone(ip6_current_src_addr()) || + ip6_addr_test_zone(ip6_current_src_addr(), netif)) +#endif /* IPV6_CUSTOM_SCOPES */ + ) { + /* accept on this netif */ + return 1; + } + } + } + return 0; +} + +/** + * This function is called by the network interface device driver when + * an IPv6 packet is received. The function does the basic checks of the + * IP header such as packet size being at least larger than the header + * size etc. If the packet was not destined for us, the packet is + * forwarded (using ip6_forward). + * + * Finally, the packet is sent to the upper layer protocol input function. + * + * @param p the received IPv6 packet (p->payload points to IPv6 header) + * @param inp the netif on which this packet was received + * @return ERR_OK if the packet was processed (could return ERR_* if it wasn't + * processed, but currently always returns ERR_OK) + */ +err_t +ip6_input(struct pbuf *p, struct netif *inp) +{ + struct ip6_hdr *ip6hdr; + struct netif *netif; + const u8_t *nexth; + u16_t hlen, hlen_tot; /* the current header length */ +#if 0 /*IP_ACCEPT_LINK_LAYER_ADDRESSING*/ + @todo + int check_ip_src=1; +#endif /* IP_ACCEPT_LINK_LAYER_ADDRESSING */ +#if LWIP_RAW + raw_input_state_t raw_status; +#endif /* LWIP_RAW */ + + LWIP_ASSERT_CORE_LOCKED(); + + IP6_STATS_INC(ip6.recv); + + /* identify the IP header */ + ip6hdr = (struct ip6_hdr *)p->payload; + if (IP6H_V(ip6hdr) != 6) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_WARNING, ("IPv6 packet dropped due to bad version number %"U32_F"\n", + IP6H_V(ip6hdr))); + pbuf_free(p); + IP6_STATS_INC(ip6.err); + IP6_STATS_INC(ip6.drop); + return ERR_OK; + } + +#ifdef LWIP_HOOK_IP6_INPUT + if (LWIP_HOOK_IP6_INPUT(p, inp)) { + /* the packet has been eaten */ + return ERR_OK; + } +#endif + + /* header length exceeds first pbuf length, or ip length exceeds total pbuf length? */ + if ((IP6_HLEN > p->len) || (IP6H_PLEN(ip6hdr) > (p->tot_len - IP6_HLEN))) { + if (IP6_HLEN > p->len) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IPv6 header (len %"U16_F") does not fit in first pbuf (len %"U16_F"), IP packet dropped.\n", + (u16_t)IP6_HLEN, p->len)); + } + if ((IP6H_PLEN(ip6hdr) + IP6_HLEN) > p->tot_len) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IPv6 (plen %"U16_F") is longer than pbuf (len %"U16_F"), IP packet dropped.\n", + (u16_t)(IP6H_PLEN(ip6hdr) + IP6_HLEN), p->tot_len)); + } + /* free (drop) packet pbufs */ + pbuf_free(p); + IP6_STATS_INC(ip6.lenerr); + IP6_STATS_INC(ip6.drop); + return ERR_OK; + } + + /* Trim pbuf. This should have been done at the netif layer, + * but we'll do it anyway just to be sure that its done. */ + pbuf_realloc(p, (u16_t)(IP6_HLEN + IP6H_PLEN(ip6hdr))); + + /* copy IP addresses to aligned ip6_addr_t */ + ip_addr_copy_from_ip6_packed(ip_data.current_iphdr_dest, ip6hdr->dest); + ip_addr_copy_from_ip6_packed(ip_data.current_iphdr_src, ip6hdr->src); + + /* Don't accept virtual IPv4 mapped IPv6 addresses. + * Don't accept multicast source addresses. */ + if (ip6_addr_isipv4mappedipv6(ip_2_ip6(&ip_data.current_iphdr_dest)) || + ip6_addr_isipv4mappedipv6(ip_2_ip6(&ip_data.current_iphdr_src)) || + ip6_addr_ismulticast(ip_2_ip6(&ip_data.current_iphdr_src))) { + /* free (drop) packet pbufs */ + pbuf_free(p); + IP6_STATS_INC(ip6.err); + IP6_STATS_INC(ip6.drop); + return ERR_OK; + } + + /* Set the appropriate zone identifier on the addresses. */ + ip6_addr_assign_zone(ip_2_ip6(&ip_data.current_iphdr_dest), IP6_UNKNOWN, inp); + ip6_addr_assign_zone(ip_2_ip6(&ip_data.current_iphdr_src), IP6_UNICAST, inp); + + /* current header pointer. */ + ip_data.current_ip6_header = ip6hdr; + + /* In netif, used in case we need to send ICMPv6 packets back. */ + ip_data.current_netif = inp; + ip_data.current_input_netif = inp; + + /* match packet against an interface, i.e. is this packet for us? */ + if (ip6_addr_ismulticast(ip6_current_dest_addr())) { + /* Always joined to multicast if-local and link-local all-nodes group. */ + if (ip6_addr_isallnodes_iflocal(ip6_current_dest_addr()) || + ip6_addr_isallnodes_linklocal(ip6_current_dest_addr())) { + netif = inp; + } +#if LWIP_IPV6_MLD + else if (mld6_lookfor_group(inp, ip6_current_dest_addr())) { + netif = inp; + } +#else /* LWIP_IPV6_MLD */ + else if (ip6_addr_issolicitednode(ip6_current_dest_addr())) { + u8_t i; + /* Filter solicited node packets when MLD is not enabled + * (for Neighbor discovery). */ + netif = NULL; + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(inp, i)) && + ip6_addr_cmp_solicitednode(ip6_current_dest_addr(), netif_ip6_addr(inp, i))) { + netif = inp; + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: solicited node packet accepted on interface %c%c\n", + netif->name[0], netif->name[1])); + break; + } + } + } +#endif /* LWIP_IPV6_MLD */ + else { + netif = NULL; + } + } else { + /* start trying with inp. if that's not acceptable, start walking the + list of configured netifs. */ + if (ip6_input_accept(inp)) { + netif = inp; + } else { + netif = NULL; +#if !IPV6_CUSTOM_SCOPES + /* Shortcut: stop looking for other interfaces if either the source or + * the destination has a scope constrained to this interface. Custom + * scopes may break the 1:1 link/interface mapping, however. */ + if (ip6_addr_islinklocal(ip6_current_dest_addr()) || + ip6_addr_islinklocal(ip6_current_src_addr())) { + goto netif_found; + } +#endif /* !IPV6_CUSTOM_SCOPES */ +#if !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF + /* The loopback address is to be considered link-local. Packets to it + * should be dropped on other interfaces, as per RFC 4291 Sec. 2.5.3. + * Its implied scope means packets *from* the loopback address should + * not be accepted on other interfaces, either. These requirements + * cannot be implemented in the case that loopback traffic is sent + * across a non-loopback interface, however. */ + if (ip6_addr_isloopback(ip6_current_dest_addr()) || + ip6_addr_isloopback(ip6_current_src_addr())) { + goto netif_found; + } +#endif /* !LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF */ +#if !LWIP_SINGLE_NETIF + NETIF_FOREACH(netif) { + if (netif == inp) { + /* we checked that before already */ + continue; + } + if (ip6_input_accept(netif)) { + break; + } + } +#endif /* !LWIP_SINGLE_NETIF */ + } +netif_found: + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet accepted on interface %c%c\n", + netif ? netif->name[0] : 'X', netif? netif->name[1] : 'X')); + } + + /* "::" packet source address? (used in duplicate address detection) */ + if (ip6_addr_isany(ip6_current_src_addr()) && + (!ip6_addr_issolicitednode(ip6_current_dest_addr()))) { + /* packet source is not valid */ + /* free (drop) packet pbufs */ + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with src ANY_ADDRESS dropped\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + + /* packet not for us? */ + if (netif == NULL) { + /* packet not for us, route or discard */ + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_TRACE, ("ip6_input: packet not for us.\n")); +#if LWIP_IPV6_FORWARD + /* non-multicast packet? */ + if (!ip6_addr_ismulticast(ip6_current_dest_addr())) { + /* try to forward IP packet on (other) interfaces */ + ip6_forward(p, ip6hdr, inp); + } +#endif /* LWIP_IPV6_FORWARD */ + pbuf_free(p); + goto ip6_input_cleanup; + } + + /* current netif pointer. */ + ip_data.current_netif = netif; + + /* Save next header type. */ + nexth = &IP6H_NEXTH(ip6hdr); + + /* Init header length. */ + hlen = hlen_tot = IP6_HLEN; + + /* Move to payload. */ + pbuf_remove_header(p, IP6_HLEN); + + /* Process known option extension headers, if present. */ + while (*nexth != IP6_NEXTH_NONE) + { + switch (*nexth) { + case IP6_NEXTH_HOPBYHOP: + { + s32_t opt_offset; + struct ip6_hbh_hdr *hbh_hdr; + struct ip6_opt_hdr *opt_hdr; + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Hop-by-Hop options header\n")); + + /* Get and check the header length, while staying in packet bounds. */ + hbh_hdr = (struct ip6_hbh_hdr *)p->payload; + + /* Get next header type. */ + nexth = &IP6_HBH_NEXTH(hbh_hdr); + + /* Get the header length. */ + hlen = (u16_t)(8 * (1 + hbh_hdr->_hlen)); + + if ((p->len < 8) || (hlen > p->len)) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", + hlen, p->len)); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP6_STATS_INC(ip6.lenerr); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + + hlen_tot = (u16_t)(hlen_tot + hlen); + + /* The extended option header starts right after Hop-by-Hop header. */ + opt_offset = IP6_HBH_HLEN; + while (opt_offset < hlen) + { + s32_t opt_dlen = 0; + + opt_hdr = (struct ip6_opt_hdr *)((u8_t *)hbh_hdr + opt_offset); + + switch (IP6_OPT_TYPE(opt_hdr)) { + /* @todo: process IPV6 Hop-by-Hop option data */ + case IP6_PAD1_OPTION: + /* PAD1 option doesn't have length and value field */ + opt_dlen = -1; + break; + case IP6_PADN_OPTION: + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + case IP6_ROUTER_ALERT_OPTION: + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + case IP6_JUMBO_OPTION: + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + default: + /* Check 2 MSB of Hop-by-Hop header type. */ + switch (IP6_OPT_TYPE_ACTION(opt_hdr)) { + case 1: + /* Discard the packet. */ + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid Hop-by-Hop option type dropped.\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + case 2: + /* Send ICMP Parameter Problem */ + icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr); + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid Hop-by-Hop option type dropped.\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + case 3: + /* Send ICMP Parameter Problem if destination address is not a multicast address */ + if (!ip6_addr_ismulticast(ip6_current_dest_addr())) { + icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr); + } + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid Hop-by-Hop option type dropped.\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + default: + /* Skip over this option. */ + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + } + break; + } + + /* Adjust the offset to move to the next extended option header */ + opt_offset = opt_offset + IP6_OPT_HLEN + opt_dlen; + } + pbuf_remove_header(p, hlen); + break; + } + case IP6_NEXTH_DESTOPTS: + { + s32_t opt_offset; + struct ip6_dest_hdr *dest_hdr; + struct ip6_opt_hdr *opt_hdr; + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Destination options header\n")); + + dest_hdr = (struct ip6_dest_hdr *)p->payload; + + /* Get next header type. */ + nexth = &IP6_DEST_NEXTH(dest_hdr); + + /* Get the header length. */ + hlen = 8 * (1 + dest_hdr->_hlen); + if ((p->len < 8) || (hlen > p->len)) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", + hlen, p->len)); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP6_STATS_INC(ip6.lenerr); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + + hlen_tot = (u16_t)(hlen_tot + hlen); + + /* The extended option header starts right after Destination header. */ + opt_offset = IP6_DEST_HLEN; + while (opt_offset < hlen) + { + s32_t opt_dlen = 0; + + opt_hdr = (struct ip6_opt_hdr *)((u8_t *)dest_hdr + opt_offset); + + switch (IP6_OPT_TYPE(opt_hdr)) + { + /* @todo: process IPV6 Destination option data */ + case IP6_PAD1_OPTION: + /* PAD1 option deosn't have length and value field */ + opt_dlen = -1; + break; + case IP6_PADN_OPTION: + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + case IP6_ROUTER_ALERT_OPTION: + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + case IP6_JUMBO_OPTION: + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + case IP6_HOME_ADDRESS_OPTION: + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + default: + /* Check 2 MSB of Destination header type. */ + switch (IP6_OPT_TYPE_ACTION(opt_hdr)) + { + case 1: + /* Discard the packet. */ + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid destination option type dropped.\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + case 2: + /* Send ICMP Parameter Problem */ + icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr); + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid destination option type dropped.\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + case 3: + /* Send ICMP Parameter Problem if destination address is not a multicast address */ + if (!ip6_addr_ismulticast(ip6_current_dest_addr())) { + icmp6_param_problem(p, ICMP6_PP_OPTION, opt_hdr); + } + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid destination option type dropped.\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + default: + /* Skip over this option. */ + opt_dlen = IP6_OPT_DLEN(opt_hdr); + break; + } + break; + } + + /* Adjust the offset to move to the next extended option header */ + opt_offset = opt_offset + IP6_OPT_HLEN + opt_dlen; + } + + pbuf_remove_header(p, hlen); + break; + } + case IP6_NEXTH_ROUTING: + { + struct ip6_rout_hdr *rout_hdr; + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Routing header\n")); + + rout_hdr = (struct ip6_rout_hdr *)p->payload; + + /* Get next header type. */ + nexth = &IP6_ROUT_NEXTH(rout_hdr); + + /* Get the header length. */ + hlen = 8 * (1 + rout_hdr->_hlen); + + if ((p->len < 8) || (hlen > p->len)) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", + hlen, p->len)); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP6_STATS_INC(ip6.lenerr); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + + /* Skip over this header. */ + hlen_tot = (u16_t)(hlen_tot + hlen); + + /* if segment left value is 0 in routing header, ignore the option */ + if (IP6_ROUT_SEG_LEFT(rout_hdr)) { + /* The length field of routing option header must be even */ + if (rout_hdr->_hlen & 0x1) { + /* Discard and send parameter field error */ + icmp6_param_problem(p, ICMP6_PP_FIELD, &rout_hdr->_hlen); + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid routing type dropped\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + + switch (IP6_ROUT_TYPE(rout_hdr)) + { + /* TODO: process routing by the type */ + case IP6_ROUT_TYPE2: + break; + case IP6_ROUT_RPL: + break; + default: + /* Discard unrecognized routing type and send parameter field error */ + icmp6_param_problem(p, ICMP6_PP_FIELD, &IP6_ROUT_TYPE(rout_hdr)); + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid routing type dropped\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + } + + pbuf_remove_header(p, hlen); + break; + } + case IP6_NEXTH_FRAGMENT: + { + struct ip6_frag_hdr *frag_hdr; + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Fragment header\n")); + + frag_hdr = (struct ip6_frag_hdr *)p->payload; + + /* Get next header type. */ + nexth = &IP6_FRAG_NEXTH(frag_hdr); + + /* Fragment Header length. */ + hlen = 8; + + /* Make sure this header fits in current pbuf. */ + if (hlen > p->len) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("IPv6 options header (hlen %"U16_F") does not fit in first pbuf (len %"U16_F"), IPv6 packet dropped.\n", + hlen, p->len)); + /* free (drop) packet pbufs */ + pbuf_free(p); + IP6_FRAG_STATS_INC(ip6_frag.lenerr); + IP6_FRAG_STATS_INC(ip6_frag.drop); + goto ip6_input_cleanup; + } + + hlen_tot = (u16_t)(hlen_tot + hlen); + + /* check payload length is multiple of 8 octets when mbit is set */ + if (IP6_FRAG_MBIT(frag_hdr) && (IP6H_PLEN(ip6hdr) & 0x7)) { + /* ipv6 payload length is not multiple of 8 octets */ + icmp6_param_problem(p, ICMP6_PP_FIELD, LWIP_PACKED_CAST(const void *, &ip6hdr->_plen)); + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with invalid payload length dropped\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + + /* Offset == 0 and more_fragments == 0? */ + if ((frag_hdr->_fragment_offset & + PP_HTONS(IP6_FRAG_OFFSET_MASK | IP6_FRAG_MORE_FLAG)) == 0) { + /* This is a 1-fragment packet. Skip this header and continue. */ + pbuf_remove_header(p, hlen); + } else { +#if LWIP_IPV6_REASS + /* reassemble the packet */ + ip_data.current_ip_header_tot_len = hlen_tot; + p = ip6_reass(p); + /* packet not fully reassembled yet? */ + if (p == NULL) { + goto ip6_input_cleanup; + } + + /* Returned p point to IPv6 header. + * Update all our variables and pointers and continue. */ + ip6hdr = (struct ip6_hdr *)p->payload; + nexth = &IP6H_NEXTH(ip6hdr); + hlen = hlen_tot = IP6_HLEN; + pbuf_remove_header(p, IP6_HLEN); + +#else /* LWIP_IPV6_REASS */ + /* free (drop) packet pbufs */ + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Fragment header dropped (with LWIP_IPV6_REASS==0)\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.opterr); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; +#endif /* LWIP_IPV6_REASS */ + } + break; + } + default: + goto options_done; + } + + if (*nexth == IP6_NEXTH_HOPBYHOP) { + /* Hop-by-Hop header comes only as a first option */ + icmp6_param_problem(p, ICMP6_PP_HEADER, nexth); + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: packet with Hop-by-Hop options header dropped (only valid as a first option)\n")); + pbuf_free(p); + IP6_STATS_INC(ip6.drop); + goto ip6_input_cleanup; + } + } + +options_done: + + /* send to upper layers */ + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: \n")); + ip6_debug_print(p); + LWIP_DEBUGF(IP6_DEBUG, ("ip6_input: p->len %"U16_F" p->tot_len %"U16_F"\n", p->len, p->tot_len)); + + ip_data.current_ip_header_tot_len = hlen_tot; + +#if LWIP_RAW + /* p points to IPv6 header again for raw_input. */ + pbuf_add_header_force(p, hlen_tot); + /* raw input did not eat the packet? */ + raw_status = raw_input(p, inp); + if (raw_status != RAW_INPUT_EATEN) + { + /* Point to payload. */ + pbuf_remove_header(p, hlen_tot); +#else /* LWIP_RAW */ + { +#endif /* LWIP_RAW */ + switch (*nexth) { + case IP6_NEXTH_NONE: + pbuf_free(p); + break; +#if LWIP_UDP + case IP6_NEXTH_UDP: +#if LWIP_UDPLITE + case IP6_NEXTH_UDPLITE: +#endif /* LWIP_UDPLITE */ + udp_input(p, inp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case IP6_NEXTH_TCP: + tcp_input(p, inp); + break; +#endif /* LWIP_TCP */ +#if LWIP_ICMP6 + case IP6_NEXTH_ICMP6: + icmp6_input(p, inp); + break; +#endif /* LWIP_ICMP */ + default: +#if LWIP_RAW + if (raw_status == RAW_INPUT_DELIVERED) { + /* @todo: ipv6 mib in-delivers? */ + } else +#endif /* LWIP_RAW */ + { +#if LWIP_ICMP6 + /* p points to IPv6 header again for raw_input. */ + pbuf_add_header_force(p, hlen_tot); + /* send ICMP parameter problem unless it was a multicast or ICMPv6 */ + if ((!ip6_addr_ismulticast(ip6_current_dest_addr())) && + (IP6H_NEXTH(ip6hdr) != IP6_NEXTH_ICMP6)) { + icmp6_param_problem(p, ICMP6_PP_HEADER, nexth); + } +#endif /* LWIP_ICMP */ + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_input: Unsupported transport protocol %"U16_F"\n", (u16_t)IP6H_NEXTH(ip6hdr))); + IP6_STATS_INC(ip6.proterr); + IP6_STATS_INC(ip6.drop); + } + pbuf_free(p); + break; + } + } + +ip6_input_cleanup: + ip_data.current_netif = NULL; + ip_data.current_input_netif = NULL; + ip_data.current_ip6_header = NULL; + ip_data.current_ip_header_tot_len = 0; + ip6_addr_set_zero(ip6_current_src_addr()); + ip6_addr_set_zero(ip6_current_dest_addr()); + + return ERR_OK; +} + + +/** + * Sends an IPv6 packet on a network interface. This function constructs + * the IPv6 header. If the source IPv6 address is NULL, the IPv6 "ANY" address is + * used as source (usually during network startup). If the source IPv6 address it + * IP6_ADDR_ANY, the most appropriate IPv6 address of the outgoing network + * interface is filled in as source address. If the destination IPv6 address is + * LWIP_IP_HDRINCL, p is assumed to already include an IPv6 header and + * p->payload points to it instead of the data. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == LWIP_IP_HDRINCL, p already includes an + IPv6 header and p->payload points to that IPv6 header) + * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an + * IP address of the netif is selected and used as source address. + * if src == NULL, IP6_ADDR_ANY is used as source) (src is possibly not + * properly zoned) + * @param dest the destination IPv6 address to send the packet to (possibly not + * properly zoned) + * @param hl the Hop Limit value to be set in the IPv6 header + * @param tc the Traffic Class value to be set in the IPv6 header + * @param nexth the Next Header to be set in the IPv6 header + * @param netif the netif on which to send this packet + * @return ERR_OK if the packet was sent OK + * ERR_BUF if p doesn't have enough space for IPv6/LINK headers + * returns errors returned by netif->output_ip6 + */ +err_t +ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, + u8_t nexth, struct netif *netif) +{ + const ip6_addr_t *src_used = src; + if (dest != LWIP_IP_HDRINCL) { + if (src != NULL && ip6_addr_isany(src)) { + src_used = ip_2_ip6(ip6_select_source_address(netif, dest)); + if ((src_used == NULL) || ip6_addr_isany(src_used)) { + /* No appropriate source address was found for this packet. */ + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_output: No suitable source address for packet.\n")); + IP6_STATS_INC(ip6.rterr); + return ERR_RTE; + } + } + } + return ip6_output_if_src(p, src_used, dest, hl, tc, nexth, netif); +} + +/** + * Same as ip6_output_if() but 'src' address is not replaced by netif address + * when it is 'any'. + */ +err_t +ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, + u8_t nexth, struct netif *netif) +{ + struct ip6_hdr *ip6hdr; + ip6_addr_t dest_addr; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + + /* Should the IPv6 header be generated or is it already included in p? */ + if (dest != LWIP_IP_HDRINCL) { +#if LWIP_IPV6_SCOPES + /* If the destination address is scoped but lacks a zone, add a zone now, + * based on the outgoing interface. The lower layers (e.g., nd6) absolutely + * require addresses to be properly zoned for correctness. In some cases, + * earlier attempts will have been made to add a zone to the destination, + * but this function is the only one that is called in all (other) cases, + * so we must do this here. */ + if (ip6_addr_lacks_zone(dest, IP6_UNKNOWN)) { + ip6_addr_copy(dest_addr, *dest); + ip6_addr_assign_zone(&dest_addr, IP6_UNKNOWN, netif); + dest = &dest_addr; + } +#endif /* LWIP_IPV6_SCOPES */ + + /* generate IPv6 header */ + if (pbuf_add_header(p, IP6_HLEN)) { + LWIP_DEBUGF(IP6_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("ip6_output: not enough room for IPv6 header in pbuf\n")); + IP6_STATS_INC(ip6.err); + return ERR_BUF; + } + + ip6hdr = (struct ip6_hdr *)p->payload; + LWIP_ASSERT("check that first pbuf can hold struct ip6_hdr", + (p->len >= sizeof(struct ip6_hdr))); + + IP6H_HOPLIM_SET(ip6hdr, hl); + IP6H_NEXTH_SET(ip6hdr, nexth); + + /* dest cannot be NULL here */ + ip6_addr_copy_to_packed(ip6hdr->dest, *dest); + + IP6H_VTCFL_SET(ip6hdr, 6, tc, 0); + IP6H_PLEN_SET(ip6hdr, (u16_t)(p->tot_len - IP6_HLEN)); + + if (src == NULL) { + src = IP6_ADDR_ANY6; + } + /* src cannot be NULL here */ + ip6_addr_copy_to_packed(ip6hdr->src, *src); + + } else { + /* IP header already included in p */ + ip6hdr = (struct ip6_hdr *)p->payload; + ip6_addr_copy_from_packed(dest_addr, ip6hdr->dest); + ip6_addr_assign_zone(&dest_addr, IP6_UNKNOWN, netif); + dest = &dest_addr; + } + + IP6_STATS_INC(ip6.xmit); + + LWIP_DEBUGF(IP6_DEBUG, ("ip6_output_if: %c%c%"U16_F"\n", netif->name[0], netif->name[1], (u16_t)netif->num)); + ip6_debug_print(p); + +#if ENABLE_LOOPBACK + { + int i; +#if !LWIP_HAVE_LOOPIF + if (ip6_addr_isloopback(dest)) { + return netif_loop_output(netif, p); + } +#endif /* !LWIP_HAVE_LOOPIF */ + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && + ip6_addr_cmp(dest, netif_ip6_addr(netif, i))) { + /* Packet to self, enqueue it for loopback */ + LWIP_DEBUGF(IP6_DEBUG, ("netif_loop_output()\n")); + return netif_loop_output(netif, p); + } + } + } +#if LWIP_MULTICAST_TX_OPTIONS + if ((p->flags & PBUF_FLAG_MCASTLOOP) != 0) { + netif_loop_output(netif, p); + } +#endif /* LWIP_MULTICAST_TX_OPTIONS */ +#endif /* ENABLE_LOOPBACK */ +#if LWIP_IPV6_FRAG + /* don't fragment if interface has mtu set to 0 [loopif] */ + if (netif_mtu6(netif) && (p->tot_len > nd6_get_destination_mtu(dest, netif))) { + return ip6_frag(p, netif, dest); + } +#endif /* LWIP_IPV6_FRAG */ + + LWIP_DEBUGF(IP6_DEBUG, ("netif->output_ip6()\n")); + return netif->output_ip6(netif, p, dest); +} + +/** + * Simple interface to ip6_output_if. It finds the outgoing network + * interface and calls upon ip6_output_if to do the actual work. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == LWIP_IP_HDRINCL, p already includes an + IPv6 header and p->payload points to that IPv6 header) + * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an + * IP address of the netif is selected and used as source address. + * if src == NULL, IP6_ADDR_ANY is used as source) + * @param dest the destination IPv6 address to send the packet to + * @param hl the Hop Limit value to be set in the IPv6 header + * @param tc the Traffic Class value to be set in the IPv6 header + * @param nexth the Next Header to be set in the IPv6 header + * + * @return ERR_RTE if no route is found + * see ip_output_if() for more return values + */ +err_t +ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, u8_t nexth) +{ + struct netif *netif; + struct ip6_hdr *ip6hdr; + ip6_addr_t src_addr, dest_addr; + + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + + if (dest != LWIP_IP_HDRINCL) { + netif = ip6_route(src, dest); + } else { + /* IP header included in p, read addresses. */ + ip6hdr = (struct ip6_hdr *)p->payload; + ip6_addr_copy_from_packed(src_addr, ip6hdr->src); + ip6_addr_copy_from_packed(dest_addr, ip6hdr->dest); + netif = ip6_route(&src_addr, &dest_addr); + } + + if (netif == NULL) { + LWIP_DEBUGF(IP6_DEBUG, ("ip6_output: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", + IP6_ADDR_BLOCK1(dest), + IP6_ADDR_BLOCK2(dest), + IP6_ADDR_BLOCK3(dest), + IP6_ADDR_BLOCK4(dest), + IP6_ADDR_BLOCK5(dest), + IP6_ADDR_BLOCK6(dest), + IP6_ADDR_BLOCK7(dest), + IP6_ADDR_BLOCK8(dest))); + IP6_STATS_INC(ip6.rterr); + return ERR_RTE; + } + + return ip6_output_if(p, src, dest, hl, tc, nexth, netif); +} + + +#if LWIP_NETIF_USE_HINTS +/** Like ip6_output, but takes and addr_hint pointer that is passed on to netif->addr_hint + * before calling ip6_output_if. + * + * @param p the packet to send (p->payload points to the data, e.g. next + protocol header; if dest == LWIP_IP_HDRINCL, p already includes an + IPv6 header and p->payload points to that IPv6 header) + * @param src the source IPv6 address to send from (if src == IP6_ADDR_ANY, an + * IP address of the netif is selected and used as source address. + * if src == NULL, IP6_ADDR_ANY is used as source) + * @param dest the destination IPv6 address to send the packet to + * @param hl the Hop Limit value to be set in the IPv6 header + * @param tc the Traffic Class value to be set in the IPv6 header + * @param nexth the Next Header to be set in the IPv6 header + * @param netif_hint netif output hint pointer set to netif->hint before + * calling ip_output_if() + * + * @return ERR_RTE if no route is found + * see ip_output_if() for more return values + */ +err_t +ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, u8_t nexth, struct netif_hint *netif_hint) +{ + struct netif *netif; + struct ip6_hdr *ip6hdr; + ip6_addr_t src_addr, dest_addr; + err_t err; + + LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p); + + if (dest != LWIP_IP_HDRINCL) { + netif = ip6_route(src, dest); + } else { + /* IP header included in p, read addresses. */ + ip6hdr = (struct ip6_hdr *)p->payload; + ip6_addr_copy_from_packed(src_addr, ip6hdr->src); + ip6_addr_copy_from_packed(dest_addr, ip6hdr->dest); + netif = ip6_route(&src_addr, &dest_addr); + } + + if (netif == NULL) { + LWIP_DEBUGF(IP6_DEBUG, ("ip6_output: no route for %"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F":%"X16_F"\n", + IP6_ADDR_BLOCK1(dest), + IP6_ADDR_BLOCK2(dest), + IP6_ADDR_BLOCK3(dest), + IP6_ADDR_BLOCK4(dest), + IP6_ADDR_BLOCK5(dest), + IP6_ADDR_BLOCK6(dest), + IP6_ADDR_BLOCK7(dest), + IP6_ADDR_BLOCK8(dest))); + IP6_STATS_INC(ip6.rterr); + return ERR_RTE; + } + + NETIF_SET_HINTS(netif, netif_hint); + err = ip6_output_if(p, src, dest, hl, tc, nexth, netif); + NETIF_RESET_HINTS(netif); + + return err; +} +#endif /* LWIP_NETIF_USE_HINTS*/ + +#if LWIP_IPV6_MLD +/** + * Add a hop-by-hop options header with a router alert option and padding. + * + * Used by MLD when sending a Multicast listener report/done message. + * + * @param p the packet to which we will prepend the options header + * @param nexth the next header protocol number (e.g. IP6_NEXTH_ICMP6) + * @param value the value of the router alert option data (e.g. IP6_ROUTER_ALERT_VALUE_MLD) + * @return ERR_OK if hop-by-hop header was added, ERR_* otherwise + */ +err_t +ip6_options_add_hbh_ra(struct pbuf *p, u8_t nexth, u8_t value) +{ + u8_t *opt_data; + u32_t offset = 0; + struct ip6_hbh_hdr *hbh_hdr; + struct ip6_opt_hdr *opt_hdr; + + /* fixed 4 bytes for router alert option and 2 bytes padding */ + const u8_t hlen = (sizeof(struct ip6_opt_hdr) * 2) + IP6_ROUTER_ALERT_DLEN; + /* Move pointer to make room for hop-by-hop options header. */ + if (pbuf_add_header(p, sizeof(struct ip6_hbh_hdr) + hlen)) { + LWIP_DEBUGF(IP6_DEBUG, ("ip6_options: no space for options header\n")); + IP6_STATS_INC(ip6.err); + return ERR_BUF; + } + + /* Set fields of Hop-by-Hop header */ + hbh_hdr = (struct ip6_hbh_hdr *)p->payload; + IP6_HBH_NEXTH(hbh_hdr) = nexth; + hbh_hdr->_hlen = 0; + offset = IP6_HBH_HLEN; + + /* Set router alert options to Hop-by-Hop extended option header */ + opt_hdr = (struct ip6_opt_hdr *)((u8_t *)hbh_hdr + offset); + IP6_OPT_TYPE(opt_hdr) = IP6_ROUTER_ALERT_OPTION; + IP6_OPT_DLEN(opt_hdr) = IP6_ROUTER_ALERT_DLEN; + offset += IP6_OPT_HLEN; + + /* Set router alert option data */ + opt_data = (u8_t *)hbh_hdr + offset; + opt_data[0] = value; + opt_data[1] = 0; + offset += IP6_OPT_DLEN(opt_hdr); + + /* add 2 bytes padding to make 8 bytes Hop-by-Hop header length */ + opt_hdr = (struct ip6_opt_hdr *)((u8_t *)hbh_hdr + offset); + IP6_OPT_TYPE(opt_hdr) = IP6_PADN_OPTION; + IP6_OPT_DLEN(opt_hdr) = 0; + + return ERR_OK; +} +#endif /* LWIP_IPV6_MLD */ + +#if IP6_DEBUG +/* Print an IPv6 header by using LWIP_DEBUGF + * @param p an IPv6 packet, p->payload pointing to the IPv6 header + */ +void +ip6_debug_print(struct pbuf *p) +{ + struct ip6_hdr *ip6hdr = (struct ip6_hdr *)p->payload; + + LWIP_DEBUGF(IP6_DEBUG, ("IPv6 header:\n")); + LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP6_DEBUG, ("| %2"U16_F" | %3"U16_F" | %7"U32_F" | (ver, class, flow)\n", + IP6H_V(ip6hdr), + IP6H_TC(ip6hdr), + IP6H_FL(ip6hdr))); + LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP6_DEBUG, ("| %5"U16_F" | %3"U16_F" | %3"U16_F" | (plen, nexth, hopl)\n", + IP6H_PLEN(ip6hdr), + IP6H_NEXTH(ip6hdr), + IP6H_HOPLIM(ip6hdr))); + LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" | (src)\n", + IP6_ADDR_BLOCK1(&(ip6hdr->src)), + IP6_ADDR_BLOCK2(&(ip6hdr->src)), + IP6_ADDR_BLOCK3(&(ip6hdr->src)), + IP6_ADDR_BLOCK4(&(ip6hdr->src)))); + LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" |\n", + IP6_ADDR_BLOCK5(&(ip6hdr->src)), + IP6_ADDR_BLOCK6(&(ip6hdr->src)), + IP6_ADDR_BLOCK7(&(ip6hdr->src)), + IP6_ADDR_BLOCK8(&(ip6hdr->src)))); + LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" | (dest)\n", + IP6_ADDR_BLOCK1(&(ip6hdr->dest)), + IP6_ADDR_BLOCK2(&(ip6hdr->dest)), + IP6_ADDR_BLOCK3(&(ip6hdr->dest)), + IP6_ADDR_BLOCK4(&(ip6hdr->dest)))); + LWIP_DEBUGF(IP6_DEBUG, ("| %4"X32_F" | %4"X32_F" | %4"X32_F" | %4"X32_F" |\n", + IP6_ADDR_BLOCK5(&(ip6hdr->dest)), + IP6_ADDR_BLOCK6(&(ip6hdr->dest)), + IP6_ADDR_BLOCK7(&(ip6hdr->dest)), + IP6_ADDR_BLOCK8(&(ip6hdr->dest)))); + LWIP_DEBUGF(IP6_DEBUG, ("+-------------------------------+\n")); +} +#endif /* IP6_DEBUG */ + +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c new file mode 100644 index 0000000..687c02f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_addr.c @@ -0,0 +1,343 @@ +/** + * @file + * + * IPv6 addresses. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * Functions for handling IPv6 addresses. + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip_addr.h" +#include "lwip/def.h" + +#include + +#if LWIP_IPV4 +#include "lwip/ip4_addr.h" /* for ip6addr_aton to handle IPv4-mapped addresses */ +#endif /* LWIP_IPV4 */ + +/* used by IP6_ADDR_ANY(6) in ip6_addr.h */ +const ip_addr_t ip6_addr_any = IPADDR6_INIT(0ul, 0ul, 0ul, 0ul); + +#define lwip_xchar(i) ((char)((i) < 10 ? '0' + (i) : 'A' + (i) - 10)) + +/** + * Check whether "cp" is a valid ascii representation + * of an IPv6 address and convert to a binary address. + * Returns 1 if the address is valid, 0 if not. + * + * @param cp IPv6 address in ascii representation (e.g. "FF01::1") + * @param addr pointer to which to save the ip address in network order + * @return 1 if cp could be converted to addr, 0 on failure + */ +int +ip6addr_aton(const char *cp, ip6_addr_t *addr) +{ + u32_t addr_index, zero_blocks, current_block_index, current_block_value; + const char *s; +#if LWIP_IPV4 + int check_ipv4_mapped = 0; +#endif /* LWIP_IPV4 */ + + /* Count the number of colons, to count the number of blocks in a "::" sequence + zero_blocks may be 1 even if there are no :: sequences */ + zero_blocks = 8; + for (s = cp; *s != 0; s++) { + if (*s == ':') { + zero_blocks--; +#if LWIP_IPV4 + } else if (*s == '.') { + if ((zero_blocks == 5) ||(zero_blocks == 2)) { + check_ipv4_mapped = 1; + /* last block could be the start of an IPv4 address */ + zero_blocks--; + } else { + /* invalid format */ + return 0; + } + break; +#endif /* LWIP_IPV4 */ + } else if (!lwip_isxdigit(*s)) { + break; + } + } + + /* parse each block */ + addr_index = 0; + current_block_index = 0; + current_block_value = 0; + for (s = cp; *s != 0; s++) { + if (*s == ':') { + if (addr) { + if (current_block_index & 0x1) { + addr->addr[addr_index++] |= current_block_value; + } + else { + addr->addr[addr_index] = current_block_value << 16; + } + } + current_block_index++; +#if LWIP_IPV4 + if (check_ipv4_mapped) { + if (current_block_index == 6) { + ip4_addr_t ip4; + int ret = ip4addr_aton(s + 1, &ip4); + if (ret) { + if (addr) { + addr->addr[3] = lwip_htonl(ip4.addr); + current_block_index++; + goto fix_byte_order_and_return; + } + return 1; + } + } + } +#endif /* LWIP_IPV4 */ + current_block_value = 0; + if (current_block_index > 7) { + /* address too long! */ + return 0; + } + if (s[1] == ':') { + if (s[2] == ':') { + /* invalid format: three successive colons */ + return 0; + } + s++; + /* "::" found, set zeros */ + while (zero_blocks > 0) { + zero_blocks--; + if (current_block_index & 0x1) { + addr_index++; + } else { + if (addr) { + addr->addr[addr_index] = 0; + } + } + current_block_index++; + if (current_block_index > 7) { + /* address too long! */ + return 0; + } + } + } + } else if (lwip_isxdigit(*s)) { + /* add current digit */ + current_block_value = (current_block_value << 4) + + (lwip_isdigit(*s) ? (u32_t)(*s - '0') : + (u32_t)(10 + (lwip_islower(*s) ? *s - 'a' : *s - 'A'))); + } else { + /* unexpected digit, space? CRLF? */ + break; + } + } + + if (addr) { + if (current_block_index & 0x1) { + addr->addr[addr_index++] |= current_block_value; + } + else { + addr->addr[addr_index] = current_block_value << 16; + } +#if LWIP_IPV4 +fix_byte_order_and_return: +#endif + /* convert to network byte order. */ + for (addr_index = 0; addr_index < 4; addr_index++) { + addr->addr[addr_index] = lwip_htonl(addr->addr[addr_index]); + } + + ip6_addr_clear_zone(addr); + } + + if (current_block_index != 7) { + return 0; + } + + return 1; +} + +/** + * Convert numeric IPv6 address into ASCII representation. + * returns ptr to static buffer; not reentrant! + * + * @param addr ip6 address in network order to convert + * @return pointer to a global static (!) buffer that holds the ASCII + * representation of addr + */ +char * +ip6addr_ntoa(const ip6_addr_t *addr) +{ + static char str[40]; + return ip6addr_ntoa_r(addr, str, 40); +} + +/** + * Same as ipaddr_ntoa, but reentrant since a user-supplied buffer is used. + * + * @param addr ip6 address in network order to convert + * @param buf target buffer where the string is stored + * @param buflen length of buf + * @return either pointer to buf which now holds the ASCII + * representation of addr or NULL if buf was too small + */ +char * +ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen) +{ + u32_t current_block_index, current_block_value, next_block_value; + s32_t i; + u8_t zero_flag, empty_block_flag; + +#if LWIP_IPV4 + if (ip6_addr_isipv4mappedipv6(addr)) { + /* This is an IPv4 mapped address */ + ip4_addr_t addr4; + char *ret; +#define IP4MAPPED_HEADER "::FFFF:" + char *buf_ip4 = buf + sizeof(IP4MAPPED_HEADER) - 1; + int buflen_ip4 = buflen - sizeof(IP4MAPPED_HEADER) + 1; + if (buflen < (int)sizeof(IP4MAPPED_HEADER)) { + return NULL; + } + memcpy(buf, IP4MAPPED_HEADER, sizeof(IP4MAPPED_HEADER)); + addr4.addr = addr->addr[3]; + ret = ip4addr_ntoa_r(&addr4, buf_ip4, buflen_ip4); + if (ret != buf_ip4) { + return NULL; + } + return buf; + } +#endif /* LWIP_IPV4 */ + i = 0; + empty_block_flag = 0; /* used to indicate a zero chain for "::' */ + + for (current_block_index = 0; current_block_index < 8; current_block_index++) { + /* get the current 16-bit block */ + current_block_value = lwip_htonl(addr->addr[current_block_index >> 1]); + if ((current_block_index & 0x1) == 0) { + current_block_value = current_block_value >> 16; + } + current_block_value &= 0xffff; + + /* Check for empty block. */ + if (current_block_value == 0) { + if (current_block_index == 7 && empty_block_flag == 1) { + /* special case, we must render a ':' for the last block. */ + buf[i++] = ':'; + if (i >= buflen) { + return NULL; + } + break; + } + if (empty_block_flag == 0) { + /* generate empty block "::", but only if more than one contiguous zero block, + * according to current formatting suggestions RFC 5952. */ + next_block_value = lwip_htonl(addr->addr[(current_block_index + 1) >> 1]); + if ((current_block_index & 0x1) == 0x01) { + next_block_value = next_block_value >> 16; + } + next_block_value &= 0xffff; + if (next_block_value == 0) { + empty_block_flag = 1; + buf[i++] = ':'; + if (i >= buflen) { + return NULL; + } + continue; /* move on to next block. */ + } + } else if (empty_block_flag == 1) { + /* move on to next block. */ + continue; + } + } else if (empty_block_flag == 1) { + /* Set this flag value so we don't produce multiple empty blocks. */ + empty_block_flag = 2; + } + + if (current_block_index > 0) { + buf[i++] = ':'; + if (i >= buflen) { + return NULL; + } + } + + if ((current_block_value & 0xf000) == 0) { + zero_flag = 1; + } else { + buf[i++] = lwip_xchar(((current_block_value & 0xf000) >> 12)); + zero_flag = 0; + if (i >= buflen) { + return NULL; + } + } + + if (((current_block_value & 0xf00) == 0) && (zero_flag)) { + /* do nothing */ + } else { + buf[i++] = lwip_xchar(((current_block_value & 0xf00) >> 8)); + zero_flag = 0; + if (i >= buflen) { + return NULL; + } + } + + if (((current_block_value & 0xf0) == 0) && (zero_flag)) { + /* do nothing */ + } + else { + buf[i++] = lwip_xchar(((current_block_value & 0xf0) >> 4)); + zero_flag = 0; + if (i >= buflen) { + return NULL; + } + } + + buf[i++] = lwip_xchar((current_block_value & 0xf)); + if (i >= buflen) { + return NULL; + } + } + + buf[i] = 0; + + return buf; +} + +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c new file mode 100644 index 0000000..d6c5d22 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/ip6_frag.c @@ -0,0 +1,862 @@ +/** + * @file + * + * IPv6 fragmentation and reassembly. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#include "lwip/opt.h" +#include "lwip/ip6_frag.h" +#include "lwip/ip6.h" +#include "lwip/icmp6.h" +#include "lwip/nd6.h" +#include "lwip/ip.h" + +#include "lwip/pbuf.h" +#include "lwip/memp.h" +#include "lwip/stats.h" + +#include + +#if LWIP_IPV6 && LWIP_IPV6_REASS /* don't build if not configured for use in lwipopts.h */ + + +/** Setting this to 0, you can turn off checking the fragments for overlapping + * regions. The code gets a little smaller. Only use this if you know that + * overlapping won't occur on your network! */ +#ifndef IP_REASS_CHECK_OVERLAP +#define IP_REASS_CHECK_OVERLAP 1 +#endif /* IP_REASS_CHECK_OVERLAP */ + +/** Set to 0 to prevent freeing the oldest datagram when the reassembly buffer is + * full (IP_REASS_MAX_PBUFS pbufs are enqueued). The code gets a little smaller. + * Datagrams will be freed by timeout only. Especially useful when MEMP_NUM_REASSDATA + * is set to 1, so one datagram can be reassembled at a time, only. */ +#ifndef IP_REASS_FREE_OLDEST +#define IP_REASS_FREE_OLDEST 1 +#endif /* IP_REASS_FREE_OLDEST */ + +#if IPV6_FRAG_COPYHEADER +/* The number of bytes we need to "borrow" from (i.e., overwrite in) the header + * that precedes the fragment header for reassembly pruposes. */ +#define IPV6_FRAG_REQROOM ((s16_t)(sizeof(struct ip6_reass_helper) - IP6_FRAG_HLEN)) +#endif + +#define IP_REASS_FLAG_LASTFRAG 0x01 + +/** This is a helper struct which holds the starting + * offset and the ending offset of this fragment to + * easily chain the fragments. + * It has the same packing requirements as the IPv6 header, since it replaces + * the Fragment Header in memory in incoming fragments to keep + * track of the various fragments. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_reass_helper { + PACK_STRUCT_FIELD(struct pbuf *next_pbuf); + PACK_STRUCT_FIELD(u16_t start); + PACK_STRUCT_FIELD(u16_t end); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* static variables */ +static struct ip6_reassdata *reassdatagrams; +static u16_t ip6_reass_pbufcount; + +/* Forward declarations. */ +static void ip6_reass_free_complete_datagram(struct ip6_reassdata *ipr); +#if IP_REASS_FREE_OLDEST +static void ip6_reass_remove_oldest_datagram(struct ip6_reassdata *ipr, int pbufs_needed); +#endif /* IP_REASS_FREE_OLDEST */ + +void +ip6_reass_tmr(void) +{ + struct ip6_reassdata *r, *tmp; + +#if !IPV6_FRAG_COPYHEADER + LWIP_ASSERT("sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN, set IPV6_FRAG_COPYHEADER to 1", + sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN); +#endif /* !IPV6_FRAG_COPYHEADER */ + + r = reassdatagrams; + while (r != NULL) { + /* Decrement the timer. Once it reaches 0, + * clean up the incomplete fragment assembly */ + if (r->timer > 0) { + r->timer--; + r = r->next; + } else { + /* reassembly timed out */ + tmp = r; + /* get the next pointer before freeing */ + r = r->next; + /* free the helper struct and all enqueued pbufs */ + ip6_reass_free_complete_datagram(tmp); + } + } +} + +/** + * Free a datagram (struct ip6_reassdata) and all its pbufs. + * Updates the total count of enqueued pbufs (ip6_reass_pbufcount), + * sends an ICMP time exceeded packet. + * + * @param ipr datagram to free + */ +static void +ip6_reass_free_complete_datagram(struct ip6_reassdata *ipr) +{ + struct ip6_reassdata *prev; + u16_t pbufs_freed = 0; + u16_t clen; + struct pbuf *p; + struct ip6_reass_helper *iprh; + +#if LWIP_ICMP6 + iprh = (struct ip6_reass_helper *)ipr->p->payload; + if (iprh->start == 0) { + /* The first fragment was received, send ICMP time exceeded. */ + /* First, de-queue the first pbuf from r->p. */ + p = ipr->p; + ipr->p = iprh->next_pbuf; + /* Restore the part that we've overwritten with our helper structure, or we + * might send garbage (and disclose a pointer) in the ICMPv6 reply. */ + MEMCPY(p->payload, ipr->orig_hdr, sizeof(iprh)); + /* Then, move back to the original ipv6 header (we are now pointing to Fragment header). + This cannot fail since we already checked when receiving this fragment. */ + if (pbuf_header_force(p, (s16_t)((u8_t*)p->payload - (u8_t*)ipr->iphdr))) { + LWIP_ASSERT("ip6_reass_free: moving p->payload to ip6 header failed\n", 0); + } + else { + /* Reconstruct the zoned source and destination addresses, so that we do + * not end up sending the ICMP response over the wrong link. */ + ip6_addr_t src_addr, dest_addr; + ip6_addr_copy_from_packed(src_addr, IPV6_FRAG_SRC(ipr)); + ip6_addr_set_zone(&src_addr, ipr->src_zone); + ip6_addr_copy_from_packed(dest_addr, IPV6_FRAG_DEST(ipr)); + ip6_addr_set_zone(&dest_addr, ipr->dest_zone); + /* Send the actual ICMP response. */ + icmp6_time_exceeded_with_addrs(p, ICMP6_TE_FRAG, &src_addr, &dest_addr); + } + clen = pbuf_clen(p); + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + pbufs_freed = (u16_t)(pbufs_freed + clen); + pbuf_free(p); + } +#endif /* LWIP_ICMP6 */ + + /* First, free all received pbufs. The individual pbufs need to be released + separately as they have not yet been chained */ + p = ipr->p; + while (p != NULL) { + struct pbuf *pcur; + iprh = (struct ip6_reass_helper *)p->payload; + pcur = p; + /* get the next pointer before freeing */ + p = iprh->next_pbuf; + clen = pbuf_clen(pcur); + LWIP_ASSERT("pbufs_freed + clen <= 0xffff", pbufs_freed + clen <= 0xffff); + pbufs_freed = (u16_t)(pbufs_freed + clen); + pbuf_free(pcur); + } + + /* Then, unchain the struct ip6_reassdata from the list and free it. */ + if (ipr == reassdatagrams) { + reassdatagrams = ipr->next; + } else { + prev = reassdatagrams; + while (prev != NULL) { + if (prev->next == ipr) { + break; + } + prev = prev->next; + } + if (prev != NULL) { + prev->next = ipr->next; + } + } + memp_free(MEMP_IP6_REASSDATA, ipr); + + /* Finally, update number of pbufs in reassembly queue */ + LWIP_ASSERT("ip_reass_pbufcount >= clen", ip6_reass_pbufcount >= pbufs_freed); + ip6_reass_pbufcount = (u16_t)(ip6_reass_pbufcount - pbufs_freed); +} + +#if IP_REASS_FREE_OLDEST +/** + * Free the oldest datagram to make room for enqueueing new fragments. + * The datagram ipr is not freed! + * + * @param ipr ip6_reassdata for the current fragment + * @param pbufs_needed number of pbufs needed to enqueue + * (used for freeing other datagrams if not enough space) + */ +static void +ip6_reass_remove_oldest_datagram(struct ip6_reassdata *ipr, int pbufs_needed) +{ + struct ip6_reassdata *r, *oldest; + + /* Free datagrams until being allowed to enqueue 'pbufs_needed' pbufs, + * but don't free the current datagram! */ + do { + r = oldest = reassdatagrams; + while (r != NULL) { + if (r != ipr) { + if (r->timer <= oldest->timer) { + /* older than the previous oldest */ + oldest = r; + } + } + r = r->next; + } + if (oldest == ipr) { + /* nothing to free, ipr is the only element on the list */ + return; + } + if (oldest != NULL) { + ip6_reass_free_complete_datagram(oldest); + } + } while (((ip6_reass_pbufcount + pbufs_needed) > IP_REASS_MAX_PBUFS) && (reassdatagrams != NULL)); +} +#endif /* IP_REASS_FREE_OLDEST */ + +/** + * Reassembles incoming IPv6 fragments into an IPv6 datagram. + * + * @param p points to the IPv6 Fragment Header + * @return NULL if reassembly is incomplete, pbuf pointing to + * IPv6 Header if reassembly is complete + */ +struct pbuf * +ip6_reass(struct pbuf *p) +{ + struct ip6_reassdata *ipr, *ipr_prev; + struct ip6_reass_helper *iprh, *iprh_tmp, *iprh_prev=NULL; + struct ip6_frag_hdr *frag_hdr; + u16_t offset, len, start, end; + ptrdiff_t hdrdiff; + u16_t clen; + u8_t valid = 1; + struct pbuf *q, *next_pbuf; + + IP6_FRAG_STATS_INC(ip6_frag.recv); + + /* ip6_frag_hdr must be in the first pbuf, not chained. Checked by caller. */ + LWIP_ASSERT("IPv6 fragment header does not fit in first pbuf", + p->len >= sizeof(struct ip6_frag_hdr)); + + frag_hdr = (struct ip6_frag_hdr *) p->payload; + + clen = pbuf_clen(p); + + offset = lwip_ntohs(frag_hdr->_fragment_offset); + + /* Calculate fragment length from IPv6 payload length. + * Adjust for headers before Fragment Header. + * And finally adjust by Fragment Header length. */ + len = lwip_ntohs(ip6_current_header()->_plen); + hdrdiff = (u8_t*)p->payload - (const u8_t*)ip6_current_header(); + LWIP_ASSERT("not a valid pbuf (ip6_input check missing?)", hdrdiff <= 0xFFFF); + LWIP_ASSERT("not a valid pbuf (ip6_input check missing?)", hdrdiff >= IP6_HLEN); + hdrdiff -= IP6_HLEN; + hdrdiff += IP6_FRAG_HLEN; + if (hdrdiff > len) { + IP6_FRAG_STATS_INC(ip6_frag.proterr); + goto nullreturn; + } + len = (u16_t)(len - hdrdiff); + start = (offset & IP6_FRAG_OFFSET_MASK); + if (start > (0xFFFF - len)) { + /* u16_t overflow, cannot handle this */ + IP6_FRAG_STATS_INC(ip6_frag.proterr); + goto nullreturn; + } + + /* Look for the datagram the fragment belongs to in the current datagram queue, + * remembering the previous in the queue for later dequeueing. */ + for (ipr = reassdatagrams, ipr_prev = NULL; ipr != NULL; ipr = ipr->next) { + /* Check if the incoming fragment matches the one currently present + in the reassembly buffer. If so, we proceed with copying the + fragment into the buffer. */ + if ((frag_hdr->_identification == ipr->identification) && + ip6_addr_cmp_packed(ip6_current_src_addr(), &(IPV6_FRAG_SRC(ipr)), ipr->src_zone) && + ip6_addr_cmp_packed(ip6_current_dest_addr(), &(IPV6_FRAG_DEST(ipr)), ipr->dest_zone)) { + IP6_FRAG_STATS_INC(ip6_frag.cachehit); + break; + } + ipr_prev = ipr; + } + + if (ipr == NULL) { + /* Enqueue a new datagram into the datagram queue */ + ipr = (struct ip6_reassdata *)memp_malloc(MEMP_IP6_REASSDATA); + if (ipr == NULL) { +#if IP_REASS_FREE_OLDEST + /* Make room and try again. */ + ip6_reass_remove_oldest_datagram(ipr, clen); + ipr = (struct ip6_reassdata *)memp_malloc(MEMP_IP6_REASSDATA); + if (ipr != NULL) { + /* re-search ipr_prev since it might have been removed */ + for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { + if (ipr_prev->next == ipr) { + break; + } + } + } else +#endif /* IP_REASS_FREE_OLDEST */ + { + IP6_FRAG_STATS_INC(ip6_frag.memerr); + goto nullreturn; + } + } + + memset(ipr, 0, sizeof(struct ip6_reassdata)); + ipr->timer = IPV6_REASS_MAXAGE; + + /* enqueue the new structure to the front of the list */ + ipr->next = reassdatagrams; + reassdatagrams = ipr; + + /* Use the current IPv6 header for src/dest address reference. + * Eventually, we will replace it when we get the first fragment + * (it might be this one, in any case, it is done later). */ + /* need to use the none-const pointer here: */ + ipr->iphdr = ip_data.current_ip6_header; +#if IPV6_FRAG_COPYHEADER + MEMCPY(&ipr->src, &ip6_current_header()->src, sizeof(ipr->src)); + MEMCPY(&ipr->dest, &ip6_current_header()->dest, sizeof(ipr->dest)); +#endif /* IPV6_FRAG_COPYHEADER */ +#if LWIP_IPV6_SCOPES + /* Also store the address zone information. + * @todo It is possible that due to netif destruction and recreation, the + * stored zones end up resolving to a different interface. In that case, we + * risk sending a "time exceeded" ICMP response over the wrong link. + * Ideally, netif destruction would clean up matching pending reassembly + * structures, but custom zone mappings would make that non-trivial. */ + ipr->src_zone = ip6_addr_zone(ip6_current_src_addr()); + ipr->dest_zone = ip6_addr_zone(ip6_current_dest_addr()); +#endif /* LWIP_IPV6_SCOPES */ + /* copy the fragmented packet id. */ + ipr->identification = frag_hdr->_identification; + + /* copy the nexth field */ + ipr->nexth = frag_hdr->_nexth; + } + + /* Check if we are allowed to enqueue more datagrams. */ + if ((ip6_reass_pbufcount + clen) > IP_REASS_MAX_PBUFS) { +#if IP_REASS_FREE_OLDEST + ip6_reass_remove_oldest_datagram(ipr, clen); + if ((ip6_reass_pbufcount + clen) <= IP_REASS_MAX_PBUFS) { + /* re-search ipr_prev since it might have been removed */ + for (ipr_prev = reassdatagrams; ipr_prev != NULL; ipr_prev = ipr_prev->next) { + if (ipr_prev->next == ipr) { + break; + } + } + } else +#endif /* IP_REASS_FREE_OLDEST */ + { + /* @todo: send ICMPv6 time exceeded here? */ + /* drop this pbuf */ + IP6_FRAG_STATS_INC(ip6_frag.memerr); + goto nullreturn; + } + } + + /* Overwrite Fragment Header with our own helper struct. */ +#if IPV6_FRAG_COPYHEADER + if (IPV6_FRAG_REQROOM > 0) { + /* Make room for struct ip6_reass_helper (only required if sizeof(void*) > 4). + This cannot fail since we already checked when receiving this fragment. */ + u8_t hdrerr = pbuf_header_force(p, IPV6_FRAG_REQROOM); + LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */ + LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0); + } +#else /* IPV6_FRAG_COPYHEADER */ + LWIP_ASSERT("sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN, set IPV6_FRAG_COPYHEADER to 1", + sizeof(struct ip6_reass_helper) <= IP6_FRAG_HLEN); +#endif /* IPV6_FRAG_COPYHEADER */ + + /* Prepare the pointer to the helper structure, and its initial values. + * Do not yet write to the structure itself, as we still have to make a + * backup of the original data, and we should not do that until we know for + * sure that we are going to add this packet to the list. */ + iprh = (struct ip6_reass_helper *)p->payload; + next_pbuf = NULL; + end = (u16_t)(start + len); + + /* find the right place to insert this pbuf */ + /* Iterate through until we either get to the end of the list (append), + * or we find on with a larger offset (insert). */ + for (q = ipr->p; q != NULL;) { + iprh_tmp = (struct ip6_reass_helper*)q->payload; + if (start < iprh_tmp->start) { +#if IP_REASS_CHECK_OVERLAP + if (end > iprh_tmp->start) { + /* fragment overlaps with following, throw away */ + IP6_FRAG_STATS_INC(ip6_frag.proterr); + goto nullreturn; + } + if (iprh_prev != NULL) { + if (start < iprh_prev->end) { + /* fragment overlaps with previous, throw away */ + IP6_FRAG_STATS_INC(ip6_frag.proterr); + goto nullreturn; + } + } +#endif /* IP_REASS_CHECK_OVERLAP */ + /* the new pbuf should be inserted before this */ + next_pbuf = q; + if (iprh_prev != NULL) { + /* not the fragment with the lowest offset */ + iprh_prev->next_pbuf = p; + } else { + /* fragment with the lowest offset */ + ipr->p = p; + } + break; + } else if (start == iprh_tmp->start) { + /* received the same datagram twice: no need to keep the datagram */ + goto nullreturn; +#if IP_REASS_CHECK_OVERLAP + } else if (start < iprh_tmp->end) { + /* overlap: no need to keep the new datagram */ + IP6_FRAG_STATS_INC(ip6_frag.proterr); + goto nullreturn; +#endif /* IP_REASS_CHECK_OVERLAP */ + } else { + /* Check if the fragments received so far have no gaps. */ + if (iprh_prev != NULL) { + if (iprh_prev->end != iprh_tmp->start) { + /* There is a fragment missing between the current + * and the previous fragment */ + valid = 0; + } + } + } + q = iprh_tmp->next_pbuf; + iprh_prev = iprh_tmp; + } + + /* If q is NULL, then we made it to the end of the list. Determine what to do now */ + if (q == NULL) { + if (iprh_prev != NULL) { + /* this is (for now), the fragment with the highest offset: + * chain it to the last fragment */ +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("check fragments don't overlap", iprh_prev->end <= start); +#endif /* IP_REASS_CHECK_OVERLAP */ + iprh_prev->next_pbuf = p; + if (iprh_prev->end != start) { + valid = 0; + } + } else { +#if IP_REASS_CHECK_OVERLAP + LWIP_ASSERT("no previous fragment, this must be the first fragment!", + ipr->p == NULL); +#endif /* IP_REASS_CHECK_OVERLAP */ + /* this is the first fragment we ever received for this ip datagram */ + ipr->p = p; + } + } + + /* Track the current number of pbufs current 'in-flight', in order to limit + the number of fragments that may be enqueued at any one time */ + ip6_reass_pbufcount = (u16_t)(ip6_reass_pbufcount + clen); + + /* Remember IPv6 header if this is the first fragment. */ + if (start == 0) { + /* need to use the none-const pointer here: */ + ipr->iphdr = ip_data.current_ip6_header; + /* Make a backup of the part of the packet data that we are about to + * overwrite, so that we can restore the original later. */ + MEMCPY(ipr->orig_hdr, p->payload, sizeof(*iprh)); + /* For IPV6_FRAG_COPYHEADER there is no need to copy src/dst again, as they + * will be the same as they were. With LWIP_IPV6_SCOPES, the same applies + * to the source/destination zones. */ + } + /* Only after the backup do we get to fill in the actual helper structure. */ + iprh->next_pbuf = next_pbuf; + iprh->start = start; + iprh->end = end; + + /* If this is the last fragment, calculate total packet length. */ + if ((offset & IP6_FRAG_MORE_FLAG) == 0) { + ipr->datagram_len = iprh->end; + } + + /* Additional validity tests: we have received first and last fragment. */ + iprh_tmp = (struct ip6_reass_helper*)ipr->p->payload; + if (iprh_tmp->start != 0) { + valid = 0; + } + if (ipr->datagram_len == 0) { + valid = 0; + } + + /* Final validity test: no gaps between current and last fragment. */ + iprh_prev = iprh; + q = iprh->next_pbuf; + while ((q != NULL) && valid) { + iprh = (struct ip6_reass_helper*)q->payload; + if (iprh_prev->end != iprh->start) { + valid = 0; + break; + } + iprh_prev = iprh; + q = iprh->next_pbuf; + } + + if (valid) { + /* All fragments have been received */ + struct ip6_hdr* iphdr_ptr; + + /* chain together the pbufs contained within the ip6_reassdata list. */ + iprh = (struct ip6_reass_helper*) ipr->p->payload; + while (iprh != NULL) { + next_pbuf = iprh->next_pbuf; + if (next_pbuf != NULL) { + /* Save next helper struct (will be hidden in next step). */ + iprh_tmp = (struct ip6_reass_helper*)next_pbuf->payload; + + /* hide the fragment header for every succeeding fragment */ + pbuf_remove_header(next_pbuf, IP6_FRAG_HLEN); +#if IPV6_FRAG_COPYHEADER + if (IPV6_FRAG_REQROOM > 0) { + /* hide the extra bytes borrowed from ip6_hdr for struct ip6_reass_helper */ + u8_t hdrerr = pbuf_remove_header(next_pbuf, IPV6_FRAG_REQROOM); + LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */ + LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0); + } +#endif + pbuf_cat(ipr->p, next_pbuf); + } + else { + iprh_tmp = NULL; + } + + iprh = iprh_tmp; + } + + /* Get the first pbuf. */ + p = ipr->p; + +#if IPV6_FRAG_COPYHEADER + if (IPV6_FRAG_REQROOM > 0) { + u8_t hdrerr; + /* Restore (only) the bytes that we overwrote beyond the fragment header. + * Those bytes may belong to either the IPv6 header or an extension + * header placed before the fragment header. */ + MEMCPY(p->payload, ipr->orig_hdr, IPV6_FRAG_REQROOM); + /* get back room for struct ip6_reass_helper (only required if sizeof(void*) > 4) */ + hdrerr = pbuf_remove_header(p, IPV6_FRAG_REQROOM); + LWIP_UNUSED_ARG(hdrerr); /* in case of LWIP_NOASSERT */ + LWIP_ASSERT("no room for struct ip6_reass_helper", hdrerr == 0); + } +#endif + + /* We need to get rid of the fragment header itself, which is somewhere in + * the middle of the packet (but still in the first pbuf of the chain). + * Getting rid of the header is required by RFC 2460 Sec. 4.5 and necessary + * in order to be able to reassemble packets that are close to full size + * (i.e., around 65535 bytes). We simply move up all the headers before the + * fragment header, including the IPv6 header, and adjust the payload start + * accordingly. This works because all these headers are in the first pbuf + * of the chain, and because the caller adjusts all its pointers on + * successful reassembly. */ + MEMMOVE((u8_t*)ipr->iphdr + sizeof(struct ip6_frag_hdr), ipr->iphdr, + (size_t)((u8_t*)p->payload - (u8_t*)ipr->iphdr)); + + /* This is where the IPv6 header is now. */ + iphdr_ptr = (struct ip6_hdr*)((u8_t*)ipr->iphdr + + sizeof(struct ip6_frag_hdr)); + + /* Adjust datagram length by adding header lengths. */ + ipr->datagram_len = (u16_t)(ipr->datagram_len + ((u8_t*)p->payload - (u8_t*)iphdr_ptr) + - IP6_HLEN); + + /* Set payload length in ip header. */ + iphdr_ptr->_plen = lwip_htons(ipr->datagram_len); + + /* With the fragment header gone, we now need to adjust the next-header + * field of whatever header was originally before it. Since the packet made + * it through the original header processing routines at least up to the + * fragment header, we do not need any further sanity checks here. */ + if (IP6H_NEXTH(iphdr_ptr) == IP6_NEXTH_FRAGMENT) { + iphdr_ptr->_nexth = ipr->nexth; + } else { + u8_t *ptr = (u8_t *)iphdr_ptr + IP6_HLEN; + while (*ptr != IP6_NEXTH_FRAGMENT) { + ptr += 8 * (1 + ptr[1]); + } + *ptr = ipr->nexth; + } + + /* release the resources allocated for the fragment queue entry */ + if (reassdatagrams == ipr) { + /* it was the first in the list */ + reassdatagrams = ipr->next; + } else { + /* it wasn't the first, so it must have a valid 'prev' */ + LWIP_ASSERT("sanity check linked list", ipr_prev != NULL); + ipr_prev->next = ipr->next; + } + memp_free(MEMP_IP6_REASSDATA, ipr); + + /* adjust the number of pbufs currently queued for reassembly. */ + clen = pbuf_clen(p); + LWIP_ASSERT("ip6_reass_pbufcount >= clen", ip6_reass_pbufcount >= clen); + ip6_reass_pbufcount = (u16_t)(ip6_reass_pbufcount - clen); + + /* Move pbuf back to IPv6 header. This should never fail. */ + if (pbuf_header_force(p, (s16_t)((u8_t*)p->payload - (u8_t*)iphdr_ptr))) { + LWIP_ASSERT("ip6_reass: moving p->payload to ip6 header failed\n", 0); + pbuf_free(p); + return NULL; + } + + /* Return the pbuf chain */ + return p; + } + /* the datagram is not (yet?) reassembled completely */ + return NULL; + +nullreturn: + IP6_FRAG_STATS_INC(ip6_frag.drop); + pbuf_free(p); + return NULL; +} + +#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */ + +#if LWIP_IPV6 && LWIP_IPV6_FRAG + +#if !LWIP_NETIF_TX_SINGLE_PBUF +/** Allocate a new struct pbuf_custom_ref */ +static struct pbuf_custom_ref* +ip6_frag_alloc_pbuf_custom_ref(void) +{ + return (struct pbuf_custom_ref*)memp_malloc(MEMP_FRAG_PBUF); +} + +/** Free a struct pbuf_custom_ref */ +static void +ip6_frag_free_pbuf_custom_ref(struct pbuf_custom_ref* p) +{ + LWIP_ASSERT("p != NULL", p != NULL); + memp_free(MEMP_FRAG_PBUF, p); +} + +/** Free-callback function to free a 'struct pbuf_custom_ref', called by + * pbuf_free. */ +static void +ip6_frag_free_pbuf_custom(struct pbuf *p) +{ + struct pbuf_custom_ref *pcr = (struct pbuf_custom_ref*)p; + LWIP_ASSERT("pcr != NULL", pcr != NULL); + LWIP_ASSERT("pcr == p", (void*)pcr == (void*)p); + if (pcr->original != NULL) { + pbuf_free(pcr->original); + } + ip6_frag_free_pbuf_custom_ref(pcr); +} +#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ + +/** + * Fragment an IPv6 datagram if too large for the netif or path MTU. + * + * Chop the datagram in MTU sized chunks and send them in order + * by pointing PBUF_REFs into p + * + * @param p ipv6 packet to send + * @param netif the netif on which to send + * @param dest destination ipv6 address to which to send + * + * @return ERR_OK if sent successfully, err_t otherwise + */ +err_t +ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest) +{ + struct ip6_hdr *original_ip6hdr; + struct ip6_hdr *ip6hdr; + struct ip6_frag_hdr *frag_hdr; + struct pbuf *rambuf; +#if !LWIP_NETIF_TX_SINGLE_PBUF + struct pbuf *newpbuf; + u16_t newpbuflen = 0; + u16_t left_to_copy; +#endif + static u32_t identification; + u16_t left, cop; + const u16_t mtu = nd6_get_destination_mtu(dest, netif); + const u16_t nfb = (u16_t)((mtu - (IP6_HLEN + IP6_FRAG_HLEN)) & IP6_FRAG_OFFSET_MASK); + u16_t fragment_offset = 0; + u16_t last; + u16_t poff = IP6_HLEN; + + identification++; + + original_ip6hdr = (struct ip6_hdr *)p->payload; + + /* @todo we assume there are no options in the unfragmentable part (IPv6 header). */ + LWIP_ASSERT("p->tot_len >= IP6_HLEN", p->tot_len >= IP6_HLEN); + left = (u16_t)(p->tot_len - IP6_HLEN); + + while (left) { + last = (left <= nfb); + + /* Fill this fragment */ + cop = last ? left : nfb; + +#if LWIP_NETIF_TX_SINGLE_PBUF + rambuf = pbuf_alloc(PBUF_IP, cop + IP6_FRAG_HLEN, PBUF_RAM); + if (rambuf == NULL) { + IP6_FRAG_STATS_INC(ip6_frag.memerr); + return ERR_MEM; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + (rambuf->len == rambuf->tot_len) && (rambuf->next == NULL)); + poff += pbuf_copy_partial(p, (u8_t*)rambuf->payload + IP6_FRAG_HLEN, cop, poff); + /* make room for the IP header */ + if (pbuf_add_header(rambuf, IP6_HLEN)) { + pbuf_free(rambuf); + IP6_FRAG_STATS_INC(ip6_frag.memerr); + return ERR_MEM; + } + /* fill in the IP header */ + SMEMCPY(rambuf->payload, original_ip6hdr, IP6_HLEN); + ip6hdr = (struct ip6_hdr *)rambuf->payload; + frag_hdr = (struct ip6_frag_hdr *)((u8_t*)rambuf->payload + IP6_HLEN); +#else + /* When not using a static buffer, create a chain of pbufs. + * The first will be a PBUF_RAM holding the link, IPv6, and Fragment header. + * The rest will be PBUF_REFs mirroring the pbuf chain to be fragged, + * but limited to the size of an mtu. + */ + rambuf = pbuf_alloc(PBUF_LINK, IP6_HLEN + IP6_FRAG_HLEN, PBUF_RAM); + if (rambuf == NULL) { + IP6_FRAG_STATS_INC(ip6_frag.memerr); + return ERR_MEM; + } + LWIP_ASSERT("this needs a pbuf in one piece!", + (p->len >= (IP6_HLEN))); + SMEMCPY(rambuf->payload, original_ip6hdr, IP6_HLEN); + ip6hdr = (struct ip6_hdr *)rambuf->payload; + frag_hdr = (struct ip6_frag_hdr *)((u8_t*)rambuf->payload + IP6_HLEN); + + /* Can just adjust p directly for needed offset. */ + p->payload = (u8_t *)p->payload + poff; + p->len = (u16_t)(p->len - poff); + p->tot_len = (u16_t)(p->tot_len - poff); + + left_to_copy = cop; + while (left_to_copy) { + struct pbuf_custom_ref *pcr; + newpbuflen = (left_to_copy < p->len) ? left_to_copy : p->len; + /* Is this pbuf already empty? */ + if (!newpbuflen) { + p = p->next; + continue; + } + pcr = ip6_frag_alloc_pbuf_custom_ref(); + if (pcr == NULL) { + pbuf_free(rambuf); + IP6_FRAG_STATS_INC(ip6_frag.memerr); + return ERR_MEM; + } + /* Mirror this pbuf, although we might not need all of it. */ + newpbuf = pbuf_alloced_custom(PBUF_RAW, newpbuflen, PBUF_REF, &pcr->pc, p->payload, newpbuflen); + if (newpbuf == NULL) { + ip6_frag_free_pbuf_custom_ref(pcr); + pbuf_free(rambuf); + IP6_FRAG_STATS_INC(ip6_frag.memerr); + return ERR_MEM; + } + pbuf_ref(p); + pcr->original = p; + pcr->pc.custom_free_function = ip6_frag_free_pbuf_custom; + + /* Add it to end of rambuf's chain, but using pbuf_cat, not pbuf_chain + * so that it is removed when pbuf_dechain is later called on rambuf. + */ + pbuf_cat(rambuf, newpbuf); + left_to_copy = (u16_t)(left_to_copy - newpbuflen); + if (left_to_copy) { + p = p->next; + } + } + poff = newpbuflen; +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + /* Set headers */ + frag_hdr->_nexth = original_ip6hdr->_nexth; + frag_hdr->reserved = 0; + frag_hdr->_fragment_offset = lwip_htons((u16_t)((fragment_offset & IP6_FRAG_OFFSET_MASK) | (last ? 0 : IP6_FRAG_MORE_FLAG))); + frag_hdr->_identification = lwip_htonl(identification); + + IP6H_NEXTH_SET(ip6hdr, IP6_NEXTH_FRAGMENT); + IP6H_PLEN_SET(ip6hdr, (u16_t)(cop + IP6_FRAG_HLEN)); + + /* No need for separate header pbuf - we allowed room for it in rambuf + * when allocated. + */ + IP6_FRAG_STATS_INC(ip6_frag.xmit); + netif->output_ip6(netif, rambuf, dest); + + /* Unfortunately we can't reuse rambuf - the hardware may still be + * using the buffer. Instead we free it (and the ensuing chain) and + * recreate it next time round the loop. If we're lucky the hardware + * will have already sent the packet, the free will really free, and + * there will be zero memory penalty. + */ + + pbuf_free(rambuf); + left = (u16_t)(left - cop); + fragment_offset = (u16_t)(fragment_offset + cop); + } + return ERR_OK; +} + +#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c new file mode 100644 index 0000000..6387d46 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/mld6.c @@ -0,0 +1,626 @@ +/** + * @file + * Multicast listener discovery + * + * @defgroup mld6 MLD6 + * @ingroup ip6 + * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710. + * No support for MLDv2.\n + * Note: The allnodes (ff01::1, ff02::1) group is assumed be received by your + * netif since it must always be received for correct IPv6 operation (e.g. SLAAC). + * Ensure the netif filters are configured accordingly!\n + * The netif flags also need NETIF_FLAG_MLD6 flag set to enable MLD6 on a + * netif ("netif->flags |= NETIF_FLAG_MLD6;").\n + * To be called from TCPIP thread. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +/* Based on igmp.c implementation of igmp v2 protocol */ + +#include "lwip/opt.h" + +#if LWIP_IPV6 && LWIP_IPV6_MLD /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/mld6.h" +#include "lwip/prot/mld6.h" +#include "lwip/icmp6.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/ip.h" +#include "lwip/inet_chksum.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/memp.h" +#include "lwip/stats.h" + +#include + + +/* + * MLD constants + */ +#define MLD6_HL 1 +#define MLD6_JOIN_DELAYING_MEMBER_TMR_MS (500) + +#define MLD6_GROUP_NON_MEMBER 0 +#define MLD6_GROUP_DELAYING_MEMBER 1 +#define MLD6_GROUP_IDLE_MEMBER 2 + +/* Forward declarations. */ +static struct mld_group *mld6_new_group(struct netif *ifp, const ip6_addr_t *addr); +static err_t mld6_remove_group(struct netif *netif, struct mld_group *group); +static void mld6_delayed_report(struct mld_group *group, u16_t maxresp); +static void mld6_send(struct netif *netif, struct mld_group *group, u8_t type); + + +/** + * Stop MLD processing on interface + * + * @param netif network interface on which stop MLD processing + */ +err_t +mld6_stop(struct netif *netif) +{ + struct mld_group *group = netif_mld6_data(netif); + + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, NULL); + + while (group != NULL) { + struct mld_group *next = group->next; /* avoid use-after-free below */ + + /* disable the group at the MAC level */ + if (netif->mld_mac_filter != NULL) { + netif->mld_mac_filter(netif, &(group->group_address), NETIF_DEL_MAC_FILTER); + } + + /* free group */ + memp_free(MEMP_MLD6_GROUP, group); + + /* move to "next" */ + group = next; + } + return ERR_OK; +} + +/** + * Report MLD memberships for this interface + * + * @param netif network interface on which report MLD memberships + */ +void +mld6_report_groups(struct netif *netif) +{ + struct mld_group *group = netif_mld6_data(netif); + + while (group != NULL) { + mld6_delayed_report(group, MLD6_JOIN_DELAYING_MEMBER_TMR_MS); + group = group->next; + } +} + +/** + * Search for a group that is joined on a netif + * + * @param ifp the network interface for which to look + * @param addr the group ipv6 address to search for + * @return a struct mld_group* if the group has been found, + * NULL if the group wasn't found. + */ +struct mld_group * +mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr) +{ + struct mld_group *group = netif_mld6_data(ifp); + + while (group != NULL) { + if (ip6_addr_cmp(&(group->group_address), addr)) { + return group; + } + group = group->next; + } + + return NULL; +} + + +/** + * create a new group + * + * @param ifp the network interface for which to create + * @param addr the new group ipv6 + * @return a struct mld_group*, + * NULL on memory error. + */ +static struct mld_group * +mld6_new_group(struct netif *ifp, const ip6_addr_t *addr) +{ + struct mld_group *group; + + group = (struct mld_group *)memp_malloc(MEMP_MLD6_GROUP); + if (group != NULL) { + ip6_addr_set(&(group->group_address), addr); + group->timer = 0; /* Not running */ + group->group_state = MLD6_GROUP_IDLE_MEMBER; + group->last_reporter_flag = 0; + group->use = 0; + group->next = netif_mld6_data(ifp); + + netif_set_client_data(ifp, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, group); + } + + return group; +} + +/** + * Remove a group from the mld_group_list, but do not free it yet + * + * @param group the group to remove + * @return ERR_OK if group was removed from the list, an err_t otherwise + */ +static err_t +mld6_remove_group(struct netif *netif, struct mld_group *group) +{ + err_t err = ERR_OK; + + /* Is it the first group? */ + if (netif_mld6_data(netif) == group) { + netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, group->next); + } else { + /* look for group further down the list */ + struct mld_group *tmpGroup; + for (tmpGroup = netif_mld6_data(netif); tmpGroup != NULL; tmpGroup = tmpGroup->next) { + if (tmpGroup->next == group) { + tmpGroup->next = group->next; + break; + } + } + /* Group not find group */ + if (tmpGroup == NULL) { + err = ERR_ARG; + } + } + + return err; +} + + +/** + * Process an input MLD message. Called by icmp6_input. + * + * @param p the mld packet, p->payload pointing to the icmpv6 header + * @param inp the netif on which this packet was received + */ +void +mld6_input(struct pbuf *p, struct netif *inp) +{ + struct mld_header *mld_hdr; + struct mld_group *group; + + MLD6_STATS_INC(mld6.recv); + + /* Check that mld header fits in packet. */ + if (p->len < sizeof(struct mld_header)) { + /* @todo debug message */ + pbuf_free(p); + MLD6_STATS_INC(mld6.lenerr); + MLD6_STATS_INC(mld6.drop); + return; + } + + mld_hdr = (struct mld_header *)p->payload; + + switch (mld_hdr->type) { + case ICMP6_TYPE_MLQ: /* Multicast listener query. */ + /* Is it a general query? */ + if (ip6_addr_isallnodes_linklocal(ip6_current_dest_addr()) && + ip6_addr_isany(&(mld_hdr->multicast_address))) { + MLD6_STATS_INC(mld6.rx_general); + /* Report all groups, except all nodes group, and if-local groups. */ + group = netif_mld6_data(inp); + while (group != NULL) { + if ((!(ip6_addr_ismulticast_iflocal(&(group->group_address)))) && + (!(ip6_addr_isallnodes_linklocal(&(group->group_address))))) { + mld6_delayed_report(group, mld_hdr->max_resp_delay); + } + group = group->next; + } + } else { + /* Have we joined this group? + * We use IP6 destination address to have a memory aligned copy. + * mld_hdr->multicast_address should be the same. */ + MLD6_STATS_INC(mld6.rx_group); + group = mld6_lookfor_group(inp, ip6_current_dest_addr()); + if (group != NULL) { + /* Schedule a report. */ + mld6_delayed_report(group, mld_hdr->max_resp_delay); + } + } + break; /* ICMP6_TYPE_MLQ */ + case ICMP6_TYPE_MLR: /* Multicast listener report. */ + /* Have we joined this group? + * We use IP6 destination address to have a memory aligned copy. + * mld_hdr->multicast_address should be the same. */ + MLD6_STATS_INC(mld6.rx_report); + group = mld6_lookfor_group(inp, ip6_current_dest_addr()); + if (group != NULL) { + /* If we are waiting to report, cancel it. */ + if (group->group_state == MLD6_GROUP_DELAYING_MEMBER) { + group->timer = 0; /* stopped */ + group->group_state = MLD6_GROUP_IDLE_MEMBER; + group->last_reporter_flag = 0; + } + } + break; /* ICMP6_TYPE_MLR */ + case ICMP6_TYPE_MLD: /* Multicast listener done. */ + /* Do nothing, router will query us. */ + break; /* ICMP6_TYPE_MLD */ + default: + MLD6_STATS_INC(mld6.proterr); + MLD6_STATS_INC(mld6.drop); + break; + } + + pbuf_free(p); +} + +/** + * @ingroup mld6 + * Join a group on one or all network interfaces. + * + * If the group is to be joined on all interfaces, the given group address must + * not have a zone set (i.e., it must have its zone index set to IP6_NO_ZONE). + * If the group is to be joined on one particular interface, the given group + * address may or may not have a zone set. + * + * @param srcaddr ipv6 address (zoned) of the network interface which should + * join a new group. If IP6_ADDR_ANY6, join on all netifs + * @param groupaddr the ipv6 address of the group to join (possibly but not + * necessarily zoned) + * @return ERR_OK if group was joined on the netif(s), an err_t otherwise + */ +err_t +mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr) +{ + err_t err = ERR_VAL; /* no matching interface */ + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + + /* loop through netif's */ + NETIF_FOREACH(netif) { + /* Should we join this interface ? */ + if (ip6_addr_isany(srcaddr) || + netif_get_ip6_addr_match(netif, srcaddr) >= 0) { + err = mld6_joingroup_netif(netif, groupaddr); + if (err != ERR_OK) { + return err; + } + } + } + + return err; +} + +/** + * @ingroup mld6 + * Join a group on a network interface. + * + * @param netif the network interface which should join a new group. + * @param groupaddr the ipv6 address of the group to join (possibly but not + * necessarily zoned) + * @return ERR_OK if group was joined on the netif, an err_t otherwise + */ +err_t +mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr) +{ + struct mld_group *group; +#if LWIP_IPV6_SCOPES + ip6_addr_t ip6addr; + + /* If the address has a particular scope but no zone set, use the netif to + * set one now. Within the mld6 module, all addresses are properly zoned. */ + if (ip6_addr_lacks_zone(groupaddr, IP6_MULTICAST)) { + ip6_addr_set(&ip6addr, groupaddr); + ip6_addr_assign_zone(&ip6addr, IP6_MULTICAST, netif); + groupaddr = &ip6addr; + } + IP6_ADDR_ZONECHECK_NETIF(groupaddr, netif); +#endif /* LWIP_IPV6_SCOPES */ + + LWIP_ASSERT_CORE_LOCKED(); + + /* find group or create a new one if not found */ + group = mld6_lookfor_group(netif, groupaddr); + + if (group == NULL) { + /* Joining a new group. Create a new group entry. */ + group = mld6_new_group(netif, groupaddr); + if (group == NULL) { + return ERR_MEM; + } + + /* Activate this address on the MAC layer. */ + if (netif->mld_mac_filter != NULL) { + netif->mld_mac_filter(netif, groupaddr, NETIF_ADD_MAC_FILTER); + } + + /* Report our membership. */ + MLD6_STATS_INC(mld6.tx_report); + mld6_send(netif, group, ICMP6_TYPE_MLR); + mld6_delayed_report(group, MLD6_JOIN_DELAYING_MEMBER_TMR_MS); + } + + /* Increment group use */ + group->use++; + return ERR_OK; +} + +/** + * @ingroup mld6 + * Leave a group on a network interface. + * + * Zoning of address follows the same rules as @ref mld6_joingroup. + * + * @param srcaddr ipv6 address (zoned) of the network interface which should + * leave the group. If IP6_ADDR_ANY6, leave on all netifs + * @param groupaddr the ipv6 address of the group to leave (possibly, but not + * necessarily zoned) + * @return ERR_OK if group was left on the netif(s), an err_t otherwise + */ +err_t +mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr) +{ + err_t err = ERR_VAL; /* no matching interface */ + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + + /* loop through netif's */ + NETIF_FOREACH(netif) { + /* Should we leave this interface ? */ + if (ip6_addr_isany(srcaddr) || + netif_get_ip6_addr_match(netif, srcaddr) >= 0) { + err_t res = mld6_leavegroup_netif(netif, groupaddr); + if (err != ERR_OK) { + /* Store this result if we have not yet gotten a success */ + err = res; + } + } + } + + return err; +} + +/** + * @ingroup mld6 + * Leave a group on a network interface. + * + * @param netif the network interface which should leave the group. + * @param groupaddr the ipv6 address of the group to leave (possibly, but not + * necessarily zoned) + * @return ERR_OK if group was left on the netif, an err_t otherwise + */ +err_t +mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr) +{ + struct mld_group *group; +#if LWIP_IPV6_SCOPES + ip6_addr_t ip6addr; + + if (ip6_addr_lacks_zone(groupaddr, IP6_MULTICAST)) { + ip6_addr_set(&ip6addr, groupaddr); + ip6_addr_assign_zone(&ip6addr, IP6_MULTICAST, netif); + groupaddr = &ip6addr; + } + IP6_ADDR_ZONECHECK_NETIF(groupaddr, netif); +#endif /* LWIP_IPV6_SCOPES */ + + LWIP_ASSERT_CORE_LOCKED(); + + /* find group */ + group = mld6_lookfor_group(netif, groupaddr); + + if (group != NULL) { + /* Leave if there is no other use of the group */ + if (group->use <= 1) { + /* Remove the group from the list */ + mld6_remove_group(netif, group); + + /* If we are the last reporter for this group */ + if (group->last_reporter_flag) { + MLD6_STATS_INC(mld6.tx_leave); + mld6_send(netif, group, ICMP6_TYPE_MLD); + } + + /* Disable the group at the MAC level */ + if (netif->mld_mac_filter != NULL) { + netif->mld_mac_filter(netif, groupaddr, NETIF_DEL_MAC_FILTER); + } + + /* free group struct */ + memp_free(MEMP_MLD6_GROUP, group); + } else { + /* Decrement group use */ + group->use--; + } + + /* Left group */ + return ERR_OK; + } + + /* Group not found */ + return ERR_VAL; +} + + +/** + * Periodic timer for mld processing. Must be called every + * MLD6_TMR_INTERVAL milliseconds (100). + * + * When a delaying member expires, a membership report is sent. + */ +void +mld6_tmr(void) +{ + struct netif *netif; + + NETIF_FOREACH(netif) { + struct mld_group *group = netif_mld6_data(netif); + + while (group != NULL) { + if (group->timer > 0) { + group->timer--; + if (group->timer == 0) { + /* If the state is MLD6_GROUP_DELAYING_MEMBER then we send a report for this group */ + if (group->group_state == MLD6_GROUP_DELAYING_MEMBER) { + MLD6_STATS_INC(mld6.tx_report); + mld6_send(netif, group, ICMP6_TYPE_MLR); + group->group_state = MLD6_GROUP_IDLE_MEMBER; + } + } + } + group = group->next; + } + } +} + +/** + * Schedule a delayed membership report for a group + * + * @param group the mld_group for which "delaying" membership report + * should be sent + * @param maxresp_in the max resp delay provided in the query + */ +static void +mld6_delayed_report(struct mld_group *group, u16_t maxresp_in) +{ + /* Convert maxresp from milliseconds to tmr ticks */ + u16_t maxresp = maxresp_in / MLD6_TMR_INTERVAL; + if (maxresp == 0) { + maxresp = 1; + } + +#ifdef LWIP_RAND + /* Randomize maxresp. (if LWIP_RAND is supported) */ + maxresp = (u16_t)(LWIP_RAND() % maxresp); + if (maxresp == 0) { + maxresp = 1; + } +#endif /* LWIP_RAND */ + + /* Apply timer value if no report has been scheduled already. */ + if ((group->group_state == MLD6_GROUP_IDLE_MEMBER) || + ((group->group_state == MLD6_GROUP_DELAYING_MEMBER) && + ((group->timer == 0) || (maxresp < group->timer)))) { + group->timer = maxresp; + group->group_state = MLD6_GROUP_DELAYING_MEMBER; + } +} + +/** + * Send a MLD message (report or done). + * + * An IPv6 hop-by-hop options header with a router alert option + * is prepended. + * + * @param group the group to report or quit + * @param type ICMP6_TYPE_MLR (report) or ICMP6_TYPE_MLD (done) + */ +static void +mld6_send(struct netif *netif, struct mld_group *group, u8_t type) +{ + struct mld_header *mld_hdr; + struct pbuf *p; + const ip6_addr_t *src_addr; + + /* Allocate a packet. Size is MLD header + IPv6 Hop-by-hop options header. */ + p = pbuf_alloc(PBUF_IP, sizeof(struct mld_header) + MLD6_HBH_HLEN, PBUF_RAM); + if (p == NULL) { + MLD6_STATS_INC(mld6.memerr); + return; + } + + /* Move to make room for Hop-by-hop options header. */ + if (pbuf_remove_header(p, MLD6_HBH_HLEN)) { + pbuf_free(p); + MLD6_STATS_INC(mld6.lenerr); + return; + } + + /* Select our source address. */ + if (!ip6_addr_isvalid(netif_ip6_addr_state(netif, 0))) { + /* This is a special case, when we are performing duplicate address detection. + * We must join the multicast group, but we don't have a valid address yet. */ + src_addr = IP6_ADDR_ANY6; + } else { + /* Use link-local address as source address. */ + src_addr = netif_ip6_addr(netif, 0); + } + + /* MLD message header pointer. */ + mld_hdr = (struct mld_header *)p->payload; + + /* Set fields. */ + mld_hdr->type = type; + mld_hdr->code = 0; + mld_hdr->chksum = 0; + mld_hdr->max_resp_delay = 0; + mld_hdr->reserved = 0; + ip6_addr_copy_to_packed(mld_hdr->multicast_address, group->group_address); + +#if CHECKSUM_GEN_ICMP6 + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { + mld_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, + src_addr, &(group->group_address)); + } +#endif /* CHECKSUM_GEN_ICMP6 */ + + /* Add hop-by-hop headers options: router alert with MLD value. */ + ip6_options_add_hbh_ra(p, IP6_NEXTH_ICMP6, IP6_ROUTER_ALERT_VALUE_MLD); + + if (type == ICMP6_TYPE_MLR) { + /* Remember we were the last to report */ + group->last_reporter_flag = 1; + } + + /* Send the packet out. */ + MLD6_STATS_INC(mld6.xmit); + ip6_output_if(p, (ip6_addr_isany(src_addr)) ? NULL : src_addr, &(group->group_address), + MLD6_HL, 0, IP6_NEXTH_HOPBYHOP, netif); + pbuf_free(p); +} + +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c b/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c new file mode 100644 index 0000000..db0c132 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/ipv6/nd6.c @@ -0,0 +1,2434 @@ +/** + * @file + * + * Neighbor discovery and stateless address autoconfiguration for IPv6. + * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 + * (Address autoconfiguration). + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#include "lwip/opt.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/nd6.h" +#include "lwip/priv/nd6_priv.h" +#include "lwip/prot/nd6.h" +#include "lwip/prot/icmp6.h" +#include "lwip/pbuf.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/inet_chksum.h" +#include "lwip/netif.h" +#include "lwip/icmp6.h" +#include "lwip/mld6.h" +#include "lwip/dhcp6.h" +#include "lwip/ip.h" +#include "lwip/stats.h" +#include "lwip/dns.h" + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +#if LWIP_IPV6_DUP_DETECT_ATTEMPTS > IP6_ADDR_TENTATIVE_COUNT_MASK +#error LWIP_IPV6_DUP_DETECT_ATTEMPTS > IP6_ADDR_TENTATIVE_COUNT_MASK +#endif + +/* Router tables. */ +struct nd6_neighbor_cache_entry neighbor_cache[LWIP_ND6_NUM_NEIGHBORS]; +struct nd6_destination_cache_entry destination_cache[LWIP_ND6_NUM_DESTINATIONS]; +struct nd6_prefix_list_entry prefix_list[LWIP_ND6_NUM_PREFIXES]; +struct nd6_router_list_entry default_router_list[LWIP_ND6_NUM_ROUTERS]; + +/* Default values, can be updated by a RA message. */ +u32_t reachable_time = LWIP_ND6_REACHABLE_TIME; +u32_t retrans_timer = LWIP_ND6_RETRANS_TIMER; /* @todo implement this value in timer */ + +/* Index for cache entries. */ +static u8_t nd6_cached_neighbor_index; +static netif_addr_idx_t nd6_cached_destination_index; + +/* Multicast address holder. */ +static ip6_addr_t multicast_address; + +static u8_t nd6_tmr_rs_reduction; + +/* Static buffer to parse RA packet options */ +union ra_options { + struct lladdr_option lladdr; + struct mtu_option mtu; + struct prefix_option prefix; +#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS + struct rdnss_option rdnss; +#endif +}; +static union ra_options nd6_ra_buffer; + +/* Forward declarations. */ +static s8_t nd6_find_neighbor_cache_entry(const ip6_addr_t *ip6addr); +static s8_t nd6_new_neighbor_cache_entry(void); +static void nd6_free_neighbor_cache_entry(s8_t i); +static s16_t nd6_find_destination_cache_entry(const ip6_addr_t *ip6addr); +static s16_t nd6_new_destination_cache_entry(void); +static int nd6_is_prefix_in_netif(const ip6_addr_t *ip6addr, struct netif *netif); +static s8_t nd6_select_router(const ip6_addr_t *ip6addr, struct netif *netif); +static s8_t nd6_get_router(const ip6_addr_t *router_addr, struct netif *netif); +static s8_t nd6_new_router(const ip6_addr_t *router_addr, struct netif *netif); +static s8_t nd6_get_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif); +static s8_t nd6_new_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif); +static s8_t nd6_get_next_hop_entry(const ip6_addr_t *ip6addr, struct netif *netif); +static err_t nd6_queue_packet(s8_t neighbor_index, struct pbuf *q); + +#define ND6_SEND_FLAG_MULTICAST_DEST 0x01 +#define ND6_SEND_FLAG_ALLNODES_DEST 0x02 +#define ND6_SEND_FLAG_ANY_SRC 0x04 +static void nd6_send_ns(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags); +static void nd6_send_na(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags); +static void nd6_send_neighbor_cache_probe(struct nd6_neighbor_cache_entry *entry, u8_t flags); +#if LWIP_IPV6_SEND_ROUTER_SOLICIT +static err_t nd6_send_rs(struct netif *netif); +#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ + +#if LWIP_ND6_QUEUEING +static void nd6_free_q(struct nd6_q_entry *q); +#else /* LWIP_ND6_QUEUEING */ +#define nd6_free_q(q) pbuf_free(q) +#endif /* LWIP_ND6_QUEUEING */ +static void nd6_send_q(s8_t i); + + +/** + * A local address has been determined to be a duplicate. Take the appropriate + * action(s) on the address and the interface as a whole. + * + * @param netif the netif that owns the address + * @param addr_idx the index of the address detected to be a duplicate + */ +static void +nd6_duplicate_addr_detected(struct netif *netif, s8_t addr_idx) +{ + + /* Mark the address as duplicate, but leave its lifetimes alone. If this was + * a manually assigned address, it will remain in existence as duplicate, and + * as such be unusable for any practical purposes until manual intervention. + * If this was an autogenerated address, the address will follow normal + * expiration rules, and thus disappear once its valid lifetime expires. */ + netif_ip6_addr_set_state(netif, addr_idx, IP6_ADDR_DUPLICATED); + +#if LWIP_IPV6_AUTOCONFIG + /* If the affected address was the link-local address that we use to generate + * all other addresses, then we should not continue to use those derived + * addresses either, so mark them as duplicate as well. For autoconfig-only + * setups, this will make the interface effectively unusable, approaching the + * intention of RFC 4862 Sec. 5.4.5. @todo implement the full requirements */ + if (addr_idx == 0) { + s8_t i; + for (i = 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, i)) && + !netif_ip6_addr_isstatic(netif, i)) { + netif_ip6_addr_set_state(netif, i, IP6_ADDR_DUPLICATED); + } + } + } +#endif /* LWIP_IPV6_AUTOCONFIG */ +} + +#if LWIP_IPV6_AUTOCONFIG +/** + * We received a router advertisement that contains a prefix with the + * autoconfiguration flag set. Add or update an associated autogenerated + * address. + * + * @param netif the netif on which the router advertisement arrived + * @param prefix_opt a pointer to the prefix option data + * @param prefix_addr an aligned copy of the prefix address + */ +static void +nd6_process_autoconfig_prefix(struct netif *netif, + struct prefix_option *prefix_opt, const ip6_addr_t *prefix_addr) +{ + ip6_addr_t ip6addr; + u32_t valid_life, pref_life; + u8_t addr_state; + s8_t i, free_idx; + + /* The caller already checks RFC 4862 Sec. 5.5.3 points (a) and (b). We do + * the rest, starting with checks for (c) and (d) here. */ + valid_life = lwip_htonl(prefix_opt->valid_lifetime); + pref_life = lwip_htonl(prefix_opt->preferred_lifetime); + if (pref_life > valid_life || prefix_opt->prefix_length != 64) { + return; /* silently ignore this prefix for autoconfiguration purposes */ + } + + /* If an autogenerated address already exists for this prefix, update its + * lifetimes. An address is considered autogenerated if 1) it is not static + * (i.e., manually assigned), and 2) there is an advertised autoconfiguration + * prefix for it (the one we are processing here). This does not necessarily + * exclude the possibility that the address was actually assigned by, say, + * DHCPv6. If that distinction becomes important in the future, more state + * must be kept. As explained elsewhere we also update lifetimes of tentative + * and duplicate addresses. Skip address slot 0 (the link-local address). */ + for (i = 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + addr_state = netif_ip6_addr_state(netif, i); + if (!ip6_addr_isinvalid(addr_state) && !netif_ip6_addr_isstatic(netif, i) && + ip6_addr_netcmp(prefix_addr, netif_ip6_addr(netif, i))) { + /* Update the valid lifetime, as per RFC 4862 Sec. 5.5.3 point (e). + * The valid lifetime will never drop to zero as a result of this. */ + u32_t remaining_life = netif_ip6_addr_valid_life(netif, i); + if (valid_life > ND6_2HRS || valid_life > remaining_life) { + netif_ip6_addr_set_valid_life(netif, i, valid_life); + } else if (remaining_life > ND6_2HRS) { + netif_ip6_addr_set_valid_life(netif, i, ND6_2HRS); + } + LWIP_ASSERT("bad valid lifetime", !netif_ip6_addr_isstatic(netif, i)); + /* Update the preferred lifetime. No bounds checks are needed here. In + * rare cases the advertisement may un-deprecate the address, though. + * Deprecation is left to the timer code where it is handled anyway. */ + if (pref_life > 0 && addr_state == IP6_ADDR_DEPRECATED) { + netif_ip6_addr_set_state(netif, i, IP6_ADDR_PREFERRED); + } + netif_ip6_addr_set_pref_life(netif, i, pref_life); + return; /* there should be at most one matching address */ + } + } + + /* No autogenerated address exists for this prefix yet. See if we can add a + * new one. However, if IPv6 autoconfiguration is administratively disabled, + * do not generate new addresses, but do keep updating lifetimes for existing + * addresses. Also, when adding new addresses, we must protect explicitly + * against a valid lifetime of zero, because again, we use that as a special + * value. The generated address would otherwise expire immediately anyway. + * Finally, the original link-local address must be usable at all. We start + * creating addresses even if the link-local address is still in tentative + * state though, and deal with the fallout of that upon DAD collision. */ + addr_state = netif_ip6_addr_state(netif, 0); + if (!netif->ip6_autoconfig_enabled || valid_life == IP6_ADDR_LIFE_STATIC || + ip6_addr_isinvalid(addr_state) || ip6_addr_isduplicated(addr_state)) { + return; + } + + /* Construct the new address that we intend to use, and then see if that + * address really does not exist. It might have been added manually, after + * all. As a side effect, find a free slot. Note that we cannot use + * netif_add_ip6_address() here, as it would return ERR_OK if the address + * already did exist, resulting in that address being given lifetimes. */ + IP6_ADDR(&ip6addr, prefix_addr->addr[0], prefix_addr->addr[1], + netif_ip6_addr(netif, 0)->addr[2], netif_ip6_addr(netif, 0)->addr[3]); + ip6_addr_assign_zone(&ip6addr, IP6_UNICAST, netif); + + free_idx = 0; + for (i = 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, i))) { + if (ip6_addr_cmp(&ip6addr, netif_ip6_addr(netif, i))) { + return; /* formed address already exists */ + } + } else if (free_idx == 0) { + free_idx = i; + } + } + if (free_idx == 0) { + return; /* no address slots available, try again on next advertisement */ + } + + /* Assign the new address to the interface. */ + ip_addr_copy_from_ip6(netif->ip6_addr[free_idx], ip6addr); + netif_ip6_addr_set_valid_life(netif, free_idx, valid_life); + netif_ip6_addr_set_pref_life(netif, free_idx, pref_life); + netif_ip6_addr_set_state(netif, free_idx, IP6_ADDR_TENTATIVE); +} +#endif /* LWIP_IPV6_AUTOCONFIG */ + +/** + * Process an incoming neighbor discovery message + * + * @param p the nd packet, p->payload pointing to the icmpv6 header + * @param inp the netif on which this packet was received + */ +void +nd6_input(struct pbuf *p, struct netif *inp) +{ + u8_t msg_type; + s8_t i; + s16_t dest_idx; + + ND6_STATS_INC(nd6.recv); + + msg_type = *((u8_t *)p->payload); + switch (msg_type) { + case ICMP6_TYPE_NA: /* Neighbor Advertisement. */ + { + struct na_header *na_hdr; + struct lladdr_option *lladdr_opt; + ip6_addr_t target_address; + + /* Check that na header fits in packet. */ + if (p->len < (sizeof(struct na_header))) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + na_hdr = (struct na_header *)p->payload; + + /* Create an aligned, zoned copy of the target address. */ + ip6_addr_copy_from_packed(target_address, na_hdr->target_address); + ip6_addr_assign_zone(&target_address, IP6_UNICAST, inp); + + /* Check a subset of the other RFC 4861 Sec. 7.1.2 requirements. */ + if (IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM || na_hdr->code != 0 || + ip6_addr_ismulticast(&target_address)) { + pbuf_free(p); + ND6_STATS_INC(nd6.proterr); + ND6_STATS_INC(nd6.drop); + return; + } + + /* @todo RFC MUST: if IP destination is multicast, Solicited flag is zero */ + /* @todo RFC MUST: all included options have a length greater than zero */ + + /* Unsolicited NA?*/ + if (ip6_addr_ismulticast(ip6_current_dest_addr())) { + /* This is an unsolicited NA. + * link-layer changed? + * part of DAD mechanism? */ + +#if LWIP_IPV6_DUP_DETECT_ATTEMPTS + /* If the target address matches this netif, it is a DAD response. */ + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (!ip6_addr_isinvalid(netif_ip6_addr_state(inp, i)) && + !ip6_addr_isduplicated(netif_ip6_addr_state(inp, i)) && + ip6_addr_cmp(&target_address, netif_ip6_addr(inp, i))) { + /* We are using a duplicate address. */ + nd6_duplicate_addr_detected(inp, i); + + pbuf_free(p); + return; + } + } +#endif /* LWIP_IPV6_DUP_DETECT_ATTEMPTS */ + + /* Check that link-layer address option also fits in packet. */ + if (p->len < (sizeof(struct na_header) + 2)) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header)); + + if (p->len < (sizeof(struct na_header) + (lladdr_opt->length << 3))) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + /* This is an unsolicited NA, most likely there was a LLADDR change. */ + i = nd6_find_neighbor_cache_entry(&target_address); + if (i >= 0) { + if (na_hdr->flags & ND6_FLAG_OVERRIDE) { + MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); + } + } + } else { + /* This is a solicited NA. + * neighbor address resolution response? + * neighbor unreachability detection response? */ + + /* Find the cache entry corresponding to this na. */ + i = nd6_find_neighbor_cache_entry(&target_address); + if (i < 0) { + /* We no longer care about this target address. drop it. */ + pbuf_free(p); + return; + } + + /* Update cache entry. */ + if ((na_hdr->flags & ND6_FLAG_OVERRIDE) || + (neighbor_cache[i].state == ND6_INCOMPLETE)) { + /* Check that link-layer address option also fits in packet. */ + if (p->len < (sizeof(struct na_header) + 2)) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header)); + + if (p->len < (sizeof(struct na_header) + (lladdr_opt->length << 3))) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); + } + + neighbor_cache[i].netif = inp; + neighbor_cache[i].state = ND6_REACHABLE; + neighbor_cache[i].counter.reachable_time = reachable_time; + + /* Send queued packets, if any. */ + if (neighbor_cache[i].q != NULL) { + nd6_send_q(i); + } + } + + break; /* ICMP6_TYPE_NA */ + } + case ICMP6_TYPE_NS: /* Neighbor solicitation. */ + { + struct ns_header *ns_hdr; + struct lladdr_option *lladdr_opt; + ip6_addr_t target_address; + u8_t accepted; + + /* Check that ns header fits in packet. */ + if (p->len < sizeof(struct ns_header)) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + ns_hdr = (struct ns_header *)p->payload; + + /* Create an aligned, zoned copy of the target address. */ + ip6_addr_copy_from_packed(target_address, ns_hdr->target_address); + ip6_addr_assign_zone(&target_address, IP6_UNICAST, inp); + + /* Check a subset of the other RFC 4861 Sec. 7.1.1 requirements. */ + if (IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM || ns_hdr->code != 0 || + ip6_addr_ismulticast(&target_address)) { + pbuf_free(p); + ND6_STATS_INC(nd6.proterr); + ND6_STATS_INC(nd6.drop); + return; + } + + /* @todo RFC MUST: all included options have a length greater than zero */ + /* @todo RFC MUST: if IP source is 'any', destination is solicited-node multicast address */ + /* @todo RFC MUST: if IP source is 'any', there is no source LL address option */ + + /* Check if there is a link-layer address provided. Only point to it if in this buffer. */ + if (p->len >= (sizeof(struct ns_header) + 2)) { + lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct ns_header)); + if (p->len < (sizeof(struct ns_header) + (lladdr_opt->length << 3))) { + lladdr_opt = NULL; + } + } else { + lladdr_opt = NULL; + } + + /* Check if the target address is configured on the receiving netif. */ + accepted = 0; + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) { + if ((ip6_addr_isvalid(netif_ip6_addr_state(inp, i)) || + (ip6_addr_istentative(netif_ip6_addr_state(inp, i)) && + ip6_addr_isany(ip6_current_src_addr()))) && + ip6_addr_cmp(&target_address, netif_ip6_addr(inp, i))) { + accepted = 1; + break; + } + } + + /* NS not for us? */ + if (!accepted) { + pbuf_free(p); + return; + } + + /* Check for ANY address in src (DAD algorithm). */ + if (ip6_addr_isany(ip6_current_src_addr())) { + /* Sender is validating this address. */ + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) { + if (!ip6_addr_isinvalid(netif_ip6_addr_state(inp, i)) && + ip6_addr_cmp(&target_address, netif_ip6_addr(inp, i))) { + /* Send a NA back so that the sender does not use this address. */ + nd6_send_na(inp, netif_ip6_addr(inp, i), ND6_FLAG_OVERRIDE | ND6_SEND_FLAG_ALLNODES_DEST); + if (ip6_addr_istentative(netif_ip6_addr_state(inp, i))) { + /* We shouldn't use this address either. */ + nd6_duplicate_addr_detected(inp, i); + } + } + } + } else { + /* Sender is trying to resolve our address. */ + /* Verify that they included their own link-layer address. */ + if (lladdr_opt == NULL) { + /* Not a valid message. */ + pbuf_free(p); + ND6_STATS_INC(nd6.proterr); + ND6_STATS_INC(nd6.drop); + return; + } + + i = nd6_find_neighbor_cache_entry(ip6_current_src_addr()); + if (i>= 0) { + /* We already have a record for the solicitor. */ + if (neighbor_cache[i].state == ND6_INCOMPLETE) { + neighbor_cache[i].netif = inp; + MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); + + /* Delay probe in case we get confirmation of reachability from upper layer (TCP). */ + neighbor_cache[i].state = ND6_DELAY; + neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; + } + } else { + /* Add their IPv6 address and link-layer address to neighbor cache. + * We will need it at least to send a unicast NA message, but most + * likely we will also be communicating with this node soon. */ + i = nd6_new_neighbor_cache_entry(); + if (i < 0) { + /* We couldn't assign a cache entry for this neighbor. + * we won't be able to reply. drop it. */ + pbuf_free(p); + ND6_STATS_INC(nd6.memerr); + return; + } + neighbor_cache[i].netif = inp; + MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); + ip6_addr_set(&(neighbor_cache[i].next_hop_address), ip6_current_src_addr()); + + /* Receiving a message does not prove reachability: only in one direction. + * Delay probe in case we get confirmation of reachability from upper layer (TCP). */ + neighbor_cache[i].state = ND6_DELAY; + neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; + } + + /* Send back a NA for us. Allocate the reply pbuf. */ + nd6_send_na(inp, &target_address, ND6_FLAG_SOLICITED | ND6_FLAG_OVERRIDE); + } + + break; /* ICMP6_TYPE_NS */ + } + case ICMP6_TYPE_RA: /* Router Advertisement. */ + { + struct ra_header *ra_hdr; + u8_t *buffer; /* Used to copy options. */ + u16_t offset; +#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS + /* There can be multiple RDNSS options per RA */ + u8_t rdnss_server_idx = 0; +#endif /* LWIP_ND6_RDNSS_MAX_DNS_SERVERS */ + + /* Check that RA header fits in packet. */ + if (p->len < sizeof(struct ra_header)) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + ra_hdr = (struct ra_header *)p->payload; + + /* Check a subset of the other RFC 4861 Sec. 6.1.2 requirements. */ + if (!ip6_addr_islinklocal(ip6_current_src_addr()) || + IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM || ra_hdr->code != 0) { + pbuf_free(p); + ND6_STATS_INC(nd6.proterr); + ND6_STATS_INC(nd6.drop); + return; + } + + /* @todo RFC MUST: all included options have a length greater than zero */ + + /* If we are sending RS messages, stop. */ +#if LWIP_IPV6_SEND_ROUTER_SOLICIT + /* ensure at least one solicitation is sent (see RFC 4861, ch. 6.3.7) */ + if ((inp->rs_count < LWIP_ND6_MAX_MULTICAST_SOLICIT) || + (nd6_send_rs(inp) == ERR_OK)) { + inp->rs_count = 0; + } else { + inp->rs_count = 1; + } +#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ + + /* Get the matching default router entry. */ + i = nd6_get_router(ip6_current_src_addr(), inp); + if (i < 0) { + /* Create a new router entry. */ + i = nd6_new_router(ip6_current_src_addr(), inp); + } + + if (i < 0) { + /* Could not create a new router entry. */ + pbuf_free(p); + ND6_STATS_INC(nd6.memerr); + return; + } + + /* Re-set invalidation timer. */ + default_router_list[i].invalidation_timer = lwip_htons(ra_hdr->router_lifetime); + + /* Re-set default timer values. */ +#if LWIP_ND6_ALLOW_RA_UPDATES + if (ra_hdr->retrans_timer > 0) { + retrans_timer = lwip_htonl(ra_hdr->retrans_timer); + } + if (ra_hdr->reachable_time > 0) { + reachable_time = lwip_htonl(ra_hdr->reachable_time); + } +#endif /* LWIP_ND6_ALLOW_RA_UPDATES */ + + /* @todo set default hop limit... */ + /* ra_hdr->current_hop_limit;*/ + + /* Update flags in local entry (incl. preference). */ + default_router_list[i].flags = ra_hdr->flags; + +#if LWIP_IPV6_DHCP6 + /* Trigger DHCPv6 if enabled */ + dhcp6_nd6_ra_trigger(inp, ra_hdr->flags & ND6_RA_FLAG_MANAGED_ADDR_CONFIG, + ra_hdr->flags & ND6_RA_FLAG_OTHER_CONFIG); +#endif + + /* Offset to options. */ + offset = sizeof(struct ra_header); + + /* Process each option. */ + while ((p->tot_len - offset) >= 2) { + u8_t option_type; + u16_t option_len; + int option_len8 = pbuf_try_get_at(p, offset + 1); + if (option_len8 <= 0) { + /* read beyond end or zero length */ + goto lenerr_drop_free_return; + } + option_len = ((u8_t)option_len8) << 3; + if (option_len > p->tot_len - offset) { + /* short packet (option does not fit in) */ + goto lenerr_drop_free_return; + } + if (p->len == p->tot_len) { + /* no need to copy from contiguous pbuf */ + buffer = &((u8_t*)p->payload)[offset]; + } else { + /* check if this option fits into our buffer */ + if (option_len > sizeof(nd6_ra_buffer)) { + option_type = pbuf_get_at(p, offset); + /* invalid option length */ + if (option_type != ND6_OPTION_TYPE_RDNSS) { + goto lenerr_drop_free_return; + } + /* we allow RDNSS option to be longer - we'll just drop some servers */ + option_len = sizeof(nd6_ra_buffer); + } + buffer = (u8_t*)&nd6_ra_buffer; + option_len = pbuf_copy_partial(p, &nd6_ra_buffer, option_len, offset); + } + option_type = buffer[0]; + switch (option_type) { + case ND6_OPTION_TYPE_SOURCE_LLADDR: + { + struct lladdr_option *lladdr_opt; + if (option_len < sizeof(struct lladdr_option)) { + goto lenerr_drop_free_return; + } + lladdr_opt = (struct lladdr_option *)buffer; + if ((default_router_list[i].neighbor_entry != NULL) && + (default_router_list[i].neighbor_entry->state == ND6_INCOMPLETE)) { + SMEMCPY(default_router_list[i].neighbor_entry->lladdr, lladdr_opt->addr, inp->hwaddr_len); + default_router_list[i].neighbor_entry->state = ND6_REACHABLE; + default_router_list[i].neighbor_entry->counter.reachable_time = reachable_time; + } + break; + } + case ND6_OPTION_TYPE_MTU: + { + struct mtu_option *mtu_opt; + u32_t mtu32; + if (option_len < sizeof(struct mtu_option)) { + goto lenerr_drop_free_return; + } + mtu_opt = (struct mtu_option *)buffer; + mtu32 = lwip_htonl(mtu_opt->mtu); + if ((mtu32 >= 1280) && (mtu32 <= 0xffff)) { +#if LWIP_ND6_ALLOW_RA_UPDATES + if (inp->mtu) { + /* don't set the mtu for IPv6 higher than the netif driver supports */ + inp->mtu6 = LWIP_MIN(inp->mtu, (u16_t)mtu32); + } else { + inp->mtu6 = (u16_t)mtu32; + } +#endif /* LWIP_ND6_ALLOW_RA_UPDATES */ + } + break; + } + case ND6_OPTION_TYPE_PREFIX_INFO: + { + struct prefix_option *prefix_opt; + ip6_addr_t prefix_addr; + if (option_len < sizeof(struct prefix_option)) { + goto lenerr_drop_free_return; + } + + prefix_opt = (struct prefix_option *)buffer; + + /* Get a memory-aligned copy of the prefix. */ + ip6_addr_copy_from_packed(prefix_addr, prefix_opt->prefix); + ip6_addr_assign_zone(&prefix_addr, IP6_UNICAST, inp); + + if (!ip6_addr_islinklocal(&prefix_addr)) { + if ((prefix_opt->flags & ND6_PREFIX_FLAG_ON_LINK) && + (prefix_opt->prefix_length == 64)) { + /* Add to on-link prefix list. */ + u32_t valid_life; + s8_t prefix; + + valid_life = lwip_htonl(prefix_opt->valid_lifetime); + + /* find cache entry for this prefix. */ + prefix = nd6_get_onlink_prefix(&prefix_addr, inp); + if (prefix < 0 && valid_life > 0) { + /* Create a new cache entry. */ + prefix = nd6_new_onlink_prefix(&prefix_addr, inp); + } + if (prefix >= 0) { + prefix_list[prefix].invalidation_timer = valid_life; + } + } +#if LWIP_IPV6_AUTOCONFIG + if (prefix_opt->flags & ND6_PREFIX_FLAG_AUTONOMOUS) { + /* Perform processing for autoconfiguration. */ + nd6_process_autoconfig_prefix(inp, prefix_opt, &prefix_addr); + } +#endif /* LWIP_IPV6_AUTOCONFIG */ + } + + break; + } + case ND6_OPTION_TYPE_ROUTE_INFO: + /* @todo implement preferred routes. + struct route_option * route_opt; + route_opt = (struct route_option *)buffer;*/ + + break; +#if LWIP_ND6_RDNSS_MAX_DNS_SERVERS + case ND6_OPTION_TYPE_RDNSS: + { + u8_t num, n; + u16_t copy_offset = offset + SIZEOF_RDNSS_OPTION_BASE; + struct rdnss_option * rdnss_opt; + if (option_len < SIZEOF_RDNSS_OPTION_BASE) { + goto lenerr_drop_free_return; + } + + rdnss_opt = (struct rdnss_option *)buffer; + num = (rdnss_opt->length - 1) / 2; + for (n = 0; (rdnss_server_idx < DNS_MAX_SERVERS) && (n < num); n++) { + ip_addr_t rdnss_address; + + /* Copy directly from pbuf to get an aligned, zoned copy of the prefix. */ + if (pbuf_copy_partial(p, &rdnss_address, sizeof(ip6_addr_p_t), copy_offset) == sizeof(ip6_addr_p_t)) { + IP_SET_TYPE_VAL(rdnss_address, IPADDR_TYPE_V6); + ip6_addr_assign_zone(ip_2_ip6(&rdnss_address), IP6_UNKNOWN, inp); + + if (htonl(rdnss_opt->lifetime) > 0) { + /* TODO implement Lifetime > 0 */ + dns_setserver(rdnss_server_idx++, &rdnss_address); + } else { + /* TODO implement DNS removal in dns.c */ + u8_t s; + for (s = 0; s < DNS_MAX_SERVERS; s++) { + const ip_addr_t *addr = dns_getserver(s); + if(ip_addr_cmp(addr, &rdnss_address)) { + dns_setserver(s, NULL); + } + } + } + } + } + break; + } +#endif /* LWIP_ND6_RDNSS_MAX_DNS_SERVERS */ + default: + /* Unrecognized option, abort. */ + ND6_STATS_INC(nd6.proterr); + break; + } + /* option length is checked earlier to be non-zero to make sure loop ends */ + offset += 8 * (u8_t)option_len8; + } + + break; /* ICMP6_TYPE_RA */ + } + case ICMP6_TYPE_RD: /* Redirect */ + { + struct redirect_header *redir_hdr; + struct lladdr_option *lladdr_opt; + ip6_addr_t destination_address, target_address; + + /* Check that Redir header fits in packet. */ + if (p->len < sizeof(struct redirect_header)) { + /* @todo debug message */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + redir_hdr = (struct redirect_header *)p->payload; + + /* Create an aligned, zoned copy of the destination address. */ + ip6_addr_copy_from_packed(destination_address, redir_hdr->destination_address); + ip6_addr_assign_zone(&destination_address, IP6_UNICAST, inp); + + /* Check a subset of the other RFC 4861 Sec. 8.1 requirements. */ + if (!ip6_addr_islinklocal(ip6_current_src_addr()) || + IP6H_HOPLIM(ip6_current_header()) != ND6_HOPLIM || + redir_hdr->code != 0 || ip6_addr_ismulticast(&destination_address)) { + pbuf_free(p); + ND6_STATS_INC(nd6.proterr); + ND6_STATS_INC(nd6.drop); + return; + } + + /* @todo RFC MUST: IP source address equals first-hop router for destination_address */ + /* @todo RFC MUST: ICMP target address is either link-local address or same as destination_address */ + /* @todo RFC MUST: all included options have a length greater than zero */ + + if (p->len >= (sizeof(struct redirect_header) + 2)) { + lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct redirect_header)); + if (p->len < (sizeof(struct redirect_header) + (lladdr_opt->length << 3))) { + lladdr_opt = NULL; + } + } else { + lladdr_opt = NULL; + } + + /* Find dest address in cache */ + dest_idx = nd6_find_destination_cache_entry(&destination_address); + if (dest_idx < 0) { + /* Destination not in cache, drop packet. */ + pbuf_free(p); + return; + } + + /* Create an aligned, zoned copy of the target address. */ + ip6_addr_copy_from_packed(target_address, redir_hdr->target_address); + ip6_addr_assign_zone(&target_address, IP6_UNICAST, inp); + + /* Set the new target address. */ + ip6_addr_copy(destination_cache[dest_idx].next_hop_addr, target_address); + + /* If Link-layer address of other router is given, try to add to neighbor cache. */ + if (lladdr_opt != NULL) { + if (lladdr_opt->type == ND6_OPTION_TYPE_TARGET_LLADDR) { + i = nd6_find_neighbor_cache_entry(&target_address); + if (i < 0) { + i = nd6_new_neighbor_cache_entry(); + if (i >= 0) { + neighbor_cache[i].netif = inp; + MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); + ip6_addr_copy(neighbor_cache[i].next_hop_address, target_address); + + /* Receiving a message does not prove reachability: only in one direction. + * Delay probe in case we get confirmation of reachability from upper layer (TCP). */ + neighbor_cache[i].state = ND6_DELAY; + neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; + } + } + if (i >= 0) { + if (neighbor_cache[i].state == ND6_INCOMPLETE) { + MEMCPY(neighbor_cache[i].lladdr, lladdr_opt->addr, inp->hwaddr_len); + /* Receiving a message does not prove reachability: only in one direction. + * Delay probe in case we get confirmation of reachability from upper layer (TCP). */ + neighbor_cache[i].state = ND6_DELAY; + neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; + } + } + } + } + break; /* ICMP6_TYPE_RD */ + } + case ICMP6_TYPE_PTB: /* Packet too big */ + { + struct icmp6_hdr *icmp6hdr; /* Packet too big message */ + struct ip6_hdr *ip6hdr; /* IPv6 header of the packet which caused the error */ + u32_t pmtu; + ip6_addr_t destination_address; + + /* Check that ICMPv6 header + IPv6 header fit in payload */ + if (p->len < (sizeof(struct icmp6_hdr) + IP6_HLEN)) { + /* drop short packets */ + pbuf_free(p); + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + return; + } + + icmp6hdr = (struct icmp6_hdr *)p->payload; + ip6hdr = (struct ip6_hdr *)((u8_t*)p->payload + sizeof(struct icmp6_hdr)); + + /* Create an aligned, zoned copy of the destination address. */ + ip6_addr_copy_from_packed(destination_address, ip6hdr->dest); + ip6_addr_assign_zone(&destination_address, IP6_UNKNOWN, inp); + + /* Look for entry in destination cache. */ + dest_idx = nd6_find_destination_cache_entry(&destination_address); + if (dest_idx < 0) { + /* Destination not in cache, drop packet. */ + pbuf_free(p); + return; + } + + /* Change the Path MTU. */ + pmtu = lwip_htonl(icmp6hdr->data); + destination_cache[dest_idx].pmtu = (u16_t)LWIP_MIN(pmtu, 0xFFFF); + + break; /* ICMP6_TYPE_PTB */ + } + + default: + ND6_STATS_INC(nd6.proterr); + ND6_STATS_INC(nd6.drop); + break; /* default */ + } + + pbuf_free(p); + return; +lenerr_drop_free_return: + ND6_STATS_INC(nd6.lenerr); + ND6_STATS_INC(nd6.drop); + pbuf_free(p); +} + + +/** + * Periodic timer for Neighbor discovery functions: + * + * - Update neighbor reachability states + * - Update destination cache entries age + * - Update invalidation timers of default routers and on-link prefixes + * - Update lifetimes of our addresses + * - Perform duplicate address detection (DAD) for our addresses + * - Send router solicitations + */ +void +nd6_tmr(void) +{ + s8_t i; + struct netif *netif; + + /* Process neighbor entries. */ + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + switch (neighbor_cache[i].state) { + case ND6_INCOMPLETE: + if ((neighbor_cache[i].counter.probes_sent >= LWIP_ND6_MAX_MULTICAST_SOLICIT) && + (!neighbor_cache[i].isrouter)) { + /* Retries exceeded. */ + nd6_free_neighbor_cache_entry(i); + } else { + /* Send a NS for this entry. */ + neighbor_cache[i].counter.probes_sent++; + nd6_send_neighbor_cache_probe(&neighbor_cache[i], ND6_SEND_FLAG_MULTICAST_DEST); + } + break; + case ND6_REACHABLE: + /* Send queued packets, if any are left. Should have been sent already. */ + if (neighbor_cache[i].q != NULL) { + nd6_send_q(i); + } + if (neighbor_cache[i].counter.reachable_time <= ND6_TMR_INTERVAL) { + /* Change to stale state. */ + neighbor_cache[i].state = ND6_STALE; + neighbor_cache[i].counter.stale_time = 0; + } else { + neighbor_cache[i].counter.reachable_time -= ND6_TMR_INTERVAL; + } + break; + case ND6_STALE: + neighbor_cache[i].counter.stale_time++; + break; + case ND6_DELAY: + if (neighbor_cache[i].counter.delay_time <= 1) { + /* Change to PROBE state. */ + neighbor_cache[i].state = ND6_PROBE; + neighbor_cache[i].counter.probes_sent = 0; + } else { + neighbor_cache[i].counter.delay_time--; + } + break; + case ND6_PROBE: + if ((neighbor_cache[i].counter.probes_sent >= LWIP_ND6_MAX_MULTICAST_SOLICIT) && + (!neighbor_cache[i].isrouter)) { + /* Retries exceeded. */ + nd6_free_neighbor_cache_entry(i); + } else { + /* Send a NS for this entry. */ + neighbor_cache[i].counter.probes_sent++; + nd6_send_neighbor_cache_probe(&neighbor_cache[i], 0); + } + break; + case ND6_NO_ENTRY: + default: + /* Do nothing. */ + break; + } + } + + /* Process destination entries. */ + for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { + destination_cache[i].age++; + } + + /* Process router entries. */ + for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { + if (default_router_list[i].neighbor_entry != NULL) { + /* Active entry. */ + if (default_router_list[i].invalidation_timer <= ND6_TMR_INTERVAL / 1000) { + /* No more than 1 second remaining. Clear this entry. Also clear any of + * its destination cache entries, as per RFC 4861 Sec. 5.3 and 6.3.5. */ + s8_t j; + for (j = 0; j < LWIP_ND6_NUM_DESTINATIONS; j++) { + if (ip6_addr_cmp(&destination_cache[j].next_hop_addr, + &default_router_list[i].neighbor_entry->next_hop_address)) { + ip6_addr_set_any(&destination_cache[j].destination_addr); + } + } + default_router_list[i].neighbor_entry->isrouter = 0; + default_router_list[i].neighbor_entry = NULL; + default_router_list[i].invalidation_timer = 0; + default_router_list[i].flags = 0; + } else { + default_router_list[i].invalidation_timer -= ND6_TMR_INTERVAL / 1000; + } + } + } + + /* Process prefix entries. */ + for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) { + if (prefix_list[i].netif != NULL) { + if (prefix_list[i].invalidation_timer <= ND6_TMR_INTERVAL / 1000) { + /* Entry timed out, remove it */ + prefix_list[i].invalidation_timer = 0; + prefix_list[i].netif = NULL; + } else { + prefix_list[i].invalidation_timer -= ND6_TMR_INTERVAL / 1000; + } + } + } + + /* Process our own addresses, updating address lifetimes and/or DAD state. */ + NETIF_FOREACH(netif) { + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; ++i) { + u8_t addr_state; +#if LWIP_IPV6_ADDRESS_LIFETIMES + /* Step 1: update address lifetimes (valid and preferred). */ + addr_state = netif_ip6_addr_state(netif, i); + /* RFC 4862 is not entirely clear as to whether address lifetimes affect + * tentative addresses, and is even less clear as to what should happen + * with duplicate addresses. We choose to track and update lifetimes for + * both those types, although for different reasons: + * - for tentative addresses, the line of thought of Sec. 5.7 combined + * with the potentially long period that an address may be in tentative + * state (due to the interface being down) suggests that lifetimes + * should be independent of external factors which would include DAD; + * - for duplicate addresses, retiring them early could result in a new + * but unwanted attempt at marking them as valid, while retiring them + * late/never could clog up address slots on the netif. + * As a result, we may end up expiring addresses of either type here. + */ + if (!ip6_addr_isinvalid(addr_state) && + !netif_ip6_addr_isstatic(netif, i)) { + u32_t life = netif_ip6_addr_valid_life(netif, i); + if (life <= ND6_TMR_INTERVAL / 1000) { + /* The address has expired. */ + netif_ip6_addr_set_valid_life(netif, i, 0); + netif_ip6_addr_set_pref_life(netif, i, 0); + netif_ip6_addr_set_state(netif, i, IP6_ADDR_INVALID); + } else { + if (!ip6_addr_life_isinfinite(life)) { + life -= ND6_TMR_INTERVAL / 1000; + LWIP_ASSERT("bad valid lifetime", life != IP6_ADDR_LIFE_STATIC); + netif_ip6_addr_set_valid_life(netif, i, life); + } + /* The address is still here. Update the preferred lifetime too. */ + life = netif_ip6_addr_pref_life(netif, i); + if (life <= ND6_TMR_INTERVAL / 1000) { + /* This case must also trigger if 'life' was already zero, so as to + * deal correctly with advertised preferred-lifetime reductions. */ + netif_ip6_addr_set_pref_life(netif, i, 0); + if (addr_state == IP6_ADDR_PREFERRED) + netif_ip6_addr_set_state(netif, i, IP6_ADDR_DEPRECATED); + } else if (!ip6_addr_life_isinfinite(life)) { + life -= ND6_TMR_INTERVAL / 1000; + netif_ip6_addr_set_pref_life(netif, i, life); + } + } + } + /* The address state may now have changed, so reobtain it next. */ +#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ + /* Step 2: update DAD state. */ + addr_state = netif_ip6_addr_state(netif, i); + if (ip6_addr_istentative(addr_state)) { + if ((addr_state & IP6_ADDR_TENTATIVE_COUNT_MASK) >= LWIP_IPV6_DUP_DETECT_ATTEMPTS) { + /* No NA received in response. Mark address as valid. For dynamic + * addresses with an expired preferred lifetime, the state is set to + * deprecated right away. That should almost never happen, though. */ + addr_state = IP6_ADDR_PREFERRED; +#if LWIP_IPV6_ADDRESS_LIFETIMES + if (!netif_ip6_addr_isstatic(netif, i) && + netif_ip6_addr_pref_life(netif, i) == 0) { + addr_state = IP6_ADDR_DEPRECATED; + } +#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ + netif_ip6_addr_set_state(netif, i, addr_state); + } else if (netif_is_up(netif) && netif_is_link_up(netif)) { + /* tentative: set next state by increasing by one */ + netif_ip6_addr_set_state(netif, i, addr_state + 1); + /* Send a NS for this address. Use the unspecified address as source + * address in all cases (RFC 4862 Sec. 5.4.2), not in the least + * because as it is, we only consider multicast replies for DAD. */ + nd6_send_ns(netif, netif_ip6_addr(netif, i), + ND6_SEND_FLAG_MULTICAST_DEST | ND6_SEND_FLAG_ANY_SRC); + } + } + } + } + +#if LWIP_IPV6_SEND_ROUTER_SOLICIT + /* Send router solicitation messages, if necessary. */ + if (!nd6_tmr_rs_reduction) { + nd6_tmr_rs_reduction = (ND6_RTR_SOLICITATION_INTERVAL / ND6_TMR_INTERVAL) - 1; + NETIF_FOREACH(netif) { + if ((netif->rs_count > 0) && netif_is_up(netif) && + netif_is_link_up(netif) && + !ip6_addr_isinvalid(netif_ip6_addr_state(netif, 0)) && + !ip6_addr_isduplicated(netif_ip6_addr_state(netif, 0))) { + if (nd6_send_rs(netif) == ERR_OK) { + netif->rs_count--; + } + } + } + } else { + nd6_tmr_rs_reduction--; + } +#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ + +} + +/** Send a neighbor solicitation message for a specific neighbor cache entry + * + * @param entry the neightbor cache entry for wich to send the message + * @param flags one of ND6_SEND_FLAG_* + */ +static void +nd6_send_neighbor_cache_probe(struct nd6_neighbor_cache_entry *entry, u8_t flags) +{ + nd6_send_ns(entry->netif, &entry->next_hop_address, flags); +} + +/** + * Send a neighbor solicitation message + * + * @param netif the netif on which to send the message + * @param target_addr the IPv6 target address for the ND message + * @param flags one of ND6_SEND_FLAG_* + */ +static void +nd6_send_ns(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags) +{ + struct ns_header *ns_hdr; + struct pbuf *p; + const ip6_addr_t *src_addr; + u16_t lladdr_opt_len; + + LWIP_ASSERT("target address is required", target_addr != NULL); + + if (!(flags & ND6_SEND_FLAG_ANY_SRC) && + ip6_addr_isvalid(netif_ip6_addr_state(netif,0))) { + /* Use link-local address as source address. */ + src_addr = netif_ip6_addr(netif, 0); + /* calculate option length (in 8-byte-blocks) */ + lladdr_opt_len = ((netif->hwaddr_len + 2) + 7) >> 3; + } else { + src_addr = IP6_ADDR_ANY6; + /* Option "MUST NOT be included when the source IP address is the unspecified address." */ + lladdr_opt_len = 0; + } + + /* Allocate a packet. */ + p = pbuf_alloc(PBUF_IP, sizeof(struct ns_header) + (lladdr_opt_len << 3), PBUF_RAM); + if (p == NULL) { + ND6_STATS_INC(nd6.memerr); + return; + } + + /* Set fields. */ + ns_hdr = (struct ns_header *)p->payload; + + ns_hdr->type = ICMP6_TYPE_NS; + ns_hdr->code = 0; + ns_hdr->chksum = 0; + ns_hdr->reserved = 0; + ip6_addr_copy_to_packed(ns_hdr->target_address, *target_addr); + + if (lladdr_opt_len != 0) { + struct lladdr_option *lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct ns_header)); + lladdr_opt->type = ND6_OPTION_TYPE_SOURCE_LLADDR; + lladdr_opt->length = (u8_t)lladdr_opt_len; + SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len); + } + + /* Generate the solicited node address for the target address. */ + if (flags & ND6_SEND_FLAG_MULTICAST_DEST) { + ip6_addr_set_solicitednode(&multicast_address, target_addr->addr[3]); + ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif); + target_addr = &multicast_address; + } + +#if CHECKSUM_GEN_ICMP6 + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { + ns_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr, + target_addr); + } +#endif /* CHECKSUM_GEN_ICMP6 */ + + /* Send the packet out. */ + ND6_STATS_INC(nd6.xmit); + ip6_output_if(p, (src_addr == IP6_ADDR_ANY6) ? NULL : src_addr, target_addr, + ND6_HOPLIM, 0, IP6_NEXTH_ICMP6, netif); + pbuf_free(p); +} + +/** + * Send a neighbor advertisement message + * + * @param netif the netif on which to send the message + * @param target_addr the IPv6 target address for the ND message + * @param flags one of ND6_SEND_FLAG_* + */ +static void +nd6_send_na(struct netif *netif, const ip6_addr_t *target_addr, u8_t flags) +{ + struct na_header *na_hdr; + struct lladdr_option *lladdr_opt; + struct pbuf *p; + const ip6_addr_t *src_addr; + const ip6_addr_t *dest_addr; + u16_t lladdr_opt_len; + + LWIP_ASSERT("target address is required", target_addr != NULL); + + /* Use link-local address as source address. */ + /* src_addr = netif_ip6_addr(netif, 0); */ + /* Use target address as source address. */ + src_addr = target_addr; + + /* Allocate a packet. */ + lladdr_opt_len = ((netif->hwaddr_len + 2) >> 3) + (((netif->hwaddr_len + 2) & 0x07) ? 1 : 0); + p = pbuf_alloc(PBUF_IP, sizeof(struct na_header) + (lladdr_opt_len << 3), PBUF_RAM); + if (p == NULL) { + ND6_STATS_INC(nd6.memerr); + return; + } + + /* Set fields. */ + na_hdr = (struct na_header *)p->payload; + lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct na_header)); + + na_hdr->type = ICMP6_TYPE_NA; + na_hdr->code = 0; + na_hdr->chksum = 0; + na_hdr->flags = flags & 0xf0; + na_hdr->reserved[0] = 0; + na_hdr->reserved[1] = 0; + na_hdr->reserved[2] = 0; + ip6_addr_copy_to_packed(na_hdr->target_address, *target_addr); + + lladdr_opt->type = ND6_OPTION_TYPE_TARGET_LLADDR; + lladdr_opt->length = (u8_t)lladdr_opt_len; + SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len); + + /* Generate the solicited node address for the target address. */ + if (flags & ND6_SEND_FLAG_MULTICAST_DEST) { + ip6_addr_set_solicitednode(&multicast_address, target_addr->addr[3]); + ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif); + dest_addr = &multicast_address; + } else if (flags & ND6_SEND_FLAG_ALLNODES_DEST) { + ip6_addr_set_allnodes_linklocal(&multicast_address); + ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif); + dest_addr = &multicast_address; + } else { + dest_addr = ip6_current_src_addr(); + } + +#if CHECKSUM_GEN_ICMP6 + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { + na_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr, + dest_addr); + } +#endif /* CHECKSUM_GEN_ICMP6 */ + + /* Send the packet out. */ + ND6_STATS_INC(nd6.xmit); + ip6_output_if(p, src_addr, dest_addr, + ND6_HOPLIM, 0, IP6_NEXTH_ICMP6, netif); + pbuf_free(p); +} + +#if LWIP_IPV6_SEND_ROUTER_SOLICIT +/** + * Send a router solicitation message + * + * @param netif the netif on which to send the message + */ +static err_t +nd6_send_rs(struct netif *netif) +{ + struct rs_header *rs_hdr; + struct lladdr_option *lladdr_opt; + struct pbuf *p; + const ip6_addr_t *src_addr; + err_t err; + u16_t lladdr_opt_len = 0; + + /* Link-local source address, or unspecified address? */ + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, 0))) { + src_addr = netif_ip6_addr(netif, 0); + } else { + src_addr = IP6_ADDR_ANY6; + } + + /* Generate the all routers target address. */ + ip6_addr_set_allrouters_linklocal(&multicast_address); + ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif); + + /* Allocate a packet. */ + if (src_addr != IP6_ADDR_ANY6) { + lladdr_opt_len = ((netif->hwaddr_len + 2) >> 3) + (((netif->hwaddr_len + 2) & 0x07) ? 1 : 0); + } + p = pbuf_alloc(PBUF_IP, sizeof(struct rs_header) + (lladdr_opt_len << 3), PBUF_RAM); + if (p == NULL) { + ND6_STATS_INC(nd6.memerr); + return ERR_BUF; + } + + /* Set fields. */ + rs_hdr = (struct rs_header *)p->payload; + + rs_hdr->type = ICMP6_TYPE_RS; + rs_hdr->code = 0; + rs_hdr->chksum = 0; + rs_hdr->reserved = 0; + + if (src_addr != IP6_ADDR_ANY6) { + /* Include our hw address. */ + lladdr_opt = (struct lladdr_option *)((u8_t*)p->payload + sizeof(struct rs_header)); + lladdr_opt->type = ND6_OPTION_TYPE_SOURCE_LLADDR; + lladdr_opt->length = (u8_t)lladdr_opt_len; + SMEMCPY(lladdr_opt->addr, netif->hwaddr, netif->hwaddr_len); + } + +#if CHECKSUM_GEN_ICMP6 + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_ICMP6) { + rs_hdr->chksum = ip6_chksum_pseudo(p, IP6_NEXTH_ICMP6, p->len, src_addr, + &multicast_address); + } +#endif /* CHECKSUM_GEN_ICMP6 */ + + /* Send the packet out. */ + ND6_STATS_INC(nd6.xmit); + + err = ip6_output_if(p, (src_addr == IP6_ADDR_ANY6) ? NULL : src_addr, &multicast_address, + ND6_HOPLIM, 0, IP6_NEXTH_ICMP6, netif); + pbuf_free(p); + + return err; +} +#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ + +/** + * Search for a neighbor cache entry + * + * @param ip6addr the IPv6 address of the neighbor + * @return The neighbor cache entry index that matched, -1 if no + * entry is found + */ +static s8_t +nd6_find_neighbor_cache_entry(const ip6_addr_t *ip6addr) +{ + s8_t i; + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if (ip6_addr_cmp(ip6addr, &(neighbor_cache[i].next_hop_address))) { + return i; + } + } + return -1; +} + +/** + * Create a new neighbor cache entry. + * + * If no unused entry is found, will try to recycle an old entry + * according to ad-hoc "age" heuristic. + * + * @return The neighbor cache entry index that was created, -1 if no + * entry could be created + */ +static s8_t +nd6_new_neighbor_cache_entry(void) +{ + s8_t i; + s8_t j; + u32_t time; + + + /* First, try to find an empty entry. */ + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if (neighbor_cache[i].state == ND6_NO_ENTRY) { + return i; + } + } + + /* We need to recycle an entry. in general, do not recycle if it is a router. */ + + /* Next, try to find a Stale entry. */ + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if ((neighbor_cache[i].state == ND6_STALE) && + (!neighbor_cache[i].isrouter)) { + nd6_free_neighbor_cache_entry(i); + return i; + } + } + + /* Next, try to find a Probe entry. */ + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if ((neighbor_cache[i].state == ND6_PROBE) && + (!neighbor_cache[i].isrouter)) { + nd6_free_neighbor_cache_entry(i); + return i; + } + } + + /* Next, try to find a Delayed entry. */ + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if ((neighbor_cache[i].state == ND6_DELAY) && + (!neighbor_cache[i].isrouter)) { + nd6_free_neighbor_cache_entry(i); + return i; + } + } + + /* Next, try to find the oldest reachable entry. */ + time = 0xfffffffful; + j = -1; + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if ((neighbor_cache[i].state == ND6_REACHABLE) && + (!neighbor_cache[i].isrouter)) { + if (neighbor_cache[i].counter.reachable_time < time) { + j = i; + time = neighbor_cache[i].counter.reachable_time; + } + } + } + if (j >= 0) { + nd6_free_neighbor_cache_entry(j); + return j; + } + + /* Next, find oldest incomplete entry without queued packets. */ + time = 0; + j = -1; + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if ( + (neighbor_cache[i].q == NULL) && + (neighbor_cache[i].state == ND6_INCOMPLETE) && + (!neighbor_cache[i].isrouter)) { + if (neighbor_cache[i].counter.probes_sent >= time) { + j = i; + time = neighbor_cache[i].counter.probes_sent; + } + } + } + if (j >= 0) { + nd6_free_neighbor_cache_entry(j); + return j; + } + + /* Next, find oldest incomplete entry with queued packets. */ + time = 0; + j = -1; + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if ((neighbor_cache[i].state == ND6_INCOMPLETE) && + (!neighbor_cache[i].isrouter)) { + if (neighbor_cache[i].counter.probes_sent >= time) { + j = i; + time = neighbor_cache[i].counter.probes_sent; + } + } + } + if (j >= 0) { + nd6_free_neighbor_cache_entry(j); + return j; + } + + /* No more entries to try. */ + return -1; +} + +/** + * Will free any resources associated with a neighbor cache + * entry, and will mark it as unused. + * + * @param i the neighbor cache entry index to free + */ +static void +nd6_free_neighbor_cache_entry(s8_t i) +{ + if ((i < 0) || (i >= LWIP_ND6_NUM_NEIGHBORS)) { + return; + } + if (neighbor_cache[i].isrouter) { + /* isrouter needs to be cleared before deleting a neighbor cache entry */ + return; + } + + /* Free any queued packets. */ + if (neighbor_cache[i].q != NULL) { + nd6_free_q(neighbor_cache[i].q); + neighbor_cache[i].q = NULL; + } + + neighbor_cache[i].state = ND6_NO_ENTRY; + neighbor_cache[i].isrouter = 0; + neighbor_cache[i].netif = NULL; + neighbor_cache[i].counter.reachable_time = 0; + ip6_addr_set_zero(&(neighbor_cache[i].next_hop_address)); +} + +/** + * Search for a destination cache entry + * + * @param ip6addr the IPv6 address of the destination + * @return The destination cache entry index that matched, -1 if no + * entry is found + */ +static s16_t +nd6_find_destination_cache_entry(const ip6_addr_t *ip6addr) +{ + s16_t i; + + IP6_ADDR_ZONECHECK(ip6addr); + + for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { + if (ip6_addr_cmp(ip6addr, &(destination_cache[i].destination_addr))) { + return i; + } + } + return -1; +} + +/** + * Create a new destination cache entry. If no unused entry is found, + * will recycle oldest entry. + * + * @return The destination cache entry index that was created, -1 if no + * entry was created + */ +static s16_t +nd6_new_destination_cache_entry(void) +{ + s16_t i, j; + u32_t age; + + /* Find an empty entry. */ + for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { + if (ip6_addr_isany(&(destination_cache[i].destination_addr))) { + return i; + } + } + + /* Find oldest entry. */ + age = 0; + j = LWIP_ND6_NUM_DESTINATIONS - 1; + for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { + if (destination_cache[i].age > age) { + j = i; + } + } + + return j; +} + +/** + * Clear the destination cache. + * + * This operation may be necessary for consistency in the light of changing + * local addresses and/or use of the gateway hook. + */ +void +nd6_clear_destination_cache(void) +{ + int i; + + for (i = 0; i < LWIP_ND6_NUM_DESTINATIONS; i++) { + ip6_addr_set_any(&destination_cache[i].destination_addr); + } +} + +/** + * Determine whether an address matches an on-link prefix or the subnet of a + * statically assigned address. + * + * @param ip6addr the IPv6 address to match + * @return 1 if the address is on-link, 0 otherwise + */ +static int +nd6_is_prefix_in_netif(const ip6_addr_t *ip6addr, struct netif *netif) +{ + s8_t i; + + /* Check to see if the address matches an on-link prefix. */ + for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) { + if ((prefix_list[i].netif == netif) && + (prefix_list[i].invalidation_timer > 0) && + ip6_addr_netcmp(ip6addr, &(prefix_list[i].prefix))) { + return 1; + } + } + /* Check to see if address prefix matches a manually configured (= static) + * address. Static addresses have an implied /64 subnet assignment. Dynamic + * addresses (from autoconfiguration) have no implied subnet assignment, and + * are thus effectively /128 assignments. See RFC 5942 for more on this. */ + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i)) && + netif_ip6_addr_isstatic(netif, i) && + ip6_addr_netcmp(ip6addr, netif_ip6_addr(netif, i))) { + return 1; + } + } + return 0; +} + +/** + * Select a default router for a destination. + * + * This function is used both for routing and for finding a next-hop target for + * a packet. In the former case, the given netif is NULL, and the returned + * router entry must be for a netif suitable for sending packets (up, link up). + * In the latter case, the given netif is not NULL and restricts router choice. + * + * @param ip6addr the destination address + * @param netif the netif for the outgoing packet, if known + * @return the default router entry index, or -1 if no suitable + * router is found + */ +static s8_t +nd6_select_router(const ip6_addr_t *ip6addr, struct netif *netif) +{ + struct netif *router_netif; + s8_t i, j, valid_router; + static s8_t last_router; + + LWIP_UNUSED_ARG(ip6addr); /* @todo match preferred routes!! (must implement ND6_OPTION_TYPE_ROUTE_INFO) */ + + /* @todo: implement default router preference */ + + /* Look for valid routers. A reachable router is preferred. */ + valid_router = -1; + for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { + /* Is the router netif both set and apppropriate? */ + if (default_router_list[i].neighbor_entry != NULL) { + router_netif = default_router_list[i].neighbor_entry->netif; + if ((router_netif != NULL) && (netif != NULL ? netif == router_netif : + (netif_is_up(router_netif) && netif_is_link_up(router_netif)))) { + /* Is the router valid, i.e., reachable or probably reachable as per + * RFC 4861 Sec. 6.3.6? Note that we will never return a router that + * has no neighbor cache entry, due to the netif association tests. */ + if (default_router_list[i].neighbor_entry->state != ND6_INCOMPLETE) { + /* Is the router known to be reachable? */ + if (default_router_list[i].neighbor_entry->state == ND6_REACHABLE) { + return i; /* valid and reachable - done! */ + } else if (valid_router < 0) { + valid_router = i; /* valid but not known to be reachable */ + } + } + } + } + } + if (valid_router >= 0) { + return valid_router; + } + + /* Look for any router for which we have any information at all. */ + /* last_router is used for round-robin selection of incomplete routers, as + * recommended in RFC 4861 Sec. 6.3.6 point (2). Advance only when picking a + * route, to select the same router as next-hop target in the common case. */ + if ((netif == NULL) && (++last_router >= LWIP_ND6_NUM_ROUTERS)) { + last_router = 0; + } + i = last_router; + for (j = 0; j < LWIP_ND6_NUM_ROUTERS; j++) { + if (default_router_list[i].neighbor_entry != NULL) { + router_netif = default_router_list[i].neighbor_entry->netif; + if ((router_netif != NULL) && (netif != NULL ? netif == router_netif : + (netif_is_up(router_netif) && netif_is_link_up(router_netif)))) { + return i; + } + } + if (++i >= LWIP_ND6_NUM_ROUTERS) { + i = 0; + } + } + + /* no suitable router found. */ + return -1; +} + +/** + * Find a router-announced route to the given destination. This route may be + * based on an on-link prefix or a default router. + * + * If a suitable route is found, the returned netif is guaranteed to be in a + * suitable state (up, link up) to be used for packet transmission. + * + * @param ip6addr the destination IPv6 address + * @return the netif to use for the destination, or NULL if none found + */ +struct netif * +nd6_find_route(const ip6_addr_t *ip6addr) +{ + struct netif *netif; + s8_t i; + + /* @todo decide if it makes sense to check the destination cache first */ + + /* Check if there is a matching on-link prefix. There may be multiple + * matches. Pick the first one that is associated with a suitable netif. */ + for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) { + netif = prefix_list[i].netif; + if ((netif != NULL) && ip6_addr_netcmp(&prefix_list[i].prefix, ip6addr) && + netif_is_up(netif) && netif_is_link_up(netif)) { + return netif; + } + } + + /* No on-link prefix match. Find a router that can forward the packet. */ + i = nd6_select_router(ip6addr, NULL); + if (i >= 0) { + LWIP_ASSERT("selected router must have a neighbor entry", + default_router_list[i].neighbor_entry != NULL); + return default_router_list[i].neighbor_entry->netif; + } + + return NULL; +} + +/** + * Find an entry for a default router. + * + * @param router_addr the IPv6 address of the router + * @param netif the netif on which the router is found, if known + * @return the index of the router entry, or -1 if not found + */ +static s8_t +nd6_get_router(const ip6_addr_t *router_addr, struct netif *netif) +{ + s8_t i; + + IP6_ADDR_ZONECHECK_NETIF(router_addr, netif); + + /* Look for router. */ + for (i = 0; i < LWIP_ND6_NUM_ROUTERS; i++) { + if ((default_router_list[i].neighbor_entry != NULL) && + ((netif != NULL) ? netif == default_router_list[i].neighbor_entry->netif : 1) && + ip6_addr_cmp(router_addr, &(default_router_list[i].neighbor_entry->next_hop_address))) { + return i; + } + } + + /* router not found. */ + return -1; +} + +/** + * Create a new entry for a default router. + * + * @param router_addr the IPv6 address of the router + * @param netif the netif on which the router is connected, if known + * @return the index on the router table, or -1 if could not be created + */ +static s8_t +nd6_new_router(const ip6_addr_t *router_addr, struct netif *netif) +{ + s8_t router_index; + s8_t free_router_index; + s8_t neighbor_index; + + IP6_ADDR_ZONECHECK_NETIF(router_addr, netif); + + /* Do we have a neighbor entry for this router? */ + neighbor_index = nd6_find_neighbor_cache_entry(router_addr); + if (neighbor_index < 0) { + /* Create a neighbor entry for this router. */ + neighbor_index = nd6_new_neighbor_cache_entry(); + if (neighbor_index < 0) { + /* Could not create neighbor entry for this router. */ + return -1; + } + ip6_addr_set(&(neighbor_cache[neighbor_index].next_hop_address), router_addr); + neighbor_cache[neighbor_index].netif = netif; + neighbor_cache[neighbor_index].q = NULL; + neighbor_cache[neighbor_index].state = ND6_INCOMPLETE; + neighbor_cache[neighbor_index].counter.probes_sent = 1; + nd6_send_neighbor_cache_probe(&neighbor_cache[neighbor_index], ND6_SEND_FLAG_MULTICAST_DEST); + } + + /* Mark neighbor as router. */ + neighbor_cache[neighbor_index].isrouter = 1; + + /* Look for empty entry. */ + free_router_index = LWIP_ND6_NUM_ROUTERS; + for (router_index = LWIP_ND6_NUM_ROUTERS - 1; router_index >= 0; router_index--) { + /* check if router already exists (this is a special case for 2 netifs on the same subnet + - e.g. wifi and cable) */ + if(default_router_list[router_index].neighbor_entry == &(neighbor_cache[neighbor_index])){ + return router_index; + } + if (default_router_list[router_index].neighbor_entry == NULL) { + /* remember lowest free index to create a new entry */ + free_router_index = router_index; + } + } + if (free_router_index < LWIP_ND6_NUM_ROUTERS) { + default_router_list[free_router_index].neighbor_entry = &(neighbor_cache[neighbor_index]); + return free_router_index; + } + + /* Could not create a router entry. */ + + /* Mark neighbor entry as not-router. Entry might be useful as neighbor still. */ + neighbor_cache[neighbor_index].isrouter = 0; + + /* router not found. */ + return -1; +} + +/** + * Find the cached entry for an on-link prefix. + * + * @param prefix the IPv6 prefix that is on-link + * @param netif the netif on which the prefix is on-link + * @return the index on the prefix table, or -1 if not found + */ +static s8_t +nd6_get_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif) +{ + s8_t i; + + /* Look for prefix in list. */ + for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) { + if ((ip6_addr_netcmp(&(prefix_list[i].prefix), prefix)) && + (prefix_list[i].netif == netif)) { + return i; + } + } + + /* Entry not available. */ + return -1; +} + +/** + * Creates a new entry for an on-link prefix. + * + * @param prefix the IPv6 prefix that is on-link + * @param netif the netif on which the prefix is on-link + * @return the index on the prefix table, or -1 if not created + */ +static s8_t +nd6_new_onlink_prefix(const ip6_addr_t *prefix, struct netif *netif) +{ + s8_t i; + + /* Create new entry. */ + for (i = 0; i < LWIP_ND6_NUM_PREFIXES; ++i) { + if ((prefix_list[i].netif == NULL) || + (prefix_list[i].invalidation_timer == 0)) { + /* Found empty prefix entry. */ + prefix_list[i].netif = netif; + ip6_addr_set(&(prefix_list[i].prefix), prefix); + return i; + } + } + + /* Entry not available. */ + return -1; +} + +/** + * Determine the next hop for a destination. Will determine if the + * destination is on-link, else a suitable on-link router is selected. + * + * The last entry index is cached for fast entry search. + * + * @param ip6addr the destination address + * @param netif the netif on which the packet will be sent + * @return the neighbor cache entry for the next hop, ERR_RTE if no + * suitable next hop was found, ERR_MEM if no cache entry + * could be created + */ +static s8_t +nd6_get_next_hop_entry(const ip6_addr_t *ip6addr, struct netif *netif) +{ +#ifdef LWIP_HOOK_ND6_GET_GW + const ip6_addr_t *next_hop_addr; +#endif /* LWIP_HOOK_ND6_GET_GW */ + s8_t i; + s16_t dst_idx; + + IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif); + +#if LWIP_NETIF_HWADDRHINT + if (netif->hints != NULL) { + /* per-pcb cached entry was given */ + netif_addr_idx_t addr_hint = netif->hints->addr_hint; + if (addr_hint < LWIP_ND6_NUM_DESTINATIONS) { + nd6_cached_destination_index = addr_hint; + } + } +#endif /* LWIP_NETIF_HWADDRHINT */ + + /* Look for ip6addr in destination cache. */ + if (ip6_addr_cmp(ip6addr, &(destination_cache[nd6_cached_destination_index].destination_addr))) { + /* the cached entry index is the right one! */ + /* do nothing. */ + ND6_STATS_INC(nd6.cachehit); + } else { + /* Search destination cache. */ + dst_idx = nd6_find_destination_cache_entry(ip6addr); + if (dst_idx >= 0) { + /* found destination entry. make it our new cached index. */ + LWIP_ASSERT("type overflow", (size_t)dst_idx < NETIF_ADDR_IDX_MAX); + nd6_cached_destination_index = (netif_addr_idx_t)dst_idx; + } else { + /* Not found. Create a new destination entry. */ + dst_idx = nd6_new_destination_cache_entry(); + if (dst_idx >= 0) { + /* got new destination entry. make it our new cached index. */ + LWIP_ASSERT("type overflow", (size_t)dst_idx < NETIF_ADDR_IDX_MAX); + nd6_cached_destination_index = (netif_addr_idx_t)dst_idx; + } else { + /* Could not create a destination cache entry. */ + return ERR_MEM; + } + + /* Copy dest address to destination cache. */ + ip6_addr_set(&(destination_cache[nd6_cached_destination_index].destination_addr), ip6addr); + + /* Now find the next hop. is it a neighbor? */ + if (ip6_addr_islinklocal(ip6addr) || + nd6_is_prefix_in_netif(ip6addr, netif)) { + /* Destination in local link. */ + destination_cache[nd6_cached_destination_index].pmtu = netif_mtu6(netif); + ip6_addr_copy(destination_cache[nd6_cached_destination_index].next_hop_addr, destination_cache[nd6_cached_destination_index].destination_addr); +#ifdef LWIP_HOOK_ND6_GET_GW + } else if ((next_hop_addr = LWIP_HOOK_ND6_GET_GW(netif, ip6addr)) != NULL) { + /* Next hop for destination provided by hook function. */ + destination_cache[nd6_cached_destination_index].pmtu = netif->mtu; + ip6_addr_set(&destination_cache[nd6_cached_destination_index].next_hop_addr, next_hop_addr); +#endif /* LWIP_HOOK_ND6_GET_GW */ + } else { + /* We need to select a router. */ + i = nd6_select_router(ip6addr, netif); + if (i < 0) { + /* No router found. */ + ip6_addr_set_any(&(destination_cache[nd6_cached_destination_index].destination_addr)); + return ERR_RTE; + } + destination_cache[nd6_cached_destination_index].pmtu = netif_mtu6(netif); /* Start with netif mtu, correct through ICMPv6 if necessary */ + ip6_addr_copy(destination_cache[nd6_cached_destination_index].next_hop_addr, default_router_list[i].neighbor_entry->next_hop_address); + } + } + } + +#if LWIP_NETIF_HWADDRHINT + if (netif->hints != NULL) { + /* per-pcb cached entry was given */ + netif->hints->addr_hint = nd6_cached_destination_index; + } +#endif /* LWIP_NETIF_HWADDRHINT */ + + /* Look in neighbor cache for the next-hop address. */ + if (ip6_addr_cmp(&(destination_cache[nd6_cached_destination_index].next_hop_addr), + &(neighbor_cache[nd6_cached_neighbor_index].next_hop_address))) { + /* Cache hit. */ + /* Do nothing. */ + ND6_STATS_INC(nd6.cachehit); + } else { + i = nd6_find_neighbor_cache_entry(&(destination_cache[nd6_cached_destination_index].next_hop_addr)); + if (i >= 0) { + /* Found a matching record, make it new cached entry. */ + nd6_cached_neighbor_index = i; + } else { + /* Neighbor not in cache. Make a new entry. */ + i = nd6_new_neighbor_cache_entry(); + if (i >= 0) { + /* got new neighbor entry. make it our new cached index. */ + nd6_cached_neighbor_index = i; + } else { + /* Could not create a neighbor cache entry. */ + return ERR_MEM; + } + + /* Initialize fields. */ + ip6_addr_copy(neighbor_cache[i].next_hop_address, + destination_cache[nd6_cached_destination_index].next_hop_addr); + neighbor_cache[i].isrouter = 0; + neighbor_cache[i].netif = netif; + neighbor_cache[i].state = ND6_INCOMPLETE; + neighbor_cache[i].counter.probes_sent = 1; + nd6_send_neighbor_cache_probe(&neighbor_cache[i], ND6_SEND_FLAG_MULTICAST_DEST); + } + } + + /* Reset this destination's age. */ + destination_cache[nd6_cached_destination_index].age = 0; + + return nd6_cached_neighbor_index; +} + +/** + * Queue a packet for a neighbor. + * + * @param neighbor_index the index in the neighbor cache table + * @param q packet to be queued + * @return ERR_OK if succeeded, ERR_MEM if out of memory + */ +static err_t +nd6_queue_packet(s8_t neighbor_index, struct pbuf *q) +{ + err_t result = ERR_MEM; + struct pbuf *p; + int copy_needed = 0; +#if LWIP_ND6_QUEUEING + struct nd6_q_entry *new_entry, *r; +#endif /* LWIP_ND6_QUEUEING */ + + if ((neighbor_index < 0) || (neighbor_index >= LWIP_ND6_NUM_NEIGHBORS)) { + return ERR_ARG; + } + + /* IF q includes a pbuf that must be copied, we have to copy the whole chain + * into a new PBUF_RAM. See the definition of PBUF_NEEDS_COPY for details. */ + p = q; + while (p) { + if (PBUF_NEEDS_COPY(p)) { + copy_needed = 1; + break; + } + p = p->next; + } + if (copy_needed) { + /* copy the whole packet into new pbufs */ + p = pbuf_clone(PBUF_LINK, PBUF_RAM, q); + while ((p == NULL) && (neighbor_cache[neighbor_index].q != NULL)) { + /* Free oldest packet (as per RFC recommendation) */ +#if LWIP_ND6_QUEUEING + r = neighbor_cache[neighbor_index].q; + neighbor_cache[neighbor_index].q = r->next; + r->next = NULL; + nd6_free_q(r); +#else /* LWIP_ND6_QUEUEING */ + pbuf_free(neighbor_cache[neighbor_index].q); + neighbor_cache[neighbor_index].q = NULL; +#endif /* LWIP_ND6_QUEUEING */ + p = pbuf_clone(PBUF_LINK, PBUF_RAM, q); + } + } else { + /* referencing the old pbuf is enough */ + p = q; + pbuf_ref(p); + } + /* packet was copied/ref'd? */ + if (p != NULL) { + /* queue packet ... */ +#if LWIP_ND6_QUEUEING + /* allocate a new nd6 queue entry */ + new_entry = (struct nd6_q_entry *)memp_malloc(MEMP_ND6_QUEUE); + if ((new_entry == NULL) && (neighbor_cache[neighbor_index].q != NULL)) { + /* Free oldest packet (as per RFC recommendation) */ + r = neighbor_cache[neighbor_index].q; + neighbor_cache[neighbor_index].q = r->next; + r->next = NULL; + nd6_free_q(r); + new_entry = (struct nd6_q_entry *)memp_malloc(MEMP_ND6_QUEUE); + } + if (new_entry != NULL) { + new_entry->next = NULL; + new_entry->p = p; + if (neighbor_cache[neighbor_index].q != NULL) { + /* queue was already existent, append the new entry to the end */ + r = neighbor_cache[neighbor_index].q; + while (r->next != NULL) { + r = r->next; + } + r->next = new_entry; + } else { + /* queue did not exist, first item in queue */ + neighbor_cache[neighbor_index].q = new_entry; + } + LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: queued packet %p on neighbor entry %"S16_F"\n", (void *)p, (s16_t)neighbor_index)); + result = ERR_OK; + } else { + /* the pool MEMP_ND6_QUEUE is empty */ + pbuf_free(p); + LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: could not queue a copy of packet %p (out of memory)\n", (void *)p)); + /* { result == ERR_MEM } through initialization */ + } +#else /* LWIP_ND6_QUEUEING */ + /* Queue a single packet. If an older packet is already queued, free it as per RFC. */ + if (neighbor_cache[neighbor_index].q != NULL) { + pbuf_free(neighbor_cache[neighbor_index].q); + } + neighbor_cache[neighbor_index].q = p; + LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: queued packet %p on neighbor entry %"S16_F"\n", (void *)p, (s16_t)neighbor_index)); + result = ERR_OK; +#endif /* LWIP_ND6_QUEUEING */ + } else { + LWIP_DEBUGF(LWIP_DBG_TRACE, ("ipv6: could not queue a copy of packet %p (out of memory)\n", (void *)q)); + /* { result == ERR_MEM } through initialization */ + } + + return result; +} + +#if LWIP_ND6_QUEUEING +/** + * Free a complete queue of nd6 q entries + * + * @param q a queue of nd6_q_entry to free + */ +static void +nd6_free_q(struct nd6_q_entry *q) +{ + struct nd6_q_entry *r; + LWIP_ASSERT("q != NULL", q != NULL); + LWIP_ASSERT("q->p != NULL", q->p != NULL); + while (q) { + r = q; + q = q->next; + LWIP_ASSERT("r->p != NULL", (r->p != NULL)); + pbuf_free(r->p); + memp_free(MEMP_ND6_QUEUE, r); + } +} +#endif /* LWIP_ND6_QUEUEING */ + +/** + * Send queued packets for a neighbor + * + * @param i the neighbor to send packets to + */ +static void +nd6_send_q(s8_t i) +{ + struct ip6_hdr *ip6hdr; + ip6_addr_t dest; +#if LWIP_ND6_QUEUEING + struct nd6_q_entry *q; +#endif /* LWIP_ND6_QUEUEING */ + + if ((i < 0) || (i >= LWIP_ND6_NUM_NEIGHBORS)) { + return; + } + +#if LWIP_ND6_QUEUEING + while (neighbor_cache[i].q != NULL) { + /* remember first in queue */ + q = neighbor_cache[i].q; + /* pop first item off the queue */ + neighbor_cache[i].q = q->next; + /* Get ipv6 header. */ + ip6hdr = (struct ip6_hdr *)(q->p->payload); + /* Create an aligned copy. */ + ip6_addr_copy_from_packed(dest, ip6hdr->dest); + /* Restore the zone, if applicable. */ + ip6_addr_assign_zone(&dest, IP6_UNKNOWN, neighbor_cache[i].netif); + /* send the queued IPv6 packet */ + (neighbor_cache[i].netif)->output_ip6(neighbor_cache[i].netif, q->p, &dest); + /* free the queued IP packet */ + pbuf_free(q->p); + /* now queue entry can be freed */ + memp_free(MEMP_ND6_QUEUE, q); + } +#else /* LWIP_ND6_QUEUEING */ + if (neighbor_cache[i].q != NULL) { + /* Get ipv6 header. */ + ip6hdr = (struct ip6_hdr *)(neighbor_cache[i].q->payload); + /* Create an aligned copy. */ + ip6_addr_copy_from_packed(dest, ip6hdr->dest); + /* Restore the zone, if applicable. */ + ip6_addr_assign_zone(&dest, IP6_UNKNOWN, neighbor_cache[i].netif); + /* send the queued IPv6 packet */ + (neighbor_cache[i].netif)->output_ip6(neighbor_cache[i].netif, neighbor_cache[i].q, &dest); + /* free the queued IP packet */ + pbuf_free(neighbor_cache[i].q); + neighbor_cache[i].q = NULL; + } +#endif /* LWIP_ND6_QUEUEING */ +} + +/** + * A packet is to be transmitted to a specific IPv6 destination on a specific + * interface. Check if we can find the hardware address of the next hop to use + * for the packet. If so, give the hardware address to the caller, which should + * use it to send the packet right away. Otherwise, enqueue the packet for + * later transmission while looking up the hardware address, if possible. + * + * As such, this function returns one of three different possible results: + * + * - ERR_OK with a non-NULL 'hwaddrp': the caller should send the packet now. + * - ERR_OK with a NULL 'hwaddrp': the packet has been enqueued for later. + * - not ERR_OK: something went wrong; forward the error upward in the stack. + * + * @param netif The lwIP network interface on which the IP packet will be sent. + * @param q The pbuf(s) containing the IP packet to be sent. + * @param ip6addr The destination IPv6 address of the packet. + * @param hwaddrp On success, filled with a pointer to a HW address or NULL (meaning + * the packet has been queued). + * @return + * - ERR_OK on success, ERR_RTE if no route was found for the packet, + * or ERR_MEM if low memory conditions prohibit sending the packet at all. + */ +err_t +nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp) +{ + s8_t i; + + /* Get next hop record. */ + i = nd6_get_next_hop_entry(ip6addr, netif); + if (i < 0) { + /* failed to get a next hop neighbor record. */ + return i; + } + + /* Now that we have a destination record, send or queue the packet. */ + if (neighbor_cache[i].state == ND6_STALE) { + /* Switch to delay state. */ + neighbor_cache[i].state = ND6_DELAY; + neighbor_cache[i].counter.delay_time = LWIP_ND6_DELAY_FIRST_PROBE_TIME / ND6_TMR_INTERVAL; + } + /* @todo should we send or queue if PROBE? send for now, to let unicast NS pass. */ + if ((neighbor_cache[i].state == ND6_REACHABLE) || + (neighbor_cache[i].state == ND6_DELAY) || + (neighbor_cache[i].state == ND6_PROBE)) { + + /* Tell the caller to send out the packet now. */ + *hwaddrp = neighbor_cache[i].lladdr; + return ERR_OK; + } + + /* We should queue packet on this interface. */ + *hwaddrp = NULL; + return nd6_queue_packet(i, q); +} + + +/** + * Get the Path MTU for a destination. + * + * @param ip6addr the destination address + * @param netif the netif on which the packet will be sent + * @return the Path MTU, if known, or the netif default MTU + */ +u16_t +nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif) +{ + s16_t i; + + i = nd6_find_destination_cache_entry(ip6addr); + if (i >= 0) { + if (destination_cache[i].pmtu > 0) { + return destination_cache[i].pmtu; + } + } + + if (netif != NULL) { + return netif_mtu6(netif); + } + + return 1280; /* Minimum MTU */ +} + + +#if LWIP_ND6_TCP_REACHABILITY_HINTS +/** + * Provide the Neighbor discovery process with a hint that a + * destination is reachable. Called by tcp_receive when ACKs are + * received or sent (as per RFC). This is useful to avoid sending + * NS messages every 30 seconds. + * + * @param ip6addr the destination address which is know to be reachable + * by an upper layer protocol (TCP) + */ +void +nd6_reachability_hint(const ip6_addr_t *ip6addr) +{ + s8_t i; + s16_t dst_idx; + + /* Find destination in cache. */ + if (ip6_addr_cmp(ip6addr, &(destination_cache[nd6_cached_destination_index].destination_addr))) { + dst_idx = nd6_cached_destination_index; + ND6_STATS_INC(nd6.cachehit); + } else { + dst_idx = nd6_find_destination_cache_entry(ip6addr); + } + if (dst_idx < 0) { + return; + } + + /* Find next hop neighbor in cache. */ + if (ip6_addr_cmp(&(destination_cache[dst_idx].next_hop_addr), &(neighbor_cache[nd6_cached_neighbor_index].next_hop_address))) { + i = nd6_cached_neighbor_index; + ND6_STATS_INC(nd6.cachehit); + } else { + i = nd6_find_neighbor_cache_entry(&(destination_cache[dst_idx].next_hop_addr)); + } + if (i < 0) { + return; + } + + /* For safety: don't set as reachable if we don't have a LL address yet. Misuse protection. */ + if (neighbor_cache[i].state == ND6_INCOMPLETE || neighbor_cache[i].state == ND6_NO_ENTRY) { + return; + } + + /* Set reachability state. */ + neighbor_cache[i].state = ND6_REACHABLE; + neighbor_cache[i].counter.reachable_time = reachable_time; +} +#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */ + +/** + * Remove all prefix, neighbor_cache and router entries of the specified netif. + * + * @param netif points to a network interface + */ +void +nd6_cleanup_netif(struct netif *netif) +{ + u8_t i; + s8_t router_index; + for (i = 0; i < LWIP_ND6_NUM_PREFIXES; i++) { + if (prefix_list[i].netif == netif) { + prefix_list[i].netif = NULL; + } + } + for (i = 0; i < LWIP_ND6_NUM_NEIGHBORS; i++) { + if (neighbor_cache[i].netif == netif) { + for (router_index = 0; router_index < LWIP_ND6_NUM_ROUTERS; router_index++) { + if (default_router_list[router_index].neighbor_entry == &neighbor_cache[i]) { + default_router_list[router_index].neighbor_entry = NULL; + default_router_list[router_index].flags = 0; + } + } + neighbor_cache[i].isrouter = 0; + nd6_free_neighbor_cache_entry(i); + } + } + /* Clear the destination cache, since many entries may now have become + * invalid for one of several reasons. As destination cache entries have no + * netif association, use a sledgehammer approach (this can be improved). */ + nd6_clear_destination_cache(); +} + +#if LWIP_IPV6_MLD +/** + * The state of a local IPv6 address entry is about to change. If needed, join + * or leave the solicited-node multicast group for the address. + * + * @param netif The netif that owns the address. + * @param addr_idx The index of the address. + * @param new_state The new (IP6_ADDR_) state for the address. + */ +void +nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state) +{ + u8_t old_state, old_member, new_member; + + old_state = netif_ip6_addr_state(netif, addr_idx); + + /* Determine whether we were, and should be, a member of the solicited-node + * multicast group for this address. For tentative addresses, the group is + * not joined until the address enters the TENTATIVE_1 (or VALID) state. */ + old_member = (old_state != IP6_ADDR_INVALID && old_state != IP6_ADDR_DUPLICATED && old_state != IP6_ADDR_TENTATIVE); + new_member = (new_state != IP6_ADDR_INVALID && new_state != IP6_ADDR_DUPLICATED && new_state != IP6_ADDR_TENTATIVE); + + if (old_member != new_member) { + ip6_addr_set_solicitednode(&multicast_address, netif_ip6_addr(netif, addr_idx)->addr[3]); + ip6_addr_assign_zone(&multicast_address, IP6_MULTICAST, netif); + + if (new_member) { + mld6_joingroup_netif(netif, &multicast_address); + } else { + mld6_leavegroup_netif(netif, &multicast_address); + } + } +} +#endif /* LWIP_IPV6_MLD */ + +/** Netif was added, set up, or reconnected (link up) */ +void +nd6_restart_netif(struct netif *netif) +{ +#if LWIP_IPV6_SEND_ROUTER_SOLICIT + /* Send Router Solicitation messages (see RFC 4861, ch. 6.3.7). */ + netif->rs_count = LWIP_ND6_MAX_MULTICAST_SOLICIT; +#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ +} + +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/core/mem.c b/Middlewares/Third_Party/LwIP/src/core/mem.c new file mode 100644 index 0000000..315fb3c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/mem.c @@ -0,0 +1,1017 @@ +/** + * @file + * Dynamic memory manager + * + * This is a lightweight replacement for the standard C library malloc(). + * + * If you want to use the standard C library malloc() instead, define + * MEM_LIBC_MALLOC to 1 in your lwipopts.h + * + * To let mem_malloc() use pools (prevents fragmentation and is much faster than + * a heap but might waste some memory), define MEM_USE_POOLS to 1, define + * MEMP_USE_CUSTOM_POOLS to 1 and create a file "lwippools.h" that includes a list + * of pools like this (more pools can be added between _START and _END): + * + * Define three pools with sizes 256, 512, and 1512 bytes + * LWIP_MALLOC_MEMPOOL_START + * LWIP_MALLOC_MEMPOOL(20, 256) + * LWIP_MALLOC_MEMPOOL(10, 512) + * LWIP_MALLOC_MEMPOOL(5, 1512) + * LWIP_MALLOC_MEMPOOL_END + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ + +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/def.h" +#include "lwip/sys.h" +#include "lwip/stats.h" +#include "lwip/err.h" + +#include + +#if MEM_LIBC_MALLOC +#include /* for malloc()/free() */ +#endif + +/* This is overridable for tests only... */ +#ifndef LWIP_MEM_ILLEGAL_FREE +#define LWIP_MEM_ILLEGAL_FREE(msg) LWIP_ASSERT(msg, 0) +#endif + +#define MEM_STATS_INC_LOCKED(x) SYS_ARCH_LOCKED(MEM_STATS_INC(x)) +#define MEM_STATS_INC_USED_LOCKED(x, y) SYS_ARCH_LOCKED(MEM_STATS_INC_USED(x, y)) +#define MEM_STATS_DEC_USED_LOCKED(x, y) SYS_ARCH_LOCKED(MEM_STATS_DEC_USED(x, y)) + +#if MEM_OVERFLOW_CHECK +#define MEM_SANITY_OFFSET MEM_SANITY_REGION_BEFORE_ALIGNED +#define MEM_SANITY_OVERHEAD (MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED) +#else +#define MEM_SANITY_OFFSET 0 +#define MEM_SANITY_OVERHEAD 0 +#endif + +#if MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK +/** + * Check if a mep element was victim of an overflow or underflow + * (e.g. the restricted area after/before it has been altered) + * + * @param p the mem element to check + * @param size allocated size of the element + * @param descr1 description of the element source shown on error + * @param descr2 description of the element source shown on error + */ +void +mem_overflow_check_raw(void *p, size_t size, const char *descr1, const char *descr2) +{ +#if MEM_SANITY_REGION_AFTER_ALIGNED || MEM_SANITY_REGION_BEFORE_ALIGNED + u16_t k; + u8_t *m; + +#if MEM_SANITY_REGION_AFTER_ALIGNED > 0 + m = (u8_t *)p + size; + for (k = 0; k < MEM_SANITY_REGION_AFTER_ALIGNED; k++) { + if (m[k] != 0xcd) { + char errstr[128]; + snprintf(errstr, sizeof(errstr), "detected mem overflow in %s%s", descr1, descr2); + LWIP_ASSERT(errstr, 0); + } + } +#endif /* MEM_SANITY_REGION_AFTER_ALIGNED > 0 */ + +#if MEM_SANITY_REGION_BEFORE_ALIGNED > 0 + m = (u8_t *)p - MEM_SANITY_REGION_BEFORE_ALIGNED; + for (k = 0; k < MEM_SANITY_REGION_BEFORE_ALIGNED; k++) { + if (m[k] != 0xcd) { + char errstr[128]; + snprintf(errstr, sizeof(errstr), "detected mem underflow in %s%s", descr1, descr2); + LWIP_ASSERT(errstr, 0); + } + } +#endif /* MEM_SANITY_REGION_BEFORE_ALIGNED > 0 */ +#else + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(desc); + LWIP_UNUSED_ARG(descr); +#endif +} + +/** + * Initialize the restricted area of a mem element. + */ +void +mem_overflow_init_raw(void *p, size_t size) +{ +#if MEM_SANITY_REGION_BEFORE_ALIGNED > 0 || MEM_SANITY_REGION_AFTER_ALIGNED > 0 + u8_t *m; +#if MEM_SANITY_REGION_BEFORE_ALIGNED > 0 + m = (u8_t *)p - MEM_SANITY_REGION_BEFORE_ALIGNED; + memset(m, 0xcd, MEM_SANITY_REGION_BEFORE_ALIGNED); +#endif +#if MEM_SANITY_REGION_AFTER_ALIGNED > 0 + m = (u8_t *)p + size; + memset(m, 0xcd, MEM_SANITY_REGION_AFTER_ALIGNED); +#endif +#else /* MEM_SANITY_REGION_BEFORE_ALIGNED > 0 || MEM_SANITY_REGION_AFTER_ALIGNED > 0 */ + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(desc); +#endif /* MEM_SANITY_REGION_BEFORE_ALIGNED > 0 || MEM_SANITY_REGION_AFTER_ALIGNED > 0 */ +} +#endif /* MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK */ + +#if MEM_LIBC_MALLOC || MEM_USE_POOLS + +/** mem_init is not used when using pools instead of a heap or using + * C library malloc(). + */ +void +mem_init(void) +{ +} + +/** mem_trim is not used when using pools instead of a heap or using + * C library malloc(): we can't free part of a pool element and the stack + * support mem_trim() to return a different pointer + */ +void * +mem_trim(void *mem, mem_size_t size) +{ + LWIP_UNUSED_ARG(size); + return mem; +} +#endif /* MEM_LIBC_MALLOC || MEM_USE_POOLS */ + +#if MEM_LIBC_MALLOC +/* lwIP heap implemented using C library malloc() */ + +/* in case C library malloc() needs extra protection, + * allow these defines to be overridden. + */ +#ifndef mem_clib_free +#define mem_clib_free free +#endif +#ifndef mem_clib_malloc +#define mem_clib_malloc malloc +#endif +#ifndef mem_clib_calloc +#define mem_clib_calloc calloc +#endif + +#if LWIP_STATS && MEM_STATS +#define MEM_LIBC_STATSHELPER_SIZE LWIP_MEM_ALIGN_SIZE(sizeof(mem_size_t)) +#else +#define MEM_LIBC_STATSHELPER_SIZE 0 +#endif + +/** + * Allocate a block of memory with a minimum of 'size' bytes. + * + * @param size is the minimum size of the requested block in bytes. + * @return pointer to allocated memory or NULL if no free memory was found. + * + * Note that the returned value must always be aligned (as defined by MEM_ALIGNMENT). + */ +void * +mem_malloc(mem_size_t size) +{ + void *ret = mem_clib_malloc(size + MEM_LIBC_STATSHELPER_SIZE); + if (ret == NULL) { + MEM_STATS_INC_LOCKED(err); + } else { + LWIP_ASSERT("malloc() must return aligned memory", LWIP_MEM_ALIGN(ret) == ret); +#if LWIP_STATS && MEM_STATS + *(mem_size_t *)ret = size; + ret = (u8_t *)ret + MEM_LIBC_STATSHELPER_SIZE; + MEM_STATS_INC_USED_LOCKED(used, size); +#endif + } + return ret; +} + +/** Put memory back on the heap + * + * @param rmem is the pointer as returned by a previous call to mem_malloc() + */ +void +mem_free(void *rmem) +{ + LWIP_ASSERT("rmem != NULL", (rmem != NULL)); + LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem))); +#if LWIP_STATS && MEM_STATS + rmem = (u8_t *)rmem - MEM_LIBC_STATSHELPER_SIZE; + MEM_STATS_DEC_USED_LOCKED(used, *(mem_size_t *)rmem); +#endif + mem_clib_free(rmem); +} + +#elif MEM_USE_POOLS + +/* lwIP heap implemented with different sized pools */ + +/** + * Allocate memory: determine the smallest pool that is big enough + * to contain an element of 'size' and get an element from that pool. + * + * @param size the size in bytes of the memory needed + * @return a pointer to the allocated memory or NULL if the pool is empty + */ +void * +mem_malloc(mem_size_t size) +{ + void *ret; + struct memp_malloc_helper *element = NULL; + memp_t poolnr; + mem_size_t required_size = size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper)); + + for (poolnr = MEMP_POOL_FIRST; poolnr <= MEMP_POOL_LAST; poolnr = (memp_t)(poolnr + 1)) { + /* is this pool big enough to hold an element of the required size + plus a struct memp_malloc_helper that saves the pool this element came from? */ + if (required_size <= memp_pools[poolnr]->size) { + element = (struct memp_malloc_helper *)memp_malloc(poolnr); + if (element == NULL) { + /* No need to DEBUGF or ASSERT: This error is already taken care of in memp.c */ +#if MEM_USE_POOLS_TRY_BIGGER_POOL + /** Try a bigger pool if this one is empty! */ + if (poolnr < MEMP_POOL_LAST) { + continue; + } +#endif /* MEM_USE_POOLS_TRY_BIGGER_POOL */ + MEM_STATS_INC_LOCKED(err); + return NULL; + } + break; + } + } + if (poolnr > MEMP_POOL_LAST) { + LWIP_ASSERT("mem_malloc(): no pool is that big!", 0); + MEM_STATS_INC_LOCKED(err); + return NULL; + } + + /* save the pool number this element came from */ + element->poolnr = poolnr; + /* and return a pointer to the memory directly after the struct memp_malloc_helper */ + ret = (u8_t *)element + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper)); + +#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) + /* truncating to u16_t is safe because struct memp_desc::size is u16_t */ + element->size = (u16_t)size; + MEM_STATS_INC_USED_LOCKED(used, element->size); +#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */ +#if MEMP_OVERFLOW_CHECK + /* initialize unused memory (diff between requested size and selected pool's size) */ + memset((u8_t *)ret + size, 0xcd, memp_pools[poolnr]->size - size); +#endif /* MEMP_OVERFLOW_CHECK */ + return ret; +} + +/** + * Free memory previously allocated by mem_malloc. Loads the pool number + * and calls memp_free with that pool number to put the element back into + * its pool + * + * @param rmem the memory element to free + */ +void +mem_free(void *rmem) +{ + struct memp_malloc_helper *hmem; + + LWIP_ASSERT("rmem != NULL", (rmem != NULL)); + LWIP_ASSERT("rmem == MEM_ALIGN(rmem)", (rmem == LWIP_MEM_ALIGN(rmem))); + + /* get the original struct memp_malloc_helper */ + /* cast through void* to get rid of alignment warnings */ + hmem = (struct memp_malloc_helper *)(void *)((u8_t *)rmem - LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))); + + LWIP_ASSERT("hmem != NULL", (hmem != NULL)); + LWIP_ASSERT("hmem == MEM_ALIGN(hmem)", (hmem == LWIP_MEM_ALIGN(hmem))); + LWIP_ASSERT("hmem->poolnr < MEMP_MAX", (hmem->poolnr < MEMP_MAX)); + + MEM_STATS_DEC_USED_LOCKED(used, hmem->size); +#if MEMP_OVERFLOW_CHECK + { + u16_t i; + LWIP_ASSERT("MEM_USE_POOLS: invalid chunk size", + hmem->size <= memp_pools[hmem->poolnr]->size); + /* check that unused memory remained untouched (diff between requested size and selected pool's size) */ + for (i = hmem->size; i < memp_pools[hmem->poolnr]->size; i++) { + u8_t data = *((u8_t *)rmem + i); + LWIP_ASSERT("MEM_USE_POOLS: mem overflow detected", data == 0xcd); + } + } +#endif /* MEMP_OVERFLOW_CHECK */ + + /* and put it in the pool we saved earlier */ + memp_free(hmem->poolnr, hmem); +} + +#else /* MEM_USE_POOLS */ +/* lwIP replacement for your libc malloc() */ + +/** + * The heap is made up as a list of structs of this type. + * This does not have to be aligned since for getting its size, + * we only use the macro SIZEOF_STRUCT_MEM, which automatically aligns. + */ +struct mem { + /** index (-> ram[next]) of the next struct */ + mem_size_t next; + /** index (-> ram[prev]) of the previous struct */ + mem_size_t prev; + /** 1: this area is used; 0: this area is unused */ + u8_t used; +#if MEM_OVERFLOW_CHECK + /** this keeps track of the user allocation size for guard checks */ + mem_size_t user_size; +#endif +}; + +/** All allocated blocks will be MIN_SIZE bytes big, at least! + * MIN_SIZE can be overridden to suit your needs. Smaller values save space, + * larger values could prevent too small blocks to fragment the RAM too much. */ +#ifndef MIN_SIZE +#define MIN_SIZE 12 +#endif /* MIN_SIZE */ +/* some alignment macros: we define them here for better source code layout */ +#define MIN_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MIN_SIZE) +#define SIZEOF_STRUCT_MEM LWIP_MEM_ALIGN_SIZE(sizeof(struct mem)) +#define MEM_SIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SIZE) + +/** If you want to relocate the heap to external memory, simply define + * LWIP_RAM_HEAP_POINTER as a void-pointer to that location. + * If so, make sure the memory at that location is big enough (see below on + * how that space is calculated). */ +#ifndef LWIP_RAM_HEAP_POINTER +/** the heap. we need one struct mem at the end and some room for alignment */ +LWIP_DECLARE_MEMORY_ALIGNED(ram_heap, MEM_SIZE_ALIGNED + (2U * SIZEOF_STRUCT_MEM)); +#define LWIP_RAM_HEAP_POINTER ram_heap +#endif /* LWIP_RAM_HEAP_POINTER */ + +/** pointer to the heap (ram_heap): for alignment, ram is now a pointer instead of an array */ +static u8_t *ram; +/** the last entry, always unused! */ +static struct mem *ram_end; + +/** concurrent access protection */ +#if !NO_SYS +static sys_mutex_t mem_mutex; +#endif + +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + +static volatile u8_t mem_free_count; + +/* Allow mem_free from other (e.g. interrupt) context */ +#define LWIP_MEM_FREE_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_free) +#define LWIP_MEM_FREE_PROTECT() SYS_ARCH_PROTECT(lev_free) +#define LWIP_MEM_FREE_UNPROTECT() SYS_ARCH_UNPROTECT(lev_free) +#define LWIP_MEM_ALLOC_DECL_PROTECT() SYS_ARCH_DECL_PROTECT(lev_alloc) +#define LWIP_MEM_ALLOC_PROTECT() SYS_ARCH_PROTECT(lev_alloc) +#define LWIP_MEM_ALLOC_UNPROTECT() SYS_ARCH_UNPROTECT(lev_alloc) +#define LWIP_MEM_LFREE_VOLATILE volatile + +#else /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + +/* Protect the heap only by using a mutex */ +#define LWIP_MEM_FREE_DECL_PROTECT() +#define LWIP_MEM_FREE_PROTECT() sys_mutex_lock(&mem_mutex) +#define LWIP_MEM_FREE_UNPROTECT() sys_mutex_unlock(&mem_mutex) +/* mem_malloc is protected using mutex AND LWIP_MEM_ALLOC_PROTECT */ +#define LWIP_MEM_ALLOC_DECL_PROTECT() +#define LWIP_MEM_ALLOC_PROTECT() +#define LWIP_MEM_ALLOC_UNPROTECT() +#define LWIP_MEM_LFREE_VOLATILE + +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + +/** pointer to the lowest free block, this is used for faster search */ +static struct mem * LWIP_MEM_LFREE_VOLATILE lfree; + +#if MEM_SANITY_CHECK +static void mem_sanity(void); +#define MEM_SANITY() mem_sanity() +#else +#define MEM_SANITY() +#endif + +#if MEM_OVERFLOW_CHECK +static void +mem_overflow_init_element(struct mem *mem, mem_size_t user_size) +{ + void *p = (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET; + mem->user_size = user_size; + mem_overflow_init_raw(p, user_size); +} + +static void +mem_overflow_check_element(struct mem *mem) +{ + void *p = (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET; + mem_overflow_check_raw(p, mem->user_size, "heap", ""); +} +#else /* MEM_OVERFLOW_CHECK */ +#define mem_overflow_init_element(mem, size) +#define mem_overflow_check_element(mem) +#endif /* MEM_OVERFLOW_CHECK */ + +static struct mem * +ptr_to_mem(mem_size_t ptr) +{ + return (struct mem *)(void *)&ram[ptr]; +} + +static mem_size_t +mem_to_ptr(void *mem) +{ + return (mem_size_t)((u8_t *)mem - ram); +} + +/** + * "Plug holes" by combining adjacent empty struct mems. + * After this function is through, there should not exist + * one empty struct mem pointing to another empty struct mem. + * + * @param mem this points to a struct mem which just has been freed + * @internal this function is only called by mem_free() and mem_trim() + * + * This assumes access to the heap is protected by the calling function + * already. + */ +static void +plug_holes(struct mem *mem) +{ + struct mem *nmem; + struct mem *pmem; + + LWIP_ASSERT("plug_holes: mem >= ram", (u8_t *)mem >= ram); + LWIP_ASSERT("plug_holes: mem < ram_end", (u8_t *)mem < (u8_t *)ram_end); + LWIP_ASSERT("plug_holes: mem->used == 0", mem->used == 0); + + /* plug hole forward */ + LWIP_ASSERT("plug_holes: mem->next <= MEM_SIZE_ALIGNED", mem->next <= MEM_SIZE_ALIGNED); + + nmem = ptr_to_mem(mem->next); + if (mem != nmem && nmem->used == 0 && (u8_t *)nmem != (u8_t *)ram_end) { + /* if mem->next is unused and not end of ram, combine mem and mem->next */ + if (lfree == nmem) { + lfree = mem; + } + mem->next = nmem->next; + if (nmem->next != MEM_SIZE_ALIGNED) { + ptr_to_mem(nmem->next)->prev = mem_to_ptr(mem); + } + } + + /* plug hole backward */ + pmem = ptr_to_mem(mem->prev); + if (pmem != mem && pmem->used == 0) { + /* if mem->prev is unused, combine mem and mem->prev */ + if (lfree == mem) { + lfree = pmem; + } + pmem->next = mem->next; + if (mem->next != MEM_SIZE_ALIGNED) { + ptr_to_mem(mem->next)->prev = mem_to_ptr(pmem); + } + } +} + +/** + * Zero the heap and initialize start, end and lowest-free + */ +void +mem_init(void) +{ + struct mem *mem; + + LWIP_ASSERT("Sanity check alignment", + (SIZEOF_STRUCT_MEM & (MEM_ALIGNMENT - 1)) == 0); + + /* align the heap */ + ram = (u8_t *)LWIP_MEM_ALIGN(LWIP_RAM_HEAP_POINTER); + /* initialize the start of the heap */ + mem = (struct mem *)(void *)ram; + mem->next = MEM_SIZE_ALIGNED; + mem->prev = 0; + mem->used = 0; + /* initialize the end of the heap */ + ram_end = ptr_to_mem(MEM_SIZE_ALIGNED); + ram_end->used = 1; + ram_end->next = MEM_SIZE_ALIGNED; + ram_end->prev = MEM_SIZE_ALIGNED; + MEM_SANITY(); + + /* initialize the lowest-free pointer to the start of the heap */ + lfree = (struct mem *)(void *)ram; + + MEM_STATS_AVAIL(avail, MEM_SIZE_ALIGNED); + + if (sys_mutex_new(&mem_mutex) != ERR_OK) { + LWIP_ASSERT("failed to create mem_mutex", 0); + } +} + +/* Check if a struct mem is correctly linked. + * If not, double-free is a possible reason. + */ +static int +mem_link_valid(struct mem *mem) +{ + struct mem *nmem, *pmem; + mem_size_t rmem_idx; + rmem_idx = mem_to_ptr(mem); + nmem = ptr_to_mem(mem->next); + pmem = ptr_to_mem(mem->prev); + if ((mem->next > MEM_SIZE_ALIGNED) || (mem->prev > MEM_SIZE_ALIGNED) || + ((mem->prev != rmem_idx) && (pmem->next != rmem_idx)) || + ((nmem != ram_end) && (nmem->prev != rmem_idx))) { + return 0; + } + return 1; +} + +#if MEM_SANITY_CHECK +static void +mem_sanity(void) +{ + struct mem *mem; + u8_t last_used; + + /* begin with first element here */ + mem = (struct mem *)ram; + LWIP_ASSERT("heap element used valid", (mem->used == 0) || (mem->used == 1)); + last_used = mem->used; + LWIP_ASSERT("heap element prev ptr valid", mem->prev == 0); + LWIP_ASSERT("heap element next ptr valid", mem->next <= MEM_SIZE_ALIGNED); + LWIP_ASSERT("heap element next ptr aligned", LWIP_MEM_ALIGN(ptr_to_mem(mem->next) == ptr_to_mem(mem->next))); + + /* check all elements before the end of the heap */ + for (mem = ptr_to_mem(mem->next); + ((u8_t *)mem > ram) && (mem < ram_end); + mem = ptr_to_mem(mem->next)) { + LWIP_ASSERT("heap element aligned", LWIP_MEM_ALIGN(mem) == mem); + LWIP_ASSERT("heap element prev ptr valid", mem->prev <= MEM_SIZE_ALIGNED); + LWIP_ASSERT("heap element next ptr valid", mem->next <= MEM_SIZE_ALIGNED); + LWIP_ASSERT("heap element prev ptr aligned", LWIP_MEM_ALIGN(ptr_to_mem(mem->prev) == ptr_to_mem(mem->prev))); + LWIP_ASSERT("heap element next ptr aligned", LWIP_MEM_ALIGN(ptr_to_mem(mem->next) == ptr_to_mem(mem->next))); + + if (last_used == 0) { + /* 2 unused elements in a row? */ + LWIP_ASSERT("heap element unused?", mem->used == 1); + } else { + LWIP_ASSERT("heap element unused member", (mem->used == 0) || (mem->used == 1)); + } + + LWIP_ASSERT("heap element link valid", mem_link_valid(mem)); + + /* used/unused altering */ + last_used = mem->used; + } + LWIP_ASSERT("heap end ptr sanity", mem == ptr_to_mem(MEM_SIZE_ALIGNED)); + LWIP_ASSERT("heap element used valid", mem->used == 1); + LWIP_ASSERT("heap element prev ptr valid", mem->prev == MEM_SIZE_ALIGNED); + LWIP_ASSERT("heap element next ptr valid", mem->next == MEM_SIZE_ALIGNED); +} +#endif /* MEM_SANITY_CHECK */ + +/** + * Put a struct mem back on the heap + * + * @param rmem is the data portion of a struct mem as returned by a previous + * call to mem_malloc() + */ +void +mem_free(void *rmem) +{ + struct mem *mem; + LWIP_MEM_FREE_DECL_PROTECT(); + + if (rmem == NULL) { + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("mem_free(p == NULL) was called.\n")); + return; + } + if ((((mem_ptr_t)rmem) & (MEM_ALIGNMENT - 1)) != 0) { + LWIP_MEM_ILLEGAL_FREE("mem_free: sanity check alignment"); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: sanity check alignment\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + } + + /* Get the corresponding struct mem: */ + /* cast through void* to get rid of alignment warnings */ + mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); + + if ((u8_t *)mem < ram || (u8_t *)rmem + MIN_SIZE_ALIGNED > (u8_t *)ram_end) { + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory"); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + } +#if MEM_OVERFLOW_CHECK + mem_overflow_check_element(mem); +#endif + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + /* mem has to be in a used state */ + if (!mem->used) { + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: double free"); + LWIP_MEM_FREE_UNPROTECT(); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: double free?\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + } + + if (!mem_link_valid(mem)) { + LWIP_MEM_ILLEGAL_FREE("mem_free: illegal memory: non-linked: double free"); + LWIP_MEM_FREE_UNPROTECT(); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_free: illegal memory: non-linked: double free?\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return; + } + + /* mem is now unused. */ + mem->used = 0; + + if (mem < lfree) { + /* the newly freed struct is now the lowest */ + lfree = mem; + } + + MEM_STATS_DEC_USED(used, mem->next - (mem_size_t)(((u8_t *)mem - ram))); + + /* finally, see if prev or next are free also */ + plug_holes(mem); + MEM_SANITY(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); +} + +/** + * Shrink memory returned by mem_malloc(). + * + * @param rmem pointer to memory allocated by mem_malloc the is to be shrinked + * @param new_size required size after shrinking (needs to be smaller than or + * equal to the previous size) + * @return for compatibility reasons: is always == rmem, at the moment + * or NULL if newsize is > old size, in which case rmem is NOT touched + * or freed! + */ +void * +mem_trim(void *rmem, mem_size_t new_size) +{ + mem_size_t size, newsize; + mem_size_t ptr, ptr2; + struct mem *mem, *mem2; + /* use the FREE_PROTECT here: it protects with sem OR SYS_ARCH_PROTECT */ + LWIP_MEM_FREE_DECL_PROTECT(); + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + newsize = (mem_size_t)LWIP_MEM_ALIGN_SIZE(new_size); + if (newsize < MIN_SIZE_ALIGNED) { + /* every data block must be at least MIN_SIZE_ALIGNED long */ + newsize = MIN_SIZE_ALIGNED; + } +#if MEM_OVERFLOW_CHECK + newsize += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; +#endif + if ((newsize > MEM_SIZE_ALIGNED) || (newsize < new_size)) { + return NULL; + } + + LWIP_ASSERT("mem_trim: legal memory", (u8_t *)rmem >= (u8_t *)ram && + (u8_t *)rmem < (u8_t *)ram_end); + + if ((u8_t *)rmem < (u8_t *)ram || (u8_t *)rmem >= (u8_t *)ram_end) { + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("mem_trim: illegal memory\n")); + /* protect mem stats from concurrent access */ + MEM_STATS_INC_LOCKED(illegal); + return rmem; + } + /* Get the corresponding struct mem ... */ + /* cast through void* to get rid of alignment warnings */ + mem = (struct mem *)(void *)((u8_t *)rmem - (SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET)); +#if MEM_OVERFLOW_CHECK + mem_overflow_check_element(mem); +#endif + /* ... and its offset pointer */ + ptr = mem_to_ptr(mem); + + size = (mem_size_t)((mem_size_t)(mem->next - ptr) - (SIZEOF_STRUCT_MEM + MEM_SANITY_OVERHEAD)); + LWIP_ASSERT("mem_trim can only shrink memory", newsize <= size); + if (newsize > size) { + /* not supported */ + return NULL; + } + if (newsize == size) { + /* No change in size, simply return */ + return rmem; + } + + /* protect the heap from concurrent access */ + LWIP_MEM_FREE_PROTECT(); + + mem2 = ptr_to_mem(mem->next); + if (mem2->used == 0) { + /* The next struct is unused, we can simply move it at little */ + mem_size_t next; + LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); + /* remember the old next pointer */ + next = mem2->next; + /* create new struct mem which is moved directly after the shrinked mem */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); + if (lfree == mem2) { + lfree = ptr_to_mem(ptr2); + } + mem2 = ptr_to_mem(ptr2); + mem2->used = 0; + /* restore the next pointer */ + mem2->next = next; + /* link it back to mem */ + mem2->prev = ptr; + /* link mem to it */ + mem->next = ptr2; + /* last thing to restore linked list: as we have moved mem2, + * let 'mem2->next->prev' point to mem2 again. but only if mem2->next is not + * the end of the heap */ + if (mem2->next != MEM_SIZE_ALIGNED) { + ptr_to_mem(mem2->next)->prev = ptr2; + } + MEM_STATS_DEC_USED(used, (size - newsize)); + /* no need to plug holes, we've already done that */ + } else if (newsize + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED <= size) { + /* Next struct is used but there's room for another struct mem with + * at least MIN_SIZE_ALIGNED of data. + * Old size ('size') must be big enough to contain at least 'newsize' plus a struct mem + * ('SIZEOF_STRUCT_MEM') with some data ('MIN_SIZE_ALIGNED'). + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + newsize); + LWIP_ASSERT("invalid next ptr", mem->next != MEM_SIZE_ALIGNED); + mem2 = ptr_to_mem(ptr2); + if (mem2 < lfree) { + lfree = mem2; + } + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + mem->next = ptr2; + if (mem2->next != MEM_SIZE_ALIGNED) { + ptr_to_mem(mem2->next)->prev = ptr2; + } + MEM_STATS_DEC_USED(used, (size - newsize)); + /* the original mem->next is used, so no need to plug holes! */ + } + /* else { + next struct mem is used but size between mem and mem2 is not big enough + to create another struct mem + -> don't do anyhting. + -> the remaining space stays unused since it is too small + } */ +#if MEM_OVERFLOW_CHECK + mem_overflow_init_element(mem, new_size); +#endif + MEM_SANITY(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 1; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_FREE_UNPROTECT(); + return rmem; +} + +/** + * Allocate a block of memory with a minimum of 'size' bytes. + * + * @param size_in is the minimum size of the requested block in bytes. + * @return pointer to allocated memory or NULL if no free memory was found. + * + * Note that the returned value will always be aligned (as defined by MEM_ALIGNMENT). + */ +void * +mem_malloc(mem_size_t size_in) +{ + mem_size_t ptr, ptr2, size; + struct mem *mem, *mem2; +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + u8_t local_mem_free_count = 0; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + LWIP_MEM_ALLOC_DECL_PROTECT(); + + if (size_in == 0) { + return NULL; + } + + /* Expand the size of the allocated memory region so that we can + adjust for alignment. */ + size = (mem_size_t)LWIP_MEM_ALIGN_SIZE(size_in); + if (size < MIN_SIZE_ALIGNED) { + /* every data block must be at least MIN_SIZE_ALIGNED long */ + size = MIN_SIZE_ALIGNED; + } +#if MEM_OVERFLOW_CHECK + size += MEM_SANITY_REGION_BEFORE_ALIGNED + MEM_SANITY_REGION_AFTER_ALIGNED; +#endif + if ((size > MEM_SIZE_ALIGNED) || (size < size_in)) { + return NULL; + } + + /* protect the heap from concurrent access */ + sys_mutex_lock(&mem_mutex); + LWIP_MEM_ALLOC_PROTECT(); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + /* run as long as a mem_free disturbed mem_malloc or mem_trim */ + do { + local_mem_free_count = 0; +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + /* Scan through the heap searching for a free block that is big enough, + * beginning with the lowest free block. + */ + for (ptr = mem_to_ptr(lfree); ptr < MEM_SIZE_ALIGNED - size; + ptr = ptr_to_mem(ptr)->next) { + mem = ptr_to_mem(ptr); +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 0; + LWIP_MEM_ALLOC_UNPROTECT(); + /* allow mem_free or mem_trim to run */ + LWIP_MEM_ALLOC_PROTECT(); + if (mem_free_count != 0) { + /* If mem_free or mem_trim have run, we have to restart since they + could have altered our current struct mem. */ + local_mem_free_count = 1; + break; + } +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + + if ((!mem->used) && + (mem->next - (ptr + SIZEOF_STRUCT_MEM)) >= size) { + /* mem is not used and at least perfect fit is possible: + * mem->next - (ptr + SIZEOF_STRUCT_MEM) gives us the 'user data size' of mem */ + + if (mem->next - (ptr + SIZEOF_STRUCT_MEM) >= (size + SIZEOF_STRUCT_MEM + MIN_SIZE_ALIGNED)) { + /* (in addition to the above, we test if another struct mem (SIZEOF_STRUCT_MEM) containing + * at least MIN_SIZE_ALIGNED of data also fits in the 'user data space' of 'mem') + * -> split large block, create empty remainder, + * remainder must be large enough to contain MIN_SIZE_ALIGNED data: if + * mem->next - (ptr + (2*SIZEOF_STRUCT_MEM)) == size, + * struct mem would fit in but no data between mem2 and mem2->next + * @todo we could leave out MIN_SIZE_ALIGNED. We would create an empty + * region that couldn't hold data, but when mem->next gets freed, + * the 2 regions would be combined, resulting in more free memory + */ + ptr2 = (mem_size_t)(ptr + SIZEOF_STRUCT_MEM + size); + LWIP_ASSERT("invalid next ptr",ptr2 != MEM_SIZE_ALIGNED); + /* create mem2 struct */ + mem2 = ptr_to_mem(ptr2); + mem2->used = 0; + mem2->next = mem->next; + mem2->prev = ptr; + /* and insert it between mem and mem->next */ + mem->next = ptr2; + mem->used = 1; + + if (mem2->next != MEM_SIZE_ALIGNED) { + ptr_to_mem(mem2->next)->prev = ptr2; + } + MEM_STATS_INC_USED(used, (size + SIZEOF_STRUCT_MEM)); + } else { + /* (a mem2 struct does no fit into the user data space of mem and mem->next will always + * be used at this point: if not we have 2 unused structs in a row, plug_holes should have + * take care of this). + * -> near fit or exact fit: do not split, no mem2 creation + * also can't move mem->next directly behind mem, since mem->next + * will always be used at this point! + */ + mem->used = 1; + MEM_STATS_INC_USED(used, mem->next - mem_to_ptr(mem)); + } +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +mem_malloc_adjust_lfree: +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + if (mem == lfree) { + struct mem *cur = lfree; + /* Find next free block after mem and update lowest free pointer */ + while (cur->used && cur != ram_end) { +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + mem_free_count = 0; + LWIP_MEM_ALLOC_UNPROTECT(); + /* prevent high interrupt latency... */ + LWIP_MEM_ALLOC_PROTECT(); + if (mem_free_count != 0) { + /* If mem_free or mem_trim have run, we have to restart since they + could have altered our current struct mem or lfree. */ + goto mem_malloc_adjust_lfree; + } +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + cur = ptr_to_mem(cur->next); + } + lfree = cur; + LWIP_ASSERT("mem_malloc: !lfree->used", ((lfree == ram_end) || (!lfree->used))); + } + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + LWIP_ASSERT("mem_malloc: allocated memory not above ram_end.", + (mem_ptr_t)mem + SIZEOF_STRUCT_MEM + size <= (mem_ptr_t)ram_end); + LWIP_ASSERT("mem_malloc: allocated memory properly aligned.", + ((mem_ptr_t)mem + SIZEOF_STRUCT_MEM) % MEM_ALIGNMENT == 0); + LWIP_ASSERT("mem_malloc: sanity check alignment", + (((mem_ptr_t)mem) & (MEM_ALIGNMENT - 1)) == 0); + +#if MEM_OVERFLOW_CHECK + mem_overflow_init_element(mem, size_in); +#endif + MEM_SANITY(); + return (u8_t *)mem + SIZEOF_STRUCT_MEM + MEM_SANITY_OFFSET; + } + } +#if LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT + /* if we got interrupted by a mem_free, try again */ + } while (local_mem_free_count != 0); +#endif /* LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT */ + MEM_STATS_INC(err); + LWIP_MEM_ALLOC_UNPROTECT(); + sys_mutex_unlock(&mem_mutex); + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_malloc: could not allocate %"S16_F" bytes\n", (s16_t)size)); + return NULL; +} + +#endif /* MEM_USE_POOLS */ + +#if MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) +void * +mem_calloc(mem_size_t count, mem_size_t size) +{ + return mem_clib_calloc(count, size); +} + +#else /* MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) */ +/** + * Contiguously allocates enough space for count objects that are size bytes + * of memory each and returns a pointer to the allocated memory. + * + * The allocated memory is filled with bytes of value zero. + * + * @param count number of objects to allocate + * @param size size of the objects to allocate + * @return pointer to allocated memory / NULL pointer if there is an error + */ +void * +mem_calloc(mem_size_t count, mem_size_t size) +{ + void *p; + size_t alloc_size = (size_t)count * (size_t)size; + + if ((size_t)(mem_size_t)alloc_size != alloc_size) { + LWIP_DEBUGF(MEM_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("mem_calloc: could not allocate %"SZT_F" bytes\n", alloc_size)); + return NULL; + } + + /* allocate 'count' objects of size 'size' */ + p = mem_malloc((mem_size_t)alloc_size); + if (p) { + /* zero the memory */ + memset(p, 0, alloc_size); + } + return p; +} +#endif /* MEM_LIBC_MALLOC && (!LWIP_STATS || !MEM_STATS) */ diff --git a/Middlewares/Third_Party/LwIP/src/core/memp.c b/Middlewares/Third_Party/LwIP/src/core/memp.c new file mode 100644 index 0000000..352ce5a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/memp.c @@ -0,0 +1,447 @@ +/** + * @file + * Dynamic pool memory manager + * + * lwIP has dedicated pools for many structures (netconn, protocol control blocks, + * packet buffers, ...). All these pools are managed here. + * + * @defgroup mempool Memory pools + * @ingroup infrastructure + * Custom memory pools + + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/stats.h" + +#include + +/* Make sure we include everything we need for size calculation required by memp_std.h */ +#include "lwip/pbuf.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" +#include "lwip/priv/tcp_priv.h" +#include "lwip/altcp.h" +#include "lwip/ip4_frag.h" +#include "lwip/netbuf.h" +#include "lwip/api.h" +#include "lwip/priv/tcpip_priv.h" +#include "lwip/priv/api_msg.h" +#include "lwip/priv/sockets_priv.h" +#include "lwip/etharp.h" +#include "lwip/igmp.h" +#include "lwip/timeouts.h" +/* needed by default MEMP_NUM_SYS_TIMEOUT */ +#include "netif/ppp/ppp_opts.h" +#include "lwip/netdb.h" +#include "lwip/dns.h" +#include "lwip/priv/nd6_priv.h" +#include "lwip/ip6_frag.h" +#include "lwip/mld6.h" + +#define LWIP_MEMPOOL(name,num,size,desc) LWIP_MEMPOOL_DECLARE(name,num,size,desc) +#include "lwip/priv/memp_std.h" + +const struct memp_desc *const memp_pools[MEMP_MAX] = { +#define LWIP_MEMPOOL(name,num,size,desc) &memp_ ## name, +#include "lwip/priv/memp_std.h" +}; + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +#if MEMP_MEM_MALLOC && MEMP_OVERFLOW_CHECK >= 2 +#undef MEMP_OVERFLOW_CHECK +/* MEMP_OVERFLOW_CHECK >= 2 does not work with MEMP_MEM_MALLOC, use 1 instead */ +#define MEMP_OVERFLOW_CHECK 1 +#endif + +#if MEMP_SANITY_CHECK && !MEMP_MEM_MALLOC +/** + * Check that memp-lists don't form a circle, using "Floyd's cycle-finding algorithm". + */ +static int +memp_sanity(const struct memp_desc *desc) +{ + struct memp *t, *h; + + t = *desc->tab; + if (t != NULL) { + for (h = t->next; (t != NULL) && (h != NULL); t = t->next, + h = ((h->next != NULL) ? h->next->next : NULL)) { + if (t == h) { + return 0; + } + } + } + + return 1; +} +#endif /* MEMP_SANITY_CHECK && !MEMP_MEM_MALLOC */ + +#if MEMP_OVERFLOW_CHECK +/** + * Check if a memp element was victim of an overflow or underflow + * (e.g. the restricted area after/before it has been altered) + * + * @param p the memp element to check + * @param desc the pool p comes from + */ +static void +memp_overflow_check_element(struct memp *p, const struct memp_desc *desc) +{ + mem_overflow_check_raw((u8_t *)p + MEMP_SIZE, desc->size, "pool ", desc->desc); +} + +/** + * Initialize the restricted area of on memp element. + */ +static void +memp_overflow_init_element(struct memp *p, const struct memp_desc *desc) +{ + mem_overflow_init_raw((u8_t *)p + MEMP_SIZE, desc->size); +} + +#if MEMP_OVERFLOW_CHECK >= 2 +/** + * Do an overflow check for all elements in every pool. + * + * @see memp_overflow_check_element for a description of the check + */ +static void +memp_overflow_check_all(void) +{ + u16_t i, j; + struct memp *p; + SYS_ARCH_DECL_PROTECT(old_level); + SYS_ARCH_PROTECT(old_level); + + for (i = 0; i < MEMP_MAX; ++i) { + p = (struct memp *)LWIP_MEM_ALIGN(memp_pools[i]->base); + for (j = 0; j < memp_pools[i]->num; ++j) { + memp_overflow_check_element(p, memp_pools[i]); + p = LWIP_ALIGNMENT_CAST(struct memp *, ((u8_t *)p + MEMP_SIZE + memp_pools[i]->size + MEM_SANITY_REGION_AFTER_ALIGNED)); + } + } + SYS_ARCH_UNPROTECT(old_level); +} +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ +#endif /* MEMP_OVERFLOW_CHECK */ + +/** + * Initialize custom memory pool. + * Related functions: memp_malloc_pool, memp_free_pool + * + * @param desc pool to initialize + */ +void +memp_init_pool(const struct memp_desc *desc) +{ +#if MEMP_MEM_MALLOC + LWIP_UNUSED_ARG(desc); +#else + int i; + struct memp *memp; + + *desc->tab = NULL; + memp = (struct memp *)LWIP_MEM_ALIGN(desc->base); +#if MEMP_MEM_INIT + /* force memset on pool memory */ + memset(memp, 0, (size_t)desc->num * (MEMP_SIZE + desc->size +#if MEMP_OVERFLOW_CHECK + + MEM_SANITY_REGION_AFTER_ALIGNED +#endif + )); +#endif + /* create a linked list of memp elements */ + for (i = 0; i < desc->num; ++i) { + memp->next = *desc->tab; + *desc->tab = memp; +#if MEMP_OVERFLOW_CHECK + memp_overflow_init_element(memp, desc); +#endif /* MEMP_OVERFLOW_CHECK */ + /* cast through void* to get rid of alignment warnings */ + memp = (struct memp *)(void *)((u8_t *)memp + MEMP_SIZE + desc->size +#if MEMP_OVERFLOW_CHECK + + MEM_SANITY_REGION_AFTER_ALIGNED +#endif + ); + } +#if MEMP_STATS + desc->stats->avail = desc->num; +#endif /* MEMP_STATS */ +#endif /* !MEMP_MEM_MALLOC */ + +#if MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) + desc->stats->name = desc->desc; +#endif /* MEMP_STATS && (defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY) */ +} + +/** + * Initializes lwIP built-in pools. + * Related functions: memp_malloc, memp_free + * + * Carves out memp_memory into linked lists for each pool-type. + */ +void +memp_init(void) +{ + u16_t i; + + /* for every pool: */ + for (i = 0; i < LWIP_ARRAYSIZE(memp_pools); i++) { + memp_init_pool(memp_pools[i]); + +#if LWIP_STATS && MEMP_STATS + lwip_stats.memp[i] = memp_pools[i]->stats; +#endif + } + +#if MEMP_OVERFLOW_CHECK >= 2 + /* check everything a first time to see if it worked */ + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ +} + +static void * +#if !MEMP_OVERFLOW_CHECK +do_memp_malloc_pool(const struct memp_desc *desc) +#else +do_memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) +#endif +{ + struct memp *memp; + SYS_ARCH_DECL_PROTECT(old_level); + +#if MEMP_MEM_MALLOC + memp = (struct memp *)mem_malloc(MEMP_SIZE + MEMP_ALIGN_SIZE(desc->size)); + SYS_ARCH_PROTECT(old_level); +#else /* MEMP_MEM_MALLOC */ + SYS_ARCH_PROTECT(old_level); + + memp = *desc->tab; +#endif /* MEMP_MEM_MALLOC */ + + if (memp != NULL) { +#if !MEMP_MEM_MALLOC +#if MEMP_OVERFLOW_CHECK == 1 + memp_overflow_check_element(memp, desc); +#endif /* MEMP_OVERFLOW_CHECK */ + + *desc->tab = memp->next; +#if MEMP_OVERFLOW_CHECK + memp->next = NULL; +#endif /* MEMP_OVERFLOW_CHECK */ +#endif /* !MEMP_MEM_MALLOC */ +#if MEMP_OVERFLOW_CHECK + memp->file = file; + memp->line = line; +#if MEMP_MEM_MALLOC + memp_overflow_init_element(memp, desc); +#endif /* MEMP_MEM_MALLOC */ +#endif /* MEMP_OVERFLOW_CHECK */ + LWIP_ASSERT("memp_malloc: memp properly aligned", + ((mem_ptr_t)memp % MEM_ALIGNMENT) == 0); +#if MEMP_STATS + desc->stats->used++; + if (desc->stats->used > desc->stats->max) { + desc->stats->max = desc->stats->used; + } +#endif + SYS_ARCH_UNPROTECT(old_level); + /* cast through u8_t* to get rid of alignment warnings */ + return ((u8_t *)memp + MEMP_SIZE); + } else { +#if MEMP_STATS + desc->stats->err++; +#endif + SYS_ARCH_UNPROTECT(old_level); + LWIP_DEBUGF(MEMP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("memp_malloc: out of memory in pool %s\n", desc->desc)); + } + + return NULL; +} + +/** + * Get an element from a custom pool. + * + * @param desc the pool to get an element from + * + * @return a pointer to the allocated memory or a NULL pointer on error + */ +void * +#if !MEMP_OVERFLOW_CHECK +memp_malloc_pool(const struct memp_desc *desc) +#else +memp_malloc_pool_fn(const struct memp_desc *desc, const char *file, const int line) +#endif +{ + LWIP_ASSERT("invalid pool desc", desc != NULL); + if (desc == NULL) { + return NULL; + } + +#if !MEMP_OVERFLOW_CHECK + return do_memp_malloc_pool(desc); +#else + return do_memp_malloc_pool_fn(desc, file, line); +#endif +} + +/** + * Get an element from a specific pool. + * + * @param type the pool to get an element from + * + * @return a pointer to the allocated memory or a NULL pointer on error + */ +void * +#if !MEMP_OVERFLOW_CHECK +memp_malloc(memp_t type) +#else +memp_malloc_fn(memp_t type, const char *file, const int line) +#endif +{ + void *memp; + LWIP_ERROR("memp_malloc: type < MEMP_MAX", (type < MEMP_MAX), return NULL;); + +#if MEMP_OVERFLOW_CHECK >= 2 + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ + +#if !MEMP_OVERFLOW_CHECK + memp = do_memp_malloc_pool(memp_pools[type]); +#else + memp = do_memp_malloc_pool_fn(memp_pools[type], file, line); +#endif + + return memp; +} + +static void +do_memp_free_pool(const struct memp_desc *desc, void *mem) +{ + struct memp *memp; + SYS_ARCH_DECL_PROTECT(old_level); + + LWIP_ASSERT("memp_free: mem properly aligned", + ((mem_ptr_t)mem % MEM_ALIGNMENT) == 0); + + /* cast through void* to get rid of alignment warnings */ + memp = (struct memp *)(void *)((u8_t *)mem - MEMP_SIZE); + + SYS_ARCH_PROTECT(old_level); + +#if MEMP_OVERFLOW_CHECK == 1 + memp_overflow_check_element(memp, desc); +#endif /* MEMP_OVERFLOW_CHECK */ + +#if MEMP_STATS + desc->stats->used--; +#endif + +#if MEMP_MEM_MALLOC + LWIP_UNUSED_ARG(desc); + SYS_ARCH_UNPROTECT(old_level); + mem_free(memp); +#else /* MEMP_MEM_MALLOC */ + memp->next = *desc->tab; + *desc->tab = memp; + +#if MEMP_SANITY_CHECK + LWIP_ASSERT("memp sanity", memp_sanity(desc)); +#endif /* MEMP_SANITY_CHECK */ + + SYS_ARCH_UNPROTECT(old_level); +#endif /* !MEMP_MEM_MALLOC */ +} + +/** + * Put a custom pool element back into its pool. + * + * @param desc the pool where to put mem + * @param mem the memp element to free + */ +void +memp_free_pool(const struct memp_desc *desc, void *mem) +{ + LWIP_ASSERT("invalid pool desc", desc != NULL); + if ((desc == NULL) || (mem == NULL)) { + return; + } + + do_memp_free_pool(desc, mem); +} + +/** + * Put an element back into its pool. + * + * @param type the pool where to put mem + * @param mem the memp element to free + */ +void +memp_free(memp_t type, void *mem) +{ +#ifdef LWIP_HOOK_MEMP_AVAILABLE + struct memp *old_first; +#endif + + LWIP_ERROR("memp_free: type < MEMP_MAX", (type < MEMP_MAX), return;); + + if (mem == NULL) { + return; + } + +#if MEMP_OVERFLOW_CHECK >= 2 + memp_overflow_check_all(); +#endif /* MEMP_OVERFLOW_CHECK >= 2 */ + +#ifdef LWIP_HOOK_MEMP_AVAILABLE + old_first = *memp_pools[type]->tab; +#endif + + do_memp_free_pool(memp_pools[type], mem); + +#ifdef LWIP_HOOK_MEMP_AVAILABLE + if (old_first == NULL) { + LWIP_HOOK_MEMP_AVAILABLE(type); + } +#endif +} diff --git a/Middlewares/Third_Party/LwIP/src/core/netif.c b/Middlewares/Third_Party/LwIP/src/core/netif.c new file mode 100644 index 0000000..15200a2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/netif.c @@ -0,0 +1,1795 @@ +/** + * @file + * lwIP network interface abstraction + * + * @defgroup netif Network interface (NETIF) + * @ingroup callbackstyle_api + * + * @defgroup netif_ip4 IPv4 address handling + * @ingroup netif + * + * @defgroup netif_ip6 IPv6 address handling + * @ingroup netif + * + * @defgroup netif_cd Client data handling + * Store data (void*) on a netif for application usage. + * @see @ref LWIP_NUM_NETIF_CLIENT_DATA + * @ingroup netif + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + */ + +#include "lwip/opt.h" + +#include /* memset */ +#include /* atoi */ + +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/ip6_addr.h" +#include "lwip/netif.h" +#include "lwip/priv/tcp_priv.h" +#include "lwip/udp.h" +#include "lwip/priv/raw_priv.h" +#include "lwip/snmp.h" +#include "lwip/igmp.h" +#include "lwip/etharp.h" +#include "lwip/stats.h" +#include "lwip/sys.h" +#include "lwip/ip.h" +#if ENABLE_LOOPBACK +#if LWIP_NETIF_LOOPBACK_MULTITHREADING +#include "lwip/tcpip.h" +#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +#include "netif/ethernet.h" + +#if LWIP_AUTOIP +#include "lwip/autoip.h" +#endif /* LWIP_AUTOIP */ +#if LWIP_DHCP +#include "lwip/dhcp.h" +#endif /* LWIP_DHCP */ +#if LWIP_IPV6_DHCP6 +#include "lwip/dhcp6.h" +#endif /* LWIP_IPV6_DHCP6 */ +#if LWIP_IPV6_MLD +#include "lwip/mld6.h" +#endif /* LWIP_IPV6_MLD */ +#if LWIP_IPV6 +#include "lwip/nd6.h" +#endif + +#if LWIP_NETIF_STATUS_CALLBACK +#define NETIF_STATUS_CALLBACK(n) do{ if (n->status_callback) { (n->status_callback)(n); }}while(0) +#else +#define NETIF_STATUS_CALLBACK(n) +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +#if LWIP_NETIF_LINK_CALLBACK +#define NETIF_LINK_CALLBACK(n) do{ if (n->link_callback) { (n->link_callback)(n); }}while(0) +#else +#define NETIF_LINK_CALLBACK(n) +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#if LWIP_NETIF_EXT_STATUS_CALLBACK +static netif_ext_callback_t *ext_callback; +#endif + +#if !LWIP_SINGLE_NETIF +struct netif *netif_list; +#endif /* !LWIP_SINGLE_NETIF */ +struct netif *netif_default; + +#define netif_index_to_num(index) ((index) - 1) +static u8_t netif_num; + +#if LWIP_NUM_NETIF_CLIENT_DATA > 0 +static u8_t netif_client_id; +#endif + +#define NETIF_REPORT_TYPE_IPV4 0x01 +#define NETIF_REPORT_TYPE_IPV6 0x02 +static void netif_issue_reports(struct netif *netif, u8_t report_type); + +#if LWIP_IPV6 +static err_t netif_null_output_ip6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr); +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 +static err_t netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr); +#endif /* LWIP_IPV4 */ + +#if LWIP_HAVE_LOOPIF +#if LWIP_IPV4 +static err_t netif_loop_output_ipv4(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr); +#endif +#if LWIP_IPV6 +static err_t netif_loop_output_ipv6(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr); +#endif + + +static struct netif loop_netif; + +/** + * Initialize a lwip network interface structure for a loopback interface + * + * @param netif the lwip network interface structure for this loopif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + */ +static err_t +netif_loopif_init(struct netif *netif) +{ + LWIP_ASSERT("netif_loopif_init: invalid netif", netif != NULL); + + /* initialize the snmp variables and counters inside the struct netif + * ifSpeed: no assumption can be made! + */ + MIB2_INIT_NETIF(netif, snmp_ifType_softwareLoopback, 0); + + netif->name[0] = 'l'; + netif->name[1] = 'o'; +#if LWIP_IPV4 + netif->output = netif_loop_output_ipv4; +#endif +#if LWIP_IPV6 + netif->output_ip6 = netif_loop_output_ipv6; +#endif +#if LWIP_LOOPIF_MULTICAST + netif_set_flags(netif, NETIF_FLAG_IGMP); +#endif + NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_DISABLE_ALL); + return ERR_OK; +} +#endif /* LWIP_HAVE_LOOPIF */ + +void +netif_init(void) +{ +#if LWIP_HAVE_LOOPIF +#if LWIP_IPV4 +#define LOOPIF_ADDRINIT &loop_ipaddr, &loop_netmask, &loop_gw, + ip4_addr_t loop_ipaddr, loop_netmask, loop_gw; + IP4_ADDR(&loop_gw, 127, 0, 0, 1); + IP4_ADDR(&loop_ipaddr, 127, 0, 0, 1); + IP4_ADDR(&loop_netmask, 255, 0, 0, 0); +#else /* LWIP_IPV4 */ +#define LOOPIF_ADDRINIT +#endif /* LWIP_IPV4 */ + +#if NO_SYS + netif_add(&loop_netif, LOOPIF_ADDRINIT NULL, netif_loopif_init, ip_input); +#else /* NO_SYS */ + netif_add(&loop_netif, LOOPIF_ADDRINIT NULL, netif_loopif_init, tcpip_input); +#endif /* NO_SYS */ + +#if LWIP_IPV6 + IP_ADDR6_HOST(loop_netif.ip6_addr, 0, 0, 0, 0x00000001UL); + loop_netif.ip6_addr_state[0] = IP6_ADDR_VALID; +#endif /* LWIP_IPV6 */ + + netif_set_link_up(&loop_netif); + netif_set_up(&loop_netif); + +#endif /* LWIP_HAVE_LOOPIF */ +} + +/** + * @ingroup lwip_nosys + * Forwards a received packet for input processing with + * ethernet_input() or ip_input() depending on netif flags. + * Don't call directly, pass to netif_add() and call + * netif->input(). + * Only works if the netif driver correctly sets + * NETIF_FLAG_ETHARP and/or NETIF_FLAG_ETHERNET flag! + */ +err_t +netif_input(struct pbuf *p, struct netif *inp) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("netif_input: invalid pbuf", p != NULL); + LWIP_ASSERT("netif_input: invalid netif", inp != NULL); + +#if LWIP_ETHERNET + if (inp->flags & (NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET)) { + return ethernet_input(p, inp); + } else +#endif /* LWIP_ETHERNET */ + return ip_input(p, inp); +} + +/** + * @ingroup netif + * Add a network interface to the list of lwIP netifs. + * + * Same as @ref netif_add but without IPv4 addresses + */ +struct netif * +netif_add_noaddr(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input) +{ + return netif_add(netif, +#if LWIP_IPV4 + NULL, NULL, NULL, +#endif /* LWIP_IPV4*/ + state, init, input); +} + +/** + * @ingroup netif + * Add a network interface to the list of lwIP netifs. + * + * @param netif a pre-allocated netif structure + * @param ipaddr IP address for the new netif + * @param netmask network mask for the new netif + * @param gw default gateway IP address for the new netif + * @param state opaque data passed to the new netif + * @param init callback function that initializes the interface + * @param input callback function that is called to pass + * ingress packets up in the protocol layer stack.\n + * It is recommended to use a function that passes the input directly + * to the stack (netif_input(), NO_SYS=1 mode) or via sending a + * message to TCPIP thread (tcpip_input(), NO_SYS=0 mode).\n + * These functions use netif flags NETIF_FLAG_ETHARP and NETIF_FLAG_ETHERNET + * to decide whether to forward to ethernet_input() or ip_input(). + * In other words, the functions only work when the netif + * driver is implemented correctly!\n + * Most members of struct netif should be be initialized by the + * netif init function = netif driver (init parameter of this function).\n + * IPv6: Don't forget to call netif_create_ip6_linklocal_address() after + * setting the MAC address in struct netif.hwaddr + * (IPv6 requires a link-local address). + * + * @return netif, or NULL if failed. + */ +struct netif * +netif_add(struct netif *netif, +#if LWIP_IPV4 + const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, +#endif /* LWIP_IPV4 */ + void *state, netif_init_fn init, netif_input_fn input) +{ +#if LWIP_IPV6 + s8_t i; +#endif + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_SINGLE_NETIF + if (netif_default != NULL) { + LWIP_ASSERT("single netif already set", 0); + return NULL; + } +#endif + + LWIP_ERROR("netif_add: invalid netif", netif != NULL, return NULL); + LWIP_ERROR("netif_add: No init function given", init != NULL, return NULL); + +#if LWIP_IPV4 + if (ipaddr == NULL) { + ipaddr = ip_2_ip4(IP4_ADDR_ANY); + } + if (netmask == NULL) { + netmask = ip_2_ip4(IP4_ADDR_ANY); + } + if (gw == NULL) { + gw = ip_2_ip4(IP4_ADDR_ANY); + } + + /* reset new interface configuration state */ + ip_addr_set_zero_ip4(&netif->ip_addr); + ip_addr_set_zero_ip4(&netif->netmask); + ip_addr_set_zero_ip4(&netif->gw); + netif->output = netif_null_output_ip4; +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + ip_addr_set_zero_ip6(&netif->ip6_addr[i]); + netif->ip6_addr_state[i] = IP6_ADDR_INVALID; +#if LWIP_IPV6_ADDRESS_LIFETIMES + netif->ip6_addr_valid_life[i] = IP6_ADDR_LIFE_STATIC; + netif->ip6_addr_pref_life[i] = IP6_ADDR_LIFE_STATIC; +#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ + } + netif->output_ip6 = netif_null_output_ip6; +#endif /* LWIP_IPV6 */ + NETIF_SET_CHECKSUM_CTRL(netif, NETIF_CHECKSUM_ENABLE_ALL); + netif->mtu = 0; + netif->flags = 0; +#ifdef netif_get_client_data + memset(netif->client_data, 0, sizeof(netif->client_data)); +#endif /* LWIP_NUM_NETIF_CLIENT_DATA */ +#if LWIP_IPV6 +#if LWIP_IPV6_AUTOCONFIG + /* IPv6 address autoconfiguration not enabled by default */ + netif->ip6_autoconfig_enabled = 0; +#endif /* LWIP_IPV6_AUTOCONFIG */ + nd6_restart_netif(netif); +#endif /* LWIP_IPV6 */ +#if LWIP_NETIF_STATUS_CALLBACK + netif->status_callback = NULL; +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + netif->link_callback = NULL; +#endif /* LWIP_NETIF_LINK_CALLBACK */ +#if LWIP_IGMP + netif->igmp_mac_filter = NULL; +#endif /* LWIP_IGMP */ +#if LWIP_IPV6 && LWIP_IPV6_MLD + netif->mld_mac_filter = NULL; +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ +#if ENABLE_LOOPBACK + netif->loop_first = NULL; + netif->loop_last = NULL; +#endif /* ENABLE_LOOPBACK */ + + /* remember netif specific state information data */ + netif->state = state; + netif->num = netif_num; + netif->input = input; + + NETIF_RESET_HINTS(netif); +#if ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS + netif->loop_cnt_current = 0; +#endif /* ENABLE_LOOPBACK && LWIP_LOOPBACK_MAX_PBUFS */ + +#if LWIP_IPV4 + netif_set_addr(netif, ipaddr, netmask, gw); +#endif /* LWIP_IPV4 */ + + /* call user specified initialization function for netif */ + if (init(netif) != ERR_OK) { + return NULL; + } +#if LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES + /* Initialize the MTU for IPv6 to the one set by the netif driver. + This can be updated later by RA. */ + netif->mtu6 = netif->mtu; +#endif /* LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES */ + +#if !LWIP_SINGLE_NETIF + /* Assign a unique netif number in the range [0..254], so that (num+1) can + serve as an interface index that fits in a u8_t. + We assume that the new netif has not yet been added to the list here. + This algorithm is O(n^2), but that should be OK for lwIP. + */ + { + struct netif *netif2; + int num_netifs; + do { + if (netif->num == 255) { + netif->num = 0; + } + num_netifs = 0; + for (netif2 = netif_list; netif2 != NULL; netif2 = netif2->next) { + LWIP_ASSERT("netif already added", netif2 != netif); + num_netifs++; + LWIP_ASSERT("too many netifs, max. supported number is 255", num_netifs <= 255); + if (netif2->num == netif->num) { + netif->num++; + break; + } + } + } while (netif2 != NULL); + } + if (netif->num == 254) { + netif_num = 0; + } else { + netif_num = (u8_t)(netif->num + 1); + } + + /* add this netif to the list */ + netif->next = netif_list; + netif_list = netif; +#endif /* "LWIP_SINGLE_NETIF */ + mib2_netif_added(netif); + +#if LWIP_IGMP + /* start IGMP processing */ + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_start(netif); + } +#endif /* LWIP_IGMP */ + + LWIP_DEBUGF(NETIF_DEBUG, ("netif: added interface %c%c IP", + netif->name[0], netif->name[1])); +#if LWIP_IPV4 + LWIP_DEBUGF(NETIF_DEBUG, (" addr ")); + ip4_addr_debug_print(NETIF_DEBUG, ipaddr); + LWIP_DEBUGF(NETIF_DEBUG, (" netmask ")); + ip4_addr_debug_print(NETIF_DEBUG, netmask); + LWIP_DEBUGF(NETIF_DEBUG, (" gw ")); + ip4_addr_debug_print(NETIF_DEBUG, gw); +#endif /* LWIP_IPV4 */ + LWIP_DEBUGF(NETIF_DEBUG, ("\n")); + + netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_ADDED, NULL); + + return netif; +} + +static void +netif_do_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ +#if LWIP_TCP + tcp_netif_ip_addr_changed(old_addr, new_addr); +#endif /* LWIP_TCP */ +#if LWIP_UDP + udp_netif_ip_addr_changed(old_addr, new_addr); +#endif /* LWIP_UDP */ +#if LWIP_RAW + raw_netif_ip_addr_changed(old_addr, new_addr); +#endif /* LWIP_RAW */ +} + +#if LWIP_IPV4 +static int +netif_do_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr, ip_addr_t *old_addr) +{ + LWIP_ASSERT("invalid pointer", ipaddr != NULL); + LWIP_ASSERT("invalid pointer", old_addr != NULL); + + /* address is actually being changed? */ + if (ip4_addr_cmp(ipaddr, netif_ip4_addr(netif)) == 0) { + ip_addr_t new_addr; + *ip_2_ip4(&new_addr) = *ipaddr; + IP_SET_TYPE_VAL(new_addr, IPADDR_TYPE_V4); + + ip_addr_copy(*old_addr, *netif_ip_addr4(netif)); + + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: netif address being changed\n")); + netif_do_ip_addr_changed(old_addr, &new_addr); + + mib2_remove_ip4(netif); + mib2_remove_route_ip4(0, netif); + /* set new IP address to netif */ + ip4_addr_set(ip_2_ip4(&netif->ip_addr), ipaddr); + IP_SET_TYPE_VAL(netif->ip_addr, IPADDR_TYPE_V4); + mib2_add_ip4(netif); + mib2_add_route_ip4(0, netif); + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4); + + NETIF_STATUS_CALLBACK(netif); + return 1; /* address changed */ + } + return 0; /* address unchanged */ +} + +/** + * @ingroup netif_ip4 + * Change the IP address of a network interface + * + * @param netif the network interface to change + * @param ipaddr the new IP address + * + * @note call netif_set_addr() if you also want to change netmask and + * default gateway + */ +void +netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr) +{ + ip_addr_t old_addr; + + LWIP_ERROR("netif_set_ipaddr: invalid netif", netif != NULL, return); + + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (ipaddr == NULL) { + ipaddr = IP4_ADDR_ANY4; + } + + LWIP_ASSERT_CORE_LOCKED(); + + if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + netif_ext_callback_args_t args; + args.ipv4_changed.old_address = &old_addr; + netif_invoke_ext_callback(netif, LWIP_NSC_IPV4_ADDRESS_CHANGED, &args); +#endif + } +} + +static int +netif_do_set_netmask(struct netif *netif, const ip4_addr_t *netmask, ip_addr_t *old_nm) +{ + /* address is actually being changed? */ + if (ip4_addr_cmp(netmask, netif_ip4_netmask(netif)) == 0) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + LWIP_ASSERT("invalid pointer", old_nm != NULL); + ip_addr_copy(*old_nm, *netif_ip_netmask4(netif)); +#else + LWIP_UNUSED_ARG(old_nm); +#endif + mib2_remove_route_ip4(0, netif); + /* set new netmask to netif */ + ip4_addr_set(ip_2_ip4(&netif->netmask), netmask); + IP_SET_TYPE_VAL(netif->netmask, IPADDR_TYPE_V4); + mib2_add_route_ip4(0, netif); + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: netmask of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1_16(netif_ip4_netmask(netif)), + ip4_addr2_16(netif_ip4_netmask(netif)), + ip4_addr3_16(netif_ip4_netmask(netif)), + ip4_addr4_16(netif_ip4_netmask(netif)))); + return 1; /* netmask changed */ + } + return 0; /* netmask unchanged */ +} + +/** + * @ingroup netif_ip4 + * Change the netmask of a network interface + * + * @param netif the network interface to change + * @param netmask the new netmask + * + * @note call netif_set_addr() if you also want to change ip address and + * default gateway + */ +void +netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask) +{ +#if LWIP_NETIF_EXT_STATUS_CALLBACK + ip_addr_t old_nm_val; + ip_addr_t *old_nm = &old_nm_val; +#else + ip_addr_t *old_nm = NULL; +#endif + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_netmask: invalid netif", netif != NULL, return); + + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (netmask == NULL) { + netmask = IP4_ADDR_ANY4; + } + + if (netif_do_set_netmask(netif, netmask, old_nm)) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + netif_ext_callback_args_t args; + args.ipv4_changed.old_netmask = old_nm; + netif_invoke_ext_callback(netif, LWIP_NSC_IPV4_NETMASK_CHANGED, &args); +#endif + } +} + +static int +netif_do_set_gw(struct netif *netif, const ip4_addr_t *gw, ip_addr_t *old_gw) +{ + /* address is actually being changed? */ + if (ip4_addr_cmp(gw, netif_ip4_gw(netif)) == 0) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + LWIP_ASSERT("invalid pointer", old_gw != NULL); + ip_addr_copy(*old_gw, *netif_ip_gw4(netif)); +#else + LWIP_UNUSED_ARG(old_gw); +#endif + + ip4_addr_set(ip_2_ip4(&netif->gw), gw); + IP_SET_TYPE_VAL(netif->gw, IPADDR_TYPE_V4); + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: GW address of interface %c%c set to %"U16_F".%"U16_F".%"U16_F".%"U16_F"\n", + netif->name[0], netif->name[1], + ip4_addr1_16(netif_ip4_gw(netif)), + ip4_addr2_16(netif_ip4_gw(netif)), + ip4_addr3_16(netif_ip4_gw(netif)), + ip4_addr4_16(netif_ip4_gw(netif)))); + return 1; /* gateway changed */ + } + return 0; /* gateway unchanged */ +} + +/** + * @ingroup netif_ip4 + * Change the default gateway for a network interface + * + * @param netif the network interface to change + * @param gw the new default gateway + * + * @note call netif_set_addr() if you also want to change ip address and netmask + */ +void +netif_set_gw(struct netif *netif, const ip4_addr_t *gw) +{ +#if LWIP_NETIF_EXT_STATUS_CALLBACK + ip_addr_t old_gw_val; + ip_addr_t *old_gw = &old_gw_val; +#else + ip_addr_t *old_gw = NULL; +#endif + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_gw: invalid netif", netif != NULL, return); + + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (gw == NULL) { + gw = IP4_ADDR_ANY4; + } + + if (netif_do_set_gw(netif, gw, old_gw)) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + netif_ext_callback_args_t args; + args.ipv4_changed.old_gw = old_gw; + netif_invoke_ext_callback(netif, LWIP_NSC_IPV4_GATEWAY_CHANGED, &args); +#endif + } +} + +/** + * @ingroup netif_ip4 + * Change IP address configuration for a network interface (including netmask + * and default gateway). + * + * @param netif the network interface to change + * @param ipaddr the new IP address + * @param netmask the new netmask + * @param gw the new default gateway + */ +void +netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, + const ip4_addr_t *gw) +{ +#if LWIP_NETIF_EXT_STATUS_CALLBACK + netif_nsc_reason_t change_reason = LWIP_NSC_NONE; + netif_ext_callback_args_t cb_args; + ip_addr_t old_nm_val; + ip_addr_t old_gw_val; + ip_addr_t *old_nm = &old_nm_val; + ip_addr_t *old_gw = &old_gw_val; +#else + ip_addr_t *old_nm = NULL; + ip_addr_t *old_gw = NULL; +#endif + ip_addr_t old_addr; + int remove; + + LWIP_ASSERT_CORE_LOCKED(); + + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (ipaddr == NULL) { + ipaddr = IP4_ADDR_ANY4; + } + if (netmask == NULL) { + netmask = IP4_ADDR_ANY4; + } + if (gw == NULL) { + gw = IP4_ADDR_ANY4; + } + + remove = ip4_addr_isany(ipaddr); + if (remove) { + /* when removing an address, we have to remove it *before* changing netmask/gw + to ensure that tcp RST segment can be sent correctly */ + if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED; + cb_args.ipv4_changed.old_address = &old_addr; +#endif + } + } + if (netif_do_set_netmask(netif, netmask, old_nm)) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_NETMASK_CHANGED; + cb_args.ipv4_changed.old_netmask = old_nm; +#endif + } + if (netif_do_set_gw(netif, gw, old_gw)) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_GATEWAY_CHANGED; + cb_args.ipv4_changed.old_gw = old_gw; +#endif + } + if (!remove) { + /* set ipaddr last to ensure netmask/gw have been set when status callback is called */ + if (netif_do_set_ipaddr(netif, ipaddr, &old_addr)) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + change_reason |= LWIP_NSC_IPV4_ADDRESS_CHANGED; + cb_args.ipv4_changed.old_address = &old_addr; +#endif + } + } + +#if LWIP_NETIF_EXT_STATUS_CALLBACK + if (change_reason != LWIP_NSC_NONE) { + change_reason |= LWIP_NSC_IPV4_SETTINGS_CHANGED; + netif_invoke_ext_callback(netif, change_reason, &cb_args); + } +#endif +} +#endif /* LWIP_IPV4*/ + +/** + * @ingroup netif + * Remove a network interface from the list of lwIP netifs. + * + * @param netif the network interface to remove + */ +void +netif_remove(struct netif *netif) +{ +#if LWIP_IPV6 + int i; +#endif + + LWIP_ASSERT_CORE_LOCKED(); + + if (netif == NULL) { + return; + } + + netif_invoke_ext_callback(netif, LWIP_NSC_NETIF_REMOVED, NULL); + +#if LWIP_IPV4 + if (!ip4_addr_isany_val(*netif_ip4_addr(netif))) { + netif_do_ip_addr_changed(netif_ip_addr4(netif), NULL); + } + +#if LWIP_IGMP + /* stop IGMP processing */ + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_stop(netif); + } +#endif /* LWIP_IGMP */ +#endif /* LWIP_IPV4*/ + +#if LWIP_IPV6 + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, i))) { + netif_do_ip_addr_changed(netif_ip_addr6(netif, i), NULL); + } + } +#if LWIP_IPV6_MLD + /* stop MLD processing */ + mld6_stop(netif); +#endif /* LWIP_IPV6_MLD */ +#endif /* LWIP_IPV6 */ + if (netif_is_up(netif)) { + /* set netif down before removing (call callback function) */ + netif_set_down(netif); + } + + mib2_remove_ip4(netif); + + /* this netif is default? */ + if (netif_default == netif) { + /* reset default netif */ + netif_set_default(NULL); + } +#if !LWIP_SINGLE_NETIF + /* is it the first netif? */ + if (netif_list == netif) { + netif_list = netif->next; + } else { + /* look for netif further down the list */ + struct netif *tmp_netif; + NETIF_FOREACH(tmp_netif) { + if (tmp_netif->next == netif) { + tmp_netif->next = netif->next; + break; + } + } + if (tmp_netif == NULL) { + return; /* netif is not on the list */ + } + } +#endif /* !LWIP_SINGLE_NETIF */ + mib2_netif_removed(netif); +#if LWIP_NETIF_REMOVE_CALLBACK + if (netif->remove_callback) { + netif->remove_callback(netif); + } +#endif /* LWIP_NETIF_REMOVE_CALLBACK */ + LWIP_DEBUGF( NETIF_DEBUG, ("netif_remove: removed netif\n") ); +} + +/** + * @ingroup netif + * Set a network interface as the default network interface + * (used to output all packets for which no specific route is found) + * + * @param netif the default network interface + */ +void +netif_set_default(struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + + if (netif == NULL) { + /* remove default route */ + mib2_remove_route_ip4(1, netif); + } else { + /* install default route */ + mib2_add_route_ip4(1, netif); + } + netif_default = netif; + LWIP_DEBUGF(NETIF_DEBUG, ("netif: setting default interface %c%c\n", + netif ? netif->name[0] : '\'', netif ? netif->name[1] : '\'')); +} + +/** + * @ingroup netif + * Bring an interface up, available for processing + * traffic. + */ +void +netif_set_up(struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_up: invalid netif", netif != NULL, return); + + if (!(netif->flags & NETIF_FLAG_UP)) { + netif_set_flags(netif, NETIF_FLAG_UP); + + MIB2_COPY_SYSUPTIME_TO(&netif->ts); + + NETIF_STATUS_CALLBACK(netif); + +#if LWIP_NETIF_EXT_STATUS_CALLBACK + { + netif_ext_callback_args_t args; + args.status_changed.state = 1; + netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); + } +#endif + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); +#if LWIP_IPV6 + nd6_restart_netif(netif); +#endif /* LWIP_IPV6 */ + } +} + +/** Send ARP/IGMP/MLD/RS events, e.g. on link-up/netif-up or addr-change + */ +static void +netif_issue_reports(struct netif *netif, u8_t report_type) +{ + LWIP_ASSERT("netif_issue_reports: invalid netif", netif != NULL); + + /* Only send reports when both link and admin states are up */ + if (!(netif->flags & NETIF_FLAG_LINK_UP) || + !(netif->flags & NETIF_FLAG_UP)) { + return; + } + +#if LWIP_IPV4 + if ((report_type & NETIF_REPORT_TYPE_IPV4) && + !ip4_addr_isany_val(*netif_ip4_addr(netif))) { +#if LWIP_ARP + /* For Ethernet network interfaces, we would like to send a "gratuitous ARP" */ + if (netif->flags & (NETIF_FLAG_ETHARP)) { + etharp_gratuitous(netif); + } +#endif /* LWIP_ARP */ + +#if LWIP_IGMP + /* resend IGMP memberships */ + if (netif->flags & NETIF_FLAG_IGMP) { + igmp_report_groups(netif); + } +#endif /* LWIP_IGMP */ + } +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 + if (report_type & NETIF_REPORT_TYPE_IPV6) { +#if LWIP_IPV6_MLD + /* send mld memberships */ + mld6_report_groups(netif); +#endif /* LWIP_IPV6_MLD */ + } +#endif /* LWIP_IPV6 */ +} + +/** + * @ingroup netif + * Bring an interface down, disabling any traffic processing. + */ +void +netif_set_down(struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_down: invalid netif", netif != NULL, return); + + if (netif->flags & NETIF_FLAG_UP) { +#if LWIP_NETIF_EXT_STATUS_CALLBACK + { + netif_ext_callback_args_t args; + args.status_changed.state = 0; + netif_invoke_ext_callback(netif, LWIP_NSC_STATUS_CHANGED, &args); + } +#endif + + netif_clear_flags(netif, NETIF_FLAG_UP); + MIB2_COPY_SYSUPTIME_TO(&netif->ts); + +#if LWIP_IPV4 && LWIP_ARP + if (netif->flags & NETIF_FLAG_ETHARP) { + etharp_cleanup_netif(netif); + } +#endif /* LWIP_IPV4 && LWIP_ARP */ + +#if LWIP_IPV6 + nd6_cleanup_netif(netif); +#endif /* LWIP_IPV6 */ + + NETIF_STATUS_CALLBACK(netif); + } +} + +#if LWIP_NETIF_STATUS_CALLBACK +/** + * @ingroup netif + * Set callback to be called when interface is brought up/down or address is changed while up + */ +void +netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback) +{ + LWIP_ASSERT_CORE_LOCKED(); + + if (netif) { + netif->status_callback = status_callback; + } +} +#endif /* LWIP_NETIF_STATUS_CALLBACK */ + +#if LWIP_NETIF_REMOVE_CALLBACK +/** + * @ingroup netif + * Set callback to be called when the interface has been removed + */ +void +netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback) +{ + LWIP_ASSERT_CORE_LOCKED(); + + if (netif) { + netif->remove_callback = remove_callback; + } +} +#endif /* LWIP_NETIF_REMOVE_CALLBACK */ + +/** + * @ingroup netif + * Called by a driver when its link goes up + */ +void +netif_set_link_up(struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_link_up: invalid netif", netif != NULL, return); + + if (!(netif->flags & NETIF_FLAG_LINK_UP)) { + netif_set_flags(netif, NETIF_FLAG_LINK_UP); + +#if LWIP_DHCP + dhcp_network_changed(netif); +#endif /* LWIP_DHCP */ + +#if LWIP_AUTOIP + autoip_network_changed(netif); +#endif /* LWIP_AUTOIP */ + + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV4 | NETIF_REPORT_TYPE_IPV6); +#if LWIP_IPV6 + nd6_restart_netif(netif); +#endif /* LWIP_IPV6 */ + + NETIF_LINK_CALLBACK(netif); +#if LWIP_NETIF_EXT_STATUS_CALLBACK + { + netif_ext_callback_args_t args; + args.link_changed.state = 1; + netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); + } +#endif + } +} + +/** + * @ingroup netif + * Called by a driver when its link goes down + */ +void +netif_set_link_down(struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("netif_set_link_down: invalid netif", netif != NULL, return); + + if (netif->flags & NETIF_FLAG_LINK_UP) { + netif_clear_flags(netif, NETIF_FLAG_LINK_UP); + NETIF_LINK_CALLBACK(netif); +#if LWIP_NETIF_EXT_STATUS_CALLBACK + { + netif_ext_callback_args_t args; + args.link_changed.state = 0; + netif_invoke_ext_callback(netif, LWIP_NSC_LINK_CHANGED, &args); + } +#endif + } +} + +#if LWIP_NETIF_LINK_CALLBACK +/** + * @ingroup netif + * Set callback to be called when link is brought up/down + */ +void +netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback) +{ + LWIP_ASSERT_CORE_LOCKED(); + + if (netif) { + netif->link_callback = link_callback; + } +} +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#if ENABLE_LOOPBACK +/** + * @ingroup netif + * Send an IP packet to be received on the same netif (loopif-like). + * The pbuf is simply copied and handed back to netif->input. + * In multithreaded mode, this is done directly since netif->input must put + * the packet on a queue. + * In callback mode, the packet is put on an internal queue and is fed to + * netif->input by netif_poll(). + * + * @param netif the lwip network interface structure + * @param p the (IP) packet to 'send' + * @return ERR_OK if the packet has been sent + * ERR_MEM if the pbuf used to copy the packet couldn't be allocated + */ +err_t +netif_loop_output(struct netif *netif, struct pbuf *p) +{ + struct pbuf *r; + err_t err; + struct pbuf *last; +#if LWIP_LOOPBACK_MAX_PBUFS + u16_t clen = 0; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + /* If we have a loopif, SNMP counters are adjusted for it, + * if not they are adjusted for 'netif'. */ +#if MIB2_STATS +#if LWIP_HAVE_LOOPIF + struct netif *stats_if = &loop_netif; +#else /* LWIP_HAVE_LOOPIF */ + struct netif *stats_if = netif; +#endif /* LWIP_HAVE_LOOPIF */ +#endif /* MIB2_STATS */ +#if LWIP_NETIF_LOOPBACK_MULTITHREADING + u8_t schedule_poll = 0; +#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_ASSERT("netif_loop_output: invalid netif", netif != NULL); + LWIP_ASSERT("netif_loop_output: invalid pbuf", p != NULL); + + /* Allocate a new pbuf */ + r = pbuf_alloc(PBUF_LINK, p->tot_len, PBUF_RAM); + if (r == NULL) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards); + return ERR_MEM; + } +#if LWIP_LOOPBACK_MAX_PBUFS + clen = pbuf_clen(r); + /* check for overflow or too many pbuf on queue */ + if (((netif->loop_cnt_current + clen) < netif->loop_cnt_current) || + ((netif->loop_cnt_current + clen) > LWIP_MIN(LWIP_LOOPBACK_MAX_PBUFS, 0xFFFF))) { + pbuf_free(r); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards); + return ERR_MEM; + } + netif->loop_cnt_current = (u16_t)(netif->loop_cnt_current + clen); +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + + /* Copy the whole pbuf queue p into the single pbuf r */ + if ((err = pbuf_copy(r, p)) != ERR_OK) { + pbuf_free(r); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(stats_if, ifoutdiscards); + return err; + } + + /* Put the packet on a linked list which gets emptied through calling + netif_poll(). */ + + /* let last point to the last pbuf in chain r */ + for (last = r; last->next != NULL; last = last->next) { + /* nothing to do here, just get to the last pbuf */ + } + + SYS_ARCH_PROTECT(lev); + if (netif->loop_first != NULL) { + LWIP_ASSERT("if first != NULL, last must also be != NULL", netif->loop_last != NULL); + netif->loop_last->next = r; + netif->loop_last = last; + } else { + netif->loop_first = r; + netif->loop_last = last; +#if LWIP_NETIF_LOOPBACK_MULTITHREADING + /* No existing packets queued, schedule poll */ + schedule_poll = 1; +#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ + } + SYS_ARCH_UNPROTECT(lev); + + LINK_STATS_INC(link.xmit); + MIB2_STATS_NETIF_ADD(stats_if, ifoutoctets, p->tot_len); + MIB2_STATS_NETIF_INC(stats_if, ifoutucastpkts); + +#if LWIP_NETIF_LOOPBACK_MULTITHREADING + /* For multithreading environment, schedule a call to netif_poll */ + if (schedule_poll) { + tcpip_try_callback((tcpip_callback_fn)netif_poll, netif); + } +#endif /* LWIP_NETIF_LOOPBACK_MULTITHREADING */ + + return ERR_OK; +} + +#if LWIP_HAVE_LOOPIF +#if LWIP_IPV4 +static err_t +netif_loop_output_ipv4(struct netif *netif, struct pbuf *p, const ip4_addr_t *addr) +{ + LWIP_UNUSED_ARG(addr); + return netif_loop_output(netif, p); +} +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +static err_t +netif_loop_output_ipv6(struct netif *netif, struct pbuf *p, const ip6_addr_t *addr) +{ + LWIP_UNUSED_ARG(addr); + return netif_loop_output(netif, p); +} +#endif /* LWIP_IPV6 */ +#endif /* LWIP_HAVE_LOOPIF */ + + +/** + * Call netif_poll() in the main loop of your application. This is to prevent + * reentering non-reentrant functions like tcp_input(). Packets passed to + * netif_loop_output() are put on a list that is passed to netif->input() by + * netif_poll(). + */ +void +netif_poll(struct netif *netif) +{ + /* If we have a loopif, SNMP counters are adjusted for it, + * if not they are adjusted for 'netif'. */ +#if MIB2_STATS +#if LWIP_HAVE_LOOPIF + struct netif *stats_if = &loop_netif; +#else /* LWIP_HAVE_LOOPIF */ + struct netif *stats_if = netif; +#endif /* LWIP_HAVE_LOOPIF */ +#endif /* MIB2_STATS */ + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_ASSERT("netif_poll: invalid netif", netif != NULL); + + /* Get a packet from the list. With SYS_LIGHTWEIGHT_PROT=1, this is protected */ + SYS_ARCH_PROTECT(lev); + while (netif->loop_first != NULL) { + struct pbuf *in, *in_end; +#if LWIP_LOOPBACK_MAX_PBUFS + u8_t clen = 1; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + + in = in_end = netif->loop_first; + while (in_end->len != in_end->tot_len) { + LWIP_ASSERT("bogus pbuf: len != tot_len but next == NULL!", in_end->next != NULL); + in_end = in_end->next; +#if LWIP_LOOPBACK_MAX_PBUFS + clen++; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + } +#if LWIP_LOOPBACK_MAX_PBUFS + /* adjust the number of pbufs on queue */ + LWIP_ASSERT("netif->loop_cnt_current underflow", + ((netif->loop_cnt_current - clen) < netif->loop_cnt_current)); + netif->loop_cnt_current = (u16_t)(netif->loop_cnt_current - clen); +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ + + /* 'in_end' now points to the last pbuf from 'in' */ + if (in_end == netif->loop_last) { + /* this was the last pbuf in the list */ + netif->loop_first = netif->loop_last = NULL; + } else { + /* pop the pbuf off the list */ + netif->loop_first = in_end->next; + LWIP_ASSERT("should not be null since first != last!", netif->loop_first != NULL); + } + /* De-queue the pbuf from its successors on the 'loop_' list. */ + in_end->next = NULL; + SYS_ARCH_UNPROTECT(lev); + + in->if_idx = netif_get_index(netif); + + LINK_STATS_INC(link.recv); + MIB2_STATS_NETIF_ADD(stats_if, ifinoctets, in->tot_len); + MIB2_STATS_NETIF_INC(stats_if, ifinucastpkts); + /* loopback packets are always IP packets! */ + if (ip_input(in, netif) != ERR_OK) { + pbuf_free(in); + } + SYS_ARCH_PROTECT(lev); + } + SYS_ARCH_UNPROTECT(lev); +} + +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +/** + * Calls netif_poll() for every netif on the netif_list. + */ +void +netif_poll_all(void) +{ + struct netif *netif; + /* loop through netifs */ + NETIF_FOREACH(netif) { + netif_poll(netif); + } +} +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +#if LWIP_NUM_NETIF_CLIENT_DATA > 0 +/** + * @ingroup netif_cd + * Allocate an index to store data in client_data member of struct netif. + * Returned value is an index in mentioned array. + * @see LWIP_NUM_NETIF_CLIENT_DATA + */ +u8_t +netif_alloc_client_data_id(void) +{ + u8_t result = netif_client_id; + netif_client_id++; + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_NUM_NETIF_CLIENT_DATA > 256 +#error LWIP_NUM_NETIF_CLIENT_DATA must be <= 256 +#endif + LWIP_ASSERT("Increase LWIP_NUM_NETIF_CLIENT_DATA in lwipopts.h", result < LWIP_NUM_NETIF_CLIENT_DATA); + return (u8_t)(result + LWIP_NETIF_CLIENT_DATA_INDEX_MAX); +} +#endif + +#if LWIP_IPV6 +/** + * @ingroup netif_ip6 + * Change an IPv6 address of a network interface + * + * @param netif the network interface to change + * @param addr_idx index of the IPv6 address + * @param addr6 the new IPv6 address + * + * @note call netif_ip6_addr_set_state() to set the address valid/temptative + */ +void +netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("netif_ip6_addr_set: invalid netif", netif != NULL); + LWIP_ASSERT("netif_ip6_addr_set: invalid addr6", addr6 != NULL); + + netif_ip6_addr_set_parts(netif, addr_idx, addr6->addr[0], addr6->addr[1], + addr6->addr[2], addr6->addr[3]); +} + +/* + * Change an IPv6 address of a network interface (internal version taking 4 * u32_t) + * + * @param netif the network interface to change + * @param addr_idx index of the IPv6 address + * @param i0 word0 of the new IPv6 address + * @param i1 word1 of the new IPv6 address + * @param i2 word2 of the new IPv6 address + * @param i3 word3 of the new IPv6 address + */ +void +netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3) +{ + ip_addr_t old_addr; + ip_addr_t new_ipaddr; + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("invalid index", addr_idx < LWIP_IPV6_NUM_ADDRESSES); + + ip6_addr_copy(*ip_2_ip6(&old_addr), *netif_ip6_addr(netif, addr_idx)); + IP_SET_TYPE_VAL(old_addr, IPADDR_TYPE_V6); + + /* address is actually being changed? */ + if ((ip_2_ip6(&old_addr)->addr[0] != i0) || (ip_2_ip6(&old_addr)->addr[1] != i1) || + (ip_2_ip6(&old_addr)->addr[2] != i2) || (ip_2_ip6(&old_addr)->addr[3] != i3)) { + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_ip6_addr_set: netif address being changed\n")); + + IP_ADDR6(&new_ipaddr, i0, i1, i2, i3); + ip6_addr_assign_zone(ip_2_ip6(&new_ipaddr), IP6_UNICAST, netif); + + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, addr_idx))) { + netif_do_ip_addr_changed(netif_ip_addr6(netif, addr_idx), &new_ipaddr); + } + /* @todo: remove/readd mib2 ip6 entries? */ + + ip_addr_copy(netif->ip6_addr[addr_idx], new_ipaddr); + + if (ip6_addr_isvalid(netif_ip6_addr_state(netif, addr_idx))) { + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV6); + NETIF_STATUS_CALLBACK(netif); + } + +#if LWIP_NETIF_EXT_STATUS_CALLBACK + { + netif_ext_callback_args_t args; + args.ipv6_set.addr_index = addr_idx; + args.ipv6_set.old_address = &old_addr; + netif_invoke_ext_callback(netif, LWIP_NSC_IPV6_SET, &args); + } +#endif + } + + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IPv6 address %d of interface %c%c set to %s/0x%"X8_F"\n", + addr_idx, netif->name[0], netif->name[1], ip6addr_ntoa(netif_ip6_addr(netif, addr_idx)), + netif_ip6_addr_state(netif, addr_idx))); +} + +/** + * @ingroup netif_ip6 + * Change the state of an IPv6 address of a network interface + * (INVALID, TEMPTATIVE, PREFERRED, DEPRECATED, where TEMPTATIVE + * includes the number of checks done, see ip6_addr.h) + * + * @param netif the network interface to change + * @param addr_idx index of the IPv6 address + * @param state the new IPv6 address state + */ +void +netif_ip6_addr_set_state(struct netif *netif, s8_t addr_idx, u8_t state) +{ + u8_t old_state; + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("invalid index", addr_idx < LWIP_IPV6_NUM_ADDRESSES); + + old_state = netif_ip6_addr_state(netif, addr_idx); + /* state is actually being changed? */ + if (old_state != state) { + u8_t old_valid = old_state & IP6_ADDR_VALID; + u8_t new_valid = state & IP6_ADDR_VALID; + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_ip6_addr_set_state: netif address state being changed\n")); + +#if LWIP_IPV6_MLD + /* Reevaluate solicited-node multicast group membership. */ + if (netif->flags & NETIF_FLAG_MLD6) { + nd6_adjust_mld_membership(netif, addr_idx, state); + } +#endif /* LWIP_IPV6_MLD */ + + if (old_valid && !new_valid) { + /* address about to be removed by setting invalid */ + netif_do_ip_addr_changed(netif_ip_addr6(netif, addr_idx), NULL); + /* @todo: remove mib2 ip6 entries? */ + } + netif->ip6_addr_state[addr_idx] = state; + + if (!old_valid && new_valid) { + /* address added by setting valid */ + /* This is a good moment to check that the address is properly zoned. */ + IP6_ADDR_ZONECHECK_NETIF(netif_ip6_addr(netif, addr_idx), netif); + /* @todo: add mib2 ip6 entries? */ + netif_issue_reports(netif, NETIF_REPORT_TYPE_IPV6); + } + if ((old_state & ~IP6_ADDR_TENTATIVE_COUNT_MASK) != + (state & ~IP6_ADDR_TENTATIVE_COUNT_MASK)) { + /* address state has changed -> call the callback function */ + NETIF_STATUS_CALLBACK(netif); + } + +#if LWIP_NETIF_EXT_STATUS_CALLBACK + { + netif_ext_callback_args_t args; + args.ipv6_addr_state_changed.addr_index = addr_idx; + args.ipv6_addr_state_changed.old_state = old_state; + args.ipv6_addr_state_changed.address = netif_ip_addr6(netif, addr_idx); + netif_invoke_ext_callback(netif, LWIP_NSC_IPV6_ADDR_STATE_CHANGED, &args); + } +#endif + } + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("netif: IPv6 address %d of interface %c%c set to %s/0x%"X8_F"\n", + addr_idx, netif->name[0], netif->name[1], ip6addr_ntoa(netif_ip6_addr(netif, addr_idx)), + netif_ip6_addr_state(netif, addr_idx))); +} + +/** + * Checks if a specific local address is present on the netif and returns its + * index. Depending on its state, it may or may not be assigned to the + * interface (as per RFC terminology). + * + * The given address may or may not be zoned (i.e., have a zone index other + * than IP6_NO_ZONE). If the address is zoned, it must have the correct zone + * for the given netif, or no match will be found. + * + * @param netif the netif to check + * @param ip6addr the IPv6 address to find + * @return >= 0: address found, this is its index + * -1: address not found on this netif + */ +s8_t +netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr) +{ + s8_t i; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("netif_get_ip6_addr_match: invalid netif", netif != NULL); + LWIP_ASSERT("netif_get_ip6_addr_match: invalid ip6addr", ip6addr != NULL); + +#if LWIP_IPV6_SCOPES + if (ip6_addr_has_zone(ip6addr) && !ip6_addr_test_zone(ip6addr, netif)) { + return -1; /* wrong zone, no match */ + } +#endif /* LWIP_IPV6_SCOPES */ + + for (i = 0; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (!ip6_addr_isinvalid(netif_ip6_addr_state(netif, i)) && + ip6_addr_cmp_zoneless(netif_ip6_addr(netif, i), ip6addr)) { + return i; + } + } + return -1; +} + +/** + * @ingroup netif_ip6 + * Create a link-local IPv6 address on a netif (stored in slot 0) + * + * @param netif the netif to create the address on + * @param from_mac_48bit if != 0, assume hwadr is a 48-bit MAC address (std conversion) + * if == 0, use hwaddr directly as interface ID + */ +void +netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit) +{ + u8_t i, addr_index; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("netif_create_ip6_linklocal_address: invalid netif", netif != NULL); + + /* Link-local prefix. */ + ip_2_ip6(&netif->ip6_addr[0])->addr[0] = PP_HTONL(0xfe800000ul); + ip_2_ip6(&netif->ip6_addr[0])->addr[1] = 0; + + /* Generate interface ID. */ + if (from_mac_48bit) { + /* Assume hwaddr is a 48-bit IEEE 802 MAC. Convert to EUI-64 address. Complement Group bit. */ + ip_2_ip6(&netif->ip6_addr[0])->addr[2] = lwip_htonl((((u32_t)(netif->hwaddr[0] ^ 0x02)) << 24) | + ((u32_t)(netif->hwaddr[1]) << 16) | + ((u32_t)(netif->hwaddr[2]) << 8) | + (0xff)); + ip_2_ip6(&netif->ip6_addr[0])->addr[3] = lwip_htonl((u32_t)(0xfeul << 24) | + ((u32_t)(netif->hwaddr[3]) << 16) | + ((u32_t)(netif->hwaddr[4]) << 8) | + (netif->hwaddr[5])); + } else { + /* Use hwaddr directly as interface ID. */ + ip_2_ip6(&netif->ip6_addr[0])->addr[2] = 0; + ip_2_ip6(&netif->ip6_addr[0])->addr[3] = 0; + + addr_index = 3; + for (i = 0; (i < 8) && (i < netif->hwaddr_len); i++) { + if (i == 4) { + addr_index--; + } + ip_2_ip6(&netif->ip6_addr[0])->addr[addr_index] |= lwip_htonl(((u32_t)(netif->hwaddr[netif->hwaddr_len - i - 1])) << (8 * (i & 0x03))); + } + } + + /* Set a link-local zone. Even though the zone is implied by the owning + * netif, setting the zone anyway has two important conceptual advantages: + * 1) it avoids the need for a ton of exceptions in internal code, allowing + * e.g. ip6_addr_cmp() to be used on local addresses; + * 2) the properly zoned address is visible externally, e.g. when any outside + * code enumerates available addresses or uses one to bind a socket. + * Any external code unaware of address scoping is likely to just ignore the + * zone field, so this should not create any compatibility problems. */ + ip6_addr_assign_zone(ip_2_ip6(&netif->ip6_addr[0]), IP6_UNICAST, netif); + + /* Set address state. */ +#if LWIP_IPV6_DUP_DETECT_ATTEMPTS + /* Will perform duplicate address detection (DAD). */ + netif_ip6_addr_set_state(netif, 0, IP6_ADDR_TENTATIVE); +#else + /* Consider address valid. */ + netif_ip6_addr_set_state(netif, 0, IP6_ADDR_PREFERRED); +#endif /* LWIP_IPV6_AUTOCONFIG */ +} + +/** + * @ingroup netif_ip6 + * This function allows for the easy addition of a new IPv6 address to an interface. + * It takes care of finding an empty slot and then sets the address tentative + * (to make sure that all the subsequent processing happens). + * + * @param netif netif to add the address on + * @param ip6addr address to add + * @param chosen_idx if != NULL, the chosen IPv6 address index will be stored here + */ +err_t +netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx) +{ + s8_t i; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("netif_add_ip6_address: invalid netif", netif != NULL); + LWIP_ASSERT("netif_add_ip6_address: invalid ip6addr", ip6addr != NULL); + + i = netif_get_ip6_addr_match(netif, ip6addr); + if (i >= 0) { + /* Address already added */ + if (chosen_idx != NULL) { + *chosen_idx = i; + } + return ERR_OK; + } + + /* Find a free slot. The first one is reserved for link-local addresses. */ + for (i = ip6_addr_islinklocal(ip6addr) ? 0 : 1; i < LWIP_IPV6_NUM_ADDRESSES; i++) { + if (ip6_addr_isinvalid(netif_ip6_addr_state(netif, i))) { + ip_addr_copy_from_ip6(netif->ip6_addr[i], *ip6addr); + ip6_addr_assign_zone(ip_2_ip6(&netif->ip6_addr[i]), IP6_UNICAST, netif); + netif_ip6_addr_set_state(netif, i, IP6_ADDR_TENTATIVE); + if (chosen_idx != NULL) { + *chosen_idx = i; + } + return ERR_OK; + } + } + + if (chosen_idx != NULL) { + *chosen_idx = -1; + } + return ERR_VAL; +} + +/** Dummy IPv6 output function for netifs not supporting IPv6 + */ +static err_t +netif_null_output_ip6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr) +{ + LWIP_UNUSED_ARG(netif); + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(ipaddr); + + return ERR_IF; +} +#endif /* LWIP_IPV6 */ + +#if LWIP_IPV4 +/** Dummy IPv4 output function for netifs not supporting IPv4 + */ +static err_t +netif_null_output_ip4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr) +{ + LWIP_UNUSED_ARG(netif); + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(ipaddr); + + return ERR_IF; +} +#endif /* LWIP_IPV4 */ + +/** +* @ingroup netif +* Return the interface index for the netif with name +* or NETIF_NO_INDEX if not found/on error +* +* @param name the name of the netif +*/ +u8_t +netif_name_to_index(const char *name) +{ + struct netif *netif = netif_find(name); + if (netif != NULL) { + return netif_get_index(netif); + } + /* No name found, return invalid index */ + return NETIF_NO_INDEX; +} + +/** +* @ingroup netif +* Return the interface name for the netif matching index +* or NULL if not found/on error +* +* @param idx the interface index of the netif +* @param name char buffer of at least NETIF_NAMESIZE bytes +*/ +char * +netif_index_to_name(u8_t idx, char *name) +{ + struct netif *netif = netif_get_by_index(idx); + + if (netif != NULL) { + name[0] = netif->name[0]; + name[1] = netif->name[1]; + lwip_itoa(&name[2], NETIF_NAMESIZE - 2, netif_index_to_num(idx)); + return name; + } + return NULL; +} + +/** +* @ingroup netif +* Return the interface for the netif index +* +* @param idx index of netif to find +*/ +struct netif * +netif_get_by_index(u8_t idx) +{ + struct netif *netif; + + LWIP_ASSERT_CORE_LOCKED(); + + if (idx != NETIF_NO_INDEX) { + NETIF_FOREACH(netif) { + if (idx == netif_get_index(netif)) { + return netif; /* found! */ + } + } + } + + return NULL; +} + +/** + * @ingroup netif + * Find a network interface by searching for its name + * + * @param name the name of the netif (like netif->name) plus concatenated number + * in ascii representation (e.g. 'en0') + */ +struct netif * +netif_find(const char *name) +{ + struct netif *netif; + u8_t num; + + LWIP_ASSERT_CORE_LOCKED(); + + if (name == NULL) { + return NULL; + } + + num = (u8_t)atoi(&name[2]); + + NETIF_FOREACH(netif) { + if (num == netif->num && + name[0] == netif->name[0] && + name[1] == netif->name[1]) { + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: found %c%c\n", name[0], name[1])); + return netif; + } + } + LWIP_DEBUGF(NETIF_DEBUG, ("netif_find: didn't find %c%c\n", name[0], name[1])); + return NULL; +} + +#if LWIP_NETIF_EXT_STATUS_CALLBACK +/** + * @ingroup netif + * Add extended netif events listener + * @param callback pointer to listener structure + * @param fn callback function + */ +void +netif_add_ext_callback(netif_ext_callback_t *callback, netif_ext_callback_fn fn) +{ + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("callback must be != NULL", callback != NULL); + LWIP_ASSERT("fn must be != NULL", fn != NULL); + + callback->callback_fn = fn; + callback->next = ext_callback; + ext_callback = callback; +} + +/** + * @ingroup netif + * Remove extended netif events listener + * @param callback pointer to listener structure + */ +void +netif_remove_ext_callback(netif_ext_callback_t* callback) +{ + netif_ext_callback_t *last, *iter; + + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("callback must be != NULL", callback != NULL); + + if (ext_callback == NULL) { + return; + } + + if (callback == ext_callback) { + ext_callback = ext_callback->next; + } else { + last = ext_callback; + for (iter = ext_callback->next; iter != NULL; last = iter, iter = iter->next) { + if (iter == callback) { + LWIP_ASSERT("last != NULL", last != NULL); + last->next = callback->next; + callback->next = NULL; + return; + } + } + } +} + +/** + * Invoke extended netif status event + * @param netif netif that is affected by change + * @param reason change reason + * @param args depends on reason, see reason description + */ +void +netif_invoke_ext_callback(struct netif *netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t *args) +{ + netif_ext_callback_t *callback = ext_callback; + + LWIP_ASSERT("netif must be != NULL", netif != NULL); + + while (callback != NULL) { + callback->callback_fn(netif, reason, args); + callback = callback->next; + } +} +#endif /* LWIP_NETIF_EXT_STATUS_CALLBACK */ diff --git a/Middlewares/Third_Party/LwIP/src/core/pbuf.c b/Middlewares/Third_Party/LwIP/src/core/pbuf.c new file mode 100644 index 0000000..a209e0c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/pbuf.c @@ -0,0 +1,1514 @@ +/** + * @file + * Packet buffer management + */ + +/** + * @defgroup pbuf Packet buffers (PBUF) + * @ingroup infrastructure + * + * Packets are built from the pbuf data structure. It supports dynamic + * memory allocation for packet contents or can reference externally + * managed packet contents both in RAM and ROM. Quick allocation for + * incoming packets is provided through pools with fixed sized pbufs. + * + * A packet may span over multiple pbufs, chained as a singly linked + * list. This is called a "pbuf chain". + * + * Multiple packets may be queued, also using this singly linked list. + * This is called a "packet queue". + * + * So, a packet queue consists of one or more pbuf chains, each of + * which consist of one or more pbufs. CURRENTLY, PACKET QUEUES ARE + * NOT SUPPORTED!!! Use helper structs to queue multiple packets. + * + * The differences between a pbuf chain and a packet queue are very + * precise but subtle. + * + * The last pbuf of a packet has a ->tot_len field that equals the + * ->len field. It can be found by traversing the list. If the last + * pbuf of a packet has a ->next field other than NULL, more packets + * are on the queue. + * + * Therefore, looping through a pbuf of a single packet, has an + * loop end condition (tot_len == p->len), NOT (next == NULL). + * + * Example of custom pbuf usage: @ref zerocopyrx + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/sys.h" +#include "lwip/netif.h" +#if LWIP_TCP && TCP_QUEUE_OOSEQ +#include "lwip/priv/tcp_priv.h" +#endif +#if LWIP_CHECKSUM_ON_COPY +#include "lwip/inet_chksum.h" +#endif + +#include + +#define SIZEOF_STRUCT_PBUF LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) +/* Since the pool is created in memp, PBUF_POOL_BUFSIZE will be automatically + aligned there. Therefore, PBUF_POOL_BUFSIZE_ALIGNED can be used here. */ +#define PBUF_POOL_BUFSIZE_ALIGNED LWIP_MEM_ALIGN_SIZE(PBUF_POOL_BUFSIZE) + +static const struct pbuf * +pbuf_skip_const(const struct pbuf *in, u16_t in_offset, u16_t *out_offset); + +#if !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ +#define PBUF_POOL_IS_EMPTY() +#else /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */ + +#if !NO_SYS +#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL +#include "lwip/tcpip.h" +#define PBUF_POOL_FREE_OOSEQ_QUEUE_CALL() do { \ + if (tcpip_try_callback(pbuf_free_ooseq_callback, NULL) != ERR_OK) { \ + SYS_ARCH_PROTECT(old_level); \ + pbuf_free_ooseq_pending = 0; \ + SYS_ARCH_UNPROTECT(old_level); \ + } } while(0) +#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ +#endif /* !NO_SYS */ + +volatile u8_t pbuf_free_ooseq_pending; +#define PBUF_POOL_IS_EMPTY() pbuf_pool_is_empty() + +/** + * Attempt to reclaim some memory from queued out-of-sequence TCP segments + * if we run out of pool pbufs. It's better to give priority to new packets + * if we're running out. + * + * This must be done in the correct thread context therefore this function + * can only be used with NO_SYS=0 and through tcpip_callback. + */ +#if !NO_SYS +static +#endif /* !NO_SYS */ +void +pbuf_free_ooseq(void) +{ + struct tcp_pcb *pcb; + SYS_ARCH_SET(pbuf_free_ooseq_pending, 0); + + for (pcb = tcp_active_pcbs; NULL != pcb; pcb = pcb->next) { + if (pcb->ooseq != NULL) { + /** Free the ooseq pbufs of one PCB only */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free_ooseq: freeing out-of-sequence pbufs\n")); + tcp_free_ooseq(pcb); + return; + } + } +} + +#if !NO_SYS +/** + * Just a callback function for tcpip_callback() that calls pbuf_free_ooseq(). + */ +static void +pbuf_free_ooseq_callback(void *arg) +{ + LWIP_UNUSED_ARG(arg); + pbuf_free_ooseq(); +} +#endif /* !NO_SYS */ + +/** Queue a call to pbuf_free_ooseq if not already queued. */ +static void +pbuf_pool_is_empty(void) +{ +#ifndef PBUF_POOL_FREE_OOSEQ_QUEUE_CALL + SYS_ARCH_SET(pbuf_free_ooseq_pending, 1); +#else /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ + u8_t queued; + SYS_ARCH_DECL_PROTECT(old_level); + SYS_ARCH_PROTECT(old_level); + queued = pbuf_free_ooseq_pending; + pbuf_free_ooseq_pending = 1; + SYS_ARCH_UNPROTECT(old_level); + + if (!queued) { + /* queue a call to pbuf_free_ooseq if not already queued */ + PBUF_POOL_FREE_OOSEQ_QUEUE_CALL(); + } +#endif /* PBUF_POOL_FREE_OOSEQ_QUEUE_CALL */ +} +#endif /* !LWIP_TCP || !TCP_QUEUE_OOSEQ || !PBUF_POOL_FREE_OOSEQ */ + +/* Initialize members of struct pbuf after allocation */ +static void +pbuf_init_alloced_pbuf(struct pbuf *p, void *payload, u16_t tot_len, u16_t len, pbuf_type type, u8_t flags) +{ + p->next = NULL; + p->payload = payload; + p->tot_len = tot_len; + p->len = len; + p->type_internal = (u8_t)type; + p->flags = flags; + p->ref = 1; + p->if_idx = NETIF_NO_INDEX; +} + +/** + * @ingroup pbuf + * Allocates a pbuf of the given type (possibly a chain for PBUF_POOL type). + * + * The actual memory allocated for the pbuf is determined by the + * layer at which the pbuf is allocated and the requested size + * (from the size parameter). + * + * @param layer header size + * @param length size of the pbuf's payload + * @param type this parameter decides how and where the pbuf + * should be allocated as follows: + * + * - PBUF_RAM: buffer memory for pbuf is allocated as one large + * chunk. This includes protocol headers as well. + * - PBUF_ROM: no buffer memory is allocated for the pbuf, even for + * protocol headers. Additional headers must be prepended + * by allocating another pbuf and chain in to the front of + * the ROM pbuf. It is assumed that the memory used is really + * similar to ROM in that it is immutable and will not be + * changed. Memory which is dynamic should generally not + * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. + * - PBUF_REF: no buffer memory is allocated for the pbuf, even for + * protocol headers. It is assumed that the pbuf is only + * being used in a single thread. If the pbuf gets queued, + * then pbuf_take should be called to copy the buffer. + * - PBUF_POOL: the pbuf is allocated as a pbuf chain, with pbufs from + * the pbuf pool that is allocated during pbuf_init(). + * + * @return the allocated pbuf. If multiple pbufs where allocated, this + * is the first pbuf of a pbuf chain. + */ +struct pbuf * +pbuf_alloc(pbuf_layer layer, u16_t length, pbuf_type type) +{ + struct pbuf *p; + u16_t offset = (u16_t)layer; + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F")\n", length)); + + switch (type) { + case PBUF_REF: /* fall through */ + case PBUF_ROM: + p = pbuf_alloc_reference(NULL, length, type); + break; + case PBUF_POOL: { + struct pbuf *q, *last; + u16_t rem_len; /* remaining length */ + p = NULL; + last = NULL; + rem_len = length; + do { + u16_t qlen; + q = (struct pbuf *)memp_malloc(MEMP_PBUF_POOL); + if (q == NULL) { + PBUF_POOL_IS_EMPTY(); + /* free chain so far allocated */ + if (p) { + pbuf_free(p); + } + /* bail out unsuccessfully */ + return NULL; + } + qlen = LWIP_MIN(rem_len, (u16_t)(PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset))); + pbuf_init_alloced_pbuf(q, LWIP_MEM_ALIGN((void *)((u8_t *)q + SIZEOF_STRUCT_PBUF + offset)), + rem_len, qlen, type, 0); + LWIP_ASSERT("pbuf_alloc: pbuf q->payload properly aligned", + ((mem_ptr_t)q->payload % MEM_ALIGNMENT) == 0); + LWIP_ASSERT("PBUF_POOL_BUFSIZE must be bigger than MEM_ALIGNMENT", + (PBUF_POOL_BUFSIZE_ALIGNED - LWIP_MEM_ALIGN_SIZE(offset)) > 0 ); + if (p == NULL) { + /* allocated head of pbuf chain (into p) */ + p = q; + } else { + /* make previous pbuf point to this pbuf */ + last->next = q; + } + last = q; + rem_len = (u16_t)(rem_len - qlen); + offset = 0; + } while (rem_len > 0); + break; + } + case PBUF_RAM: { + u16_t payload_len = (u16_t)(LWIP_MEM_ALIGN_SIZE(offset) + LWIP_MEM_ALIGN_SIZE(length)); + mem_size_t alloc_len = (mem_size_t)(LWIP_MEM_ALIGN_SIZE(SIZEOF_STRUCT_PBUF) + payload_len); + + /* bug #50040: Check for integer overflow when calculating alloc_len */ + if ((payload_len < LWIP_MEM_ALIGN_SIZE(length)) || + (alloc_len < LWIP_MEM_ALIGN_SIZE(length))) { + return NULL; + } + + /* If pbuf is to be allocated in RAM, allocate memory for it. */ + p = (struct pbuf *)mem_malloc(alloc_len); + if (p == NULL) { + return NULL; + } + pbuf_init_alloced_pbuf(p, LWIP_MEM_ALIGN((void *)((u8_t *)p + SIZEOF_STRUCT_PBUF + offset)), + length, length, type, 0); + LWIP_ASSERT("pbuf_alloc: pbuf->payload properly aligned", + ((mem_ptr_t)p->payload % MEM_ALIGNMENT) == 0); + break; + } + default: + LWIP_ASSERT("pbuf_alloc: erroneous type", 0); + return NULL; + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloc(length=%"U16_F") == %p\n", length, (void *)p)); + return p; +} + +/** + * @ingroup pbuf + * Allocates a pbuf for referenced data. + * Referenced data can be volatile (PBUF_REF) or long-lived (PBUF_ROM). + * + * The actual memory allocated for the pbuf is determined by the + * layer at which the pbuf is allocated and the requested size + * (from the size parameter). + * + * @param payload referenced payload + * @param length size of the pbuf's payload + * @param type this parameter decides how and where the pbuf + * should be allocated as follows: + * + * - PBUF_ROM: It is assumed that the memory used is really + * similar to ROM in that it is immutable and will not be + * changed. Memory which is dynamic should generally not + * be attached to PBUF_ROM pbufs. Use PBUF_REF instead. + * - PBUF_REF: It is assumed that the pbuf is only + * being used in a single thread. If the pbuf gets queued, + * then pbuf_take should be called to copy the buffer. + * + * @return the allocated pbuf. + */ +struct pbuf * +pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type) +{ + struct pbuf *p; + LWIP_ASSERT("invalid pbuf_type", (type == PBUF_REF) || (type == PBUF_ROM)); + /* only allocate memory for the pbuf structure */ + p = (struct pbuf *)memp_malloc(MEMP_PBUF); + if (p == NULL) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_alloc_reference: Could not allocate MEMP_PBUF for PBUF_%s.\n", + (type == PBUF_ROM) ? "ROM" : "REF")); + return NULL; + } + pbuf_init_alloced_pbuf(p, payload, length, length, type, 0); + return p; +} + + +#if LWIP_SUPPORT_CUSTOM_PBUF +/** + * @ingroup pbuf + * Initialize a custom pbuf (already allocated). + * Example of custom pbuf usage: @ref zerocopyrx + * + * @param l header size + * @param length size of the pbuf's payload + * @param type type of the pbuf (only used to treat the pbuf accordingly, as + * this function allocates no memory) + * @param p pointer to the custom pbuf to initialize (already allocated) + * @param payload_mem pointer to the buffer that is used for payload and headers, + * must be at least big enough to hold 'length' plus the header size, + * may be NULL if set later. + * ATTENTION: The caller is responsible for correct alignment of this buffer!! + * @param payload_mem_len the size of the 'payload_mem' buffer, must be at least + * big enough to hold 'length' plus the header size + */ +struct pbuf * +pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, struct pbuf_custom *p, + void *payload_mem, u16_t payload_mem_len) +{ + u16_t offset = (u16_t)l; + void *payload; + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_alloced_custom(length=%"U16_F")\n", length)); + + if (LWIP_MEM_ALIGN_SIZE(offset) + length > payload_mem_len) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_WARNING, ("pbuf_alloced_custom(length=%"U16_F") buffer too short\n", length)); + return NULL; + } + + if (payload_mem != NULL) { + payload = (u8_t *)payload_mem + LWIP_MEM_ALIGN_SIZE(offset); + } else { + payload = NULL; + } + pbuf_init_alloced_pbuf(&p->pbuf, payload, length, length, type, PBUF_FLAG_IS_CUSTOM); + return &p->pbuf; +} +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + +/** + * @ingroup pbuf + * Shrink a pbuf chain to a desired length. + * + * @param p pbuf to shrink. + * @param new_len desired new length of pbuf chain + * + * Depending on the desired length, the first few pbufs in a chain might + * be skipped and left unchanged. The new last pbuf in the chain will be + * resized, and any remaining pbufs will be freed. + * + * @note If the pbuf is ROM/REF, only the ->tot_len and ->len fields are adjusted. + * @note May not be called on a packet queue. + * + * @note Despite its name, pbuf_realloc cannot grow the size of a pbuf (chain). + */ +void +pbuf_realloc(struct pbuf *p, u16_t new_len) +{ + struct pbuf *q; + u16_t rem_len; /* remaining length */ + u16_t shrink; + + LWIP_ASSERT("pbuf_realloc: p != NULL", p != NULL); + + /* desired length larger than current length? */ + if (new_len >= p->tot_len) { + /* enlarging not yet supported */ + return; + } + + /* the pbuf chain grows by (new_len - p->tot_len) bytes + * (which may be negative in case of shrinking) */ + shrink = (u16_t)(p->tot_len - new_len); + + /* first, step over any pbufs that should remain in the chain */ + rem_len = new_len; + q = p; + /* should this pbuf be kept? */ + while (rem_len > q->len) { + /* decrease remaining length by pbuf length */ + rem_len = (u16_t)(rem_len - q->len); + /* decrease total length indicator */ + q->tot_len = (u16_t)(q->tot_len - shrink); + /* proceed to next pbuf in chain */ + q = q->next; + LWIP_ASSERT("pbuf_realloc: q != NULL", q != NULL); + } + /* we have now reached the new last pbuf (in q) */ + /* rem_len == desired length for pbuf q */ + + /* shrink allocated memory for PBUF_RAM */ + /* (other types merely adjust their length fields */ + if (pbuf_match_allocsrc(q, PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) && (rem_len != q->len) +#if LWIP_SUPPORT_CUSTOM_PBUF + && ((q->flags & PBUF_FLAG_IS_CUSTOM) == 0) +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + ) { + /* reallocate and adjust the length of the pbuf that will be split */ + q = (struct pbuf *)mem_trim(q, (mem_size_t)(((u8_t *)q->payload - (u8_t *)q) + rem_len)); + LWIP_ASSERT("mem_trim returned q == NULL", q != NULL); + } + /* adjust length fields for new last pbuf */ + q->len = rem_len; + q->tot_len = q->len; + + /* any remaining pbufs in chain? */ + if (q->next != NULL) { + /* free remaining pbufs in chain */ + pbuf_free(q->next); + } + /* q is last packet in chain */ + q->next = NULL; + +} + +/** + * Adjusts the payload pointer to reveal headers in the payload. + * @see pbuf_add_header. + * + * @param p pbuf to change the header size. + * @param header_size_increment Number of bytes to increment header size. + * @param force Allow 'header_size_increment > 0' for PBUF_REF/PBUF_ROM types + * + * @return non-zero on failure, zero on success. + * + */ +static u8_t +pbuf_add_header_impl(struct pbuf *p, size_t header_size_increment, u8_t force) +{ + u16_t type_internal; + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + if ((p == NULL) || (header_size_increment > 0xFFFF)) { + return 1; + } + if (header_size_increment == 0) { + return 0; + } + + increment_magnitude = (u16_t)header_size_increment; + /* Do not allow tot_len to wrap as a result. */ + if ((u16_t)(increment_magnitude + p->tot_len) < increment_magnitude) { + return 1; + } + + type_internal = p->type_internal; + + /* pbuf types containing payloads? */ + if (type_internal & PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS) { + /* set new payload pointer */ + payload = (u8_t *)p->payload - header_size_increment; + /* boundary check fails? */ + if ((u8_t *)payload < (u8_t *)p + SIZEOF_STRUCT_PBUF) { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, + ("pbuf_add_header: failed as %p < %p (not enough space for new header size)\n", + (void *)payload, (void *)((u8_t *)p + SIZEOF_STRUCT_PBUF))); + /* bail out unsuccessfully */ + return 1; + } + /* pbuf types referring to external payloads? */ + } else { + /* hide a header in the payload? */ + if (force) { + payload = (u8_t *)p->payload - header_size_increment; + } else { + /* cannot expand payload to front (yet!) + * bail out unsuccessfully */ + return 1; + } + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_add_header: old %p new %p (%"U16_F")\n", + (void *)p->payload, (void *)payload, increment_magnitude)); + + /* modify pbuf fields */ + p->payload = payload; + p->len = (u16_t)(p->len + increment_magnitude); + p->tot_len = (u16_t)(p->tot_len + increment_magnitude); + + + return 0; +} + +/** + * Adjusts the payload pointer to reveal headers in the payload. + * + * Adjusts the ->payload pointer so that space for a header + * appears in the pbuf payload. + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * + * @param p pbuf to change the header size. + * @param header_size_increment Number of bytes to increment header size which + * increases the size of the pbuf. New space is on the front. + * If header_size_increment is 0, this function does nothing and returns successful. + * + * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so + * the call will fail. A check is made that the increase in header size does + * not move the payload pointer in front of the start of the buffer. + * + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_add_header(struct pbuf *p, size_t header_size_increment) +{ + return pbuf_add_header_impl(p, header_size_increment, 0); +} + +/** + * Same as @ref pbuf_add_header but does not check if 'header_size > 0' is allowed. + * This is used internally only, to allow PBUF_REF for RX. + */ +u8_t +pbuf_add_header_force(struct pbuf *p, size_t header_size_increment) +{ + return pbuf_add_header_impl(p, header_size_increment, 1); +} + +/** + * Adjusts the payload pointer to hide headers in the payload. + * + * Adjusts the ->payload pointer so that space for a header + * disappears in the pbuf payload. + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * + * @param p pbuf to change the header size. + * @param header_size_decrement Number of bytes to decrement header size which + * decreases the size of the pbuf. + * If header_size_decrement is 0, this function does nothing and returns successful. + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_remove_header(struct pbuf *p, size_t header_size_decrement) +{ + void *payload; + u16_t increment_magnitude; + + LWIP_ASSERT("p != NULL", p != NULL); + if ((p == NULL) || (header_size_decrement > 0xFFFF)) { + return 1; + } + if (header_size_decrement == 0) { + return 0; + } + + increment_magnitude = (u16_t)header_size_decrement; + /* Check that we aren't going to move off the end of the pbuf */ + LWIP_ERROR("increment_magnitude <= p->len", (increment_magnitude <= p->len), return 1;); + + /* remember current payload pointer */ + payload = p->payload; + LWIP_UNUSED_ARG(payload); /* only used in LWIP_DEBUGF below */ + + /* increase payload pointer (guarded by length check above) */ + p->payload = (u8_t *)p->payload + header_size_decrement; + /* modify pbuf length fields */ + p->len = (u16_t)(p->len - increment_magnitude); + p->tot_len = (u16_t)(p->tot_len - increment_magnitude); + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_remove_header: old %p new %p (%"U16_F")\n", + (void *)payload, (void *)p->payload, increment_magnitude)); + + return 0; +} + +static u8_t +pbuf_header_impl(struct pbuf *p, s16_t header_size_increment, u8_t force) +{ + if (header_size_increment < 0) { + return pbuf_remove_header(p, (size_t) - header_size_increment); + } else { + return pbuf_add_header_impl(p, (size_t)header_size_increment, force); + } +} + +/** + * Adjusts the payload pointer to hide or reveal headers in the payload. + * + * Adjusts the ->payload pointer so that space for a header + * (dis)appears in the pbuf payload. + * + * The ->payload, ->tot_len and ->len fields are adjusted. + * + * @param p pbuf to change the header size. + * @param header_size_increment Number of bytes to increment header size which + * increases the size of the pbuf. New space is on the front. + * (Using a negative value decreases the header size.) + * If header_size_increment is 0, this function does nothing and returns successful. + * + * PBUF_ROM and PBUF_REF type buffers cannot have their sizes increased, so + * the call will fail. A check is made that the increase in header size does + * not move the payload pointer in front of the start of the buffer. + * @return non-zero on failure, zero on success. + * + */ +u8_t +pbuf_header(struct pbuf *p, s16_t header_size_increment) +{ + return pbuf_header_impl(p, header_size_increment, 0); +} + +/** + * Same as pbuf_header but does not check if 'header_size > 0' is allowed. + * This is used internally only, to allow PBUF_REF for RX. + */ +u8_t +pbuf_header_force(struct pbuf *p, s16_t header_size_increment) +{ + return pbuf_header_impl(p, header_size_increment, 1); +} + +/** Similar to pbuf_header(-size) but de-refs header pbufs for (size >= p->len) + * + * @param q pbufs to operate on + * @param size The number of bytes to remove from the beginning of the pbuf list. + * While size >= p->len, pbufs are freed. + * ATTENTION: this is the opposite direction as @ref pbuf_header, but + * takes an u16_t not s16_t! + * @return the new head pbuf + */ +struct pbuf * +pbuf_free_header(struct pbuf *q, u16_t size) +{ + struct pbuf *p = q; + u16_t free_left = size; + while (free_left && p) { + if (free_left >= p->len) { + struct pbuf *f = p; + free_left = (u16_t)(free_left - p->len); + p = p->next; + f->next = 0; + pbuf_free(f); + } else { + pbuf_remove_header(p, free_left); + free_left = 0; + } + } + return p; +} + +/** + * @ingroup pbuf + * Dereference a pbuf chain or queue and deallocate any no-longer-used + * pbufs at the head of this chain or queue. + * + * Decrements the pbuf reference count. If it reaches zero, the pbuf is + * deallocated. + * + * For a pbuf chain, this is repeated for each pbuf in the chain, + * up to the first pbuf which has a non-zero reference count after + * decrementing. So, when all reference counts are one, the whole + * chain is free'd. + * + * @param p The pbuf (chain) to be dereferenced. + * + * @return the number of pbufs that were de-allocated + * from the head of the chain. + * + * @note MUST NOT be called on a packet queue (Not verified to work yet). + * @note the reference counter of a pbuf equals the number of pointers + * that refer to the pbuf (or into the pbuf). + * + * @internal examples: + * + * Assuming existing chains a->b->c with the following reference + * counts, calling pbuf_free(a) results in: + * + * 1->2->3 becomes ...1->3 + * 3->3->3 becomes 2->3->3 + * 1->1->2 becomes ......1 + * 2->1->1 becomes 1->1->1 + * 1->1->1 becomes ....... + * + */ +u8_t +pbuf_free(struct pbuf *p) +{ + u8_t alloc_src; + struct pbuf *q; + u8_t count; + + if (p == NULL) { + LWIP_ASSERT("p != NULL", p != NULL); + /* if assertions are disabled, proceed with debug output */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("pbuf_free(p == NULL) was called.\n")); + return 0; + } + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free(%p)\n", (void *)p)); + + PERF_START; + + count = 0; + /* de-allocate all consecutive pbufs from the head of the chain that + * obtain a zero reference count after decrementing*/ + while (p != NULL) { + LWIP_PBUF_REF_T ref; + SYS_ARCH_DECL_PROTECT(old_level); + /* Since decrementing ref cannot be guaranteed to be a single machine operation + * we must protect it. We put the new ref into a local variable to prevent + * further protection. */ + SYS_ARCH_PROTECT(old_level); + /* all pbufs in a chain are referenced at least once */ + LWIP_ASSERT("pbuf_free: p->ref > 0", p->ref > 0); + /* decrease reference count (number of pointers to pbuf) */ + ref = --(p->ref); + SYS_ARCH_UNPROTECT(old_level); + /* this pbuf is no longer referenced to? */ + if (ref == 0) { + /* remember next pbuf in chain for next iteration */ + q = p->next; + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: deallocating %p\n", (void *)p)); + alloc_src = pbuf_get_allocsrc(p); +#if LWIP_SUPPORT_CUSTOM_PBUF + /* is this a custom pbuf? */ + if ((p->flags & PBUF_FLAG_IS_CUSTOM) != 0) { + struct pbuf_custom *pc = (struct pbuf_custom *)p; + LWIP_ASSERT("pc->custom_free_function != NULL", pc->custom_free_function != NULL); + pc->custom_free_function(p); + } else +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + { + /* is this a pbuf from the pool? */ + if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) { + memp_free(MEMP_PBUF_POOL, p); + /* is this a ROM or RAM referencing pbuf? */ + } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF) { + memp_free(MEMP_PBUF, p); + /* type == PBUF_RAM */ + } else if (alloc_src == PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP) { + mem_free(p); + } else { + /* @todo: support freeing other types */ + LWIP_ASSERT("invalid pbuf type", 0); + } + } + count++; + /* proceed to next pbuf */ + p = q; + /* p->ref > 0, this pbuf is still referenced to */ + /* (and so the remaining pbufs in chain as well) */ + } else { + LWIP_DEBUGF( PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_free: %p has ref %"U16_F", ending here.\n", (void *)p, (u16_t)ref)); + /* stop walking through the chain */ + p = NULL; + } + } + PERF_STOP("pbuf_free"); + /* return number of de-allocated pbufs */ + return count; +} + +/** + * Count number of pbufs in a chain + * + * @param p first pbuf of chain + * @return the number of pbufs in a chain + */ +u16_t +pbuf_clen(const struct pbuf *p) +{ + u16_t len; + + len = 0; + while (p != NULL) { + ++len; + p = p->next; + } + return len; +} + +/** + * @ingroup pbuf + * Increment the reference count of the pbuf. + * + * @param p pbuf to increase reference counter of + * + */ +void +pbuf_ref(struct pbuf *p) +{ + /* pbuf given? */ + if (p != NULL) { + SYS_ARCH_SET(p->ref, (LWIP_PBUF_REF_T)(p->ref + 1)); + LWIP_ASSERT("pbuf ref overflow", p->ref > 0); + } +} + +/** + * @ingroup pbuf + * Concatenate two pbufs (each may be a pbuf chain) and take over + * the caller's reference of the tail pbuf. + * + * @note The caller MAY NOT reference the tail pbuf afterwards. + * Use pbuf_chain() for that purpose. + * + * This function explicitly does not check for tot_len overflow to prevent + * failing to queue too long pbufs. This can produce invalid pbufs, so + * handle with care! + * + * @see pbuf_chain() + */ +void +pbuf_cat(struct pbuf *h, struct pbuf *t) +{ + struct pbuf *p; + + LWIP_ERROR("(h != NULL) && (t != NULL) (programmer violates API)", + ((h != NULL) && (t != NULL)), return;); + + /* proceed to last pbuf of chain */ + for (p = h; p->next != NULL; p = p->next) { + /* add total length of second chain to all totals of first chain */ + p->tot_len = (u16_t)(p->tot_len + t->tot_len); + } + /* { p is last pbuf of first h chain, p->next == NULL } */ + LWIP_ASSERT("p->tot_len == p->len (of last pbuf in chain)", p->tot_len == p->len); + LWIP_ASSERT("p->next == NULL", p->next == NULL); + /* add total length of second chain to last pbuf total of first chain */ + p->tot_len = (u16_t)(p->tot_len + t->tot_len); + /* chain last pbuf of head (p) with first of tail (t) */ + p->next = t; + /* p->next now references t, but the caller will drop its reference to t, + * so netto there is no change to the reference count of t. + */ +} + +/** + * @ingroup pbuf + * Chain two pbufs (or pbuf chains) together. + * + * The caller MUST call pbuf_free(t) once it has stopped + * using it. Use pbuf_cat() instead if you no longer use t. + * + * @param h head pbuf (chain) + * @param t tail pbuf (chain) + * @note The pbufs MUST belong to the same packet. + * @note MAY NOT be called on a packet queue. + * + * The ->tot_len fields of all pbufs of the head chain are adjusted. + * The ->next field of the last pbuf of the head chain is adjusted. + * The ->ref field of the first pbuf of the tail chain is adjusted. + * + */ +void +pbuf_chain(struct pbuf *h, struct pbuf *t) +{ + pbuf_cat(h, t); + /* t is now referenced by h */ + pbuf_ref(t); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_chain: %p references %p\n", (void *)h, (void *)t)); +} + +/** + * Dechains the first pbuf from its succeeding pbufs in the chain. + * + * Makes p->tot_len field equal to p->len. + * @param p pbuf to dechain + * @return remainder of the pbuf chain, or NULL if it was de-allocated. + * @note May not be called on a packet queue. + */ +struct pbuf * +pbuf_dechain(struct pbuf *p) +{ + struct pbuf *q; + u8_t tail_gone = 1; + /* tail */ + q = p->next; + /* pbuf has successor in chain? */ + if (q != NULL) { + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len + q->tot_len", q->tot_len == p->tot_len - p->len); + /* enforce invariant if assertion is disabled */ + q->tot_len = (u16_t)(p->tot_len - p->len); + /* decouple pbuf from remainder */ + p->next = NULL; + /* total length of pbuf p is its own length only */ + p->tot_len = p->len; + /* q is no longer referenced by p, free it */ + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_dechain: unreferencing %p\n", (void *)q)); + tail_gone = pbuf_free(q); + if (tail_gone > 0) { + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, + ("pbuf_dechain: deallocated %p (as it is no longer referenced)\n", (void *)q)); + } + /* return remaining tail or NULL if deallocated */ + } + /* assert tot_len invariant: (p->tot_len == p->len + (p->next? p->next->tot_len: 0) */ + LWIP_ASSERT("p->tot_len == p->len", p->tot_len == p->len); + return ((tail_gone > 0) ? NULL : q); +} + +/** + * @ingroup pbuf + * Create PBUF_RAM copies of pbufs. + * + * Used to queue packets on behalf of the lwIP stack, such as + * ARP based queueing. + * + * @note You MUST explicitly use p = pbuf_take(p); + * + * @note Only one packet is copied, no packet queue! + * + * @param p_to pbuf destination of the copy + * @param p_from pbuf source of the copy + * + * @return ERR_OK if pbuf was copied + * ERR_ARG if one of the pbufs is NULL or p_to is not big + * enough to hold p_from + */ +err_t +pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from) +{ + size_t offset_to = 0, offset_from = 0, len; + + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy(%p, %p)\n", + (const void *)p_to, (const void *)p_from)); + + /* is the target big enough to hold the source? */ + LWIP_ERROR("pbuf_copy: target not big enough to hold source", ((p_to != NULL) && + (p_from != NULL) && (p_to->tot_len >= p_from->tot_len)), return ERR_ARG;); + + /* iterate through pbuf chain */ + do { + /* copy one part of the original chain */ + if ((p_to->len - offset_to) >= (p_from->len - offset_from)) { + /* complete current p_from fits into current p_to */ + len = p_from->len - offset_from; + } else { + /* current p_from does not fit into current p_to */ + len = p_to->len - offset_to; + } + MEMCPY((u8_t *)p_to->payload + offset_to, (u8_t *)p_from->payload + offset_from, len); + offset_to += len; + offset_from += len; + LWIP_ASSERT("offset_to <= p_to->len", offset_to <= p_to->len); + LWIP_ASSERT("offset_from <= p_from->len", offset_from <= p_from->len); + if (offset_from >= p_from->len) { + /* on to next p_from (if any) */ + offset_from = 0; + p_from = p_from->next; + } + if (offset_to == p_to->len) { + /* on to next p_to (if any) */ + offset_to = 0; + p_to = p_to->next; + LWIP_ERROR("p_to != NULL", (p_to != NULL) || (p_from == NULL), return ERR_ARG;); + } + + if ((p_from != NULL) && (p_from->len == p_from->tot_len)) { + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!", + (p_from->next == NULL), return ERR_VAL;); + } + if ((p_to != NULL) && (p_to->len == p_to->tot_len)) { + /* don't copy more than one packet! */ + LWIP_ERROR("pbuf_copy() does not allow packet queues!", + (p_to->next == NULL), return ERR_VAL;); + } + } while (p_from); + LWIP_DEBUGF(PBUF_DEBUG | LWIP_DBG_TRACE, ("pbuf_copy: end of chain reached.\n")); + return ERR_OK; +} + +/** + * @ingroup pbuf + * Copy (part of) the contents of a packet buffer + * to an application supplied buffer. + * + * @param buf the pbuf from which to copy data + * @param dataptr the application supplied buffer + * @param len length of data to copy (dataptr must be big enough). No more + * than buf->tot_len will be copied, irrespective of len + * @param offset offset into the packet buffer from where to begin copying len bytes + * @return the number of bytes copied, or 0 on failure + */ +u16_t +pbuf_copy_partial(const struct pbuf *buf, void *dataptr, u16_t len, u16_t offset) +{ + const struct pbuf *p; + u16_t left = 0; + u16_t buf_copy_len; + u16_t copied_total = 0; + + LWIP_ERROR("pbuf_copy_partial: invalid buf", (buf != NULL), return 0;); + LWIP_ERROR("pbuf_copy_partial: invalid dataptr", (dataptr != NULL), return 0;); + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for (p = buf; len != 0 && p != NULL; p = p->next) { + if ((offset != 0) && (offset >= p->len)) { + /* don't copy from this buffer -> on to the next */ + offset = (u16_t)(offset - p->len); + } else { + /* copy from this buffer. maybe only partially. */ + buf_copy_len = (u16_t)(p->len - offset); + if (buf_copy_len > len) { + buf_copy_len = len; + } + /* copy the necessary parts of the buffer */ + MEMCPY(&((char *)dataptr)[left], &((char *)p->payload)[offset], buf_copy_len); + copied_total = (u16_t)(copied_total + buf_copy_len); + left = (u16_t)(left + buf_copy_len); + len = (u16_t)(len - buf_copy_len); + offset = 0; + } + } + return copied_total; +} + +/** + * @ingroup pbuf + * Get part of a pbuf's payload as contiguous memory. The returned memory is + * either a pointer into the pbuf's payload or, if split over multiple pbufs, + * a copy into the user-supplied buffer. + * + * @param p the pbuf from which to copy data + * @param buffer the application supplied buffer + * @param bufsize size of the application supplied buffer + * @param len length of data to copy (dataptr must be big enough). No more + * than buf->tot_len will be copied, irrespective of len + * @param offset offset into the packet buffer from where to begin copying len bytes + * @return the number of bytes copied, or 0 on failure + */ +void * +pbuf_get_contiguous(const struct pbuf *p, void *buffer, size_t bufsize, u16_t len, u16_t offset) +{ + const struct pbuf *q; + u16_t out_offset; + + LWIP_ERROR("pbuf_get_contiguous: invalid buf", (p != NULL), return NULL;); + LWIP_ERROR("pbuf_get_contiguous: invalid dataptr", (buffer != NULL), return NULL;); + LWIP_ERROR("pbuf_get_contiguous: invalid dataptr", (bufsize >= len), return NULL;); + + q = pbuf_skip_const(p, offset, &out_offset); + if (q != NULL) { + if (q->len >= (out_offset + len)) { + /* all data in this pbuf, return zero-copy */ + return (u8_t *)q->payload + out_offset; + } + /* need to copy */ + if (pbuf_copy_partial(q, buffer, len, out_offset) != len) { + /* copying failed: pbuf is too short */ + return NULL; + } + return buffer; + } + /* pbuf is too short (offset does not fit in) */ + return NULL; +} + +#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE +/** + * This method modifies a 'pbuf chain', so that its total length is + * smaller than 64K. The remainder of the original pbuf chain is stored + * in *rest. + * This function never creates new pbufs, but splits an existing chain + * in two parts. The tot_len of the modified packet queue will likely be + * smaller than 64K. + * 'packet queues' are not supported by this function. + * + * @param p the pbuf queue to be split + * @param rest pointer to store the remainder (after the first 64K) + */ +void pbuf_split_64k(struct pbuf *p, struct pbuf **rest) +{ + *rest = NULL; + if ((p != NULL) && (p->next != NULL)) { + u16_t tot_len_front = p->len; + struct pbuf *i = p; + struct pbuf *r = p->next; + + /* continue until the total length (summed up as u16_t) overflows */ + while ((r != NULL) && ((u16_t)(tot_len_front + r->len) >= tot_len_front)) { + tot_len_front = (u16_t)(tot_len_front + r->len); + i = r; + r = r->next; + } + /* i now points to last packet of the first segment. Set next + pointer to NULL */ + i->next = NULL; + + if (r != NULL) { + /* Update the tot_len field in the first part */ + for (i = p; i != NULL; i = i->next) { + i->tot_len = (u16_t)(i->tot_len - r->tot_len); + LWIP_ASSERT("tot_len/len mismatch in last pbuf", + (i->next != NULL) || (i->tot_len == i->len)); + } + if (p->flags & PBUF_FLAG_TCP_FIN) { + r->flags |= PBUF_FLAG_TCP_FIN; + } + + /* tot_len field in rest does not need modifications */ + /* reference counters do not need modifications */ + *rest = r; + } + } +} +#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + +/* Actual implementation of pbuf_skip() but returning const pointer... */ +static const struct pbuf * +pbuf_skip_const(const struct pbuf *in, u16_t in_offset, u16_t *out_offset) +{ + u16_t offset_left = in_offset; + const struct pbuf *q = in; + + /* get the correct pbuf */ + while ((q != NULL) && (q->len <= offset_left)) { + offset_left = (u16_t)(offset_left - q->len); + q = q->next; + } + if (out_offset != NULL) { + *out_offset = offset_left; + } + return q; +} + +/** + * @ingroup pbuf + * Skip a number of bytes at the start of a pbuf + * + * @param in input pbuf + * @param in_offset offset to skip + * @param out_offset resulting offset in the returned pbuf + * @return the pbuf in the queue where the offset is + */ +struct pbuf * +pbuf_skip(struct pbuf *in, u16_t in_offset, u16_t *out_offset) +{ + const struct pbuf *out = pbuf_skip_const(in, in_offset, out_offset); + return LWIP_CONST_CAST(struct pbuf *, out); +} + +/** + * @ingroup pbuf + * Copy application supplied data into a pbuf. + * This function can only be used to copy the equivalent of buf->tot_len data. + * + * @param buf pbuf to fill with data + * @param dataptr application supplied data buffer + * @param len length of the application supplied data buffer + * + * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough + */ +err_t +pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len) +{ + struct pbuf *p; + size_t buf_copy_len; + size_t total_copy_len = len; + size_t copied_total = 0; + + LWIP_ERROR("pbuf_take: invalid buf", (buf != NULL), return ERR_ARG;); + LWIP_ERROR("pbuf_take: invalid dataptr", (dataptr != NULL), return ERR_ARG;); + LWIP_ERROR("pbuf_take: buf not large enough", (buf->tot_len >= len), return ERR_MEM;); + + if ((buf == NULL) || (dataptr == NULL) || (buf->tot_len < len)) { + return ERR_ARG; + } + + /* Note some systems use byte copy if dataptr or one of the pbuf payload pointers are unaligned. */ + for (p = buf; total_copy_len != 0; p = p->next) { + LWIP_ASSERT("pbuf_take: invalid pbuf", p != NULL); + buf_copy_len = total_copy_len; + if (buf_copy_len > p->len) { + /* this pbuf cannot hold all remaining data */ + buf_copy_len = p->len; + } + /* copy the necessary parts of the buffer */ + MEMCPY(p->payload, &((const char *)dataptr)[copied_total], buf_copy_len); + total_copy_len -= buf_copy_len; + copied_total += buf_copy_len; + } + LWIP_ASSERT("did not copy all data", total_copy_len == 0 && copied_total == len); + return ERR_OK; +} + +/** + * @ingroup pbuf + * Same as pbuf_take() but puts data at an offset + * + * @param buf pbuf to fill with data + * @param dataptr application supplied data buffer + * @param len length of the application supplied data buffer + * @param offset offset in pbuf where to copy dataptr to + * + * @return ERR_OK if successful, ERR_MEM if the pbuf is not big enough + */ +err_t +pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset) +{ + u16_t target_offset; + struct pbuf *q = pbuf_skip(buf, offset, &target_offset); + + /* return requested data if pbuf is OK */ + if ((q != NULL) && (q->tot_len >= target_offset + len)) { + u16_t remaining_len = len; + const u8_t *src_ptr = (const u8_t *)dataptr; + /* copy the part that goes into the first pbuf */ + u16_t first_copy_len; + LWIP_ASSERT("check pbuf_skip result", target_offset < q->len); + first_copy_len = (u16_t)LWIP_MIN(q->len - target_offset, len); + MEMCPY(((u8_t *)q->payload) + target_offset, dataptr, first_copy_len); + remaining_len = (u16_t)(remaining_len - first_copy_len); + src_ptr += first_copy_len; + if (remaining_len > 0) { + return pbuf_take(q->next, src_ptr, remaining_len); + } + return ERR_OK; + } + return ERR_MEM; +} + +/** + * @ingroup pbuf + * Creates a single pbuf out of a queue of pbufs. + * + * @remark: Either the source pbuf 'p' is freed by this function or the original + * pbuf 'p' is returned, therefore the caller has to check the result! + * + * @param p the source pbuf + * @param layer pbuf_layer of the new pbuf + * + * @return a new, single pbuf (p->next is NULL) + * or the old pbuf if allocation fails + */ +struct pbuf * +pbuf_coalesce(struct pbuf *p, pbuf_layer layer) +{ + struct pbuf *q; + if (p->next == NULL) { + return p; + } + q = pbuf_clone(layer, PBUF_RAM, p); + if (q == NULL) { + /* @todo: what do we do now? */ + return p; + } + pbuf_free(p); + return q; +} + +/** + * @ingroup pbuf + * Allocates a new pbuf of same length (via pbuf_alloc()) and copies the source + * pbuf into this new pbuf (using pbuf_copy()). + * + * @param layer pbuf_layer of the new pbuf + * @param type this parameter decides how and where the pbuf should be allocated + * (@see pbuf_alloc()) + * @param p the source pbuf + * + * @return a new pbuf or NULL if allocation fails + */ +struct pbuf * +pbuf_clone(pbuf_layer layer, pbuf_type type, struct pbuf *p) +{ + struct pbuf *q; + err_t err; + q = pbuf_alloc(layer, p->tot_len, type); + if (q == NULL) { + return NULL; + } + err = pbuf_copy(q, p); + LWIP_UNUSED_ARG(err); /* in case of LWIP_NOASSERT */ + LWIP_ASSERT("pbuf_copy failed", err == ERR_OK); + return q; +} + +#if LWIP_CHECKSUM_ON_COPY +/** + * Copies data into a single pbuf (*not* into a pbuf queue!) and updates + * the checksum while copying + * + * @param p the pbuf to copy data into + * @param start_offset offset of p->payload where to copy the data to + * @param dataptr data to copy into the pbuf + * @param len length of data to copy into the pbuf + * @param chksum pointer to the checksum which is updated + * @return ERR_OK if successful, another error if the data does not fit + * within the (first) pbuf (no pbuf queues!) + */ +err_t +pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr, + u16_t len, u16_t *chksum) +{ + u32_t acc; + u16_t copy_chksum; + char *dst_ptr; + LWIP_ASSERT("p != NULL", p != NULL); + LWIP_ASSERT("dataptr != NULL", dataptr != NULL); + LWIP_ASSERT("chksum != NULL", chksum != NULL); + LWIP_ASSERT("len != 0", len != 0); + + if ((start_offset >= p->len) || (start_offset + len > p->len)) { + return ERR_ARG; + } + + dst_ptr = ((char *)p->payload) + start_offset; + copy_chksum = LWIP_CHKSUM_COPY(dst_ptr, dataptr, len); + if ((start_offset & 1) != 0) { + copy_chksum = SWAP_BYTES_IN_WORD(copy_chksum); + } + acc = *chksum; + acc += copy_chksum; + *chksum = FOLD_U32T(acc); + return ERR_OK; +} +#endif /* LWIP_CHECKSUM_ON_COPY */ + +/** + * @ingroup pbuf + * Get one byte from the specified position in a pbuf + * WARNING: returns zero for offset >= p->tot_len + * + * @param p pbuf to parse + * @param offset offset into p of the byte to return + * @return byte at an offset into p OR ZERO IF 'offset' >= p->tot_len + */ +u8_t +pbuf_get_at(const struct pbuf *p, u16_t offset) +{ + int ret = pbuf_try_get_at(p, offset); + if (ret >= 0) { + return (u8_t)ret; + } + return 0; +} + +/** + * @ingroup pbuf + * Get one byte from the specified position in a pbuf + * + * @param p pbuf to parse + * @param offset offset into p of the byte to return + * @return byte at an offset into p [0..0xFF] OR negative if 'offset' >= p->tot_len + */ +int +pbuf_try_get_at(const struct pbuf *p, u16_t offset) +{ + u16_t q_idx; + const struct pbuf *q = pbuf_skip_const(p, offset, &q_idx); + + /* return requested data if pbuf is OK */ + if ((q != NULL) && (q->len > q_idx)) { + return ((u8_t *)q->payload)[q_idx]; + } + return -1; +} + +/** + * @ingroup pbuf + * Put one byte to the specified position in a pbuf + * WARNING: silently ignores offset >= p->tot_len + * + * @param p pbuf to fill + * @param offset offset into p of the byte to write + * @param data byte to write at an offset into p + */ +void +pbuf_put_at(struct pbuf *p, u16_t offset, u8_t data) +{ + u16_t q_idx; + struct pbuf *q = pbuf_skip(p, offset, &q_idx); + + /* write requested data if pbuf is OK */ + if ((q != NULL) && (q->len > q_idx)) { + ((u8_t *)q->payload)[q_idx] = data; + } +} + +/** + * @ingroup pbuf + * Compare pbuf contents at specified offset with memory s2, both of length n + * + * @param p pbuf to compare + * @param offset offset into p at which to start comparing + * @param s2 buffer to compare + * @param n length of buffer to compare + * @return zero if equal, nonzero otherwise + * (0xffff if p is too short, diffoffset+1 otherwise) + */ +u16_t +pbuf_memcmp(const struct pbuf *p, u16_t offset, const void *s2, u16_t n) +{ + u16_t start = offset; + const struct pbuf *q = p; + u16_t i; + + /* pbuf long enough to perform check? */ + if (p->tot_len < (offset + n)) { + return 0xffff; + } + + /* get the correct pbuf from chain. We know it succeeds because of p->tot_len check above. */ + while ((q != NULL) && (q->len <= start)) { + start = (u16_t)(start - q->len); + q = q->next; + } + + /* return requested data if pbuf is OK */ + for (i = 0; i < n; i++) { + /* We know pbuf_get_at() succeeds because of p->tot_len check above. */ + u8_t a = pbuf_get_at(q, (u16_t)(start + i)); + u8_t b = ((const u8_t *)s2)[i]; + if (a != b) { + return (u16_t)LWIP_MIN(i + 1, 0xFFFF); + } + } + return 0; +} + +/** + * @ingroup pbuf + * Find occurrence of mem (with length mem_len) in pbuf p, starting at offset + * start_offset. + * + * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as + * return value 'not found' + * @param mem search for the contents of this buffer + * @param mem_len length of 'mem' + * @param start_offset offset into p at which to start searching + * @return 0xFFFF if substr was not found in p or the index where it was found + */ +u16_t +pbuf_memfind(const struct pbuf *p, const void *mem, u16_t mem_len, u16_t start_offset) +{ + u16_t i; + u16_t max_cmp_start = (u16_t)(p->tot_len - mem_len); + if (p->tot_len >= mem_len + start_offset) { + for (i = start_offset; i <= max_cmp_start; i++) { + u16_t plus = pbuf_memcmp(p, i, mem, mem_len); + if (plus == 0) { + return i; + } + } + } + return 0xFFFF; +} + +/** + * Find occurrence of substr with length substr_len in pbuf p, start at offset + * start_offset + * WARNING: in contrast to strstr(), this one does not stop at the first \0 in + * the pbuf/source string! + * + * @param p pbuf to search, maximum length is 0xFFFE since 0xFFFF is used as + * return value 'not found' + * @param substr string to search for in p, maximum length is 0xFFFE + * @return 0xFFFF if substr was not found in p or the index where it was found + */ +u16_t +pbuf_strstr(const struct pbuf *p, const char *substr) +{ + size_t substr_len; + if ((substr == NULL) || (substr[0] == 0) || (p->tot_len == 0xFFFF)) { + return 0xFFFF; + } + substr_len = strlen(substr); + if (substr_len >= 0xFFFF) { + return 0xFFFF; + } + return pbuf_memfind(p, substr, (u16_t)substr_len, 0); +} diff --git a/Middlewares/Third_Party/LwIP/src/core/raw.c b/Middlewares/Third_Party/LwIP/src/core/raw.c new file mode 100644 index 0000000..3b34544 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/raw.c @@ -0,0 +1,671 @@ +/** + * @file + * Implementation of raw protocol PCBs for low-level handling of + * different types of protocols besides (or overriding) those + * already available in lwIP.\n + * See also @ref raw_raw + * + * @defgroup raw_raw RAW + * @ingroup callbackstyle_api + * Implementation of raw protocol PCBs for low-level handling of + * different types of protocols besides (or overriding) those + * already available in lwIP.\n + * @see @ref api + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/raw.h" +#include "lwip/priv/raw_priv.h" +#include "lwip/stats.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/inet_chksum.h" + +#include + +/** The list of RAW PCBs */ +static struct raw_pcb *raw_pcbs; + +static u8_t +raw_input_local_match(struct raw_pcb *pcb, u8_t broadcast) +{ + LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */ + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + return 0; + } + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: PCBs listening to any IP type also listen to any IP address */ + if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { +#if IP_SOF_BROADCAST_RECV + if ((broadcast != 0) && !ip_get_option(pcb, SOF_BROADCAST)) { + return 0; + } +#endif /* IP_SOF_BROADCAST_RECV */ + return 1; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + /* Only need to check PCB if incoming IP version matches PCB IP version */ + if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) { +#if LWIP_IPV4 + /* Special case: IPv4 broadcast: receive all broadcasts + * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */ + if (broadcast != 0) { +#if IP_SOF_BROADCAST_RECV + if (ip_get_option(pcb, SOF_BROADCAST)) +#endif /* IP_SOF_BROADCAST_RECV */ + { + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip))) { + return 1; + } + } + } else +#endif /* LWIP_IPV4 */ + /* Handle IPv4 and IPv6: catch all or exact match */ + if (ip_addr_isany(&pcb->local_ip) || + ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + return 1; + } + } + + return 0; +} + +/** + * Determine if in incoming IP packet is covered by a RAW PCB + * and if so, pass it to a user-provided receive callback function. + * + * Given an incoming IP datagram (as a chain of pbufs) this function + * finds a corresponding RAW PCB and calls the corresponding receive + * callback function. + * + * @param p pbuf to be demultiplexed to a RAW PCB. + * @param inp network interface on which the datagram was received. + * @return - 1 if the packet has been eaten by a RAW PCB receive + * callback function. The caller MAY NOT not reference the + * packet any longer, and MAY NOT call pbuf_free(). + * @return - 0 if packet is not eaten (pbuf is still referenced by the + * caller). + * + */ +raw_input_state_t +raw_input(struct pbuf *p, struct netif *inp) +{ + struct raw_pcb *pcb, *prev; + s16_t proto; + raw_input_state_t ret = RAW_INPUT_NONE; + u8_t broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()); + + LWIP_UNUSED_ARG(inp); + +#if LWIP_IPV6 +#if LWIP_IPV4 + if (IP_HDR_GET_VERSION(p->payload) == 6) +#endif /* LWIP_IPV4 */ + { + struct ip6_hdr *ip6hdr = (struct ip6_hdr *)p->payload; + proto = IP6H_NEXTH(ip6hdr); + } +#if LWIP_IPV4 + else +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + { + proto = IPH_PROTO((struct ip_hdr *)p->payload); + } +#endif /* LWIP_IPV4 */ + + prev = NULL; + pcb = raw_pcbs; + /* loop through all raw pcbs until the packet is eaten by one */ + /* this allows multiple pcbs to match against the packet by design */ + while (pcb != NULL) { + if ((pcb->protocol == proto) && raw_input_local_match(pcb, broadcast) && + (((pcb->flags & RAW_FLAGS_CONNECTED) == 0) || + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) { + /* receive callback function available? */ + if (pcb->recv != NULL) { + u8_t eaten; +#ifndef LWIP_NOASSERT + void *old_payload = p->payload; +#endif + ret = RAW_INPUT_DELIVERED; + /* the receive callback function did not eat the packet? */ + eaten = pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr()); + if (eaten != 0) { + /* receive function ate the packet */ + p = NULL; + if (prev != NULL) { + /* move the pcb to the front of raw_pcbs so that is + found faster next time */ + prev->next = pcb->next; + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + return RAW_INPUT_EATEN; + } else { + /* sanity-check that the receive callback did not alter the pbuf */ + LWIP_ASSERT("raw pcb recv callback altered pbuf payload pointer without eating packet", + p->payload == old_payload); + } + } + /* no receive callback function was set for this raw PCB */ + } + /* drop the packet */ + prev = pcb; + pcb = pcb->next; + } + return ret; +} + +/** + * @ingroup raw_raw + * Bind a RAW PCB. + * + * @param pcb RAW PCB to be bound with a local address ipaddr. + * @param ipaddr local IP address to bind with. Use IP4_ADDR_ANY to + * bind to all local interfaces. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occurred. + * - ERR_USE. The specified IP address is already bound to by + * another RAW PCB. + * + * @see raw_disconnect() + */ +err_t +raw_bind(struct raw_pcb *pcb, const ip_addr_t *ipaddr) +{ + LWIP_ASSERT_CORE_LOCKED(); + if ((pcb == NULL) || (ipaddr == NULL)) { + return ERR_VAL; + } + ip_addr_set_ipaddr(&pcb->local_ip, ipaddr); +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + /* If the given IP address should have a zone but doesn't, assign one now. + * This is legacy support: scope-aware callers should always provide properly + * zoned source addresses. */ + if (IP_IS_V6(&pcb->local_ip) && + ip6_addr_lacks_zone(ip_2_ip6(&pcb->local_ip), IP6_UNKNOWN)) { + ip6_addr_select_zone(ip_2_ip6(&pcb->local_ip), ip_2_ip6(&pcb->local_ip)); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + return ERR_OK; +} + +/** + * @ingroup raw_raw + * Bind an RAW PCB to a specific netif. + * After calling this function, all packets received via this PCB + * are guaranteed to have come in via the specified netif, and all + * outgoing packets will go out via the specified netif. + * + * @param pcb RAW PCB to be bound with netif. + * @param netif netif to bind to. Can be NULL. + * + * @see raw_disconnect() + */ +void +raw_bind_netif(struct raw_pcb *pcb, const struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + if (netif != NULL) { + pcb->netif_idx = netif_get_index(netif); + } else { + pcb->netif_idx = NETIF_NO_INDEX; + } +} + +/** + * @ingroup raw_raw + * Connect an RAW PCB. This function is required by upper layers + * of lwip. Using the raw api you could use raw_sendto() instead + * + * This will associate the RAW PCB with the remote address. + * + * @param pcb RAW PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * + * @return lwIP error code + * + * @see raw_disconnect() and raw_sendto() + */ +err_t +raw_connect(struct raw_pcb *pcb, const ip_addr_t *ipaddr) +{ + LWIP_ASSERT_CORE_LOCKED(); + if ((pcb == NULL) || (ipaddr == NULL)) { + return ERR_VAL; + } + ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr); +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + /* If the given IP address should have a zone but doesn't, assign one now, + * using the bound address to make a more informed decision when possible. */ + if (IP_IS_V6(&pcb->remote_ip) && + ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) { + ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip)); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + raw_set_flags(pcb, RAW_FLAGS_CONNECTED); + return ERR_OK; +} + +/** + * @ingroup raw_raw + * Disconnect a RAW PCB. + * + * @param pcb the raw pcb to disconnect. + */ +void +raw_disconnect(struct raw_pcb *pcb) +{ + LWIP_ASSERT_CORE_LOCKED(); + /* reset remote address association */ +#if LWIP_IPV4 && LWIP_IPV6 + if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { + ip_addr_copy(pcb->remote_ip, *IP_ANY_TYPE); + } else { +#endif + ip_addr_set_any(IP_IS_V6_VAL(pcb->remote_ip), &pcb->remote_ip); +#if LWIP_IPV4 && LWIP_IPV6 + } +#endif + pcb->netif_idx = NETIF_NO_INDEX; + /* mark PCB as unconnected */ + raw_clear_flags(pcb, RAW_FLAGS_CONNECTED); +} + +/** + * @ingroup raw_raw + * Set the callback function for received packets that match the + * raw PCB's protocol and binding. + * + * The callback function MUST either + * - eat the packet by calling pbuf_free() and returning non-zero. The + * packet will not be passed to other raw PCBs or other protocol layers. + * - not free the packet, and return zero. The packet will be matched + * against further PCBs and/or forwarded to another protocol layers. + */ +void +raw_recv(struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg) +{ + LWIP_ASSERT_CORE_LOCKED(); + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * @ingroup raw_raw + * Send the raw IP packet to the given address. An IP header will be prepended + * to the packet, unless the RAW_FLAGS_HDRINCL flag is set on the PCB. In that + * case, the packet must include an IP header, which will then be sent as is. + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * @param ipaddr the destination address of the IP packet + * + */ +err_t +raw_sendto(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr) +{ + struct netif *netif; + const ip_addr_t *src_ip; + + if ((pcb == NULL) || (ipaddr == NULL) || !IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr)) { + return ERR_VAL; + } + + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_sendto\n")); + + if (pcb->netif_idx != NETIF_NO_INDEX) { + netif = netif_get_by_index(pcb->netif_idx); + } else { +#if LWIP_MULTICAST_TX_OPTIONS + netif = NULL; + if (ip_addr_ismulticast(ipaddr)) { + /* For multicast-destined packets, use the user-provided interface index to + * determine the outgoing interface, if an interface index is set and a + * matching netif can be found. Otherwise, fall back to regular routing. */ + netif = netif_get_by_index(pcb->mcast_ifindex); + } + + if (netif == NULL) +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + { + netif = ip_route(&pcb->local_ip, ipaddr); + } + } + + if (netif == NULL) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: No route to ")); + ip_addr_debug_print(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ipaddr); + return ERR_RTE; + } + + if (ip_addr_isany(&pcb->local_ip) || ip_addr_ismulticast(&pcb->local_ip)) { + /* use outgoing network interface IP address as source address */ + src_ip = ip_netif_get_local_ip(netif, ipaddr); +#if LWIP_IPV6 + if (src_ip == NULL) { + return ERR_RTE; + } +#endif /* LWIP_IPV6 */ + } else { + /* use RAW PCB local IP address as source address */ + src_ip = &pcb->local_ip; + } + + return raw_sendto_if_src(pcb, p, ipaddr, netif, src_ip); +} + +/** + * @ingroup raw_raw + * Send the raw IP packet to the given address, using a particular outgoing + * netif and source IP address. An IP header will be prepended to the packet, + * unless the RAW_FLAGS_HDRINCL flag is set on the PCB. In that case, the + * packet must include an IP header, which will then be sent as is. + * + * @param pcb RAW PCB used to send the data + * @param p chain of pbufs to be sent + * @param dst_ip destination IP address + * @param netif the netif used for sending + * @param src_ip source IP address + */ +err_t +raw_sendto_if_src(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, + struct netif *netif, const ip_addr_t *src_ip) +{ + err_t err; + struct pbuf *q; /* q will be sent down the stack */ + u16_t header_size; + u8_t ttl; + + LWIP_ASSERT_CORE_LOCKED(); + + if ((pcb == NULL) || (dst_ip == NULL) || (netif == NULL) || (src_ip == NULL) || + !IP_ADDR_PCB_VERSION_MATCH(pcb, src_ip) || !IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) { + return ERR_VAL; + } + + header_size = ( +#if LWIP_IPV4 && LWIP_IPV6 + IP_IS_V6(dst_ip) ? IP6_HLEN : IP_HLEN); +#elif LWIP_IPV4 + IP_HLEN); +#else + IP6_HLEN); +#endif + + /* Handle the HDRINCL option as an exception: none of the code below applies + * to this case, and sending the packet needs to be done differently too. */ + if (pcb->flags & RAW_FLAGS_HDRINCL) { + /* A full header *must* be present in the first pbuf of the chain, as the + * output routines may access its fields directly. */ + if (p->len < header_size) { + return ERR_VAL; + } + /* @todo multicast loop support, if at all desired for this scenario.. */ + NETIF_SET_HINTS(netif, &pcb->netif_hints); + err = ip_output_if_hdrincl(p, src_ip, dst_ip, netif); + NETIF_RESET_HINTS(netif); + return err; + } + + /* packet too large to add an IP header without causing an overflow? */ + if ((u16_t)(p->tot_len + header_size) < p->tot_len) { + return ERR_MEM; + } + /* not enough space to add an IP header to first pbuf in given p chain? */ + if (pbuf_add_header(p, header_size)) { + /* allocate header in new pbuf */ + q = pbuf_alloc(PBUF_IP, 0, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("raw_sendto: could not allocate header\n")); + return ERR_MEM; + } + if (p->tot_len != 0) { + /* chain header q in front of given pbuf p */ + pbuf_chain(q, p); + } + /* { first pbuf q points to header pbuf } */ + LWIP_DEBUGF(RAW_DEBUG, ("raw_sendto: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* first pbuf q equals given pbuf */ + q = p; + if (pbuf_remove_header(q, header_size)) { + LWIP_ASSERT("Can't restore header we just removed!", 0); + return ERR_MEM; + } + } + +#if IP_SOF_BROADCAST + if (IP_IS_V4(dst_ip)) { + /* broadcast filter? */ + if (!ip_get_option(pcb, SOF_BROADCAST) && ip_addr_isbroadcast(dst_ip, netif)) { + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_LEVEL_WARNING, ("raw_sendto: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); + /* free any temporary header pbuf allocated by pbuf_header() */ + if (q != p) { + pbuf_free(q); + } + return ERR_VAL; + } + } +#endif /* IP_SOF_BROADCAST */ + + /* Multicast Loop? */ +#if LWIP_MULTICAST_TX_OPTIONS + if (((pcb->flags & RAW_FLAGS_MULTICAST_LOOP) != 0) && ip_addr_ismulticast(dst_ip)) { + q->flags |= PBUF_FLAG_MCASTLOOP; + } +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + +#if LWIP_IPV6 + /* If requested, based on the IPV6_CHECKSUM socket option per RFC3542, + compute the checksum and update the checksum in the payload. */ + if (IP_IS_V6(dst_ip) && pcb->chksum_reqd) { + u16_t chksum = ip6_chksum_pseudo(p, pcb->protocol, p->tot_len, ip_2_ip6(src_ip), ip_2_ip6(dst_ip)); + LWIP_ASSERT("Checksum must fit into first pbuf", p->len >= (pcb->chksum_offset + 2)); + SMEMCPY(((u8_t *)p->payload) + pcb->chksum_offset, &chksum, sizeof(u16_t)); + } +#endif + + /* Determine TTL to use */ +#if LWIP_MULTICAST_TX_OPTIONS + ttl = (ip_addr_ismulticast(dst_ip) ? raw_get_multicast_ttl(pcb) : pcb->ttl); +#else /* LWIP_MULTICAST_TX_OPTIONS */ + ttl = pcb->ttl; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + + NETIF_SET_HINTS(netif, &pcb->netif_hints); + err = ip_output_if(q, src_ip, dst_ip, ttl, pcb->tos, pcb->protocol, netif); + NETIF_RESET_HINTS(netif); + + /* did we chain a header earlier? */ + if (q != p) { + /* free the header */ + pbuf_free(q); + } + return err; +} + +/** + * @ingroup raw_raw + * Send the raw IP packet to the address given by raw_connect() + * + * @param pcb the raw pcb which to send + * @param p the IP payload to send + * + */ +err_t +raw_send(struct raw_pcb *pcb, struct pbuf *p) +{ + return raw_sendto(pcb, p, &pcb->remote_ip); +} + +/** + * @ingroup raw_raw + * Remove an RAW PCB. + * + * @param pcb RAW PCB to be removed. The PCB is removed from the list of + * RAW PCB's and the data structure is freed from memory. + * + * @see raw_new() + */ +void +raw_remove(struct raw_pcb *pcb) +{ + struct raw_pcb *pcb2; + LWIP_ASSERT_CORE_LOCKED(); + /* pcb to be removed is first in list? */ + if (raw_pcbs == pcb) { + /* make list start at 2nd pcb */ + raw_pcbs = raw_pcbs->next; + /* pcb not 1st in list */ + } else { + for (pcb2 = raw_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in raw_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + break; + } + } + } + memp_free(MEMP_RAW_PCB, pcb); +} + +/** + * @ingroup raw_raw + * Create a RAW PCB. + * + * @return The RAW PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @param proto the protocol number of the IPs payload (e.g. IP_PROTO_ICMP) + * + * @see raw_remove() + */ +struct raw_pcb * +raw_new(u8_t proto) +{ + struct raw_pcb *pcb; + + LWIP_DEBUGF(RAW_DEBUG | LWIP_DBG_TRACE, ("raw_new\n")); + LWIP_ASSERT_CORE_LOCKED(); + + pcb = (struct raw_pcb *)memp_malloc(MEMP_RAW_PCB); + /* could allocate RAW PCB? */ + if (pcb != NULL) { + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct raw_pcb)); + pcb->protocol = proto; + pcb->ttl = RAW_TTL; +#if LWIP_MULTICAST_TX_OPTIONS + raw_set_multicast_ttl(pcb, RAW_TTL); +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + pcb->next = raw_pcbs; + raw_pcbs = pcb; + } + return pcb; +} + +/** + * @ingroup raw_raw + * Create a RAW PCB for specific IP type. + * + * @return The RAW PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @param type IP address type, see @ref lwip_ip_addr_type definitions. + * If you want to listen to IPv4 and IPv6 (dual-stack) packets, + * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE. + * @param proto the protocol number (next header) of the IPv6 packet payload + * (e.g. IP6_NEXTH_ICMP6) + * + * @see raw_remove() + */ +struct raw_pcb * +raw_new_ip_type(u8_t type, u8_t proto) +{ + struct raw_pcb *pcb; + LWIP_ASSERT_CORE_LOCKED(); + pcb = raw_new(proto); +#if LWIP_IPV4 && LWIP_IPV6 + if (pcb != NULL) { + IP_SET_TYPE_VAL(pcb->local_ip, type); + IP_SET_TYPE_VAL(pcb->remote_ip, type); + } +#else /* LWIP_IPV4 && LWIP_IPV6 */ + LWIP_UNUSED_ARG(type); +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + return pcb; +} + +/** This function is called from netif.c when address is changed + * + * @param old_addr IP address of the netif before change + * @param new_addr IP address of the netif after change + */ +void raw_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + struct raw_pcb *rpcb; + + if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) { + for (rpcb = raw_pcbs; rpcb != NULL; rpcb = rpcb->next) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&rpcb->local_ip, old_addr)) { + /* The PCB is bound to the old ipaddr and + * is set to bound to the new one instead */ + ip_addr_copy(rpcb->local_ip, *new_addr); + } + } + } +} + +#endif /* LWIP_RAW */ diff --git a/Middlewares/Third_Party/LwIP/src/core/stats.c b/Middlewares/Third_Party/LwIP/src/core/stats.c new file mode 100644 index 0000000..34e9b27 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/stats.c @@ -0,0 +1,169 @@ +/** + * @file + * Statistics module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_STATS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/debug.h" + +#include + +struct stats_ lwip_stats; + +void +stats_init(void) +{ +#ifdef LWIP_DEBUG +#if MEM_STATS + lwip_stats.mem.name = "MEM"; +#endif /* MEM_STATS */ +#endif /* LWIP_DEBUG */ +} + +#if LWIP_STATS_DISPLAY +void +stats_display_proto(struct stats_proto *proto, const char *name) +{ + LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); + LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", proto->xmit)); + LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", proto->recv)); + LWIP_PLATFORM_DIAG(("fw: %"STAT_COUNTER_F"\n\t", proto->fw)); + LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", proto->drop)); + LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", proto->chkerr)); + LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", proto->lenerr)); + LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", proto->memerr)); + LWIP_PLATFORM_DIAG(("rterr: %"STAT_COUNTER_F"\n\t", proto->rterr)); + LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", proto->proterr)); + LWIP_PLATFORM_DIAG(("opterr: %"STAT_COUNTER_F"\n\t", proto->opterr)); + LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n\t", proto->err)); + LWIP_PLATFORM_DIAG(("cachehit: %"STAT_COUNTER_F"\n", proto->cachehit)); +} + +#if IGMP_STATS || MLD6_STATS +void +stats_display_igmp(struct stats_igmp *igmp, const char *name) +{ + LWIP_PLATFORM_DIAG(("\n%s\n\t", name)); + LWIP_PLATFORM_DIAG(("xmit: %"STAT_COUNTER_F"\n\t", igmp->xmit)); + LWIP_PLATFORM_DIAG(("recv: %"STAT_COUNTER_F"\n\t", igmp->recv)); + LWIP_PLATFORM_DIAG(("drop: %"STAT_COUNTER_F"\n\t", igmp->drop)); + LWIP_PLATFORM_DIAG(("chkerr: %"STAT_COUNTER_F"\n\t", igmp->chkerr)); + LWIP_PLATFORM_DIAG(("lenerr: %"STAT_COUNTER_F"\n\t", igmp->lenerr)); + LWIP_PLATFORM_DIAG(("memerr: %"STAT_COUNTER_F"\n\t", igmp->memerr)); + LWIP_PLATFORM_DIAG(("proterr: %"STAT_COUNTER_F"\n\t", igmp->proterr)); + LWIP_PLATFORM_DIAG(("rx_v1: %"STAT_COUNTER_F"\n\t", igmp->rx_v1)); + LWIP_PLATFORM_DIAG(("rx_group: %"STAT_COUNTER_F"\n\t", igmp->rx_group)); + LWIP_PLATFORM_DIAG(("rx_general: %"STAT_COUNTER_F"\n\t", igmp->rx_general)); + LWIP_PLATFORM_DIAG(("rx_report: %"STAT_COUNTER_F"\n\t", igmp->rx_report)); + LWIP_PLATFORM_DIAG(("tx_join: %"STAT_COUNTER_F"\n\t", igmp->tx_join)); + LWIP_PLATFORM_DIAG(("tx_leave: %"STAT_COUNTER_F"\n\t", igmp->tx_leave)); + LWIP_PLATFORM_DIAG(("tx_report: %"STAT_COUNTER_F"\n", igmp->tx_report)); +} +#endif /* IGMP_STATS || MLD6_STATS */ + +#if MEM_STATS || MEMP_STATS +void +stats_display_mem(struct stats_mem *mem, const char *name) +{ + LWIP_PLATFORM_DIAG(("\nMEM %s\n\t", name)); + LWIP_PLATFORM_DIAG(("avail: %"MEM_SIZE_F"\n\t", mem->avail)); + LWIP_PLATFORM_DIAG(("used: %"MEM_SIZE_F"\n\t", mem->used)); + LWIP_PLATFORM_DIAG(("max: %"MEM_SIZE_F"\n\t", mem->max)); + LWIP_PLATFORM_DIAG(("err: %"STAT_COUNTER_F"\n", mem->err)); +} + +#if MEMP_STATS +void +stats_display_memp(struct stats_mem *mem, int idx) +{ + if (idx < MEMP_MAX) { + stats_display_mem(mem, mem->name); + } +} +#endif /* MEMP_STATS */ +#endif /* MEM_STATS || MEMP_STATS */ + +#if SYS_STATS +void +stats_display_sys(struct stats_sys *sys) +{ + LWIP_PLATFORM_DIAG(("\nSYS\n\t")); + LWIP_PLATFORM_DIAG(("sem.used: %"STAT_COUNTER_F"\n\t", sys->sem.used)); + LWIP_PLATFORM_DIAG(("sem.max: %"STAT_COUNTER_F"\n\t", sys->sem.max)); + LWIP_PLATFORM_DIAG(("sem.err: %"STAT_COUNTER_F"\n\t", sys->sem.err)); + LWIP_PLATFORM_DIAG(("mutex.used: %"STAT_COUNTER_F"\n\t", sys->mutex.used)); + LWIP_PLATFORM_DIAG(("mutex.max: %"STAT_COUNTER_F"\n\t", sys->mutex.max)); + LWIP_PLATFORM_DIAG(("mutex.err: %"STAT_COUNTER_F"\n\t", sys->mutex.err)); + LWIP_PLATFORM_DIAG(("mbox.used: %"STAT_COUNTER_F"\n\t", sys->mbox.used)); + LWIP_PLATFORM_DIAG(("mbox.max: %"STAT_COUNTER_F"\n\t", sys->mbox.max)); + LWIP_PLATFORM_DIAG(("mbox.err: %"STAT_COUNTER_F"\n", sys->mbox.err)); +} +#endif /* SYS_STATS */ + +void +stats_display(void) +{ + s16_t i; + + LINK_STATS_DISPLAY(); + ETHARP_STATS_DISPLAY(); + IPFRAG_STATS_DISPLAY(); + IP6_FRAG_STATS_DISPLAY(); + IP_STATS_DISPLAY(); + ND6_STATS_DISPLAY(); + IP6_STATS_DISPLAY(); + IGMP_STATS_DISPLAY(); + MLD6_STATS_DISPLAY(); + ICMP_STATS_DISPLAY(); + ICMP6_STATS_DISPLAY(); + UDP_STATS_DISPLAY(); + TCP_STATS_DISPLAY(); + MEM_STATS_DISPLAY(); + for (i = 0; i < MEMP_MAX; i++) { + MEMP_STATS_DISPLAY(i); + } + SYS_STATS_DISPLAY(); +} +#endif /* LWIP_STATS_DISPLAY */ + +#endif /* LWIP_STATS */ + diff --git a/Middlewares/Third_Party/LwIP/src/core/sys.c b/Middlewares/Third_Party/LwIP/src/core/sys.c new file mode 100644 index 0000000..5f08352 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/sys.c @@ -0,0 +1,148 @@ +/** + * @file + * lwIP Operating System abstraction + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/** + * @defgroup sys_layer Porting (system abstraction layer) + * @ingroup lwip + * + * @defgroup sys_os OS abstraction layer + * @ingroup sys_layer + * No need to implement functions in this section in NO_SYS mode. + * The OS-specific code should be implemented in arch/sys_arch.h + * and sys_arch.c of your port. + * + * The operating system emulation layer provides a common interface + * between the lwIP code and the underlying operating system kernel. The + * general idea is that porting lwIP to new architectures requires only + * small changes to a few header files and a new sys_arch + * implementation. It is also possible to do a sys_arch implementation + * that does not rely on any underlying operating system. + * + * The sys_arch provides semaphores, mailboxes and mutexes to lwIP. For the full + * lwIP functionality, multiple threads support can be implemented in the + * sys_arch, but this is not required for the basic lwIP + * functionality. Timer scheduling is implemented in lwIP, but can be implemented + * by the sys_arch port (LWIP_TIMERS_CUSTOM==1). + * + * In addition to the source file providing the functionality of sys_arch, + * the OS emulation layer must provide several header files defining + * macros used throughout lwip. The files required and the macros they + * must define are listed below the sys_arch description. + * + * Since lwIP 1.4.0, semaphore, mutexes and mailbox functions are prototyped in a way that + * allows both using pointers or actual OS structures to be used. This way, memory + * required for such types can be either allocated in place (globally or on the + * stack) or on the heap (allocated internally in the "*_new()" functions). + * + * Note: + * ----- + * Be careful with using mem_malloc() in sys_arch. When malloc() refers to + * mem_malloc() you can run into a circular function call problem. In mem.c + * mem_init() tries to allocate a semaphore using mem_malloc, which of course + * can't be performed when sys_arch uses mem_malloc. + * + * @defgroup sys_sem Semaphores + * @ingroup sys_os + * Semaphores can be either counting or binary - lwIP works with both + * kinds. + * Semaphores are represented by the type "sys_sem_t" which is typedef'd + * in the sys_arch.h file. Mailboxes are equivalently represented by the + * type "sys_mbox_t". Mutexes are represented by the type "sys_mutex_t". + * lwIP does not place any restrictions on how these types are represented + * internally. + * + * @defgroup sys_mutex Mutexes + * @ingroup sys_os + * Mutexes are recommended to correctly handle priority inversion, + * especially if you use LWIP_CORE_LOCKING . + * + * @defgroup sys_mbox Mailboxes + * @ingroup sys_os + * Mailboxes should be implemented as a queue which allows multiple messages + * to be posted (implementing as a rendez-vous point where only one message can be + * posted at a time can have a highly negative impact on performance). A message + * in a mailbox is just a pointer, nothing more. + * + * @defgroup sys_time Time + * @ingroup sys_layer + * + * @defgroup sys_prot Critical sections + * @ingroup sys_layer + * Used to protect short regions of code against concurrent access. + * - Your system is a bare-metal system (probably with an RTOS) + * and interrupts are under your control: + * Implement this as LockInterrupts() / UnlockInterrupts() + * - Your system uses an RTOS with deferred interrupt handling from a + * worker thread: Implement as a global mutex or lock/unlock scheduler + * - Your system uses a high-level OS with e.g. POSIX signals: + * Implement as a global mutex + * + * @defgroup sys_misc Misc + * @ingroup sys_os + */ + +#include "lwip/opt.h" + +#include "lwip/sys.h" + +/* Most of the functions defined in sys.h must be implemented in the + * architecture-dependent file sys_arch.c */ + +#if !NO_SYS + +#ifndef sys_msleep +/** + * Sleep for some ms. Timeouts are NOT processed while sleeping. + * + * @param ms number of milliseconds to sleep + */ +void +sys_msleep(u32_t ms) +{ + if (ms > 0) { + sys_sem_t delaysem; + err_t err = sys_sem_new(&delaysem, 0); + if (err == ERR_OK) { + sys_arch_sem_wait(&delaysem, ms); + sys_sem_free(&delaysem); + } + } +} +#endif /* sys_msleep */ + +#endif /* !NO_SYS */ diff --git a/Middlewares/Third_Party/LwIP/src/core/tcp.c b/Middlewares/Third_Party/LwIP/src/core/tcp.c new file mode 100644 index 0000000..1ad705e --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/tcp.c @@ -0,0 +1,2686 @@ +/** + * @file + * Transmission Control Protocol for IP + * See also @ref tcp_raw + * + * @defgroup tcp_raw TCP + * @ingroup callbackstyle_api + * Transmission Control Protocol for IP\n + * @see @ref api + * + * Common functions for the TCP implementation, such as functions + * for manipulating the data structures and the TCP timer functions. TCP functions + * related to input and output is found in tcp_in.c and tcp_out.c respectively.\n + * + * TCP connection setup + * -------------------- + * The functions used for setting up connections is similar to that of + * the sequential API and of the BSD socket API. A new TCP connection + * identifier (i.e., a protocol control block - PCB) is created with the + * tcp_new() function. This PCB can then be either set to listen for new + * incoming connections or be explicitly connected to another host. + * - tcp_new() + * - tcp_bind() + * - tcp_listen() and tcp_listen_with_backlog() + * - tcp_accept() + * - tcp_connect() + * + * Sending TCP data + * ---------------- + * TCP data is sent by enqueueing the data with a call to tcp_write() and + * triggering to send by calling tcp_output(). When the data is successfully + * transmitted to the remote host, the application will be notified with a + * call to a specified callback function. + * - tcp_write() + * - tcp_output() + * - tcp_sent() + * + * Receiving TCP data + * ------------------ + * TCP data reception is callback based - an application specified + * callback function is called when new data arrives. When the + * application has taken the data, it has to call the tcp_recved() + * function to indicate that TCP can advertise increase the receive + * window. + * - tcp_recv() + * - tcp_recved() + * + * Application polling + * ------------------- + * When a connection is idle (i.e., no data is either transmitted or + * received), lwIP will repeatedly poll the application by calling a + * specified callback function. This can be used either as a watchdog + * timer for killing connections that have stayed idle for too long, or + * as a method of waiting for memory to become available. For instance, + * if a call to tcp_write() has failed because memory wasn't available, + * the application may use the polling functionality to call tcp_write() + * again when the connection has been idle for a while. + * - tcp_poll() + * + * Closing and aborting connections + * -------------------------------- + * - tcp_close() + * - tcp_abort() + * - tcp_err() + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/tcp.h" +#include "lwip/priv/tcp_priv.h" +#include "lwip/debug.h" +#include "lwip/stats.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/nd6.h" + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +#ifndef TCP_LOCAL_PORT_RANGE_START +/* From http://www.iana.org/assignments/port-numbers: + "The Dynamic and/or Private Ports are those from 49152 through 65535" */ +#define TCP_LOCAL_PORT_RANGE_START 0xc000 +#define TCP_LOCAL_PORT_RANGE_END 0xffff +#define TCP_ENSURE_LOCAL_PORT_RANGE(port) ((u16_t)(((port) & (u16_t)~TCP_LOCAL_PORT_RANGE_START) + TCP_LOCAL_PORT_RANGE_START)) +#endif + +#if LWIP_TCP_KEEPALIVE +#define TCP_KEEP_DUR(pcb) ((pcb)->keep_cnt * (pcb)->keep_intvl) +#define TCP_KEEP_INTVL(pcb) ((pcb)->keep_intvl) +#else /* LWIP_TCP_KEEPALIVE */ +#define TCP_KEEP_DUR(pcb) TCP_MAXIDLE +#define TCP_KEEP_INTVL(pcb) TCP_KEEPINTVL_DEFAULT +#endif /* LWIP_TCP_KEEPALIVE */ + +/* As initial send MSS, we use TCP_MSS but limit it to 536. */ +#if TCP_MSS > 536 +#define INITIAL_MSS 536 +#else +#define INITIAL_MSS TCP_MSS +#endif + +static const char *const tcp_state_str[] = { + "CLOSED", + "LISTEN", + "SYN_SENT", + "SYN_RCVD", + "ESTABLISHED", + "FIN_WAIT_1", + "FIN_WAIT_2", + "CLOSE_WAIT", + "CLOSING", + "LAST_ACK", + "TIME_WAIT" +}; + +/* last local TCP port */ +static u16_t tcp_port = TCP_LOCAL_PORT_RANGE_START; + +/* Incremented every coarse grained timer shot (typically every 500 ms). */ +u32_t tcp_ticks; +static const u8_t tcp_backoff[13] = +{ 1, 2, 3, 4, 5, 6, 7, 7, 7, 7, 7, 7, 7}; +/* Times per slowtmr hits */ +static const u8_t tcp_persist_backoff[7] = { 3, 6, 12, 24, 48, 96, 120 }; + +/* The TCP PCB lists. */ + +/** List of all TCP PCBs bound but not yet (connected || listening) */ +struct tcp_pcb *tcp_bound_pcbs; +/** List of all TCP PCBs in LISTEN state */ +union tcp_listen_pcbs_t tcp_listen_pcbs; +/** List of all TCP PCBs that are in a state in which + * they accept or send data. */ +struct tcp_pcb *tcp_active_pcbs; +/** List of all TCP PCBs in TIME-WAIT state */ +struct tcp_pcb *tcp_tw_pcbs; + +/** An array with all (non-temporary) PCB lists, mainly used for smaller code size */ +struct tcp_pcb **const tcp_pcb_lists[] = {&tcp_listen_pcbs.pcbs, &tcp_bound_pcbs, + &tcp_active_pcbs, &tcp_tw_pcbs +}; + +u8_t tcp_active_pcbs_changed; + +/** Timer counter to handle calling slow-timer from tcp_tmr() */ +static u8_t tcp_timer; +static u8_t tcp_timer_ctr; +static u16_t tcp_new_port(void); + +static err_t tcp_close_shutdown_fin(struct tcp_pcb *pcb); +#if LWIP_TCP_PCB_NUM_EXT_ARGS +static void tcp_ext_arg_invoke_callbacks_destroyed(struct tcp_pcb_ext_args *ext_args); +#endif + +/** + * Initialize this module. + */ +void +tcp_init(void) +{ +#ifdef LWIP_RAND + tcp_port = TCP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); +#endif /* LWIP_RAND */ +} + +/** Free a tcp pcb */ +void +tcp_free(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_free: LISTEN", pcb->state != LISTEN); +#if LWIP_TCP_PCB_NUM_EXT_ARGS + tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); +#endif + memp_free(MEMP_TCP_PCB, pcb); +} + +/** Free a tcp listen pcb */ +static void +tcp_free_listen(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_free_listen: !LISTEN", pcb->state != LISTEN); +#if LWIP_TCP_PCB_NUM_EXT_ARGS + tcp_ext_arg_invoke_callbacks_destroyed(pcb->ext_args); +#endif + memp_free(MEMP_TCP_PCB_LISTEN, pcb); +} + +/** + * Called periodically to dispatch TCP timers. + */ +void +tcp_tmr(void) +{ + /* Call tcp_fasttmr() every 250 ms */ + tcp_fasttmr(); + + if (++tcp_timer & 1) { + /* Call tcp_slowtmr() every 500 ms, i.e., every other timer + tcp_tmr() is called. */ + tcp_slowtmr(); + } +} + +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG +/** Called when a listen pcb is closed. Iterates one pcb list and removes the + * closed listener pcb from pcb->listener if matching. + */ +static void +tcp_remove_listener(struct tcp_pcb *list, struct tcp_pcb_listen *lpcb) +{ + struct tcp_pcb *pcb; + + LWIP_ASSERT("tcp_remove_listener: invalid listener", lpcb != NULL); + + for (pcb = list; pcb != NULL; pcb = pcb->next) { + if (pcb->listener == lpcb) { + pcb->listener = NULL; + } + } +} +#endif + +/** Called when a listen pcb is closed. Iterates all pcb lists and removes the + * closed listener pcb from pcb->listener if matching. + */ +static void +tcp_listen_closed(struct tcp_pcb *pcb) +{ +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + size_t i; + LWIP_ASSERT("pcb != NULL", pcb != NULL); + LWIP_ASSERT("pcb->state == LISTEN", pcb->state == LISTEN); + for (i = 1; i < LWIP_ARRAYSIZE(tcp_pcb_lists); i++) { + tcp_remove_listener(*tcp_pcb_lists[i], (struct tcp_pcb_listen *)pcb); + } +#endif + LWIP_UNUSED_ARG(pcb); +} + +#if TCP_LISTEN_BACKLOG +/** @ingroup tcp_raw + * Delay accepting a connection in respect to the listen backlog: + * the number of outstanding connections is increased until + * tcp_backlog_accepted() is called. + * + * ATTENTION: the caller is responsible for calling tcp_backlog_accepted() + * or else the backlog feature will get out of sync! + * + * @param pcb the connection pcb which is not fully accepted yet + */ +void +tcp_backlog_delayed(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("pcb != NULL", pcb != NULL); + LWIP_ASSERT_CORE_LOCKED(); + if ((pcb->flags & TF_BACKLOGPEND) == 0) { + if (pcb->listener != NULL) { + pcb->listener->accepts_pending++; + LWIP_ASSERT("accepts_pending != 0", pcb->listener->accepts_pending != 0); + tcp_set_flags(pcb, TF_BACKLOGPEND); + } + } +} + +/** @ingroup tcp_raw + * A delayed-accept a connection is accepted (or closed/aborted): decreases + * the number of outstanding connections after calling tcp_backlog_delayed(). + * + * ATTENTION: the caller is responsible for calling tcp_backlog_accepted() + * or else the backlog feature will get out of sync! + * + * @param pcb the connection pcb which is now fully accepted (or closed/aborted) + */ +void +tcp_backlog_accepted(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("pcb != NULL", pcb != NULL); + LWIP_ASSERT_CORE_LOCKED(); + if ((pcb->flags & TF_BACKLOGPEND) != 0) { + if (pcb->listener != NULL) { + LWIP_ASSERT("accepts_pending != 0", pcb->listener->accepts_pending != 0); + pcb->listener->accepts_pending--; + tcp_clear_flags(pcb, TF_BACKLOGPEND); + } + } +} +#endif /* TCP_LISTEN_BACKLOG */ + +/** + * Closes the TX side of a connection held by the PCB. + * For tcp_close(), a RST is sent if the application didn't receive all data + * (tcp_recved() not called for all data passed to recv callback). + * + * Listening pcbs are freed and may not be referenced any more. + * Connection pcbs are freed if not yet connected and may not be referenced + * any more. If a connection is established (at least SYN received or in + * a closing state), the connection is closed, and put in a closing state. + * The pcb is then automatically freed in tcp_slowtmr(). It is therefore + * unsafe to reference it. + * + * @param pcb the tcp_pcb to close + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +static err_t +tcp_close_shutdown(struct tcp_pcb *pcb, u8_t rst_on_unacked_data) +{ + LWIP_ASSERT("tcp_close_shutdown: invalid pcb", pcb != NULL); + + if (rst_on_unacked_data && ((pcb->state == ESTABLISHED) || (pcb->state == CLOSE_WAIT))) { + if ((pcb->refused_data != NULL) || (pcb->rcv_wnd != TCP_WND_MAX(pcb))) { + /* Not all data received by application, send RST to tell the remote + side about this. */ + LWIP_ASSERT("pcb->flags & TF_RXCLOSED", pcb->flags & TF_RXCLOSED); + + /* don't call tcp_abort here: we must not deallocate the pcb since + that might not be expected when calling tcp_close */ + tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + pcb->local_port, pcb->remote_port); + + tcp_pcb_purge(pcb); + TCP_RMV_ACTIVE(pcb); + /* Deallocate the pcb since we already sent a RST for it */ + if (tcp_input_pcb == pcb) { + /* prevent using a deallocated pcb: free it from tcp_input later */ + tcp_trigger_input_pcb_close(); + } else { + tcp_free(pcb); + } + return ERR_OK; + } + } + + /* - states which free the pcb are handled here, + - states which send FIN and change state are handled in tcp_close_shutdown_fin() */ + switch (pcb->state) { + case CLOSED: + /* Closing a pcb in the CLOSED state might seem erroneous, + * however, it is in this state once allocated and as yet unused + * and the user needs some way to free it should the need arise. + * Calling tcp_close() with a pcb that has already been closed, (i.e. twice) + * or for a pcb that has been used and then entered the CLOSED state + * is erroneous, but this should never happen as the pcb has in those cases + * been freed, and so any remaining handles are bogus. */ + if (pcb->local_port != 0) { + TCP_RMV(&tcp_bound_pcbs, pcb); + } + tcp_free(pcb); + break; + case LISTEN: + tcp_listen_closed(pcb); + tcp_pcb_remove(&tcp_listen_pcbs.pcbs, pcb); + tcp_free_listen(pcb); + break; + case SYN_SENT: + TCP_PCB_REMOVE_ACTIVE(pcb); + tcp_free(pcb); + MIB2_STATS_INC(mib2.tcpattemptfails); + break; + default: + return tcp_close_shutdown_fin(pcb); + } + return ERR_OK; +} + +static err_t +tcp_close_shutdown_fin(struct tcp_pcb *pcb) +{ + err_t err; + LWIP_ASSERT("pcb != NULL", pcb != NULL); + + switch (pcb->state) { + case SYN_RCVD: + err = tcp_send_fin(pcb); + if (err == ERR_OK) { + tcp_backlog_accepted(pcb); + MIB2_STATS_INC(mib2.tcpattemptfails); + pcb->state = FIN_WAIT_1; + } + break; + case ESTABLISHED: + err = tcp_send_fin(pcb); + if (err == ERR_OK) { + MIB2_STATS_INC(mib2.tcpestabresets); + pcb->state = FIN_WAIT_1; + } + break; + case CLOSE_WAIT: + err = tcp_send_fin(pcb); + if (err == ERR_OK) { + MIB2_STATS_INC(mib2.tcpestabresets); + pcb->state = LAST_ACK; + } + break; + default: + /* Has already been closed, do nothing. */ + return ERR_OK; + } + + if (err == ERR_OK) { + /* To ensure all data has been sent when tcp_close returns, we have + to make sure tcp_output doesn't fail. + Since we don't really have to ensure all data has been sent when tcp_close + returns (unsent data is sent from tcp timer functions, also), we don't care + for the return value of tcp_output for now. */ + tcp_output(pcb); + } else if (err == ERR_MEM) { + /* Mark this pcb for closing. Closing is retried from tcp_tmr. */ + tcp_set_flags(pcb, TF_CLOSEPEND); + /* We have to return ERR_OK from here to indicate to the callers that this + pcb should not be used any more as it will be freed soon via tcp_tmr. + This is OK here since sending FIN does not guarantee a time frime for + actually freeing the pcb, either (it is left in closure states for + remote ACK or timeout) */ + return ERR_OK; + } + return err; +} + +/** + * @ingroup tcp_raw + * Closes the connection held by the PCB. + * + * Listening pcbs are freed and may not be referenced any more. + * Connection pcbs are freed if not yet connected and may not be referenced + * any more. If a connection is established (at least SYN received or in + * a closing state), the connection is closed, and put in a closing state. + * The pcb is then automatically freed in tcp_slowtmr(). It is therefore + * unsafe to reference it (unless an error is returned). + * + * The function may return ERR_MEM if no memory + * was available for closing the connection. If so, the application + * should wait and try again either by using the acknowledgment + * callback or the polling functionality. If the close succeeds, the + * function returns ERR_OK. + * + * @param pcb the tcp_pcb to close + * @return ERR_OK if connection has been closed + * another err_t if closing failed and pcb is not freed + */ +err_t +tcp_close(struct tcp_pcb *pcb) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_close: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_close: closing in ")); + + tcp_debug_print_state(pcb->state); + + if (pcb->state != LISTEN) { + /* Set a flag not to receive any more data... */ + tcp_set_flags(pcb, TF_RXCLOSED); + } + /* ... and close */ + return tcp_close_shutdown(pcb, 1); +} + +/** + * @ingroup tcp_raw + * Causes all or part of a full-duplex connection of this PCB to be shut down. + * This doesn't deallocate the PCB unless shutting down both sides! + * Shutting down both sides is the same as calling tcp_close, so if it succeds + * (i.e. returns ER_OK), the PCB must not be referenced any more! + * + * @param pcb PCB to shutdown + * @param shut_rx shut down receive side if this is != 0 + * @param shut_tx shut down send side if this is != 0 + * @return ERR_OK if shutdown succeeded (or the PCB has already been shut down) + * another err_t on error. + */ +err_t +tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_shutdown: invalid pcb", pcb != NULL, return ERR_ARG); + + if (pcb->state == LISTEN) { + return ERR_CONN; + } + if (shut_rx) { + /* shut down the receive side: set a flag not to receive any more data... */ + tcp_set_flags(pcb, TF_RXCLOSED); + if (shut_tx) { + /* shutting down the tx AND rx side is the same as closing for the raw API */ + return tcp_close_shutdown(pcb, 1); + } + /* ... and free buffered data */ + if (pcb->refused_data != NULL) { + pbuf_free(pcb->refused_data); + pcb->refused_data = NULL; + } + } + if (shut_tx) { + /* This can't happen twice since if it succeeds, the pcb's state is changed. + Only close in these states as the others directly deallocate the PCB */ + switch (pcb->state) { + case SYN_RCVD: + case ESTABLISHED: + case CLOSE_WAIT: + return tcp_close_shutdown(pcb, (u8_t)shut_rx); + default: + /* Not (yet?) connected, cannot shutdown the TX side as that would bring us + into CLOSED state, where the PCB is deallocated. */ + return ERR_CONN; + } + } + return ERR_OK; +} + +/** + * Abandons a connection and optionally sends a RST to the remote + * host. Deletes the local protocol control block. This is done when + * a connection is killed because of shortage of memory. + * + * @param pcb the tcp_pcb to abort + * @param reset boolean to indicate whether a reset should be sent + */ +void +tcp_abandon(struct tcp_pcb *pcb, int reset) +{ + u32_t seqno, ackno; +#if LWIP_CALLBACK_API + tcp_err_fn errf; +#endif /* LWIP_CALLBACK_API */ + void *errf_arg; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_abandon: invalid pcb", pcb != NULL, return); + + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_abort/tcp_abandon for listen-pcbs", + pcb->state != LISTEN); + /* Figure out on which TCP PCB list we are, and remove us. If we + are in an active state, call the receive function associated with + the PCB with a NULL argument, and send an RST to the remote end. */ + if (pcb->state == TIME_WAIT) { + tcp_pcb_remove(&tcp_tw_pcbs, pcb); + tcp_free(pcb); + } else { + int send_rst = 0; + u16_t local_port = 0; + enum tcp_state last_state; + seqno = pcb->snd_nxt; + ackno = pcb->rcv_nxt; +#if LWIP_CALLBACK_API + errf = pcb->errf; +#endif /* LWIP_CALLBACK_API */ + errf_arg = pcb->callback_arg; + if (pcb->state == CLOSED) { + if (pcb->local_port != 0) { + /* bound, not yet opened */ + TCP_RMV(&tcp_bound_pcbs, pcb); + } + } else { + send_rst = reset; + local_port = pcb->local_port; + TCP_PCB_REMOVE_ACTIVE(pcb); + } + if (pcb->unacked != NULL) { + tcp_segs_free(pcb->unacked); + } + if (pcb->unsent != NULL) { + tcp_segs_free(pcb->unsent); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + tcp_segs_free(pcb->ooseq); + } +#endif /* TCP_QUEUE_OOSEQ */ + tcp_backlog_accepted(pcb); + if (send_rst) { + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_abandon: sending RST\n")); + tcp_rst(pcb, seqno, ackno, &pcb->local_ip, &pcb->remote_ip, local_port, pcb->remote_port); + } + last_state = pcb->state; + tcp_free(pcb); + TCP_EVENT_ERR(last_state, errf, errf_arg, ERR_ABRT); + } +} + +/** + * @ingroup tcp_raw + * Aborts the connection by sending a RST (reset) segment to the remote + * host. The pcb is deallocated. This function never fails. + * + * ATTENTION: When calling this from one of the TCP callbacks, make + * sure you always return ERR_ABRT (and never return ERR_ABRT otherwise + * or you will risk accessing deallocated memory or memory leaks! + * + * @param pcb the tcp pcb to abort + */ +void +tcp_abort(struct tcp_pcb *pcb) +{ + tcp_abandon(pcb, 1); +} + +/** + * @ingroup tcp_raw + * Binds the connection to a local port number and IP address. If the + * IP address is not given (i.e., ipaddr == IP_ANY_TYPE), the connection is + * bound to all local IP addresses. + * If another connection is bound to the same port, the function will + * return ERR_USE, otherwise ERR_OK is returned. + * + * @param pcb the tcp_pcb to bind (no check is done whether this pcb is + * already bound!) + * @param ipaddr the local ip address to bind to (use IPx_ADDR_ANY to bind + * to any local address + * @param port the local port to bind to + * @return ERR_USE if the port is already in use + * ERR_VAL if bind failed because the PCB is not in a valid state + * ERR_OK if bound + */ +err_t +tcp_bind(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) +{ + int i; + int max_pcb_list = NUM_TCP_PCB_LISTS; + struct tcp_pcb *cpcb; +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + ip_addr_t zoned_ipaddr; +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_IPV4 + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (ipaddr == NULL) { + ipaddr = IP4_ADDR_ANY; + } +#else /* LWIP_IPV4 */ + LWIP_ERROR("tcp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG); +#endif /* LWIP_IPV4 */ + + LWIP_ERROR("tcp_bind: invalid pcb", pcb != NULL, return ERR_ARG); + + LWIP_ERROR("tcp_bind: can only bind in state CLOSED", pcb->state == CLOSED, return ERR_VAL); + +#if SO_REUSE + /* Unless the REUSEADDR flag is set, + we have to check the pcbs in TIME-WAIT state, also. + We do not dump TIME_WAIT pcb's; they can still be matched by incoming + packets using both local and remote IP addresses and ports to distinguish. + */ + if (ip_get_option(pcb, SOF_REUSEADDR)) { + max_pcb_list = NUM_TCP_PCB_LISTS_NO_TIME_WAIT; + } +#endif /* SO_REUSE */ + +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + /* If the given IP address should have a zone but doesn't, assign one now. + * This is legacy support: scope-aware callers should always provide properly + * zoned source addresses. Do the zone selection before the address-in-use + * check below; as such we have to make a temporary copy of the address. */ + if (IP_IS_V6(ipaddr) && ip6_addr_lacks_zone(ip_2_ip6(ipaddr), IP6_UNICAST)) { + ip_addr_copy(zoned_ipaddr, *ipaddr); + ip6_addr_select_zone(ip_2_ip6(&zoned_ipaddr), ip_2_ip6(&zoned_ipaddr)); + ipaddr = &zoned_ipaddr; + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + if (port == 0) { + port = tcp_new_port(); + if (port == 0) { + return ERR_BUF; + } + } else { + /* Check if the address already is in use (on all lists) */ + for (i = 0; i < max_pcb_list; i++) { + for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { + if (cpcb->local_port == port) { +#if SO_REUSE + /* Omit checking for the same port if both pcbs have REUSEADDR set. + For SO_REUSEADDR, the duplicate-check for a 5-tuple is done in + tcp_connect. */ + if (!ip_get_option(pcb, SOF_REUSEADDR) || + !ip_get_option(cpcb, SOF_REUSEADDR)) +#endif /* SO_REUSE */ + { + /* @todo: check accept_any_ip_version */ + if ((IP_IS_V6(ipaddr) == IP_IS_V6_VAL(cpcb->local_ip)) && + (ip_addr_isany(&cpcb->local_ip) || + ip_addr_isany(ipaddr) || + ip_addr_cmp(&cpcb->local_ip, ipaddr))) { + return ERR_USE; + } + } + } + } + } + } + + if (!ip_addr_isany(ipaddr) +#if LWIP_IPV4 && LWIP_IPV6 + || (IP_GET_TYPE(ipaddr) != IP_GET_TYPE(&pcb->local_ip)) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + ) { + ip_addr_set(&pcb->local_ip, ipaddr); + } + pcb->local_port = port; + TCP_REG(&tcp_bound_pcbs, pcb); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_bind: bind to port %"U16_F"\n", port)); + return ERR_OK; +} + +/** + * @ingroup tcp_raw + * Binds the connection to a netif and IP address. + * After calling this function, all packets received via this PCB + * are guaranteed to have come in via the specified netif, and all + * outgoing packets will go out via the specified netif. + * + * @param pcb the tcp_pcb to bind. + * @param netif the netif to bind to. Can be NULL. + */ +void +tcp_bind_netif(struct tcp_pcb *pcb, const struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + if (netif != NULL) { + pcb->netif_idx = netif_get_index(netif); + } else { + pcb->netif_idx = NETIF_NO_INDEX; + } +} + +#if LWIP_CALLBACK_API +/** + * Default accept callback if no accept callback is specified by the user. + */ +static err_t +tcp_accept_null(void *arg, struct tcp_pcb *pcb, err_t err) +{ + LWIP_UNUSED_ARG(arg); + LWIP_UNUSED_ARG(err); + + LWIP_ASSERT("tcp_accept_null: invalid pcb", pcb != NULL); + + tcp_abort(pcb); + + return ERR_ABRT; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * @ingroup tcp_raw + * Set the state of the connection to be LISTEN, which means that it + * is able to accept incoming connections. The protocol control block + * is reallocated in order to consume less memory. Setting the + * connection to LISTEN is an irreversible process. + * When an incoming connection is accepted, the function specified with + * the tcp_accept() function will be called. The pcb has to be bound + * to a local port with the tcp_bind() function. + * + * The tcp_listen() function returns a new connection identifier, and + * the one passed as an argument to the function will be + * deallocated. The reason for this behavior is that less memory is + * needed for a connection that is listening, so tcp_listen() will + * reclaim the memory needed for the original connection and allocate a + * new smaller memory block for the listening connection. + * + * tcp_listen() may return NULL if no memory was available for the + * listening connection. If so, the memory associated with the pcb + * passed as an argument to tcp_listen() will not be deallocated. + * + * The backlog limits the number of outstanding connections + * in the listen queue to the value specified by the backlog argument. + * To use it, your need to set TCP_LISTEN_BACKLOG=1 in your lwipopts.h. + * + * @param pcb the original tcp_pcb + * @param backlog the incoming connections queue limit + * @return tcp_pcb used for listening, consumes less memory. + * + * @note The original tcp_pcb is freed. This function therefore has to be + * called like this: + * tpcb = tcp_listen_with_backlog(tpcb, backlog); + */ +struct tcp_pcb * +tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog) +{ + LWIP_ASSERT_CORE_LOCKED(); + return tcp_listen_with_backlog_and_err(pcb, backlog, NULL); +} + +/** + * @ingroup tcp_raw + * Set the state of the connection to be LISTEN, which means that it + * is able to accept incoming connections. The protocol control block + * is reallocated in order to consume less memory. Setting the + * connection to LISTEN is an irreversible process. + * + * @param pcb the original tcp_pcb + * @param backlog the incoming connections queue limit + * @param err when NULL is returned, this contains the error reason + * @return tcp_pcb used for listening, consumes less memory. + * + * @note The original tcp_pcb is freed. This function therefore has to be + * called like this: + * tpcb = tcp_listen_with_backlog_and_err(tpcb, backlog, &err); + */ +struct tcp_pcb * +tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err) +{ + struct tcp_pcb_listen *lpcb = NULL; + err_t res; + + LWIP_UNUSED_ARG(backlog); + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_listen_with_backlog_and_err: invalid pcb", pcb != NULL, res = ERR_ARG; goto done); + LWIP_ERROR("tcp_listen_with_backlog_and_err: pcb already connected", pcb->state == CLOSED, res = ERR_CLSD; goto done); + + /* already listening? */ + if (pcb->state == LISTEN) { + lpcb = (struct tcp_pcb_listen *)pcb; + res = ERR_ALREADY; + goto done; + } +#if SO_REUSE + if (ip_get_option(pcb, SOF_REUSEADDR)) { + /* Since SOF_REUSEADDR allows reusing a local address before the pcb's usage + is declared (listen-/connection-pcb), we have to make sure now that + this port is only used once for every local IP. */ + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + if ((lpcb->local_port == pcb->local_port) && + ip_addr_cmp(&lpcb->local_ip, &pcb->local_ip)) { + /* this address/port is already used */ + lpcb = NULL; + res = ERR_USE; + goto done; + } + } + } +#endif /* SO_REUSE */ + lpcb = (struct tcp_pcb_listen *)memp_malloc(MEMP_TCP_PCB_LISTEN); + if (lpcb == NULL) { + res = ERR_MEM; + goto done; + } + lpcb->callback_arg = pcb->callback_arg; + lpcb->local_port = pcb->local_port; + lpcb->state = LISTEN; + lpcb->prio = pcb->prio; + lpcb->so_options = pcb->so_options; + lpcb->netif_idx = NETIF_NO_INDEX; + lpcb->ttl = pcb->ttl; + lpcb->tos = pcb->tos; +#if LWIP_IPV4 && LWIP_IPV6 + IP_SET_TYPE_VAL(lpcb->remote_ip, pcb->local_ip.type); +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + ip_addr_copy(lpcb->local_ip, pcb->local_ip); + if (pcb->local_port != 0) { + TCP_RMV(&tcp_bound_pcbs, pcb); + } +#if LWIP_TCP_PCB_NUM_EXT_ARGS + /* copy over ext_args to listening pcb */ + memcpy(&lpcb->ext_args, &pcb->ext_args, sizeof(pcb->ext_args)); +#endif + tcp_free(pcb); +#if LWIP_CALLBACK_API + lpcb->accept = tcp_accept_null; +#endif /* LWIP_CALLBACK_API */ +#if TCP_LISTEN_BACKLOG + lpcb->accepts_pending = 0; + tcp_backlog_set(lpcb, backlog); +#endif /* TCP_LISTEN_BACKLOG */ + TCP_REG(&tcp_listen_pcbs.pcbs, (struct tcp_pcb *)lpcb); + res = ERR_OK; +done: + if (err != NULL) { + *err = res; + } + return (struct tcp_pcb *)lpcb; +} + +/** + * Update the state that tracks the available window space to advertise. + * + * Returns how much extra window would be advertised if we sent an + * update now. + */ +u32_t +tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb) +{ + u32_t new_right_edge; + + LWIP_ASSERT("tcp_update_rcv_ann_wnd: invalid pcb", pcb != NULL); + new_right_edge = pcb->rcv_nxt + pcb->rcv_wnd; + + if (TCP_SEQ_GEQ(new_right_edge, pcb->rcv_ann_right_edge + LWIP_MIN((TCP_WND / 2), pcb->mss))) { + /* we can advertise more window */ + pcb->rcv_ann_wnd = pcb->rcv_wnd; + return new_right_edge - pcb->rcv_ann_right_edge; + } else { + if (TCP_SEQ_GT(pcb->rcv_nxt, pcb->rcv_ann_right_edge)) { + /* Can happen due to other end sending out of advertised window, + * but within actual available (but not yet advertised) window */ + pcb->rcv_ann_wnd = 0; + } else { + /* keep the right edge of window constant */ + u32_t new_rcv_ann_wnd = pcb->rcv_ann_right_edge - pcb->rcv_nxt; +#if !LWIP_WND_SCALE + LWIP_ASSERT("new_rcv_ann_wnd <= 0xffff", new_rcv_ann_wnd <= 0xffff); +#endif + pcb->rcv_ann_wnd = (tcpwnd_size_t)new_rcv_ann_wnd; + } + return 0; + } +} + +/** + * @ingroup tcp_raw + * This function should be called by the application when it has + * processed the data. The purpose is to advertise a larger window + * when the data has been processed. + * + * @param pcb the tcp_pcb for which data is read + * @param len the amount of bytes that have been read by the application + */ +void +tcp_recved(struct tcp_pcb *pcb, u16_t len) +{ + u32_t wnd_inflation; + tcpwnd_size_t rcv_wnd; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_recved: invalid pcb", pcb != NULL, return); + + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_recved for listen-pcbs", + pcb->state != LISTEN); + + rcv_wnd = (tcpwnd_size_t)(pcb->rcv_wnd + len); + if ((rcv_wnd > TCP_WND_MAX(pcb)) || (rcv_wnd < pcb->rcv_wnd)) { + /* window got too big or tcpwnd_size_t overflow */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: window got too big or tcpwnd_size_t overflow\n")); + pcb->rcv_wnd = TCP_WND_MAX(pcb); + } else { + pcb->rcv_wnd = rcv_wnd; + } + + wnd_inflation = tcp_update_rcv_ann_wnd(pcb); + + /* If the change in the right edge of window is significant (default + * watermark is TCP_WND/4), then send an explicit update now. + * Otherwise wait for a packet to be sent in the normal course of + * events (or more window to be available later) */ + if (wnd_inflation >= TCP_WND_UPDATE_THRESHOLD) { + tcp_ack_now(pcb); + tcp_output(pcb); + } + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_recved: received %"U16_F" bytes, wnd %"TCPWNDSIZE_F" (%"TCPWNDSIZE_F").\n", + len, pcb->rcv_wnd, (u16_t)(TCP_WND_MAX(pcb) - pcb->rcv_wnd))); +} + +/** + * Allocate a new local TCP port. + * + * @return a new (free) local TCP port number + */ +static u16_t +tcp_new_port(void) +{ + u8_t i; + u16_t n = 0; + struct tcp_pcb *pcb; + +again: + tcp_port++; + if (tcp_port == TCP_LOCAL_PORT_RANGE_END) { + tcp_port = TCP_LOCAL_PORT_RANGE_START; + } + /* Check all PCB lists. */ + for (i = 0; i < NUM_TCP_PCB_LISTS; i++) { + for (pcb = *tcp_pcb_lists[i]; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == tcp_port) { + n++; + if (n > (TCP_LOCAL_PORT_RANGE_END - TCP_LOCAL_PORT_RANGE_START)) { + return 0; + } + goto again; + } + } + } + return tcp_port; +} + +/** + * @ingroup tcp_raw + * Connects to another host. The function given as the "connected" + * argument will be called when the connection has been established. + * Sets up the pcb to connect to the remote host and sends the + * initial SYN segment which opens the connection. + * + * The tcp_connect() function returns immediately; it does not wait for + * the connection to be properly setup. Instead, it will call the + * function specified as the fourth argument (the "connected" argument) + * when the connection is established. If the connection could not be + * properly established, either because the other host refused the + * connection or because the other host didn't answer, the "err" + * callback function of this pcb (registered with tcp_err, see below) + * will be called. + * + * The tcp_connect() function can return ERR_MEM if no memory is + * available for enqueueing the SYN segment. If the SYN indeed was + * enqueued successfully, the tcp_connect() function returns ERR_OK. + * + * @param pcb the tcp_pcb used to establish the connection + * @param ipaddr the remote ip address to connect to + * @param port the remote tcp port to connect to + * @param connected callback function to call when connected (on error, + the err calback will be called) + * @return ERR_VAL if invalid arguments are given + * ERR_OK if connect request has been sent + * other err_t values if connect request couldn't be sent + */ +err_t +tcp_connect(struct tcp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port, + tcp_connected_fn connected) +{ + struct netif *netif = NULL; + err_t ret; + u32_t iss; + u16_t old_local_port; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_connect: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_ERROR("tcp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG); + + LWIP_ERROR("tcp_connect: can only connect from state CLOSED", pcb->state == CLOSED, return ERR_ISCONN); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_connect to port %"U16_F"\n", port)); + ip_addr_set(&pcb->remote_ip, ipaddr); + pcb->remote_port = port; + + if (pcb->netif_idx != NETIF_NO_INDEX) { + netif = netif_get_by_index(pcb->netif_idx); + } else { + /* check if we have a route to the remote host */ + netif = ip_route(&pcb->local_ip, &pcb->remote_ip); + } + if (netif == NULL) { + /* Don't even try to send a SYN packet if we have no route since that will fail. */ + return ERR_RTE; + } + + /* check if local IP has been assigned to pcb, if not, get one */ + if (ip_addr_isany(&pcb->local_ip)) { + const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, ipaddr); + if (local_ip == NULL) { + return ERR_RTE; + } + ip_addr_copy(pcb->local_ip, *local_ip); + } + +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + /* If the given IP address should have a zone but doesn't, assign one now. + * Given that we already have the target netif, this is easy and cheap. */ + if (IP_IS_V6(&pcb->remote_ip) && + ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST)) { + ip6_addr_assign_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNICAST, netif); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + old_local_port = pcb->local_port; + if (pcb->local_port == 0) { + pcb->local_port = tcp_new_port(); + if (pcb->local_port == 0) { + return ERR_BUF; + } + } else { +#if SO_REUSE + if (ip_get_option(pcb, SOF_REUSEADDR)) { + /* Since SOF_REUSEADDR allows reusing a local address, we have to make sure + now that the 5-tuple is unique. */ + struct tcp_pcb *cpcb; + int i; + /* Don't check listen- and bound-PCBs, check active- and TIME-WAIT PCBs. */ + for (i = 2; i < NUM_TCP_PCB_LISTS; i++) { + for (cpcb = *tcp_pcb_lists[i]; cpcb != NULL; cpcb = cpcb->next) { + if ((cpcb->local_port == pcb->local_port) && + (cpcb->remote_port == port) && + ip_addr_cmp(&cpcb->local_ip, &pcb->local_ip) && + ip_addr_cmp(&cpcb->remote_ip, ipaddr)) { + /* linux returns EISCONN here, but ERR_USE should be OK for us */ + return ERR_USE; + } + } + } + } +#endif /* SO_REUSE */ + } + + iss = tcp_next_iss(pcb); + pcb->rcv_nxt = 0; + pcb->snd_nxt = iss; + pcb->lastack = iss - 1; + pcb->snd_wl2 = iss - 1; + pcb->snd_lbb = iss - 1; + /* Start with a window that does not need scaling. When window scaling is + enabled and used, the window is enlarged when both sides agree on scaling. */ + pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + pcb->snd_wnd = TCP_WND; + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = INITIAL_MSS; +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss_netif(pcb->mss, netif, &pcb->remote_ip); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + pcb->cwnd = 1; +#if LWIP_CALLBACK_API + pcb->connected = connected; +#else /* LWIP_CALLBACK_API */ + LWIP_UNUSED_ARG(connected); +#endif /* LWIP_CALLBACK_API */ + + /* Send a SYN together with the MSS option. */ + ret = tcp_enqueue_flags(pcb, TCP_SYN); + if (ret == ERR_OK) { + /* SYN segment was enqueued, changed the pcbs state now */ + pcb->state = SYN_SENT; + if (old_local_port != 0) { + TCP_RMV(&tcp_bound_pcbs, pcb); + } + TCP_REG_ACTIVE(pcb); + MIB2_STATS_INC(mib2.tcpactiveopens); + + tcp_output(pcb); + } + return ret; +} + +/** + * Called every 500 ms and implements the retransmission timer and the timer that + * removes PCBs that have been in TIME-WAIT for enough time. It also increments + * various timers such as the inactivity timer in each PCB. + * + * Automatically called from tcp_tmr(). + */ +void +tcp_slowtmr(void) +{ + struct tcp_pcb *pcb, *prev; + tcpwnd_size_t eff_wnd; + u8_t pcb_remove; /* flag if a PCB should be removed */ + u8_t pcb_reset; /* flag if a RST should be sent when removing */ + err_t err; + + err = ERR_OK; + + ++tcp_ticks; + ++tcp_timer_ctr; + +tcp_slowtmr_start: + /* Steps through all of the active PCBs. */ + prev = NULL; + pcb = tcp_active_pcbs; + if (pcb == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: no active pcbs\n")); + } + while (pcb != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: processing active pcb\n")); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != CLOSED\n", pcb->state != CLOSED); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != LISTEN\n", pcb->state != LISTEN); + LWIP_ASSERT("tcp_slowtmr: active pcb->state != TIME-WAIT\n", pcb->state != TIME_WAIT); + if (pcb->last_timer == tcp_timer_ctr) { + /* skip this pcb, we have already processed it */ + prev = pcb; + pcb = pcb->next; + continue; + } + pcb->last_timer = tcp_timer_ctr; + + pcb_remove = 0; + pcb_reset = 0; + + if (pcb->state == SYN_SENT && pcb->nrtx >= TCP_SYNMAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max SYN retries reached\n")); + } else if (pcb->nrtx >= TCP_MAXRTX) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: max DATA retries reached\n")); + } else { + if (pcb->persist_backoff > 0) { + LWIP_ASSERT("tcp_slowtimr: persist ticking with in-flight data", pcb->unacked == NULL); + LWIP_ASSERT("tcp_slowtimr: persist ticking with empty send buffer", pcb->unsent != NULL); + if (pcb->persist_probe >= TCP_MAXRTX) { + ++pcb_remove; /* max probes reached */ + } else { + u8_t backoff_cnt = tcp_persist_backoff[pcb->persist_backoff - 1]; + if (pcb->persist_cnt < backoff_cnt) { + pcb->persist_cnt++; + } + if (pcb->persist_cnt >= backoff_cnt) { + int next_slot = 1; /* increment timer to next slot */ + /* If snd_wnd is zero, send 1 byte probes */ + if (pcb->snd_wnd == 0) { + if (tcp_zero_window_probe(pcb) != ERR_OK) { + next_slot = 0; /* try probe again with current slot */ + } + /* snd_wnd not fully closed, split unsent head and fill window */ + } else { + if (tcp_split_unsent_seg(pcb, (u16_t)pcb->snd_wnd) == ERR_OK) { + if (tcp_output(pcb) == ERR_OK) { + /* sending will cancel persist timer, else retry with current slot */ + next_slot = 0; + } + } + } + if (next_slot) { + pcb->persist_cnt = 0; + if (pcb->persist_backoff < sizeof(tcp_persist_backoff)) { + pcb->persist_backoff++; + } + } + } + } + } else { + /* Increase the retransmission timer if it is running */ + if ((pcb->rtime >= 0) && (pcb->rtime < 0x7FFF)) { + ++pcb->rtime; + } + + if (pcb->rtime >= pcb->rto) { + /* Time for a retransmission. */ + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_slowtmr: rtime %"S16_F + " pcb->rto %"S16_F"\n", + pcb->rtime, pcb->rto)); + /* If prepare phase fails but we have unsent data but no unacked data, + still execute the backoff calculations below, as this means we somehow + failed to send segment. */ + if ((tcp_rexmit_rto_prepare(pcb) == ERR_OK) || ((pcb->unacked == NULL) && (pcb->unsent != NULL))) { + /* Double retransmission time-out unless we are trying to + * connect to somebody (i.e., we are in SYN_SENT). */ + if (pcb->state != SYN_SENT) { + u8_t backoff_idx = LWIP_MIN(pcb->nrtx, sizeof(tcp_backoff) - 1); + int calc_rto = ((pcb->sa >> 3) + pcb->sv) << tcp_backoff[backoff_idx]; + pcb->rto = (s16_t)LWIP_MIN(calc_rto, 0x7FFF); + } + + /* Reset the retransmission timer. */ + pcb->rtime = 0; + + /* Reduce congestion window and ssthresh. */ + eff_wnd = LWIP_MIN(pcb->cwnd, pcb->snd_wnd); + pcb->ssthresh = eff_wnd >> 1; + if (pcb->ssthresh < (tcpwnd_size_t)(pcb->mss << 1)) { + pcb->ssthresh = (tcpwnd_size_t)(pcb->mss << 1); + } + pcb->cwnd = pcb->mss; + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + pcb->bytes_acked = 0; + + /* The following needs to be called AFTER cwnd is set to one + mss - STJ */ + tcp_rexmit_rto_commit(pcb); + } + } + } + } + /* Check if this PCB has stayed too long in FIN-WAIT-2 */ + if (pcb->state == FIN_WAIT_2) { + /* If this PCB is in FIN_WAIT_2 because of SHUT_WR don't let it time out. */ + if (pcb->flags & TF_RXCLOSED) { + /* PCB was fully closed (either through close() or SHUT_RDWR): + normal FIN-WAIT timeout handling. */ + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_FIN_WAIT_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in FIN-WAIT-2\n")); + } + } + } + + /* Check if KEEPALIVE should be sent */ + if (ip_get_option(pcb, SOF_KEEPALIVE) && + ((pcb->state == ESTABLISHED) || + (pcb->state == CLOSE_WAIT))) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + TCP_KEEP_DUR(pcb)) / TCP_SLOW_INTERVAL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: KEEPALIVE timeout. Aborting connection to ")); + ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + + ++pcb_remove; + ++pcb_reset; + } else if ((u32_t)(tcp_ticks - pcb->tmr) > + (pcb->keep_idle + pcb->keep_cnt_sent * TCP_KEEP_INTVL(pcb)) + / TCP_SLOW_INTERVAL) { + err = tcp_keepalive(pcb); + if (err == ERR_OK) { + pcb->keep_cnt_sent++; + } + } + } + + /* If this PCB has queued out of sequence data, but has been + inactive for too long, will drop the data (it will eventually + be retransmitted). */ +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL && + (tcp_ticks - pcb->tmr >= (u32_t)pcb->rto * TCP_OOSEQ_TIMEOUT)) { + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_slowtmr: dropping OOSEQ queued data\n")); + tcp_free_ooseq(pcb); + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Check if this PCB has stayed too long in SYN-RCVD */ + if (pcb->state == SYN_RCVD) { + if ((u32_t)(tcp_ticks - pcb->tmr) > + TCP_SYN_RCVD_TIMEOUT / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in SYN-RCVD\n")); + } + } + + /* Check if this PCB has stayed too long in LAST-ACK */ + if (pcb->state == LAST_ACK) { + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: removing pcb stuck in LAST-ACK\n")); + } + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + struct tcp_pcb *pcb2; +#if LWIP_CALLBACK_API + tcp_err_fn err_fn = pcb->errf; +#endif /* LWIP_CALLBACK_API */ + void *err_arg; + enum tcp_state last_state; + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_active_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_active_pcbs", pcb != tcp_active_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_active_pcbs", tcp_active_pcbs == pcb); + tcp_active_pcbs = pcb->next; + } + + if (pcb_reset) { + tcp_rst(pcb, pcb->snd_nxt, pcb->rcv_nxt, &pcb->local_ip, &pcb->remote_ip, + pcb->local_port, pcb->remote_port); + } + + err_arg = pcb->callback_arg; + last_state = pcb->state; + pcb2 = pcb; + pcb = pcb->next; + tcp_free(pcb2); + + tcp_active_pcbs_changed = 0; + TCP_EVENT_ERR(last_state, err_fn, err_arg, ERR_ABRT); + if (tcp_active_pcbs_changed) { + goto tcp_slowtmr_start; + } + } else { + /* get the 'next' element now and work with 'prev' below (in case of abort) */ + prev = pcb; + pcb = pcb->next; + + /* We check if we should poll the connection. */ + ++prev->polltmr; + if (prev->polltmr >= prev->pollinterval) { + prev->polltmr = 0; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_slowtmr: polling application\n")); + tcp_active_pcbs_changed = 0; + TCP_EVENT_POLL(prev, err); + if (tcp_active_pcbs_changed) { + goto tcp_slowtmr_start; + } + /* if err == ERR_ABRT, 'prev' is already deallocated */ + if (err == ERR_OK) { + tcp_output(prev); + } + } + } + } + + + /* Steps through all of the TIME-WAIT PCBs. */ + prev = NULL; + pcb = tcp_tw_pcbs; + while (pcb != NULL) { + LWIP_ASSERT("tcp_slowtmr: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + pcb_remove = 0; + + /* Check if this PCB has stayed long enough in TIME-WAIT */ + if ((u32_t)(tcp_ticks - pcb->tmr) > 2 * TCP_MSL / TCP_SLOW_INTERVAL) { + ++pcb_remove; + } + + /* If the PCB should be removed, do it. */ + if (pcb_remove) { + struct tcp_pcb *pcb2; + tcp_pcb_purge(pcb); + /* Remove PCB from tcp_tw_pcbs list. */ + if (prev != NULL) { + LWIP_ASSERT("tcp_slowtmr: middle tcp != tcp_tw_pcbs", pcb != tcp_tw_pcbs); + prev->next = pcb->next; + } else { + /* This PCB was the first. */ + LWIP_ASSERT("tcp_slowtmr: first pcb == tcp_tw_pcbs", tcp_tw_pcbs == pcb); + tcp_tw_pcbs = pcb->next; + } + pcb2 = pcb; + pcb = pcb->next; + tcp_free(pcb2); + } else { + prev = pcb; + pcb = pcb->next; + } + } +} + +/** + * Is called every TCP_FAST_INTERVAL (250 ms) and process data previously + * "refused" by upper layer (application) and sends delayed ACKs or pending FINs. + * + * Automatically called from tcp_tmr(). + */ +void +tcp_fasttmr(void) +{ + struct tcp_pcb *pcb; + + ++tcp_timer_ctr; + +tcp_fasttmr_start: + pcb = tcp_active_pcbs; + + while (pcb != NULL) { + if (pcb->last_timer != tcp_timer_ctr) { + struct tcp_pcb *next; + pcb->last_timer = tcp_timer_ctr; + /* send delayed ACKs */ + if (pcb->flags & TF_ACK_DELAY) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: delayed ACK\n")); + tcp_ack_now(pcb); + tcp_output(pcb); + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + } + /* send pending FIN */ + if (pcb->flags & TF_CLOSEPEND) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_fasttmr: pending FIN\n")); + tcp_clear_flags(pcb, TF_CLOSEPEND); + tcp_close_shutdown_fin(pcb); + } + + next = pcb->next; + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + tcp_active_pcbs_changed = 0; + tcp_process_refused_data(pcb); + if (tcp_active_pcbs_changed) { + /* application callback has changed the pcb list: restart the loop */ + goto tcp_fasttmr_start; + } + } + pcb = next; + } else { + pcb = pcb->next; + } + } +} + +/** Call tcp_output for all active pcbs that have TF_NAGLEMEMERR set */ +void +tcp_txnow(void) +{ + struct tcp_pcb *pcb; + + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->flags & TF_NAGLEMEMERR) { + tcp_output(pcb); + } + } +} + +/** Pass pcb->refused_data to the recv callback */ +err_t +tcp_process_refused_data(struct tcp_pcb *pcb) +{ +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + struct pbuf *rest; +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + + LWIP_ERROR("tcp_process_refused_data: invalid pcb", pcb != NULL, return ERR_ARG); + +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + while (pcb->refused_data != NULL) +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + { + err_t err; + u8_t refused_flags = pcb->refused_data->flags; + /* set pcb->refused_data to NULL in case the callback frees it and then + closes the pcb */ + struct pbuf *refused_data = pcb->refused_data; +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + pbuf_split_64k(refused_data, &rest); + pcb->refused_data = rest; +#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = NULL; +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + /* Notify again application with data previously received. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: notify kept packet\n")); + TCP_EVENT_RECV(pcb, refused_data, ERR_OK, err); + if (err == ERR_OK) { + /* did refused_data include a FIN? */ + if ((refused_flags & PBUF_FLAG_TCP_FIN) +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + && (rest == NULL) +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + ) { + /* correct rcv_wnd as the application won't call tcp_recved() + for the FIN's seqno */ + if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { + pcb->rcv_wnd++; + } + TCP_EVENT_CLOSED(pcb, err); + if (err == ERR_ABRT) { + return ERR_ABRT; + } + } + } else if (err == ERR_ABRT) { + /* if err == ERR_ABRT, 'pcb' is already deallocated */ + /* Drop incoming packets because pcb is "full" (only if the incoming + segment contains data). */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: drop incoming packets, because pcb is \"full\"\n")); + return ERR_ABRT; + } else { + /* data is still refused, pbuf is still valid (go on for ACK-only packets) */ +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_cat(refused_data, rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = refused_data; + return ERR_INPROGRESS; + } + } + return ERR_OK; +} + +/** + * Deallocates a list of TCP segments (tcp_seg structures). + * + * @param seg tcp_seg list of TCP segments to free + */ +void +tcp_segs_free(struct tcp_seg *seg) +{ + while (seg != NULL) { + struct tcp_seg *next = seg->next; + tcp_seg_free(seg); + seg = next; + } +} + +/** + * Frees a TCP segment (tcp_seg structure). + * + * @param seg single tcp_seg to free + */ +void +tcp_seg_free(struct tcp_seg *seg) +{ + if (seg != NULL) { + if (seg->p != NULL) { + pbuf_free(seg->p); +#if TCP_DEBUG + seg->p = NULL; +#endif /* TCP_DEBUG */ + } + memp_free(MEMP_TCP_SEG, seg); + } +} + +/** + * @ingroup tcp + * Sets the priority of a connection. + * + * @param pcb the tcp_pcb to manipulate + * @param prio new priority + */ +void +tcp_setprio(struct tcp_pcb *pcb, u8_t prio) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_setprio: invalid pcb", pcb != NULL, return); + + pcb->prio = prio; +} + +#if TCP_QUEUE_OOSEQ +/** + * Returns a copy of the given TCP segment. + * The pbuf and data are not copied, only the pointers + * + * @param seg the old tcp_seg + * @return a copy of seg + */ +struct tcp_seg * +tcp_seg_copy(struct tcp_seg *seg) +{ + struct tcp_seg *cseg; + + LWIP_ASSERT("tcp_seg_copy: invalid seg", seg != NULL); + + cseg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG); + if (cseg == NULL) { + return NULL; + } + SMEMCPY((u8_t *)cseg, (const u8_t *)seg, sizeof(struct tcp_seg)); + pbuf_ref(cseg->p); + return cseg; +} +#endif /* TCP_QUEUE_OOSEQ */ + +#if LWIP_CALLBACK_API +/** + * Default receive callback that is called if the user didn't register + * a recv callback for the pcb. + */ +err_t +tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + LWIP_UNUSED_ARG(arg); + + LWIP_ERROR("tcp_recv_null: invalid pcb", pcb != NULL, return ERR_ARG); + + if (p != NULL) { + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } else if (err == ERR_OK) { + return tcp_close(pcb); + } + return ERR_OK; +} +#endif /* LWIP_CALLBACK_API */ + +/** + * Kills the oldest active connection that has a lower priority than 'prio'. + * + * @param prio minimum priority + */ +static void +tcp_kill_prio(u8_t prio) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + u8_t mprio; + + mprio = LWIP_MIN(TCP_PRIO_MAX, prio); + + /* We want to kill connections with a lower prio, so bail out if + * supplied prio is 0 - there can never be a lower prio + */ + if (mprio == 0) { + return; + } + + /* We only want kill connections with a lower prio, so decrement prio by one + * and start searching for oldest connection with same or lower priority than mprio. + * We want to find the connections with the lowest possible prio, and among + * these the one with the longest inactivity time. + */ + mprio--; + + inactivity = 0; + inactive = NULL; + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + /* lower prio is always a kill candidate */ + if ((pcb->prio < mprio) || + /* longer inactivity is also a kill candidate */ + ((pcb->prio == mprio) && ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity))) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + mprio = pcb->prio; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_prio: killing oldest PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + +/** + * Kills the oldest connection that is in specific state. + * Called from tcp_alloc() for LAST_ACK and CLOSING if no more connections are available. + */ +static void +tcp_kill_state(enum tcp_state state) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + LWIP_ASSERT("invalid state", (state == CLOSING) || (state == LAST_ACK)); + + inactivity = 0; + inactive = NULL; + /* Go through the list of active pcbs and get the oldest pcb that is in state + CLOSING/LAST_ACK. */ + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->state == state) { + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + } + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_closing: killing oldest %s PCB %p (%"S32_F")\n", + tcp_state_str[state], (void *)inactive, inactivity)); + /* Don't send a RST, since no data is lost. */ + tcp_abandon(inactive, 0); + } +} + +/** + * Kills the oldest connection that is in TIME_WAIT state. + * Called from tcp_alloc() if no more connections are available. + */ +static void +tcp_kill_timewait(void) +{ + struct tcp_pcb *pcb, *inactive; + u32_t inactivity; + + inactivity = 0; + inactive = NULL; + /* Go through the list of TIME_WAIT pcbs and get the oldest pcb. */ + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + if ((u32_t)(tcp_ticks - pcb->tmr) >= inactivity) { + inactivity = tcp_ticks - pcb->tmr; + inactive = pcb; + } + } + if (inactive != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_kill_timewait: killing oldest TIME-WAIT PCB %p (%"S32_F")\n", + (void *)inactive, inactivity)); + tcp_abort(inactive); + } +} + +/* Called when allocating a pcb fails. + * In this case, we want to handle all pcbs that want to close first: if we can + * now send the FIN (which failed before), the pcb might be in a state that is + * OK for us to now free it. + */ +static void +tcp_handle_closepend(void) +{ + struct tcp_pcb *pcb = tcp_active_pcbs; + + while (pcb != NULL) { + struct tcp_pcb *next = pcb->next; + /* send pending FIN */ + if (pcb->flags & TF_CLOSEPEND) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_handle_closepend: pending FIN\n")); + tcp_clear_flags(pcb, TF_CLOSEPEND); + tcp_close_shutdown_fin(pcb); + } + pcb = next; + } +} + +/** + * Allocate a new tcp_pcb structure. + * + * @param prio priority for the new pcb + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_alloc(u8_t prio) +{ + struct tcp_pcb *pcb; + + LWIP_ASSERT_CORE_LOCKED(); + + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try to send FIN for all pcbs stuck in TF_CLOSEPEND first */ + tcp_handle_closepend(); + + /* Try killing oldest connection in TIME-WAIT. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest TIME-WAIT connection\n")); + tcp_kill_timewait(); + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing oldest connection in LAST-ACK (these wouldn't go to TIME-WAIT). */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest LAST-ACK connection\n")); + tcp_kill_state(LAST_ACK); + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing oldest connection in CLOSING. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing off oldest CLOSING connection\n")); + tcp_kill_state(CLOSING); + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb == NULL) { + /* Try killing oldest active connection with lower priority than the new one. */ + LWIP_DEBUGF(TCP_DEBUG, ("tcp_alloc: killing oldest connection with prio lower than %d\n", prio)); + tcp_kill_prio(prio); + /* Try to allocate a tcp_pcb again. */ + pcb = (struct tcp_pcb *)memp_malloc(MEMP_TCP_PCB); + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed multiple times before */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed multiple times before */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed multiple times before */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + /* adjust err stats: memp_malloc failed above */ + MEMP_STATS_DEC(err, MEMP_TCP_PCB); + } + } + if (pcb != NULL) { + /* zero out the whole pcb, so there is no need to initialize members to zero */ + memset(pcb, 0, sizeof(struct tcp_pcb)); + pcb->prio = prio; + pcb->snd_buf = TCP_SND_BUF; + /* Start with a window that does not need scaling. When window scaling is + enabled and used, the window is enlarged when both sides agree on scaling. */ + pcb->rcv_wnd = pcb->rcv_ann_wnd = TCPWND_MIN16(TCP_WND); + pcb->ttl = TCP_TTL; + /* As initial send MSS, we use TCP_MSS but limit it to 536. + The send MSS is updated when an MSS option is received. */ + pcb->mss = INITIAL_MSS; + pcb->rto = 3000 / TCP_SLOW_INTERVAL; + pcb->sv = 3000 / TCP_SLOW_INTERVAL; + pcb->rtime = -1; + pcb->cwnd = 1; + pcb->tmr = tcp_ticks; + pcb->last_timer = tcp_timer_ctr; + + /* RFC 5681 recommends setting ssthresh abritrarily high and gives an example + of using the largest advertised receive window. We've seen complications with + receiving TCPs that use window scaling and/or window auto-tuning where the + initial advertised window is very small and then grows rapidly once the + connection is established. To avoid these complications, we set ssthresh to the + largest effective cwnd (amount of in-flight data) that the sender can have. */ + pcb->ssthresh = TCP_SND_BUF; + +#if LWIP_CALLBACK_API + pcb->recv = tcp_recv_null; +#endif /* LWIP_CALLBACK_API */ + + /* Init KEEPALIVE timer */ + pcb->keep_idle = TCP_KEEPIDLE_DEFAULT; + +#if LWIP_TCP_KEEPALIVE + pcb->keep_intvl = TCP_KEEPINTVL_DEFAULT; + pcb->keep_cnt = TCP_KEEPCNT_DEFAULT; +#endif /* LWIP_TCP_KEEPALIVE */ + } + return pcb; +} + +/** + * @ingroup tcp_raw + * Creates a new TCP protocol control block but doesn't place it on + * any of the TCP PCB lists. + * The pcb is not put on any list until binding using tcp_bind(). + * If memory is not available for creating the new pcb, NULL is returned. + * + * @internal: Maybe there should be a idle TCP PCB list where these + * PCBs are put on. Port reservation using tcp_bind() is implemented but + * allocated pcbs that are not bound can't be killed automatically if wanting + * to allocate a pcb with higher prio (@see tcp_kill_prio()) + * + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_new(void) +{ + return tcp_alloc(TCP_PRIO_NORMAL); +} + +/** + * @ingroup tcp_raw + * Creates a new TCP protocol control block but doesn't + * place it on any of the TCP PCB lists. + * The pcb is not put on any list until binding using tcp_bind(). + * + * @param type IP address type, see @ref lwip_ip_addr_type definitions. + * If you want to listen to IPv4 and IPv6 (dual-stack) connections, + * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE. + * @return a new tcp_pcb that initially is in state CLOSED + */ +struct tcp_pcb * +tcp_new_ip_type(u8_t type) +{ + struct tcp_pcb *pcb; + pcb = tcp_alloc(TCP_PRIO_NORMAL); +#if LWIP_IPV4 && LWIP_IPV6 + if (pcb != NULL) { + IP_SET_TYPE_VAL(pcb->local_ip, type); + IP_SET_TYPE_VAL(pcb->remote_ip, type); + } +#else + LWIP_UNUSED_ARG(type); +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + return pcb; +} + +/** + * @ingroup tcp_raw + * Specifies the program specific state that should be passed to all + * other callback functions. The "pcb" argument is the current TCP + * connection control block, and the "arg" argument is the argument + * that will be passed to the callbacks. + * + * @param pcb tcp_pcb to set the callback argument + * @param arg void pointer argument to pass to callback functions + */ +void +tcp_arg(struct tcp_pcb *pcb, void *arg) +{ + LWIP_ASSERT_CORE_LOCKED(); + /* This function is allowed to be called for both listen pcbs and + connection pcbs. */ + if (pcb != NULL) { + pcb->callback_arg = arg; + } +} +#if LWIP_CALLBACK_API + +/** + * @ingroup tcp_raw + * Sets the callback function that will be called when new data + * arrives. The callback function will be passed a NULL pbuf to + * indicate that the remote host has closed the connection. If the + * callback function returns ERR_OK or ERR_ABRT it must have + * freed the pbuf, otherwise it must not have freed it. + * + * @param pcb tcp_pcb to set the recv callback + * @param recv callback function to call for this pcb when data is received + */ +void +tcp_recv(struct tcp_pcb *pcb, tcp_recv_fn recv) +{ + LWIP_ASSERT_CORE_LOCKED(); + if (pcb != NULL) { + LWIP_ASSERT("invalid socket state for recv callback", pcb->state != LISTEN); + pcb->recv = recv; + } +} + +/** + * @ingroup tcp_raw + * Specifies the callback function that should be called when data has + * successfully been received (i.e., acknowledged) by the remote + * host. The len argument passed to the callback function gives the + * amount bytes that was acknowledged by the last acknowledgment. + * + * @param pcb tcp_pcb to set the sent callback + * @param sent callback function to call for this pcb when data is successfully sent + */ +void +tcp_sent(struct tcp_pcb *pcb, tcp_sent_fn sent) +{ + LWIP_ASSERT_CORE_LOCKED(); + if (pcb != NULL) { + LWIP_ASSERT("invalid socket state for sent callback", pcb->state != LISTEN); + pcb->sent = sent; + } +} + +/** + * @ingroup tcp_raw + * Used to specify the function that should be called when a fatal error + * has occurred on the connection. + * + * If a connection is aborted because of an error, the application is + * alerted of this event by the err callback. Errors that might abort a + * connection are when there is a shortage of memory. The callback + * function to be called is set using the tcp_err() function. + * + * @note The corresponding pcb is already freed when this callback is called! + * + * @param pcb tcp_pcb to set the err callback + * @param err callback function to call for this pcb when a fatal error + * has occurred on the connection + */ +void +tcp_err(struct tcp_pcb *pcb, tcp_err_fn err) +{ + LWIP_ASSERT_CORE_LOCKED(); + if (pcb != NULL) { + LWIP_ASSERT("invalid socket state for err callback", pcb->state != LISTEN); + pcb->errf = err; + } +} + +/** + * @ingroup tcp_raw + * Used for specifying the function that should be called when a + * LISTENing connection has been connected to another host. + * + * @param pcb tcp_pcb to set the accept callback + * @param accept callback function to call for this pcb when LISTENing + * connection has been connected to another host + */ +void +tcp_accept(struct tcp_pcb *pcb, tcp_accept_fn accept) +{ + LWIP_ASSERT_CORE_LOCKED(); + if ((pcb != NULL) && (pcb->state == LISTEN)) { + struct tcp_pcb_listen *lpcb = (struct tcp_pcb_listen *)pcb; + lpcb->accept = accept; + } +} +#endif /* LWIP_CALLBACK_API */ + + +/** + * @ingroup tcp_raw + * Specifies the polling interval and the callback function that should + * be called to poll the application. The interval is specified in + * number of TCP coarse grained timer shots, which typically occurs + * twice a second. An interval of 10 means that the application would + * be polled every 5 seconds. + * + * When a connection is idle (i.e., no data is either transmitted or + * received), lwIP will repeatedly poll the application by calling a + * specified callback function. This can be used either as a watchdog + * timer for killing connections that have stayed idle for too long, or + * as a method of waiting for memory to become available. For instance, + * if a call to tcp_write() has failed because memory wasn't available, + * the application may use the polling functionality to call tcp_write() + * again when the connection has been idle for a while. + */ +void +tcp_poll(struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("tcp_poll: invalid pcb", pcb != NULL, return); + LWIP_ASSERT("invalid socket state for poll", pcb->state != LISTEN); + +#if LWIP_CALLBACK_API + pcb->poll = poll; +#else /* LWIP_CALLBACK_API */ + LWIP_UNUSED_ARG(poll); +#endif /* LWIP_CALLBACK_API */ + pcb->pollinterval = interval; +} + +/** + * Purges a TCP PCB. Removes any buffered data and frees the buffer memory + * (pcb->ooseq, pcb->unsent and pcb->unacked are freed). + * + * @param pcb tcp_pcb to purge. The pcb itself is not deallocated! + */ +void +tcp_pcb_purge(struct tcp_pcb *pcb) +{ + LWIP_ERROR("tcp_pcb_purge: invalid pcb", pcb != NULL, return); + + if (pcb->state != CLOSED && + pcb->state != TIME_WAIT && + pcb->state != LISTEN) { + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge\n")); + + tcp_backlog_accepted(pcb); + + if (pcb->refused_data != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->refused_data\n")); + pbuf_free(pcb->refused_data); + pcb->refused_data = NULL; + } + if (pcb->unsent != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: not all data sent\n")); + } + if (pcb->unacked != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->unacked\n")); + } +#if TCP_QUEUE_OOSEQ + if (pcb->ooseq != NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_pcb_purge: data left on ->ooseq\n")); + tcp_free_ooseq(pcb); + } +#endif /* TCP_QUEUE_OOSEQ */ + + /* Stop the retransmission timer as it will expect data on unacked + queue if it fires */ + pcb->rtime = -1; + + tcp_segs_free(pcb->unsent); + tcp_segs_free(pcb->unacked); + pcb->unacked = pcb->unsent = NULL; +#if TCP_OVERSIZE + pcb->unsent_oversize = 0; +#endif /* TCP_OVERSIZE */ + } +} + +/** + * Purges the PCB and removes it from a PCB list. Any delayed ACKs are sent first. + * + * @param pcblist PCB list to purge. + * @param pcb tcp_pcb to purge. The pcb itself is NOT deallocated! + */ +void +tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_pcb_remove: invalid pcb", pcb != NULL); + LWIP_ASSERT("tcp_pcb_remove: invalid pcblist", pcblist != NULL); + + TCP_RMV(pcblist, pcb); + + tcp_pcb_purge(pcb); + + /* if there is an outstanding delayed ACKs, send it */ + if ((pcb->state != TIME_WAIT) && + (pcb->state != LISTEN) && + (pcb->flags & TF_ACK_DELAY)) { + tcp_ack_now(pcb); + tcp_output(pcb); + } + + if (pcb->state != LISTEN) { + LWIP_ASSERT("unsent segments leaking", pcb->unsent == NULL); + LWIP_ASSERT("unacked segments leaking", pcb->unacked == NULL); +#if TCP_QUEUE_OOSEQ + LWIP_ASSERT("ooseq segments leaking", pcb->ooseq == NULL); +#endif /* TCP_QUEUE_OOSEQ */ + } + + pcb->state = CLOSED; + /* reset the local port to prevent the pcb from being 'bound' */ + pcb->local_port = 0; + + LWIP_ASSERT("tcp_pcb_remove: tcp_pcbs_sane()", tcp_pcbs_sane()); +} + +/** + * Calculates a new initial sequence number for new connections. + * + * @return u32_t pseudo random sequence number + */ +u32_t +tcp_next_iss(struct tcp_pcb *pcb) +{ +#ifdef LWIP_HOOK_TCP_ISN + LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); + return LWIP_HOOK_TCP_ISN(&pcb->local_ip, pcb->local_port, &pcb->remote_ip, pcb->remote_port); +#else /* LWIP_HOOK_TCP_ISN */ + static u32_t iss = 6510; + + LWIP_ASSERT("tcp_next_iss: invalid pcb", pcb != NULL); + LWIP_UNUSED_ARG(pcb); + + iss += tcp_ticks; /* XXX */ + return iss; +#endif /* LWIP_HOOK_TCP_ISN */ +} + +#if TCP_CALCULATE_EFF_SEND_MSS +/** + * Calculates the effective send mss that can be used for a specific IP address + * by calculating the minimum of TCP_MSS and the mtu (if set) of the target + * netif (if not NULL). + */ +u16_t +tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, const ip_addr_t *dest) +{ + u16_t mss_s; + u16_t mtu; + + LWIP_UNUSED_ARG(dest); /* in case IPv6 is disabled */ + + LWIP_ASSERT("tcp_eff_send_mss_netif: invalid dst_ip", dest != NULL); + +#if LWIP_IPV6 +#if LWIP_IPV4 + if (IP_IS_V6(dest)) +#endif /* LWIP_IPV4 */ + { + /* First look in destination cache, to see if there is a Path MTU. */ + mtu = nd6_get_destination_mtu(ip_2_ip6(dest), outif); + } +#if LWIP_IPV4 + else +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + { + if (outif == NULL) { + return sendmss; + } + mtu = outif->mtu; + } +#endif /* LWIP_IPV4 */ + + if (mtu != 0) { + u16_t offset; +#if LWIP_IPV6 +#if LWIP_IPV4 + if (IP_IS_V6(dest)) +#endif /* LWIP_IPV4 */ + { + offset = IP6_HLEN + TCP_HLEN; + } +#if LWIP_IPV4 + else +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + { + offset = IP_HLEN + TCP_HLEN; + } +#endif /* LWIP_IPV4 */ + mss_s = (mtu > offset) ? (u16_t)(mtu - offset) : 0; + /* RFC 1122, chap 4.2.2.6: + * Eff.snd.MSS = min(SendMSS+20, MMS_S) - TCPhdrsize - IPoptionsize + * We correct for TCP options in tcp_write(), and don't support IP options. + */ + sendmss = LWIP_MIN(sendmss, mss_s); + } + return sendmss; +} +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +/** Helper function for tcp_netif_ip_addr_changed() that iterates a pcb list */ +static void +tcp_netif_ip_addr_changed_pcblist(const ip_addr_t *old_addr, struct tcp_pcb *pcb_list) +{ + struct tcp_pcb *pcb; + pcb = pcb_list; + + LWIP_ASSERT("tcp_netif_ip_addr_changed_pcblist: invalid old_addr", old_addr != NULL); + + while (pcb != NULL) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&pcb->local_ip, old_addr) +#if LWIP_AUTOIP + /* connections to link-local addresses must persist (RFC3927 ch. 1.9) */ + && (!IP_IS_V4_VAL(pcb->local_ip) || !ip4_addr_islinklocal(ip_2_ip4(&pcb->local_ip))) +#endif /* LWIP_AUTOIP */ + ) { + /* this connection must be aborted */ + struct tcp_pcb *next = pcb->next; + LWIP_DEBUGF(NETIF_DEBUG | LWIP_DBG_STATE, ("netif_set_ipaddr: aborting TCP pcb %p\n", (void *)pcb)); + tcp_abort(pcb); + pcb = next; + } else { + pcb = pcb->next; + } + } +} + +/** This function is called from netif.c when address is changed or netif is removed + * + * @param old_addr IP address of the netif before change + * @param new_addr IP address of the netif after change or NULL if netif has been removed + */ +void +tcp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + struct tcp_pcb_listen *lpcb; + + if (!ip_addr_isany(old_addr)) { + tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_active_pcbs); + tcp_netif_ip_addr_changed_pcblist(old_addr, tcp_bound_pcbs); + + if (!ip_addr_isany(new_addr)) { + /* PCB bound to current local interface address? */ + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&lpcb->local_ip, old_addr)) { + /* The PCB is listening to the old ipaddr and + * is set to listen to the new one instead */ + ip_addr_copy(lpcb->local_ip, *new_addr); + } + } + } + } +} + +const char * +tcp_debug_state_str(enum tcp_state s) +{ + return tcp_state_str[s]; +} + +err_t +tcp_tcp_get_tcp_addrinfo(struct tcp_pcb *pcb, int local, ip_addr_t *addr, u16_t *port) +{ + if (pcb) { + if (local) { + if (addr) { + *addr = pcb->local_ip; + } + if (port) { + *port = pcb->local_port; + } + } else { + if (addr) { + *addr = pcb->remote_ip; + } + if (port) { + *port = pcb->remote_port; + } + } + return ERR_OK; + } + return ERR_VAL; +} + +#if TCP_QUEUE_OOSEQ +/* Free all ooseq pbufs (and possibly reset SACK state) */ +void +tcp_free_ooseq(struct tcp_pcb *pcb) +{ + if (pcb->ooseq) { + tcp_segs_free(pcb->ooseq); + pcb->ooseq = NULL; +#if LWIP_TCP_SACK_OUT + memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks)); +#endif /* LWIP_TCP_SACK_OUT */ + } +} +#endif /* TCP_QUEUE_OOSEQ */ + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +/** + * Print a tcp header for debugging purposes. + * + * @param tcphdr pointer to a struct tcp_hdr + */ +void +tcp_debug_print(struct tcp_hdr *tcphdr) +{ + LWIP_DEBUGF(TCP_DEBUG, ("TCP header:\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + lwip_ntohs(tcphdr->src), lwip_ntohs(tcphdr->dest))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (seq no)\n", + lwip_ntohl(tcphdr->seqno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %010"U32_F" | (ack no)\n", + lwip_ntohl(tcphdr->ackno))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| %2"U16_F" | |%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"%"U16_F"| %5"U16_F" | (hdrlen, flags (", + TCPH_HDRLEN(tcphdr), + (u16_t)(TCPH_FLAGS(tcphdr) >> 5 & 1), + (u16_t)(TCPH_FLAGS(tcphdr) >> 4 & 1), + (u16_t)(TCPH_FLAGS(tcphdr) >> 3 & 1), + (u16_t)(TCPH_FLAGS(tcphdr) >> 2 & 1), + (u16_t)(TCPH_FLAGS(tcphdr) >> 1 & 1), + (u16_t)(TCPH_FLAGS(tcphdr) & 1), + lwip_ntohs(tcphdr->wnd))); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_DEBUG, ("), win)\n")); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(TCP_DEBUG, ("| 0x%04"X16_F" | %5"U16_F" | (chksum, urgp)\n", + lwip_ntohs(tcphdr->chksum), lwip_ntohs(tcphdr->urgp))); + LWIP_DEBUGF(TCP_DEBUG, ("+-------------------------------+\n")); +} + +/** + * Print a tcp state for debugging purposes. + * + * @param s enum tcp_state to print + */ +void +tcp_debug_print_state(enum tcp_state s) +{ + LWIP_DEBUGF(TCP_DEBUG, ("State: %s\n", tcp_state_str[s])); +} + +/** + * Print tcp flags for debugging purposes. + * + * @param flags tcp flags, all active flags are printed + */ +void +tcp_debug_print_flags(u8_t flags) +{ + if (flags & TCP_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("FIN ")); + } + if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("SYN ")); + } + if (flags & TCP_RST) { + LWIP_DEBUGF(TCP_DEBUG, ("RST ")); + } + if (flags & TCP_PSH) { + LWIP_DEBUGF(TCP_DEBUG, ("PSH ")); + } + if (flags & TCP_ACK) { + LWIP_DEBUGF(TCP_DEBUG, ("ACK ")); + } + if (flags & TCP_URG) { + LWIP_DEBUGF(TCP_DEBUG, ("URG ")); + } + if (flags & TCP_ECE) { + LWIP_DEBUGF(TCP_DEBUG, ("ECE ")); + } + if (flags & TCP_CWR) { + LWIP_DEBUGF(TCP_DEBUG, ("CWR ")); + } + LWIP_DEBUGF(TCP_DEBUG, ("\n")); +} + +/** + * Print all tcp_pcbs in every list for debugging purposes. + */ +void +tcp_debug_print_pcbs(void) +{ + struct tcp_pcb *pcb; + struct tcp_pcb_listen *pcbl; + + LWIP_DEBUGF(TCP_DEBUG, ("Active PCB states:\n")); + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } + + LWIP_DEBUGF(TCP_DEBUG, ("Listen PCB states:\n")); + for (pcbl = tcp_listen_pcbs.listen_pcbs; pcbl != NULL; pcbl = pcbl->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F" ", pcbl->local_port)); + tcp_debug_print_state(pcbl->state); + } + + LWIP_DEBUGF(TCP_DEBUG, ("TIME-WAIT PCB states:\n")); + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_DEBUGF(TCP_DEBUG, ("Local port %"U16_F", foreign port %"U16_F" snd_nxt %"U32_F" rcv_nxt %"U32_F" ", + pcb->local_port, pcb->remote_port, + pcb->snd_nxt, pcb->rcv_nxt)); + tcp_debug_print_state(pcb->state); + } +} + +/** + * Check state consistency of the tcp_pcb lists. + */ +s16_t +tcp_pcbs_sane(void) +{ + struct tcp_pcb *pcb; + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != LISTEN", pcb->state != LISTEN); + LWIP_ASSERT("tcp_pcbs_sane: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + } + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_pcbs_sane: tw pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + } + return 1; +} +#endif /* TCP_DEBUG */ + +#if LWIP_TCP_PCB_NUM_EXT_ARGS +/** + * @defgroup tcp_raw_extargs ext arguments + * @ingroup tcp_raw + * Additional data storage per tcp pcb\n + * @see @ref tcp_raw + * + * When LWIP_TCP_PCB_NUM_EXT_ARGS is > 0, every tcp pcb (including listen pcb) + * includes a number of additional argument entries in an array. + * + * To support memory management, in addition to a 'void *', callbacks can be + * provided to manage transition from listening pcbs to connections and to + * deallocate memory when a pcb is deallocated (see struct @ref tcp_ext_arg_callbacks). + * + * After allocating this index, use @ref tcp_ext_arg_set and @ref tcp_ext_arg_get + * to store and load arguments from this index for a given pcb. + */ + +static u8_t tcp_ext_arg_id; + +/** + * @ingroup tcp_raw_extargs + * Allocate an index to store data in ext_args member of struct tcp_pcb. + * Returned value is an index in mentioned array. + * The index is *global* over all pcbs! + * + * When @ref LWIP_TCP_PCB_NUM_EXT_ARGS is > 0, every tcp pcb (including listen pcb) + * includes a number of additional argument entries in an array. + * + * To support memory management, in addition to a 'void *', callbacks can be + * provided to manage transition from listening pcbs to connections and to + * deallocate memory when a pcb is deallocated (see struct @ref tcp_ext_arg_callbacks). + * + * After allocating this index, use @ref tcp_ext_arg_set and @ref tcp_ext_arg_get + * to store and load arguments from this index for a given pcb. + * + * @return a unique index into struct tcp_pcb.ext_args + */ +u8_t +tcp_ext_arg_alloc_id(void) +{ + u8_t result = tcp_ext_arg_id; + tcp_ext_arg_id++; + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_TCP_PCB_NUM_EXT_ARGS >= 255 +#error LWIP_TCP_PCB_NUM_EXT_ARGS +#endif + LWIP_ASSERT("Increase LWIP_TCP_PCB_NUM_EXT_ARGS in lwipopts.h", result < LWIP_TCP_PCB_NUM_EXT_ARGS); + return result; +} + +/** + * @ingroup tcp_raw_extargs + * Set callbacks for a given index of ext_args on the specified pcb. + * + * @param pcb tcp_pcb for which to set the callback + * @param id ext_args index to set (allocated via @ref tcp_ext_arg_alloc_id) + * @param callbacks callback table (const since it is referenced, not copied!) + */ +void +tcp_ext_arg_set_callbacks(struct tcp_pcb *pcb, uint8_t id, const struct tcp_ext_arg_callbacks * const callbacks) +{ + LWIP_ASSERT("pcb != NULL", pcb != NULL); + LWIP_ASSERT("id < LWIP_TCP_PCB_NUM_EXT_ARGS", id < LWIP_TCP_PCB_NUM_EXT_ARGS); + LWIP_ASSERT("callbacks != NULL", callbacks != NULL); + + LWIP_ASSERT_CORE_LOCKED(); + + pcb->ext_args[id].callbacks = callbacks; +} + +/** + * @ingroup tcp_raw_extargs + * Set data for a given index of ext_args on the specified pcb. + * + * @param pcb tcp_pcb for which to set the data + * @param id ext_args index to set (allocated via @ref tcp_ext_arg_alloc_id) + * @param arg data pointer to set + */ +void tcp_ext_arg_set(struct tcp_pcb *pcb, uint8_t id, void *arg) +{ + LWIP_ASSERT("pcb != NULL", pcb != NULL); + LWIP_ASSERT("id < LWIP_TCP_PCB_NUM_EXT_ARGS", id < LWIP_TCP_PCB_NUM_EXT_ARGS); + + LWIP_ASSERT_CORE_LOCKED(); + + pcb->ext_args[id].data = arg; +} + +/** + * @ingroup tcp_raw_extargs + * Set data for a given index of ext_args on the specified pcb. + * + * @param pcb tcp_pcb for which to set the data + * @param id ext_args index to set (allocated via @ref tcp_ext_arg_alloc_id) + * @return data pointer at the given index + */ +void *tcp_ext_arg_get(const struct tcp_pcb *pcb, uint8_t id) +{ + LWIP_ASSERT("pcb != NULL", pcb != NULL); + LWIP_ASSERT("id < LWIP_TCP_PCB_NUM_EXT_ARGS", id < LWIP_TCP_PCB_NUM_EXT_ARGS); + + LWIP_ASSERT_CORE_LOCKED(); + + return pcb->ext_args[id].data; +} + +/** This function calls the "destroy" callback for all ext_args once a pcb is + * freed. + */ +static void +tcp_ext_arg_invoke_callbacks_destroyed(struct tcp_pcb_ext_args *ext_args) +{ + int i; + LWIP_ASSERT("ext_args != NULL", ext_args != NULL); + + for (i = 0; i < LWIP_TCP_PCB_NUM_EXT_ARGS; i++) { + if (ext_args[i].callbacks != NULL) { + if (ext_args[i].callbacks->destroy != NULL) { + ext_args[i].callbacks->destroy((u8_t)i, ext_args[i].data); + } + } + } +} + +/** This function calls the "passive_open" callback for all ext_args if a connection + * is in the process of being accepted. This is called just after the SYN is + * received and before a SYN/ACK is sent, to allow to modify the very first + * segment sent even on passive open. Naturally, the "accepted" callback of the + * pcb has not been called yet! + */ +err_t +tcp_ext_arg_invoke_callbacks_passive_open(struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb) +{ + int i; + LWIP_ASSERT("lpcb != NULL", lpcb != NULL); + LWIP_ASSERT("cpcb != NULL", cpcb != NULL); + + for (i = 0; i < LWIP_TCP_PCB_NUM_EXT_ARGS; i++) { + if (lpcb->ext_args[i].callbacks != NULL) { + if (lpcb->ext_args[i].callbacks->passive_open != NULL) { + err_t err = lpcb->ext_args[i].callbacks->passive_open((u8_t)i, lpcb, cpcb); + if (err != ERR_OK) { + return err; + } + } + } + } + return ERR_OK; +} +#endif /* LWIP_TCP_PCB_NUM_EXT_ARGS */ + +#endif /* LWIP_TCP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/tcp_in.c b/Middlewares/Third_Party/LwIP/src/core/tcp_in.c new file mode 100644 index 0000000..428a6f4 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/tcp_in.c @@ -0,0 +1,2178 @@ +/** + * @file + * Transmission Control Protocol, incoming traffic + * + * The input processing functions of the TCP layer. + * + * These functions are generally called in the order (ip_input() ->) + * tcp_input() -> * tcp_process() -> tcp_receive() (-> application). + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/priv/tcp_priv.h" +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/inet_chksum.h" +#include "lwip/stats.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#if LWIP_ND6_TCP_REACHABILITY_HINTS +#include "lwip/nd6.h" +#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */ + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +/** Initial CWND calculation as defined RFC 2581 */ +#define LWIP_TCP_CALC_INITIAL_CWND(mss) ((tcpwnd_size_t)LWIP_MIN((4U * (mss)), LWIP_MAX((2U * (mss)), 4380U))) + +/* These variables are global to all functions involved in the input + processing of TCP segments. They are set by the tcp_input() + function. */ +static struct tcp_seg inseg; +static struct tcp_hdr *tcphdr; +static u16_t tcphdr_optlen; +static u16_t tcphdr_opt1len; +static u8_t *tcphdr_opt2; +static u16_t tcp_optidx; +static u32_t seqno, ackno; +static tcpwnd_size_t recv_acked; +static u16_t tcplen; +static u8_t flags; + +static u8_t recv_flags; +static struct pbuf *recv_data; + +struct tcp_pcb *tcp_input_pcb; + +/* Forward declarations. */ +static err_t tcp_process(struct tcp_pcb *pcb); +static void tcp_receive(struct tcp_pcb *pcb); +static void tcp_parseopt(struct tcp_pcb *pcb); + +static void tcp_listen_input(struct tcp_pcb_listen *pcb); +static void tcp_timewait_input(struct tcp_pcb *pcb); + +static int tcp_input_delayed_close(struct tcp_pcb *pcb); + +#if LWIP_TCP_SACK_OUT +static void tcp_add_sack(struct tcp_pcb *pcb, u32_t left, u32_t right); +static void tcp_remove_sacks_lt(struct tcp_pcb *pcb, u32_t seq); +#if defined(TCP_OOSEQ_BYTES_LIMIT) || defined(TCP_OOSEQ_PBUFS_LIMIT) +static void tcp_remove_sacks_gt(struct tcp_pcb *pcb, u32_t seq); +#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */ +#endif /* LWIP_TCP_SACK_OUT */ + +/** + * The initial input processing of TCP. It verifies the TCP header, demultiplexes + * the segment between the PCBs and passes it on to tcp_process(), which implements + * the TCP finite state machine. This function is called by the IP layer (in + * ip_input()). + * + * @param p received TCP segment to process (p->payload pointing to the TCP header) + * @param inp network interface on which this segment was received + */ +void +tcp_input(struct pbuf *p, struct netif *inp) +{ + struct tcp_pcb *pcb, *prev; + struct tcp_pcb_listen *lpcb; +#if SO_REUSE + struct tcp_pcb *lpcb_prev = NULL; + struct tcp_pcb_listen *lpcb_any = NULL; +#endif /* SO_REUSE */ + u8_t hdrlen_bytes; + err_t err; + + LWIP_UNUSED_ARG(inp); + LWIP_ASSERT_CORE_LOCKED(); + LWIP_ASSERT("tcp_input: invalid pbuf", p != NULL); + + PERF_START; + + TCP_STATS_INC(tcp.recv); + MIB2_STATS_INC(mib2.tcpinsegs); + + tcphdr = (struct tcp_hdr *)p->payload; + +#if TCP_INPUT_DEBUG + tcp_debug_print(tcphdr); +#endif + + /* Check that TCP header fits in payload */ + if (p->len < TCP_HLEN) { + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: short packet (%"U16_F" bytes) discarded\n", p->tot_len)); + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + + /* Don't even process incoming broadcasts/multicasts. */ + if (ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()) || + ip_addr_ismulticast(ip_current_dest_addr())) { + TCP_STATS_INC(tcp.proterr); + goto dropped; + } + +#if CHECKSUM_CHECK_TCP + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_TCP) { + /* Verify TCP checksum. */ + u16_t chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, + ip_current_src_addr(), ip_current_dest_addr()); + if (chksum != 0) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packet discarded due to failing checksum 0x%04"X16_F"\n", + chksum)); + tcp_debug_print(tcphdr); + TCP_STATS_INC(tcp.chkerr); + goto dropped; + } + } +#endif /* CHECKSUM_CHECK_TCP */ + + /* sanity-check header length */ + hdrlen_bytes = TCPH_HDRLEN_BYTES(tcphdr); + if ((hdrlen_bytes < TCP_HLEN) || (hdrlen_bytes > p->tot_len)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: invalid header length (%"U16_F")\n", (u16_t)hdrlen_bytes)); + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + + /* Move the payload pointer in the pbuf so that it points to the + TCP data instead of the TCP header. */ + tcphdr_optlen = (u16_t)(hdrlen_bytes - TCP_HLEN); + tcphdr_opt2 = NULL; + if (p->len >= hdrlen_bytes) { + /* all options are in the first pbuf */ + tcphdr_opt1len = tcphdr_optlen; + pbuf_remove_header(p, hdrlen_bytes); /* cannot fail */ + } else { + u16_t opt2len; + /* TCP header fits into first pbuf, options don't - data is in the next pbuf */ + /* there must be a next pbuf, due to hdrlen_bytes sanity check above */ + LWIP_ASSERT("p->next != NULL", p->next != NULL); + + /* advance over the TCP header (cannot fail) */ + pbuf_remove_header(p, TCP_HLEN); + + /* determine how long the first and second parts of the options are */ + tcphdr_opt1len = p->len; + opt2len = (u16_t)(tcphdr_optlen - tcphdr_opt1len); + + /* options continue in the next pbuf: set p to zero length and hide the + options in the next pbuf (adjusting p->tot_len) */ + pbuf_remove_header(p, tcphdr_opt1len); + + /* check that the options fit in the second pbuf */ + if (opt2len > p->next->len) { + /* drop short packets */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: options overflow second pbuf (%"U16_F" bytes)\n", p->next->len)); + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + + /* remember the pointer to the second part of the options */ + tcphdr_opt2 = (u8_t *)p->next->payload; + + /* advance p->next to point after the options, and manually + adjust p->tot_len to keep it consistent with the changed p->next */ + pbuf_remove_header(p->next, opt2len); + p->tot_len = (u16_t)(p->tot_len - opt2len); + + LWIP_ASSERT("p->len == 0", p->len == 0); + LWIP_ASSERT("p->tot_len == p->next->tot_len", p->tot_len == p->next->tot_len); + } + + /* Convert fields in TCP header to host byte order. */ + tcphdr->src = lwip_ntohs(tcphdr->src); + tcphdr->dest = lwip_ntohs(tcphdr->dest); + seqno = tcphdr->seqno = lwip_ntohl(tcphdr->seqno); + ackno = tcphdr->ackno = lwip_ntohl(tcphdr->ackno); + tcphdr->wnd = lwip_ntohs(tcphdr->wnd); + + flags = TCPH_FLAGS(tcphdr); + tcplen = p->tot_len; + if (flags & (TCP_FIN | TCP_SYN)) { + tcplen++; + if (tcplen < p->tot_len) { + /* u16_t overflow, cannot handle this */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: length u16_t overflow, cannot handle this\n")); + TCP_STATS_INC(tcp.lenerr); + goto dropped; + } + } + + /* Demultiplex an incoming segment. First, we check if it is destined + for an active connection. */ + prev = NULL; + + for (pcb = tcp_active_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: active pcb->state != CLOSED", pcb->state != CLOSED); + LWIP_ASSERT("tcp_input: active pcb->state != TIME-WAIT", pcb->state != TIME_WAIT); + LWIP_ASSERT("tcp_input: active pcb->state != LISTEN", pcb->state != LISTEN); + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + prev = pcb; + continue; + } + + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + LWIP_ASSERT("tcp_input: pcb->next != pcb (before cache)", pcb->next != pcb); + if (prev != NULL) { + prev->next = pcb->next; + pcb->next = tcp_active_pcbs; + tcp_active_pcbs = pcb; + } else { + TCP_STATS_INC(tcp.cachehit); + } + LWIP_ASSERT("tcp_input: pcb->next != pcb (after cache)", pcb->next != pcb); + break; + } + prev = pcb; + } + + if (pcb == NULL) { + /* If it did not go to an active connection, we check the connections + in the TIME-WAIT state. */ + for (pcb = tcp_tw_pcbs; pcb != NULL; pcb = pcb->next) { + LWIP_ASSERT("tcp_input: TIME-WAIT pcb->state == TIME-WAIT", pcb->state == TIME_WAIT); + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + continue; + } + + if (pcb->remote_port == tcphdr->src && + pcb->local_port == tcphdr->dest && + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()) && + ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + /* We don't really care enough to move this PCB to the front + of the list since we are not very likely to receive that + many segments for connections in TIME-WAIT. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for TIME_WAITing connection.\n")); +#ifdef LWIP_HOOK_TCP_INPACKET_PCB + if (LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, tcphdr_opt1len, + tcphdr_opt2, p) == ERR_OK) +#endif + { + tcp_timewait_input(pcb); + } + pbuf_free(p); + return; + } + } + + /* Finally, if we still did not get a match, we check all PCBs that + are LISTENing for incoming connections. */ + prev = NULL; + for (lpcb = tcp_listen_pcbs.listen_pcbs; lpcb != NULL; lpcb = lpcb->next) { + /* check if PCB is bound to specific netif */ + if ((lpcb->netif_idx != NETIF_NO_INDEX) && + (lpcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + prev = (struct tcp_pcb *)lpcb; + continue; + } + + if (lpcb->local_port == tcphdr->dest) { + if (IP_IS_ANY_TYPE_VAL(lpcb->local_ip)) { + /* found an ANY TYPE (IPv4/IPv6) match */ +#if SO_REUSE + lpcb_any = lpcb; + lpcb_prev = prev; +#else /* SO_REUSE */ + break; +#endif /* SO_REUSE */ + } else if (IP_ADDR_PCB_VERSION_MATCH_EXACT(lpcb, ip_current_dest_addr())) { + if (ip_addr_cmp(&lpcb->local_ip, ip_current_dest_addr())) { + /* found an exact match */ + break; + } else if (ip_addr_isany(&lpcb->local_ip)) { + /* found an ANY-match */ +#if SO_REUSE + lpcb_any = lpcb; + lpcb_prev = prev; +#else /* SO_REUSE */ + break; +#endif /* SO_REUSE */ + } + } + } + prev = (struct tcp_pcb *)lpcb; + } +#if SO_REUSE + /* first try specific local IP */ + if (lpcb == NULL) { + /* only pass to ANY if no specific local IP has been found */ + lpcb = lpcb_any; + prev = lpcb_prev; + } +#endif /* SO_REUSE */ + if (lpcb != NULL) { + /* Move this PCB to the front of the list so that subsequent + lookups will be faster (we exploit locality in TCP segment + arrivals). */ + if (prev != NULL) { + ((struct tcp_pcb_listen *)prev)->next = lpcb->next; + /* our successor is the remainder of the listening list */ + lpcb->next = tcp_listen_pcbs.listen_pcbs; + /* put this listening pcb at the head of the listening list */ + tcp_listen_pcbs.listen_pcbs = lpcb; + } else { + TCP_STATS_INC(tcp.cachehit); + } + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: packed for LISTENing connection.\n")); +#ifdef LWIP_HOOK_TCP_INPACKET_PCB + if (LWIP_HOOK_TCP_INPACKET_PCB((struct tcp_pcb *)lpcb, tcphdr, tcphdr_optlen, + tcphdr_opt1len, tcphdr_opt2, p) == ERR_OK) +#endif + { + tcp_listen_input(lpcb); + } + pbuf_free(p); + return; + } + } + +#if TCP_INPUT_DEBUG + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("+-+-+-+-+-+-+-+-+-+-+-+-+-+- tcp_input: flags ")); + tcp_debug_print_flags(TCPH_FLAGS(tcphdr)); + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n")); +#endif /* TCP_INPUT_DEBUG */ + + +#ifdef LWIP_HOOK_TCP_INPACKET_PCB + if ((pcb != NULL) && LWIP_HOOK_TCP_INPACKET_PCB(pcb, tcphdr, tcphdr_optlen, + tcphdr_opt1len, tcphdr_opt2, p) != ERR_OK) { + pbuf_free(p); + return; + } +#endif + if (pcb != NULL) { + /* The incoming segment belongs to a connection. */ +#if TCP_INPUT_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_INPUT_DEBUG */ + + /* Set up a tcp_seg structure. */ + inseg.next = NULL; + inseg.len = p->tot_len; + inseg.p = p; + inseg.tcphdr = tcphdr; + + recv_data = NULL; + recv_flags = 0; + recv_acked = 0; + + if (flags & TCP_PSH) { + p->flags |= PBUF_FLAG_PUSH; + } + + /* If there is data which was previously "refused" by upper layer */ + if (pcb->refused_data != NULL) { + if ((tcp_process_refused_data(pcb) == ERR_ABRT) || + ((pcb->refused_data != NULL) && (tcplen > 0))) { + /* pcb has been aborted or refused data is still refused and the new + segment contains data */ + if (pcb->rcv_ann_wnd == 0) { + /* this is a zero-window probe, we respond to it with current RCV.NXT + and drop the data segment */ + tcp_send_empty_ack(pcb); + } + TCP_STATS_INC(tcp.drop); + MIB2_STATS_INC(mib2.tcpinerrs); + goto aborted; + } + } + tcp_input_pcb = pcb; + err = tcp_process(pcb); + /* A return value of ERR_ABRT means that tcp_abort() was called + and that the pcb has been freed. If so, we don't do anything. */ + if (err != ERR_ABRT) { + if (recv_flags & TF_RESET) { + /* TF_RESET means that the connection was reset by the other + end. We then call the error callback to inform the + application that the connection is dead before we + deallocate the PCB. */ + TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_RST); + tcp_pcb_remove(&tcp_active_pcbs, pcb); + tcp_free(pcb); + } else { + err = ERR_OK; + /* If the application has registered a "sent" function to be + called when new send buffer space is available, we call it + now. */ + if (recv_acked > 0) { + u16_t acked16; +#if LWIP_WND_SCALE + /* recv_acked is u32_t but the sent callback only takes a u16_t, + so we might have to call it multiple times. */ + u32_t acked = recv_acked; + while (acked > 0) { + acked16 = (u16_t)LWIP_MIN(acked, 0xffffu); + acked -= acked16; +#else + { + acked16 = recv_acked; +#endif + TCP_EVENT_SENT(pcb, (u16_t)acked16, err); + if (err == ERR_ABRT) { + goto aborted; + } + } + recv_acked = 0; + } + if (tcp_input_delayed_close(pcb)) { + goto aborted; + } +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + while (recv_data != NULL) { + struct pbuf *rest = NULL; + pbuf_split_64k(recv_data, &rest); +#else /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + if (recv_data != NULL) { +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + + LWIP_ASSERT("pcb->refused_data == NULL", pcb->refused_data == NULL); + if (pcb->flags & TF_RXCLOSED) { + /* received data although already closed -> abort (send RST) to + notify the remote host that not all data has been processed */ + pbuf_free(recv_data); +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_free(rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + tcp_abort(pcb); + goto aborted; + } + + /* Notify application that data has been received. */ + TCP_EVENT_RECV(pcb, recv_data, ERR_OK, err); + if (err == ERR_ABRT) { +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_free(rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + goto aborted; + } + + /* If the upper layer can't receive this data, store it */ + if (err != ERR_OK) { +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + if (rest != NULL) { + pbuf_cat(recv_data, rest); + } +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + pcb->refused_data = recv_data; + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_input: keep incoming packet, because pcb is \"full\"\n")); +#if TCP_QUEUE_OOSEQ && LWIP_WND_SCALE + break; + } else { + /* Upper layer received the data, go on with the rest if > 64K */ + recv_data = rest; +#endif /* TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + } + } + + /* If a FIN segment was received, we call the callback + function with a NULL buffer to indicate EOF. */ + if (recv_flags & TF_GOT_FIN) { + if (pcb->refused_data != NULL) { + /* Delay this if we have refused data. */ + pcb->refused_data->flags |= PBUF_FLAG_TCP_FIN; + } else { + /* correct rcv_wnd as the application won't call tcp_recved() + for the FIN's seqno */ + if (pcb->rcv_wnd != TCP_WND_MAX(pcb)) { + pcb->rcv_wnd++; + } + TCP_EVENT_CLOSED(pcb, err); + if (err == ERR_ABRT) { + goto aborted; + } + } + } + + tcp_input_pcb = NULL; + if (tcp_input_delayed_close(pcb)) { + goto aborted; + } + /* Try to send something out. */ + tcp_output(pcb); +#if TCP_INPUT_DEBUG +#if TCP_DEBUG + tcp_debug_print_state(pcb->state); +#endif /* TCP_DEBUG */ +#endif /* TCP_INPUT_DEBUG */ + } + } + /* Jump target if pcb has been aborted in a callback (by calling tcp_abort()). + Below this line, 'pcb' may not be dereferenced! */ +aborted: + tcp_input_pcb = NULL; + recv_data = NULL; + + /* give up our reference to inseg.p */ + if (inseg.p != NULL) { + pbuf_free(inseg.p); + inseg.p = NULL; + } + } else { + /* If no matching PCB was found, send a TCP RST (reset) to the + sender. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_input: no PCB match found, resetting.\n")); + if (!(TCPH_FLAGS(tcphdr) & TCP_RST)) { + TCP_STATS_INC(tcp.proterr); + TCP_STATS_INC(tcp.drop); + tcp_rst(NULL, ackno, seqno + tcplen, ip_current_dest_addr(), + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + } + pbuf_free(p); + } + + LWIP_ASSERT("tcp_input: tcp_pcbs_sane()", tcp_pcbs_sane()); + PERF_STOP("tcp_input"); + return; +dropped: + TCP_STATS_INC(tcp.drop); + MIB2_STATS_INC(mib2.tcpinerrs); + pbuf_free(p); +} + +/** Called from tcp_input to check for TF_CLOSED flag. This results in closing + * and deallocating a pcb at the correct place to ensure noone references it + * any more. + * @returns 1 if the pcb has been closed and deallocated, 0 otherwise + */ +static int +tcp_input_delayed_close(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_input_delayed_close: invalid pcb", pcb != NULL); + + if (recv_flags & TF_CLOSED) { + /* The connection has been closed and we will deallocate the + PCB. */ + if (!(pcb->flags & TF_RXCLOSED)) { + /* Connection closed although the application has only shut down the + tx side: call the PCB's err callback and indicate the closure to + ensure the application doesn't continue using the PCB. */ + TCP_EVENT_ERR(pcb->state, pcb->errf, pcb->callback_arg, ERR_CLSD); + } + tcp_pcb_remove(&tcp_active_pcbs, pcb); + tcp_free(pcb); + return 1; + } + return 0; +} + +/** + * Called by tcp_input() when a segment arrives for a listening + * connection (from tcp_input()). + * + * @param pcb the tcp_pcb_listen for which a segment arrived + * + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static void +tcp_listen_input(struct tcp_pcb_listen *pcb) +{ + struct tcp_pcb *npcb; + u32_t iss; + err_t rc; + + if (flags & TCP_RST) { + /* An incoming RST should be ignored. Return. */ + return; + } + + LWIP_ASSERT("tcp_listen_input: invalid pcb", pcb != NULL); + + /* In the LISTEN state, we check for incoming SYN segments, + creates a new PCB, and responds with a SYN|ACK. */ + if (flags & TCP_ACK) { + /* For incoming segments with the ACK flag set, respond with a + RST. */ + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_listen_input: ACK in LISTEN, sending reset\n")); + tcp_rst((const struct tcp_pcb *)pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + } else if (flags & TCP_SYN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection request %"U16_F" -> %"U16_F".\n", tcphdr->src, tcphdr->dest)); +#if TCP_LISTEN_BACKLOG + if (pcb->accepts_pending >= pcb->backlog) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: listen backlog exceeded for port %"U16_F"\n", tcphdr->dest)); + return; + } +#endif /* TCP_LISTEN_BACKLOG */ + npcb = tcp_alloc(pcb->prio); + /* If a new PCB could not be created (probably due to lack of memory), + we don't do anything, but rely on the sender will retransmit the + SYN at a time when we have more memory available. */ + if (npcb == NULL) { + err_t err; + LWIP_DEBUGF(TCP_DEBUG, ("tcp_listen_input: could not allocate PCB\n")); + TCP_STATS_INC(tcp.memerr); + TCP_EVENT_ACCEPT(pcb, NULL, pcb->callback_arg, ERR_MEM, err); + LWIP_UNUSED_ARG(err); /* err not useful here */ + return; + } +#if TCP_LISTEN_BACKLOG + pcb->accepts_pending++; + tcp_set_flags(npcb, TF_BACKLOGPEND); +#endif /* TCP_LISTEN_BACKLOG */ + /* Set up the new PCB. */ + ip_addr_copy(npcb->local_ip, *ip_current_dest_addr()); + ip_addr_copy(npcb->remote_ip, *ip_current_src_addr()); + npcb->local_port = pcb->local_port; + npcb->remote_port = tcphdr->src; + npcb->state = SYN_RCVD; + npcb->rcv_nxt = seqno + 1; + npcb->rcv_ann_right_edge = npcb->rcv_nxt; + iss = tcp_next_iss(npcb); + npcb->snd_wl2 = iss; + npcb->snd_nxt = iss; + npcb->lastack = iss; + npcb->snd_lbb = iss; + npcb->snd_wl1 = seqno - 1;/* initialise to seqno-1 to force window update */ + npcb->callback_arg = pcb->callback_arg; +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + npcb->listener = pcb; +#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ + /* inherit socket options */ + npcb->so_options = pcb->so_options & SOF_INHERITED; + npcb->netif_idx = pcb->netif_idx; + /* Register the new PCB so that we can begin receiving segments + for it. */ + TCP_REG_ACTIVE(npcb); + + /* Parse any options in the SYN. */ + tcp_parseopt(npcb); + npcb->snd_wnd = tcphdr->wnd; + npcb->snd_wnd_max = npcb->snd_wnd; + +#if TCP_CALCULATE_EFF_SEND_MSS + npcb->mss = tcp_eff_send_mss(npcb->mss, &npcb->local_ip, &npcb->remote_ip); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + MIB2_STATS_INC(mib2.tcppassiveopens); + +#if LWIP_TCP_PCB_NUM_EXT_ARGS + if (tcp_ext_arg_invoke_callbacks_passive_open(pcb, npcb) != ERR_OK) { + tcp_abandon(npcb, 0); + return; + } +#endif + + /* Send a SYN|ACK together with the MSS option. */ + rc = tcp_enqueue_flags(npcb, TCP_SYN | TCP_ACK); + if (rc != ERR_OK) { + tcp_abandon(npcb, 0); + return; + } + tcp_output(npcb); + } + return; +} + +/** + * Called by tcp_input() when a segment arrives for a connection in + * TIME_WAIT. + * + * @param pcb the tcp_pcb for which a segment arrived + * + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static void +tcp_timewait_input(struct tcp_pcb *pcb) +{ + /* RFC 1337: in TIME_WAIT, ignore RST and ACK FINs + any 'acceptable' segments */ + /* RFC 793 3.9 Event Processing - Segment Arrives: + * - first check sequence number - we skip that one in TIME_WAIT (always + * acceptable since we only send ACKs) + * - second check the RST bit (... return) */ + if (flags & TCP_RST) { + return; + } + + LWIP_ASSERT("tcp_timewait_input: invalid pcb", pcb != NULL); + + /* - fourth, check the SYN bit, */ + if (flags & TCP_SYN) { + /* If an incoming segment is not acceptable, an acknowledgment + should be sent in reply */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd)) { + /* If the SYN is in the window it is an error, send a reset */ + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + return; + } + } else if (flags & TCP_FIN) { + /* - eighth, check the FIN bit: Remain in the TIME-WAIT state. + Restart the 2 MSL time-wait timeout.*/ + pcb->tmr = tcp_ticks; + } + + if ((tcplen > 0)) { + /* Acknowledge data, FIN or out-of-window SYN */ + tcp_ack_now(pcb); + tcp_output(pcb); + } + return; +} + +/** + * Implements the TCP state machine. Called by tcp_input. In some + * states tcp_receive() is called to receive data. The tcp_seg + * argument will be freed by the caller (tcp_input()) unless the + * recv_data pointer in the pcb is set. + * + * @param pcb the tcp_pcb for which a segment arrived + * + * @note the segment which arrived is saved in global variables, therefore only the pcb + * involved is passed as a parameter to this function + */ +static err_t +tcp_process(struct tcp_pcb *pcb) +{ + struct tcp_seg *rseg; + u8_t acceptable = 0; + err_t err; + + err = ERR_OK; + + LWIP_ASSERT("tcp_process: invalid pcb", pcb != NULL); + + /* Process incoming RST segments. */ + if (flags & TCP_RST) { + /* First, determine if the reset is acceptable. */ + if (pcb->state == SYN_SENT) { + /* "In the SYN-SENT state (a RST received in response to an initial SYN), + the RST is acceptable if the ACK field acknowledges the SYN." */ + if (ackno == pcb->snd_nxt) { + acceptable = 1; + } + } else { + /* "In all states except SYN-SENT, all reset (RST) segments are validated + by checking their SEQ-fields." */ + if (seqno == pcb->rcv_nxt) { + acceptable = 1; + } else if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + pcb->rcv_nxt + pcb->rcv_wnd)) { + /* If the sequence number is inside the window, we send a challenge ACK + and wait for a re-send with matching sequence number. + This follows RFC 5961 section 3.2 and addresses CVE-2004-0230 + (RST spoofing attack), which is present in RFC 793 RST handling. */ + tcp_ack_now(pcb); + } + } + + if (acceptable) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: Connection RESET\n")); + LWIP_ASSERT("tcp_input: pcb->state != CLOSED", pcb->state != CLOSED); + recv_flags |= TF_RESET; + tcp_clear_flags(pcb, TF_ACK_DELAY); + return ERR_RST; + } else { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + LWIP_DEBUGF(TCP_DEBUG, ("tcp_process: unacceptable reset seqno %"U32_F" rcv_nxt %"U32_F"\n", + seqno, pcb->rcv_nxt)); + return ERR_OK; + } + } + + if ((flags & TCP_SYN) && (pcb->state != SYN_SENT && pcb->state != SYN_RCVD)) { + /* Cope with new connection attempt after remote end crashed */ + tcp_ack_now(pcb); + return ERR_OK; + } + + if ((pcb->flags & TF_RXCLOSED) == 0) { + /* Update the PCB (in)activity timer unless rx is closed (see tcp_shutdown) */ + pcb->tmr = tcp_ticks; + } + pcb->keep_cnt_sent = 0; + pcb->persist_probe = 0; + + tcp_parseopt(pcb); + + /* Do different things depending on the TCP state. */ + switch (pcb->state) { + case SYN_SENT: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("SYN-SENT: ackno %"U32_F" pcb->snd_nxt %"U32_F" unacked %"U32_F"\n", ackno, + pcb->snd_nxt, lwip_ntohl(pcb->unacked->tcphdr->seqno))); + /* received SYN ACK with expected sequence number? */ + if ((flags & TCP_ACK) && (flags & TCP_SYN) + && (ackno == pcb->lastack + 1)) { + pcb->rcv_nxt = seqno + 1; + pcb->rcv_ann_right_edge = pcb->rcv_nxt; + pcb->lastack = ackno; + pcb->snd_wnd = tcphdr->wnd; + pcb->snd_wnd_max = pcb->snd_wnd; + pcb->snd_wl1 = seqno - 1; /* initialise to seqno - 1 to force window update */ + pcb->state = ESTABLISHED; + +#if TCP_CALCULATE_EFF_SEND_MSS + pcb->mss = tcp_eff_send_mss(pcb->mss, &pcb->local_ip, &pcb->remote_ip); +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + + pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SENT): cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + LWIP_ASSERT("pcb->snd_queuelen > 0", (pcb->snd_queuelen > 0)); + --pcb->snd_queuelen; + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_process: SYN-SENT --queuelen %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); + rseg = pcb->unacked; + if (rseg == NULL) { + /* might happen if tcp_output fails in tcp_rexmit_rto() + in which case the segment is on the unsent list */ + rseg = pcb->unsent; + LWIP_ASSERT("no segment to free", rseg != NULL); + pcb->unsent = rseg->next; + } else { + pcb->unacked = rseg->next; + } + tcp_seg_free(rseg); + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if (pcb->unacked == NULL) { + pcb->rtime = -1; + } else { + pcb->rtime = 0; + pcb->nrtx = 0; + } + + /* Call the user specified function to call when successfully + * connected. */ + TCP_EVENT_CONNECTED(pcb, ERR_OK, err); + if (err == ERR_ABRT) { + return ERR_ABRT; + } + tcp_ack_now(pcb); + } + /* received ACK? possibly a half-open connection */ + else if (flags & TCP_ACK) { + /* send a RST to bring the other side in a non-synchronized state. */ + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + /* Resend SYN immediately (don't wait for rto timeout) to establish + connection faster, but do not send more SYNs than we otherwise would + have, or we might get caught in a loop on loopback interfaces. */ + if (pcb->nrtx < TCP_SYNMAXRTX) { + pcb->rtime = 0; + tcp_rexmit_rto(pcb); + } + } + break; + case SYN_RCVD: + if (flags & TCP_ACK) { + /* expected ACK number? */ + if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + pcb->state = ESTABLISHED; + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection established %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + if (pcb->listener == NULL) { + /* listen pcb might be closed by now */ + err = ERR_VAL; + } else +#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ + { +#if LWIP_CALLBACK_API + LWIP_ASSERT("pcb->listener->accept != NULL", pcb->listener->accept != NULL); +#endif + tcp_backlog_accepted(pcb); + /* Call the accept function. */ + TCP_EVENT_ACCEPT(pcb->listener, pcb, pcb->callback_arg, ERR_OK, err); + } + if (err != ERR_OK) { + /* If the accept function returns with an error, we abort + * the connection. */ + /* Already aborted? */ + if (err != ERR_ABRT) { + tcp_abort(pcb); + } + return ERR_ABRT; + } + /* If there was any data contained within this ACK, + * we'd better pass it on to the application as well. */ + tcp_receive(pcb); + + /* Prevent ACK for SYN to generate a sent event */ + if (recv_acked != 0) { + recv_acked--; + } + + pcb->cwnd = LWIP_TCP_CALC_INITIAL_CWND(pcb->mss); + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_process (SYN_RCVD): cwnd %"TCPWNDSIZE_F + " ssthresh %"TCPWNDSIZE_F"\n", + pcb->cwnd, pcb->ssthresh)); + + if (recv_flags & TF_GOT_FIN) { + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + } else { + /* incorrect ACK number, send RST */ + tcp_rst(pcb, ackno, seqno + tcplen, ip_current_dest_addr(), + ip_current_src_addr(), tcphdr->dest, tcphdr->src); + } + } else if ((flags & TCP_SYN) && (seqno == pcb->rcv_nxt - 1)) { + /* Looks like another copy of the SYN - retransmit our SYN-ACK */ + tcp_rexmit(pcb); + } + break; + case CLOSE_WAIT: + /* FALLTHROUGH */ + case ESTABLISHED: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { /* passive close */ + tcp_ack_now(pcb); + pcb->state = CLOSE_WAIT; + } + break; + case FIN_WAIT_1: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { + if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + pcb->unsent == NULL) { + LWIP_DEBUGF(TCP_DEBUG, + ("TCP connection closed: FIN_WAIT_1 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV_ACTIVE(pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } else { + tcp_ack_now(pcb); + pcb->state = CLOSING; + } + } else if ((flags & TCP_ACK) && (ackno == pcb->snd_nxt) && + pcb->unsent == NULL) { + pcb->state = FIN_WAIT_2; + } + break; + case FIN_WAIT_2: + tcp_receive(pcb); + if (recv_flags & TF_GOT_FIN) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: FIN_WAIT_2 %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_ack_now(pcb); + tcp_pcb_purge(pcb); + TCP_RMV_ACTIVE(pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case CLOSING: + tcp_receive(pcb); + if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: CLOSING %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + tcp_pcb_purge(pcb); + TCP_RMV_ACTIVE(pcb); + pcb->state = TIME_WAIT; + TCP_REG(&tcp_tw_pcbs, pcb); + } + break; + case LAST_ACK: + tcp_receive(pcb); + if ((flags & TCP_ACK) && ackno == pcb->snd_nxt && pcb->unsent == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("TCP connection closed: LAST_ACK %"U16_F" -> %"U16_F".\n", inseg.tcphdr->src, inseg.tcphdr->dest)); + /* bugfix #21699: don't set pcb->state to CLOSED here or we risk leaking segments */ + recv_flags |= TF_CLOSED; + } + break; + default: + break; + } + return ERR_OK; +} + +#if TCP_QUEUE_OOSEQ +/** + * Insert segment into the list (segments covered with new one will be deleted) + * + * Called from tcp_receive() + */ +static void +tcp_oos_insert_segment(struct tcp_seg *cseg, struct tcp_seg *next) +{ + struct tcp_seg *old_seg; + + LWIP_ASSERT("tcp_oos_insert_segment: invalid cseg", cseg != NULL); + + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + /* received segment overlaps all following segments */ + tcp_segs_free(next); + next = NULL; + } else { + /* delete some following segments + oos queue may have segments with FIN flag */ + while (next && + TCP_SEQ_GEQ((seqno + cseg->len), + (next->tcphdr->seqno + next->len))) { + /* cseg with FIN already processed */ + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + TCPH_SET_FLAG(cseg->tcphdr, TCP_FIN); + } + old_seg = next; + next = next->next; + tcp_seg_free(old_seg); + } + if (next && + TCP_SEQ_GT(seqno + cseg->len, next->tcphdr->seqno)) { + /* We need to trim the incoming segment. */ + cseg->len = (u16_t)(next->tcphdr->seqno - seqno); + pbuf_realloc(cseg->p, cseg->len); + } + } + cseg->next = next; +} +#endif /* TCP_QUEUE_OOSEQ */ + +/** Remove segments from a list if the incoming ACK acknowledges them */ +static struct tcp_seg * +tcp_free_acked_segments(struct tcp_pcb *pcb, struct tcp_seg *seg_list, const char *dbg_list_name, + struct tcp_seg *dbg_other_seg_list) +{ + struct tcp_seg *next; + u16_t clen; + + LWIP_UNUSED_ARG(dbg_list_name); + LWIP_UNUSED_ARG(dbg_other_seg_list); + + while (seg_list != NULL && + TCP_SEQ_LEQ(lwip_ntohl(seg_list->tcphdr->seqno) + + TCP_TCPLEN(seg_list), ackno)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: removing %"U32_F":%"U32_F" from pcb->%s\n", + lwip_ntohl(seg_list->tcphdr->seqno), + lwip_ntohl(seg_list->tcphdr->seqno) + TCP_TCPLEN(seg_list), + dbg_list_name)); + + next = seg_list; + seg_list = seg_list->next; + + clen = pbuf_clen(next->p); + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_receive: queuelen %"TCPWNDSIZE_F" ... ", + (tcpwnd_size_t)pcb->snd_queuelen)); + LWIP_ASSERT("pcb->snd_queuelen >= pbuf_clen(next->p)", (pcb->snd_queuelen >= clen)); + + pcb->snd_queuelen = (u16_t)(pcb->snd_queuelen - clen); + recv_acked = (tcpwnd_size_t)(recv_acked + next->len); + tcp_seg_free(next); + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("%"TCPWNDSIZE_F" (after freeing %s)\n", + (tcpwnd_size_t)pcb->snd_queuelen, + dbg_list_name)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_receive: valid queue length", + seg_list != NULL || dbg_other_seg_list != NULL); + } + } + return seg_list; +} + +/** + * Called by tcp_process. Checks if the given segment is an ACK for outstanding + * data, and if so frees the memory of the buffered data. Next, it places the + * segment on any of the receive queues (pcb->recved or pcb->ooseq). If the segment + * is buffered, the pbuf is referenced by pbuf_ref so that it will not be freed until + * it has been removed from the buffer. + * + * If the incoming segment constitutes an ACK for a segment that was used for RTT + * estimation, the RTT is estimated here as well. + * + * Called from tcp_process(). + */ +static void +tcp_receive(struct tcp_pcb *pcb) +{ + s16_t m; + u32_t right_wnd_edge; + int found_dupack = 0; + + LWIP_ASSERT("tcp_receive: invalid pcb", pcb != NULL); + LWIP_ASSERT("tcp_receive: wrong state", pcb->state >= ESTABLISHED); + + if (flags & TCP_ACK) { + right_wnd_edge = pcb->snd_wnd + pcb->snd_wl2; + + /* Update window. */ + if (TCP_SEQ_LT(pcb->snd_wl1, seqno) || + (pcb->snd_wl1 == seqno && TCP_SEQ_LT(pcb->snd_wl2, ackno)) || + (pcb->snd_wl2 == ackno && (u32_t)SND_WND_SCALE(pcb, tcphdr->wnd) > pcb->snd_wnd)) { + pcb->snd_wnd = SND_WND_SCALE(pcb, tcphdr->wnd); + /* keep track of the biggest window announced by the remote host to calculate + the maximum segment size */ + if (pcb->snd_wnd_max < pcb->snd_wnd) { + pcb->snd_wnd_max = pcb->snd_wnd; + } + pcb->snd_wl1 = seqno; + pcb->snd_wl2 = ackno; + LWIP_DEBUGF(TCP_WND_DEBUG, ("tcp_receive: window update %"TCPWNDSIZE_F"\n", pcb->snd_wnd)); +#if TCP_WND_DEBUG + } else { + if (pcb->snd_wnd != (tcpwnd_size_t)SND_WND_SCALE(pcb, tcphdr->wnd)) { + LWIP_DEBUGF(TCP_WND_DEBUG, + ("tcp_receive: no window update lastack %"U32_F" ackno %" + U32_F" wl1 %"U32_F" seqno %"U32_F" wl2 %"U32_F"\n", + pcb->lastack, ackno, pcb->snd_wl1, seqno, pcb->snd_wl2)); + } +#endif /* TCP_WND_DEBUG */ + } + + /* (From Stevens TCP/IP Illustrated Vol II, p970.) Its only a + * duplicate ack if: + * 1) It doesn't ACK new data + * 2) length of received packet is zero (i.e. no payload) + * 3) the advertised window hasn't changed + * 4) There is outstanding unacknowledged data (retransmission timer running) + * 5) The ACK is == biggest ACK sequence number so far seen (snd_una) + * + * If it passes all five, should process as a dupack: + * a) dupacks < 3: do nothing + * b) dupacks == 3: fast retransmit + * c) dupacks > 3: increase cwnd + * + * If it only passes 1-3, should reset dupack counter (and add to + * stats, which we don't do in lwIP) + * + * If it only passes 1, should reset dupack counter + * + */ + + /* Clause 1 */ + if (TCP_SEQ_LEQ(ackno, pcb->lastack)) { + /* Clause 2 */ + if (tcplen == 0) { + /* Clause 3 */ + if (pcb->snd_wl2 + pcb->snd_wnd == right_wnd_edge) { + /* Clause 4 */ + if (pcb->rtime >= 0) { + /* Clause 5 */ + if (pcb->lastack == ackno) { + found_dupack = 1; + if ((u8_t)(pcb->dupacks + 1) > pcb->dupacks) { + ++pcb->dupacks; + } + if (pcb->dupacks > 3) { + /* Inflate the congestion window */ + TCP_WND_INC(pcb->cwnd, pcb->mss); + } + if (pcb->dupacks >= 3) { + /* Do fast retransmit (checked via TF_INFR, not via dupacks count) */ + tcp_rexmit_fast(pcb); + } + } + } + } + } + /* If Clause (1) or more is true, but not a duplicate ack, reset + * count of consecutive duplicate acks */ + if (!found_dupack) { + pcb->dupacks = 0; + } + } else if (TCP_SEQ_BETWEEN(ackno, pcb->lastack + 1, pcb->snd_nxt)) { + /* We come here when the ACK acknowledges new data. */ + tcpwnd_size_t acked; + + /* Reset the "IN Fast Retransmit" flag, since we are no longer + in fast retransmit. Also reset the congestion window to the + slow start threshold. */ + if (pcb->flags & TF_INFR) { + tcp_clear_flags(pcb, TF_INFR); + pcb->cwnd = pcb->ssthresh; + pcb->bytes_acked = 0; + } + + /* Reset the number of retransmissions. */ + pcb->nrtx = 0; + + /* Reset the retransmission time-out. */ + pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); + + /* Record how much data this ACK acks */ + acked = (tcpwnd_size_t)(ackno - pcb->lastack); + + /* Reset the fast retransmit variables. */ + pcb->dupacks = 0; + pcb->lastack = ackno; + + /* Update the congestion control variables (cwnd and + ssthresh). */ + if (pcb->state >= ESTABLISHED) { + if (pcb->cwnd < pcb->ssthresh) { + tcpwnd_size_t increase; + /* limit to 1 SMSS segment during period following RTO */ + u8_t num_seg = (pcb->flags & TF_RTO) ? 1 : 2; + /* RFC 3465, section 2.2 Slow Start */ + increase = LWIP_MIN(acked, (tcpwnd_size_t)(num_seg * pcb->mss)); + TCP_WND_INC(pcb->cwnd, increase); + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: slow start cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd)); + } else { + /* RFC 3465, section 2.1 Congestion Avoidance */ + TCP_WND_INC(pcb->bytes_acked, acked); + if (pcb->bytes_acked >= pcb->cwnd) { + pcb->bytes_acked = (tcpwnd_size_t)(pcb->bytes_acked - pcb->cwnd); + TCP_WND_INC(pcb->cwnd, pcb->mss); + } + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_receive: congestion avoidance cwnd %"TCPWNDSIZE_F"\n", pcb->cwnd)); + } + } + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: ACK for %"U32_F", unacked->seqno %"U32_F":%"U32_F"\n", + ackno, + pcb->unacked != NULL ? + lwip_ntohl(pcb->unacked->tcphdr->seqno) : 0, + pcb->unacked != NULL ? + lwip_ntohl(pcb->unacked->tcphdr->seqno) + TCP_TCPLEN(pcb->unacked) : 0)); + + /* Remove segment from the unacknowledged list if the incoming + ACK acknowledges them. */ + pcb->unacked = tcp_free_acked_segments(pcb, pcb->unacked, "unacked", pcb->unsent); + /* We go through the ->unsent list to see if any of the segments + on the list are acknowledged by the ACK. This may seem + strange since an "unsent" segment shouldn't be acked. The + rationale is that lwIP puts all outstanding segments on the + ->unsent list after a retransmission, so these segments may + in fact have been sent once. */ + pcb->unsent = tcp_free_acked_segments(pcb, pcb->unsent, "unsent", pcb->unacked); + + /* If there's nothing left to acknowledge, stop the retransmit + timer, otherwise reset it to start again */ + if (pcb->unacked == NULL) { + pcb->rtime = -1; + } else { + pcb->rtime = 0; + } + + pcb->polltmr = 0; + +#if TCP_OVERSIZE + if (pcb->unsent == NULL) { + pcb->unsent_oversize = 0; + } +#endif /* TCP_OVERSIZE */ + +#if LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS + if (ip_current_is_v6()) { + /* Inform neighbor reachability of forward progress. */ + nd6_reachability_hint(ip6_current_src_addr()); + } +#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/ + + pcb->snd_buf = (tcpwnd_size_t)(pcb->snd_buf + recv_acked); + /* check if this ACK ends our retransmission of in-flight data */ + if (pcb->flags & TF_RTO) { + /* RTO is done if + 1) both queues are empty or + 2) unacked is empty and unsent head contains data not part of RTO or + 3) unacked head contains data not part of RTO */ + if (pcb->unacked == NULL) { + if ((pcb->unsent == NULL) || + (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unsent->tcphdr->seqno)))) { + tcp_clear_flags(pcb, TF_RTO); + } + } else if (TCP_SEQ_LEQ(pcb->rto_end, lwip_ntohl(pcb->unacked->tcphdr->seqno))) { + tcp_clear_flags(pcb, TF_RTO); + } + } + /* End of ACK for new data processing. */ + } else { + /* Out of sequence ACK, didn't really ack anything */ + tcp_send_empty_ack(pcb); + } + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: pcb->rttest %"U32_F" rtseq %"U32_F" ackno %"U32_F"\n", + pcb->rttest, pcb->rtseq, ackno)); + + /* RTT estimation calculations. This is done by checking if the + incoming segment acknowledges the segment we use to take a + round-trip time measurement. */ + if (pcb->rttest && TCP_SEQ_LT(pcb->rtseq, ackno)) { + /* diff between this shouldn't exceed 32K since this are tcp timer ticks + and a round-trip shouldn't be that long... */ + m = (s16_t)(tcp_ticks - pcb->rttest); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: experienced rtt %"U16_F" ticks (%"U16_F" msec).\n", + m, (u16_t)(m * TCP_SLOW_INTERVAL))); + + /* This is taken directly from VJs original code in his paper */ + m = (s16_t)(m - (pcb->sa >> 3)); + pcb->sa = (s16_t)(pcb->sa + m); + if (m < 0) { + m = (s16_t) - m; + } + m = (s16_t)(m - (pcb->sv >> 2)); + pcb->sv = (s16_t)(pcb->sv + m); + pcb->rto = (s16_t)((pcb->sa >> 3) + pcb->sv); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_receive: RTO %"U16_F" (%"U16_F" milliseconds)\n", + pcb->rto, (u16_t)(pcb->rto * TCP_SLOW_INTERVAL))); + + pcb->rttest = 0; + } + } + + /* If the incoming segment contains data, we must process it + further unless the pcb already received a FIN. + (RFC 793, chapter 3.9, "SEGMENT ARRIVES" in states CLOSE-WAIT, CLOSING, + LAST-ACK and TIME-WAIT: "Ignore the segment text.") */ + if ((tcplen > 0) && (pcb->state < CLOSE_WAIT)) { + /* This code basically does three things: + + +) If the incoming segment contains data that is the next + in-sequence data, this data is passed to the application. This + might involve trimming the first edge of the data. The rcv_nxt + variable and the advertised window are adjusted. + + +) If the incoming segment has data that is above the next + sequence number expected (->rcv_nxt), the segment is placed on + the ->ooseq queue. This is done by finding the appropriate + place in the ->ooseq queue (which is ordered by sequence + number) and trim the segment in both ends if needed. An + immediate ACK is sent to indicate that we received an + out-of-sequence segment. + + +) Finally, we check if the first segment on the ->ooseq queue + now is in sequence (i.e., if rcv_nxt >= ooseq->seqno). If + rcv_nxt > ooseq->seqno, we must trim the first edge of the + segment on ->ooseq before we adjust rcv_nxt. The data in the + segments that are now on sequence are chained onto the + incoming segment so that we only need to call the application + once. + */ + + /* First, we check if we must trim the first edge. We have to do + this if the sequence number of the incoming segment is less + than rcv_nxt, and the sequence number plus the length of the + segment is larger than rcv_nxt. */ + /* if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { + if (TCP_SEQ_LT(pcb->rcv_nxt, seqno + tcplen)) {*/ + if (TCP_SEQ_BETWEEN(pcb->rcv_nxt, seqno + 1, seqno + tcplen - 1)) { + /* Trimming the first edge is done by pushing the payload + pointer in the pbuf downwards. This is somewhat tricky since + we do not want to discard the full contents of the pbuf up to + the new starting point of the data since we have to keep the + TCP header which is present in the first pbuf in the chain. + + What is done is really quite a nasty hack: the first pbuf in + the pbuf chain is pointed to by inseg.p. Since we need to be + able to deallocate the whole pbuf, we cannot change this + inseg.p pointer to point to any of the later pbufs in the + chain. Instead, we point the ->payload pointer in the first + pbuf to data in one of the later pbufs. We also set the + inseg.data pointer to point to the right place. This way, the + ->p pointer will still point to the first pbuf, but the + ->p->payload pointer will point to data in another pbuf. + + After we are done with adjusting the pbuf pointers we must + adjust the ->data pointer in the seg and the segment + length.*/ + + struct pbuf *p = inseg.p; + u32_t off32 = pcb->rcv_nxt - seqno; + u16_t new_tot_len, off; + LWIP_ASSERT("inseg.p != NULL", inseg.p); + LWIP_ASSERT("insane offset!", (off32 < 0xffff)); + off = (u16_t)off32; + LWIP_ASSERT("pbuf too short!", (((s32_t)inseg.p->tot_len) >= off)); + inseg.len -= off; + new_tot_len = (u16_t)(inseg.p->tot_len - off); + while (p->len < off) { + off -= p->len; + /* all pbufs up to and including this one have len==0, so tot_len is equal */ + p->tot_len = new_tot_len; + p->len = 0; + p = p->next; + } + /* cannot fail... */ + pbuf_remove_header(p, off); + inseg.tcphdr->seqno = seqno = pcb->rcv_nxt; + } else { + if (TCP_SEQ_LT(seqno, pcb->rcv_nxt)) { + /* the whole segment is < rcv_nxt */ + /* must be a duplicate of a packet that has already been correctly handled */ + + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: duplicate seqno %"U32_F"\n", seqno)); + tcp_ack_now(pcb); + } + } + + /* The sequence number must be within the window (above rcv_nxt + and below rcv_nxt + rcv_wnd) in order to be further + processed. */ + if (TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, + pcb->rcv_nxt + pcb->rcv_wnd - 1)) { + if (pcb->rcv_nxt == seqno) { + /* The incoming segment is the next in sequence. We check if + we have to trim the end of the segment and update rcv_nxt + and pass the data to the application. */ + tcplen = TCP_TCPLEN(&inseg); + + if (tcplen > pcb->rcv_wnd) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(inseg.tcphdr, TCPH_FLAGS(inseg.tcphdr) & ~(unsigned int)TCP_FIN); + } + /* Adjust length of segment to fit in the window. */ + TCPWND_CHECK16(pcb->rcv_wnd); + inseg.len = (u16_t)pcb->rcv_wnd; + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + inseg.len -= 1; + } + pbuf_realloc(inseg.p, inseg.len); + tcplen = TCP_TCPLEN(&inseg); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); + } +#if TCP_QUEUE_OOSEQ + /* Received in-sequence data, adjust ooseq data if: + - FIN has been received or + - inseq overlaps with ooseq */ + if (pcb->ooseq != NULL) { + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: received in-order FIN, binning ooseq queue\n")); + /* Received in-order FIN means anything that was received + * out of order must now have been received in-order, so + * bin the ooseq queue */ + while (pcb->ooseq != NULL) { + struct tcp_seg *old_ooseq = pcb->ooseq; + pcb->ooseq = pcb->ooseq->next; + tcp_seg_free(old_ooseq); + } + } else { + struct tcp_seg *next = pcb->ooseq; + /* Remove all segments on ooseq that are covered by inseg already. + * FIN is copied from ooseq to inseg if present. */ + while (next && + TCP_SEQ_GEQ(seqno + tcplen, + next->tcphdr->seqno + next->len)) { + struct tcp_seg *tmp; + /* inseg cannot have FIN here (already processed above) */ + if ((TCPH_FLAGS(next->tcphdr) & TCP_FIN) != 0 && + (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) == 0) { + TCPH_SET_FLAG(inseg.tcphdr, TCP_FIN); + tcplen = TCP_TCPLEN(&inseg); + } + tmp = next; + next = next->next; + tcp_seg_free(tmp); + } + /* Now trim right side of inseg if it overlaps with the first + * segment on ooseq */ + if (next && + TCP_SEQ_GT(seqno + tcplen, + next->tcphdr->seqno)) { + /* inseg cannot have FIN here (already processed above) */ + inseg.len = (u16_t)(next->tcphdr->seqno - seqno); + if (TCPH_FLAGS(inseg.tcphdr) & TCP_SYN) { + inseg.len -= 1; + } + pbuf_realloc(inseg.p, inseg.len); + tcplen = TCP_TCPLEN(&inseg); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to ooseq queue\n", + (seqno + tcplen) == next->tcphdr->seqno); + } + pcb->ooseq = next; + } + } +#endif /* TCP_QUEUE_OOSEQ */ + + pcb->rcv_nxt = seqno + tcplen; + + /* Update the receiver's (our) window. */ + LWIP_ASSERT("tcp_receive: tcplen > rcv_wnd\n", pcb->rcv_wnd >= tcplen); + pcb->rcv_wnd -= tcplen; + + tcp_update_rcv_ann_wnd(pcb); + + /* If there is data in the segment, we make preparations to + pass this up to the application. The ->recv_data variable + is used for holding the pbuf that goes to the + application. The code for reassembling out-of-sequence data + chains its data on this pbuf as well. + + If the segment was a FIN, we set the TF_GOT_FIN flag that will + be used to indicate to the application that the remote side has + closed its end of the connection. */ + if (inseg.p->tot_len > 0) { + recv_data = inseg.p; + /* Since this pbuf now is the responsibility of the + application, we delete our reference to it so that we won't + (mistakingly) deallocate it. */ + inseg.p = NULL; + } + if (TCPH_FLAGS(inseg.tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: received FIN.\n")); + recv_flags |= TF_GOT_FIN; + } + +#if TCP_QUEUE_OOSEQ + /* We now check if we have segments on the ->ooseq queue that + are now in sequence. */ + while (pcb->ooseq != NULL && + pcb->ooseq->tcphdr->seqno == pcb->rcv_nxt) { + + struct tcp_seg *cseg = pcb->ooseq; + seqno = pcb->ooseq->tcphdr->seqno; + + pcb->rcv_nxt += TCP_TCPLEN(cseg); + LWIP_ASSERT("tcp_receive: ooseq tcplen > rcv_wnd\n", + pcb->rcv_wnd >= TCP_TCPLEN(cseg)); + pcb->rcv_wnd -= TCP_TCPLEN(cseg); + + tcp_update_rcv_ann_wnd(pcb); + + if (cseg->p->tot_len > 0) { + /* Chain this pbuf onto the pbuf that we will pass to + the application. */ + /* With window scaling, this can overflow recv_data->tot_len, but + that's not a problem since we explicitly fix that before passing + recv_data to the application. */ + if (recv_data) { + pbuf_cat(recv_data, cseg->p); + } else { + recv_data = cseg->p; + } + cseg->p = NULL; + } + if (TCPH_FLAGS(cseg->tcphdr) & TCP_FIN) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_receive: dequeued FIN.\n")); + recv_flags |= TF_GOT_FIN; + if (pcb->state == ESTABLISHED) { /* force passive close or we can move to active close */ + pcb->state = CLOSE_WAIT; + } + } + + pcb->ooseq = cseg->next; + tcp_seg_free(cseg); + } +#if LWIP_TCP_SACK_OUT + if (pcb->flags & TF_SACK) { + if (pcb->ooseq != NULL) { + /* Some segments may have been removed from ooseq, let's remove all SACKs that + describe anything before the new beginning of that list. */ + tcp_remove_sacks_lt(pcb, pcb->ooseq->tcphdr->seqno); + } else if (LWIP_TCP_SACK_VALID(pcb, 0)) { + /* ooseq has been cleared. Nothing to SACK */ + memset(pcb->rcv_sacks, 0, sizeof(pcb->rcv_sacks)); + } + } +#endif /* LWIP_TCP_SACK_OUT */ +#endif /* TCP_QUEUE_OOSEQ */ + + + /* Acknowledge the segment(s). */ + tcp_ack(pcb); + +#if LWIP_TCP_SACK_OUT + if (LWIP_TCP_SACK_VALID(pcb, 0)) { + /* Normally the ACK for the data received could be piggy-backed on a data packet, + but lwIP currently does not support including SACKs in data packets. So we force + it to respond with an empty ACK packet (only if there is at least one SACK to be sent). + NOTE: tcp_send_empty_ack() on success clears the ACK flags (set by tcp_ack()) */ + tcp_send_empty_ack(pcb); + } +#endif /* LWIP_TCP_SACK_OUT */ + +#if LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS + if (ip_current_is_v6()) { + /* Inform neighbor reachability of forward progress. */ + nd6_reachability_hint(ip6_current_src_addr()); + } +#endif /* LWIP_IPV6 && LWIP_ND6_TCP_REACHABILITY_HINTS*/ + + } else { + /* We get here if the incoming segment is out-of-sequence. */ + +#if TCP_QUEUE_OOSEQ + /* We queue the segment on the ->ooseq queue. */ + if (pcb->ooseq == NULL) { + pcb->ooseq = tcp_seg_copy(&inseg); +#if LWIP_TCP_SACK_OUT + if (pcb->flags & TF_SACK) { + /* All the SACKs should be invalid, so we can simply store the most recent one: */ + pcb->rcv_sacks[0].left = seqno; + pcb->rcv_sacks[0].right = seqno + inseg.len; + } +#endif /* LWIP_TCP_SACK_OUT */ + } else { + /* If the queue is not empty, we walk through the queue and + try to find a place where the sequence number of the + incoming segment is between the sequence numbers of the + previous and the next segment on the ->ooseq queue. That is + the place where we put the incoming segment. If needed, we + trim the second edges of the previous and the incoming + segment so that it will fit into the sequence. + + If the incoming segment has the same sequence number as a + segment on the ->ooseq queue, we discard the segment that + contains less data. */ + +#if LWIP_TCP_SACK_OUT + /* This is the left edge of the lowest possible SACK range. + It may start before the newly received segment (possibly adjusted below). */ + u32_t sackbeg = TCP_SEQ_LT(seqno, pcb->ooseq->tcphdr->seqno) ? seqno : pcb->ooseq->tcphdr->seqno; +#endif /* LWIP_TCP_SACK_OUT */ + struct tcp_seg *next, *prev = NULL; + for (next = pcb->ooseq; next != NULL; next = next->next) { + if (seqno == next->tcphdr->seqno) { + /* The sequence number of the incoming segment is the + same as the sequence number of the segment on + ->ooseq. We check the lengths to see which one to + discard. */ + if (inseg.len > next->len) { + /* The incoming segment is larger than the old + segment. We replace some segments with the new + one. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + if (prev != NULL) { + prev->next = cseg; + } else { + pcb->ooseq = cseg; + } + tcp_oos_insert_segment(cseg, next); + } + break; + } else { + /* Either the lengths are the same or the incoming + segment was smaller than the old one; in either + case, we ditch the incoming segment. */ + break; + } + } else { + if (prev == NULL) { + if (TCP_SEQ_LT(seqno, next->tcphdr->seqno)) { + /* The sequence number of the incoming segment is lower + than the sequence number of the first segment on the + queue. We put the incoming segment first on the + queue. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + pcb->ooseq = cseg; + tcp_oos_insert_segment(cseg, next); + } + break; + } + } else { + /*if (TCP_SEQ_LT(prev->tcphdr->seqno, seqno) && + TCP_SEQ_LT(seqno, next->tcphdr->seqno)) {*/ + if (TCP_SEQ_BETWEEN(seqno, prev->tcphdr->seqno + 1, next->tcphdr->seqno - 1)) { + /* The sequence number of the incoming segment is in + between the sequence numbers of the previous and + the next segment on ->ooseq. We trim trim the previous + segment, delete next segments that included in received segment + and trim received, if needed. */ + struct tcp_seg *cseg = tcp_seg_copy(&inseg); + if (cseg != NULL) { + if (TCP_SEQ_GT(prev->tcphdr->seqno + prev->len, seqno)) { + /* We need to trim the prev segment. */ + prev->len = (u16_t)(seqno - prev->tcphdr->seqno); + pbuf_realloc(prev->p, prev->len); + } + prev->next = cseg; + tcp_oos_insert_segment(cseg, next); + } + break; + } + } + +#if LWIP_TCP_SACK_OUT + /* The new segment goes after the 'next' one. If there is a "hole" in sequence numbers + between 'prev' and the beginning of 'next', we want to move sackbeg. */ + if (prev != NULL && prev->tcphdr->seqno + prev->len != next->tcphdr->seqno) { + sackbeg = next->tcphdr->seqno; + } +#endif /* LWIP_TCP_SACK_OUT */ + + /* We don't use 'prev' below, so let's set it to current 'next'. + This way even if we break the loop below, 'prev' will be pointing + at the segment right in front of the newly added one. */ + prev = next; + + /* If the "next" segment is the last segment on the + ooseq queue, we add the incoming segment to the end + of the list. */ + if (next->next == NULL && + TCP_SEQ_GT(seqno, next->tcphdr->seqno)) { + if (TCPH_FLAGS(next->tcphdr) & TCP_FIN) { + /* segment "next" already contains all data */ + break; + } + next->next = tcp_seg_copy(&inseg); + if (next->next != NULL) { + if (TCP_SEQ_GT(next->tcphdr->seqno + next->len, seqno)) { + /* We need to trim the last segment. */ + next->len = (u16_t)(seqno - next->tcphdr->seqno); + pbuf_realloc(next->p, next->len); + } + /* check if the remote side overruns our receive window */ + if (TCP_SEQ_GT((u32_t)tcplen + seqno, pcb->rcv_nxt + (u32_t)pcb->rcv_wnd)) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, + ("tcp_receive: other end overran receive window" + "seqno %"U32_F" len %"U16_F" right edge %"U32_F"\n", + seqno, tcplen, pcb->rcv_nxt + pcb->rcv_wnd)); + if (TCPH_FLAGS(next->next->tcphdr) & TCP_FIN) { + /* Must remove the FIN from the header as we're trimming + * that byte of sequence-space from the packet */ + TCPH_FLAGS_SET(next->next->tcphdr, TCPH_FLAGS(next->next->tcphdr) & ~TCP_FIN); + } + /* Adjust length of segment to fit in the window. */ + next->next->len = (u16_t)(pcb->rcv_nxt + pcb->rcv_wnd - seqno); + pbuf_realloc(next->next->p, next->next->len); + tcplen = TCP_TCPLEN(next->next); + LWIP_ASSERT("tcp_receive: segment not trimmed correctly to rcv_wnd\n", + (seqno + tcplen) == (pcb->rcv_nxt + pcb->rcv_wnd)); + } + } + break; + } + } + } + +#if LWIP_TCP_SACK_OUT + if (pcb->flags & TF_SACK) { + if (prev == NULL) { + /* The new segment is at the beginning. sackbeg should already be set properly. + We need to find the right edge. */ + next = pcb->ooseq; + } else if (prev->next != NULL) { + /* The new segment was added after 'prev'. If there is a "hole" between 'prev' and 'prev->next', + we need to move sackbeg. After that we should find the right edge. */ + next = prev->next; + if (prev->tcphdr->seqno + prev->len != next->tcphdr->seqno) { + sackbeg = next->tcphdr->seqno; + } + } else { + next = NULL; + } + if (next != NULL) { + u32_t sackend = next->tcphdr->seqno; + for ( ; (next != NULL) && (sackend == next->tcphdr->seqno); next = next->next) { + sackend += next->len; + } + tcp_add_sack(pcb, sackbeg, sackend); + } + } +#endif /* LWIP_TCP_SACK_OUT */ + } +#if defined(TCP_OOSEQ_BYTES_LIMIT) || defined(TCP_OOSEQ_PBUFS_LIMIT) + { + /* Check that the data on ooseq doesn't exceed one of the limits + and throw away everything above that limit. */ +#ifdef TCP_OOSEQ_BYTES_LIMIT + const u32_t ooseq_max_blen = TCP_OOSEQ_BYTES_LIMIT(pcb); + u32_t ooseq_blen = 0; +#endif +#ifdef TCP_OOSEQ_PBUFS_LIMIT + const u16_t ooseq_max_qlen = TCP_OOSEQ_PBUFS_LIMIT(pcb); + u16_t ooseq_qlen = 0; +#endif + struct tcp_seg *next, *prev = NULL; + for (next = pcb->ooseq; next != NULL; prev = next, next = next->next) { + struct pbuf *p = next->p; + int stop_here = 0; +#ifdef TCP_OOSEQ_BYTES_LIMIT + ooseq_blen += p->tot_len; + if (ooseq_blen > ooseq_max_blen) { + stop_here = 1; + } +#endif +#ifdef TCP_OOSEQ_PBUFS_LIMIT + ooseq_qlen += pbuf_clen(p); + if (ooseq_qlen > ooseq_max_qlen) { + stop_here = 1; + } +#endif + if (stop_here) { +#if LWIP_TCP_SACK_OUT + if (pcb->flags & TF_SACK) { + /* Let's remove all SACKs from next's seqno up. */ + tcp_remove_sacks_gt(pcb, next->tcphdr->seqno); + } +#endif /* LWIP_TCP_SACK_OUT */ + /* too much ooseq data, dump this and everything after it */ + tcp_segs_free(next); + if (prev == NULL) { + /* first ooseq segment is too much, dump the whole queue */ + pcb->ooseq = NULL; + } else { + /* just dump 'next' and everything after it */ + prev->next = NULL; + } + break; + } + } + } +#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */ +#endif /* TCP_QUEUE_OOSEQ */ + + /* We send the ACK packet after we've (potentially) dealt with SACKs, + so they can be included in the acknowledgment. */ + tcp_send_empty_ack(pcb); + } + } else { + /* The incoming segment is not within the window. */ + tcp_send_empty_ack(pcb); + } + } else { + /* Segments with length 0 is taken care of here. Segments that + fall out of the window are ACKed. */ + if (!TCP_SEQ_BETWEEN(seqno, pcb->rcv_nxt, pcb->rcv_nxt + pcb->rcv_wnd - 1)) { + tcp_ack_now(pcb); + } + } +} + +static u8_t +tcp_get_next_optbyte(void) +{ + u16_t optidx = tcp_optidx++; + if ((tcphdr_opt2 == NULL) || (optidx < tcphdr_opt1len)) { + u8_t *opts = (u8_t *)tcphdr + TCP_HLEN; + return opts[optidx]; + } else { + u8_t idx = (u8_t)(optidx - tcphdr_opt1len); + return tcphdr_opt2[idx]; + } +} + +/** + * Parses the options contained in the incoming segment. + * + * Called from tcp_listen_input() and tcp_process(). + * Currently, only the MSS option is supported! + * + * @param pcb the tcp_pcb for which a segment arrived + */ +static void +tcp_parseopt(struct tcp_pcb *pcb) +{ + u8_t data; + u16_t mss; +#if LWIP_TCP_TIMESTAMPS + u32_t tsval; +#endif + + LWIP_ASSERT("tcp_parseopt: invalid pcb", pcb != NULL); + + /* Parse the TCP MSS option, if present. */ + if (tcphdr_optlen != 0) { + for (tcp_optidx = 0; tcp_optidx < tcphdr_optlen; ) { + u8_t opt = tcp_get_next_optbyte(); + switch (opt) { + case LWIP_TCP_OPT_EOL: + /* End of options. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: EOL\n")); + return; + case LWIP_TCP_OPT_NOP: + /* NOP option. */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: NOP\n")); + break; + case LWIP_TCP_OPT_MSS: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: MSS\n")); + if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_MSS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_MSS) > tcphdr_optlen) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* An MSS option with the right option length. */ + mss = (u16_t)(tcp_get_next_optbyte() << 8); + mss |= tcp_get_next_optbyte(); + /* Limit the mss to the configured TCP_MSS and prevent division by zero */ + pcb->mss = ((mss > TCP_MSS) || (mss == 0)) ? TCP_MSS : mss; + break; +#if LWIP_WND_SCALE + case LWIP_TCP_OPT_WS: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: WND_SCALE\n")); + if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_WS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_WS) > tcphdr_optlen) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* An WND_SCALE option with the right option length. */ + data = tcp_get_next_optbyte(); + /* If syn was received with wnd scale option, + activate wnd scale opt, but only if this is not a retransmission */ + if ((flags & TCP_SYN) && !(pcb->flags & TF_WND_SCALE)) { + pcb->snd_scale = data; + if (pcb->snd_scale > 14U) { + pcb->snd_scale = 14U; + } + pcb->rcv_scale = TCP_RCV_SCALE; + tcp_set_flags(pcb, TF_WND_SCALE); + /* window scaling is enabled, we can use the full receive window */ + LWIP_ASSERT("window not at default value", pcb->rcv_wnd == TCPWND_MIN16(TCP_WND)); + LWIP_ASSERT("window not at default value", pcb->rcv_ann_wnd == TCPWND_MIN16(TCP_WND)); + pcb->rcv_wnd = pcb->rcv_ann_wnd = TCP_WND; + } + break; +#endif /* LWIP_WND_SCALE */ +#if LWIP_TCP_TIMESTAMPS + case LWIP_TCP_OPT_TS: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: TS\n")); + if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_TS || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_TS) > tcphdr_optlen) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* TCP timestamp option with valid length */ + tsval = tcp_get_next_optbyte(); + tsval |= (tcp_get_next_optbyte() << 8); + tsval |= (tcp_get_next_optbyte() << 16); + tsval |= (tcp_get_next_optbyte() << 24); + if (flags & TCP_SYN) { + pcb->ts_recent = lwip_ntohl(tsval); + /* Enable sending timestamps in every segment now that we know + the remote host supports it. */ + tcp_set_flags(pcb, TF_TIMESTAMP); + } else if (TCP_SEQ_BETWEEN(pcb->ts_lastacksent, seqno, seqno + tcplen)) { + pcb->ts_recent = lwip_ntohl(tsval); + } + /* Advance to next option (6 bytes already read) */ + tcp_optidx += LWIP_TCP_OPT_LEN_TS - 6; + break; +#endif /* LWIP_TCP_TIMESTAMPS */ +#if LWIP_TCP_SACK_OUT + case LWIP_TCP_OPT_SACK_PERM: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: SACK_PERM\n")); + if (tcp_get_next_optbyte() != LWIP_TCP_OPT_LEN_SACK_PERM || (tcp_optidx - 2 + LWIP_TCP_OPT_LEN_SACK_PERM) > tcphdr_optlen) { + /* Bad length */ + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + return; + } + /* TCP SACK_PERM option with valid length */ + if (flags & TCP_SYN) { + /* We only set it if we receive it in a SYN (or SYN+ACK) packet */ + tcp_set_flags(pcb, TF_SACK); + } + break; +#endif /* LWIP_TCP_SACK_OUT */ + default: + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: other\n")); + data = tcp_get_next_optbyte(); + if (data < 2) { + LWIP_DEBUGF(TCP_INPUT_DEBUG, ("tcp_parseopt: bad length\n")); + /* If the length field is zero, the options are malformed + and we don't process them further. */ + return; + } + /* All other options have a length field, so that we easily + can skip past them. */ + tcp_optidx += data - 2; + } + } + } +} + +void +tcp_trigger_input_pcb_close(void) +{ + recv_flags |= TF_CLOSED; +} + +#if LWIP_TCP_SACK_OUT +/** + * Called by tcp_receive() to add new SACK entry. + * + * The new SACK entry will be placed at the beginning of rcv_sacks[], as the newest one. + * Existing SACK entries will be "pushed back", to preserve their order. + * This is the behavior described in RFC 2018, section 4. + * + * @param pcb the tcp_pcb for which a segment arrived + * @param left the left side of the SACK (the first sequence number) + * @param right the right side of the SACK (the first sequence number past this SACK) + */ +static void +tcp_add_sack(struct tcp_pcb *pcb, u32_t left, u32_t right) +{ + u8_t i; + u8_t unused_idx; + + if ((pcb->flags & TF_SACK) == 0 || !TCP_SEQ_LT(left, right)) { + return; + } + + /* First, let's remove all SACKs that are no longer needed (because they overlap with the newest one), + while moving all other SACKs forward. + We run this loop for all entries, until we find the first invalid one. + There is no point checking after that. */ + for (i = unused_idx = 0; (i < LWIP_TCP_MAX_SACK_NUM) && LWIP_TCP_SACK_VALID(pcb, i); ++i) { + /* We only want to use SACK at [i] if it doesn't overlap with left:right range. + It does not overlap if its right side is before the newly added SACK, + or if its left side is after the newly added SACK. + NOTE: The equality should not really happen, but it doesn't hurt. */ + if (TCP_SEQ_LEQ(pcb->rcv_sacks[i].right, left) || TCP_SEQ_LEQ(right, pcb->rcv_sacks[i].left)) { + if (unused_idx != i) { + /* We don't need to copy if it's already in the right spot */ + pcb->rcv_sacks[unused_idx] = pcb->rcv_sacks[i]; + } + ++unused_idx; + } + } + + /* Now 'unused_idx' is the index of the first invalid SACK entry, + anywhere between 0 (no valid entries) and LWIP_TCP_MAX_SACK_NUM (all entries are valid). + We want to clear this and all following SACKs. + However, we will be adding another one in the front (and shifting everything else back). + So let's just iterate from the back, and set each entry to the one to the left if it's valid, + or to 0 if it is not. */ + for (i = LWIP_TCP_MAX_SACK_NUM - 1; i > 0; --i) { + /* [i] is the index we are setting, and the value should be at index [i-1], + or 0 if that index is unused (>= unused_idx). */ + if (i - 1 >= unused_idx) { + /* [i-1] is unused. Let's clear [i]. */ + pcb->rcv_sacks[i].left = pcb->rcv_sacks[i].right = 0; + } else { + pcb->rcv_sacks[i] = pcb->rcv_sacks[i - 1]; + } + } + + /* And now we can store the newest SACK */ + pcb->rcv_sacks[0].left = left; + pcb->rcv_sacks[0].right = right; +} + +/** + * Called to remove a range of SACKs. + * + * SACK entries will be removed or adjusted to not acknowledge any sequence + * numbers that are less than 'seq' passed. It not only invalidates entries, + * but also moves all entries that are still valid to the beginning. + * + * @param pcb the tcp_pcb to modify + * @param seq the lowest sequence number to keep in SACK entries + */ +static void +tcp_remove_sacks_lt(struct tcp_pcb *pcb, u32_t seq) +{ + u8_t i; + u8_t unused_idx; + + /* We run this loop for all entries, until we find the first invalid one. + There is no point checking after that. */ + for (i = unused_idx = 0; (i < LWIP_TCP_MAX_SACK_NUM) && LWIP_TCP_SACK_VALID(pcb, i); ++i) { + /* We only want to use SACK at index [i] if its right side is > 'seq'. */ + if (TCP_SEQ_GT(pcb->rcv_sacks[i].right, seq)) { + if (unused_idx != i) { + /* We only copy it if it's not in the right spot already. */ + pcb->rcv_sacks[unused_idx] = pcb->rcv_sacks[i]; + } + /* NOTE: It is possible that its left side is < 'seq', in which case we should adjust it. */ + if (TCP_SEQ_LT(pcb->rcv_sacks[unused_idx].left, seq)) { + pcb->rcv_sacks[unused_idx].left = seq; + } + ++unused_idx; + } + } + + /* We also need to invalidate everything from 'unused_idx' till the end */ + for (i = unused_idx; i < LWIP_TCP_MAX_SACK_NUM; ++i) { + pcb->rcv_sacks[i].left = pcb->rcv_sacks[i].right = 0; + } +} + +#if defined(TCP_OOSEQ_BYTES_LIMIT) || defined(TCP_OOSEQ_PBUFS_LIMIT) +/** + * Called to remove a range of SACKs. + * + * SACK entries will be removed or adjusted to not acknowledge any sequence + * numbers that are greater than (or equal to) 'seq' passed. It not only invalidates entries, + * but also moves all entries that are still valid to the beginning. + * + * @param pcb the tcp_pcb to modify + * @param seq the highest sequence number to keep in SACK entries + */ +static void +tcp_remove_sacks_gt(struct tcp_pcb *pcb, u32_t seq) +{ + u8_t i; + u8_t unused_idx; + + /* We run this loop for all entries, until we find the first invalid one. + There is no point checking after that. */ + for (i = unused_idx = 0; (i < LWIP_TCP_MAX_SACK_NUM) && LWIP_TCP_SACK_VALID(pcb, i); ++i) { + /* We only want to use SACK at index [i] if its left side is < 'seq'. */ + if (TCP_SEQ_LT(pcb->rcv_sacks[i].left, seq)) { + if (unused_idx != i) { + /* We only copy it if it's not in the right spot already. */ + pcb->rcv_sacks[unused_idx] = pcb->rcv_sacks[i]; + } + /* NOTE: It is possible that its right side is > 'seq', in which case we should adjust it. */ + if (TCP_SEQ_GT(pcb->rcv_sacks[unused_idx].right, seq)) { + pcb->rcv_sacks[unused_idx].right = seq; + } + ++unused_idx; + } + } + + /* We also need to invalidate everything from 'unused_idx' till the end */ + for (i = unused_idx; i < LWIP_TCP_MAX_SACK_NUM; ++i) { + pcb->rcv_sacks[i].left = pcb->rcv_sacks[i].right = 0; + } +} +#endif /* TCP_OOSEQ_BYTES_LIMIT || TCP_OOSEQ_PBUFS_LIMIT */ + +#endif /* LWIP_TCP_SACK_OUT */ + +#endif /* LWIP_TCP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/tcp_out.c b/Middlewares/Third_Party/LwIP/src/core/tcp_out.c new file mode 100644 index 0000000..724df10 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/tcp_out.c @@ -0,0 +1,2190 @@ +/** + * @file + * Transmission Control Protocol, outgoing traffic + * + * The output functions of TCP. + * + * There are two distinct ways for TCP segments to get sent: + * - queued data: these are segments transferring data or segments containing + * SYN or FIN (which both count as one sequence number). They are created as + * struct @ref pbuf together with a struct tcp_seg and enqueue to the + * unsent list of the pcb. They are sent by tcp_output: + * - @ref tcp_write : creates data segments + * - @ref tcp_split_unsent_seg : splits a data segment + * - @ref tcp_enqueue_flags : creates SYN-only or FIN-only segments + * - @ref tcp_output / tcp_output_segment : finalize the tcp header + * (e.g. sequence numbers, options, checksum) and output to IP + * - the various tcp_rexmit functions shuffle around segments between the + * unsent an unacked lists to retransmit them + * - tcp_create_segment and tcp_pbuf_prealloc allocate pbuf and + * segment for these functions + * - direct send: these segments don't contain data but control the connection + * behaviour. They are created as pbuf only and sent directly without + * enqueueing them: + * - @ref tcp_send_empty_ack sends an ACK-only segment + * - @ref tcp_rst sends a RST segment + * - @ref tcp_keepalive sends a keepalive segment + * - @ref tcp_zero_window_probe sends a window probe segment + * - tcp_output_alloc_header allocates a header-only pbuf for these functions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/priv/tcp_priv.h" +#include "lwip/def.h" +#include "lwip/mem.h" +#include "lwip/memp.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/inet_chksum.h" +#include "lwip/stats.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#if LWIP_TCP_TIMESTAMPS +#include "lwip/sys.h" +#endif + +#include + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +/* Allow to add custom TCP header options by defining this hook */ +#ifdef LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH +#define LWIP_TCP_OPT_LENGTH_SEGMENT(flags, pcb) LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH(pcb, LWIP_TCP_OPT_LENGTH(flags)) +#else +#define LWIP_TCP_OPT_LENGTH_SEGMENT(flags, pcb) LWIP_TCP_OPT_LENGTH(flags) +#endif + +/* Define some copy-macros for checksum-on-copy so that the code looks + nicer by preventing too many ifdef's. */ +#if TCP_CHECKSUM_ON_COPY +#define TCP_DATA_COPY(dst, src, len, seg) do { \ + tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), \ + len, &seg->chksum, &seg->chksum_swapped); \ + seg->flags |= TF_SEG_DATA_CHECKSUMMED; } while(0) +#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) \ + tcp_seg_add_chksum(LWIP_CHKSUM_COPY(dst, src, len), len, chksum, chksum_swapped); +#else /* TCP_CHECKSUM_ON_COPY*/ +#define TCP_DATA_COPY(dst, src, len, seg) MEMCPY(dst, src, len) +#define TCP_DATA_COPY2(dst, src, len, chksum, chksum_swapped) MEMCPY(dst, src, len) +#endif /* TCP_CHECKSUM_ON_COPY*/ + +/** Define this to 1 for an extra check that the output checksum is valid + * (usefule when the checksum is generated by the application, not the stack) */ +#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK +#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK 0 +#endif +/* Allow to override the failure of sanity check from warning to e.g. hard failure */ +#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK +#ifndef TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL +#define TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL(msg) LWIP_DEBUGF(TCP_DEBUG | LWIP_DBG_LEVEL_WARNING, msg) +#endif +#endif + +#if TCP_OVERSIZE +/** The size of segment pbufs created when TCP_OVERSIZE is enabled */ +#ifndef TCP_OVERSIZE_CALC_LENGTH +#define TCP_OVERSIZE_CALC_LENGTH(length) ((length) + TCP_OVERSIZE) +#endif +#endif + +/* Forward declarations.*/ +static err_t tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif); + +/* tcp_route: common code that returns a fixed bound netif or calls ip_route */ +static struct netif * +tcp_route(const struct tcp_pcb *pcb, const ip_addr_t *src, const ip_addr_t *dst) +{ + LWIP_UNUSED_ARG(src); /* in case IPv4-only and source-based routing is disabled */ + + if ((pcb != NULL) && (pcb->netif_idx != NETIF_NO_INDEX)) { + return netif_get_by_index(pcb->netif_idx); + } else { + return ip_route(src, dst); + } +} + +/** + * Create a TCP segment with prefilled header. + * + * Called by @ref tcp_write, @ref tcp_enqueue_flags and @ref tcp_split_unsent_seg + * + * @param pcb Protocol control block for the TCP connection. + * @param p pbuf that is used to hold the TCP header. + * @param hdrflags TCP flags for header. + * @param seqno TCP sequence number of this packet + * @param optflags options to include in TCP header + * @return a new tcp_seg pointing to p, or NULL. + * The TCP header is filled in except ackno and wnd. + * p is freed on failure. + */ +static struct tcp_seg * +tcp_create_segment(const struct tcp_pcb *pcb, struct pbuf *p, u8_t hdrflags, u32_t seqno, u8_t optflags) +{ + struct tcp_seg *seg; + u8_t optlen; + + LWIP_ASSERT("tcp_create_segment: invalid pcb", pcb != NULL); + LWIP_ASSERT("tcp_create_segment: invalid pbuf", p != NULL); + + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + + if ((seg = (struct tcp_seg *)memp_malloc(MEMP_TCP_SEG)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no memory.\n")); + pbuf_free(p); + return NULL; + } + seg->flags = optflags; + seg->next = NULL; + seg->p = p; + LWIP_ASSERT("p->tot_len >= optlen", p->tot_len >= optlen); + seg->len = p->tot_len - optlen; +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = 0; +#endif /* TCP_OVERSIZE_DBGCHECK */ +#if TCP_CHECKSUM_ON_COPY + seg->chksum = 0; + seg->chksum_swapped = 0; + /* check optflags */ + LWIP_ASSERT("invalid optflags passed: TF_SEG_DATA_CHECKSUMMED", + (optflags & TF_SEG_DATA_CHECKSUMMED) == 0); +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* build TCP header */ + if (pbuf_add_header(p, TCP_HLEN)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_create_segment: no room for TCP header in pbuf.\n")); + TCP_STATS_INC(tcp.err); + tcp_seg_free(seg); + return NULL; + } + seg->tcphdr = (struct tcp_hdr *)seg->p->payload; + seg->tcphdr->src = lwip_htons(pcb->local_port); + seg->tcphdr->dest = lwip_htons(pcb->remote_port); + seg->tcphdr->seqno = lwip_htonl(seqno); + /* ackno is set in tcp_output */ + TCPH_HDRLEN_FLAGS_SET(seg->tcphdr, (5 + optlen / 4), hdrflags); + /* wnd and chksum are set in tcp_output */ + seg->tcphdr->urgp = 0; + return seg; +} + +/** + * Allocate a PBUF_RAM pbuf, perhaps with extra space at the end. + * + * This function is like pbuf_alloc(layer, length, PBUF_RAM) except + * there may be extra bytes available at the end. + * + * Called by @ref tcp_write + * + * @param layer flag to define header size. + * @param length size of the pbuf's payload. + * @param max_length maximum usable size of payload+oversize. + * @param oversize pointer to a u16_t that will receive the number of usable tail bytes. + * @param pcb The TCP connection that will enqueue the pbuf. + * @param apiflags API flags given to tcp_write. + * @param first_seg true when this pbuf will be used in the first enqueued segment. + */ +#if TCP_OVERSIZE +static struct pbuf * +tcp_pbuf_prealloc(pbuf_layer layer, u16_t length, u16_t max_length, + u16_t *oversize, const struct tcp_pcb *pcb, u8_t apiflags, + u8_t first_seg) +{ + struct pbuf *p; + u16_t alloc = length; + + LWIP_ASSERT("tcp_pbuf_prealloc: invalid oversize", oversize != NULL); + LWIP_ASSERT("tcp_pbuf_prealloc: invalid pcb", pcb != NULL); + +#if LWIP_NETIF_TX_SINGLE_PBUF + LWIP_UNUSED_ARG(max_length); + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(apiflags); + LWIP_UNUSED_ARG(first_seg); + alloc = max_length; +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + if (length < max_length) { + /* Should we allocate an oversized pbuf, or just the minimum + * length required? If tcp_write is going to be called again + * before this segment is transmitted, we want the oversized + * buffer. If the segment will be transmitted immediately, we can + * save memory by allocating only length. We use a simple + * heuristic based on the following information: + * + * Did the user set TCP_WRITE_FLAG_MORE? + * + * Will the Nagle algorithm defer transmission of this segment? + */ + if ((apiflags & TCP_WRITE_FLAG_MORE) || + (!(pcb->flags & TF_NODELAY) && + (!first_seg || + pcb->unsent != NULL || + pcb->unacked != NULL))) { + alloc = LWIP_MIN(max_length, LWIP_MEM_ALIGN_SIZE(TCP_OVERSIZE_CALC_LENGTH(length))); + } + } +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + p = pbuf_alloc(layer, alloc, PBUF_RAM); + if (p == NULL) { + return NULL; + } + LWIP_ASSERT("need unchained pbuf", p->next == NULL); + *oversize = p->len - length; + /* trim p->len to the currently used size */ + p->len = p->tot_len = length; + return p; +} +#else /* TCP_OVERSIZE */ +#define tcp_pbuf_prealloc(layer, length, mx, os, pcb, api, fst) pbuf_alloc((layer), (length), PBUF_RAM) +#endif /* TCP_OVERSIZE */ + +#if TCP_CHECKSUM_ON_COPY +/** Add a checksum of newly added data to the segment. + * + * Called by tcp_write and tcp_split_unsent_seg. + */ +static void +tcp_seg_add_chksum(u16_t chksum, u16_t len, u16_t *seg_chksum, + u8_t *seg_chksum_swapped) +{ + u32_t helper; + /* add chksum to old chksum and fold to u16_t */ + helper = chksum + *seg_chksum; + chksum = FOLD_U32T(helper); + if ((len & 1) != 0) { + *seg_chksum_swapped = 1 - *seg_chksum_swapped; + chksum = SWAP_BYTES_IN_WORD(chksum); + } + *seg_chksum = chksum; +} +#endif /* TCP_CHECKSUM_ON_COPY */ + +/** Checks if tcp_write is allowed or not (checks state, snd_buf and snd_queuelen). + * + * @param pcb the tcp pcb to check for + * @param len length of data to send (checked agains snd_buf) + * @return ERR_OK if tcp_write is allowed to proceed, another err_t otherwise + */ +static err_t +tcp_write_checks(struct tcp_pcb *pcb, u16_t len) +{ + LWIP_ASSERT("tcp_write_checks: invalid pcb", pcb != NULL); + + /* connection is in invalid state for data transmission? */ + if ((pcb->state != ESTABLISHED) && + (pcb->state != CLOSE_WAIT) && + (pcb->state != SYN_SENT) && + (pcb->state != SYN_RCVD)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_STATE | LWIP_DBG_LEVEL_SEVERE, ("tcp_write() called in invalid state\n")); + return ERR_CONN; + } else if (len == 0) { + return ERR_OK; + } + + /* fail on too much data */ + if (len > pcb->snd_buf) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too much data (len=%"U16_F" > snd_buf=%"TCPWNDSIZE_F")\n", + len, pcb->snd_buf)); + tcp_set_flags(pcb, TF_NAGLEMEMERR); + return ERR_MEM; + } + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: queuelen: %"TCPWNDSIZE_F"\n", (tcpwnd_size_t)pcb->snd_queuelen)); + + /* If total number of pbufs on the unsent/unacked queues exceeds the + * configured maximum, return an error */ + /* check for configured max queuelen and possible overflow */ + if (pcb->snd_queuelen >= LWIP_MIN(TCP_SND_QUEUELEN, (TCP_SNDQUEUELEN_OVERFLOW + 1))) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SEVERE, ("tcp_write: too long queue %"U16_F" (max %"U16_F")\n", + pcb->snd_queuelen, (u16_t)TCP_SND_QUEUELEN)); + TCP_STATS_INC(tcp.memerr); + tcp_set_flags(pcb, TF_NAGLEMEMERR); + return ERR_MEM; + } + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_write: pbufs on queue => at least one queue non-empty", + pcb->unacked != NULL || pcb->unsent != NULL); + } else { + LWIP_ASSERT("tcp_write: no pbufs on queue => both queues empty", + pcb->unacked == NULL && pcb->unsent == NULL); + } + return ERR_OK; +} + +/** + * @ingroup tcp_raw + * Write data for sending (but does not send it immediately). + * + * It waits in the expectation of more data being sent soon (as + * it can send them more efficiently by combining them together). + * To prompt the system to send data now, call tcp_output() after + * calling tcp_write(). + * + * This function enqueues the data pointed to by the argument dataptr. The length of + * the data is passed as the len parameter. The apiflags can be one or more of: + * - TCP_WRITE_FLAG_COPY: indicates whether the new memory should be allocated + * for the data to be copied into. If this flag is not given, no new memory + * should be allocated and the data should only be referenced by pointer. This + * also means that the memory behind dataptr must not change until the data is + * ACKed by the remote host + * - TCP_WRITE_FLAG_MORE: indicates that more data follows. If this is omitted, + * the PSH flag is set in the last segment created by this call to tcp_write. + * If this flag is given, the PSH flag is not set. + * + * The tcp_write() function will fail and return ERR_MEM if the length + * of the data exceeds the current send buffer size or if the length of + * the queue of outgoing segment is larger than the upper limit defined + * in lwipopts.h. The number of bytes available in the output queue can + * be retrieved with the tcp_sndbuf() function. + * + * The proper way to use this function is to call the function with at + * most tcp_sndbuf() bytes of data. If the function returns ERR_MEM, + * the application should wait until some of the currently enqueued + * data has been successfully received by the other host and try again. + * + * @param pcb Protocol control block for the TCP connection to enqueue data for. + * @param arg Pointer to the data to be enqueued for sending. + * @param len Data length in bytes + * @param apiflags combination of following flags : + * - TCP_WRITE_FLAG_COPY (0x01) data will be copied into memory belonging to the stack + * - TCP_WRITE_FLAG_MORE (0x02) for TCP connection, PSH flag will not be set on last segment sent, + * @return ERR_OK if enqueued, another err_t on error + */ +err_t +tcp_write(struct tcp_pcb *pcb, const void *arg, u16_t len, u8_t apiflags) +{ + struct pbuf *concat_p = NULL; + struct tcp_seg *last_unsent = NULL, *seg = NULL, *prev_seg = NULL, *queue = NULL; + u16_t pos = 0; /* position in 'arg' data */ + u16_t queuelen; + u8_t optlen; + u8_t optflags = 0; +#if TCP_OVERSIZE + u16_t oversize = 0; + u16_t oversize_used = 0; +#if TCP_OVERSIZE_DBGCHECK + u16_t oversize_add = 0; +#endif /* TCP_OVERSIZE_DBGCHECK*/ +#endif /* TCP_OVERSIZE */ + u16_t extendlen = 0; +#if TCP_CHECKSUM_ON_COPY + u16_t concat_chksum = 0; + u8_t concat_chksum_swapped = 0; + u16_t concat_chksummed = 0; +#endif /* TCP_CHECKSUM_ON_COPY */ + err_t err; + u16_t mss_local; + + LWIP_ERROR("tcp_write: invalid pcb", pcb != NULL, return ERR_ARG); + + /* don't allocate segments bigger than half the maximum window we ever received */ + mss_local = LWIP_MIN(pcb->mss, TCPWND_MIN16(pcb->snd_wnd_max / 2)); + mss_local = mss_local ? mss_local : pcb->mss; + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_NETIF_TX_SINGLE_PBUF + /* Always copy to try to create single pbufs for TX */ + apiflags |= TCP_WRITE_FLAG_COPY; +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_write(pcb=%p, data=%p, len=%"U16_F", apiflags=%"U16_F")\n", + (void *)pcb, arg, len, (u16_t)apiflags)); + LWIP_ERROR("tcp_write: arg == NULL (programmer violates API)", + arg != NULL, return ERR_ARG;); + + err = tcp_write_checks(pcb, len); + if (err != ERR_OK) { + return err; + } + queuelen = pcb->snd_queuelen; + +#if LWIP_TCP_TIMESTAMPS + if ((pcb->flags & TF_TIMESTAMP)) { + /* Make sure the timestamp option is only included in data segments if we + agreed about it with the remote host. */ + optflags = TF_SEG_OPTS_TS; + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(TF_SEG_OPTS_TS, pcb); + /* ensure that segments can hold at least one data byte... */ + mss_local = LWIP_MAX(mss_local, LWIP_TCP_OPT_LEN_TS + 1); + } else +#endif /* LWIP_TCP_TIMESTAMPS */ + { + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + } + + + /* + * TCP segmentation is done in three phases with increasing complexity: + * + * 1. Copy data directly into an oversized pbuf. + * 2. Chain a new pbuf to the end of pcb->unsent. + * 3. Create new segments. + * + * We may run out of memory at any point. In that case we must + * return ERR_MEM and not change anything in pcb. Therefore, all + * changes are recorded in local variables and committed at the end + * of the function. Some pcb fields are maintained in local copies: + * + * queuelen = pcb->snd_queuelen + * oversize = pcb->unsent_oversize + * + * These variables are set consistently by the phases: + * + * seg points to the last segment tampered with. + * + * pos records progress as data is segmented. + */ + + /* Find the tail of the unsent queue. */ + if (pcb->unsent != NULL) { + u16_t space; + u16_t unsent_optlen; + + /* @todo: this could be sped up by keeping last_unsent in the pcb */ + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + last_unsent = last_unsent->next); + + /* Usable space at the end of the last unsent segment */ + unsent_optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(last_unsent->flags, pcb); + LWIP_ASSERT("mss_local is too small", mss_local >= last_unsent->len + unsent_optlen); + space = mss_local - (last_unsent->len + unsent_optlen); + + /* + * Phase 1: Copy data directly into an oversized pbuf. + * + * The number of bytes copied is recorded in the oversize_used + * variable. The actual copying is done at the bottom of the + * function. + */ +#if TCP_OVERSIZE +#if TCP_OVERSIZE_DBGCHECK + /* check that pcb->unsent_oversize matches last_unsent->oversize_left */ + LWIP_ASSERT("unsent_oversize mismatch (pcb vs. last_unsent)", + pcb->unsent_oversize == last_unsent->oversize_left); +#endif /* TCP_OVERSIZE_DBGCHECK */ + oversize = pcb->unsent_oversize; + if (oversize > 0) { + LWIP_ASSERT("inconsistent oversize vs. space", oversize <= space); + seg = last_unsent; + oversize_used = LWIP_MIN(space, LWIP_MIN(oversize, len)); + pos += oversize_used; + oversize -= oversize_used; + space -= oversize_used; + } + /* now we are either finished or oversize is zero */ + LWIP_ASSERT("inconsistent oversize vs. len", (oversize == 0) || (pos == len)); +#endif /* TCP_OVERSIZE */ + +#if !LWIP_NETIF_TX_SINGLE_PBUF + /* + * Phase 2: Chain a new pbuf to the end of pcb->unsent. + * + * As an exception when NOT copying the data, if the given data buffer + * directly follows the last unsent data buffer in memory, extend the last + * ROM pbuf reference to the buffer, thus saving a ROM pbuf allocation. + * + * We don't extend segments containing SYN/FIN flags or options + * (len==0). The new pbuf is kept in concat_p and pbuf_cat'ed at + * the end. + * + * This phase is skipped for LWIP_NETIF_TX_SINGLE_PBUF as we could only execute + * it after rexmit puts a segment from unacked to unsent and at this point, + * oversize info is lost. + */ + if ((pos < len) && (space > 0) && (last_unsent->len > 0)) { + u16_t seglen = LWIP_MIN(space, len - pos); + seg = last_unsent; + + /* Create a pbuf with a copy or reference to seglen bytes. We + * can use PBUF_RAW here since the data appears in the middle of + * a segment. A header will never be prepended. */ + if (apiflags & TCP_WRITE_FLAG_COPY) { + /* Data is copied */ + if ((concat_p = tcp_pbuf_prealloc(PBUF_RAW, seglen, space, &oversize, pcb, apiflags, 1)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", + seglen)); + goto memerr; + } +#if TCP_OVERSIZE_DBGCHECK + oversize_add = oversize; +#endif /* TCP_OVERSIZE_DBGCHECK */ + TCP_DATA_COPY2(concat_p->payload, (const u8_t *)arg + pos, seglen, &concat_chksum, &concat_chksum_swapped); +#if TCP_CHECKSUM_ON_COPY + concat_chksummed += seglen; +#endif /* TCP_CHECKSUM_ON_COPY */ + queuelen += pbuf_clen(concat_p); + } else { + /* Data is not copied */ + /* If the last unsent pbuf is of type PBUF_ROM, try to extend it. */ + struct pbuf *p; + for (p = last_unsent->p; p->next != NULL; p = p->next); + if (((p->type_internal & (PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_DATA_VOLATILE)) == 0) && + (const u8_t *)p->payload + p->len == (const u8_t *)arg) { + LWIP_ASSERT("tcp_write: ROM pbufs cannot be oversized", pos == 0); + extendlen = seglen; + } else { + if ((concat_p = pbuf_alloc(PBUF_RAW, seglen, PBUF_ROM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_write: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } + /* reference the non-volatile payload data */ + ((struct pbuf_rom *)concat_p)->payload = (const u8_t *)arg + pos; + queuelen += pbuf_clen(concat_p); + } +#if TCP_CHECKSUM_ON_COPY + /* calculate the checksum of nocopy-data */ + tcp_seg_add_chksum(~inet_chksum((const u8_t *)arg + pos, seglen), seglen, + &concat_chksum, &concat_chksum_swapped); + concat_chksummed += seglen; +#endif /* TCP_CHECKSUM_ON_COPY */ + } + + pos += seglen; + } +#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ + } else { +#if TCP_OVERSIZE + LWIP_ASSERT("unsent_oversize mismatch (pcb->unsent is NULL)", + pcb->unsent_oversize == 0); +#endif /* TCP_OVERSIZE */ + } + + /* + * Phase 3: Create new segments. + * + * The new segments are chained together in the local 'queue' + * variable, ready to be appended to pcb->unsent. + */ + while (pos < len) { + struct pbuf *p; + u16_t left = len - pos; + u16_t max_len = mss_local - optlen; + u16_t seglen = LWIP_MIN(left, max_len); +#if TCP_CHECKSUM_ON_COPY + u16_t chksum = 0; + u8_t chksum_swapped = 0; +#endif /* TCP_CHECKSUM_ON_COPY */ + + if (apiflags & TCP_WRITE_FLAG_COPY) { + /* If copy is set, memory should be allocated and data copied + * into pbuf */ + if ((p = tcp_pbuf_prealloc(PBUF_TRANSPORT, seglen + optlen, mss_local, &oversize, pcb, apiflags, queue == NULL)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write : could not allocate memory for pbuf copy size %"U16_F"\n", seglen)); + goto memerr; + } + LWIP_ASSERT("tcp_write: check that first pbuf can hold the complete seglen", + (p->len >= seglen)); + TCP_DATA_COPY2((char *)p->payload + optlen, (const u8_t *)arg + pos, seglen, &chksum, &chksum_swapped); + } else { + /* Copy is not set: First allocate a pbuf for holding the data. + * Since the referenced data is available at least until it is + * sent out on the link (as it has to be ACKed by the remote + * party) we can safely use PBUF_ROM instead of PBUF_REF here. + */ + struct pbuf *p2; +#if TCP_OVERSIZE + LWIP_ASSERT("oversize == 0", oversize == 0); +#endif /* TCP_OVERSIZE */ + if ((p2 = pbuf_alloc(PBUF_TRANSPORT, seglen, PBUF_ROM)) == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for zero-copy pbuf\n")); + goto memerr; + } +#if TCP_CHECKSUM_ON_COPY + /* calculate the checksum of nocopy-data */ + chksum = ~inet_chksum((const u8_t *)arg + pos, seglen); + if (seglen & 1) { + chksum_swapped = 1; + chksum = SWAP_BYTES_IN_WORD(chksum); + } +#endif /* TCP_CHECKSUM_ON_COPY */ + /* reference the non-volatile payload data */ + ((struct pbuf_rom *)p2)->payload = (const u8_t *)arg + pos; + + /* Second, allocate a pbuf for the headers. */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + /* If allocation fails, we have to deallocate the data pbuf as + * well. */ + pbuf_free(p2); + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: could not allocate memory for header pbuf\n")); + goto memerr; + } + /* Concatenate the headers and data pbufs together. */ + pbuf_cat(p/*header*/, p2/*data*/); + } + + queuelen += pbuf_clen(p); + + /* Now that there are more segments queued, we check again if the + * length of the queue exceeds the configured maximum or + * overflows. */ + if (queuelen > LWIP_MIN(TCP_SND_QUEUELEN, TCP_SNDQUEUELEN_OVERFLOW)) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_write: queue too long %"U16_F" (%d)\n", + queuelen, (int)TCP_SND_QUEUELEN)); + pbuf_free(p); + goto memerr; + } + + if ((seg = tcp_create_segment(pcb, p, 0, pcb->snd_lbb + pos, optflags)) == NULL) { + goto memerr; + } +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = oversize; +#endif /* TCP_OVERSIZE_DBGCHECK */ +#if TCP_CHECKSUM_ON_COPY + seg->chksum = chksum; + seg->chksum_swapped = chksum_swapped; + seg->flags |= TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* first segment of to-be-queued data? */ + if (queue == NULL) { + queue = seg; + } else { + /* Attach the segment to the end of the queued segments */ + LWIP_ASSERT("prev_seg != NULL", prev_seg != NULL); + prev_seg->next = seg; + } + /* remember last segment of to-be-queued data for next iteration */ + prev_seg = seg; + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, ("tcp_write: queueing %"U32_F":%"U32_F"\n", + lwip_ntohl(seg->tcphdr->seqno), + lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg))); + + pos += seglen; + } + + /* + * All three segmentation phases were successful. We can commit the + * transaction. + */ +#if TCP_OVERSIZE_DBGCHECK + if ((last_unsent != NULL) && (oversize_add != 0)) { + last_unsent->oversize_left += oversize_add; + } +#endif /* TCP_OVERSIZE_DBGCHECK */ + + /* + * Phase 1: If data has been added to the preallocated tail of + * last_unsent, we update the length fields of the pbuf chain. + */ +#if TCP_OVERSIZE + if (oversize_used > 0) { + struct pbuf *p; + /* Bump tot_len of whole chain, len of tail */ + for (p = last_unsent->p; p; p = p->next) { + p->tot_len += oversize_used; + if (p->next == NULL) { + TCP_DATA_COPY((char *)p->payload + p->len, arg, oversize_used, last_unsent); + p->len += oversize_used; + } + } + last_unsent->len += oversize_used; +#if TCP_OVERSIZE_DBGCHECK + LWIP_ASSERT("last_unsent->oversize_left >= oversize_used", + last_unsent->oversize_left >= oversize_used); + last_unsent->oversize_left -= oversize_used; +#endif /* TCP_OVERSIZE_DBGCHECK */ + } + pcb->unsent_oversize = oversize; +#endif /* TCP_OVERSIZE */ + + /* + * Phase 2: concat_p can be concatenated onto last_unsent->p, unless we + * determined that the last ROM pbuf can be extended to include the new data. + */ + if (concat_p != NULL) { + LWIP_ASSERT("tcp_write: cannot concatenate when pcb->unsent is empty", + (last_unsent != NULL)); + pbuf_cat(last_unsent->p, concat_p); + last_unsent->len += concat_p->tot_len; + } else if (extendlen > 0) { + struct pbuf *p; + LWIP_ASSERT("tcp_write: extension of reference requires reference", + last_unsent != NULL && last_unsent->p != NULL); + for (p = last_unsent->p; p->next != NULL; p = p->next) { + p->tot_len += extendlen; + } + p->tot_len += extendlen; + p->len += extendlen; + last_unsent->len += extendlen; + } + +#if TCP_CHECKSUM_ON_COPY + if (concat_chksummed) { + LWIP_ASSERT("tcp_write: concat checksum needs concatenated data", + concat_p != NULL || extendlen > 0); + /*if concat checksumm swapped - swap it back */ + if (concat_chksum_swapped) { + concat_chksum = SWAP_BYTES_IN_WORD(concat_chksum); + } + tcp_seg_add_chksum(concat_chksum, concat_chksummed, &last_unsent->chksum, + &last_unsent->chksum_swapped); + last_unsent->flags |= TF_SEG_DATA_CHECKSUMMED; + } +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* + * Phase 3: Append queue to pcb->unsent. Queue may be NULL, but that + * is harmless + */ + if (last_unsent == NULL) { + pcb->unsent = queue; + } else { + last_unsent->next = queue; + } + + /* + * Finally update the pcb state. + */ + pcb->snd_lbb += len; + pcb->snd_buf -= len; + pcb->snd_queuelen = queuelen; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_write: %"S16_F" (after enqueued)\n", + pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_write: valid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + /* Set the PSH flag in the last segment that we enqueued. */ + if (seg != NULL && seg->tcphdr != NULL && ((apiflags & TCP_WRITE_FLAG_MORE) == 0)) { + TCPH_SET_FLAG(seg->tcphdr, TCP_PSH); + } + + return ERR_OK; +memerr: + tcp_set_flags(pcb, TF_NAGLEMEMERR); + TCP_STATS_INC(tcp.memerr); + + if (concat_p != NULL) { + pbuf_free(concat_p); + } + if (queue != NULL) { + tcp_segs_free(queue); + } + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_write: valid queue length", pcb->unacked != NULL || + pcb->unsent != NULL); + } + LWIP_DEBUGF(TCP_QLEN_DEBUG | LWIP_DBG_STATE, ("tcp_write: %"S16_F" (with mem err)\n", pcb->snd_queuelen)); + return ERR_MEM; +} + +/** + * Split segment on the head of the unsent queue. If return is not + * ERR_OK, existing head remains intact + * + * The split is accomplished by creating a new TCP segment and pbuf + * which holds the remainder payload after the split. The original + * pbuf is trimmed to new length. This allows splitting of read-only + * pbufs + * + * @param pcb the tcp_pcb for which to split the unsent head + * @param split the amount of payload to remain in the head + */ +err_t +tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split) +{ + struct tcp_seg *seg = NULL, *useg = NULL; + struct pbuf *p = NULL; + u8_t optlen; + u8_t optflags; + u8_t split_flags; + u8_t remainder_flags; + u16_t remainder; + u16_t offset; +#if TCP_CHECKSUM_ON_COPY + u16_t chksum = 0; + u8_t chksum_swapped = 0; + struct pbuf *q; +#endif /* TCP_CHECKSUM_ON_COPY */ + + LWIP_ASSERT("tcp_split_unsent_seg: invalid pcb", pcb != NULL); + + useg = pcb->unsent; + if (useg == NULL) { + return ERR_MEM; + } + + if (split == 0) { + LWIP_ASSERT("Can't split segment into length 0", 0); + return ERR_VAL; + } + + if (useg->len <= split) { + return ERR_OK; + } + + LWIP_ASSERT("split <= mss", split <= pcb->mss); + LWIP_ASSERT("useg->len > 0", useg->len > 0); + + /* We should check that we don't exceed TCP_SND_QUEUELEN but we need + * to split this packet so we may actually exceed the max value by + * one! + */ + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue: split_unsent_seg: %u\n", (unsigned int)pcb->snd_queuelen)); + + optflags = useg->flags; +#if TCP_CHECKSUM_ON_COPY + /* Remove since checksum is not stored until after tcp_create_segment() */ + optflags &= ~TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + optlen = LWIP_TCP_OPT_LENGTH(optflags); + remainder = useg->len - split; + + /* Create new pbuf for the remainder of the split */ + p = pbuf_alloc(PBUF_TRANSPORT, remainder + optlen, PBUF_RAM); + if (p == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_split_unsent_seg: could not allocate memory for pbuf remainder %u\n", remainder)); + goto memerr; + } + + /* Offset into the original pbuf is past TCP/IP headers, options, and split amount */ + offset = useg->p->tot_len - useg->len + split; + /* Copy remainder into new pbuf, headers and options will not be filled out */ + if (pbuf_copy_partial(useg->p, (u8_t *)p->payload + optlen, remainder, offset ) != remainder) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_split_unsent_seg: could not copy pbuf remainder %u\n", remainder)); + goto memerr; + } +#if TCP_CHECKSUM_ON_COPY + /* calculate the checksum on remainder data */ + tcp_seg_add_chksum(~inet_chksum((const u8_t *)p->payload + optlen, remainder), remainder, + &chksum, &chksum_swapped); +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Options are created when calling tcp_output() */ + + /* Migrate flags from original segment */ + split_flags = TCPH_FLAGS(useg->tcphdr); + remainder_flags = 0; /* ACK added in tcp_output() */ + + if (split_flags & TCP_PSH) { + split_flags &= ~TCP_PSH; + remainder_flags |= TCP_PSH; + } + if (split_flags & TCP_FIN) { + split_flags &= ~TCP_FIN; + remainder_flags |= TCP_FIN; + } + /* SYN should be left on split, RST should not be present with data */ + + seg = tcp_create_segment(pcb, p, remainder_flags, lwip_ntohl(useg->tcphdr->seqno) + split, optflags); + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("tcp_split_unsent_seg: could not create new TCP segment\n")); + goto memerr; + } + +#if TCP_CHECKSUM_ON_COPY + seg->chksum = chksum; + seg->chksum_swapped = chksum_swapped; + seg->flags |= TF_SEG_DATA_CHECKSUMMED; +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Remove this segment from the queue since trimming it may free pbufs */ + pcb->snd_queuelen -= pbuf_clen(useg->p); + + /* Trim the original pbuf into our split size. At this point our remainder segment must be setup + successfully because we are modifying the original segment */ + pbuf_realloc(useg->p, useg->p->tot_len - remainder); + useg->len -= remainder; + TCPH_SET_FLAG(useg->tcphdr, split_flags); +#if TCP_OVERSIZE_DBGCHECK + /* By trimming, realloc may have actually shrunk the pbuf, so clear oversize_left */ + useg->oversize_left = 0; +#endif /* TCP_OVERSIZE_DBGCHECK */ + + /* Add back to the queue with new trimmed pbuf */ + pcb->snd_queuelen += pbuf_clen(useg->p); + +#if TCP_CHECKSUM_ON_COPY + /* The checksum on the split segment is now incorrect. We need to re-run it over the split */ + useg->chksum = 0; + useg->chksum_swapped = 0; + q = useg->p; + offset = q->tot_len - useg->len; /* Offset due to exposed headers */ + + /* Advance to the pbuf where the offset ends */ + while (q != NULL && offset > q->len) { + offset -= q->len; + q = q->next; + } + LWIP_ASSERT("Found start of payload pbuf", q != NULL); + /* Checksum the first payload pbuf accounting for offset, then other pbufs are all payload */ + for (; q != NULL; offset = 0, q = q->next) { + tcp_seg_add_chksum(~inet_chksum((const u8_t *)q->payload + offset, q->len - offset), q->len - offset, + &useg->chksum, &useg->chksum_swapped); + } +#endif /* TCP_CHECKSUM_ON_COPY */ + + /* Update number of segments on the queues. Note that length now may + * exceed TCP_SND_QUEUELEN! We don't have to touch pcb->snd_buf + * because the total amount of data is constant when packet is split */ + pcb->snd_queuelen += pbuf_clen(seg->p); + + /* Finally insert remainder into queue after split (which stays head) */ + seg->next = useg->next; + useg->next = seg; + +#if TCP_OVERSIZE + /* If remainder is last segment on the unsent, ensure we clear the oversize amount + * because the remainder is always sized to the exact remaining amount */ + if (seg->next == NULL) { + pcb->unsent_oversize = 0; + } +#endif /* TCP_OVERSIZE */ + + return ERR_OK; +memerr: + TCP_STATS_INC(tcp.memerr); + + LWIP_ASSERT("seg == NULL", seg == NULL); + if (p != NULL) { + pbuf_free(p); + } + + return ERR_MEM; +} + +/** + * Called by tcp_close() to send a segment including FIN flag but not data. + * This FIN may be added to an existing segment or a new, otherwise empty + * segment is enqueued. + * + * @param pcb the tcp_pcb over which to send a segment + * @return ERR_OK if sent, another err_t otherwise + */ +err_t +tcp_send_fin(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_send_fin: invalid pcb", pcb != NULL); + + /* first, try to add the fin to the last unsent segment */ + if (pcb->unsent != NULL) { + struct tcp_seg *last_unsent; + for (last_unsent = pcb->unsent; last_unsent->next != NULL; + last_unsent = last_unsent->next); + + if ((TCPH_FLAGS(last_unsent->tcphdr) & (TCP_SYN | TCP_FIN | TCP_RST)) == 0) { + /* no SYN/FIN/RST flag in the header, we can add the FIN flag */ + TCPH_SET_FLAG(last_unsent->tcphdr, TCP_FIN); + tcp_set_flags(pcb, TF_FIN); + return ERR_OK; + } + } + /* no data, no length, flags, copy=1, no optdata */ + return tcp_enqueue_flags(pcb, TCP_FIN); +} + +/** + * Enqueue SYN or FIN for transmission. + * + * Called by @ref tcp_connect, tcp_listen_input, and @ref tcp_close + * (via @ref tcp_send_fin) + * + * @param pcb Protocol control block for the TCP connection. + * @param flags TCP header flags to set in the outgoing segment. + */ +err_t +tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags) +{ + struct pbuf *p; + struct tcp_seg *seg; + u8_t optflags = 0; + u8_t optlen = 0; + + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: queuelen: %"U16_F"\n", (u16_t)pcb->snd_queuelen)); + + LWIP_ASSERT("tcp_enqueue_flags: need either TCP_SYN or TCP_FIN in flags (programmer violates API)", + (flags & (TCP_SYN | TCP_FIN)) != 0); + LWIP_ASSERT("tcp_enqueue_flags: invalid pcb", pcb != NULL); + + /* No need to check pcb->snd_queuelen if only SYN or FIN are allowed! */ + + /* Get options for this segment. This is a special case since this is the + only place where a SYN can be sent. */ + if (flags & TCP_SYN) { + optflags = TF_SEG_OPTS_MSS; +#if LWIP_WND_SCALE + if ((pcb->state != SYN_RCVD) || (pcb->flags & TF_WND_SCALE)) { + /* In a (sent in state SYN_RCVD), the window scale option may only + be sent if we received a window scale option from the remote host. */ + optflags |= TF_SEG_OPTS_WND_SCALE; + } +#endif /* LWIP_WND_SCALE */ +#if LWIP_TCP_SACK_OUT + if ((pcb->state != SYN_RCVD) || (pcb->flags & TF_SACK)) { + /* In a (sent in state SYN_RCVD), the SACK_PERM option may only + be sent if we received a SACK_PERM option from the remote host. */ + optflags |= TF_SEG_OPTS_SACK_PERM; + } +#endif /* LWIP_TCP_SACK_OUT */ + } +#if LWIP_TCP_TIMESTAMPS + if ((pcb->flags & TF_TIMESTAMP) || ((flags & TCP_SYN) && (pcb->state != SYN_RCVD))) { + /* Make sure the timestamp option is only included in data segments if we + agreed about it with the remote host (and in active open SYN segments). */ + optflags |= TF_SEG_OPTS_TS; + } +#endif /* LWIP_TCP_TIMESTAMPS */ + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + + /* Allocate pbuf with room for TCP header + options */ + if ((p = pbuf_alloc(PBUF_TRANSPORT, optlen, PBUF_RAM)) == NULL) { + tcp_set_flags(pcb, TF_NAGLEMEMERR); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + LWIP_ASSERT("tcp_enqueue_flags: check that first pbuf can hold optlen", + (p->len >= optlen)); + + /* Allocate memory for tcp_seg, and fill in fields. */ + if ((seg = tcp_create_segment(pcb, p, flags, pcb->snd_lbb, optflags)) == NULL) { + tcp_set_flags(pcb, TF_NAGLEMEMERR); + TCP_STATS_INC(tcp.memerr); + return ERR_MEM; + } + LWIP_ASSERT("seg->tcphdr not aligned", ((mem_ptr_t)seg->tcphdr % LWIP_MIN(MEM_ALIGNMENT, 4)) == 0); + LWIP_ASSERT("tcp_enqueue_flags: invalid segment length", seg->len == 0); + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG | LWIP_DBG_TRACE, + ("tcp_enqueue_flags: queueing %"U32_F":%"U32_F" (0x%"X16_F")\n", + lwip_ntohl(seg->tcphdr->seqno), + lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg), + (u16_t)flags)); + + /* Now append seg to pcb->unsent queue */ + if (pcb->unsent == NULL) { + pcb->unsent = seg; + } else { + struct tcp_seg *useg; + for (useg = pcb->unsent; useg->next != NULL; useg = useg->next); + useg->next = seg; + } +#if TCP_OVERSIZE + /* The new unsent tail has no space */ + pcb->unsent_oversize = 0; +#endif /* TCP_OVERSIZE */ + + /* SYN and FIN bump the sequence number */ + if ((flags & TCP_SYN) || (flags & TCP_FIN)) { + pcb->snd_lbb++; + /* optlen does not influence snd_buf */ + } + if (flags & TCP_FIN) { + tcp_set_flags(pcb, TF_FIN); + } + + /* update number of segments on the queues */ + pcb->snd_queuelen += pbuf_clen(seg->p); + LWIP_DEBUGF(TCP_QLEN_DEBUG, ("tcp_enqueue_flags: %"S16_F" (after enqueued)\n", pcb->snd_queuelen)); + if (pcb->snd_queuelen != 0) { + LWIP_ASSERT("tcp_enqueue_flags: invalid queue length", + pcb->unacked != NULL || pcb->unsent != NULL); + } + + return ERR_OK; +} + +#if LWIP_TCP_TIMESTAMPS +/* Build a timestamp option (12 bytes long) at the specified options pointer) + * + * @param pcb tcp_pcb + * @param opts option pointer where to store the timestamp option + */ +static void +tcp_build_timestamp_option(const struct tcp_pcb *pcb, u32_t *opts) +{ + LWIP_ASSERT("tcp_build_timestamp_option: invalid pcb", pcb != NULL); + + /* Pad with two NOP options to make everything nicely aligned */ + opts[0] = PP_HTONL(0x0101080A); + opts[1] = lwip_htonl(sys_now()); + opts[2] = lwip_htonl(pcb->ts_recent); +} +#endif + +#if LWIP_TCP_SACK_OUT +/** + * Calculates the number of SACK entries that should be generated. + * It takes into account whether TF_SACK flag is set, + * the number of SACK entries in tcp_pcb that are valid, + * as well as the available options size. + * + * @param pcb tcp_pcb + * @param optlen the length of other TCP options (in bytes) + * @return the number of SACK ranges that can be used + */ +static u8_t +tcp_get_num_sacks(const struct tcp_pcb *pcb, u8_t optlen) +{ + u8_t num_sacks = 0; + + LWIP_ASSERT("tcp_get_num_sacks: invalid pcb", pcb != NULL); + + if (pcb->flags & TF_SACK) { + u8_t i; + + /* The first SACK takes up 12 bytes (it includes SACK header and two NOP options), + each additional one - 8 bytes. */ + optlen += 12; + + /* Max options size = 40, number of SACK array entries = LWIP_TCP_MAX_SACK_NUM */ + for (i = 0; (i < LWIP_TCP_MAX_SACK_NUM) && (optlen <= TCP_MAX_OPTION_BYTES) && + LWIP_TCP_SACK_VALID(pcb, i); ++i) { + ++num_sacks; + optlen += 8; + } + } + + return num_sacks; +} + +/** Build a SACK option (12 or more bytes long) at the specified options pointer) + * + * @param pcb tcp_pcb + * @param opts option pointer where to store the SACK option + * @param num_sacks the number of SACKs to store + */ +static void +tcp_build_sack_option(const struct tcp_pcb *pcb, u32_t *opts, u8_t num_sacks) +{ + u8_t i; + + LWIP_ASSERT("tcp_build_sack_option: invalid pcb", pcb != NULL); + LWIP_ASSERT("tcp_build_sack_option: invalid opts", opts != NULL); + + /* Pad with two NOP options to make everything nicely aligned. + We add the length (of just the SACK option, not the NOPs in front of it), + which is 2B of header, plus 8B for each SACK. */ + *(opts++) = PP_HTONL(0x01010500 + 2 + num_sacks * 8); + + for (i = 0; i < num_sacks; ++i) { + *(opts++) = lwip_htonl(pcb->rcv_sacks[i].left); + *(opts++) = lwip_htonl(pcb->rcv_sacks[i].right); + } +} + +#endif + +#if LWIP_WND_SCALE +/** Build a window scale option (3 bytes long) at the specified options pointer) + * + * @param opts option pointer where to store the window scale option + */ +static void +tcp_build_wnd_scale_option(u32_t *opts) +{ + LWIP_ASSERT("tcp_build_wnd_scale_option: invalid opts", opts != NULL); + + /* Pad with one NOP option to make everything nicely aligned */ + opts[0] = PP_HTONL(0x01030300 | TCP_RCV_SCALE); +} +#endif + +/** + * @ingroup tcp_raw + * Find out what we can send and send it + * + * @param pcb Protocol control block for the TCP connection to send data + * @return ERR_OK if data has been sent or nothing to send + * another err_t on error + */ +err_t +tcp_output(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg, *useg; + u32_t wnd, snd_nxt; + err_t err; + struct netif *netif; +#if TCP_CWND_DEBUG + s16_t i = 0; +#endif /* TCP_CWND_DEBUG */ + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("tcp_output: invalid pcb", pcb != NULL); + /* pcb->state LISTEN not allowed here */ + LWIP_ASSERT("don't call tcp_output for listen-pcbs", + pcb->state != LISTEN); + + /* First, check if we are invoked by the TCP input processing + code. If so, we do not output anything. Instead, we rely on the + input processing code to call us when input processing is done + with. */ + if (tcp_input_pcb == pcb) { + return ERR_OK; + } + + wnd = LWIP_MIN(pcb->snd_wnd, pcb->cwnd); + + seg = pcb->unsent; + + if (seg == NULL) { + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: nothing to send (%p)\n", + (void *)pcb->unsent)); + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"TCPWNDSIZE_F + ", cwnd %"TCPWNDSIZE_F", wnd %"U32_F + ", seg == NULL, ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, pcb->lastack)); + + /* If the TF_ACK_NOW flag is set and the ->unsent queue is empty, construct + * an empty ACK segment and send it. */ + if (pcb->flags & TF_ACK_NOW) { + return tcp_send_empty_ack(pcb); + } + /* nothing to send: shortcut out of here */ + goto output_done; + } else { + LWIP_DEBUGF(TCP_CWND_DEBUG, + ("tcp_output: snd_wnd %"TCPWNDSIZE_F", cwnd %"TCPWNDSIZE_F", wnd %"U32_F + ", effwnd %"U32_F", seq %"U32_F", ack %"U32_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len, + lwip_ntohl(seg->tcphdr->seqno), pcb->lastack)); + } + + netif = tcp_route(pcb, &pcb->local_ip, &pcb->remote_ip); + if (netif == NULL) { + return ERR_RTE; + } + + /* If we don't have a local IP address, we get one from netif */ + if (ip_addr_isany(&pcb->local_ip)) { + const ip_addr_t *local_ip = ip_netif_get_local_ip(netif, &pcb->remote_ip); + if (local_ip == NULL) { + return ERR_RTE; + } + ip_addr_copy(pcb->local_ip, *local_ip); + } + + /* Handle the current segment not fitting within the window */ + if (lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len > wnd) { + /* We need to start the persistent timer when the next unsent segment does not fit + * within the remaining (could be 0) send window and RTO timer is not running (we + * have no in-flight data). If window is still too small after persist timer fires, + * then we split the segment. We don't consider the congestion window since a cwnd + * smaller than 1 SMSS implies in-flight data + */ + if (wnd == pcb->snd_wnd && pcb->unacked == NULL && pcb->persist_backoff == 0) { + pcb->persist_cnt = 0; + pcb->persist_backoff = 1; + pcb->persist_probe = 0; + } + /* We need an ACK, but can't send data now, so send an empty ACK */ + if (pcb->flags & TF_ACK_NOW) { + return tcp_send_empty_ack(pcb); + } + goto output_done; + } + /* Stop persist timer, above conditions are not active */ + pcb->persist_backoff = 0; + + /* useg should point to last segment on unacked queue */ + useg = pcb->unacked; + if (useg != NULL) { + for (; useg->next != NULL; useg = useg->next); + } + /* data available and window allows it to be sent? */ + while (seg != NULL && + lwip_ntohl(seg->tcphdr->seqno) - pcb->lastack + seg->len <= wnd) { + LWIP_ASSERT("RST not expected here!", + (TCPH_FLAGS(seg->tcphdr) & TCP_RST) == 0); + /* Stop sending if the nagle algorithm would prevent it + * Don't stop: + * - if tcp_write had a memory error before (prevent delayed ACK timeout) or + * - if FIN was already enqueued for this PCB (SYN is always alone in a segment - + * either seg->next != NULL or pcb->unacked == NULL; + * RST is no sent using tcp_write/tcp_output. + */ + if ((tcp_do_output_nagle(pcb) == 0) && + ((pcb->flags & (TF_NAGLEMEMERR | TF_FIN)) == 0)) { + break; + } +#if TCP_CWND_DEBUG + LWIP_DEBUGF(TCP_CWND_DEBUG, ("tcp_output: snd_wnd %"TCPWNDSIZE_F", cwnd %"TCPWNDSIZE_F", wnd %"U32_F", effwnd %"U32_F", seq %"U32_F", ack %"U32_F", i %"S16_F"\n", + pcb->snd_wnd, pcb->cwnd, wnd, + lwip_ntohl(seg->tcphdr->seqno) + seg->len - + pcb->lastack, + lwip_ntohl(seg->tcphdr->seqno), pcb->lastack, i)); + ++i; +#endif /* TCP_CWND_DEBUG */ + + if (pcb->state != SYN_SENT) { + TCPH_SET_FLAG(seg->tcphdr, TCP_ACK); + } + + err = tcp_output_segment(seg, pcb, netif); + if (err != ERR_OK) { + /* segment could not be sent, for whatever reason */ + tcp_set_flags(pcb, TF_NAGLEMEMERR); + return err; + } +#if TCP_OVERSIZE_DBGCHECK + seg->oversize_left = 0; +#endif /* TCP_OVERSIZE_DBGCHECK */ + pcb->unsent = seg->next; + if (pcb->state != SYN_SENT) { + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + } + snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + pcb->snd_nxt = snd_nxt; + } + /* put segment on unacknowledged list if length > 0 */ + if (TCP_TCPLEN(seg) > 0) { + seg->next = NULL; + /* unacked list is empty? */ + if (pcb->unacked == NULL) { + pcb->unacked = seg; + useg = seg; + /* unacked list is not empty? */ + } else { + /* In the case of fast retransmit, the packet should not go to the tail + * of the unacked queue, but rather somewhere before it. We need to check for + * this case. -STJ Jul 27, 2004 */ + if (TCP_SEQ_LT(lwip_ntohl(seg->tcphdr->seqno), lwip_ntohl(useg->tcphdr->seqno))) { + /* add segment to before tail of unacked list, keeping the list sorted */ + struct tcp_seg **cur_seg = &(pcb->unacked); + while (*cur_seg && + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + } + seg->next = (*cur_seg); + (*cur_seg) = seg; + } else { + /* add segment to tail of unacked list */ + useg->next = seg; + useg = useg->next; + } + } + /* do not queue empty segments on the unacked list */ + } else { + tcp_seg_free(seg); + } + seg = pcb->unsent; + } +#if TCP_OVERSIZE + if (pcb->unsent == NULL) { + /* last unsent has been removed, reset unsent_oversize */ + pcb->unsent_oversize = 0; + } +#endif /* TCP_OVERSIZE */ + +output_done: + tcp_clear_flags(pcb, TF_NAGLEMEMERR); + return ERR_OK; +} + +/** Check if a segment's pbufs are used by someone else than TCP. + * This can happen on retransmission if the pbuf of this segment is still + * referenced by the netif driver due to deferred transmission. + * This is the case (only!) if someone down the TX call path called + * pbuf_ref() on one of the pbufs! + * + * @arg seg the tcp segment to check + * @return 1 if ref != 1, 0 if ref == 1 + */ +static int +tcp_output_segment_busy(const struct tcp_seg *seg) +{ + LWIP_ASSERT("tcp_output_segment_busy: invalid seg", seg != NULL); + + /* We only need to check the first pbuf here: + If a pbuf is queued for transmission, a driver calls pbuf_ref(), + which only changes the ref count of the first pbuf */ + if (seg->p->ref != 1) { + /* other reference found */ + return 1; + } + /* no other references found */ + return 0; +} + +/** + * Called by tcp_output() to actually send a TCP segment over IP. + * + * @param seg the tcp_seg to send + * @param pcb the tcp_pcb for the TCP connection used to send the segment + * @param netif the netif used to send the segment + */ +static err_t +tcp_output_segment(struct tcp_seg *seg, struct tcp_pcb *pcb, struct netif *netif) +{ + err_t err; + u16_t len; + u32_t *opts; +#if TCP_CHECKSUM_ON_COPY + int seg_chksum_was_swapped = 0; +#endif + + LWIP_ASSERT("tcp_output_segment: invalid seg", seg != NULL); + LWIP_ASSERT("tcp_output_segment: invalid pcb", pcb != NULL); + LWIP_ASSERT("tcp_output_segment: invalid netif", netif != NULL); + + if (tcp_output_segment_busy(seg)) { + /* This should not happen: rexmit functions should have checked this. + However, since this function modifies p->len, we must not continue in this case. */ + LWIP_DEBUGF(TCP_RTO_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("tcp_output_segment: segment busy\n")); + return ERR_OK; + } + + /* The TCP header has already been constructed, but the ackno and + wnd fields remain. */ + seg->tcphdr->ackno = lwip_htonl(pcb->rcv_nxt); + + /* advertise our receive window size in this TCP segment */ +#if LWIP_WND_SCALE + if (seg->flags & TF_SEG_OPTS_WND_SCALE) { + /* The Window field in a SYN segment itself (the only type where we send + the window scale option) is never scaled. */ + seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(pcb->rcv_ann_wnd)); + } else +#endif /* LWIP_WND_SCALE */ + { + seg->tcphdr->wnd = lwip_htons(TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); + } + + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + + /* Add any requested options. NB MSS option is only set on SYN + packets, so ignore it here */ + /* cast through void* to get rid of alignment warnings */ + opts = (u32_t *)(void *)(seg->tcphdr + 1); + if (seg->flags & TF_SEG_OPTS_MSS) { + u16_t mss; +#if TCP_CALCULATE_EFF_SEND_MSS + mss = tcp_eff_send_mss_netif(TCP_MSS, netif, &pcb->remote_ip); +#else /* TCP_CALCULATE_EFF_SEND_MSS */ + mss = TCP_MSS; +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + *opts = TCP_BUILD_MSS_OPTION(mss); + opts += 1; + } +#if LWIP_TCP_TIMESTAMPS + pcb->ts_lastacksent = pcb->rcv_nxt; + + if (seg->flags & TF_SEG_OPTS_TS) { + tcp_build_timestamp_option(pcb, opts); + opts += 3; + } +#endif +#if LWIP_WND_SCALE + if (seg->flags & TF_SEG_OPTS_WND_SCALE) { + tcp_build_wnd_scale_option(opts); + opts += 1; + } +#endif +#if LWIP_TCP_SACK_OUT + if (seg->flags & TF_SEG_OPTS_SACK_PERM) { + /* Pad with two NOP options to make everything nicely aligned + * NOTE: When we send both timestamp and SACK_PERM options, + * we could use the first two NOPs before the timestamp to store SACK_PERM option, + * but that would complicate the code. + */ + *(opts++) = PP_HTONL(0x01010402); + } +#endif + + /* Set retransmission timer running if it is not currently enabled + This must be set before checking the route. */ + if (pcb->rtime < 0) { + pcb->rtime = 0; + } + + if (pcb->rttest == 0) { + pcb->rttest = tcp_ticks; + pcb->rtseq = lwip_ntohl(seg->tcphdr->seqno); + + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_output_segment: rtseq %"U32_F"\n", pcb->rtseq)); + } + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output_segment: %"U32_F":%"U32_F"\n", + lwip_htonl(seg->tcphdr->seqno), lwip_htonl(seg->tcphdr->seqno) + + seg->len)); + + len = (u16_t)((u8_t *)seg->tcphdr - (u8_t *)seg->p->payload); + if (len == 0) { + /** Exclude retransmitted segments from this count. */ + MIB2_STATS_INC(mib2.tcpoutsegs); + } + + seg->p->len -= len; + seg->p->tot_len -= len; + + seg->p->payload = seg->tcphdr; + + seg->tcphdr->chksum = 0; + +#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS + opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(seg->p, seg->tcphdr, pcb, opts); +#endif + LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(seg->tcphdr + 1)) + LWIP_TCP_OPT_LENGTH_SEGMENT(seg->flags, pcb)); + +#if CHECKSUM_GEN_TCP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) { +#if TCP_CHECKSUM_ON_COPY + u32_t acc; +#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK + u16_t chksum_slow = ip_chksum_pseudo(seg->p, IP_PROTO_TCP, + seg->p->tot_len, &pcb->local_ip, &pcb->remote_ip); +#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */ + if ((seg->flags & TF_SEG_DATA_CHECKSUMMED) == 0) { + LWIP_ASSERT("data included but not checksummed", + seg->p->tot_len == TCPH_HDRLEN_BYTES(seg->tcphdr)); + } + + /* rebuild TCP header checksum (TCP header changes for retransmissions!) */ + acc = ip_chksum_pseudo_partial(seg->p, IP_PROTO_TCP, + seg->p->tot_len, TCPH_HDRLEN_BYTES(seg->tcphdr), &pcb->local_ip, &pcb->remote_ip); + /* add payload checksum */ + if (seg->chksum_swapped) { + seg_chksum_was_swapped = 1; + seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum); + seg->chksum_swapped = 0; + } + acc = (u16_t)~acc + seg->chksum; + seg->tcphdr->chksum = (u16_t)~FOLD_U32T(acc); +#if TCP_CHECKSUM_ON_COPY_SANITY_CHECK + if (chksum_slow != seg->tcphdr->chksum) { + TCP_CHECKSUM_ON_COPY_SANITY_CHECK_FAIL( + ("tcp_output_segment: calculated checksum is %"X16_F" instead of %"X16_F"\n", + seg->tcphdr->chksum, chksum_slow)); + seg->tcphdr->chksum = chksum_slow; + } +#endif /* TCP_CHECKSUM_ON_COPY_SANITY_CHECK */ +#else /* TCP_CHECKSUM_ON_COPY */ + seg->tcphdr->chksum = ip_chksum_pseudo(seg->p, IP_PROTO_TCP, + seg->p->tot_len, &pcb->local_ip, &pcb->remote_ip); +#endif /* TCP_CHECKSUM_ON_COPY */ + } +#endif /* CHECKSUM_GEN_TCP */ + TCP_STATS_INC(tcp.xmit); + + NETIF_SET_HINTS(netif, &(pcb->netif_hints)); + err = ip_output_if(seg->p, &pcb->local_ip, &pcb->remote_ip, pcb->ttl, + pcb->tos, IP_PROTO_TCP, netif); + NETIF_RESET_HINTS(netif); + +#if TCP_CHECKSUM_ON_COPY + if (seg_chksum_was_swapped) { + /* if data is added to this segment later, chksum needs to be swapped, + so restore this now */ + seg->chksum = SWAP_BYTES_IN_WORD(seg->chksum); + seg->chksum_swapped = 1; + } +#endif + + return err; +} + +/** + * Requeue all unacked segments for retransmission + * + * Called by tcp_slowtmr() for slow retransmission. + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +err_t +tcp_rexmit_rto_prepare(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + + LWIP_ASSERT("tcp_rexmit_rto_prepare: invalid pcb", pcb != NULL); + + if (pcb->unacked == NULL) { + return ERR_VAL; + } + + /* Move all unacked segments to the head of the unsent queue. + However, give up if any of the unsent pbufs are still referenced by the + netif driver due to deferred transmission. No point loading the link further + if it is struggling to flush its buffered writes. */ + for (seg = pcb->unacked; seg->next != NULL; seg = seg->next) { + if (tcp_output_segment_busy(seg)) { + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); + return ERR_VAL; + } + } + if (tcp_output_segment_busy(seg)) { + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit_rto: segment busy\n")); + return ERR_VAL; + } + /* concatenate unsent queue after unacked queue */ + seg->next = pcb->unsent; +#if TCP_OVERSIZE_DBGCHECK + /* if last unsent changed, we need to update unsent_oversize */ + if (pcb->unsent == NULL) { + pcb->unsent_oversize = seg->oversize_left; + } +#endif /* TCP_OVERSIZE_DBGCHECK */ + /* unsent queue is the concatenated queue (of unacked, unsent) */ + pcb->unsent = pcb->unacked; + /* unacked queue is now empty */ + pcb->unacked = NULL; + + /* Mark RTO in-progress */ + tcp_set_flags(pcb, TF_RTO); + /* Record the next byte following retransmit */ + pcb->rto_end = lwip_ntohl(seg->tcphdr->seqno) + TCP_TCPLEN(seg); + /* Don't take any RTT measurements after retransmitting. */ + pcb->rttest = 0; + + return ERR_OK; +} + +/** + * Requeue all unacked segments for retransmission + * + * Called by tcp_slowtmr() for slow retransmission. + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto_commit(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_rexmit_rto_commit: invalid pcb", pcb != NULL); + + /* increment number of retransmissions */ + if (pcb->nrtx < 0xFF) { + ++pcb->nrtx; + } + /* Do the actual retransmission */ + tcp_output(pcb); +} + +/** + * Requeue all unacked segments for retransmission + * + * Called by tcp_process() only, tcp_slowtmr() needs to do some things between + * "prepare" and "commit". + * + * @param pcb the tcp_pcb for which to re-enqueue all unacked segments + */ +void +tcp_rexmit_rto(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_rexmit_rto: invalid pcb", pcb != NULL); + + if (tcp_rexmit_rto_prepare(pcb) == ERR_OK) { + tcp_rexmit_rto_commit(pcb); + } +} + +/** + * Requeue the first unacked segment for retransmission + * + * Called by tcp_receive() for fast retransmit. + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +err_t +tcp_rexmit(struct tcp_pcb *pcb) +{ + struct tcp_seg *seg; + struct tcp_seg **cur_seg; + + LWIP_ASSERT("tcp_rexmit: invalid pcb", pcb != NULL); + + if (pcb->unacked == NULL) { + return ERR_VAL; + } + + seg = pcb->unacked; + + /* Give up if the segment is still referenced by the netif driver + due to deferred transmission. */ + if (tcp_output_segment_busy(seg)) { + LWIP_DEBUGF(TCP_RTO_DEBUG, ("tcp_rexmit busy\n")); + return ERR_VAL; + } + + /* Move the first unacked segment to the unsent queue */ + /* Keep the unsent queue sorted. */ + pcb->unacked = seg->next; + + cur_seg = &(pcb->unsent); + while (*cur_seg && + TCP_SEQ_LT(lwip_ntohl((*cur_seg)->tcphdr->seqno), lwip_ntohl(seg->tcphdr->seqno))) { + cur_seg = &((*cur_seg)->next ); + } + seg->next = *cur_seg; + *cur_seg = seg; +#if TCP_OVERSIZE + if (seg->next == NULL) { + /* the retransmitted segment is last in unsent, so reset unsent_oversize */ + pcb->unsent_oversize = 0; + } +#endif /* TCP_OVERSIZE */ + + if (pcb->nrtx < 0xFF) { + ++pcb->nrtx; + } + + /* Don't take any rtt measurements after retransmitting. */ + pcb->rttest = 0; + + /* Do the actual retransmission. */ + MIB2_STATS_INC(mib2.tcpretranssegs); + /* No need to call tcp_output: we are always called from tcp_input() + and thus tcp_output directly returns. */ + return ERR_OK; +} + + +/** + * Handle retransmission after three dupacks received + * + * @param pcb the tcp_pcb for which to retransmit the first unacked segment + */ +void +tcp_rexmit_fast(struct tcp_pcb *pcb) +{ + LWIP_ASSERT("tcp_rexmit_fast: invalid pcb", pcb != NULL); + + if (pcb->unacked != NULL && !(pcb->flags & TF_INFR)) { + /* This is fast retransmit. Retransmit the first unacked segment. */ + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: dupacks %"U16_F" (%"U32_F + "), fast retransmit %"U32_F"\n", + (u16_t)pcb->dupacks, pcb->lastack, + lwip_ntohl(pcb->unacked->tcphdr->seqno))); + if (tcp_rexmit(pcb) == ERR_OK) { + /* Set ssthresh to half of the minimum of the current + * cwnd and the advertised window */ + pcb->ssthresh = LWIP_MIN(pcb->cwnd, pcb->snd_wnd) / 2; + + /* The minimum value for ssthresh should be 2 MSS */ + if (pcb->ssthresh < (2U * pcb->mss)) { + LWIP_DEBUGF(TCP_FR_DEBUG, + ("tcp_receive: The minimum value for ssthresh %"TCPWNDSIZE_F + " should be min 2 mss %"U16_F"...\n", + pcb->ssthresh, (u16_t)(2 * pcb->mss))); + pcb->ssthresh = 2 * pcb->mss; + } + + pcb->cwnd = pcb->ssthresh + 3 * pcb->mss; + tcp_set_flags(pcb, TF_INFR); + + /* Reset the retransmission timer to prevent immediate rto retransmissions */ + pcb->rtime = 0; + } + } +} + +static struct pbuf * +tcp_output_alloc_header_common(u32_t ackno, u16_t optlen, u16_t datalen, + u32_t seqno_be /* already in network byte order */, + u16_t src_port, u16_t dst_port, u8_t flags, u16_t wnd) +{ + struct tcp_hdr *tcphdr; + struct pbuf *p; + + p = pbuf_alloc(PBUF_IP, TCP_HLEN + optlen + datalen, PBUF_RAM); + if (p != NULL) { + LWIP_ASSERT("check that first pbuf can hold struct tcp_hdr", + (p->len >= TCP_HLEN + optlen)); + tcphdr = (struct tcp_hdr *)p->payload; + tcphdr->src = lwip_htons(src_port); + tcphdr->dest = lwip_htons(dst_port); + tcphdr->seqno = seqno_be; + tcphdr->ackno = lwip_htonl(ackno); + TCPH_HDRLEN_FLAGS_SET(tcphdr, (5 + optlen / 4), flags); + tcphdr->wnd = lwip_htons(wnd); + tcphdr->chksum = 0; + tcphdr->urgp = 0; + } + return p; +} + +/** Allocate a pbuf and create a tcphdr at p->payload, used for output + * functions other than the default tcp_output -> tcp_output_segment + * (e.g. tcp_send_empty_ack, etc.) + * + * @param pcb tcp pcb for which to send a packet (used to initialize tcp_hdr) + * @param optlen length of header-options + * @param datalen length of tcp data to reserve in pbuf + * @param seqno_be seqno in network byte order (big-endian) + * @return pbuf with p->payload being the tcp_hdr + */ +static struct pbuf * +tcp_output_alloc_header(struct tcp_pcb *pcb, u16_t optlen, u16_t datalen, + u32_t seqno_be /* already in network byte order */) +{ + struct pbuf *p; + + LWIP_ASSERT("tcp_output_alloc_header: invalid pcb", pcb != NULL); + + p = tcp_output_alloc_header_common(pcb->rcv_nxt, optlen, datalen, + seqno_be, pcb->local_port, pcb->remote_port, TCP_ACK, + TCPWND_MIN16(RCV_WND_SCALE(pcb, pcb->rcv_ann_wnd))); + if (p != NULL) { + /* If we're sending a packet, update the announced right window edge */ + pcb->rcv_ann_right_edge = pcb->rcv_nxt + pcb->rcv_ann_wnd; + } + return p; +} + +/* Fill in options for control segments */ +static void +tcp_output_fill_options(const struct tcp_pcb *pcb, struct pbuf *p, u8_t optflags, u8_t num_sacks) +{ + struct tcp_hdr *tcphdr; + u32_t *opts; + u16_t sacks_len = 0; + + LWIP_ASSERT("tcp_output_fill_options: invalid pbuf", p != NULL); + + tcphdr = (struct tcp_hdr *)p->payload; + opts = (u32_t *)(void *)(tcphdr + 1); + + /* NB. MSS and window scale options are only sent on SYNs, so ignore them here */ + +#if LWIP_TCP_TIMESTAMPS + if (optflags & TF_SEG_OPTS_TS) { + tcp_build_timestamp_option(pcb, opts); + opts += 3; + } +#endif + +#if LWIP_TCP_SACK_OUT + if (pcb && (num_sacks > 0)) { + tcp_build_sack_option(pcb, opts, num_sacks); + /* 1 word for SACKs header (including 2xNOP), and 2 words for each SACK */ + sacks_len = 1 + num_sacks * 2; + opts += sacks_len; + } +#else + LWIP_UNUSED_ARG(num_sacks); +#endif + +#ifdef LWIP_HOOK_TCP_OUT_ADD_TCPOPTS + opts = LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, tcphdr, pcb, opts); +#endif + + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(sacks_len); + LWIP_ASSERT("options not filled", (u8_t *)opts == ((u8_t *)(tcphdr + 1)) + sacks_len * 4 + LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb)); + LWIP_UNUSED_ARG(optflags); /* for LWIP_NOASSERT */ + LWIP_UNUSED_ARG(opts); /* for LWIP_NOASSERT */ +} + +/** Output a control segment pbuf to IP. + * + * Called from tcp_rst, tcp_send_empty_ack, tcp_keepalive and tcp_zero_window_probe, + * this function combines selecting a netif for transmission, generating the tcp + * header checksum and calling ip_output_if while handling netif hints and stats. + */ +static err_t +tcp_output_control_segment(const struct tcp_pcb *pcb, struct pbuf *p, + const ip_addr_t *src, const ip_addr_t *dst) +{ + err_t err; + struct netif *netif; + + LWIP_ASSERT("tcp_output_control_segment: invalid pbuf", p != NULL); + + netif = tcp_route(pcb, src, dst); + if (netif == NULL) { + err = ERR_RTE; + } else { + u8_t ttl, tos; +#if CHECKSUM_GEN_TCP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_TCP) { + struct tcp_hdr *tcphdr = (struct tcp_hdr *)p->payload; + tcphdr->chksum = ip_chksum_pseudo(p, IP_PROTO_TCP, p->tot_len, + src, dst); + } +#endif + if (pcb != NULL) { + NETIF_SET_HINTS(netif, LWIP_CONST_CAST(struct netif_hint*, &(pcb->netif_hints))); + ttl = pcb->ttl; + tos = pcb->tos; + } else { + /* Send output with hardcoded TTL/HL since we have no access to the pcb */ + ttl = TCP_TTL; + tos = 0; + } + TCP_STATS_INC(tcp.xmit); + err = ip_output_if(p, src, dst, ttl, tos, IP_PROTO_TCP, netif); + NETIF_RESET_HINTS(netif); + } + pbuf_free(p); + return err; +} + +/** + * Send a TCP RESET packet (empty segment with RST flag set) either to + * abort a connection or to show that there is no matching local connection + * for a received segment. + * + * Called by tcp_abort() (to abort a local connection), tcp_input() (if no + * matching local pcb was found), tcp_listen_input() (if incoming segment + * has ACK flag set) and tcp_process() (received segment in the wrong state) + * + * Since a RST segment is in most cases not sent for an active connection, + * tcp_rst() has a number of arguments that are taken from a tcp_pcb for + * most other segment output functions. + * + * @param pcb TCP pcb (may be NULL if no pcb is available) + * @param seqno the sequence number to use for the outgoing segment + * @param ackno the acknowledge number to use for the outgoing segment + * @param local_ip the local IP address to send the segment from + * @param remote_ip the remote IP address to send the segment to + * @param local_port the local TCP port to send the segment from + * @param remote_port the remote TCP port to send the segment to + */ +void +tcp_rst(const struct tcp_pcb *pcb, u32_t seqno, u32_t ackno, + const ip_addr_t *local_ip, const ip_addr_t *remote_ip, + u16_t local_port, u16_t remote_port) +{ + struct pbuf *p; + u16_t wnd; + u8_t optlen; + + LWIP_ASSERT("tcp_rst: invalid local_ip", local_ip != NULL); + LWIP_ASSERT("tcp_rst: invalid remote_ip", remote_ip != NULL); + + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + +#if LWIP_WND_SCALE + wnd = PP_HTONS(((TCP_WND >> TCP_RCV_SCALE) & 0xFFFF)); +#else + wnd = PP_HTONS(TCP_WND); +#endif + + p = tcp_output_alloc_header_common(ackno, optlen, 0, lwip_htonl(seqno), local_port, + remote_port, TCP_RST | TCP_ACK, wnd); + if (p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_rst: could not allocate memory for pbuf\n")); + return; + } + tcp_output_fill_options(pcb, p, 0, optlen); + + MIB2_STATS_INC(mib2.tcpoutrsts); + + tcp_output_control_segment(pcb, p, local_ip, remote_ip); + LWIP_DEBUGF(TCP_RST_DEBUG, ("tcp_rst: seqno %"U32_F" ackno %"U32_F".\n", seqno, ackno)); +} + +/** + * Send an ACK without data. + * + * @param pcb Protocol control block for the TCP connection to send the ACK + */ +err_t +tcp_send_empty_ack(struct tcp_pcb *pcb) +{ + err_t err; + struct pbuf *p; + u8_t optlen, optflags = 0; + u8_t num_sacks = 0; + + LWIP_ASSERT("tcp_send_empty_ack: invalid pcb", pcb != NULL); + +#if LWIP_TCP_TIMESTAMPS + if (pcb->flags & TF_TIMESTAMP) { + optflags = TF_SEG_OPTS_TS; + } +#endif + optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(optflags, pcb); + +#if LWIP_TCP_SACK_OUT + /* For now, SACKs are only sent with empty ACKs */ + if ((num_sacks = tcp_get_num_sacks(pcb, optlen)) > 0) { + optlen += 4 + num_sacks * 8; /* 4 bytes for header (including 2*NOP), plus 8B for each SACK */ + } +#endif + + p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt)); + if (p == NULL) { + /* let tcp_fasttmr retry sending this ACK */ + tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, ("tcp_output: (ACK) could not allocate pbuf\n")); + return ERR_BUF; + } + tcp_output_fill_options(pcb, p, optflags, num_sacks); + +#if LWIP_TCP_TIMESTAMPS + pcb->ts_lastacksent = pcb->rcv_nxt; +#endif + + LWIP_DEBUGF(TCP_OUTPUT_DEBUG, + ("tcp_output: sending ACK for %"U32_F"\n", pcb->rcv_nxt)); + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + if (err != ERR_OK) { + /* let tcp_fasttmr retry sending this ACK */ + tcp_set_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + } else { + /* remove ACK flags from the PCB, as we sent an empty ACK now */ + tcp_clear_flags(pcb, TF_ACK_DELAY | TF_ACK_NOW); + } + + return err; +} + +/** + * Send keepalive packets to keep a connection active although + * no data is sent over it. + * + * Called by tcp_slowtmr() + * + * @param pcb the tcp_pcb for which to send a keepalive packet + */ +err_t +tcp_keepalive(struct tcp_pcb *pcb) +{ + err_t err; + struct pbuf *p; + u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + + LWIP_ASSERT("tcp_keepalive: invalid pcb", pcb != NULL); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: sending KEEPALIVE probe to ")); + ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: tcp_ticks %"U32_F" pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); + + p = tcp_output_alloc_header(pcb, optlen, 0, lwip_htonl(pcb->snd_nxt - 1)); + if (p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_keepalive: could not allocate memory for pbuf\n")); + return ERR_MEM; + } + tcp_output_fill_options(pcb, p, 0, optlen); + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_keepalive: seqno %"U32_F" ackno %"U32_F" err %d.\n", + pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); + return err; +} + +/** + * Send persist timer zero-window probes to keep a connection active + * when a window update is lost. + * + * Called by tcp_slowtmr() + * + * @param pcb the tcp_pcb for which to send a zero-window probe packet + */ +err_t +tcp_zero_window_probe(struct tcp_pcb *pcb) +{ + err_t err; + struct pbuf *p; + struct tcp_hdr *tcphdr; + struct tcp_seg *seg; + u16_t len; + u8_t is_fin; + u32_t snd_nxt; + u8_t optlen = LWIP_TCP_OPT_LENGTH_SEGMENT(0, pcb); + + LWIP_ASSERT("tcp_zero_window_probe: invalid pcb", pcb != NULL); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: sending ZERO WINDOW probe to ")); + ip_addr_debug_print_val(TCP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(TCP_DEBUG, ("\n")); + + LWIP_DEBUGF(TCP_DEBUG, + ("tcp_zero_window_probe: tcp_ticks %"U32_F + " pcb->tmr %"U32_F" pcb->keep_cnt_sent %"U16_F"\n", + tcp_ticks, pcb->tmr, (u16_t)pcb->keep_cnt_sent)); + + /* Only consider unsent, persist timer should be off when there is data in-flight */ + seg = pcb->unsent; + if (seg == NULL) { + /* Not expected, persist timer should be off when the send buffer is empty */ + return ERR_OK; + } + + /* increment probe count. NOTE: we record probe even if it fails + to actually transmit due to an error. This ensures memory exhaustion/ + routing problem doesn't leave a zero-window pcb as an indefinite zombie. + RTO mechanism has similar behavior, see pcb->nrtx */ + if (pcb->persist_probe < 0xFF) { + ++pcb->persist_probe; + } + + is_fin = ((TCPH_FLAGS(seg->tcphdr) & TCP_FIN) != 0) && (seg->len == 0); + /* we want to send one seqno: either FIN or data (no options) */ + len = is_fin ? 0 : 1; + + p = tcp_output_alloc_header(pcb, optlen, len, seg->tcphdr->seqno); + if (p == NULL) { + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: no memory for pbuf\n")); + return ERR_MEM; + } + tcphdr = (struct tcp_hdr *)p->payload; + + if (is_fin) { + /* FIN segment, no data */ + TCPH_FLAGS_SET(tcphdr, TCP_ACK | TCP_FIN); + } else { + /* Data segment, copy in one byte from the head of the unacked queue */ + char *d = ((char *)p->payload + TCP_HLEN); + /* Depending on whether the segment has already been sent (unacked) or not + (unsent), seg->p->payload points to the IP header or TCP header. + Ensure we copy the first TCP data byte: */ + pbuf_copy_partial(seg->p, d, 1, seg->p->tot_len - seg->len); + } + + /* The byte may be acknowledged without the window being opened. */ + snd_nxt = lwip_ntohl(seg->tcphdr->seqno) + 1; + if (TCP_SEQ_LT(pcb->snd_nxt, snd_nxt)) { + pcb->snd_nxt = snd_nxt; + } + tcp_output_fill_options(pcb, p, 0, optlen); + + err = tcp_output_control_segment(pcb, p, &pcb->local_ip, &pcb->remote_ip); + + LWIP_DEBUGF(TCP_DEBUG, ("tcp_zero_window_probe: seqno %"U32_F + " ackno %"U32_F" err %d.\n", + pcb->snd_nxt - 1, pcb->rcv_nxt, (int)err)); + return err; +} +#endif /* LWIP_TCP */ diff --git a/Middlewares/Third_Party/LwIP/src/core/timeouts.c b/Middlewares/Third_Party/LwIP/src/core/timeouts.c new file mode 100644 index 0000000..f37acfe --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/timeouts.c @@ -0,0 +1,451 @@ +/** + * @file + * Stack-internal timers implementation. + * This file includes timer callbacks for stack-internal timers as well as + * functions to set up or stop timers and check for expired timers. + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ + +#include "lwip/opt.h" + +#include "lwip/timeouts.h" +#include "lwip/priv/tcp_priv.h" + +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/priv/tcpip_priv.h" + +#include "lwip/ip4_frag.h" +#include "lwip/etharp.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" +#include "lwip/nd6.h" +#include "lwip/ip6_frag.h" +#include "lwip/mld6.h" +#include "lwip/dhcp6.h" +#include "lwip/sys.h" +#include "lwip/pbuf.h" + +#if LWIP_DEBUG_TIMERNAMES +#define HANDLER(x) x, #x +#else /* LWIP_DEBUG_TIMERNAMES */ +#define HANDLER(x) x +#endif /* LWIP_DEBUG_TIMERNAMES */ + +#define LWIP_MAX_TIMEOUT 0x7fffffff + +/* Check if timer's expiry time is greater than time and care about u32_t wraparounds */ +#define TIME_LESS_THAN(t, compare_to) ( (((u32_t)((t)-(compare_to))) > LWIP_MAX_TIMEOUT) ? 1 : 0 ) + +/** This array contains all stack-internal cyclic timers. To get the number of + * timers, use LWIP_ARRAYSIZE() */ +const struct lwip_cyclic_timer lwip_cyclic_timers[] = { +#if LWIP_TCP + /* The TCP timer is a special case: it does not have to run always and + is triggered to start from TCP using tcp_timer_needed() */ + {TCP_TMR_INTERVAL, HANDLER(tcp_tmr)}, +#endif /* LWIP_TCP */ +#if LWIP_IPV4 +#if IP_REASSEMBLY + {IP_TMR_INTERVAL, HANDLER(ip_reass_tmr)}, +#endif /* IP_REASSEMBLY */ +#if LWIP_ARP + {ARP_TMR_INTERVAL, HANDLER(etharp_tmr)}, +#endif /* LWIP_ARP */ +#if LWIP_DHCP + {DHCP_COARSE_TIMER_MSECS, HANDLER(dhcp_coarse_tmr)}, + {DHCP_FINE_TIMER_MSECS, HANDLER(dhcp_fine_tmr)}, +#endif /* LWIP_DHCP */ +#if LWIP_AUTOIP + {AUTOIP_TMR_INTERVAL, HANDLER(autoip_tmr)}, +#endif /* LWIP_AUTOIP */ +#if LWIP_IGMP + {IGMP_TMR_INTERVAL, HANDLER(igmp_tmr)}, +#endif /* LWIP_IGMP */ +#endif /* LWIP_IPV4 */ +#if LWIP_DNS + {DNS_TMR_INTERVAL, HANDLER(dns_tmr)}, +#endif /* LWIP_DNS */ +#if LWIP_IPV6 + {ND6_TMR_INTERVAL, HANDLER(nd6_tmr)}, +#if LWIP_IPV6_REASS + {IP6_REASS_TMR_INTERVAL, HANDLER(ip6_reass_tmr)}, +#endif /* LWIP_IPV6_REASS */ +#if LWIP_IPV6_MLD + {MLD6_TMR_INTERVAL, HANDLER(mld6_tmr)}, +#endif /* LWIP_IPV6_MLD */ +#if LWIP_IPV6_DHCP6 + {DHCP6_TIMER_MSECS, HANDLER(dhcp6_tmr)}, +#endif /* LWIP_IPV6_DHCP6 */ +#endif /* LWIP_IPV6 */ +}; +const int lwip_num_cyclic_timers = LWIP_ARRAYSIZE(lwip_cyclic_timers); + +#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM + +/** The one and only timeout list */ +static struct sys_timeo *next_timeout; + +static u32_t current_timeout_due_time; + +#if LWIP_TESTMODE +struct sys_timeo** +sys_timeouts_get_next_timeout(void) +{ + return &next_timeout; +} +#endif + +#if LWIP_TCP +/** global variable that shows if the tcp timer is currently scheduled or not */ +static int tcpip_tcp_timer_active; + +/** + * Timer callback function that calls tcp_tmr() and reschedules itself. + * + * @param arg unused argument + */ +static void +tcpip_tcp_timer(void *arg) +{ + LWIP_UNUSED_ARG(arg); + + /* call TCP timer handler */ + tcp_tmr(); + /* timer still needed? */ + if (tcp_active_pcbs || tcp_tw_pcbs) { + /* restart timer */ + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } else { + /* disable timer */ + tcpip_tcp_timer_active = 0; + } +} + +/** + * Called from TCP_REG when registering a new PCB: + * the reason is to have the TCP timer only running when + * there are active (or time-wait) PCBs. + */ +void +tcp_timer_needed(void) +{ + LWIP_ASSERT_CORE_LOCKED(); + + /* timer is off but needed again? */ + if (!tcpip_tcp_timer_active && (tcp_active_pcbs || tcp_tw_pcbs)) { + /* enable and start timer */ + tcpip_tcp_timer_active = 1; + sys_timeout(TCP_TMR_INTERVAL, tcpip_tcp_timer, NULL); + } +} +#endif /* LWIP_TCP */ + +static void +#if LWIP_DEBUG_TIMERNAMES +sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg, const char *handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +sys_timeout_abs(u32_t abs_time, sys_timeout_handler handler, void *arg) +#endif +{ + struct sys_timeo *timeout, *t; + + timeout = (struct sys_timeo *)memp_malloc(MEMP_SYS_TIMEOUT); + if (timeout == NULL) { + LWIP_ASSERT("sys_timeout: timeout != NULL, pool MEMP_SYS_TIMEOUT is empty", timeout != NULL); + return; + } + + timeout->next = NULL; + timeout->h = handler; + timeout->arg = arg; + timeout->time = abs_time; + +#if LWIP_DEBUG_TIMERNAMES + timeout->handler_name = handler_name; + LWIP_DEBUGF(TIMERS_DEBUG, ("sys_timeout: %p abs_time=%"U32_F" handler=%s arg=%p\n", + (void *)timeout, abs_time, handler_name, (void *)arg)); +#endif /* LWIP_DEBUG_TIMERNAMES */ + + if (next_timeout == NULL) { + next_timeout = timeout; + return; + } + if (TIME_LESS_THAN(timeout->time, next_timeout->time)) { + timeout->next = next_timeout; + next_timeout = timeout; + } else { + for (t = next_timeout; t != NULL; t = t->next) { + if ((t->next == NULL) || TIME_LESS_THAN(timeout->time, t->next->time)) { + timeout->next = t->next; + t->next = timeout; + break; + } + } + } +} + +/** + * Timer callback function that calls cyclic->handler() and reschedules itself. + * + * @param arg unused argument + */ +#if !LWIP_TESTMODE +static +#endif +void +lwip_cyclic_timer(void *arg) +{ + u32_t now; + u32_t next_timeout_time; + const struct lwip_cyclic_timer *cyclic = (const struct lwip_cyclic_timer *)arg; + +#if LWIP_DEBUG_TIMERNAMES + LWIP_DEBUGF(TIMERS_DEBUG, ("tcpip: %s()\n", cyclic->handler_name)); +#endif + cyclic->handler(); + + now = sys_now(); + next_timeout_time = (u32_t)(current_timeout_due_time + cyclic->interval_ms); /* overflow handled by TIME_LESS_THAN macro */ + if (TIME_LESS_THAN(next_timeout_time, now)) { + /* timer would immediately expire again -> "overload" -> restart without any correction */ +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs((u32_t)(now + cyclic->interval_ms), lwip_cyclic_timer, arg); +#endif + + } else { + /* correct cyclic interval with handler execution delay and sys_check_timeouts jitter */ +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg, cyclic->handler_name); +#else + sys_timeout_abs(next_timeout_time, lwip_cyclic_timer, arg); +#endif + } +} + +/** Initialize this module */ +void sys_timeouts_init(void) +{ + size_t i; + /* tcp_tmr() at index 0 is started on demand */ + for (i = (LWIP_TCP ? 1 : 0); i < LWIP_ARRAYSIZE(lwip_cyclic_timers); i++) { + /* we have to cast via size_t to get rid of const warning + (this is OK as cyclic_timer() casts back to const* */ + sys_timeout(lwip_cyclic_timers[i].interval_ms, lwip_cyclic_timer, LWIP_CONST_CAST(void *, &lwip_cyclic_timers[i])); + } +} + +/** + * Create a one-shot timer (aka timeout). Timeouts are processed in the + * following cases: + * - while waiting for a message using sys_timeouts_mbox_fetch() + * - by calling sys_check_timeouts() (NO_SYS==1 only) + * + * @param msecs time in milliseconds after that the timer should expire + * @param handler callback function to call when msecs have elapsed + * @param arg argument to pass to the callback function + */ +#if LWIP_DEBUG_TIMERNAMES +void +sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char *handler_name) +#else /* LWIP_DEBUG_TIMERNAMES */ +void +sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg) +#endif /* LWIP_DEBUG_TIMERNAMES */ +{ + u32_t next_timeout_time; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("Timeout time too long, max is LWIP_UINT32_MAX/4 msecs", msecs <= (LWIP_UINT32_MAX / 4)); + + next_timeout_time = (u32_t)(sys_now() + msecs); /* overflow handled by TIME_LESS_THAN macro */ + +#if LWIP_DEBUG_TIMERNAMES + sys_timeout_abs(next_timeout_time, handler, arg, handler_name); +#else + sys_timeout_abs(next_timeout_time, handler, arg); +#endif +} + +/** + * Go through timeout list (for this task only) and remove the first matching + * entry (subsequent entries remain untouched), even though the timeout has not + * triggered yet. + * + * @param handler callback function that would be called by the timeout + * @param arg callback argument that would be passed to handler +*/ +void +sys_untimeout(sys_timeout_handler handler, void *arg) +{ + struct sys_timeo *prev_t, *t; + + LWIP_ASSERT_CORE_LOCKED(); + + if (next_timeout == NULL) { + return; + } + + for (t = next_timeout, prev_t = NULL; t != NULL; prev_t = t, t = t->next) { + if ((t->h == handler) && (t->arg == arg)) { + /* We have a match */ + /* Unlink from previous in list */ + if (prev_t == NULL) { + next_timeout = t->next; + } else { + prev_t->next = t->next; + } + memp_free(MEMP_SYS_TIMEOUT, t); + return; + } + } + return; +} + +/** + * @ingroup lwip_nosys + * Handle timeouts for NO_SYS==1 (i.e. without using + * tcpip_thread/sys_timeouts_mbox_fetch(). Uses sys_now() to call timeout + * handler functions when timeouts expire. + * + * Must be called periodically from your main loop. + */ +void +sys_check_timeouts(void) +{ + u32_t now; + + LWIP_ASSERT_CORE_LOCKED(); + + /* Process only timers expired at the start of the function. */ + now = sys_now(); + + do { + struct sys_timeo *tmptimeout; + sys_timeout_handler handler; + void *arg; + + PBUF_CHECK_FREE_OOSEQ(); + + tmptimeout = next_timeout; + if (tmptimeout == NULL) { + return; + } + + if (TIME_LESS_THAN(now, tmptimeout->time)) { + return; + } + + /* Timeout has expired */ + next_timeout = tmptimeout->next; + handler = tmptimeout->h; + arg = tmptimeout->arg; + current_timeout_due_time = tmptimeout->time; +#if LWIP_DEBUG_TIMERNAMES + if (handler != NULL) { + LWIP_DEBUGF(TIMERS_DEBUG, ("sct calling h=%s t=%"U32_F" arg=%p\n", + tmptimeout->handler_name, sys_now() - tmptimeout->time, arg)); + } +#endif /* LWIP_DEBUG_TIMERNAMES */ + memp_free(MEMP_SYS_TIMEOUT, tmptimeout); + if (handler != NULL) { + handler(arg); + } + LWIP_TCPIP_THREAD_ALIVE(); + + /* Repeat until all expired timers have been called */ + } while (1); +} + +/** Rebase the timeout times to the current time. + * This is necessary if sys_check_timeouts() hasn't been called for a long + * time (e.g. while saving energy) to prevent all timer functions of that + * period being called. + */ +void +sys_restart_timeouts(void) +{ + u32_t now; + u32_t base; + struct sys_timeo *t; + + if (next_timeout == NULL) { + return; + } + + now = sys_now(); + base = next_timeout->time; + + for (t = next_timeout; t != NULL; t = t->next) { + t->time = (t->time - base) + now; + } +} + +/** Return the time left before the next timeout is due. If no timeouts are + * enqueued, returns 0xffffffff + */ +u32_t +sys_timeouts_sleeptime(void) +{ + u32_t now; + + LWIP_ASSERT_CORE_LOCKED(); + + if (next_timeout == NULL) { + return SYS_TIMEOUTS_SLEEPTIME_INFINITE; + } + now = sys_now(); + if (TIME_LESS_THAN(next_timeout->time, now)) { + return 0; + } else { + u32_t ret = (u32_t)(next_timeout->time - now); + LWIP_ASSERT("invalid sleeptime", ret <= LWIP_MAX_TIMEOUT); + return ret; + } +} + +#else /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */ +/* Satisfy the TCP code which calls this function */ +void +tcp_timer_needed(void) +{ +} +#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */ diff --git a/Middlewares/Third_Party/LwIP/src/core/udp.c b/Middlewares/Third_Party/LwIP/src/core/udp.c new file mode 100644 index 0000000..9d2cb4a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/core/udp.c @@ -0,0 +1,1314 @@ +/** + * @file + * User Datagram Protocol module\n + * The code for the User Datagram Protocol UDP & UDPLite (RFC 3828).\n + * See also @ref udp_raw + * + * @defgroup udp_raw UDP + * @ingroup callbackstyle_api + * User Datagram Protocol module\n + * @see @ref api + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* @todo Check the use of '(struct udp_pcb).chksum_len_rx'! + */ + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/udp.h" +#include "lwip/def.h" +#include "lwip/memp.h" +#include "lwip/inet_chksum.h" +#include "lwip/ip_addr.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/netif.h" +#include "lwip/icmp.h" +#include "lwip/icmp6.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/dhcp.h" + +#include + +#ifndef UDP_LOCAL_PORT_RANGE_START +/* From http://www.iana.org/assignments/port-numbers: + "The Dynamic and/or Private Ports are those from 49152 through 65535" */ +#define UDP_LOCAL_PORT_RANGE_START 0xc000 +#define UDP_LOCAL_PORT_RANGE_END 0xffff +#define UDP_ENSURE_LOCAL_PORT_RANGE(port) ((u16_t)(((port) & (u16_t)~UDP_LOCAL_PORT_RANGE_START) + UDP_LOCAL_PORT_RANGE_START)) +#endif + +/* last local UDP port */ +static u16_t udp_port = UDP_LOCAL_PORT_RANGE_START; + +/* The list of UDP PCBs */ +/* exported in udp.h (was static) */ +struct udp_pcb *udp_pcbs; + +/** + * Initialize this module. + */ +void +udp_init(void) +{ +#ifdef LWIP_RAND + udp_port = UDP_ENSURE_LOCAL_PORT_RANGE(LWIP_RAND()); +#endif /* LWIP_RAND */ +} + +/** + * Allocate a new local UDP port. + * + * @return a new (free) local UDP port number + */ +static u16_t +udp_new_port(void) +{ + u16_t n = 0; + struct udp_pcb *pcb; + +again: + if (udp_port++ == UDP_LOCAL_PORT_RANGE_END) { + udp_port = UDP_LOCAL_PORT_RANGE_START; + } + /* Check all PCBs. */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + if (pcb->local_port == udp_port) { + if (++n > (UDP_LOCAL_PORT_RANGE_END - UDP_LOCAL_PORT_RANGE_START)) { + return 0; + } + goto again; + } + } + return udp_port; +} + +/** Common code to see if the current input packet matches the pcb + * (current input packet is accessed via ip(4/6)_current_* macros) + * + * @param pcb pcb to check + * @param inp network interface on which the datagram was received (only used for IPv4) + * @param broadcast 1 if his is an IPv4 broadcast (global or subnet-only), 0 otherwise (only used for IPv4) + * @return 1 on match, 0 otherwise + */ +static u8_t +udp_input_local_match(struct udp_pcb *pcb, struct netif *inp, u8_t broadcast) +{ + LWIP_UNUSED_ARG(inp); /* in IPv6 only case */ + LWIP_UNUSED_ARG(broadcast); /* in IPv6 only case */ + + LWIP_ASSERT("udp_input_local_match: invalid pcb", pcb != NULL); + LWIP_ASSERT("udp_input_local_match: invalid netif", inp != NULL); + + /* check if PCB is bound to specific netif */ + if ((pcb->netif_idx != NETIF_NO_INDEX) && + (pcb->netif_idx != netif_get_index(ip_data.current_input_netif))) { + return 0; + } + + /* Dual-stack: PCBs listening to any IP type also listen to any IP address */ + if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { +#if LWIP_IPV4 && IP_SOF_BROADCAST_RECV + if ((broadcast != 0) && !ip_get_option(pcb, SOF_BROADCAST)) { + return 0; + } +#endif /* LWIP_IPV4 && IP_SOF_BROADCAST_RECV */ + return 1; + } + + /* Only need to check PCB if incoming IP version matches PCB IP version */ + if (IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ip_current_dest_addr())) { +#if LWIP_IPV4 + /* Special case: IPv4 broadcast: all or broadcasts in my subnet + * Note: broadcast variable can only be 1 if it is an IPv4 broadcast */ + if (broadcast != 0) { +#if IP_SOF_BROADCAST_RECV + if (ip_get_option(pcb, SOF_BROADCAST)) +#endif /* IP_SOF_BROADCAST_RECV */ + { + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + ((ip4_current_dest_addr()->addr == IPADDR_BROADCAST)) || + ip4_addr_netcmp(ip_2_ip4(&pcb->local_ip), ip4_current_dest_addr(), netif_ip4_netmask(inp))) { + return 1; + } + } + } else +#endif /* LWIP_IPV4 */ + /* Handle IPv4 and IPv6: all or exact match */ + if (ip_addr_isany(&pcb->local_ip) || ip_addr_cmp(&pcb->local_ip, ip_current_dest_addr())) { + return 1; + } + } + + return 0; +} + +/** + * Process an incoming UDP datagram. + * + * Given an incoming UDP datagram (as a chain of pbufs) this function + * finds a corresponding UDP PCB and hands over the pbuf to the pcbs + * recv function. If no pcb is found or the datagram is incorrect, the + * pbuf is freed. + * + * @param p pbuf to be demultiplexed to a UDP PCB (p->payload pointing to the UDP header) + * @param inp network interface on which the datagram was received. + * + */ +void +udp_input(struct pbuf *p, struct netif *inp) +{ + struct udp_hdr *udphdr; + struct udp_pcb *pcb, *prev; + struct udp_pcb *uncon_pcb; + u16_t src, dest; + u8_t broadcast; + u8_t for_us = 0; + + LWIP_UNUSED_ARG(inp); + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ASSERT("udp_input: invalid pbuf", p != NULL); + LWIP_ASSERT("udp_input: invalid netif", inp != NULL); + + PERF_START; + + UDP_STATS_INC(udp.recv); + + /* Check minimum length (UDP header) */ + if (p->len < UDP_HLEN) { + /* drop short packets */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_input: short UDP datagram (%"U16_F" bytes) discarded\n", p->tot_len)); + UDP_STATS_INC(udp.lenerr); + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + goto end; + } + + udphdr = (struct udp_hdr *)p->payload; + + /* is broadcast packet ? */ + broadcast = ip_addr_isbroadcast(ip_current_dest_addr(), ip_current_netif()); + + LWIP_DEBUGF(UDP_DEBUG, ("udp_input: received datagram of length %"U16_F"\n", p->tot_len)); + + /* convert src and dest ports to host byte order */ + src = lwip_ntohs(udphdr->src); + dest = lwip_ntohs(udphdr->dest); + + udp_debug_print(udphdr); + + /* print the UDP source and destination */ + LWIP_DEBUGF(UDP_DEBUG, ("udp (")); + ip_addr_debug_print_val(UDP_DEBUG, *ip_current_dest_addr()); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", lwip_ntohs(udphdr->dest))); + ip_addr_debug_print_val(UDP_DEBUG, *ip_current_src_addr()); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", lwip_ntohs(udphdr->src))); + + pcb = NULL; + prev = NULL; + uncon_pcb = NULL; + /* Iterate through the UDP pcb list for a matching pcb. + * 'Perfect match' pcbs (connected to the remote port & ip address) are + * preferred. If no perfect match is found, the first unconnected pcb that + * matches the local port and ip address gets the datagram. */ + for (pcb = udp_pcbs; pcb != NULL; pcb = pcb->next) { + /* print the PCB local and remote address */ + LWIP_DEBUGF(UDP_DEBUG, ("pcb (")); + ip_addr_debug_print_val(UDP_DEBUG, pcb->local_ip); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F") <-- (", pcb->local_port)); + ip_addr_debug_print_val(UDP_DEBUG, pcb->remote_ip); + LWIP_DEBUGF(UDP_DEBUG, (", %"U16_F")\n", pcb->remote_port)); + + /* compare PCB local addr+port to UDP destination addr+port */ + if ((pcb->local_port == dest) && + (udp_input_local_match(pcb, inp, broadcast) != 0)) { + if ((pcb->flags & UDP_FLAGS_CONNECTED) == 0) { + if (uncon_pcb == NULL) { + /* the first unconnected matching PCB */ + uncon_pcb = pcb; +#if LWIP_IPV4 + } else if (broadcast && ip4_current_dest_addr()->addr == IPADDR_BROADCAST) { + /* global broadcast address (only valid for IPv4; match was checked before) */ + if (!IP_IS_V4_VAL(uncon_pcb->local_ip) || !ip4_addr_cmp(ip_2_ip4(&uncon_pcb->local_ip), netif_ip4_addr(inp))) { + /* uncon_pcb does not match the input netif, check this pcb */ + if (IP_IS_V4_VAL(pcb->local_ip) && ip4_addr_cmp(ip_2_ip4(&pcb->local_ip), netif_ip4_addr(inp))) { + /* better match */ + uncon_pcb = pcb; + } + } +#endif /* LWIP_IPV4 */ + } +#if SO_REUSE + else if (!ip_addr_isany(&pcb->local_ip)) { + /* prefer specific IPs over catch-all */ + uncon_pcb = pcb; + } +#endif /* SO_REUSE */ + } + + /* compare PCB remote addr+port to UDP source addr+port */ + if ((pcb->remote_port == src) && + (ip_addr_isany_val(pcb->remote_ip) || + ip_addr_cmp(&pcb->remote_ip, ip_current_src_addr()))) { + /* the first fully matching PCB */ + if (prev != NULL) { + /* move the pcb to the front of udp_pcbs so that is + found faster next time */ + prev->next = pcb->next; + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } else { + UDP_STATS_INC(udp.cachehit); + } + break; + } + } + + prev = pcb; + } + /* no fully matching pcb found? then look for an unconnected pcb */ + if (pcb == NULL) { + pcb = uncon_pcb; + } + + /* Check checksum if this is a match or if it was directed at us. */ + if (pcb != NULL) { + for_us = 1; + } else { +#if LWIP_IPV6 + if (ip_current_is_v6()) { + for_us = netif_get_ip6_addr_match(inp, ip6_current_dest_addr()) >= 0; + } +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + if (!ip_current_is_v6()) { + for_us = ip4_addr_cmp(netif_ip4_addr(inp), ip4_current_dest_addr()); + } +#endif /* LWIP_IPV4 */ + } + + if (for_us) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: calculating checksum\n")); +#if CHECKSUM_CHECK_UDP + IF__NETIF_CHECKSUM_ENABLED(inp, NETIF_CHECKSUM_CHECK_UDP) { +#if LWIP_UDPLITE + if (ip_current_header_proto() == IP_PROTO_UDPLITE) { + /* Do the UDP Lite checksum */ + u16_t chklen = lwip_ntohs(udphdr->len); + if (chklen < sizeof(struct udp_hdr)) { + if (chklen == 0) { + /* For UDP-Lite, checksum length of 0 means checksum + over the complete packet (See RFC 3828 chap. 3.1) */ + chklen = p->tot_len; + } else { + /* At least the UDP-Lite header must be covered by the + checksum! (Again, see RFC 3828 chap. 3.1) */ + goto chkerr; + } + } + if (ip_chksum_pseudo_partial(p, IP_PROTO_UDPLITE, + p->tot_len, chklen, + ip_current_src_addr(), ip_current_dest_addr()) != 0) { + goto chkerr; + } + } else +#endif /* LWIP_UDPLITE */ + { + if (udphdr->chksum != 0) { + if (ip_chksum_pseudo(p, IP_PROTO_UDP, p->tot_len, + ip_current_src_addr(), + ip_current_dest_addr()) != 0) { + goto chkerr; + } + } + } + } +#endif /* CHECKSUM_CHECK_UDP */ + if (pbuf_remove_header(p, UDP_HLEN)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + goto end; + } + + if (pcb != NULL) { + MIB2_STATS_INC(mib2.udpindatagrams); +#if SO_REUSE && SO_REUSE_RXTOALL + if (ip_get_option(pcb, SOF_REUSEADDR) && + (broadcast || ip_addr_ismulticast(ip_current_dest_addr()))) { + /* pass broadcast- or multicast packets to all multicast pcbs + if SOF_REUSEADDR is set on the first match */ + struct udp_pcb *mpcb; + for (mpcb = udp_pcbs; mpcb != NULL; mpcb = mpcb->next) { + if (mpcb != pcb) { + /* compare PCB local addr+port to UDP destination addr+port */ + if ((mpcb->local_port == dest) && + (udp_input_local_match(mpcb, inp, broadcast) != 0)) { + /* pass a copy of the packet to all local matches */ + if (mpcb->recv != NULL) { + struct pbuf *q; + q = pbuf_clone(PBUF_RAW, PBUF_POOL, p); + if (q != NULL) { + mpcb->recv(mpcb->recv_arg, mpcb, q, ip_current_src_addr(), src); + } + } + } + } + } + } +#endif /* SO_REUSE && SO_REUSE_RXTOALL */ + /* callback */ + if (pcb->recv != NULL) { + /* now the recv function is responsible for freeing p */ + pcb->recv(pcb->recv_arg, pcb, p, ip_current_src_addr(), src); + } else { + /* no recv function registered? then we have to free the pbuf! */ + pbuf_free(p); + goto end; + } + } else { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_input: not for us.\n")); + +#if LWIP_ICMP || LWIP_ICMP6 + /* No match was found, send ICMP destination port unreachable unless + destination address was broadcast/multicast. */ + if (!broadcast && !ip_addr_ismulticast(ip_current_dest_addr())) { + /* move payload pointer back to ip header */ + pbuf_header_force(p, (s16_t)(ip_current_header_tot_len() + UDP_HLEN)); + icmp_port_unreach(ip_current_is_v6(), p); + } +#endif /* LWIP_ICMP || LWIP_ICMP6 */ + UDP_STATS_INC(udp.proterr); + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpnoports); + pbuf_free(p); + } + } else { + pbuf_free(p); + } +end: + PERF_STOP("udp_input"); + return; +#if CHECKSUM_CHECK_UDP +chkerr: + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_input: UDP (or UDP Lite) datagram discarded due to failing checksum\n")); + UDP_STATS_INC(udp.chkerr); + UDP_STATS_INC(udp.drop); + MIB2_STATS_INC(mib2.udpinerrors); + pbuf_free(p); + PERF_STOP("udp_input"); +#endif /* CHECKSUM_CHECK_UDP */ +} + +/** + * @ingroup udp_raw + * Sends the pbuf p using UDP. The pbuf is not deallocated. + * + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * + * The datagram will be sent to the current remote_ip & remote_port + * stored in pcb. If the pcb is not bound to a port, it will + * automatically be bound to a random port. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occurred. + * - ERR_MEM. Out of memory. + * - ERR_RTE. Could not find route to destination address. + * - ERR_VAL. No PCB or PCB is dual-stack + * - More errors could be returned by lower protocol layers. + * + * @see udp_disconnect() udp_sendto() + */ +err_t +udp_send(struct udp_pcb *pcb, struct pbuf *p) +{ + LWIP_ERROR("udp_send: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_ERROR("udp_send: invalid pbuf", p != NULL, return ERR_ARG); + + if (IP_IS_ANY_TYPE_VAL(pcb->remote_ip)) { + return ERR_VAL; + } + + /* send to the packet using remote ip and port stored in the pcb */ + return udp_sendto(pcb, p, &pcb->remote_ip, pcb->remote_port); +} + +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP +/** @ingroup udp_raw + * Same as udp_send() but with checksum + */ +err_t +udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p, + u8_t have_chksum, u16_t chksum) +{ + LWIP_ERROR("udp_send_chksum: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_ERROR("udp_send_chksum: invalid pbuf", p != NULL, return ERR_ARG); + + if (IP_IS_ANY_TYPE_VAL(pcb->remote_ip)) { + return ERR_VAL; + } + + /* send to the packet using remote ip and port stored in the pcb */ + return udp_sendto_chksum(pcb, p, &pcb->remote_ip, pcb->remote_port, + have_chksum, chksum); +} +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + +/** + * @ingroup udp_raw + * Send data to a specified address using UDP. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * + * dst_ip & dst_port are expected to be in the same byte order as in the pcb. + * + * If the PCB already has a remote address association, it will + * be restored after the data is sent. + * + * @return lwIP error code (@see udp_send for possible error codes) + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port) +{ +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP + return udp_sendto_chksum(pcb, p, dst_ip, dst_port, 0, 0); +} + +/** @ingroup udp_raw + * Same as udp_sendto(), but with checksum */ +err_t +udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, + u16_t dst_port, u8_t have_chksum, u16_t chksum) +{ +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + struct netif *netif; + + LWIP_ERROR("udp_sendto: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto: invalid pbuf", p != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto: invalid dst_ip", dst_ip != NULL, return ERR_ARG); + + if (!IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) { + return ERR_VAL; + } + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send\n")); + + if (pcb->netif_idx != NETIF_NO_INDEX) { + netif = netif_get_by_index(pcb->netif_idx); + } else { +#if LWIP_MULTICAST_TX_OPTIONS + netif = NULL; + if (ip_addr_ismulticast(dst_ip)) { + /* For IPv6, the interface to use for packets with a multicast destination + * is specified using an interface index. The same approach may be used for + * IPv4 as well, in which case it overrides the IPv4 multicast override + * address below. Here we have to look up the netif by going through the + * list, but by doing so we skip a route lookup. If the interface index has + * gone stale, we fall through and do the regular route lookup after all. */ + if (pcb->mcast_ifindex != NETIF_NO_INDEX) { + netif = netif_get_by_index(pcb->mcast_ifindex); + } +#if LWIP_IPV4 + else +#if LWIP_IPV6 + if (IP_IS_V4(dst_ip)) +#endif /* LWIP_IPV6 */ + { + /* IPv4 does not use source-based routing by default, so we use an + administratively selected interface for multicast by default. + However, this can be overridden by setting an interface address + in pcb->mcast_ip4 that is used for routing. If this routing lookup + fails, we try regular routing as though no override was set. */ + if (!ip4_addr_isany_val(pcb->mcast_ip4) && + !ip4_addr_cmp(&pcb->mcast_ip4, IP4_ADDR_BROADCAST)) { + netif = ip4_route_src(ip_2_ip4(&pcb->local_ip), &pcb->mcast_ip4); + } + } +#endif /* LWIP_IPV4 */ + } + + if (netif == NULL) +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + { + /* find the outgoing network interface for this packet */ + netif = ip_route(&pcb->local_ip, dst_ip); + } + } + + /* no outgoing network interface could be found? */ + if (netif == NULL) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: No route to ")); + ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, dst_ip); + LWIP_DEBUGF(UDP_DEBUG, ("\n")); + UDP_STATS_INC(udp.rterr); + return ERR_RTE; + } +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP + return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum); +#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + return udp_sendto_if(pcb, p, dst_ip, dst_port, netif); +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ +} + +/** + * @ingroup udp_raw + * Send data to a specified address using UDP. + * The netif used for sending can be specified. + * + * This function exists mainly for DHCP, to be able to send UDP packets + * on a netif that is still down. + * + * @param pcb UDP PCB used to send the data. + * @param p chain of pbuf's to be sent. + * @param dst_ip Destination IP address. + * @param dst_port Destination UDP port. + * @param netif the netif used for sending. + * + * dst_ip & dst_port are expected to be in the same byte order as in the pcb. + * + * @return lwIP error code (@see udp_send for possible error codes) + * + * @see udp_disconnect() udp_send() + */ +err_t +udp_sendto_if(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif) +{ +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP + return udp_sendto_if_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0); +} + +/** Same as udp_sendto_if(), but with checksum */ +err_t +udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, + u16_t dst_port, struct netif *netif, u8_t have_chksum, + u16_t chksum) +{ +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + const ip_addr_t *src_ip; + + LWIP_ERROR("udp_sendto_if: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto_if: invalid pbuf", p != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto_if: invalid dst_ip", dst_ip != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto_if: invalid netif", netif != NULL, return ERR_ARG); + + if (!IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) { + return ERR_VAL; + } + + /* PCB local address is IP_ANY_ADDR or multicast? */ +#if LWIP_IPV6 + if (IP_IS_V6(dst_ip)) { + if (ip6_addr_isany(ip_2_ip6(&pcb->local_ip)) || + ip6_addr_ismulticast(ip_2_ip6(&pcb->local_ip))) { + src_ip = ip6_select_source_address(netif, ip_2_ip6(dst_ip)); + if (src_ip == NULL) { + /* No suitable source address was found. */ + return ERR_RTE; + } + } else { + /* use UDP PCB local IPv6 address as source address, if still valid. */ + if (netif_get_ip6_addr_match(netif, ip_2_ip6(&pcb->local_ip)) < 0) { + /* Address isn't valid anymore. */ + return ERR_RTE; + } + src_ip = &pcb->local_ip; + } + } +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 && LWIP_IPV6 + else +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#if LWIP_IPV4 + if (ip4_addr_isany(ip_2_ip4(&pcb->local_ip)) || + ip4_addr_ismulticast(ip_2_ip4(&pcb->local_ip))) { + /* if the local_ip is any or multicast + * use the outgoing network interface IP address as source address */ + src_ip = netif_ip_addr4(netif); + } else { + /* check if UDP PCB local IP address is correct + * this could be an old address if netif->ip_addr has changed */ + if (!ip4_addr_cmp(ip_2_ip4(&(pcb->local_ip)), netif_ip4_addr(netif))) { + /* local_ip doesn't match, drop the packet */ + return ERR_RTE; + } + /* use UDP PCB local IP address as source address */ + src_ip = &pcb->local_ip; + } +#endif /* LWIP_IPV4 */ +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP + return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, have_chksum, chksum, src_ip); +#else /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + return udp_sendto_if_src(pcb, p, dst_ip, dst_port, netif, src_ip); +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ +} + +/** @ingroup udp_raw + * Same as @ref udp_sendto_if, but with source address */ +err_t +udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, const ip_addr_t *src_ip) +{ +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP + return udp_sendto_if_src_chksum(pcb, p, dst_ip, dst_port, netif, 0, 0, src_ip); +} + +/** Same as udp_sendto_if_src(), but with checksum */ +err_t +udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, + u16_t dst_port, struct netif *netif, u8_t have_chksum, + u16_t chksum, const ip_addr_t *src_ip) +{ +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + struct udp_hdr *udphdr; + err_t err; + struct pbuf *q; /* q will be sent down the stack */ + u8_t ip_proto; + u8_t ttl; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_sendto_if_src: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto_if_src: invalid pbuf", p != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto_if_src: invalid dst_ip", dst_ip != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto_if_src: invalid src_ip", src_ip != NULL, return ERR_ARG); + LWIP_ERROR("udp_sendto_if_src: invalid netif", netif != NULL, return ERR_ARG); + + if (!IP_ADDR_PCB_VERSION_MATCH(pcb, src_ip) || + !IP_ADDR_PCB_VERSION_MATCH(pcb, dst_ip)) { + return ERR_VAL; + } + +#if LWIP_IPV4 && IP_SOF_BROADCAST + /* broadcast filter? */ + if (!ip_get_option(pcb, SOF_BROADCAST) && +#if LWIP_IPV6 + IP_IS_V4(dst_ip) && +#endif /* LWIP_IPV6 */ + ip_addr_isbroadcast(dst_ip, netif)) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_LEVEL_SERIOUS, + ("udp_sendto_if: SOF_BROADCAST not enabled on pcb %p\n", (void *)pcb)); + return ERR_VAL; + } +#endif /* LWIP_IPV4 && IP_SOF_BROADCAST */ + + /* if the PCB is not yet bound to a port, bind it here */ + if (pcb->local_port == 0) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_send: not yet bound to a port, binding now\n")); + err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: forced port bind failed\n")); + return err; + } + } + + /* packet too large to add a UDP header without causing an overflow? */ + if ((u16_t)(p->tot_len + UDP_HLEN) < p->tot_len) { + return ERR_MEM; + } + /* not enough space to add an UDP header to first pbuf in given p chain? */ + if (pbuf_add_header(p, UDP_HLEN)) { + /* allocate header in a separate new pbuf */ + q = pbuf_alloc(PBUF_IP, UDP_HLEN, PBUF_RAM); + /* new header pbuf could not be allocated? */ + if (q == NULL) { + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, ("udp_send: could not allocate header\n")); + return ERR_MEM; + } + if (p->tot_len != 0) { + /* chain header q in front of given pbuf p (only if p contains data) */ + pbuf_chain(q, p); + } + /* first pbuf q points to header pbuf */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_send: added header pbuf %p before given pbuf %p\n", (void *)q, (void *)p)); + } else { + /* adding space for header within p succeeded */ + /* first pbuf q equals given pbuf */ + q = p; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: added header in given pbuf %p\n", (void *)p)); + } + LWIP_ASSERT("check that first pbuf can hold struct udp_hdr", + (q->len >= sizeof(struct udp_hdr))); + /* q now represents the packet to be sent */ + udphdr = (struct udp_hdr *)q->payload; + udphdr->src = lwip_htons(pcb->local_port); + udphdr->dest = lwip_htons(dst_port); + /* in UDP, 0 checksum means 'no checksum' */ + udphdr->chksum = 0x0000; + + /* Multicast Loop? */ +#if LWIP_MULTICAST_TX_OPTIONS + if (((pcb->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) && ip_addr_ismulticast(dst_ip)) { + q->flags |= PBUF_FLAG_MCASTLOOP; + } +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: sending datagram of length %"U16_F"\n", q->tot_len)); + +#if LWIP_UDPLITE + /* UDP Lite protocol? */ + if (pcb->flags & UDP_FLAGS_UDPLITE) { + u16_t chklen, chklen_hdr; + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE packet length %"U16_F"\n", q->tot_len)); + /* set UDP message length in UDP header */ + chklen_hdr = chklen = pcb->chksum_len_tx; + if ((chklen < sizeof(struct udp_hdr)) || (chklen > q->tot_len)) { + if (chklen != 0) { + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP LITE pcb->chksum_len is illegal: %"U16_F"\n", chklen)); + } + /* For UDP-Lite, checksum length of 0 means checksum + over the complete packet. (See RFC 3828 chap. 3.1) + At least the UDP-Lite header must be covered by the + checksum, therefore, if chksum_len has an illegal + value, we generate the checksum over the complete + packet to be safe. */ + chklen_hdr = 0; + chklen = q->tot_len; + } + udphdr->len = lwip_htons(chklen_hdr); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_UDP) { +#if LWIP_CHECKSUM_ON_COPY + if (have_chksum) { + chklen = UDP_HLEN; + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + udphdr->chksum = ip_chksum_pseudo_partial(q, IP_PROTO_UDPLITE, + q->tot_len, chklen, src_ip, dst_ip); +#if LWIP_CHECKSUM_ON_COPY + if (have_chksum) { + u32_t acc; + acc = udphdr->chksum + (u16_t)~(chksum); + udphdr->chksum = FOLD_U32T(acc); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udphdr->chksum == 0x0000) { + udphdr->chksum = 0xffff; + } + } +#endif /* CHECKSUM_GEN_UDP */ + + ip_proto = IP_PROTO_UDPLITE; + } else +#endif /* LWIP_UDPLITE */ + { /* UDP */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP packet length %"U16_F"\n", q->tot_len)); + udphdr->len = lwip_htons(q->tot_len); + /* calculate checksum */ +#if CHECKSUM_GEN_UDP + IF__NETIF_CHECKSUM_ENABLED(netif, NETIF_CHECKSUM_GEN_UDP) { + /* Checksum is mandatory over IPv6. */ + if (IP_IS_V6(dst_ip) || (pcb->flags & UDP_FLAGS_NOCHKSUM) == 0) { + u16_t udpchksum; +#if LWIP_CHECKSUM_ON_COPY + if (have_chksum) { + u32_t acc; + udpchksum = ip_chksum_pseudo_partial(q, IP_PROTO_UDP, + q->tot_len, UDP_HLEN, src_ip, dst_ip); + acc = udpchksum + (u16_t)~(chksum); + udpchksum = FOLD_U32T(acc); + } else +#endif /* LWIP_CHECKSUM_ON_COPY */ + { + udpchksum = ip_chksum_pseudo(q, IP_PROTO_UDP, q->tot_len, + src_ip, dst_ip); + } + + /* chksum zero must become 0xffff, as zero means 'no checksum' */ + if (udpchksum == 0x0000) { + udpchksum = 0xffff; + } + udphdr->chksum = udpchksum; + } + } +#endif /* CHECKSUM_GEN_UDP */ + ip_proto = IP_PROTO_UDP; + } + + /* Determine TTL to use */ +#if LWIP_MULTICAST_TX_OPTIONS + ttl = (ip_addr_ismulticast(dst_ip) ? udp_get_multicast_ttl(pcb) : pcb->ttl); +#else /* LWIP_MULTICAST_TX_OPTIONS */ + ttl = pcb->ttl; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: UDP checksum 0x%04"X16_F"\n", udphdr->chksum)); + LWIP_DEBUGF(UDP_DEBUG, ("udp_send: ip_output_if (,,,,0x%02"X16_F",)\n", (u16_t)ip_proto)); + /* output to IP */ + NETIF_SET_HINTS(netif, &(pcb->netif_hints)); + err = ip_output_if_src(q, src_ip, dst_ip, ttl, pcb->tos, ip_proto, netif); + NETIF_RESET_HINTS(netif); + + /* @todo: must this be increased even if error occurred? */ + MIB2_STATS_INC(mib2.udpoutdatagrams); + + /* did we chain a separate header pbuf earlier? */ + if (q != p) { + /* free the header pbuf */ + pbuf_free(q); + q = NULL; + /* p is still referenced by the caller, and will live on */ + } + + UDP_STATS_INC(udp.xmit); + return err; +} + +/** + * @ingroup udp_raw + * Bind an UDP PCB. + * + * @param pcb UDP PCB to be bound with a local address ipaddr and port. + * @param ipaddr local IP address to bind with. Use IP_ANY_TYPE to + * bind to all local interfaces. + * @param port local UDP port to bind with. Use 0 to automatically bind + * to a random port between UDP_LOCAL_PORT_RANGE_START and + * UDP_LOCAL_PORT_RANGE_END. + * + * ipaddr & port are expected to be in the same byte order as in the pcb. + * + * @return lwIP error code. + * - ERR_OK. Successful. No error occurred. + * - ERR_USE. The specified ipaddr and port are already bound to by + * another UDP PCB. + * + * @see udp_disconnect() + */ +err_t +udp_bind(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + u8_t rebind; +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + ip_addr_t zoned_ipaddr; +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + LWIP_ASSERT_CORE_LOCKED(); + +#if LWIP_IPV4 + /* Don't propagate NULL pointer (IPv4 ANY) to subsequent functions */ + if (ipaddr == NULL) { + ipaddr = IP4_ADDR_ANY; + } +#else /* LWIP_IPV4 */ + LWIP_ERROR("udp_bind: invalid ipaddr", ipaddr != NULL, return ERR_ARG); +#endif /* LWIP_IPV4 */ + + LWIP_ERROR("udp_bind: invalid pcb", pcb != NULL, return ERR_ARG); + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, ("udp_bind(ipaddr = ")); + ip_addr_debug_print(UDP_DEBUG | LWIP_DBG_TRACE, ipaddr); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE, (", port = %"U16_F")\n", port)); + + rebind = 0; + /* Check for double bind and rebind of the same pcb */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + /* is this UDP PCB already on active list? */ + if (pcb == ipcb) { + rebind = 1; + break; + } + } + +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + /* If the given IP address should have a zone but doesn't, assign one now. + * This is legacy support: scope-aware callers should always provide properly + * zoned source addresses. Do the zone selection before the address-in-use + * check below; as such we have to make a temporary copy of the address. */ + if (IP_IS_V6(ipaddr) && ip6_addr_lacks_zone(ip_2_ip6(ipaddr), IP6_UNKNOWN)) { + ip_addr_copy(zoned_ipaddr, *ipaddr); + ip6_addr_select_zone(ip_2_ip6(&zoned_ipaddr), ip_2_ip6(&zoned_ipaddr)); + ipaddr = &zoned_ipaddr; + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + /* no port specified? */ + if (port == 0) { + port = udp_new_port(); + if (port == 0) { + /* no more ports available in local range */ + LWIP_DEBUGF(UDP_DEBUG, ("udp_bind: out of free UDP ports\n")); + return ERR_USE; + } + } else { + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + if (pcb != ipcb) { + /* By default, we don't allow to bind to a port that any other udp + PCB is already bound to, unless *all* PCBs with that port have tha + REUSEADDR flag set. */ +#if SO_REUSE + if (!ip_get_option(pcb, SOF_REUSEADDR) || + !ip_get_option(ipcb, SOF_REUSEADDR)) +#endif /* SO_REUSE */ + { + /* port matches that of PCB in list and REUSEADDR not set -> reject */ + if ((ipcb->local_port == port) && + /* IP address matches or any IP used? */ + (ip_addr_cmp(&ipcb->local_ip, ipaddr) || ip_addr_isany(ipaddr) || + ip_addr_isany(&ipcb->local_ip))) { + /* other PCB already binds to this local IP and port */ + LWIP_DEBUGF(UDP_DEBUG, + ("udp_bind: local port %"U16_F" already bound by another pcb\n", port)); + return ERR_USE; + } + } + } + } + } + + ip_addr_set_ipaddr(&pcb->local_ip, ipaddr); + + pcb->local_port = port; + mib2_udp_bind(pcb); + /* pcb not active yet? */ + if (rebind == 0) { + /* place the PCB on the active list if not already there */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + } + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_bind: bound to ")); + ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, pcb->local_ip); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->local_port)); + return ERR_OK; +} + +/** + * @ingroup udp_raw + * Bind an UDP PCB to a specific netif. + * After calling this function, all packets received via this PCB + * are guaranteed to have come in via the specified netif, and all + * outgoing packets will go out via the specified netif. + * + * @param pcb UDP PCB to be bound. + * @param netif netif to bind udp pcb to. Can be NULL. + * + * @see udp_disconnect() + */ +void +udp_bind_netif(struct udp_pcb *pcb, const struct netif *netif) +{ + LWIP_ASSERT_CORE_LOCKED(); + + if (netif != NULL) { + pcb->netif_idx = netif_get_index(netif); + } else { + pcb->netif_idx = NETIF_NO_INDEX; + } +} + +/** + * @ingroup udp_raw + * Sets the remote end of the pcb. This function does not generate any + * network traffic, but only sets the remote address of the pcb. + * + * @param pcb UDP PCB to be connected with remote address ipaddr and port. + * @param ipaddr remote IP address to connect with. + * @param port remote UDP port to connect with. + * + * @return lwIP error code + * + * ipaddr & port are expected to be in the same byte order as in the pcb. + * + * The udp pcb is bound to a random local port if not already bound. + * + * @see udp_disconnect() + */ +err_t +udp_connect(struct udp_pcb *pcb, const ip_addr_t *ipaddr, u16_t port) +{ + struct udp_pcb *ipcb; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_connect: invalid pcb", pcb != NULL, return ERR_ARG); + LWIP_ERROR("udp_connect: invalid ipaddr", ipaddr != NULL, return ERR_ARG); + + if (pcb->local_port == 0) { + err_t err = udp_bind(pcb, &pcb->local_ip, pcb->local_port); + if (err != ERR_OK) { + return err; + } + } + + ip_addr_set_ipaddr(&pcb->remote_ip, ipaddr); +#if LWIP_IPV6 && LWIP_IPV6_SCOPES + /* If the given IP address should have a zone but doesn't, assign one now, + * using the bound address to make a more informed decision when possible. */ + if (IP_IS_V6(&pcb->remote_ip) && + ip6_addr_lacks_zone(ip_2_ip6(&pcb->remote_ip), IP6_UNKNOWN)) { + ip6_addr_select_zone(ip_2_ip6(&pcb->remote_ip), ip_2_ip6(&pcb->local_ip)); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_SCOPES */ + + pcb->remote_port = port; + pcb->flags |= UDP_FLAGS_CONNECTED; + + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, ("udp_connect: connected to ")); + ip_addr_debug_print_val(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, + pcb->remote_ip); + LWIP_DEBUGF(UDP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_STATE, (", port %"U16_F")\n", pcb->remote_port)); + + /* Insert UDP PCB into the list of active UDP PCBs. */ + for (ipcb = udp_pcbs; ipcb != NULL; ipcb = ipcb->next) { + if (pcb == ipcb) { + /* already on the list, just return */ + return ERR_OK; + } + } + /* PCB not yet on the list, add PCB now */ + pcb->next = udp_pcbs; + udp_pcbs = pcb; + return ERR_OK; +} + +/** + * @ingroup udp_raw + * Remove the remote end of the pcb. This function does not generate + * any network traffic, but only removes the remote address of the pcb. + * + * @param pcb the udp pcb to disconnect. + */ +void +udp_disconnect(struct udp_pcb *pcb) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_disconnect: invalid pcb", pcb != NULL, return); + + /* reset remote address association */ +#if LWIP_IPV4 && LWIP_IPV6 + if (IP_IS_ANY_TYPE_VAL(pcb->local_ip)) { + ip_addr_copy(pcb->remote_ip, *IP_ANY_TYPE); + } else { +#endif + ip_addr_set_any(IP_IS_V6_VAL(pcb->remote_ip), &pcb->remote_ip); +#if LWIP_IPV4 && LWIP_IPV6 + } +#endif + pcb->remote_port = 0; + pcb->netif_idx = NETIF_NO_INDEX; + /* mark PCB as unconnected */ + udp_clear_flags(pcb, UDP_FLAGS_CONNECTED); +} + +/** + * @ingroup udp_raw + * Set a receive callback for a UDP PCB. + * This callback will be called when receiving a datagram for the pcb. + * + * @param pcb the pcb for which to set the recv callback + * @param recv function pointer of the callback function + * @param recv_arg additional argument to pass to the callback function + */ +void +udp_recv(struct udp_pcb *pcb, udp_recv_fn recv, void *recv_arg) +{ + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_recv: invalid pcb", pcb != NULL, return); + + /* remember recv() callback and user data */ + pcb->recv = recv; + pcb->recv_arg = recv_arg; +} + +/** + * @ingroup udp_raw + * Removes and deallocates the pcb. + * + * @param pcb UDP PCB to be removed. The PCB is removed from the list of + * UDP PCB's and the data structure is freed from memory. + * + * @see udp_new() + */ +void +udp_remove(struct udp_pcb *pcb) +{ + struct udp_pcb *pcb2; + + LWIP_ASSERT_CORE_LOCKED(); + + LWIP_ERROR("udp_remove: invalid pcb", pcb != NULL, return); + + mib2_udp_unbind(pcb); + /* pcb to be removed is first in list? */ + if (udp_pcbs == pcb) { + /* make list start at 2nd pcb */ + udp_pcbs = udp_pcbs->next; + /* pcb not 1st in list */ + } else { + for (pcb2 = udp_pcbs; pcb2 != NULL; pcb2 = pcb2->next) { + /* find pcb in udp_pcbs list */ + if (pcb2->next != NULL && pcb2->next == pcb) { + /* remove pcb from list */ + pcb2->next = pcb->next; + break; + } + } + } + memp_free(MEMP_UDP_PCB, pcb); +} + +/** + * @ingroup udp_raw + * Creates a new UDP pcb which can be used for UDP communication. The + * pcb is not active until it has either been bound to a local address + * or connected to a remote address. + * + * @return The UDP PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new(void) +{ + struct udp_pcb *pcb; + + LWIP_ASSERT_CORE_LOCKED(); + + pcb = (struct udp_pcb *)memp_malloc(MEMP_UDP_PCB); + /* could allocate UDP PCB? */ + if (pcb != NULL) { + /* UDP Lite: by initializing to all zeroes, chksum_len is set to 0 + * which means checksum is generated over the whole datagram per default + * (recommended as default by RFC 3828). */ + /* initialize PCB to all zeroes */ + memset(pcb, 0, sizeof(struct udp_pcb)); + pcb->ttl = UDP_TTL; +#if LWIP_MULTICAST_TX_OPTIONS + udp_set_multicast_ttl(pcb, UDP_TTL); +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + } + return pcb; +} + +/** + * @ingroup udp_raw + * Create a UDP PCB for specific IP type. + * The pcb is not active until it has either been bound to a local address + * or connected to a remote address. + * + * @param type IP address type, see @ref lwip_ip_addr_type definitions. + * If you want to listen to IPv4 and IPv6 (dual-stack) packets, + * supply @ref IPADDR_TYPE_ANY as argument and bind to @ref IP_ANY_TYPE. + * @return The UDP PCB which was created. NULL if the PCB data structure + * could not be allocated. + * + * @see udp_remove() + */ +struct udp_pcb * +udp_new_ip_type(u8_t type) +{ + struct udp_pcb *pcb; + + LWIP_ASSERT_CORE_LOCKED(); + + pcb = udp_new(); +#if LWIP_IPV4 && LWIP_IPV6 + if (pcb != NULL) { + IP_SET_TYPE_VAL(pcb->local_ip, type); + IP_SET_TYPE_VAL(pcb->remote_ip, type); + } +#else + LWIP_UNUSED_ARG(type); +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + return pcb; +} + +/** This function is called from netif.c when address is changed + * + * @param old_addr IP address of the netif before change + * @param new_addr IP address of the netif after change + */ +void udp_netif_ip_addr_changed(const ip_addr_t *old_addr, const ip_addr_t *new_addr) +{ + struct udp_pcb *upcb; + + if (!ip_addr_isany(old_addr) && !ip_addr_isany(new_addr)) { + for (upcb = udp_pcbs; upcb != NULL; upcb = upcb->next) { + /* PCB bound to current local interface address? */ + if (ip_addr_cmp(&upcb->local_ip, old_addr)) { + /* The PCB is bound to the old ipaddr and + * is set to bound to the new one instead */ + ip_addr_copy(upcb->local_ip, *new_addr); + } + } + } +} + +#if UDP_DEBUG +/** + * Print UDP header information for debug purposes. + * + * @param udphdr pointer to the udp header in memory. + */ +void +udp_debug_print(struct udp_hdr *udphdr) +{ + LWIP_DEBUGF(UDP_DEBUG, ("UDP header:\n")); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | %5"U16_F" | (src port, dest port)\n", + lwip_ntohs(udphdr->src), lwip_ntohs(udphdr->dest))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); + LWIP_DEBUGF(UDP_DEBUG, ("| %5"U16_F" | 0x%04"X16_F" | (len, chksum)\n", + lwip_ntohs(udphdr->len), lwip_ntohs(udphdr->chksum))); + LWIP_DEBUGF(UDP_DEBUG, ("+-------------------------------+\n")); +} +#endif /* UDP_DEBUG */ + +#endif /* LWIP_UDP */ diff --git a/Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h b/Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h new file mode 100644 index 0000000..0ed9baf --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/compat/posix/arpa/inet.h @@ -0,0 +1,33 @@ +/** + * @file + * This file is a posix wrapper for lwip/sockets.h. + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/sockets.h" diff --git a/Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h b/Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h new file mode 100644 index 0000000..6b8e63a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/compat/posix/net/if.h @@ -0,0 +1,36 @@ +/** + * @file + * This file is a posix wrapper for lwip/if_api.h. + */ + +/* + * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/if_api.h" diff --git a/Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h b/Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h new file mode 100644 index 0000000..12d4c7f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/compat/posix/netdb.h @@ -0,0 +1,33 @@ +/** + * @file + * This file is a posix wrapper for lwip/netdb.h. + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/netdb.h" diff --git a/Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h b/Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h new file mode 100644 index 0000000..0ed9baf --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/compat/posix/sys/socket.h @@ -0,0 +1,33 @@ +/** + * @file + * This file is a posix wrapper for lwip/sockets.h. + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/sockets.h" diff --git a/Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h b/Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h new file mode 100644 index 0000000..98a9aec --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/compat/stdc/errno.h @@ -0,0 +1,33 @@ +/** + * @file + * This file is a posix/stdc wrapper for lwip/errno.h. + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/errno.h" diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h new file mode 100644 index 0000000..97abc54 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/altcp.h @@ -0,0 +1,201 @@ +/** + * @file + * Application layered TCP connection API (to be used from TCPIP thread)\n + * + * This file contains the generic API. + * For more details see @ref altcp_api. + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_ALTCP_H +#define LWIP_HDR_ALTCP_H + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcpbase.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct altcp_pcb; +struct altcp_functions; + +typedef err_t (*altcp_accept_fn)(void *arg, struct altcp_pcb *new_conn, err_t err); +typedef err_t (*altcp_connected_fn)(void *arg, struct altcp_pcb *conn, err_t err); +typedef err_t (*altcp_recv_fn)(void *arg, struct altcp_pcb *conn, struct pbuf *p, err_t err); +typedef err_t (*altcp_sent_fn)(void *arg, struct altcp_pcb *conn, u16_t len); +typedef err_t (*altcp_poll_fn)(void *arg, struct altcp_pcb *conn); +typedef void (*altcp_err_fn)(void *arg, err_t err); + +typedef struct altcp_pcb* (*altcp_new_fn)(void *arg, u8_t ip_type); + +struct altcp_pcb { + const struct altcp_functions *fns; + struct altcp_pcb *inner_conn; + void *arg; + void *state; + /* application callbacks */ + altcp_accept_fn accept; + altcp_connected_fn connected; + altcp_recv_fn recv; + altcp_sent_fn sent; + altcp_poll_fn poll; + altcp_err_fn err; + u8_t pollinterval; +}; + +/** @ingroup altcp */ +typedef struct altcp_allocator_s { + /** Allocator function */ + altcp_new_fn alloc; + /** Argument to allocator function */ + void *arg; +} altcp_allocator_t; + +struct altcp_pcb *altcp_new(altcp_allocator_t *allocator); +struct altcp_pcb *altcp_new_ip6(altcp_allocator_t *allocator); +struct altcp_pcb *altcp_new_ip_type(altcp_allocator_t *allocator, u8_t ip_type); + +void altcp_arg(struct altcp_pcb *conn, void *arg); +void altcp_accept(struct altcp_pcb *conn, altcp_accept_fn accept); +void altcp_recv(struct altcp_pcb *conn, altcp_recv_fn recv); +void altcp_sent(struct altcp_pcb *conn, altcp_sent_fn sent); +void altcp_poll(struct altcp_pcb *conn, altcp_poll_fn poll, u8_t interval); +void altcp_err(struct altcp_pcb *conn, altcp_err_fn err); + +void altcp_recved(struct altcp_pcb *conn, u16_t len); +err_t altcp_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port); +err_t altcp_connect(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected); + +/* return conn for source code compatibility to tcp callback API only */ +struct altcp_pcb *altcp_listen_with_backlog_and_err(struct altcp_pcb *conn, u8_t backlog, err_t *err); +#define altcp_listen_with_backlog(conn, backlog) altcp_listen_with_backlog_and_err(conn, backlog, NULL) +/** @ingroup altcp */ +#define altcp_listen(conn) altcp_listen_with_backlog_and_err(conn, TCP_DEFAULT_LISTEN_BACKLOG, NULL) + +void altcp_abort(struct altcp_pcb *conn); +err_t altcp_close(struct altcp_pcb *conn); +err_t altcp_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx); + +err_t altcp_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags); +err_t altcp_output(struct altcp_pcb *conn); + +u16_t altcp_mss(struct altcp_pcb *conn); +u16_t altcp_sndbuf(struct altcp_pcb *conn); +u16_t altcp_sndqueuelen(struct altcp_pcb *conn); +void altcp_nagle_disable(struct altcp_pcb *conn); +void altcp_nagle_enable(struct altcp_pcb *conn); +int altcp_nagle_disabled(struct altcp_pcb *conn); + +void altcp_setprio(struct altcp_pcb *conn, u8_t prio); + +err_t altcp_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port); +ip_addr_t *altcp_get_ip(struct altcp_pcb *conn, int local); +u16_t altcp_get_port(struct altcp_pcb *conn, int local); + +#ifdef LWIP_DEBUG +enum tcp_state altcp_dbg_get_tcp_state(struct altcp_pcb *conn); +#endif + +#ifdef __cplusplus +} +#endif + +#else /* LWIP_ALTCP */ + +/* ALTCP disabled, define everything to link against tcp callback API (e.g. to get a small non-ssl httpd) */ + +#include "lwip/tcp.h" + +#define altcp_accept_fn tcp_accept_fn +#define altcp_connected_fn tcp_connected_fn +#define altcp_recv_fn tcp_recv_fn +#define altcp_sent_fn tcp_sent_fn +#define altcp_poll_fn tcp_poll_fn +#define altcp_err_fn tcp_err_fn + +#define altcp_pcb tcp_pcb +#define altcp_tcp_new_ip_type tcp_new_ip_type +#define altcp_tcp_new tcp_new +#define altcp_tcp_new_ip6 tcp_new_ip6 + +#define altcp_new(allocator) tcp_new() +#define altcp_new_ip6(allocator) tcp_new_ip6() +#define altcp_new_ip_type(allocator, ip_type) tcp_new_ip_type(ip_type) + +#define altcp_arg tcp_arg +#define altcp_accept tcp_accept +#define altcp_recv tcp_recv +#define altcp_sent tcp_sent +#define altcp_poll tcp_poll +#define altcp_err tcp_err + +#define altcp_recved tcp_recved +#define altcp_bind tcp_bind +#define altcp_connect tcp_connect + +#define altcp_listen_with_backlog_and_err tcp_listen_with_backlog_and_err +#define altcp_listen_with_backlog tcp_listen_with_backlog +#define altcp_listen tcp_listen + +#define altcp_abort tcp_abort +#define altcp_close tcp_close +#define altcp_shutdown tcp_shutdown + +#define altcp_write tcp_write +#define altcp_output tcp_output + +#define altcp_mss tcp_mss +#define altcp_sndbuf tcp_sndbuf +#define altcp_sndqueuelen tcp_sndqueuelen +#define altcp_nagle_disable tcp_nagle_disable +#define altcp_nagle_enable tcp_nagle_enable +#define altcp_nagle_disabled tcp_nagle_disabled +#define altcp_setprio tcp_setprio + +#define altcp_get_tcp_addrinfo tcp_get_tcp_addrinfo +#define altcp_get_ip(pcb, local) ((local) ? (&(pcb)->local_ip) : (&(pcb)->remote_ip)) + +#ifdef LWIP_DEBUG +#define altcp_dbg_get_tcp_state tcp_dbg_get_tcp_state +#endif + +#endif /* LWIP_ALTCP */ + +#endif /* LWIP_HDR_ALTCP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h new file mode 100644 index 0000000..dbde584 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tcp.h @@ -0,0 +1,72 @@ +/** + * @file + * Application layered TCP connection API (to be used from TCPIP thread)\n + * This interface mimics the tcp callback API to the application while preventing + * direct linking (much like virtual functions). + * This way, an application can make use of other application layer protocols + * on top of TCP without knowing the details (e.g. TLS, proxy connection). + * + * This file contains the base implementation calling into tcp. + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_ALTCP_TCP_H +#define LWIP_HDR_ALTCP_TCP_H + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/altcp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct altcp_pcb *altcp_tcp_new_ip_type(u8_t ip_type); + +#define altcp_tcp_new() altcp_tcp_new_ip_type(IPADDR_TYPE_V4) +#define altcp_tcp_new_ip6() altcp_tcp_new_ip_type(IPADDR_TYPE_V6) + +struct altcp_pcb *altcp_tcp_alloc(void *arg, u8_t ip_type); + +struct tcp_pcb; +struct altcp_pcb *altcp_tcp_wrap(struct tcp_pcb *tpcb); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ALTCP */ + +#endif /* LWIP_HDR_ALTCP_TCP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h b/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h new file mode 100644 index 0000000..7b17c60 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/altcp_tls.h @@ -0,0 +1,117 @@ +/** + * @file + * Application layered TCP/TLS connection API (to be used from TCPIP thread) + * + * @defgroup altcp_tls TLS layer + * @ingroup altcp + * This file contains function prototypes for a TLS layer. + * A port to ARM mbedtls is provided in the apps/ tree + * (LWIP_ALTCP_TLS_MBEDTLS option). + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_ALTCP_TLS_H +#define LWIP_HDR_ALTCP_TLS_H + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#if LWIP_ALTCP_TLS + +#include "lwip/altcp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup altcp_tls + * ALTCP_TLS configuration handle, content depends on port (e.g. mbedtls) + */ +struct altcp_tls_config; + +/** @ingroup altcp_tls + * Create an ALTCP_TLS server configuration handle + */ +struct altcp_tls_config *altcp_tls_create_config_server_privkey_cert(const u8_t *privkey, size_t privkey_len, + const u8_t *privkey_pass, size_t privkey_pass_len, + const u8_t *cert, size_t cert_len); + +/** @ingroup altcp_tls + * Create an ALTCP_TLS client configuration handle + */ +struct altcp_tls_config *altcp_tls_create_config_client(const u8_t *cert, size_t cert_len); + +/** @ingroup altcp_tls + * Create an ALTCP_TLS client configuration handle with two-way server/client authentication + */ +struct altcp_tls_config *altcp_tls_create_config_client_2wayauth(const u8_t *ca, size_t ca_len, const u8_t *privkey, size_t privkey_len, + const u8_t *privkey_pass, size_t privkey_pass_len, + const u8_t *cert, size_t cert_len); + +/** @ingroup altcp_tls + * Free an ALTCP_TLS configuration handle + */ +void altcp_tls_free_config(struct altcp_tls_config *conf); + +/** @ingroup altcp_tls + * Create new ALTCP_TLS layer wrapping an existing pcb as inner connection (e.g. TLS over TCP) + */ +struct altcp_pcb *altcp_tls_wrap(struct altcp_tls_config *config, struct altcp_pcb *inner_pcb); + +/** @ingroup altcp_tls + * Create new ALTCP_TLS pcb and its inner tcp pcb + */ +struct altcp_pcb *altcp_tls_new(struct altcp_tls_config *config, u8_t ip_type); + +/** @ingroup altcp_tls + * Create new ALTCP_TLS layer pcb and its inner tcp pcb. + * Same as @ref altcp_tls_new but this allocator function fits to + * @ref altcp_allocator_t / @ref altcp_new.\n + 'arg' must contain a struct altcp_tls_config *. + */ +struct altcp_pcb *altcp_tls_alloc(void *arg, u8_t ip_type); + +/** @ingroup altcp_tls + * Return pointer to internal TLS context so application can tweak it. + * Real type depends on port (e.g. mbedtls) + */ +void *altcp_tls_context(struct altcp_pcb *conn); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ALTCP_TLS */ +#endif /* LWIP_ALTCP */ +#endif /* LWIP_HDR_ALTCP_TLS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/api.h b/Middlewares/Third_Party/LwIP/src/include/lwip/api.h new file mode 100644 index 0000000..c2afaf2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/api.h @@ -0,0 +1,431 @@ +/** + * @file + * netconn API (to be used from non-TCPIP threads) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_API_H +#define LWIP_HDR_API_H + +#include "lwip/opt.h" + +#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ +/* Note: Netconn API is always available when sockets are enabled - + * sockets are implemented on top of them */ + +#include "lwip/arch.h" +#include "lwip/netbuf.h" +#include "lwip/sys.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ + +/* Flags for netconn_write (u8_t) */ +#define NETCONN_NOFLAG 0x00 +#define NETCONN_NOCOPY 0x00 /* Only for source code compatibility */ +#define NETCONN_COPY 0x01 +#define NETCONN_MORE 0x02 +#define NETCONN_DONTBLOCK 0x04 +#define NETCONN_NOAUTORCVD 0x08 /* prevent netconn_recv_data_tcp() from updating the tcp window - must be done manually via netconn_tcp_recvd() */ +#define NETCONN_NOFIN 0x10 /* upper layer already received data, leave FIN in queue until called again */ + +/* Flags for struct netconn.flags (u8_t) */ +/** This netconn had an error, don't block on recvmbox/acceptmbox any more */ +#define NETCONN_FLAG_MBOXCLOSED 0x01 +/** Should this netconn avoid blocking? */ +#define NETCONN_FLAG_NON_BLOCKING 0x02 +/** Was the last connect action a non-blocking one? */ +#define NETCONN_FLAG_IN_NONBLOCKING_CONNECT 0x04 +#if LWIP_NETCONN_FULLDUPLEX + /** The mbox of this netconn is being deallocated, don't use it anymore */ +#define NETCONN_FLAG_MBOXINVALID 0x08 +#endif /* LWIP_NETCONN_FULLDUPLEX */ +/** If a nonblocking write has been rejected before, poll_tcp needs to + check if the netconn is writable again */ +#define NETCONN_FLAG_CHECK_WRITESPACE 0x10 +#if LWIP_IPV6 +/** If this flag is set then only IPv6 communication is allowed on the + netconn. As per RFC#3493 this features defaults to OFF allowing + dual-stack usage by default. */ +#define NETCONN_FLAG_IPV6_V6ONLY 0x20 +#endif /* LWIP_IPV6 */ +#if LWIP_NETBUF_RECVINFO +/** Received packet info will be recorded for this netconn */ +#define NETCONN_FLAG_PKTINFO 0x40 +#endif /* LWIP_NETBUF_RECVINFO */ +/** A FIN has been received but not passed to the application yet */ +#define NETCONN_FIN_RX_PENDING 0x80 + +/* Helpers to process several netconn_types by the same code */ +#define NETCONNTYPE_GROUP(t) ((t)&0xF0) +#define NETCONNTYPE_DATAGRAM(t) ((t)&0xE0) +#if LWIP_IPV6 +#define NETCONN_TYPE_IPV6 0x08 +#define NETCONNTYPE_ISIPV6(t) (((t)&NETCONN_TYPE_IPV6) != 0) +#define NETCONNTYPE_ISUDPLITE(t) (((t)&0xF3) == NETCONN_UDPLITE) +#define NETCONNTYPE_ISUDPNOCHKSUM(t) (((t)&0xF3) == NETCONN_UDPNOCHKSUM) +#else /* LWIP_IPV6 */ +#define NETCONNTYPE_ISIPV6(t) (0) +#define NETCONNTYPE_ISUDPLITE(t) ((t) == NETCONN_UDPLITE) +#define NETCONNTYPE_ISUDPNOCHKSUM(t) ((t) == NETCONN_UDPNOCHKSUM) +#endif /* LWIP_IPV6 */ + +/** @ingroup netconn_common + * Protocol family and type of the netconn + */ +enum netconn_type { + NETCONN_INVALID = 0, + /** TCP IPv4 */ + NETCONN_TCP = 0x10, +#if LWIP_IPV6 + /** TCP IPv6 */ + NETCONN_TCP_IPV6 = NETCONN_TCP | NETCONN_TYPE_IPV6 /* 0x18 */, +#endif /* LWIP_IPV6 */ + /** UDP IPv4 */ + NETCONN_UDP = 0x20, + /** UDP IPv4 lite */ + NETCONN_UDPLITE = 0x21, + /** UDP IPv4 no checksum */ + NETCONN_UDPNOCHKSUM = 0x22, + +#if LWIP_IPV6 + /** UDP IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ + NETCONN_UDP_IPV6 = NETCONN_UDP | NETCONN_TYPE_IPV6 /* 0x28 */, + /** UDP IPv6 lite (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ + NETCONN_UDPLITE_IPV6 = NETCONN_UDPLITE | NETCONN_TYPE_IPV6 /* 0x29 */, + /** UDP IPv6 no checksum (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ + NETCONN_UDPNOCHKSUM_IPV6 = NETCONN_UDPNOCHKSUM | NETCONN_TYPE_IPV6 /* 0x2a */, +#endif /* LWIP_IPV6 */ + + /** Raw connection IPv4 */ + NETCONN_RAW = 0x40 +#if LWIP_IPV6 + /** Raw connection IPv6 (dual-stack by default, unless you call @ref netconn_set_ipv6only) */ + , NETCONN_RAW_IPV6 = NETCONN_RAW | NETCONN_TYPE_IPV6 /* 0x48 */ +#endif /* LWIP_IPV6 */ +}; + +/** Current state of the netconn. Non-TCP netconns are always + * in state NETCONN_NONE! */ +enum netconn_state { + NETCONN_NONE, + NETCONN_WRITE, + NETCONN_LISTEN, + NETCONN_CONNECT, + NETCONN_CLOSE +}; + +/** Used to inform the callback function about changes + * + * Event explanation: + * + * In the netconn implementation, there are three ways to block a client: + * + * - accept mbox (sys_arch_mbox_fetch(&conn->acceptmbox, &accept_ptr, 0); in netconn_accept()) + * - receive mbox (sys_arch_mbox_fetch(&conn->recvmbox, &buf, 0); in netconn_recv_data()) + * - send queue is full (sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); in lwip_netconn_do_write()) + * + * The events have to be seen as events signaling the state of these mboxes/semaphores. For non-blocking + * connections, you need to know in advance whether a call to a netconn function call would block or not, + * and these events tell you about that. + * + * RCVPLUS events say: Safe to perform a potentially blocking call call once more. + * They are counted in sockets - three RCVPLUS events for accept mbox means you are safe + * to call netconn_accept 3 times without being blocked. + * Same thing for receive mbox. + * + * RCVMINUS events say: Your call to to a possibly blocking function is "acknowledged". + * Socket implementation decrements the counter. + * + * For TX, there is no need to count, its merely a flag. SENDPLUS means you may send something. + * SENDPLUS occurs when enough data was delivered to peer so netconn_send() can be called again. + * A SENDMINUS event occurs when the next call to a netconn_send() would be blocking. + */ +enum netconn_evt { + NETCONN_EVT_RCVPLUS, + NETCONN_EVT_RCVMINUS, + NETCONN_EVT_SENDPLUS, + NETCONN_EVT_SENDMINUS, + NETCONN_EVT_ERROR +}; + +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) +/** Used for netconn_join_leave_group() */ +enum netconn_igmp { + NETCONN_JOIN, + NETCONN_LEAVE +}; +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ + +#if LWIP_DNS +/* Used for netconn_gethostbyname_addrtype(), these should match the DNS_ADDRTYPE defines in dns.h */ +#define NETCONN_DNS_DEFAULT NETCONN_DNS_IPV4_IPV6 +#define NETCONN_DNS_IPV4 0 +#define NETCONN_DNS_IPV6 1 +#define NETCONN_DNS_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */ +#define NETCONN_DNS_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */ +#endif /* LWIP_DNS */ + +/* forward-declare some structs to avoid to include their headers */ +struct ip_pcb; +struct tcp_pcb; +struct udp_pcb; +struct raw_pcb; +struct netconn; +struct api_msg; + +/** A callback prototype to inform about events for a netconn */ +typedef void (* netconn_callback)(struct netconn *, enum netconn_evt, u16_t len); + +/** A netconn descriptor */ +struct netconn { + /** type of the netconn (TCP, UDP or RAW) */ + enum netconn_type type; + /** current state of the netconn */ + enum netconn_state state; + /** the lwIP internal protocol control block */ + union { + struct ip_pcb *ip; + struct tcp_pcb *tcp; + struct udp_pcb *udp; + struct raw_pcb *raw; + } pcb; + /** the last asynchronous unreported error this netconn had */ + err_t pending_err; +#if !LWIP_NETCONN_SEM_PER_THREAD + /** sem that is used to synchronously execute functions in the core context */ + sys_sem_t op_completed; +#endif + /** mbox where received packets are stored until they are fetched + by the netconn application thread (can grow quite big) */ + sys_mbox_t recvmbox; +#if LWIP_TCP + /** mbox where new connections are stored until processed + by the application thread */ + sys_mbox_t acceptmbox; +#endif /* LWIP_TCP */ +#if LWIP_NETCONN_FULLDUPLEX + /** number of threads waiting on an mbox. This is required to unblock + all threads when closing while threads are waiting. */ + int mbox_threads_waiting; +#endif + /** only used for socket layer */ +#if LWIP_SOCKET + int socket; +#endif /* LWIP_SOCKET */ +#if LWIP_SO_SNDTIMEO + /** timeout to wait for sending data (which means enqueueing data for sending + in internal buffers) in milliseconds */ + s32_t send_timeout; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVTIMEO + /** timeout in milliseconds to wait for new data to be received + (or connections to arrive for listening netconns) */ + u32_t recv_timeout; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + /** maximum amount of bytes queued in recvmbox + not used for TCP: adjust TCP_WND instead! */ + int recv_bufsize; + /** number of bytes currently in recvmbox to be received, + tested against recv_bufsize to limit bytes on recvmbox + for UDP and RAW, used for FIONREAD */ + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + /** values <0 mean linger is disabled, values > 0 are seconds to linger */ + s16_t linger; +#endif /* LWIP_SO_LINGER */ + /** flags holding more netconn-internal state, see NETCONN_FLAG_* defines */ + u8_t flags; +#if LWIP_TCP + /** TCP: when data passed to netconn_write doesn't fit into the send buffer, + this temporarily stores the message. + Also used during connect and close. */ + struct api_msg *current_msg; +#endif /* LWIP_TCP */ + /** A callback function that is informed about events for this netconn */ + netconn_callback callback; +}; + +/** This vector type is passed to @ref netconn_write_vectors_partly to send + * multiple buffers at once. + * ATTENTION: This type has to directly map struct iovec since one is casted + * into the other! + */ +struct netvector { + /** pointer to the application buffer that contains the data to send */ + const void *ptr; + /** size of the application data to send */ + size_t len; +}; + +/** Register an Network connection event */ +#define API_EVENT(c,e,l) if (c->callback) { \ + (*c->callback)(c, e, l); \ + } + +/* Network connection functions: */ + +/** @ingroup netconn_common + * Create new netconn connection + * @param t @ref netconn_type */ +#define netconn_new(t) netconn_new_with_proto_and_callback(t, 0, NULL) +#define netconn_new_with_callback(t, c) netconn_new_with_proto_and_callback(t, 0, c) +struct netconn *netconn_new_with_proto_and_callback(enum netconn_type t, u8_t proto, + netconn_callback callback); +err_t netconn_prepare_delete(struct netconn *conn); +err_t netconn_delete(struct netconn *conn); +/** Get the type of a netconn (as enum netconn_type). */ +#define netconn_type(conn) (conn->type) + +err_t netconn_getaddr(struct netconn *conn, ip_addr_t *addr, + u16_t *port, u8_t local); +/** @ingroup netconn_common */ +#define netconn_peer(c,i,p) netconn_getaddr(c,i,p,0) +/** @ingroup netconn_common */ +#define netconn_addr(c,i,p) netconn_getaddr(c,i,p,1) + +err_t netconn_bind(struct netconn *conn, const ip_addr_t *addr, u16_t port); +err_t netconn_bind_if(struct netconn *conn, u8_t if_idx); +err_t netconn_connect(struct netconn *conn, const ip_addr_t *addr, u16_t port); +err_t netconn_disconnect (struct netconn *conn); +err_t netconn_listen_with_backlog(struct netconn *conn, u8_t backlog); +/** @ingroup netconn_tcp */ +#define netconn_listen(conn) netconn_listen_with_backlog(conn, TCP_DEFAULT_LISTEN_BACKLOG) +err_t netconn_accept(struct netconn *conn, struct netconn **new_conn); +err_t netconn_recv(struct netconn *conn, struct netbuf **new_buf); +err_t netconn_recv_udp_raw_netbuf(struct netconn *conn, struct netbuf **new_buf); +err_t netconn_recv_udp_raw_netbuf_flags(struct netconn *conn, struct netbuf **new_buf, u8_t apiflags); +err_t netconn_recv_tcp_pbuf(struct netconn *conn, struct pbuf **new_buf); +err_t netconn_recv_tcp_pbuf_flags(struct netconn *conn, struct pbuf **new_buf, u8_t apiflags); +err_t netconn_tcp_recvd(struct netconn *conn, size_t len); +err_t netconn_sendto(struct netconn *conn, struct netbuf *buf, + const ip_addr_t *addr, u16_t port); +err_t netconn_send(struct netconn *conn, struct netbuf *buf); +err_t netconn_write_partly(struct netconn *conn, const void *dataptr, size_t size, + u8_t apiflags, size_t *bytes_written); +err_t netconn_write_vectors_partly(struct netconn *conn, struct netvector *vectors, u16_t vectorcnt, + u8_t apiflags, size_t *bytes_written); +/** @ingroup netconn_tcp */ +#define netconn_write(conn, dataptr, size, apiflags) \ + netconn_write_partly(conn, dataptr, size, apiflags, NULL) +err_t netconn_close(struct netconn *conn); +err_t netconn_shutdown(struct netconn *conn, u8_t shut_rx, u8_t shut_tx); + +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) +err_t netconn_join_leave_group(struct netconn *conn, const ip_addr_t *multiaddr, + const ip_addr_t *netif_addr, enum netconn_igmp join_or_leave); +err_t netconn_join_leave_group_netif(struct netconn *conn, const ip_addr_t *multiaddr, + u8_t if_idx, enum netconn_igmp join_or_leave); +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ +#if LWIP_DNS +#if LWIP_IPV4 && LWIP_IPV6 +err_t netconn_gethostbyname_addrtype(const char *name, ip_addr_t *addr, u8_t dns_addrtype); +#define netconn_gethostbyname(name, addr) netconn_gethostbyname_addrtype(name, addr, NETCONN_DNS_DEFAULT) +#else /* LWIP_IPV4 && LWIP_IPV6 */ +err_t netconn_gethostbyname(const char *name, ip_addr_t *addr); +#define netconn_gethostbyname_addrtype(name, addr, dns_addrtype) netconn_gethostbyname(name, addr) +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#endif /* LWIP_DNS */ + +err_t netconn_err(struct netconn *conn); +#define netconn_recv_bufsize(conn) ((conn)->recv_bufsize) + +#define netconn_set_flags(conn, set_flags) do { (conn)->flags = (u8_t)((conn)->flags | (set_flags)); } while(0) +#define netconn_clear_flags(conn, clr_flags) do { (conn)->flags = (u8_t)((conn)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0) +#define netconn_is_flag_set(conn, flag) (((conn)->flags & (flag)) != 0) + +/** Set the blocking status of netconn calls (@todo: write/send is missing) */ +#define netconn_set_nonblocking(conn, val) do { if(val) { \ + netconn_set_flags(conn, NETCONN_FLAG_NON_BLOCKING); \ +} else { \ + netconn_clear_flags(conn, NETCONN_FLAG_NON_BLOCKING); }} while(0) +/** Get the blocking status of netconn calls (@todo: write/send is missing) */ +#define netconn_is_nonblocking(conn) (((conn)->flags & NETCONN_FLAG_NON_BLOCKING) != 0) + +#if LWIP_IPV6 +/** @ingroup netconn_common + * TCP: Set the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY) + */ +#define netconn_set_ipv6only(conn, val) do { if(val) { \ + netconn_set_flags(conn, NETCONN_FLAG_IPV6_V6ONLY); \ +} else { \ + netconn_clear_flags(conn, NETCONN_FLAG_IPV6_V6ONLY); }} while(0) +/** @ingroup netconn_common + * TCP: Get the IPv6 ONLY status of netconn calls (see NETCONN_FLAG_IPV6_V6ONLY) + */ +#define netconn_get_ipv6only(conn) (((conn)->flags & NETCONN_FLAG_IPV6_V6ONLY) != 0) +#endif /* LWIP_IPV6 */ + +#if LWIP_SO_SNDTIMEO +/** Set the send timeout in milliseconds */ +#define netconn_set_sendtimeout(conn, timeout) ((conn)->send_timeout = (timeout)) +/** Get the send timeout in milliseconds */ +#define netconn_get_sendtimeout(conn) ((conn)->send_timeout) +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO +/** Set the receive timeout in milliseconds */ +#define netconn_set_recvtimeout(conn, timeout) ((conn)->recv_timeout = (timeout)) +/** Get the receive timeout in milliseconds */ +#define netconn_get_recvtimeout(conn) ((conn)->recv_timeout) +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF +/** Set the receive buffer in bytes */ +#define netconn_set_recvbufsize(conn, recvbufsize) ((conn)->recv_bufsize = (recvbufsize)) +/** Get the receive buffer in bytes */ +#define netconn_get_recvbufsize(conn) ((conn)->recv_bufsize) +#endif /* LWIP_SO_RCVBUF*/ + +#if LWIP_NETCONN_SEM_PER_THREAD +void netconn_thread_init(void); +void netconn_thread_cleanup(void); +#else /* LWIP_NETCONN_SEM_PER_THREAD */ +#define netconn_thread_init() +#define netconn_thread_cleanup() +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN || LWIP_SOCKET */ + +#endif /* LWIP_HDR_API_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h new file mode 100644 index 0000000..65d3127 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_proxyconnect.h @@ -0,0 +1,79 @@ +/** + * @file + * Application layered TCP connection API that executes a proxy-connect. + * + * This file provides a starting layer that executes a proxy-connect e.g. to + * set up TLS connections through a http proxy. + */ + +/* + * Copyright (c) 2018 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#ifndef LWIP_HDR_APPS_ALTCP_PROXYCONNECT_H +#define LWIP_HDR_APPS_ALTCP_PROXYCONNECT_H + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct altcp_proxyconnect_config { + ip_addr_t proxy_addr; + u16_t proxy_port; +}; + + +struct altcp_pcb *altcp_proxyconnect_new(struct altcp_proxyconnect_config *config, struct altcp_pcb *inner_pcb); +struct altcp_pcb *altcp_proxyconnect_new_tcp(struct altcp_proxyconnect_config *config, u8_t ip_type); + +struct altcp_pcb *altcp_proxyconnect_alloc(void *arg, u8_t ip_type); + +#if LWIP_ALTCP_TLS +struct altcp_proxyconnect_tls_config { + struct altcp_proxyconnect_config proxy; + struct altcp_tls_config *tls_config; +}; + +struct altcp_pcb *altcp_proxyconnect_tls_alloc(void *arg, u8_t ip_type); +#endif /* LWIP_ALTCP_TLS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ALTCP */ +#endif /* LWIP_HDR_APPS_ALTCP_PROXYCONNECT_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h new file mode 100644 index 0000000..36cddd9 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/altcp_tls_mbedtls_opts.h @@ -0,0 +1,67 @@ +/** + * @file + * Application layered TCP/TLS connection API (to be used from TCPIP thread) + * + * This file contains options for an mbedtls port of the TLS layer. + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_ALTCP_TLS_OPTS_H +#define LWIP_HDR_ALTCP_TLS_OPTS_H + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +/** LWIP_ALTCP_TLS_MBEDTLS==1: use mbedTLS for TLS support for altcp API + * mbedtls include directory must be reachable via include search path + */ +#ifndef LWIP_ALTCP_TLS_MBEDTLS +#define LWIP_ALTCP_TLS_MBEDTLS 0 +#endif + +/** Configure debug level of this file */ +#ifndef ALTCP_MBEDTLS_DEBUG +#define ALTCP_MBEDTLS_DEBUG LWIP_DBG_OFF +#endif + +/** Set a session timeout in seconds for the basic session cache + * ATTENTION: Using a session cache can lower security by reusing keys! + */ +#ifndef ALTCP_MBEDTLS_SESSION_CACHE_TIMEOUT_SECONDS +#define ALTCP_MBEDTLS_SESSION_CACHE_TIMEOUT_SECONDS 0 +#endif + +#endif /* LWIP_ALTCP */ + +#endif /* LWIP_HDR_ALTCP_TLS_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h new file mode 100644 index 0000000..67b9a60 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/fs.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_APPS_FS_H +#define LWIP_HDR_APPS_FS_H + +#include "httpd_opts.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define FS_READ_EOF -1 +#define FS_READ_DELAYED -2 + +#if HTTPD_PRECALCULATED_CHECKSUM +struct fsdata_chksum { + u32_t offset; + u16_t chksum; + u16_t len; +}; +#endif /* HTTPD_PRECALCULATED_CHECKSUM */ + +#define FS_FILE_FLAGS_HEADER_INCLUDED 0x01 +#define FS_FILE_FLAGS_HEADER_PERSISTENT 0x02 +#define FS_FILE_FLAGS_HEADER_HTTPVER_1_1 0x04 +#define FS_FILE_FLAGS_SSI 0x08 + +/** Define FS_FILE_EXTENSION_T_DEFINED if you have typedef'ed to your private + * pointer type (defaults to 'void' so the default usage is 'void*') + */ +#ifndef FS_FILE_EXTENSION_T_DEFINED +typedef void fs_file_extension; +#endif + +struct fs_file { + const char *data; + int len; + int index; + /* pextension is free for implementations to hold private (extensional) + arbitrary data, e.g. holding some file state or file system handle */ + fs_file_extension *pextension; +#if HTTPD_PRECALCULATED_CHECKSUM + const struct fsdata_chksum *chksum; + u16_t chksum_count; +#endif /* HTTPD_PRECALCULATED_CHECKSUM */ + u8_t flags; +#if LWIP_HTTPD_CUSTOM_FILES + u8_t is_custom_file; +#endif /* LWIP_HTTPD_CUSTOM_FILES */ +#if LWIP_HTTPD_FILE_STATE + void *state; +#endif /* LWIP_HTTPD_FILE_STATE */ +}; + +#if LWIP_HTTPD_FS_ASYNC_READ +typedef void (*fs_wait_cb)(void *arg); +#endif /* LWIP_HTTPD_FS_ASYNC_READ */ + +err_t fs_open(struct fs_file *file, const char *name); +void fs_close(struct fs_file *file); +#if LWIP_HTTPD_DYNAMIC_FILE_READ +#if LWIP_HTTPD_FS_ASYNC_READ +int fs_read_async(struct fs_file *file, char *buffer, int count, fs_wait_cb callback_fn, void *callback_arg); +#else /* LWIP_HTTPD_FS_ASYNC_READ */ +int fs_read(struct fs_file *file, char *buffer, int count); +#endif /* LWIP_HTTPD_FS_ASYNC_READ */ +#endif /* LWIP_HTTPD_DYNAMIC_FILE_READ */ +#if LWIP_HTTPD_FS_ASYNC_READ +int fs_is_file_ready(struct fs_file *file, fs_wait_cb callback_fn, void *callback_arg); +#endif /* LWIP_HTTPD_FS_ASYNC_READ */ +int fs_bytes_left(struct fs_file *file); + +#if LWIP_HTTPD_FILE_STATE +/** This user-defined function is called when a file is opened. */ +void *fs_state_init(struct fs_file *file, const char *name); +/** This user-defined function is called when a file is closed. */ +void fs_state_free(struct fs_file *file, void *state); +#endif /* #if LWIP_HTTPD_FILE_STATE */ + +struct fsdata_file { + const struct fsdata_file *next; + const unsigned char *name; + const unsigned char *data; + int len; + u8_t flags; +#if HTTPD_PRECALCULATED_CHECKSUM + u16_t chksum_count; + const struct fsdata_chksum *chksum; +#endif /* HTTPD_PRECALCULATED_CHECKSUM */ +}; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_FS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h new file mode 100644 index 0000000..8a06308 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/http_client.h @@ -0,0 +1,160 @@ +/** + * @file + * HTTP client + */ + +/* + * Copyright (c) 2018 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#ifndef LWIP_HDR_APPS_HTTP_CLIENT_H +#define LWIP_HDR_APPS_HTTP_CLIENT_H + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/altcp.h" +#include "lwip/prot/iana.h" +#include "lwip/pbuf.h" + +#if LWIP_TCP && LWIP_CALLBACK_API + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup httpc + * HTTPC_HAVE_FILE_IO: define this to 1 to have functions dowloading directly + * to disk via fopen/fwrite. + * These functions are example implementations of the interface only. + */ +#ifndef LWIP_HTTPC_HAVE_FILE_IO +#define LWIP_HTTPC_HAVE_FILE_IO 0 +#endif + +/** + * @ingroup httpc + * The default TCP port used for HTTP + */ +#define HTTP_DEFAULT_PORT LWIP_IANA_PORT_HTTP + +/** + * @ingroup httpc + * HTTP client result codes + */ +typedef enum ehttpc_result { + /** File successfully received */ + HTTPC_RESULT_OK = 0, + /** Unknown error */ + HTTPC_RESULT_ERR_UNKNOWN = 1, + /** Connection to server failed */ + HTTPC_RESULT_ERR_CONNECT = 2, + /** Failed to resolve server hostname */ + HTTPC_RESULT_ERR_HOSTNAME = 3, + /** Connection unexpectedly closed by remote server */ + HTTPC_RESULT_ERR_CLOSED = 4, + /** Connection timed out (server didn't respond in time) */ + HTTPC_RESULT_ERR_TIMEOUT = 5, + /** Server responded with an error code */ + HTTPC_RESULT_ERR_SVR_RESP = 6, + /** Local memory error */ + HTTPC_RESULT_ERR_MEM = 7, + /** Local abort */ + HTTPC_RESULT_LOCAL_ABORT = 8, + /** Content length mismatch */ + HTTPC_RESULT_ERR_CONTENT_LEN = 9 +} httpc_result_t; + +typedef struct _httpc_state httpc_state_t; + +/** + * @ingroup httpc + * Prototype of a http client callback function + * + * @param arg argument specified when initiating the request + * @param httpc_result result of the http transfer (see enum httpc_result_t) + * @param rx_content_len number of bytes received (without headers) + * @param srv_res this contains the http status code received (if any) + * @param err an error returned by internal lwip functions, can help to specify + * the source of the error but must not necessarily be != ERR_OK + */ +typedef void (*httpc_result_fn)(void *arg, httpc_result_t httpc_result, u32_t rx_content_len, u32_t srv_res, err_t err); + +/** + * @ingroup httpc + * Prototype of http client callback: called when the headers are received + * + * @param connection http client connection + * @param arg argument specified when initiating the request + * @param hdr header pbuf(s) (may contain data also) + * @param hdr_len length of the heders in 'hdr' + * @param content_len content length as received in the headers (-1 if not received) + * @return if != ERR_OK is returned, the connection is aborted + */ +typedef err_t (*httpc_headers_done_fn)(httpc_state_t *connection, void *arg, struct pbuf *hdr, u16_t hdr_len, u32_t content_len); + +typedef struct _httpc_connection { + ip_addr_t proxy_addr; + u16_t proxy_port; + u8_t use_proxy; + /* @todo: add username:pass? */ + +#if LWIP_ALTCP + altcp_allocator_t *altcp_allocator; +#endif + + /* this callback is called when the transfer is finished (or aborted) */ + httpc_result_fn result_fn; + /* this callback is called after receiving the http headers + It can abort the connection by returning != ERR_OK */ + httpc_headers_done_fn headers_done_fn; +} httpc_connection_t; + +err_t httpc_get_file(const ip_addr_t* server_addr, u16_t port, const char* uri, const httpc_connection_t *settings, + altcp_recv_fn recv_fn, void* callback_arg, httpc_state_t **connection); +err_t httpc_get_file_dns(const char* server_name, u16_t port, const char* uri, const httpc_connection_t *settings, + altcp_recv_fn recv_fn, void* callback_arg, httpc_state_t **connection); + +#if LWIP_HTTPC_HAVE_FILE_IO +err_t httpc_get_file_to_disk(const ip_addr_t* server_addr, u16_t port, const char* uri, const httpc_connection_t *settings, + void* callback_arg, const char* local_file_name, httpc_state_t **connection); +err_t httpc_get_file_dns_to_disk(const char* server_name, u16_t port, const char* uri, const httpc_connection_t *settings, + void* callback_arg, const char* local_file_name, httpc_state_t **connection); +#endif /* LWIP_HTTPC_HAVE_FILE_IO */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP && LWIP_CALLBACK_API */ + +#endif /* LWIP_HDR_APPS_HTTP_CLIENT_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h new file mode 100644 index 0000000..e872429 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd.h @@ -0,0 +1,255 @@ +/** + * @file + * HTTP server + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * This version of the file has been modified by Texas Instruments to offer + * simple server-side-include (SSI) and Common Gateway Interface (CGI) + * capability. + */ + +#ifndef LWIP_HDR_APPS_HTTPD_H +#define LWIP_HDR_APPS_HTTPD_H + +#include "httpd_opts.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_HTTPD_CGI + +/** + * @ingroup httpd + * Function pointer for a CGI script handler. + * + * This function is called each time the HTTPD server is asked for a file + * whose name was previously registered as a CGI function using a call to + * http_set_cgi_handlers. The iIndex parameter provides the index of the + * CGI within the cgis array passed to http_set_cgi_handlers. Parameters + * pcParam and pcValue provide access to the parameters provided along with + * the URI. iNumParams provides a count of the entries in the pcParam and + * pcValue arrays. Each entry in the pcParam array contains the name of a + * parameter with the corresponding entry in the pcValue array containing the + * value for that parameter. Note that pcParam may contain multiple elements + * with the same name if, for example, a multi-selection list control is used + * in the form generating the data. + * + * The function should return a pointer to a character string which is the + * path and filename of the response that is to be sent to the connected + * browser, for example "/thanks.htm" or "/response/error.ssi". + * + * The maximum number of parameters that will be passed to this function via + * iNumParams is defined by LWIP_HTTPD_MAX_CGI_PARAMETERS. Any parameters in + * the incoming HTTP request above this number will be discarded. + * + * Requests intended for use by this CGI mechanism must be sent using the GET + * method (which encodes all parameters within the URI rather than in a block + * later in the request). Attempts to use the POST method will result in the + * request being ignored. + * + */ +typedef const char *(*tCGIHandler)(int iIndex, int iNumParams, char *pcParam[], + char *pcValue[]); + +/** + * @ingroup httpd + * Structure defining the base filename (URL) of a CGI and the associated + * function which is to be called when that URL is requested. + */ +typedef struct +{ + const char *pcCGIName; + tCGIHandler pfnCGIHandler; +} tCGI; + +void http_set_cgi_handlers(const tCGI *pCGIs, int iNumHandlers); + +#endif /* LWIP_HTTPD_CGI */ + +#if LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI + +#if LWIP_HTTPD_CGI_SSI +/* we have to prototype this struct here to make it available for the handler */ +struct fs_file; + +/** Define this generic CGI handler in your application. + * It is called once for every URI with parameters. + * The parameters can be stored to the object passed as connection_state, which + * is allocated to file->state via fs_state_init() from fs_open() or fs_open_custom(). + * Content creation via SSI or complete dynamic files can retrieve the CGI params from there. + */ +extern void httpd_cgi_handler(struct fs_file *file, const char* uri, int iNumParams, + char **pcParam, char **pcValue +#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE + , void *connection_state +#endif /* LWIP_HTTPD_FILE_STATE */ + ); +#endif /* LWIP_HTTPD_CGI_SSI */ + +#endif /* LWIP_HTTPD_CGI || LWIP_HTTPD_CGI_SSI */ + +#if LWIP_HTTPD_SSI + +/** + * @ingroup httpd + * Function pointer for the SSI tag handler callback. + * + * This function will be called each time the HTTPD server detects a tag of the + * form in files with extensions mentioned in the g_pcSSIExtensions + * array (currently .shtml, .shtm, .ssi, .xml, .json) where "name" appears as + * one of the tags supplied to http_set_ssi_handler in the tags array. The + * returned insert string, which will be appended after the the string + * "" in file sent back to the client, should be written to pointer + * pcInsert. iInsertLen contains the size of the buffer pointed to by + * pcInsert. The iIndex parameter provides the zero-based index of the tag as + * found in the tags array and identifies the tag that is to be processed. + * + * The handler returns the number of characters written to pcInsert excluding + * any terminating NULL or HTTPD_SSI_TAG_UNKNOWN when tag is not recognized. + * + * Note that the behavior of this SSI mechanism is somewhat different from the + * "normal" SSI processing as found in, for example, the Apache web server. In + * this case, the inserted text is appended following the SSI tag rather than + * replacing the tag entirely. This allows for an implementation that does not + * require significant additional buffering of output data yet which will still + * offer usable SSI functionality. One downside to this approach is when + * attempting to use SSI within JavaScript. The SSI tag is structured to + * resemble an HTML comment but this syntax does not constitute a comment + * within JavaScript and, hence, leaving the tag in place will result in + * problems in these cases. In order to avoid these problems, define + * LWIP_HTTPD_SSI_INCLUDE_TAG as zero in your lwip options file, or use JavaScript + * style block comments in the form / * # name * / (without the spaces). + */ +typedef u16_t (*tSSIHandler)( +#if LWIP_HTTPD_SSI_RAW + const char* ssi_tag_name, +#else /* LWIP_HTTPD_SSI_RAW */ + int iIndex, +#endif /* LWIP_HTTPD_SSI_RAW */ + char *pcInsert, int iInsertLen +#if LWIP_HTTPD_SSI_MULTIPART + , u16_t current_tag_part, u16_t *next_tag_part +#endif /* LWIP_HTTPD_SSI_MULTIPART */ +#if defined(LWIP_HTTPD_FILE_STATE) && LWIP_HTTPD_FILE_STATE + , void *connection_state +#endif /* LWIP_HTTPD_FILE_STATE */ + ); + +/** Set the SSI handler function + * (if LWIP_HTTPD_SSI_RAW==1, only the first argument is used) + */ +void http_set_ssi_handler(tSSIHandler pfnSSIHandler, + const char **ppcTags, int iNumTags); + +/** For LWIP_HTTPD_SSI_RAW==1, return this to indicate the tag is unknown. + * In this case, the webserver writes a warning into the page. + * You can also just return 0 to write nothing for unknown tags. + */ +#define HTTPD_SSI_TAG_UNKNOWN 0xFFFF + +#endif /* LWIP_HTTPD_SSI */ + +#if LWIP_HTTPD_SUPPORT_POST + +/* These functions must be implemented by the application */ + +/** + * @ingroup httpd + * Called when a POST request has been received. The application can decide + * whether to accept it or not. + * + * @param connection Unique connection identifier, valid until httpd_post_end + * is called. + * @param uri The HTTP header URI receiving the POST request. + * @param http_request The raw HTTP request (the first packet, normally). + * @param http_request_len Size of 'http_request'. + * @param content_len Content-Length from HTTP header. + * @param response_uri Filename of response file, to be filled when denying the + * request + * @param response_uri_len Size of the 'response_uri' buffer. + * @param post_auto_wnd Set this to 0 to let the callback code handle window + * updates by calling 'httpd_post_data_recved' (to throttle rx speed) + * default is 1 (httpd handles window updates automatically) + * @return ERR_OK: Accept the POST request, data may be passed in + * another err_t: Deny the POST request, send back 'bad request'. + */ +err_t httpd_post_begin(void *connection, const char *uri, const char *http_request, + u16_t http_request_len, int content_len, char *response_uri, + u16_t response_uri_len, u8_t *post_auto_wnd); + +/** + * @ingroup httpd + * Called for each pbuf of data that has been received for a POST. + * ATTENTION: The application is responsible for freeing the pbufs passed in! + * + * @param connection Unique connection identifier. + * @param p Received data. + * @return ERR_OK: Data accepted. + * another err_t: Data denied, http_post_get_response_uri will be called. + */ +err_t httpd_post_receive_data(void *connection, struct pbuf *p); + +/** + * @ingroup httpd + * Called when all data is received or when the connection is closed. + * The application must return the filename/URI of a file to send in response + * to this POST request. If the response_uri buffer is untouched, a 404 + * response is returned. + * + * @param connection Unique connection identifier. + * @param response_uri Filename of response file, to be filled when denying the request + * @param response_uri_len Size of the 'response_uri' buffer. + */ +void httpd_post_finished(void *connection, char *response_uri, u16_t response_uri_len); + +#if LWIP_HTTPD_POST_MANUAL_WND +void httpd_post_data_recved(void *connection, u16_t recved_len); +#endif /* LWIP_HTTPD_POST_MANUAL_WND */ + +#endif /* LWIP_HTTPD_SUPPORT_POST */ + +void httpd_init(void); + +#if HTTPD_ENABLE_HTTPS +struct altcp_tls_config; +void httpd_inits(struct altcp_tls_config *conf); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_HTTPD_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h new file mode 100644 index 0000000..8723961 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/httpd_opts.h @@ -0,0 +1,396 @@ +/** + * @file + * HTTP server options list + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * This version of the file has been modified by Texas Instruments to offer + * simple server-side-include (SSI) and Common Gateway Interface (CGI) + * capability. + */ + +#ifndef LWIP_HDR_APPS_HTTPD_OPTS_H +#define LWIP_HDR_APPS_HTTPD_OPTS_H + +#include "lwip/opt.h" +#include "lwip/prot/iana.h" + +/** + * @defgroup httpd_opts Options + * @ingroup httpd + * @{ + */ + +/** Set this to 1 to support CGI (old style). + * + * This old style CGI support works by registering an array of URLs and + * associated CGI handler functions (@ref http_set_cgi_handlers). + * This list is scanned just before fs_open is called from request handling. + * The handler can return a new URL that is used internally by the httpd to + * load the returned page (passed to fs_open). + * + * Use this CGI type e.g. to execute specific actions and return a page that + * does not depend on the CGI parameters. + */ +#if !defined LWIP_HTTPD_CGI || defined __DOXYGEN__ +#define LWIP_HTTPD_CGI 0 +#endif + +/** Set this to 1 to support CGI (new style). + * + * This new style CGI support works by calling a global function + * (@ref tCGIHandler) for all URLs that are found. fs_open is called first + * and the URL can not be written by the CGI handler. Instead, this handler gets + * passed the http file state, an object where it can store information derived + * from the CGI URL or parameters. This file state is later passed to SSI, so + * the SSI code can return data depending on CGI input. + * + * Use this CGI handler if you want CGI information passed on to SSI. + */ +#if !defined LWIP_HTTPD_CGI_SSI || defined __DOXYGEN__ +#define LWIP_HTTPD_CGI_SSI 0 +#endif + +/** Set this to 1 to support SSI (Server-Side-Includes) + * + * In contrast to other http servers, this only calls a preregistered callback + * function (@see http_set_ssi_handler) for each tag (in the format of + * ) encountered in SSI-enabled pages. + * SSI-enabled pages must have one of the predefined SSI-enabled file extensions. + * All files with one of these extensions are parsed when sent. + * + * A downside of the current SSI implementation is that persistent connections + * don't work, as the file length is not known in advance (and httpd currently + * relies on the Content-Length header for persistent connections). + * + * To save memory, the maximum tag length is limited (@see LWIP_HTTPD_MAX_TAG_NAME_LEN). + * To save memory, the maximum insertion string length is limited (@see + * LWIP_HTTPD_MAX_TAG_INSERT_LEN). If this is not enought, @ref LWIP_HTTPD_SSI_MULTIPART + * can be used. + */ +#if !defined LWIP_HTTPD_SSI || defined __DOXYGEN__ +#define LWIP_HTTPD_SSI 0 +#endif + +/** Set this to 1 to implement an SSI tag handler callback that gets a const char* + * to the tag (instead of an index into a pre-registered array of known tags) + * If this is 0, the SSI handler callback function is only called pre-registered tags. + */ +#if !defined LWIP_HTTPD_SSI_RAW || defined __DOXYGEN__ +#define LWIP_HTTPD_SSI_RAW 0 +#endif + +/** Set this to 0 to prevent parsing the file extension at runtime to decide + * if a file should be scanned for SSI tags or not. + * Default is 1 (file extensions are checked using the g_pcSSIExtensions array) + * Set to 2 to override this runtime test function. + * + * This is enabled by default, but if you only use a newer version of makefsdata + * supporting the "-ssi" option, this info is already present in + */ +#if !defined LWIP_HTTPD_SSI_BY_FILE_EXTENSION || defined __DOXYGEN__ +#define LWIP_HTTPD_SSI_BY_FILE_EXTENSION 1 +#endif + +/** Set this to 1 to support HTTP POST */ +#if !defined LWIP_HTTPD_SUPPORT_POST || defined __DOXYGEN__ +#define LWIP_HTTPD_SUPPORT_POST 0 +#endif + +/* The maximum number of parameters that the CGI handler can be sent. */ +#if !defined LWIP_HTTPD_MAX_CGI_PARAMETERS || defined __DOXYGEN__ +#define LWIP_HTTPD_MAX_CGI_PARAMETERS 16 +#endif + +/** LWIP_HTTPD_SSI_MULTIPART==1: SSI handler function is called with 2 more + * arguments indicating a counter for insert string that are too long to be + * inserted at once: the SSI handler function must then set 'next_tag_part' + * which will be passed back to it in the next call. */ +#if !defined LWIP_HTTPD_SSI_MULTIPART || defined __DOXYGEN__ +#define LWIP_HTTPD_SSI_MULTIPART 0 +#endif + +/* The maximum length of the string comprising the SSI tag name + * ATTENTION: tags longer than this are ignored, not truncated! + */ +#if !defined LWIP_HTTPD_MAX_TAG_NAME_LEN || defined __DOXYGEN__ +#define LWIP_HTTPD_MAX_TAG_NAME_LEN 8 +#endif + +/* The maximum length of string that can be returned to replace any given tag + * If this buffer is not long enough, use LWIP_HTTPD_SSI_MULTIPART. + */ +#if !defined LWIP_HTTPD_MAX_TAG_INSERT_LEN || defined __DOXYGEN__ +#define LWIP_HTTPD_MAX_TAG_INSERT_LEN 192 +#endif + +#if !defined LWIP_HTTPD_POST_MANUAL_WND || defined __DOXYGEN__ +#define LWIP_HTTPD_POST_MANUAL_WND 0 +#endif + +/** This string is passed in the HTTP header as "Server: " */ +#if !defined HTTPD_SERVER_AGENT || defined __DOXYGEN__ +#define HTTPD_SERVER_AGENT "lwIP/" LWIP_VERSION_STRING " (http://savannah.nongnu.org/projects/lwip)" +#endif + +/** Set this to 1 if you want to include code that creates HTTP headers + * at runtime. Default is off: HTTP headers are then created statically + * by the makefsdata tool. Static headers mean smaller code size, but + * the (readonly) fsdata will grow a bit as every file includes the HTTP + * header. */ +#if !defined LWIP_HTTPD_DYNAMIC_HEADERS || defined __DOXYGEN__ +#define LWIP_HTTPD_DYNAMIC_HEADERS 0 +#endif + +#if !defined HTTPD_DEBUG || defined __DOXYGEN__ +#define HTTPD_DEBUG LWIP_DBG_OFF +#endif + +/** Set this to 1 to use a memp pool for allocating + * struct http_state instead of the heap. + * If enabled, you'll need to define MEMP_NUM_PARALLEL_HTTPD_CONNS + * (and MEMP_NUM_PARALLEL_HTTPD_SSI_CONNS for SSI) to set the size of + * the pool(s). + */ +#if !defined HTTPD_USE_MEM_POOL || defined __DOXYGEN__ +#define HTTPD_USE_MEM_POOL 0 +#endif + +/** The server port for HTTPD to use */ +#if !defined HTTPD_SERVER_PORT || defined __DOXYGEN__ +#define HTTPD_SERVER_PORT LWIP_IANA_PORT_HTTP +#endif + +/** The https server port for HTTPD to use */ +#if !defined HTTPD_SERVER_PORT_HTTPS || defined __DOXYGEN__ +#define HTTPD_SERVER_PORT_HTTPS LWIP_IANA_PORT_HTTPS +#endif + +/** Enable https support? */ +#if !defined HTTPD_ENABLE_HTTPS || defined __DOXYGEN__ +#define HTTPD_ENABLE_HTTPS 0 +#endif + +/** Maximum retries before the connection is aborted/closed. + * - number of times pcb->poll is called -> default is 4*500ms = 2s; + * - reset when pcb->sent is called + */ +#if !defined HTTPD_MAX_RETRIES || defined __DOXYGEN__ +#define HTTPD_MAX_RETRIES 4 +#endif + +/** The poll delay is X*500ms */ +#if !defined HTTPD_POLL_INTERVAL || defined __DOXYGEN__ +#define HTTPD_POLL_INTERVAL 4 +#endif + +/** Priority for tcp pcbs created by HTTPD (very low by default). + * Lower priorities get killed first when running out of memory. + */ +#if !defined HTTPD_TCP_PRIO || defined __DOXYGEN__ +#define HTTPD_TCP_PRIO TCP_PRIO_MIN +#endif + +/** Set this to 1 to enable timing each file sent */ +#if !defined LWIP_HTTPD_TIMING || defined __DOXYGEN__ +#define LWIP_HTTPD_TIMING 0 +#endif +/** Set this to 1 to enable timing each file sent */ +#if !defined HTTPD_DEBUG_TIMING || defined __DOXYGEN__ +#define HTTPD_DEBUG_TIMING LWIP_DBG_OFF +#endif + +/** Set this to one to show error pages when parsing a request fails instead + of simply closing the connection. */ +#if !defined LWIP_HTTPD_SUPPORT_EXTSTATUS || defined __DOXYGEN__ +#define LWIP_HTTPD_SUPPORT_EXTSTATUS 0 +#endif + +/** Set this to 0 to drop support for HTTP/0.9 clients (to save some bytes) */ +#if !defined LWIP_HTTPD_SUPPORT_V09 || defined __DOXYGEN__ +#define LWIP_HTTPD_SUPPORT_V09 1 +#endif + +/** Set this to 1 to enable HTTP/1.1 persistent connections. + * ATTENTION: If the generated file system includes HTTP headers, these must + * include the "Connection: keep-alive" header (pass argument "-11" to makefsdata). + */ +#if !defined LWIP_HTTPD_SUPPORT_11_KEEPALIVE || defined __DOXYGEN__ +#define LWIP_HTTPD_SUPPORT_11_KEEPALIVE 0 +#endif + +/** Set this to 1 to support HTTP request coming in in multiple packets/pbufs */ +#if !defined LWIP_HTTPD_SUPPORT_REQUESTLIST || defined __DOXYGEN__ +#define LWIP_HTTPD_SUPPORT_REQUESTLIST 1 +#endif + +#if LWIP_HTTPD_SUPPORT_REQUESTLIST +/** Number of rx pbufs to enqueue to parse an incoming request (up to the first + newline) */ +#if !defined LWIP_HTTPD_REQ_QUEUELEN || defined __DOXYGEN__ +#define LWIP_HTTPD_REQ_QUEUELEN 5 +#endif + +/** Number of (TCP payload-) bytes (in pbufs) to enqueue to parse and incoming + request (up to the first double-newline) */ +#if !defined LWIP_HTTPD_REQ_BUFSIZE || defined __DOXYGEN__ +#define LWIP_HTTPD_REQ_BUFSIZE LWIP_HTTPD_MAX_REQ_LENGTH +#endif + +/** Defines the maximum length of a HTTP request line (up to the first CRLF, + copied from pbuf into this a global buffer when pbuf- or packet-queues + are received - otherwise the input pbuf is used directly) */ +#if !defined LWIP_HTTPD_MAX_REQ_LENGTH || defined __DOXYGEN__ +#define LWIP_HTTPD_MAX_REQ_LENGTH LWIP_MIN(1023, (LWIP_HTTPD_REQ_QUEUELEN * PBUF_POOL_BUFSIZE)) +#endif +#endif /* LWIP_HTTPD_SUPPORT_REQUESTLIST */ + +/** This is the size of a static buffer used when URIs end with '/'. + * In this buffer, the directory requested is concatenated with all the + * configured default file names. + * Set to 0 to disable checking default filenames on non-root directories. + */ +#if !defined LWIP_HTTPD_MAX_REQUEST_URI_LEN || defined __DOXYGEN__ +#define LWIP_HTTPD_MAX_REQUEST_URI_LEN 63 +#endif + +/** Maximum length of the filename to send as response to a POST request, + * filled in by the application when a POST is finished. + */ +#if !defined LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN || defined __DOXYGEN__ +#define LWIP_HTTPD_POST_MAX_RESPONSE_URI_LEN 63 +#endif + +/** Set this to 0 to not send the SSI tag (default is on, so the tag will + * be sent in the HTML page */ +#if !defined LWIP_HTTPD_SSI_INCLUDE_TAG || defined __DOXYGEN__ +#define LWIP_HTTPD_SSI_INCLUDE_TAG 1 +#endif + +/** Set this to 1 to call tcp_abort when tcp_close fails with memory error. + * This can be used to prevent consuming all memory in situations where the + * HTTP server has low priority compared to other communication. */ +#if !defined LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR || defined __DOXYGEN__ +#define LWIP_HTTPD_ABORT_ON_CLOSE_MEM_ERROR 0 +#endif + +/** Set this to 1 to kill the oldest connection when running out of + * memory for 'struct http_state' or 'struct http_ssi_state'. + * ATTENTION: This puts all connections on a linked list, so may be kind of slow. + */ +#if !defined LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED || defined __DOXYGEN__ +#define LWIP_HTTPD_KILL_OLD_ON_CONNECTIONS_EXCEEDED 0 +#endif + +/** Set this to 1 to send URIs without extension without headers + * (who uses this at all??) */ +#if !defined LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI || defined __DOXYGEN__ +#define LWIP_HTTPD_OMIT_HEADER_FOR_EXTENSIONLESS_URI 0 +#endif + +/** Default: Tags are sent from struct http_state and are therefore volatile */ +#if !defined HTTP_IS_TAG_VOLATILE || defined __DOXYGEN__ +#define HTTP_IS_TAG_VOLATILE(ptr) TCP_WRITE_FLAG_COPY +#endif + +/* By default, the httpd is limited to send 2*pcb->mss to keep resource usage low + when http is not an important protocol in the device. */ +#if !defined HTTPD_LIMIT_SENDING_TO_2MSS || defined __DOXYGEN__ +#define HTTPD_LIMIT_SENDING_TO_2MSS 1 +#endif + +/* Define this to a function that returns the maximum amount of data to enqueue. + The function have this signature: u16_t fn(struct altcp_pcb* pcb); + The best place to define this is the hooks file (@see LWIP_HOOK_FILENAME) */ +#if !defined HTTPD_MAX_WRITE_LEN || defined __DOXYGEN__ +#if HTTPD_LIMIT_SENDING_TO_2MSS +#define HTTPD_MAX_WRITE_LEN(pcb) ((u16_t)(2 * altcp_mss(pcb))) +#endif +#endif + +/*------------------- FS OPTIONS -------------------*/ + +/** Set this to 1 and provide the functions: + * - "int fs_open_custom(struct fs_file *file, const char *name)" + * Called first for every opened file to allow opening files + * that are not included in fsdata(_custom).c + * - "void fs_close_custom(struct fs_file *file)" + * Called to free resources allocated by fs_open_custom(). + */ +#if !defined LWIP_HTTPD_CUSTOM_FILES || defined __DOXYGEN__ +#define LWIP_HTTPD_CUSTOM_FILES 0 +#endif + +/** Set this to 1 to support fs_read() to dynamically read file data. + * Without this (default=off), only one-block files are supported, + * and the contents must be ready after fs_open(). + */ +#if !defined LWIP_HTTPD_DYNAMIC_FILE_READ || defined __DOXYGEN__ +#define LWIP_HTTPD_DYNAMIC_FILE_READ 0 +#endif + +/** Set this to 1 to include an application state argument per file + * that is opened. This allows to keep a state per connection/file. + */ +#if !defined LWIP_HTTPD_FILE_STATE || defined __DOXYGEN__ +#define LWIP_HTTPD_FILE_STATE 0 +#endif + +/** HTTPD_PRECALCULATED_CHECKSUM==1: include precompiled checksums for + * predefined (MSS-sized) chunks of the files to prevent having to calculate + * the checksums at runtime. */ +#if !defined HTTPD_PRECALCULATED_CHECKSUM || defined __DOXYGEN__ +#define HTTPD_PRECALCULATED_CHECKSUM 0 +#endif + +/** LWIP_HTTPD_FS_ASYNC_READ==1: support asynchronous read operations + * (fs_read_async returns FS_READ_DELAYED and calls a callback when finished). + */ +#if !defined LWIP_HTTPD_FS_ASYNC_READ || defined __DOXYGEN__ +#define LWIP_HTTPD_FS_ASYNC_READ 0 +#endif + +/** Filename (including path) to use as FS data file */ +#if !defined HTTPD_FSDATA_FILE || defined __DOXYGEN__ +/* HTTPD_USE_CUSTOM_FSDATA: Compatibility with deprecated lwIP option */ +#if defined(HTTPD_USE_CUSTOM_FSDATA) && (HTTPD_USE_CUSTOM_FSDATA != 0) +#define HTTPD_FSDATA_FILE "fsdata_custom.c" +#else +#define HTTPD_FSDATA_FILE "fsdata.c" +#endif +#endif + +/** + * @} + */ + +#endif /* LWIP_HDR_APPS_HTTPD_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h new file mode 100644 index 0000000..cc86e7f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/lwiperf.h @@ -0,0 +1,100 @@ +/** + * @file + * lwIP iPerf server implementation + */ + +/* + * Copyright (c) 2014 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_APPS_LWIPERF_H +#define LWIP_HDR_APPS_LWIPERF_H + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LWIPERF_TCP_PORT_DEFAULT 5001 + +/** lwIPerf test results */ +enum lwiperf_report_type +{ + /** The server side test is done */ + LWIPERF_TCP_DONE_SERVER, + /** The client side test is done */ + LWIPERF_TCP_DONE_CLIENT, + /** Local error lead to test abort */ + LWIPERF_TCP_ABORTED_LOCAL, + /** Data check error lead to test abort */ + LWIPERF_TCP_ABORTED_LOCAL_DATAERROR, + /** Transmit error lead to test abort */ + LWIPERF_TCP_ABORTED_LOCAL_TXERROR, + /** Remote side aborted the test */ + LWIPERF_TCP_ABORTED_REMOTE +}; + +/** Control */ +enum lwiperf_client_type +{ + /** Unidirectional tx only test */ + LWIPERF_CLIENT, + /** Do a bidirectional test simultaneously */ + LWIPERF_DUAL, + /** Do a bidirectional test individually */ + LWIPERF_TRADEOFF +}; + +/** Prototype of a report function that is called when a session is finished. + This report function can show the test results. + @param report_type contains the test result */ +typedef void (*lwiperf_report_fn)(void *arg, enum lwiperf_report_type report_type, + const ip_addr_t* local_addr, u16_t local_port, const ip_addr_t* remote_addr, u16_t remote_port, + u32_t bytes_transferred, u32_t ms_duration, u32_t bandwidth_kbitpsec); + +void* lwiperf_start_tcp_server(const ip_addr_t* local_addr, u16_t local_port, + lwiperf_report_fn report_fn, void* report_arg); +void* lwiperf_start_tcp_server_default(lwiperf_report_fn report_fn, void* report_arg); +void* lwiperf_start_tcp_client(const ip_addr_t* remote_addr, u16_t remote_port, + enum lwiperf_client_type type, + lwiperf_report_fn report_fn, void* report_arg); +void* lwiperf_start_tcp_client_default(const ip_addr_t* remote_addr, + lwiperf_report_fn report_fn, void* report_arg); + +void lwiperf_abort(void* lwiperf_session); + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_LWIPERF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h new file mode 100644 index 0000000..20d7ee2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns.h @@ -0,0 +1,105 @@ +/** + * @file + * MDNS responder + */ + + /* + * Copyright (c) 2015 Verisure Innovation AB + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Erik Ekman + * + */ + +#ifndef LWIP_HDR_APPS_MDNS_H +#define LWIP_HDR_APPS_MDNS_H + +#include "lwip/apps/mdns_opts.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_MDNS_RESPONDER + +enum mdns_sd_proto { + DNSSD_PROTO_UDP = 0, + DNSSD_PROTO_TCP = 1 +}; + +#define MDNS_PROBING_CONFLICT 0 +#define MDNS_PROBING_SUCCESSFUL 1 + +#define MDNS_LABEL_MAXLEN 63 + +struct mdns_host; +struct mdns_service; + +/** Callback function to add text to a reply, called when generating the reply */ +typedef void (*service_get_txt_fn_t)(struct mdns_service *service, void *txt_userdata); + +/** Callback function to let application know the result of probing network for name + * uniqueness, called with result MDNS_PROBING_SUCCESSFUL if no other node claimed + * use for the name for the netif or a service and is safe to use, or MDNS_PROBING_CONFLICT + * if another node is already using it and mdns is disabled on this interface */ +typedef void (*mdns_name_result_cb_t)(struct netif* netif, u8_t result); + +void mdns_resp_init(void); + +void mdns_resp_register_name_result_cb(mdns_name_result_cb_t cb); + +err_t mdns_resp_add_netif(struct netif *netif, const char *hostname, u32_t dns_ttl); +err_t mdns_resp_remove_netif(struct netif *netif); +err_t mdns_resp_rename_netif(struct netif *netif, const char *hostname); + +s8_t mdns_resp_add_service(struct netif *netif, const char *name, const char *service, enum mdns_sd_proto proto, u16_t port, u32_t dns_ttl, service_get_txt_fn_t txt_fn, void *txt_userdata); +err_t mdns_resp_del_service(struct netif *netif, s8_t slot); +err_t mdns_resp_rename_service(struct netif *netif, s8_t slot, const char *name); + +err_t mdns_resp_add_service_txtitem(struct mdns_service *service, const char *txt, u8_t txt_len); + +void mdns_resp_restart(struct netif *netif); +void mdns_resp_announce(struct netif *netif); + +/** + * @ingroup mdns + * Announce IP settings have changed on netif. + * Call this in your callback registered by netif_set_status_callback(). + * No need to call this function when LWIP_NETIF_EXT_STATUS_CALLBACK==1, + * this handled automatically for you. + * @param netif The network interface where settings have changed. + */ +#define mdns_resp_netif_settings_changed(netif) mdns_resp_announce(netif) + +#endif /* LWIP_MDNS_RESPONDER */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_MDNS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h new file mode 100644 index 0000000..45f2c50 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_opts.h @@ -0,0 +1,81 @@ +/** + * @file + * MDNS responder + */ + + /* + * Copyright (c) 2015 Verisure Innovation AB + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Erik Ekman + * + */ + +#ifndef LWIP_HDR_APPS_MDNS_OPTS_H +#define LWIP_HDR_APPS_MDNS_OPTS_H + +#include "lwip/opt.h" + +/** + * @defgroup mdns_opts Options + * @ingroup mdns + * @{ + */ + +/** + * LWIP_MDNS_RESPONDER==1: Turn on multicast DNS module. UDP must be available for MDNS + * transport. IGMP is needed for IPv4 multicast. + */ +#ifndef LWIP_MDNS_RESPONDER +#define LWIP_MDNS_RESPONDER 0 +#endif /* LWIP_MDNS_RESPONDER */ + +/** The maximum number of services per netif */ +#ifndef MDNS_MAX_SERVICES +#define MDNS_MAX_SERVICES 1 +#endif + +/** MDNS_RESP_USENETIF_EXTCALLBACK==1: register an ext_callback on the netif + * to automatically restart probing/announcing on status or address change. + */ +#ifndef MDNS_RESP_USENETIF_EXTCALLBACK +#define MDNS_RESP_USENETIF_EXTCALLBACK LWIP_NETIF_EXT_STATUS_CALLBACK +#endif + +/** + * MDNS_DEBUG: Enable debugging for multicast DNS. + */ +#ifndef MDNS_DEBUG +#define MDNS_DEBUG LWIP_DBG_OFF +#endif + +/** + * @} + */ + +#endif /* LWIP_HDR_APPS_MDNS_OPTS_H */ + diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h new file mode 100644 index 0000000..9635b5b --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mdns_priv.h @@ -0,0 +1,74 @@ +/** + * @file + * MDNS responder private definitions + */ + + /* + * Copyright (c) 2015 Verisure Innovation AB + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Erik Ekman + * + */ +#ifndef LWIP_HDR_MDNS_PRIV_H +#define LWIP_HDR_MDNS_PRIV_H + +#include "lwip/apps/mdns_opts.h" +#include "lwip/pbuf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_MDNS_RESPONDER + +/* Domain struct and methods - visible for unit tests */ + +#define MDNS_DOMAIN_MAXLEN 256 +#define MDNS_READNAME_ERROR 0xFFFF + +struct mdns_domain { + /* Encoded domain name */ + u8_t name[MDNS_DOMAIN_MAXLEN]; + /* Total length of domain name, including zero */ + u16_t length; + /* Set if compression of this domain is not allowed */ + u8_t skip_compression; +}; + +err_t mdns_domain_add_label(struct mdns_domain *domain, const char *label, u8_t len); +u16_t mdns_readname(struct pbuf *p, u16_t offset, struct mdns_domain *domain); +int mdns_domain_eq(struct mdns_domain *a, struct mdns_domain *b); +u16_t mdns_compress_domain(struct pbuf *pbuf, u16_t *offset, struct mdns_domain *domain); + +#endif /* LWIP_MDNS_RESPONDER */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_MDNS_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h new file mode 100644 index 0000000..c2bb228 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt.h @@ -0,0 +1,205 @@ +/** + * @file + * MQTT client + */ + +/* + * Copyright (c) 2016 Erik Andersson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Erik Andersson + * + */ +#ifndef LWIP_HDR_APPS_MQTT_CLIENT_H +#define LWIP_HDR_APPS_MQTT_CLIENT_H + +#include "lwip/apps/mqtt_opts.h" +#include "lwip/err.h" +#include "lwip/ip_addr.h" +#include "lwip/prot/iana.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct mqtt_client_s mqtt_client_t; + +#if LWIP_ALTCP && LWIP_ALTCP_TLS +struct altcp_tls_config; +#endif + +/** @ingroup mqtt + * Default MQTT port (non-TLS) */ +#define MQTT_PORT LWIP_IANA_PORT_MQTT +/** @ingroup mqtt + * Default MQTT TLS port */ +#define MQTT_TLS_PORT LWIP_IANA_PORT_SECURE_MQTT + +/*---------------------------------------------------------------------------------------------- */ +/* Connection with server */ + +/** + * @ingroup mqtt + * Client information and connection parameters */ +struct mqtt_connect_client_info_t { + /** Client identifier, must be set by caller */ + const char *client_id; + /** User name, set to NULL if not used */ + const char* client_user; + /** Password, set to NULL if not used */ + const char* client_pass; + /** keep alive time in seconds, 0 to disable keep alive functionality*/ + u16_t keep_alive; + /** will topic, set to NULL if will is not to be used, + will_msg, will_qos and will retain are then ignored */ + const char* will_topic; + /** will_msg, see will_topic */ + const char* will_msg; + /** will_qos, see will_topic */ + u8_t will_qos; + /** will_retain, see will_topic */ + u8_t will_retain; +#if LWIP_ALTCP && LWIP_ALTCP_TLS + /** TLS configuration for secure connections */ + struct altcp_tls_config *tls_config; +#endif +}; + +/** + * @ingroup mqtt + * Connection status codes */ +typedef enum +{ + /** Accepted */ + MQTT_CONNECT_ACCEPTED = 0, + /** Refused protocol version */ + MQTT_CONNECT_REFUSED_PROTOCOL_VERSION = 1, + /** Refused identifier */ + MQTT_CONNECT_REFUSED_IDENTIFIER = 2, + /** Refused server */ + MQTT_CONNECT_REFUSED_SERVER = 3, + /** Refused user credentials */ + MQTT_CONNECT_REFUSED_USERNAME_PASS = 4, + /** Refused not authorized */ + MQTT_CONNECT_REFUSED_NOT_AUTHORIZED_ = 5, + /** Disconnected */ + MQTT_CONNECT_DISCONNECTED = 256, + /** Timeout */ + MQTT_CONNECT_TIMEOUT = 257 +} mqtt_connection_status_t; + +/** + * @ingroup mqtt + * Function prototype for mqtt connection status callback. Called when + * client has connected to the server after initiating a mqtt connection attempt by + * calling mqtt_client_connect() or when connection is closed by server or an error + * + * @param client MQTT client itself + * @param arg Additional argument to pass to the callback function + * @param status Connect result code or disconnection notification @see mqtt_connection_status_t + * + */ +typedef void (*mqtt_connection_cb_t)(mqtt_client_t *client, void *arg, mqtt_connection_status_t status); + + +/** + * @ingroup mqtt + * Data callback flags */ +enum { + /** Flag set when last fragment of data arrives in data callback */ + MQTT_DATA_FLAG_LAST = 1 +}; + +/** + * @ingroup mqtt + * Function prototype for MQTT incoming publish data callback function. Called when data + * arrives to a subscribed topic @see mqtt_subscribe + * + * @param arg Additional argument to pass to the callback function + * @param data User data, pointed object, data may not be referenced after callback return, + NULL is passed when all publish data are delivered + * @param len Length of publish data fragment + * @param flags MQTT_DATA_FLAG_LAST set when this call contains the last part of data from publish message + * + */ +typedef void (*mqtt_incoming_data_cb_t)(void *arg, const u8_t *data, u16_t len, u8_t flags); + + +/** + * @ingroup mqtt + * Function prototype for MQTT incoming publish function. Called when an incoming publish + * arrives to a subscribed topic @see mqtt_subscribe + * + * @param arg Additional argument to pass to the callback function + * @param topic Zero terminated Topic text string, topic may not be referenced after callback return + * @param tot_len Total length of publish data, if set to 0 (no publish payload) data callback will not be invoked + */ +typedef void (*mqtt_incoming_publish_cb_t)(void *arg, const char *topic, u32_t tot_len); + + +/** + * @ingroup mqtt + * Function prototype for mqtt request callback. Called when a subscribe, unsubscribe + * or publish request has completed + * @param arg Pointer to user data supplied when invoking request + * @param err ERR_OK on success + * ERR_TIMEOUT if no response was received within timeout, + * ERR_ABRT if (un)subscribe was denied + */ +typedef void (*mqtt_request_cb_t)(void *arg, err_t err); + + +err_t mqtt_client_connect(mqtt_client_t *client, const ip_addr_t *ipaddr, u16_t port, mqtt_connection_cb_t cb, void *arg, + const struct mqtt_connect_client_info_t *client_info); + +void mqtt_disconnect(mqtt_client_t *client); + +mqtt_client_t *mqtt_client_new(void); +void mqtt_client_free(mqtt_client_t* client); + +u8_t mqtt_client_is_connected(mqtt_client_t *client); + +void mqtt_set_inpub_callback(mqtt_client_t *client, mqtt_incoming_publish_cb_t, + mqtt_incoming_data_cb_t data_cb, void *arg); + +err_t mqtt_sub_unsub(mqtt_client_t *client, const char *topic, u8_t qos, mqtt_request_cb_t cb, void *arg, u8_t sub); + +/** @ingroup mqtt + *Subscribe to topic */ +#define mqtt_subscribe(client, topic, qos, cb, arg) mqtt_sub_unsub(client, topic, qos, cb, arg, 1) +/** @ingroup mqtt + * Unsubscribe to topic */ +#define mqtt_unsubscribe(client, topic, cb, arg) mqtt_sub_unsub(client, topic, 0, cb, arg, 0) + +err_t mqtt_publish(mqtt_client_t *client, const char *topic, const void *payload, u16_t payload_length, u8_t qos, u8_t retain, + mqtt_request_cb_t cb, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_MQTT_CLIENT_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h new file mode 100644 index 0000000..4226d21 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_opts.h @@ -0,0 +1,103 @@ +/** + * @file + * MQTT client options + */ + +/* + * Copyright (c) 2016 Erik Andersson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Erik Andersson + * + */ +#ifndef LWIP_HDR_APPS_MQTT_OPTS_H +#define LWIP_HDR_APPS_MQTT_OPTS_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mqtt_opts Options + * @ingroup mqtt + * @{ + */ + +/** + * Output ring-buffer size, must be able to fit largest outgoing publish message topic+payloads + */ +#ifndef MQTT_OUTPUT_RINGBUF_SIZE +#define MQTT_OUTPUT_RINGBUF_SIZE 256 +#endif + +/** + * Number of bytes in receive buffer, must be at least the size of the longest incoming topic + 8 + * If one wants to avoid fragmented incoming publish, set length to max incoming topic length + max payload length + 8 + */ +#ifndef MQTT_VAR_HEADER_BUFFER_LEN +#define MQTT_VAR_HEADER_BUFFER_LEN 128 +#endif + +/** + * Maximum number of pending subscribe, unsubscribe and publish requests to server . + */ +#ifndef MQTT_REQ_MAX_IN_FLIGHT +#define MQTT_REQ_MAX_IN_FLIGHT 4 +#endif + +/** + * Seconds between each cyclic timer call. + */ +#ifndef MQTT_CYCLIC_TIMER_INTERVAL +#define MQTT_CYCLIC_TIMER_INTERVAL 5 +#endif + +/** + * Publish, subscribe and unsubscribe request timeout in seconds. + */ +#ifndef MQTT_REQ_TIMEOUT +#define MQTT_REQ_TIMEOUT 30 +#endif + +/** + * Seconds for MQTT connect response timeout after sending connect request + */ +#ifndef MQTT_CONNECT_TIMOUT +#define MQTT_CONNECT_TIMOUT 100 +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_MQTT_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h new file mode 100644 index 0000000..b775913 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/mqtt_priv.h @@ -0,0 +1,104 @@ +/** + * @file + * MQTT client (private interface) + */ + +/* + * Copyright (c) 2016 Erik Andersson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Erik Andersson + * + */ +#ifndef LWIP_HDR_APPS_MQTT_PRIV_H +#define LWIP_HDR_APPS_MQTT_PRIV_H + +#include "lwip/apps/mqtt.h" +#include "lwip/altcp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Pending request item, binds application callback to pending server requests */ +struct mqtt_request_t +{ + /** Next item in list, NULL means this is the last in chain, + next pointing at itself means request is unallocated */ + struct mqtt_request_t *next; + /** Callback to upper layer */ + mqtt_request_cb_t cb; + void *arg; + /** MQTT packet identifier */ + u16_t pkt_id; + /** Expire time relative to element before this */ + u16_t timeout_diff; +}; + +/** Ring buffer */ +struct mqtt_ringbuf_t { + u16_t put; + u16_t get; + u8_t buf[MQTT_OUTPUT_RINGBUF_SIZE]; +}; + +/** MQTT client */ +struct mqtt_client_s +{ + /** Timers and timeouts */ + u16_t cyclic_tick; + u16_t keep_alive; + u16_t server_watchdog; + /** Packet identifier generator*/ + u16_t pkt_id_seq; + /** Packet identifier of pending incoming publish */ + u16_t inpub_pkt_id; + /** Connection state */ + u8_t conn_state; + struct altcp_pcb *conn; + /** Connection callback */ + void *connect_arg; + mqtt_connection_cb_t connect_cb; + /** Pending requests to server */ + struct mqtt_request_t *pend_req_queue; + struct mqtt_request_t req_list[MQTT_REQ_MAX_IN_FLIGHT]; + void *inpub_arg; + /** Incoming data callback */ + mqtt_incoming_data_cb_t data_cb; + mqtt_incoming_publish_cb_t pub_cb; + /** Input */ + u32_t msg_idx; + u8_t rx_buffer[MQTT_VAR_HEADER_BUFFER_LEN]; + /** Output ring-buffer */ + struct mqtt_ringbuf_t output; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_MQTT_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h new file mode 100644 index 0000000..a326d33 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns.h @@ -0,0 +1,51 @@ +/** + * @file + * NETBIOS name service responder + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ +#ifndef LWIP_HDR_APPS_NETBIOS_H +#define LWIP_HDR_APPS_NETBIOS_H + +#include "lwip/apps/netbiosns_opts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void netbiosns_init(void); +#ifndef NETBIOS_LWIP_NAME +void netbiosns_set_name(const char* hostname); +#endif +void netbiosns_stop(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_NETBIOS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h new file mode 100644 index 0000000..1f51ab0 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/netbiosns_opts.h @@ -0,0 +1,66 @@ +/** + * @file + * NETBIOS name service responder options + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ +#ifndef LWIP_HDR_APPS_NETBIOS_OPTS_H +#define LWIP_HDR_APPS_NETBIOS_OPTS_H + +#include "lwip/opt.h" + +/** + * @defgroup netbiosns_opts Options + * @ingroup netbiosns + * @{ + */ + +/** NetBIOS name of lwip device + * This must be uppercase until NETBIOS_STRCMP() is defined to a string + * comparision function that is case insensitive. + * If you want to use the netif's hostname, use this (with LWIP_NETIF_HOSTNAME): + * (ip_current_netif() != NULL ? ip_current_netif()->hostname != NULL ? ip_current_netif()->hostname : "" : "") + * + * If this is not defined, netbiosns_set_name() can be called at runtime to change the name. + */ +#ifdef __DOXYGEN__ +#define NETBIOS_LWIP_NAME "NETBIOSLWIPDEV" +#endif + +/** Respond to NetBIOS name queries + * Default is disabled + */ +#if !defined LWIP_NETBIOS_RESPOND_NAME_QUERY || defined __DOXYGEN__ +#define LWIP_NETBIOS_RESPOND_NAME_QUERY 0 +#endif + +/** + * @} + */ + +#endif /* LWIP_HDR_APPS_NETBIOS_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h new file mode 100644 index 0000000..fb4a4a7 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp.h @@ -0,0 +1,128 @@ +#ifndef LWIP_HDR_APPS_SMTP_H +#define LWIP_HDR_APPS_SMTP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwip/apps/smtp_opts.h" +#include "lwip/err.h" +#include "lwip/prot/iana.h" + +/** The default TCP port used for SMTP */ +#define SMTP_DEFAULT_PORT LWIP_IANA_PORT_SMTP +/** The default TCP port used for SMTPS */ +#define SMTPS_DEFAULT_PORT LWIP_IANA_PORT_SMTPS + +/** Email successfully sent */ +#define SMTP_RESULT_OK 0 +/** Unknown error */ +#define SMTP_RESULT_ERR_UNKNOWN 1 +/** Connection to server failed */ +#define SMTP_RESULT_ERR_CONNECT 2 +/** Failed to resolve server hostname */ +#define SMTP_RESULT_ERR_HOSTNAME 3 +/** Connection unexpectedly closed by remote server */ +#define SMTP_RESULT_ERR_CLOSED 4 +/** Connection timed out (server didn't respond in time) */ +#define SMTP_RESULT_ERR_TIMEOUT 5 +/** Server responded with an unknown response code */ +#define SMTP_RESULT_ERR_SVR_RESP 6 +/** Out of resources locally */ +#define SMTP_RESULT_ERR_MEM 7 + +/** Prototype of an smtp callback function + * + * @param arg argument specified when initiating the email + * @param smtp_result result of the mail transfer (see defines SMTP_RESULT_*) + * @param srv_err if aborted by the server, this contains the error code received + * @param err an error returned by internal lwip functions, can help to specify + * the source of the error but must not necessarily be != ERR_OK + */ +typedef void (*smtp_result_fn)(void *arg, u8_t smtp_result, u16_t srv_err, err_t err); + +/** This structure is used as argument for smtp_send_mail_int(), + * which in turn can be used with tcpip_callback() to send mail + * from interrupt context, e.g. like this: + * struct smtp_send_request *req; (to be filled) + * tcpip_try_callback(smtp_send_mail_int, (void*)req); + * + * For member description, see parameter description of smtp_send_mail(). + * When using with tcpip_callback, this structure has to stay allocated + * (e.g. using mem_malloc/mem_free) until its 'callback_fn' is called. + */ +struct smtp_send_request { + const char *from; + const char* to; + const char* subject; + const char* body; + smtp_result_fn callback_fn; + void* callback_arg; + /** If this is != 0, data is *not* copied into an extra buffer + * but used from the pointers supplied in this struct. + * This means less memory usage, but data must stay untouched until + * the callback function is called. */ + u8_t static_data; +}; + + +#if SMTP_BODYDH + +#ifndef SMTP_BODYDH_BUFFER_SIZE +#define SMTP_BODYDH_BUFFER_SIZE 256 +#endif /* SMTP_BODYDH_BUFFER_SIZE */ + +struct smtp_bodydh { + u16_t state; + u16_t length; /* Length of content in buffer */ + char buffer[SMTP_BODYDH_BUFFER_SIZE]; /* buffer for generated content */ +#ifdef SMTP_BODYDH_USER_SIZE + u8_t user[SMTP_BODYDH_USER_SIZE]; +#endif /* SMTP_BODYDH_USER_SIZE */ +}; + +enum bdh_retvals_e { + BDH_DONE = 0, + BDH_WORKING +}; + +/** Prototype of an smtp body callback function + * It receives a struct smtp_bodydh, and a buffer to write data, + * must return BDH_WORKING to be called again and BDH_DONE when + * it has finished processing. This one tries to fill one TCP buffer with + * data, your function will be repeatedly called until that happens; so if you + * know you'll be taking too long to serve your request, pause once in a while + * by writing length=0 to avoid hogging system resources + * + * @param arg argument specified when initiating the email + * @param smtp_bodydh state handling + buffer structure + */ +typedef int (*smtp_bodycback_fn)(void *arg, struct smtp_bodydh *bodydh); + +err_t smtp_send_mail_bodycback(const char *from, const char* to, const char* subject, + smtp_bodycback_fn bodycback_fn, smtp_result_fn callback_fn, void* callback_arg); + +#endif /* SMTP_BODYDH */ + + +err_t smtp_set_server_addr(const char* server); +void smtp_set_server_port(u16_t port); +#if LWIP_ALTCP && LWIP_ALTCP_TLS +struct altcp_tls_config; +void smtp_set_tls_config(struct altcp_tls_config *tls_config); +#endif +err_t smtp_set_auth(const char* username, const char* pass); +err_t smtp_send_mail(const char *from, const char* to, const char* subject, const char* body, + smtp_result_fn callback_fn, void* callback_arg); +err_t smtp_send_mail_static(const char *from, const char* to, const char* subject, const char* body, + smtp_result_fn callback_fn, void* callback_arg); +void smtp_send_mail_int(void *arg); +#ifdef LWIP_DEBUG +const char* smtp_result_str(u8_t smtp_result); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SMTP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h new file mode 100644 index 0000000..bc743f6 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/smtp_opts.h @@ -0,0 +1,81 @@ +#ifndef LWIP_HDR_APPS_SMTP_OPTS_H +#define LWIP_HDR_APPS_SMTP_OPTS_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup smtp_opts Options + * @ingroup smtp + * + * @{ + */ + +/** Set this to 1 to enable data handler callback on BODY */ +#ifndef SMTP_BODYDH +#define SMTP_BODYDH 0 +#endif + +/** SMTP_DEBUG: Enable debugging for SNTP. */ +#ifndef SMTP_DEBUG +#define SMTP_DEBUG LWIP_DBG_OFF +#endif + +/** Maximum length reserved for server name including terminating 0 byte */ +#ifndef SMTP_MAX_SERVERNAME_LEN +#define SMTP_MAX_SERVERNAME_LEN 256 +#endif + +/** Maximum length reserved for username */ +#ifndef SMTP_MAX_USERNAME_LEN +#define SMTP_MAX_USERNAME_LEN 32 +#endif + +/** Maximum length reserved for password */ +#ifndef SMTP_MAX_PASS_LEN +#define SMTP_MAX_PASS_LEN 32 +#endif + +/** Set this to 0 if you know the authentication data will not change + * during the smtp session, which saves some heap space. */ +#ifndef SMTP_COPY_AUTHDATA +#define SMTP_COPY_AUTHDATA 1 +#endif + +/** Set this to 0 to save some code space if you know for sure that all data + * passed to this module conforms to the requirements in the SMTP RFC. + * WARNING: use this with care! + */ +#ifndef SMTP_CHECK_DATA +#define SMTP_CHECK_DATA 1 +#endif + +/** Set this to 1 to enable AUTH PLAIN support */ +#ifndef SMTP_SUPPORT_AUTH_PLAIN +#define SMTP_SUPPORT_AUTH_PLAIN 1 +#endif + +/** Set this to 1 to enable AUTH LOGIN support */ +#ifndef SMTP_SUPPORT_AUTH_LOGIN +#define SMTP_SUPPORT_AUTH_LOGIN 1 +#endif + +/* Memory allocation/deallocation can be overridden... */ +#ifndef SMTP_STATE_MALLOC +#define SMTP_STATE_MALLOC(size) mem_malloc(size) +#define SMTP_STATE_FREE(ptr) mem_free(ptr) +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SMTP_OPTS_H */ + diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h new file mode 100644 index 0000000..a3f8eb1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp.h @@ -0,0 +1,135 @@ +/** + * @file + * SNMP server main API - start and basic configuration + */ + +/* + * Copyright (c) 2001, 2002 Leon Woestenberg + * Copyright (c) 2001, 2002 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * Martin Hentschel + * + */ +#ifndef LWIP_HDR_APPS_SNMP_H +#define LWIP_HDR_APPS_SNMP_H + +#include "lwip/apps/snmp_opts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/err.h" +#include "lwip/apps/snmp_core.h" + +/** SNMP variable binding descriptor (publically needed for traps) */ +struct snmp_varbind +{ + /** pointer to next varbind, NULL for last in list */ + struct snmp_varbind *next; + /** pointer to previous varbind, NULL for first in list */ + struct snmp_varbind *prev; + + /** object identifier */ + struct snmp_obj_id oid; + + /** value ASN1 type */ + u8_t type; + /** object value length */ + u16_t value_len; + /** object value */ + void *value; +}; + +/** + * @ingroup snmp_core + * Agent setup, start listening to port 161. + */ +void snmp_init(void); +void snmp_set_mibs(const struct snmp_mib **mibs, u8_t num_mibs); + +void snmp_set_device_enterprise_oid(const struct snmp_obj_id* device_enterprise_oid); +const struct snmp_obj_id* snmp_get_device_enterprise_oid(void); + +void snmp_trap_dst_enable(u8_t dst_idx, u8_t enable); +void snmp_trap_dst_ip_set(u8_t dst_idx, const ip_addr_t *dst); + +/** Generic trap: cold start */ +#define SNMP_GENTRAP_COLDSTART 0 +/** Generic trap: warm start */ +#define SNMP_GENTRAP_WARMSTART 1 +/** Generic trap: link down */ +#define SNMP_GENTRAP_LINKDOWN 2 +/** Generic trap: link up */ +#define SNMP_GENTRAP_LINKUP 3 +/** Generic trap: authentication failure */ +#define SNMP_GENTRAP_AUTH_FAILURE 4 +/** Generic trap: EGP neighbor lost */ +#define SNMP_GENTRAP_EGP_NEIGHBOR_LOSS 5 +/** Generic trap: enterprise specific */ +#define SNMP_GENTRAP_ENTERPRISE_SPECIFIC 6 + +err_t snmp_send_trap_generic(s32_t generic_trap); +err_t snmp_send_trap_specific(s32_t specific_trap, struct snmp_varbind *varbinds); +err_t snmp_send_trap(const struct snmp_obj_id* oid, s32_t generic_trap, s32_t specific_trap, struct snmp_varbind *varbinds); + +#define SNMP_AUTH_TRAPS_DISABLED 0 +#define SNMP_AUTH_TRAPS_ENABLED 1 +void snmp_set_auth_traps_enabled(u8_t enable); +u8_t snmp_get_auth_traps_enabled(void); + +u8_t snmp_v1_enabled(void); +u8_t snmp_v2c_enabled(void); +u8_t snmp_v3_enabled(void); +void snmp_v1_enable(u8_t enable); +void snmp_v2c_enable(u8_t enable); +void snmp_v3_enable(u8_t enable); + +const char * snmp_get_community(void); +const char * snmp_get_community_write(void); +const char * snmp_get_community_trap(void); +void snmp_set_community(const char * const community); +void snmp_set_community_write(const char * const community); +void snmp_set_community_trap(const char * const community); + +void snmp_coldstart_trap(void); +void snmp_authfail_trap(void); + +typedef void (*snmp_write_callback_fct)(const u32_t* oid, u8_t oid_len, void* callback_arg); +void snmp_set_write_callback(snmp_write_callback_fct write_callback, void* callback_arg); + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SNMP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h new file mode 100644 index 0000000..6021c72 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_core.h @@ -0,0 +1,377 @@ +/** + * @file + * SNMP core API for implementing MIBs + */ + +/* + * Copyright (c) 2006 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Christiaan Simons + * Martin Hentschel + */ + +#ifndef LWIP_HDR_APPS_SNMP_CORE_H +#define LWIP_HDR_APPS_SNMP_CORE_H + +#include "lwip/apps/snmp_opts.h" + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* basic ASN1 defines */ +#define SNMP_ASN1_CLASS_UNIVERSAL 0x00 +#define SNMP_ASN1_CLASS_APPLICATION 0x40 +#define SNMP_ASN1_CLASS_CONTEXT 0x80 +#define SNMP_ASN1_CLASS_PRIVATE 0xC0 + +#define SNMP_ASN1_CONTENTTYPE_PRIMITIVE 0x00 +#define SNMP_ASN1_CONTENTTYPE_CONSTRUCTED 0x20 + +/* universal tags (from ASN.1 spec.) */ +#define SNMP_ASN1_UNIVERSAL_END_OF_CONTENT 0 +#define SNMP_ASN1_UNIVERSAL_INTEGER 2 +#define SNMP_ASN1_UNIVERSAL_OCTET_STRING 4 +#define SNMP_ASN1_UNIVERSAL_NULL 5 +#define SNMP_ASN1_UNIVERSAL_OBJECT_ID 6 +#define SNMP_ASN1_UNIVERSAL_SEQUENCE_OF 16 + +/* application specific (SNMP) tags (from SNMPv2-SMI) */ +#define SNMP_ASN1_APPLICATION_IPADDR 0 /* [APPLICATION 0] IMPLICIT OCTET STRING (SIZE (4)) */ +#define SNMP_ASN1_APPLICATION_COUNTER 1 /* [APPLICATION 1] IMPLICIT INTEGER (0..4294967295) => u32_t */ +#define SNMP_ASN1_APPLICATION_GAUGE 2 /* [APPLICATION 2] IMPLICIT INTEGER (0..4294967295) => u32_t */ +#define SNMP_ASN1_APPLICATION_TIMETICKS 3 /* [APPLICATION 3] IMPLICIT INTEGER (0..4294967295) => u32_t */ +#define SNMP_ASN1_APPLICATION_OPAQUE 4 /* [APPLICATION 4] IMPLICIT OCTET STRING */ +#define SNMP_ASN1_APPLICATION_COUNTER64 6 /* [APPLICATION 6] IMPLICIT INTEGER (0..18446744073709551615) */ + +/* context specific (SNMP) tags (from RFC 1905) */ +#define SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE 1 + +/* full ASN1 type defines */ +#define SNMP_ASN1_TYPE_END_OF_CONTENT (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_END_OF_CONTENT) +#define SNMP_ASN1_TYPE_INTEGER (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_INTEGER) +#define SNMP_ASN1_TYPE_OCTET_STRING (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OCTET_STRING) +#define SNMP_ASN1_TYPE_NULL (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_NULL) +#define SNMP_ASN1_TYPE_OBJECT_ID (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_UNIVERSAL_OBJECT_ID) +#define SNMP_ASN1_TYPE_SEQUENCE (SNMP_ASN1_CLASS_UNIVERSAL | SNMP_ASN1_CONTENTTYPE_CONSTRUCTED | SNMP_ASN1_UNIVERSAL_SEQUENCE_OF) +#define SNMP_ASN1_TYPE_IPADDR (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_IPADDR) +#define SNMP_ASN1_TYPE_IPADDRESS SNMP_ASN1_TYPE_IPADDR +#define SNMP_ASN1_TYPE_COUNTER (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER) +#define SNMP_ASN1_TYPE_COUNTER32 SNMP_ASN1_TYPE_COUNTER +#define SNMP_ASN1_TYPE_GAUGE (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_GAUGE) +#define SNMP_ASN1_TYPE_GAUGE32 SNMP_ASN1_TYPE_GAUGE +#define SNMP_ASN1_TYPE_UNSIGNED32 SNMP_ASN1_TYPE_GAUGE +#define SNMP_ASN1_TYPE_TIMETICKS (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_TIMETICKS) +#define SNMP_ASN1_TYPE_OPAQUE (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_OPAQUE) +#if LWIP_HAVE_INT64 +#define SNMP_ASN1_TYPE_COUNTER64 (SNMP_ASN1_CLASS_APPLICATION | SNMP_ASN1_CONTENTTYPE_PRIMITIVE | SNMP_ASN1_APPLICATION_COUNTER64) +#endif + +#define SNMP_VARBIND_EXCEPTION_OFFSET 0xF0 +#define SNMP_VARBIND_EXCEPTION_MASK 0x0F + +/** error codes predefined by SNMP prot. */ +typedef enum { + SNMP_ERR_NOERROR = 0, +/* +outdated v1 error codes. do not use anmore! +#define SNMP_ERR_NOSUCHNAME 2 use SNMP_ERR_NOSUCHINSTANCE instead +#define SNMP_ERR_BADVALUE 3 use SNMP_ERR_WRONGTYPE,SNMP_ERR_WRONGLENGTH,SNMP_ERR_WRONGENCODING or SNMP_ERR_WRONGVALUE instead +#define SNMP_ERR_READONLY 4 use SNMP_ERR_NOTWRITABLE instead +*/ + SNMP_ERR_GENERROR = 5, + SNMP_ERR_NOACCESS = 6, + SNMP_ERR_WRONGTYPE = 7, + SNMP_ERR_WRONGLENGTH = 8, + SNMP_ERR_WRONGENCODING = 9, + SNMP_ERR_WRONGVALUE = 10, + SNMP_ERR_NOCREATION = 11, + SNMP_ERR_INCONSISTENTVALUE = 12, + SNMP_ERR_RESOURCEUNAVAILABLE = 13, + SNMP_ERR_COMMITFAILED = 14, + SNMP_ERR_UNDOFAILED = 15, + SNMP_ERR_NOTWRITABLE = 17, + SNMP_ERR_INCONSISTENTNAME = 18, + + SNMP_ERR_NOSUCHINSTANCE = SNMP_VARBIND_EXCEPTION_OFFSET + SNMP_ASN1_CONTEXT_VARBIND_NO_SUCH_INSTANCE +} snmp_err_t; + +/** internal object identifier representation */ +struct snmp_obj_id +{ + u8_t len; + u32_t id[SNMP_MAX_OBJ_ID_LEN]; +}; + +struct snmp_obj_id_const_ref +{ + u8_t len; + const u32_t* id; +}; + +extern const struct snmp_obj_id_const_ref snmp_zero_dot_zero; /* administrative identifier from SNMPv2-SMI */ + +/** SNMP variant value, used as reference in struct snmp_node_instance and table implementation */ +union snmp_variant_value +{ + void* ptr; + const void* const_ptr; + u32_t u32; + s32_t s32; +#if LWIP_HAVE_INT64 + u64_t u64; +#endif +}; + + +/** +SNMP MIB node types + tree node is the only node the stack can process in order to walk the tree, + all other nodes are assumed to be leaf nodes. + This cannot be an enum because users may want to define their own node types. +*/ +#define SNMP_NODE_TREE 0x00 +/* predefined leaf node types */ +#define SNMP_NODE_SCALAR 0x01 +#define SNMP_NODE_SCALAR_ARRAY 0x02 +#define SNMP_NODE_TABLE 0x03 +#define SNMP_NODE_THREADSYNC 0x04 + +/** node "base class" layout, the mandatory fields for a node */ +struct snmp_node +{ + /** one out of SNMP_NODE_TREE or any leaf node type (like SNMP_NODE_SCALAR) */ + u8_t node_type; + /** the number assigned to this node which used as part of the full OID */ + u32_t oid; +}; + +/** SNMP node instance access types */ +typedef enum { + SNMP_NODE_INSTANCE_ACCESS_READ = 1, + SNMP_NODE_INSTANCE_ACCESS_WRITE = 2, + SNMP_NODE_INSTANCE_READ_ONLY = SNMP_NODE_INSTANCE_ACCESS_READ, + SNMP_NODE_INSTANCE_READ_WRITE = (SNMP_NODE_INSTANCE_ACCESS_READ | SNMP_NODE_INSTANCE_ACCESS_WRITE), + SNMP_NODE_INSTANCE_WRITE_ONLY = SNMP_NODE_INSTANCE_ACCESS_WRITE, + SNMP_NODE_INSTANCE_NOT_ACCESSIBLE = 0 +} snmp_access_t; + +struct snmp_node_instance; + +typedef s16_t (*node_instance_get_value_method)(struct snmp_node_instance*, void*); +typedef snmp_err_t (*node_instance_set_test_method)(struct snmp_node_instance*, u16_t, void*); +typedef snmp_err_t (*node_instance_set_value_method)(struct snmp_node_instance*, u16_t, void*); +typedef void (*node_instance_release_method)(struct snmp_node_instance*); + +#define SNMP_GET_VALUE_RAW_DATA 0x4000 /* do not use 0x8000 because return value of node_instance_get_value_method is signed16 and 0x8000 would be the signed bit */ + +/** SNMP node instance */ +struct snmp_node_instance +{ + /** prefilled with the node, get_instance() is called on; may be changed by user to any value to pass an arbitrary node between calls to get_instance() and get_value/test_value/set_value */ + const struct snmp_node* node; + /** prefilled with the instance id requested; for get_instance() this is the exact oid requested; for get_next_instance() this is the relative starting point, stack expects relative oid of next node here */ + struct snmp_obj_id instance_oid; + + /** ASN type for this object (see snmp_asn1.h for definitions) */ + u8_t asn1_type; + /** one out of instance access types defined above (SNMP_NODE_INSTANCE_READ_ONLY,...) */ + snmp_access_t access; + + /** returns object value for the given object identifier. Return values <0 to indicate an error */ + node_instance_get_value_method get_value; + /** tests length and/or range BEFORE setting */ + node_instance_set_test_method set_test; + /** sets object value, only called when set_test() was successful */ + node_instance_set_value_method set_value; + /** called in any case when the instance is not required anymore by stack (useful for freeing memory allocated in get_instance/get_next_instance methods) */ + node_instance_release_method release_instance; + + /** reference to pass arbitrary value between calls to get_instance() and get_value/test_value/set_value */ + union snmp_variant_value reference; + /** see reference (if reference is a pointer, the length of underlying data may be stored here or anything else) */ + u32_t reference_len; +}; + + +/** SNMP tree node */ +struct snmp_tree_node +{ + /** inherited "base class" members */ + struct snmp_node node; + u16_t subnode_count; + const struct snmp_node* const *subnodes; +}; + +#define SNMP_CREATE_TREE_NODE(oid, subnodes) \ + {{ SNMP_NODE_TREE, (oid) }, \ + (u16_t)LWIP_ARRAYSIZE(subnodes), (subnodes) } + +#define SNMP_CREATE_EMPTY_TREE_NODE(oid) \ + {{ SNMP_NODE_TREE, (oid) }, \ + 0, NULL } + +/** SNMP leaf node */ +struct snmp_leaf_node +{ + /** inherited "base class" members */ + struct snmp_node node; + snmp_err_t (*get_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); + snmp_err_t (*get_next_instance)(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); +}; + +/** represents a single mib with its base oid and root node */ +struct snmp_mib +{ + const u32_t *base_oid; + u8_t base_oid_len; + const struct snmp_node *root_node; +}; + +#define SNMP_MIB_CREATE(oid_list, root_node) { (oid_list), (u8_t)LWIP_ARRAYSIZE(oid_list), root_node } + +/** OID range structure */ +struct snmp_oid_range +{ + u32_t min; + u32_t max; +}; + +/** checks if incoming OID length and values are in allowed ranges */ +u8_t snmp_oid_in_range(const u32_t *oid_in, u8_t oid_len, const struct snmp_oid_range *oid_ranges, u8_t oid_ranges_len); + +typedef enum { + SNMP_NEXT_OID_STATUS_SUCCESS, + SNMP_NEXT_OID_STATUS_NO_MATCH, + SNMP_NEXT_OID_STATUS_BUF_TO_SMALL +} snmp_next_oid_status_t; + +/** state for next_oid_init / next_oid_check functions */ +struct snmp_next_oid_state +{ + const u32_t* start_oid; + u8_t start_oid_len; + + u32_t* next_oid; + u8_t next_oid_len; + u8_t next_oid_max_len; + + snmp_next_oid_status_t status; + void* reference; +}; + +void snmp_next_oid_init(struct snmp_next_oid_state *state, + const u32_t *start_oid, u8_t start_oid_len, + u32_t *next_oid_buf, u8_t next_oid_max_len); +u8_t snmp_next_oid_precheck(struct snmp_next_oid_state *state, const u32_t *oid, u8_t oid_len); +u8_t snmp_next_oid_check(struct snmp_next_oid_state *state, const u32_t *oid, u8_t oid_len, void* reference); + +void snmp_oid_assign(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len); +void snmp_oid_combine(struct snmp_obj_id* target, const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len); +void snmp_oid_prefix(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len); +void snmp_oid_append(struct snmp_obj_id* target, const u32_t *oid, u8_t oid_len); +u8_t snmp_oid_equal(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len); +s8_t snmp_oid_compare(const u32_t *oid1, u8_t oid1_len, const u32_t *oid2, u8_t oid2_len); + +#if LWIP_IPV4 +u8_t snmp_oid_to_ip4(const u32_t *oid, ip4_addr_t *ip); +void snmp_ip4_to_oid(const ip4_addr_t *ip, u32_t *oid); +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 +u8_t snmp_oid_to_ip6(const u32_t *oid, ip6_addr_t *ip); +void snmp_ip6_to_oid(const ip6_addr_t *ip, u32_t *oid); +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 || LWIP_IPV6 +u8_t snmp_ip_to_oid(const ip_addr_t *ip, u32_t *oid); +u8_t snmp_ip_port_to_oid(const ip_addr_t *ip, u16_t port, u32_t *oid); + +u8_t snmp_oid_to_ip(const u32_t *oid, u8_t oid_len, ip_addr_t *ip); +u8_t snmp_oid_to_ip_port(const u32_t *oid, u8_t oid_len, ip_addr_t *ip, u16_t *port); +#endif /* LWIP_IPV4 || LWIP_IPV6 */ + +struct netif; +u8_t netif_to_num(const struct netif *netif); + +snmp_err_t snmp_set_test_ok(struct snmp_node_instance* instance, u16_t value_len, void* value); /* generic function which can be used if test is always successful */ + +err_t snmp_decode_bits(const u8_t *buf, u32_t buf_len, u32_t *bit_value); +err_t snmp_decode_truthvalue(const s32_t *asn1_value, u8_t *bool_value); +u8_t snmp_encode_bits(u8_t *buf, u32_t buf_len, u32_t bit_value, u8_t bit_count); +u8_t snmp_encode_truthvalue(s32_t *asn1_value, u32_t bool_value); + +struct snmp_statistics +{ + u32_t inpkts; + u32_t outpkts; + u32_t inbadversions; + u32_t inbadcommunitynames; + u32_t inbadcommunityuses; + u32_t inasnparseerrs; + u32_t intoobigs; + u32_t innosuchnames; + u32_t inbadvalues; + u32_t inreadonlys; + u32_t ingenerrs; + u32_t intotalreqvars; + u32_t intotalsetvars; + u32_t ingetrequests; + u32_t ingetnexts; + u32_t insetrequests; + u32_t ingetresponses; + u32_t intraps; + u32_t outtoobigs; + u32_t outnosuchnames; + u32_t outbadvalues; + u32_t outgenerrs; + u32_t outgetrequests; + u32_t outgetnexts; + u32_t outsetrequests; + u32_t outgetresponses; + u32_t outtraps; +#if LWIP_SNMP_V3 + u32_t unsupportedseclevels; + u32_t notintimewindows; + u32_t unknownusernames; + u32_t unknownengineids; + u32_t wrongdigests; + u32_t decryptionerrors; +#endif +}; + +extern struct snmp_statistics snmp_stats; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SNMP */ + +#endif /* LWIP_HDR_APPS_SNMP_CORE_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h new file mode 100644 index 0000000..2f4a689 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_mib2.h @@ -0,0 +1,78 @@ +/** + * @file + * SNMP MIB2 API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Dirk Ziegelmeier + * + */ +#ifndef LWIP_HDR_APPS_SNMP_MIB2_H +#define LWIP_HDR_APPS_SNMP_MIB2_H + +#include "lwip/apps/snmp_opts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ +#if SNMP_LWIP_MIB2 + +#include "lwip/apps/snmp_core.h" + +extern const struct snmp_mib mib2; + +#if SNMP_USE_NETCONN +#include "lwip/apps/snmp_threadsync.h" +void snmp_mib2_lwip_synchronizer(snmp_threadsync_called_fn fn, void* arg); +extern struct snmp_threadsync_instance snmp_mib2_lwip_locks; +#endif + +#ifndef SNMP_SYSSERVICES +#define SNMP_SYSSERVICES ((1 << 6) | (1 << 3) | ((IP_FORWARD) << 2)) +#endif + +void snmp_mib2_set_sysdescr(const u8_t* str, const u16_t* len); /* read-only be defintion */ +void snmp_mib2_set_syscontact(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize); +void snmp_mib2_set_syscontact_readonly(const u8_t *ocstr, const u16_t *ocstrlen); +void snmp_mib2_set_sysname(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize); +void snmp_mib2_set_sysname_readonly(const u8_t *ocstr, const u16_t *ocstrlen); +void snmp_mib2_set_syslocation(u8_t *ocstr, u16_t *ocstrlen, u16_t bufsize); +void snmp_mib2_set_syslocation_readonly(const u8_t *ocstr, const u16_t *ocstrlen); + +#endif /* SNMP_LWIP_MIB2 */ +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SNMP_MIB2_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h new file mode 100644 index 0000000..c892d22 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_opts.h @@ -0,0 +1,297 @@ +/** + * @file + * SNMP server options list + */ + +/* + * Copyright (c) 2015 Dirk Ziegelmeier + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Dirk Ziegelmeier + * + */ +#ifndef LWIP_HDR_SNMP_OPTS_H +#define LWIP_HDR_SNMP_OPTS_H + +#include "lwip/opt.h" + +/** + * @defgroup snmp_opts Options + * @ingroup snmp + * @{ + */ + +/** + * LWIP_SNMP==1: This enables the lwIP SNMP agent. UDP must be available + * for SNMP transport. + * If you want to use your own SNMP agent, leave this disabled. + * To integrate MIB2 of an external agent, you need to enable + * LWIP_MIB2_CALLBACKS and MIB2_STATS. This will give you the callbacks + * and statistics counters you need to get MIB2 working. + */ +#if !defined LWIP_SNMP || defined __DOXYGEN__ +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_USE_NETCONN: Use netconn API instead of raw API. + * Makes SNMP agent run in a worker thread, so blocking operations + * can be done in MIB calls. + */ +#if !defined SNMP_USE_NETCONN || defined __DOXYGEN__ +#define SNMP_USE_NETCONN 0 +#endif + +/** + * SNMP_USE_RAW: Use raw API. + * SNMP agent does not run in a worker thread, so blocking operations + * should not be done in MIB calls. + */ +#if !defined SNMP_USE_RAW || defined __DOXYGEN__ +#define SNMP_USE_RAW 1 +#endif + +#if SNMP_USE_NETCONN && SNMP_USE_RAW +#error SNMP stack can use only one of the APIs {raw, netconn} +#endif + +#if LWIP_SNMP && !SNMP_USE_NETCONN && !SNMP_USE_RAW +#error SNMP stack needs a receive API and UDP {raw, netconn} +#endif + +#if SNMP_USE_NETCONN +/** + * SNMP_STACK_SIZE: Stack size of SNMP netconn worker thread + */ +#if !defined SNMP_STACK_SIZE || defined __DOXYGEN__ +#define SNMP_STACK_SIZE DEFAULT_THREAD_STACKSIZE +#endif + +/** + * SNMP_THREAD_PRIO: SNMP netconn worker thread priority + */ +#if !defined SNMP_THREAD_PRIO || defined __DOXYGEN__ +#define SNMP_THREAD_PRIO DEFAULT_THREAD_PRIO +#endif +#endif /* SNMP_USE_NETCONN */ + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#if !defined SNMP_TRAP_DESTINATIONS || defined __DOXYGEN__ +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#if !defined SNMP_SAFE_REQUESTS || defined __DOXYGEN__ +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. + */ +#if !defined SNMP_MAX_OCTET_STRING_LEN || defined __DOXYGEN__ +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum number of Sub ID's inside an object identifier. + * Indirectly this also limits the maximum depth of SNMP tree. + */ +#if !defined SNMP_MAX_OBJ_ID_LEN || defined __DOXYGEN__ +#define SNMP_MAX_OBJ_ID_LEN 50 +#endif + +#if !defined SNMP_MAX_VALUE_SIZE || defined __DOXYGEN__ +/** + * The minimum size of a value. + */ +#define SNMP_MIN_VALUE_SIZE (2 * sizeof(u32_t*)) /* size required to store the basic types (8 bytes for counter64) */ +/** + * The maximum size of a value. + */ +#define SNMP_MAX_VALUE_SIZE LWIP_MAX(LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN), sizeof(u32_t)*(SNMP_MAX_OBJ_ID_LEN)), SNMP_MIN_VALUE_SIZE) +#endif + +/** + * The snmp read-access community. Used for write-access and traps, too + * unless SNMP_COMMUNITY_WRITE or SNMP_COMMUNITY_TRAP are enabled, respectively. + */ +#if !defined SNMP_COMMUNITY || defined __DOXYGEN__ +#define SNMP_COMMUNITY "public" +#endif + +/** + * The snmp write-access community. + * Set this community to "" in order to disallow any write access. + */ +#if !defined SNMP_COMMUNITY_WRITE || defined __DOXYGEN__ +#define SNMP_COMMUNITY_WRITE "private" +#endif + +/** + * The snmp community used for sending traps. + */ +#if !defined SNMP_COMMUNITY_TRAP || defined __DOXYGEN__ +#define SNMP_COMMUNITY_TRAP "public" +#endif + +/** + * The maximum length of community string. + * If community names shall be adjusted at runtime via snmp_set_community() calls, + * enter here the possible maximum length (+1 for terminating null character). + */ +#if !defined SNMP_MAX_COMMUNITY_STR_LEN || defined __DOXYGEN__ +#define SNMP_MAX_COMMUNITY_STR_LEN LWIP_MAX(LWIP_MAX(sizeof(SNMP_COMMUNITY), sizeof(SNMP_COMMUNITY_WRITE)), sizeof(SNMP_COMMUNITY_TRAP)) +#endif + +/** + * The OID identifiying the device. This may be the enterprise OID itself or any OID located below it in tree. + */ +#if !defined SNMP_DEVICE_ENTERPRISE_OID || defined __DOXYGEN__ +#define SNMP_LWIP_ENTERPRISE_OID 26381 +/** + * IANA assigned enterprise ID for lwIP is 26381 + * @see http://www.iana.org/assignments/enterprise-numbers + * + * @note this enterprise ID is assigned to the lwIP project, + * all object identifiers living under this ID are assigned + * by the lwIP maintainers! + * @note don't change this define, use snmp_set_device_enterprise_oid() + * + * If you need to create your own private MIB you'll need + * to apply for your own enterprise ID with IANA: + * http://www.iana.org/numbers.html + */ +#define SNMP_DEVICE_ENTERPRISE_OID {1, 3, 6, 1, 4, 1, SNMP_LWIP_ENTERPRISE_OID} +/** + * Length of SNMP_DEVICE_ENTERPRISE_OID + */ +#define SNMP_DEVICE_ENTERPRISE_OID_LEN 7 +#endif + +/** + * SNMP_DEBUG: Enable debugging for SNMP messages. + */ +#if !defined SNMP_DEBUG || defined __DOXYGEN__ +#define SNMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#if !defined SNMP_MIB_DEBUG || defined __DOXYGEN__ +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * Indicates if the MIB2 implementation of LWIP SNMP stack is used. + */ +#if !defined SNMP_LWIP_MIB2 || defined __DOXYGEN__ +#define SNMP_LWIP_MIB2 LWIP_SNMP +#endif + +/** + * Value return for sysDesc field of MIB2. + */ +#if !defined SNMP_LWIP_MIB2_SYSDESC || defined __DOXYGEN__ +#define SNMP_LWIP_MIB2_SYSDESC "lwIP" +#endif + +/** + * Value return for sysName field of MIB2. + * To make sysName field settable, call snmp_mib2_set_sysname() to provide the necessary buffers. + */ +#if !defined SNMP_LWIP_MIB2_SYSNAME || defined __DOXYGEN__ +#define SNMP_LWIP_MIB2_SYSNAME "FQDN-unk" +#endif + +/** + * Value return for sysContact field of MIB2. + * To make sysContact field settable, call snmp_mib2_set_syscontact() to provide the necessary buffers. + */ +#if !defined SNMP_LWIP_MIB2_SYSCONTACT || defined __DOXYGEN__ +#define SNMP_LWIP_MIB2_SYSCONTACT "" +#endif + +/** + * Value return for sysLocation field of MIB2. + * To make sysLocation field settable, call snmp_mib2_set_syslocation() to provide the necessary buffers. + */ +#if !defined SNMP_LWIP_MIB2_SYSLOCATION || defined __DOXYGEN__ +#define SNMP_LWIP_MIB2_SYSLOCATION "" +#endif + +/** + * This value is used to limit the repetitions processed in GetBulk requests (value == 0 means no limitation). + * This may be useful to limit the load for a single request. + * According to SNMP RFC 1905 it is allowed to not return all requested variables from a GetBulk request if system load would be too high. + * so the effect is that the client will do more requests to gather all data. + * For the stack this could be useful in case that SNMP processing is done in TCP/IP thread. In this situation a request with many + * repetitions could block the thread for a longer time. Setting limit here will keep the stack more responsive. + */ +#if !defined SNMP_LWIP_GETBULK_MAX_REPETITIONS || defined __DOXYGEN__ +#define SNMP_LWIP_GETBULK_MAX_REPETITIONS 0 +#endif + +/** + * @} + */ + +/* + ------------------------------------ + ---------- SNMPv3 options ---------- + ------------------------------------ +*/ + +/** + * LWIP_SNMP_V3==1: This enables EXPERIMENTAL SNMPv3 support. LWIP_SNMP must + * also be enabled. + * THIS IS UNDER DEVELOPMENT AND SHOULD NOT BE ENABLED IN PRODUCTS. + */ +#ifndef LWIP_SNMP_V3 +#define LWIP_SNMP_V3 0 +#endif + +#ifndef LWIP_SNMP_V3_MBEDTLS +#define LWIP_SNMP_V3_MBEDTLS LWIP_SNMP_V3 +#endif + +#ifndef LWIP_SNMP_V3_CRYPTO +#define LWIP_SNMP_V3_CRYPTO LWIP_SNMP_V3_MBEDTLS +#endif + +#ifndef LWIP_SNMP_CONFIGURE_VERSIONS +#define LWIP_SNMP_CONFIGURE_VERSIONS 0 +#endif + +#endif /* LWIP_HDR_SNMP_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h new file mode 100644 index 0000000..40a060c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_scalar.h @@ -0,0 +1,113 @@ +/** + * @file + * SNMP server MIB API to implement scalar nodes + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Martin Hentschel + * + */ + +#ifndef LWIP_HDR_APPS_SNMP_SCALAR_H +#define LWIP_HDR_APPS_SNMP_SCALAR_H + +#include "lwip/apps/snmp_opts.h" +#include "lwip/apps/snmp_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +/** basic scalar node */ +struct snmp_scalar_node +{ + /** inherited "base class" members */ + struct snmp_leaf_node node; + u8_t asn1_type; + snmp_access_t access; + node_instance_get_value_method get_value; + node_instance_set_test_method set_test; + node_instance_set_value_method set_value; +}; + + +snmp_err_t snmp_scalar_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); +snmp_err_t snmp_scalar_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); + +#define SNMP_SCALAR_CREATE_NODE(oid, access, asn1_type, get_value_method, set_test_method, set_value_method) \ + {{{ SNMP_NODE_SCALAR, (oid) }, \ + snmp_scalar_get_instance, \ + snmp_scalar_get_next_instance }, \ + (asn1_type), (access), (get_value_method), (set_test_method), (set_value_method) } + +#define SNMP_SCALAR_CREATE_NODE_READONLY(oid, asn1_type, get_value_method) SNMP_SCALAR_CREATE_NODE(oid, SNMP_NODE_INSTANCE_READ_ONLY, asn1_type, get_value_method, NULL, NULL) + +/** scalar array node - a tree node which contains scalars only as children */ +struct snmp_scalar_array_node_def +{ + u32_t oid; + u8_t asn1_type; + snmp_access_t access; +}; + +typedef s16_t (*snmp_scalar_array_get_value_method)(const struct snmp_scalar_array_node_def*, void*); +typedef snmp_err_t (*snmp_scalar_array_set_test_method)(const struct snmp_scalar_array_node_def*, u16_t, void*); +typedef snmp_err_t (*snmp_scalar_array_set_value_method)(const struct snmp_scalar_array_node_def*, u16_t, void*); + +/** basic scalar array node */ +struct snmp_scalar_array_node +{ + /** inherited "base class" members */ + struct snmp_leaf_node node; + u16_t array_node_count; + const struct snmp_scalar_array_node_def* array_nodes; + snmp_scalar_array_get_value_method get_value; + snmp_scalar_array_set_test_method set_test; + snmp_scalar_array_set_value_method set_value; +}; + +snmp_err_t snmp_scalar_array_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); +snmp_err_t snmp_scalar_array_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); + +#define SNMP_SCALAR_CREATE_ARRAY_NODE(oid, array_nodes, get_value_method, set_test_method, set_value_method) \ + {{{ SNMP_NODE_SCALAR_ARRAY, (oid) }, \ + snmp_scalar_array_get_instance, \ + snmp_scalar_array_get_next_instance }, \ + (u16_t)LWIP_ARRAYSIZE(array_nodes), (array_nodes), (get_value_method), (set_test_method), (set_value_method) } + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SNMP_SCALAR_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h new file mode 100644 index 0000000..47409cc --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_framework.h @@ -0,0 +1,32 @@ +/* +Generated by LwipMibCompiler +*/ + +#ifndef LWIP_HDR_APPS_SNMP_FRAMEWORK_MIB_H +#define LWIP_HDR_APPS_SNMP_FRAMEWORK_MIB_H + +#include "lwip/apps/snmp_opts.h" +#if LWIP_SNMP + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "lwip/apps/snmp_core.h" + +extern const struct snmp_obj_id usmNoAuthProtocol; +extern const struct snmp_obj_id usmHMACMD5AuthProtocol; +extern const struct snmp_obj_id usmHMACSHAAuthProtocol; + +extern const struct snmp_obj_id usmNoPrivProtocol; +extern const struct snmp_obj_id usmDESPrivProtocol; +extern const struct snmp_obj_id usmAESPrivProtocol; + +extern const struct snmp_mib snmpframeworkmib; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LWIP_SNMP */ +#endif /* LWIP_HDR_APPS_SNMP_FRAMEWORK_MIB_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h new file mode 100644 index 0000000..88cfcd8 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_snmpv2_usm.h @@ -0,0 +1,24 @@ +/* +Generated by LwipMibCompiler +*/ + +#ifndef LWIP_HDR_APPS_SNMP_USER_BASED_SM_MIB_H +#define LWIP_HDR_APPS_SNMP_USER_BASED_SM_MIB_H + +#include "lwip/apps/snmp_opts.h" +#if LWIP_SNMP + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include "lwip/apps/snmp_core.h" + +extern const struct snmp_mib snmpusmmib; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LWIP_SNMP */ +#endif /* LWIP_HDR_APPS_SNMP_USER_BASED_SM_MIB_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h new file mode 100644 index 0000000..4988b51 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_table.h @@ -0,0 +1,134 @@ +/** + * @file + * SNMP server MIB API to implement table nodes + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Martin Hentschel + * + */ + +#ifndef LWIP_HDR_APPS_SNMP_TABLE_H +#define LWIP_HDR_APPS_SNMP_TABLE_H + +#include "lwip/apps/snmp_opts.h" +#include "lwip/apps/snmp_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +/** default (customizable) read/write table */ +struct snmp_table_col_def +{ + u32_t index; + u8_t asn1_type; + snmp_access_t access; +}; + +/** table node */ +struct snmp_table_node +{ + /** inherited "base class" members */ + struct snmp_leaf_node node; + u16_t column_count; + const struct snmp_table_col_def* columns; + snmp_err_t (*get_cell_instance)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, struct snmp_node_instance* cell_instance); + snmp_err_t (*get_next_cell_instance)(const u32_t* column, struct snmp_obj_id* row_oid, struct snmp_node_instance* cell_instance); + /** returns object value for the given object identifier */ + node_instance_get_value_method get_value; + /** tests length and/or range BEFORE setting */ + node_instance_set_test_method set_test; + /** sets object value, only called when set_test() was successful */ + node_instance_set_value_method set_value; +}; + +snmp_err_t snmp_table_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); +snmp_err_t snmp_table_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); + +#define SNMP_TABLE_CREATE(oid, columns, get_cell_instance_method, get_next_cell_instance_method, get_value_method, set_test_method, set_value_method) \ + {{{ SNMP_NODE_TABLE, (oid) }, \ + snmp_table_get_instance, \ + snmp_table_get_next_instance }, \ + (u16_t)LWIP_ARRAYSIZE(columns), (columns), \ + (get_cell_instance_method), (get_next_cell_instance_method), \ + (get_value_method), (set_test_method), (set_value_method)} + +#define SNMP_TABLE_GET_COLUMN_FROM_OID(oid) ((oid)[1]) /* first array value is (fixed) row entry (fixed to 1) and 2nd value is column, follow3ed by instance */ + + +/** simple read-only table */ +typedef enum { + SNMP_VARIANT_VALUE_TYPE_U32, + SNMP_VARIANT_VALUE_TYPE_S32, + SNMP_VARIANT_VALUE_TYPE_PTR, + SNMP_VARIANT_VALUE_TYPE_CONST_PTR +} snmp_table_column_data_type_t; + +struct snmp_table_simple_col_def +{ + u32_t index; + u8_t asn1_type; + snmp_table_column_data_type_t data_type; /* depending of what union member is used to store the value*/ +}; + +/** simple read-only table node */ +struct snmp_table_simple_node +{ + /* inherited "base class" members */ + struct snmp_leaf_node node; + u16_t column_count; + const struct snmp_table_simple_col_def* columns; + snmp_err_t (*get_cell_value)(const u32_t* column, const u32_t* row_oid, u8_t row_oid_len, union snmp_variant_value* value, u32_t* value_len); + snmp_err_t (*get_next_cell_instance_and_value)(const u32_t* column, struct snmp_obj_id* row_oid, union snmp_variant_value* value, u32_t* value_len); +}; + +snmp_err_t snmp_table_simple_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); +snmp_err_t snmp_table_simple_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); + +#define SNMP_TABLE_CREATE_SIMPLE(oid, columns, get_cell_value_method, get_next_cell_instance_and_value_method) \ + {{{ SNMP_NODE_TABLE, (oid) }, \ + snmp_table_simple_get_instance, \ + snmp_table_simple_get_next_instance }, \ + (u16_t)LWIP_ARRAYSIZE(columns), (columns), (get_cell_value_method), (get_next_cell_instance_and_value_method) } + +s16_t snmp_table_extract_value_from_s32ref(struct snmp_node_instance* instance, void* value); +s16_t snmp_table_extract_value_from_u32ref(struct snmp_node_instance* instance, void* value); +s16_t snmp_table_extract_value_from_refconstptr(struct snmp_node_instance* instance, void* value); + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SNMP_TABLE_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h new file mode 100644 index 0000000..a25dbf2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmp_threadsync.h @@ -0,0 +1,114 @@ +/** + * @file + * SNMP server MIB API to implement thread synchronization + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Dirk Ziegelmeier + * + */ + +#ifndef LWIP_HDR_APPS_SNMP_THREADSYNC_H +#define LWIP_HDR_APPS_SNMP_THREADSYNC_H + +#include "lwip/apps/snmp_opts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_SNMP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/apps/snmp_core.h" +#include "lwip/sys.h" + +typedef void (*snmp_threadsync_called_fn)(void* arg); +typedef void (*snmp_threadsync_synchronizer_fn)(snmp_threadsync_called_fn fn, void* arg); + + +/** Thread sync runtime data. For internal usage only. */ +struct threadsync_data +{ + union { + snmp_err_t err; + s16_t s16; + } retval; + union { + const u32_t *root_oid; + void *value; + } arg1; + union { + u8_t root_oid_len; + u16_t len; + } arg2; + const struct snmp_threadsync_node *threadsync_node; + struct snmp_node_instance proxy_instance; +}; + +/** Thread sync instance. Needed EXCATLY once for every thread to be synced into. */ +struct snmp_threadsync_instance +{ + sys_sem_t sem; + sys_mutex_t sem_usage_mutex; + snmp_threadsync_synchronizer_fn sync_fn; + struct threadsync_data data; +}; + +/** SNMP thread sync proxy leaf node */ +struct snmp_threadsync_node +{ + /* inherited "base class" members */ + struct snmp_leaf_node node; + + const struct snmp_leaf_node *target; + struct snmp_threadsync_instance *instance; +}; + +snmp_err_t snmp_threadsync_get_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); +snmp_err_t snmp_threadsync_get_next_instance(const u32_t *root_oid, u8_t root_oid_len, struct snmp_node_instance* instance); + +/** Create thread sync proxy node */ +#define SNMP_CREATE_THREAD_SYNC_NODE(oid, target_leaf_node, threadsync_instance) \ + {{{ SNMP_NODE_THREADSYNC, (oid) }, \ + snmp_threadsync_get_instance, \ + snmp_threadsync_get_next_instance }, \ + (target_leaf_node), \ + (threadsync_instance) } + +/** Create thread sync instance data */ +void snmp_threadsync_init(struct snmp_threadsync_instance *instance, snmp_threadsync_synchronizer_fn sync_fn); + +#endif /* LWIP_SNMP */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SNMP_THREADSYNC_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h new file mode 100644 index 0000000..e0dda64 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/snmpv3.h @@ -0,0 +1,114 @@ +/** + * @file + * Additional SNMPv3 functionality RFC3414 and RFC3826. + */ + +/* + * Copyright (c) 2016 Elias Oenal. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Elias Oenal + */ + +#ifndef LWIP_HDR_APPS_SNMP_V3_H +#define LWIP_HDR_APPS_SNMP_V3_H + +#include "lwip/apps/snmp_opts.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_SNMP && LWIP_SNMP_V3 + +typedef enum +{ + SNMP_V3_AUTH_ALGO_INVAL = 0, + SNMP_V3_AUTH_ALGO_MD5 = 1, + SNMP_V3_AUTH_ALGO_SHA = 2 +} snmpv3_auth_algo_t; + +typedef enum +{ + SNMP_V3_PRIV_ALGO_INVAL = 0, + SNMP_V3_PRIV_ALGO_DES = 1, + SNMP_V3_PRIV_ALGO_AES = 2 +} snmpv3_priv_algo_t; + +typedef enum +{ + SNMP_V3_USER_STORAGETYPE_OTHER = 1, + SNMP_V3_USER_STORAGETYPE_VOLATILE = 2, + SNMP_V3_USER_STORAGETYPE_NONVOLATILE = 3, + SNMP_V3_USER_STORAGETYPE_PERMANENT = 4, + SNMP_V3_USER_STORAGETYPE_READONLY = 5 +} snmpv3_user_storagetype_t; + +/* + * The following callback functions must be implemented by the application. + * There is a dummy implementation in snmpv3_dummy.c. + */ + +void snmpv3_get_engine_id(const char **id, u8_t *len); +err_t snmpv3_set_engine_id(const char* id, u8_t len); + +u32_t snmpv3_get_engine_boots(void); +void snmpv3_set_engine_boots(u32_t boots); + +u32_t snmpv3_get_engine_time(void); +void snmpv3_reset_engine_time(void); + +err_t snmpv3_get_user(const char* username, snmpv3_auth_algo_t *auth_algo, u8_t *auth_key, snmpv3_priv_algo_t *priv_algo, u8_t *priv_key); +u8_t snmpv3_get_amount_of_users(void); +err_t snmpv3_get_user_storagetype(const char *username, snmpv3_user_storagetype_t *storagetype); +err_t snmpv3_get_username(char *username, u8_t index); + +/* The following functions are provided by the SNMPv3 agent */ + +void snmpv3_engine_id_changed(void); +s32_t snmpv3_get_engine_time_internal(void); + +void snmpv3_password_to_key_md5( + const u8_t *password, /* IN */ + size_t passwordlen, /* IN */ + const u8_t *engineID, /* IN - pointer to snmpEngineID */ + u8_t engineLength, /* IN - length of snmpEngineID */ + u8_t *key); /* OUT - pointer to caller 16-octet buffer */ + +void snmpv3_password_to_key_sha( + const u8_t *password, /* IN */ + size_t passwordlen, /* IN */ + const u8_t *engineID, /* IN - pointer to snmpEngineID */ + u8_t engineLength, /* IN - length of snmpEngineID */ + u8_t *key); /* OUT - pointer to caller 20-octet buffer */ + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SNMP_V3_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h new file mode 100644 index 0000000..3c0f95f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp.h @@ -0,0 +1,80 @@ +/** + * @file + * SNTP client API + */ + +/* + * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Frédéric Bernon, Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_APPS_SNTP_H +#define LWIP_HDR_APPS_SNTP_H + +#include "lwip/apps/sntp_opts.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* SNTP operating modes: default is to poll using unicast. + The mode has to be set before calling sntp_init(). */ +#define SNTP_OPMODE_POLL 0 +#define SNTP_OPMODE_LISTENONLY 1 +void sntp_setoperatingmode(u8_t operating_mode); +u8_t sntp_getoperatingmode(void); + +void sntp_init(void); +void sntp_stop(void); +u8_t sntp_enabled(void); + +void sntp_setserver(u8_t idx, const ip_addr_t *addr); +const ip_addr_t* sntp_getserver(u8_t idx); + +#if SNTP_MONITOR_SERVER_REACHABILITY +u8_t sntp_getreachability(u8_t idx); +#endif /* SNTP_MONITOR_SERVER_REACHABILITY */ + +#if SNTP_SERVER_DNS +void sntp_setservername(u8_t idx, const char *server); +const char *sntp_getservername(u8_t idx); +#endif /* SNTP_SERVER_DNS */ + +#if SNTP_GET_SERVERS_FROM_DHCP +void sntp_servermode_dhcp(int set_servers_from_dhcp); +#else /* SNTP_GET_SERVERS_FROM_DHCP */ +#define sntp_servermode_dhcp(x) +#endif /* SNTP_GET_SERVERS_FROM_DHCP */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_SNTP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h new file mode 100644 index 0000000..ed98040 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/sntp_opts.h @@ -0,0 +1,209 @@ +/** + * @file + * SNTP client options list + */ + +/* + * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Frédéric Bernon, Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_APPS_SNTP_OPTS_H +#define LWIP_HDR_APPS_SNTP_OPTS_H + +#include "lwip/opt.h" +#include "lwip/prot/iana.h" + +/** + * @defgroup sntp_opts Options + * @ingroup sntp + * @{ + */ + +/** SNTP macro to change system time in seconds + * Define SNTP_SET_SYSTEM_TIME_US(sec, us) to set the time in microseconds + * instead of this one if you need the additional precision. Alternatively, + * define SNTP_SET_SYSTEM_TIME_NTP(sec, frac) in order to work with native + * NTP timestamps instead. + */ +#if !defined SNTP_SET_SYSTEM_TIME || defined __DOXYGEN__ +#define SNTP_SET_SYSTEM_TIME(sec) LWIP_UNUSED_ARG(sec) +#endif + +/** The maximum number of SNTP servers that can be set */ +#if !defined SNTP_MAX_SERVERS || defined __DOXYGEN__ +#define SNTP_MAX_SERVERS LWIP_DHCP_MAX_NTP_SERVERS +#endif + +/** Set this to 1 to implement the callback function called by dhcp when + * NTP servers are received. */ +#if !defined SNTP_GET_SERVERS_FROM_DHCP || defined __DOXYGEN__ +#define SNTP_GET_SERVERS_FROM_DHCP LWIP_DHCP_GET_NTP_SRV +#endif + +/** Set this to 1 to support DNS names (or IP address strings) to set sntp servers + * One server address/name can be defined as default if SNTP_SERVER_DNS == 1: + * \#define SNTP_SERVER_ADDRESS "pool.ntp.org" + */ +#if !defined SNTP_SERVER_DNS || defined __DOXYGEN__ +#define SNTP_SERVER_DNS 0 +#endif + +/** + * SNTP_DEBUG: Enable debugging for SNTP. + */ +#if !defined SNTP_DEBUG || defined __DOXYGEN__ +#define SNTP_DEBUG LWIP_DBG_OFF +#endif + +/** SNTP server port */ +#if !defined SNTP_PORT || defined __DOXYGEN__ +#define SNTP_PORT LWIP_IANA_PORT_SNTP +#endif + +/** Sanity check: + * Define this to + * - 0 to turn off sanity checks (default; smaller code) + * - >= 1 to check address and port of the response packet to ensure the + * response comes from the server we sent the request to. + * - >= 2 to check returned Originate Timestamp against Transmit Timestamp + * sent to the server (to ensure response to older request). + * - >= 3 @todo: discard reply if any of the VN, Stratum, or Transmit Timestamp + * fields is 0 or the Mode field is not 4 (unicast) or 5 (broadcast). + * - >= 4 @todo: to check that the Root Delay and Root Dispersion fields are each + * greater than or equal to 0 and less than infinity, where infinity is + * currently a cozy number like one second. This check avoids using a + * server whose synchronization source has expired for a very long time. + */ +#if !defined SNTP_CHECK_RESPONSE || defined __DOXYGEN__ +#define SNTP_CHECK_RESPONSE 0 +#endif + +/** Enable round-trip delay compensation. + * Compensate for the round-trip delay by calculating the clock offset from + * the originate, receive, transmit and destination timestamps, as per RFC. + * + * The calculation requires compiler support for 64-bit integers. Also, either + * SNTP_SET_SYSTEM_TIME_US or SNTP_SET_SYSTEM_TIME_NTP has to be implemented + * for setting the system clock with sub-second precision. Likewise, either + * SNTP_GET_SYSTEM_TIME or SNTP_GET_SYSTEM_TIME_NTP needs to be implemented + * with sub-second precision. + * + * Although not strictly required, it makes sense to combine this option with + * SNTP_CHECK_RESPONSE >= 2 for sanity-checking of the received timestamps. + * Also, in order for the round-trip calculation to work, the difference + * between the local clock and the NTP server clock must not be larger than + * about 34 years. If that limit is exceeded, the implementation will fall back + * to setting the clock without compensation. In order to ensure that the local + * clock is always within the permitted range for compensation, even at first + * try, it may be necessary to store at least the current year in non-volatile + * memory. + */ +#if !defined SNTP_COMP_ROUNDTRIP || defined __DOXYGEN__ +#define SNTP_COMP_ROUNDTRIP 0 +#endif + +/** According to the RFC, this shall be a random delay + * between 1 and 5 minutes (in milliseconds) to prevent load peaks. + * This can be defined to a random generation function, + * which must return the delay in milliseconds as u32_t. + * Turned off by default. + */ +#if !defined SNTP_STARTUP_DELAY || defined __DOXYGEN__ +#ifdef LWIP_RAND +#define SNTP_STARTUP_DELAY 1 +#else +#define SNTP_STARTUP_DELAY 0 +#endif +#endif + +/** If you want the startup delay to be a function, define this + * to a function (including the brackets) and define SNTP_STARTUP_DELAY to 1. + */ +#if !defined SNTP_STARTUP_DELAY_FUNC || defined __DOXYGEN__ +#define SNTP_STARTUP_DELAY_FUNC (LWIP_RAND() % 5000) +#endif + +/** SNTP receive timeout - in milliseconds + * Also used as retry timeout - this shouldn't be too low. + * Default is 15 seconds. Must not be beolw 15 seconds by specification (i.e. 15000) + */ +#if !defined SNTP_RECV_TIMEOUT || defined __DOXYGEN__ +#define SNTP_RECV_TIMEOUT 15000 +#endif + +/** SNTP update delay - in milliseconds + * Default is 1 hour. Must not be beolw 60 seconds by specification (i.e. 60000) + */ +#if !defined SNTP_UPDATE_DELAY || defined __DOXYGEN__ +#define SNTP_UPDATE_DELAY 3600000 +#endif + +/** SNTP macro to get system time, used with SNTP_CHECK_RESPONSE >= 2 + * to send in request and compare in response. Also used for round-trip + * delay compensation if SNTP_COMP_ROUNDTRIP != 0. + * Alternatively, define SNTP_GET_SYSTEM_TIME_NTP(sec, frac) in order to + * work with native NTP timestamps instead. + */ +#if !defined SNTP_GET_SYSTEM_TIME || defined __DOXYGEN__ +#define SNTP_GET_SYSTEM_TIME(sec, us) do { (sec) = 0; (us) = 0; } while(0) +#endif + +/** Default retry timeout (in milliseconds) if the response + * received is invalid. + * This is doubled with each retry until SNTP_RETRY_TIMEOUT_MAX is reached. + */ +#if !defined SNTP_RETRY_TIMEOUT || defined __DOXYGEN__ +#define SNTP_RETRY_TIMEOUT SNTP_RECV_TIMEOUT +#endif + +/** Maximum retry timeout (in milliseconds). */ +#if !defined SNTP_RETRY_TIMEOUT_MAX || defined __DOXYGEN__ +#define SNTP_RETRY_TIMEOUT_MAX (SNTP_RETRY_TIMEOUT * 10) +#endif + +/** Increase retry timeout with every retry sent + * Default is on to conform to RFC. + */ +#if !defined SNTP_RETRY_TIMEOUT_EXP || defined __DOXYGEN__ +#define SNTP_RETRY_TIMEOUT_EXP 1 +#endif + +/** Keep a reachability shift register per server + * Default is on to conform to RFC. + */ +#if !defined SNTP_MONITOR_SERVER_REACHABILITY || defined __DOXYGEN__ +#define SNTP_MONITOR_SERVER_REACHABILITY 1 +#endif + +/** + * @} + */ + +#endif /* LWIP_HDR_APPS_SNTP_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h new file mode 100644 index 0000000..198f632 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_opts.h @@ -0,0 +1,106 @@ +/** + * + * @file tftp_opts.h + * + * @author Logan Gunthorpe + * + * @brief Trivial File Transfer Protocol (RFC 1350) implementation options + * + * Copyright (c) Deltatee Enterprises Ltd. 2013 + * All rights reserved. + * + */ + +/* + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Logan Gunthorpe + * + */ + +#ifndef LWIP_HDR_APPS_TFTP_OPTS_H +#define LWIP_HDR_APPS_TFTP_OPTS_H + +#include "lwip/opt.h" +#include "lwip/prot/iana.h" + +/** + * @defgroup tftp_opts Options + * @ingroup tftp + * @{ + */ + +/** + * Enable TFTP debug messages + */ +#if !defined TFTP_DEBUG || defined __DOXYGEN__ +#define TFTP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TFTP server port + */ +#if !defined TFTP_PORT || defined __DOXYGEN__ +#define TFTP_PORT LWIP_IANA_PORT_TFTP +#endif + +/** + * TFTP timeout + */ +#if !defined TFTP_TIMEOUT_MSECS || defined __DOXYGEN__ +#define TFTP_TIMEOUT_MSECS 10000 +#endif + +/** + * Max. number of retries when a file is read from server + */ +#if !defined TFTP_MAX_RETRIES || defined __DOXYGEN__ +#define TFTP_MAX_RETRIES 5 +#endif + +/** + * TFTP timer cyclic interval + */ +#if !defined TFTP_TIMER_MSECS || defined __DOXYGEN__ +#define TFTP_TIMER_MSECS (TFTP_TIMEOUT_MSECS / 10) +#endif + +/** + * Max. length of TFTP filename + */ +#if !defined TFTP_MAX_FILENAME_LEN || defined __DOXYGEN__ +#define TFTP_MAX_FILENAME_LEN 20 +#endif + +/** + * Max. length of TFTP mode + */ +#if !defined TFTP_MAX_MODE_LEN || defined __DOXYGEN__ +#define TFTP_MAX_MODE_LEN 7 +#endif + +/** + * @} + */ + +#endif /* LWIP_HDR_APPS_TFTP_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h new file mode 100644 index 0000000..0a7fbee --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/apps/tftp_server.h @@ -0,0 +1,95 @@ +/** + * + * @file tftp_server.h + * + * @author Logan Gunthorpe + * + * @brief Trivial File Transfer Protocol (RFC 1350) + * + * Copyright (c) Deltatee Enterprises Ltd. 2013 + * All rights reserved. + * + */ + +/* + * Redistribution and use in source and binary forms, with or without + * modification,are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Author: Logan Gunthorpe + * + */ + +#ifndef LWIP_HDR_APPS_TFTP_SERVER_H +#define LWIP_HDR_APPS_TFTP_SERVER_H + +#include "lwip/apps/tftp_opts.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup tftp + * TFTP context containing callback functions for TFTP transfers + */ +struct tftp_context { + /** + * Open file for read/write. + * @param fname Filename + * @param mode Mode string from TFTP RFC 1350 (netascii, octet, mail) + * @param write Flag indicating read (0) or write (!= 0) access + * @returns File handle supplied to other functions + */ + void* (*open)(const char* fname, const char* mode, u8_t write); + /** + * Close file handle + * @param handle File handle returned by open() + */ + void (*close)(void* handle); + /** + * Read from file + * @param handle File handle returned by open() + * @param buf Target buffer to copy read data to + * @param bytes Number of bytes to copy to buf + * @returns >= 0: Success; < 0: Error + */ + int (*read)(void* handle, void* buf, int bytes); + /** + * Write to file + * @param handle File handle returned by open() + * @param pbuf PBUF adjusted such that payload pointer points + * to the beginning of write data. In other words, + * TFTP headers are stripped off. + * @returns >= 0: Success; < 0: Error + */ + int (*write)(void* handle, struct pbuf* p); +}; + +err_t tftp_init(const struct tftp_context* ctx); +void tftp_cleanup(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_APPS_TFTP_SERVER_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/arch.h b/Middlewares/Third_Party/LwIP/src/include/lwip/arch.h new file mode 100644 index 0000000..58dae33 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/arch.h @@ -0,0 +1,393 @@ +/** + * @file + * Support for different processor and compiler architectures + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_ARCH_H +#define LWIP_HDR_ARCH_H + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 1234 +#endif + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 4321 +#endif + +#include "arch/cc.h" + +/** + * @defgroup compiler_abstraction Compiler/platform abstraction + * @ingroup sys_layer + * All defines related to this section must not be placed in lwipopts.h, + * but in arch/cc.h! + * If the compiler does not provide memset() this file must include a + * definition of it, or include a file which defines it. + * These options cannot be \#defined in lwipopts.h since they are not options + * of lwIP itself, but options of the lwIP port to your system. + * @{ + */ + +/** Define the byte order of the system. + * Needed for conversion of network data to host byte order. + * Allowed values: LITTLE_ENDIAN and BIG_ENDIAN + */ +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +/** Define random number generator function of your system */ +#ifdef __DOXYGEN__ +#define LWIP_RAND() ((u32_t)rand()) +#endif + +/** Platform specific diagnostic output.\n + * Note the default implementation pulls in printf, which may + * in turn pull in a lot of standard libary code. In resource-constrained + * systems, this should be defined to something less resource-consuming. + */ +#ifndef LWIP_PLATFORM_DIAG +#define LWIP_PLATFORM_DIAG(x) do {printf x;} while(0) +#include +#include +#endif + +/** Platform specific assertion handling.\n + * Note the default implementation pulls in printf, fflush and abort, which may + * in turn pull in a lot of standard libary code. In resource-constrained + * systems, this should be defined to something less resource-consuming. + */ +#ifndef LWIP_PLATFORM_ASSERT +#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \ + x, __LINE__, __FILE__); fflush(NULL); abort();} while(0) +#include +#include +#endif + +/** Define this to 1 in arch/cc.h of your port if you do not want to + * include stddef.h header to get size_t. You need to typedef size_t + * by yourself in this case. + */ +#ifndef LWIP_NO_STDDEF_H +#define LWIP_NO_STDDEF_H 0 +#endif + +#if !LWIP_NO_STDDEF_H +#include /* for size_t */ +#endif + +/** Define this to 1 in arch/cc.h of your port if your compiler does not provide + * the stdint.h header. You need to typedef the generic types listed in + * lwip/arch.h yourself in this case (u8_t, u16_t...). + */ +#ifndef LWIP_NO_STDINT_H +#define LWIP_NO_STDINT_H 0 +#endif + +/* Define generic types used in lwIP */ +#if !LWIP_NO_STDINT_H +#include +/* stdint.h is C99 which should also provide support for 64-bit integers */ +#if !defined(LWIP_HAVE_INT64) && defined(UINT64_MAX) +#define LWIP_HAVE_INT64 1 +#endif +typedef uint8_t u8_t; +typedef int8_t s8_t; +typedef uint16_t u16_t; +typedef int16_t s16_t; +typedef uint32_t u32_t; +typedef int32_t s32_t; +#if LWIP_HAVE_INT64 +typedef uint64_t u64_t; +typedef int64_t s64_t; +#endif +typedef uintptr_t mem_ptr_t; +#endif + +/** Define this to 1 in arch/cc.h of your port if your compiler does not provide + * the inttypes.h header. You need to define the format strings listed in + * lwip/arch.h yourself in this case (X8_F, U16_F...). + */ +#ifndef LWIP_NO_INTTYPES_H +#define LWIP_NO_INTTYPES_H 0 +#endif + +/* Define (sn)printf formatters for these lwIP types */ +#if !LWIP_NO_INTTYPES_H +#include +#ifndef X8_F +#define X8_F "02" PRIx8 +#endif +#ifndef U16_F +#define U16_F PRIu16 +#endif +#ifndef S16_F +#define S16_F PRId16 +#endif +#ifndef X16_F +#define X16_F PRIx16 +#endif +#ifndef U32_F +#define U32_F PRIu32 +#endif +#ifndef S32_F +#define S32_F PRId32 +#endif +#ifndef X32_F +#define X32_F PRIx32 +#endif +#ifndef SZT_F +#define SZT_F PRIuPTR +#endif +#endif + +/** Define this to 1 in arch/cc.h of your port if your compiler does not provide + * the limits.h header. You need to define the type limits yourself in this case + * (e.g. INT_MAX, SSIZE_MAX). + */ +#ifndef LWIP_NO_LIMITS_H +#define LWIP_NO_LIMITS_H 0 +#endif + +/* Include limits.h? */ +#if !LWIP_NO_LIMITS_H +#include +#endif + +/* Do we need to define ssize_t? This is a compatibility hack: + * Unfortunately, this type seems to be unavailable on some systems (even if + * sys/types or unistd.h are available). + * Being like that, we define it to 'int' if SSIZE_MAX is not defined. + */ +#ifdef SSIZE_MAX +/* If SSIZE_MAX is defined, unistd.h should provide the type as well */ +#ifndef LWIP_NO_UNISTD_H +#define LWIP_NO_UNISTD_H 0 +#endif +#if !LWIP_NO_UNISTD_H +#include +#endif +#else /* SSIZE_MAX */ +typedef int ssize_t; +#define SSIZE_MAX INT_MAX +#endif /* SSIZE_MAX */ + +/* some maximum values needed in lwip code */ +#define LWIP_UINT32_MAX 0xffffffff + +/** Define this to 1 in arch/cc.h of your port if your compiler does not provide + * the ctype.h header. If ctype.h is available, a few character functions + * are mapped to the appropriate functions (lwip_islower, lwip_isdigit...), if + * not, a private implementation is provided. + */ +#ifndef LWIP_NO_CTYPE_H +#define LWIP_NO_CTYPE_H 0 +#endif + +#if LWIP_NO_CTYPE_H +#define lwip_in_range(c, lo, up) ((u8_t)(c) >= (lo) && (u8_t)(c) <= (up)) +#define lwip_isdigit(c) lwip_in_range((c), '0', '9') +#define lwip_isxdigit(c) (lwip_isdigit(c) || lwip_in_range((c), 'a', 'f') || lwip_in_range((c), 'A', 'F')) +#define lwip_islower(c) lwip_in_range((c), 'a', 'z') +#define lwip_isspace(c) ((c) == ' ' || (c) == '\f' || (c) == '\n' || (c) == '\r' || (c) == '\t' || (c) == '\v') +#define lwip_isupper(c) lwip_in_range((c), 'A', 'Z') +#define lwip_tolower(c) (lwip_isupper(c) ? (c) - 'A' + 'a' : c) +#define lwip_toupper(c) (lwip_islower(c) ? (c) - 'a' + 'A' : c) +#else +#include +#define lwip_isdigit(c) isdigit((unsigned char)(c)) +#define lwip_isxdigit(c) isxdigit((unsigned char)(c)) +#define lwip_islower(c) islower((unsigned char)(c)) +#define lwip_isspace(c) isspace((unsigned char)(c)) +#define lwip_isupper(c) isupper((unsigned char)(c)) +#define lwip_tolower(c) tolower((unsigned char)(c)) +#define lwip_toupper(c) toupper((unsigned char)(c)) +#endif + +/** C++ const_cast(val) equivalent to remove constness from a value (GCC -Wcast-qual) */ +#ifndef LWIP_CONST_CAST +#define LWIP_CONST_CAST(target_type, val) ((target_type)((ptrdiff_t)val)) +#endif + +/** Get rid of alignment cast warnings (GCC -Wcast-align) */ +#ifndef LWIP_ALIGNMENT_CAST +#define LWIP_ALIGNMENT_CAST(target_type, val) LWIP_CONST_CAST(target_type, val) +#endif + +/** Get rid of warnings related to pointer-to-numeric and vice-versa casts, + * e.g. "conversion from 'u8_t' to 'void *' of greater size" + */ +#ifndef LWIP_PTR_NUMERIC_CAST +#define LWIP_PTR_NUMERIC_CAST(target_type, val) LWIP_CONST_CAST(target_type, val) +#endif + +/** Avoid warnings/errors related to implicitly casting away packed attributes by doing a explicit cast */ +#ifndef LWIP_PACKED_CAST +#define LWIP_PACKED_CAST(target_type, val) LWIP_CONST_CAST(target_type, val) +#endif + +/** Allocates a memory buffer of specified size that is of sufficient size to align + * its start address using LWIP_MEM_ALIGN. + * You can declare your own version here e.g. to enforce alignment without adding + * trailing padding bytes (see LWIP_MEM_ALIGN_BUFFER) or your own section placement + * requirements.\n + * e.g. if you use gcc and need 32 bit alignment:\n + * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[size] \_\_attribute\_\_((aligned(4)))\n + * or more portable:\n + * \#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u32_t variable_name[(size + sizeof(u32_t) - 1) / sizeof(u32_t)] + */ +#ifndef LWIP_DECLARE_MEMORY_ALIGNED +#define LWIP_DECLARE_MEMORY_ALIGNED(variable_name, size) u8_t variable_name[LWIP_MEM_ALIGN_BUFFER(size)] +#endif + +/** Calculate memory size for an aligned buffer - returns the next highest + * multiple of MEM_ALIGNMENT (e.g. LWIP_MEM_ALIGN_SIZE(3) and + * LWIP_MEM_ALIGN_SIZE(4) will both yield 4 for MEM_ALIGNMENT == 4). + */ +#ifndef LWIP_MEM_ALIGN_SIZE +#define LWIP_MEM_ALIGN_SIZE(size) (((size) + MEM_ALIGNMENT - 1U) & ~(MEM_ALIGNMENT-1U)) +#endif + +/** Calculate safe memory size for an aligned buffer when using an unaligned + * type as storage. This includes a safety-margin on (MEM_ALIGNMENT - 1) at the + * start (e.g. if buffer is u8_t[] and actual data will be u32_t*) + */ +#ifndef LWIP_MEM_ALIGN_BUFFER +#define LWIP_MEM_ALIGN_BUFFER(size) (((size) + MEM_ALIGNMENT - 1U)) +#endif + +/** Align a memory pointer to the alignment defined by MEM_ALIGNMENT + * so that ADDR % MEM_ALIGNMENT == 0 + */ +#ifndef LWIP_MEM_ALIGN +#define LWIP_MEM_ALIGN(addr) ((void *)(((mem_ptr_t)(addr) + MEM_ALIGNMENT - 1) & ~(mem_ptr_t)(MEM_ALIGNMENT-1))) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** Packed structs support. + * Placed BEFORE declaration of a packed struct.\n + * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n + * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. + */ +#ifndef PACK_STRUCT_BEGIN +#define PACK_STRUCT_BEGIN +#endif /* PACK_STRUCT_BEGIN */ + +/** Packed structs support. + * Placed AFTER declaration of a packed struct.\n + * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n + * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. + */ +#ifndef PACK_STRUCT_END +#define PACK_STRUCT_END +#endif /* PACK_STRUCT_END */ + +/** Packed structs support. + * Placed between end of declaration of a packed struct and trailing semicolon.\n + * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n + * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. + */ +#ifndef PACK_STRUCT_STRUCT +#if defined(__GNUC__) || defined(__clang__) +#define PACK_STRUCT_STRUCT __attribute__((packed)) +#else +#define PACK_STRUCT_STRUCT +#endif +#endif /* PACK_STRUCT_STRUCT */ + +/** Packed structs support. + * Wraps u32_t and u16_t members.\n + * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n + * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. + */ +#ifndef PACK_STRUCT_FIELD +#define PACK_STRUCT_FIELD(x) x +#endif /* PACK_STRUCT_FIELD */ + +/** Packed structs support. + * Wraps u8_t members, where some compilers warn that packing is not necessary.\n + * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n + * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. + */ +#ifndef PACK_STRUCT_FLD_8 +#define PACK_STRUCT_FLD_8(x) PACK_STRUCT_FIELD(x) +#endif /* PACK_STRUCT_FLD_8 */ + +/** Packed structs support. + * Wraps members that are packed structs themselves, where some compilers warn that packing is not necessary.\n + * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n + * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. + */ +#ifndef PACK_STRUCT_FLD_S +#define PACK_STRUCT_FLD_S(x) PACK_STRUCT_FIELD(x) +#endif /* PACK_STRUCT_FLD_S */ + +/** PACK_STRUCT_USE_INCLUDES==1: Packed structs support using \#include files before and after struct to be packed.\n + * The file included BEFORE the struct is "arch/bpstruct.h".\n + * The file included AFTER the struct is "arch/epstruct.h".\n + * This can be used to implement struct packing on MS Visual C compilers, see + * the Win32 port in the lwIP contrib repository for reference. + * For examples of packed struct declarations, see include/lwip/prot/ subfolder.\n + * A port to GCC/clang is included in lwIP, if you use these compilers there is nothing to do here. + */ +#ifdef __DOXYGEN__ +#define PACK_STRUCT_USE_INCLUDES +#endif + +/** Eliminates compiler warning about unused arguments (GCC -Wextra -Wunused). */ +#ifndef LWIP_UNUSED_ARG +#define LWIP_UNUSED_ARG(x) (void)x +#endif /* LWIP_UNUSED_ARG */ + +/** LWIP_PROVIDE_ERRNO==1: Let lwIP provide ERRNO values and the 'errno' variable. + * If this is disabled, cc.h must either define 'errno', include , + * define LWIP_ERRNO_STDINCLUDE to get included or + * define LWIP_ERRNO_INCLUDE to or equivalent. + */ +#if defined __DOXYGEN__ +#define LWIP_PROVIDE_ERRNO +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_ARCH_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h b/Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h new file mode 100644 index 0000000..1d85bcc --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/autoip.h @@ -0,0 +1,99 @@ +/** + * @file + * + * AutoIP Automatic LinkLocal IP Configuration + */ + +/* + * + * Copyright (c) 2007 Dominik Spies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + */ + +#ifndef LWIP_HDR_AUTOIP_H +#define LWIP_HDR_AUTOIP_H + +#include "lwip/opt.h" + +#if LWIP_IPV4 && LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +/* #include "lwip/udp.h" */ +#include "lwip/etharp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** AutoIP Timing */ +#define AUTOIP_TMR_INTERVAL 100 +#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL) + +/** AutoIP state information per netif */ +struct autoip +{ + /** the currently selected, probed, announced or used LL IP-Address */ + ip4_addr_t llipaddr; + /** current AutoIP state machine state */ + u8_t state; + /** sent number of probes or announces, dependent on state */ + u8_t sent_num; + /** ticks to wait, tick is AUTOIP_TMR_INTERVAL long */ + u16_t ttw; + /** ticks until a conflict can be solved by defending */ + u8_t lastconflict; + /** total number of probed/used Link Local IP-Addresses */ + u8_t tried_llipaddr; +}; + + +void autoip_set_struct(struct netif *netif, struct autoip *autoip); +/** Remove a struct autoip previously set to the netif using autoip_set_struct() */ +#define autoip_remove_struct(netif) do { (netif)->autoip = NULL; } while (0) +err_t autoip_start(struct netif *netif); +err_t autoip_stop(struct netif *netif); +void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr); +void autoip_tmr(void); +void autoip_network_changed(struct netif *netif); +u8_t autoip_supplied_address(const struct netif *netif); + +/* for lwIP internal use by ip4.c */ +u8_t autoip_accept_packet(struct netif *netif, const ip4_addr_t *addr); + +#define netif_autoip_data(netif) ((struct autoip*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV4 && LWIP_AUTOIP */ + +#endif /* LWIP_HDR_AUTOIP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/debug.h b/Middlewares/Third_Party/LwIP/src/include/lwip/debug.h new file mode 100644 index 0000000..baa6a40 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/debug.h @@ -0,0 +1,161 @@ +/** + * @file + * Debug messages infrastructure + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_DEBUG_H +#define LWIP_HDR_DEBUG_H + +#include "lwip/arch.h" +#include "lwip/opt.h" + +/** + * @defgroup debugging_levels LWIP_DBG_MIN_LEVEL and LWIP_DBG_TYPES_ON values + * @ingroup lwip_opts_debugmsg + * @{ + */ + +/** @name Debug level (LWIP_DBG_MIN_LEVEL) + * @{ + */ +/** Debug level: ALL messages*/ +#define LWIP_DBG_LEVEL_ALL 0x00 +/** Debug level: Warnings. bad checksums, dropped packets, ... */ +#define LWIP_DBG_LEVEL_WARNING 0x01 +/** Debug level: Serious. memory allocation failures, ... */ +#define LWIP_DBG_LEVEL_SERIOUS 0x02 +/** Debug level: Severe */ +#define LWIP_DBG_LEVEL_SEVERE 0x03 +/** + * @} + */ + +#define LWIP_DBG_MASK_LEVEL 0x03 +/* compatibility define only */ +#define LWIP_DBG_LEVEL_OFF LWIP_DBG_LEVEL_ALL + +/** @name Enable/disable debug messages completely (LWIP_DBG_TYPES_ON) + * @{ + */ +/** flag for LWIP_DEBUGF to enable that debug message */ +#define LWIP_DBG_ON 0x80U +/** flag for LWIP_DEBUGF to disable that debug message */ +#define LWIP_DBG_OFF 0x00U +/** + * @} + */ + +/** @name Debug message types (LWIP_DBG_TYPES_ON) + * @{ + */ +/** flag for LWIP_DEBUGF indicating a tracing message (to follow program flow) */ +#define LWIP_DBG_TRACE 0x40U +/** flag for LWIP_DEBUGF indicating a state debug message (to follow module states) */ +#define LWIP_DBG_STATE 0x20U +/** flag for LWIP_DEBUGF indicating newly added code, not thoroughly tested yet */ +#define LWIP_DBG_FRESH 0x10U +/** flag for LWIP_DEBUGF to halt after printing this debug message */ +#define LWIP_DBG_HALT 0x08U +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup lwip_assertions Assertion handling + * @ingroup lwip_opts_debug + * @{ + */ +/** + * LWIP_NOASSERT: Disable LWIP_ASSERT checks: + * To disable assertions define LWIP_NOASSERT in arch/cc.h. + */ +#ifdef __DOXYGEN__ +#define LWIP_NOASSERT +#undef LWIP_NOASSERT +#endif +/** + * @} + */ + +#ifndef LWIP_NOASSERT +#define LWIP_ASSERT(message, assertion) do { if (!(assertion)) { \ + LWIP_PLATFORM_ASSERT(message); }} while(0) +#else /* LWIP_NOASSERT */ +#define LWIP_ASSERT(message, assertion) +#endif /* LWIP_NOASSERT */ + +#ifndef LWIP_ERROR +#ifndef LWIP_NOASSERT +#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_ASSERT(message) +#elif defined LWIP_DEBUG +#define LWIP_PLATFORM_ERROR(message) LWIP_PLATFORM_DIAG((message)) +#else +#define LWIP_PLATFORM_ERROR(message) +#endif + +/* if "expression" isn't true, then print "message" and execute "handler" expression */ +#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \ + LWIP_PLATFORM_ERROR(message); handler;}} while(0) +#endif /* LWIP_ERROR */ + +/** Enable debug message printing, but only if debug message type is enabled + * AND is of correct type AND is at least LWIP_DBG_LEVEL. + */ +#ifdef __DOXYGEN__ +#define LWIP_DEBUG +#undef LWIP_DEBUG +#endif + +#ifdef LWIP_DEBUG +#define LWIP_DEBUGF(debug, message) do { \ + if ( \ + ((debug) & LWIP_DBG_ON) && \ + ((debug) & LWIP_DBG_TYPES_ON) && \ + ((s16_t)((debug) & LWIP_DBG_MASK_LEVEL) >= LWIP_DBG_MIN_LEVEL)) { \ + LWIP_PLATFORM_DIAG(message); \ + if ((debug) & LWIP_DBG_HALT) { \ + while(1); \ + } \ + } \ + } while(0) + +#else /* LWIP_DEBUG */ +#define LWIP_DEBUGF(debug, message) +#endif /* LWIP_DEBUG */ + +#endif /* LWIP_HDR_DEBUG_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/def.h b/Middlewares/Third_Party/LwIP/src/include/lwip/def.h new file mode 100644 index 0000000..dfb266d --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/def.h @@ -0,0 +1,152 @@ +/** + * @file + * various utility macros + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/** + * @defgroup perf Performance measurement + * @ingroup sys_layer + * All defines related to this section must not be placed in lwipopts.h, + * but in arch/perf.h! + * Measurement calls made throughout lwip, these can be defined to nothing. + * - PERF_START: start measuring something. + * - PERF_STOP(x): stop measuring something, and record the result. + */ + +#ifndef LWIP_HDR_DEF_H +#define LWIP_HDR_DEF_H + +/* arch.h might define NULL already */ +#include "lwip/arch.h" +#include "lwip/opt.h" +#if LWIP_PERF +#include "arch/perf.h" +#else /* LWIP_PERF */ +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ +#endif /* LWIP_PERF */ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LWIP_MAX(x , y) (((x) > (y)) ? (x) : (y)) +#define LWIP_MIN(x , y) (((x) < (y)) ? (x) : (y)) + +/* Get the number of entries in an array ('x' must NOT be a pointer!) */ +#define LWIP_ARRAYSIZE(x) (sizeof(x)/sizeof((x)[0])) + +/** Create u32_t value from bytes */ +#define LWIP_MAKEU32(a,b,c,d) (((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff)) + +#ifndef NULL +#ifdef __cplusplus +#define NULL 0 +#else +#define NULL ((void *)0) +#endif +#endif + +#if BYTE_ORDER == BIG_ENDIAN +#define lwip_htons(x) ((u16_t)(x)) +#define lwip_ntohs(x) ((u16_t)(x)) +#define lwip_htonl(x) ((u32_t)(x)) +#define lwip_ntohl(x) ((u32_t)(x)) +#define PP_HTONS(x) ((u16_t)(x)) +#define PP_NTOHS(x) ((u16_t)(x)) +#define PP_HTONL(x) ((u32_t)(x)) +#define PP_NTOHL(x) ((u32_t)(x)) +#else /* BYTE_ORDER != BIG_ENDIAN */ +#ifndef lwip_htons +u16_t lwip_htons(u16_t x); +#endif +#define lwip_ntohs(x) lwip_htons(x) + +#ifndef lwip_htonl +u32_t lwip_htonl(u32_t x); +#endif +#define lwip_ntohl(x) lwip_htonl(x) + +/* These macros should be calculated by the preprocessor and are used + with compile-time constants only (so that there is no little-endian + overhead at runtime). */ +#define PP_HTONS(x) ((u16_t)((((x) & (u16_t)0x00ffU) << 8) | (((x) & (u16_t)0xff00U) >> 8))) +#define PP_NTOHS(x) PP_HTONS(x) +#define PP_HTONL(x) ((((x) & (u32_t)0x000000ffUL) << 24) | \ + (((x) & (u32_t)0x0000ff00UL) << 8) | \ + (((x) & (u32_t)0x00ff0000UL) >> 8) | \ + (((x) & (u32_t)0xff000000UL) >> 24)) +#define PP_NTOHL(x) PP_HTONL(x) +#endif /* BYTE_ORDER == BIG_ENDIAN */ + +/* Provide usual function names as macros for users, but this can be turned off */ +#ifndef LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS +#define htons(x) lwip_htons(x) +#define ntohs(x) lwip_ntohs(x) +#define htonl(x) lwip_htonl(x) +#define ntohl(x) lwip_ntohl(x) +#endif + +/* Functions that are not available as standard implementations. + * In cc.h, you can #define these to implementations available on + * your platform to save some code bytes if you use these functions + * in your application, too. + */ + +#ifndef lwip_itoa +/* This can be #defined to itoa() or snprintf(result, bufsize, "%d", number) depending on your platform */ +void lwip_itoa(char* result, size_t bufsize, int number); +#endif +#ifndef lwip_strnicmp +/* This can be #defined to strnicmp() or strncasecmp() depending on your platform */ +int lwip_strnicmp(const char* str1, const char* str2, size_t len); +#endif +#ifndef lwip_stricmp +/* This can be #defined to stricmp() or strcasecmp() depending on your platform */ +int lwip_stricmp(const char* str1, const char* str2); +#endif +#ifndef lwip_strnstr +/* This can be #defined to strnstr() depending on your platform */ +char* lwip_strnstr(const char* buffer, const char* token, size_t n); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_DEF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h new file mode 100644 index 0000000..c78aa0b --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp.h @@ -0,0 +1,139 @@ +/** + * @file + * DHCP client API + */ + +/* + * Copyright (c) 2001-2004 Leon Woestenberg + * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * + */ +#ifndef LWIP_HDR_DHCP_H +#define LWIP_HDR_DHCP_H + +#include "lwip/opt.h" + +#if LWIP_DHCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" +#include "lwip/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** period (in seconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_SECS 60 +/** period (in milliseconds) of the application calling dhcp_coarse_tmr() */ +#define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL) +/** period (in milliseconds) of the application calling dhcp_fine_tmr() */ +#define DHCP_FINE_TIMER_MSECS 500 + +#define DHCP_BOOT_FILE_LEN 128U + +/* AutoIP cooperation flags (struct dhcp.autoip_coop_state) */ +typedef enum { + DHCP_AUTOIP_COOP_STATE_OFF = 0, + DHCP_AUTOIP_COOP_STATE_ON = 1 +} dhcp_autoip_coop_state_enum_t; + +struct dhcp +{ + /** transaction identifier of last sent request */ + u32_t xid; + /** track PCB allocation state */ + u8_t pcb_allocated; + /** current DHCP state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; +#if LWIP_DHCP_AUTOIP_COOP + u8_t autoip_coop_state; +#endif + u8_t subnet_mask_given; + + u16_t request_timeout; /* #ticks with period DHCP_FINE_TIMER_SECS for request timeout */ + u16_t t1_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for renewal time */ + u16_t t2_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for rebind time */ + u16_t t1_renew_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next renew try */ + u16_t t2_rebind_time; /* #ticks with period DHCP_COARSE_TIMER_SECS until next rebind try */ + u16_t lease_used; /* #ticks with period DHCP_COARSE_TIMER_SECS since last received DHCP ack */ + u16_t t0_timeout; /* #ticks with period DHCP_COARSE_TIMER_SECS for lease time */ + ip_addr_t server_ip_addr; /* dhcp server address that offered this lease (ip_addr_t because passed to UDP) */ + ip4_addr_t offered_ip_addr; + ip4_addr_t offered_sn_mask; + ip4_addr_t offered_gw_addr; + + u32_t offered_t0_lease; /* lease period (in seconds) */ + u32_t offered_t1_renew; /* recommended renew time (usually 50% of lease period) */ + u32_t offered_t2_rebind; /* recommended rebind time (usually 87.5 of lease period) */ +#if LWIP_DHCP_BOOTP_FILE + ip4_addr_t offered_si_addr; + char boot_file_name[DHCP_BOOT_FILE_LEN]; +#endif /* LWIP_DHCP_BOOTPFILE */ +}; + + +void dhcp_set_struct(struct netif *netif, struct dhcp *dhcp); +/** Remove a struct dhcp previously set to the netif using dhcp_set_struct() */ +#define dhcp_remove_struct(netif) netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, NULL) +void dhcp_cleanup(struct netif *netif); +err_t dhcp_start(struct netif *netif); +err_t dhcp_renew(struct netif *netif); +err_t dhcp_release(struct netif *netif); +void dhcp_stop(struct netif *netif); +void dhcp_release_and_stop(struct netif *netif); +void dhcp_inform(struct netif *netif); +void dhcp_network_changed(struct netif *netif); +#if DHCP_DOES_ARP_CHECK +void dhcp_arp_reply(struct netif *netif, const ip4_addr_t *addr); +#endif +u8_t dhcp_supplied_address(const struct netif *netif); +/* to be called every minute */ +void dhcp_coarse_tmr(void); +/* to be called every half second */ +void dhcp_fine_tmr(void); + +#if LWIP_DHCP_GET_NTP_SRV +/** This function must exist, in other to add offered NTP servers to + * the NTP (or SNTP) engine. + * See LWIP_DHCP_MAX_NTP_SERVERS */ +extern void dhcp_set_ntp_servers(u8_t num_ntp_servers, const ip4_addr_t* ntp_server_addrs); +#endif /* LWIP_DHCP_GET_NTP_SRV */ + +#define netif_dhcp_data(netif) ((struct dhcp*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DHCP */ + +#endif /*LWIP_HDR_DHCP_H*/ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h new file mode 100644 index 0000000..5cc4a01 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/dhcp6.h @@ -0,0 +1,104 @@ +/** + * @file + * + * DHCPv6 client: IPv6 address autoconfiguration as per + * RFC 3315 (stateful DHCPv6) and + * RFC 3736 (stateless DHCPv6). + */ + +/* + * Copyright (c) 2018 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + */ + +#ifndef LWIP_HDR_IP6_DHCP6_H +#define LWIP_HDR_IP6_DHCP6_H + +#include "lwip/opt.h" + +#if LWIP_IPV6_DHCP6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/err.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** period (in milliseconds) of the application calling dhcp6_tmr() */ +#define DHCP6_TIMER_MSECS 500 + +struct dhcp6 +{ + /** transaction identifier of last sent request */ + u32_t xid; + /** track PCB allocation state */ + u8_t pcb_allocated; + /** current DHCPv6 state machine state */ + u8_t state; + /** retries of current request */ + u8_t tries; + /** if request config is triggered while another action is active, this keeps track of it */ + u8_t request_config_pending; + /** #ticks with period DHCP6_TIMER_MSECS for request timeout */ + u16_t request_timeout; +#if LWIP_IPV6_DHCP6_STATEFUL + /* @todo: add more members here to keep track of stateful DHCPv6 data, like lease times */ +#endif /* LWIP_IPV6_DHCP6_STATEFUL */ +}; + +void dhcp6_set_struct(struct netif *netif, struct dhcp6 *dhcp6); +/** Remove a struct dhcp6 previously set to the netif using dhcp6_set_struct() */ +#define dhcp6_remove_struct(netif) netif_set_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, NULL) +void dhcp6_cleanup(struct netif *netif); + +err_t dhcp6_enable_stateful(struct netif *netif); +err_t dhcp6_enable_stateless(struct netif *netif); +void dhcp6_disable(struct netif *netif); + +void dhcp6_tmr(void); + +void dhcp6_nd6_ra_trigger(struct netif *netif, u8_t managed_addr_config, u8_t other_config); + +#if LWIP_DHCP6_GET_NTP_SRV +/** This function must exist, in other to add offered NTP servers to + * the NTP (or SNTP) engine. + * See LWIP_DHCP6_MAX_NTP_SERVERS */ +extern void dhcp6_set_ntp_servers(u8_t num_ntp_servers, const ip_addr_t* ntp_server_addrs); +#endif /* LWIP_DHCP6_GET_NTP_SRV */ + +#define netif_dhcp6_data(netif) ((struct dhcp6*)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6_DHCP6 */ + +#endif /* LWIP_HDR_IP6_DHCP6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/dns.h b/Middlewares/Third_Party/LwIP/src/include/lwip/dns.h new file mode 100644 index 0000000..0913415 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/dns.h @@ -0,0 +1,131 @@ +/** + * @file + * DNS API + */ + +/** + * lwip DNS resolver header file. + + * Author: Jim Pettinato + * April 2007 + + * ported from uIP resolv.c Copyright (c) 2002-2003, Adam Dunkels. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LWIP_HDR_DNS_H +#define LWIP_HDR_DNS_H + +#include "lwip/opt.h" + +#if LWIP_DNS + +#include "lwip/ip_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** DNS timer period */ +#define DNS_TMR_INTERVAL 1000 + +/* DNS resolve types: */ +#define LWIP_DNS_ADDRTYPE_IPV4 0 +#define LWIP_DNS_ADDRTYPE_IPV6 1 +#define LWIP_DNS_ADDRTYPE_IPV4_IPV6 2 /* try to resolve IPv4 first, try IPv6 if IPv4 fails only */ +#define LWIP_DNS_ADDRTYPE_IPV6_IPV4 3 /* try to resolve IPv6 first, try IPv4 if IPv6 fails only */ +#if LWIP_IPV4 && LWIP_IPV6 +#ifndef LWIP_DNS_ADDRTYPE_DEFAULT +#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV4_IPV6 +#endif +#elif LWIP_IPV4 +#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV4 +#else +#define LWIP_DNS_ADDRTYPE_DEFAULT LWIP_DNS_ADDRTYPE_IPV6 +#endif + +#if DNS_LOCAL_HOSTLIST +/** struct used for local host-list */ +struct local_hostlist_entry { + /** static hostname */ + const char *name; + /** static host address in network byteorder */ + ip_addr_t addr; + struct local_hostlist_entry *next; +}; +#define DNS_LOCAL_HOSTLIST_ELEM(name, addr_init) {name, addr_init, NULL} +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#ifndef DNS_LOCAL_HOSTLIST_MAX_NAMELEN +#define DNS_LOCAL_HOSTLIST_MAX_NAMELEN DNS_MAX_NAME_LENGTH +#endif +#define LOCALHOSTLIST_ELEM_SIZE ((sizeof(struct local_hostlist_entry) + DNS_LOCAL_HOSTLIST_MAX_NAMELEN + 1)) +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ +#endif /* DNS_LOCAL_HOSTLIST */ + +#if LWIP_IPV4 +extern const ip_addr_t dns_mquery_v4group; +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 +extern const ip_addr_t dns_mquery_v6group; +#endif /* LWIP_IPV6 */ + +/** Callback which is invoked when a hostname is found. + * A function of this type must be implemented by the application using the DNS resolver. + * @param name pointer to the name that was looked up. + * @param ipaddr pointer to an ip_addr_t containing the IP address of the hostname, + * or NULL if the name could not be found (or on any other error). + * @param callback_arg a user-specified callback argument passed to dns_gethostbyname +*/ +typedef void (*dns_found_callback)(const char *name, const ip_addr_t *ipaddr, void *callback_arg); + +void dns_init(void); +void dns_tmr(void); +void dns_setserver(u8_t numdns, const ip_addr_t *dnsserver); +const ip_addr_t* dns_getserver(u8_t numdns); +err_t dns_gethostbyname(const char *hostname, ip_addr_t *addr, + dns_found_callback found, void *callback_arg); +err_t dns_gethostbyname_addrtype(const char *hostname, ip_addr_t *addr, + dns_found_callback found, void *callback_arg, + u8_t dns_addrtype); + + +#if DNS_LOCAL_HOSTLIST +size_t dns_local_iterate(dns_found_callback iterator_fn, void *iterator_arg); +err_t dns_local_lookup(const char *hostname, ip_addr_t *addr, u8_t dns_addrtype); +#if DNS_LOCAL_HOSTLIST_IS_DYNAMIC +int dns_local_removehost(const char *hostname, const ip_addr_t *addr); +err_t dns_local_addhost(const char *hostname, const ip_addr_t *addr); +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ +#endif /* DNS_LOCAL_HOSTLIST */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DNS */ + +#endif /* LWIP_HDR_DNS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/err.h b/Middlewares/Third_Party/LwIP/src/include/lwip/err.h new file mode 100644 index 0000000..887d9b3 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/err.h @@ -0,0 +1,117 @@ +/** + * @file + * lwIP Error codes + */ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_ERR_H +#define LWIP_HDR_ERR_H + +#include "lwip/opt.h" +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup infrastructure_errors Error codes + * @ingroup infrastructure + * @{ + */ + +/** Definitions for error constants. */ +typedef enum { +/** No error, everything OK. */ + ERR_OK = 0, +/** Out of memory error. */ + ERR_MEM = -1, +/** Buffer error. */ + ERR_BUF = -2, +/** Timeout. */ + ERR_TIMEOUT = -3, +/** Routing problem. */ + ERR_RTE = -4, +/** Operation in progress */ + ERR_INPROGRESS = -5, +/** Illegal value. */ + ERR_VAL = -6, +/** Operation would block. */ + ERR_WOULDBLOCK = -7, +/** Address in use. */ + ERR_USE = -8, +/** Already connecting. */ + ERR_ALREADY = -9, +/** Conn already established.*/ + ERR_ISCONN = -10, +/** Not connected. */ + ERR_CONN = -11, +/** Low-level netif error */ + ERR_IF = -12, + +/** Connection aborted. */ + ERR_ABRT = -13, +/** Connection reset. */ + ERR_RST = -14, +/** Connection closed. */ + ERR_CLSD = -15, +/** Illegal argument. */ + ERR_ARG = -16 +} err_enum_t; + +/** Define LWIP_ERR_T in cc.h if you want to use + * a different type for your platform (must be signed). */ +#ifdef LWIP_ERR_T +typedef LWIP_ERR_T err_t; +#else /* LWIP_ERR_T */ +typedef s8_t err_t; +#endif /* LWIP_ERR_T*/ + +/** + * @} + */ + +#ifdef LWIP_DEBUG +extern const char *lwip_strerr(err_t err); +#else +#define lwip_strerr(x) "" +#endif /* LWIP_DEBUG */ + +#if !NO_SYS +int err_to_errno(err_t err); +#endif /* !NO_SYS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_ERR_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/errno.h b/Middlewares/Third_Party/LwIP/src/include/lwip/errno.h new file mode 100644 index 0000000..48d6b53 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/errno.h @@ -0,0 +1,198 @@ +/** + * @file + * Posix Errno defines + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_ERRNO_H +#define LWIP_HDR_ERRNO_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef LWIP_PROVIDE_ERRNO + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Arg list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ +#define ENOSYS 38 /* Function not implemented */ +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale NFS file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ + +#ifndef errno +extern int errno; +#endif + +#else /* LWIP_PROVIDE_ERRNO */ + +/* Define LWIP_ERRNO_STDINCLUDE if you want to include here */ +#ifdef LWIP_ERRNO_STDINCLUDE +#include +#else /* LWIP_ERRNO_STDINCLUDE */ +/* Define LWIP_ERRNO_INCLUDE to an equivalent of to include the error defines here */ +#ifdef LWIP_ERRNO_INCLUDE +#include LWIP_ERRNO_INCLUDE +#endif /* LWIP_ERRNO_INCLUDE */ +#endif /* LWIP_ERRNO_STDINCLUDE */ + +#endif /* LWIP_PROVIDE_ERRNO */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_ERRNO_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h new file mode 100644 index 0000000..2036b24 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/etharp.h @@ -0,0 +1,105 @@ +/** + * @file + * Ethernet output function - handles OUTGOING ethernet level traffic, implements + * ARP resolving. + * To be used in most low-level netif implementations + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef LWIP_HDR_NETIF_ETHARP_H +#define LWIP_HDR_NETIF_ETHARP_H + +#include "lwip/opt.h" + +#if LWIP_ARP || LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip4_addr.h" +#include "lwip/netif.h" +#include "lwip/ip4.h" +#include "lwip/prot/ethernet.h" + +#if LWIP_IPV4 && LWIP_ARP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/prot/etharp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** 1 seconds period */ +#define ARP_TMR_INTERVAL 1000 + +#if ARP_QUEUEING +/** struct for queueing outgoing packets for unknown address + * defined here to be accessed by memp.h + */ +struct etharp_q_entry { + struct etharp_q_entry *next; + struct pbuf *p; +}; +#endif /* ARP_QUEUEING */ + +#define etharp_init() /* Compatibility define, no init needed. */ +void etharp_tmr(void); +ssize_t etharp_find_addr(struct netif *netif, const ip4_addr_t *ipaddr, + struct eth_addr **eth_ret, const ip4_addr_t **ip_ret); +int etharp_get_entry(size_t i, ip4_addr_t **ipaddr, struct netif **netif, struct eth_addr **eth_ret); +err_t etharp_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr); +err_t etharp_query(struct netif *netif, const ip4_addr_t *ipaddr, struct pbuf *q); +err_t etharp_request(struct netif *netif, const ip4_addr_t *ipaddr); +/** For Ethernet network interfaces, we might want to send "gratuitous ARP"; + * this is an ARP packet sent by a node in order to spontaneously cause other + * nodes to update an entry in their ARP cache. + * From RFC 3220 "IP Mobility Support for IPv4" section 4.6. */ +#define etharp_gratuitous(netif) etharp_request((netif), netif_ip4_addr(netif)) +void etharp_cleanup_netif(struct netif *netif); + +#if ETHARP_SUPPORT_STATIC_ENTRIES +err_t etharp_add_static_entry(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr); +err_t etharp_remove_static_entry(const ip4_addr_t *ipaddr); +#endif /* ETHARP_SUPPORT_STATIC_ENTRIES */ + +void etharp_input(struct pbuf *p, struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV4 && LWIP_ARP */ +#endif /* LWIP_ARP || LWIP_ETHERNET */ + +#endif /* LWIP_HDR_NETIF_ETHARP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h new file mode 100644 index 0000000..5e88dff --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ethip6.h @@ -0,0 +1,68 @@ +/** + * @file + * + * Ethernet output for IPv6. Uses ND tables for link-layer addressing. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#ifndef LWIP_HDR_ETHIP6_H +#define LWIP_HDR_ETHIP6_H + +#include "lwip/opt.h" + +#if LWIP_IPV6 && LWIP_ETHERNET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/netif.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +err_t ethip6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 && LWIP_ETHERNET */ + +#endif /* LWIP_HDR_ETHIP6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h new file mode 100644 index 0000000..f5a31fd --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/icmp.h @@ -0,0 +1,110 @@ +/** + * @file + * ICMP API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_ICMP_H +#define LWIP_HDR_ICMP_H + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/prot/icmp.h" + +#if LWIP_IPV6 && LWIP_ICMP6 +#include "lwip/icmp6.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** ICMP destination unreachable codes */ +enum icmp_dur_type { + /** net unreachable */ + ICMP_DUR_NET = 0, + /** host unreachable */ + ICMP_DUR_HOST = 1, + /** protocol unreachable */ + ICMP_DUR_PROTO = 2, + /** port unreachable */ + ICMP_DUR_PORT = 3, + /** fragmentation needed and DF set */ + ICMP_DUR_FRAG = 4, + /** source route failed */ + ICMP_DUR_SR = 5 +}; + +/** ICMP time exceeded codes */ +enum icmp_te_type { + /** time to live exceeded in transit */ + ICMP_TE_TTL = 0, + /** fragment reassembly time exceeded */ + ICMP_TE_FRAG = 1 +}; + +#if LWIP_IPV4 && LWIP_ICMP /* don't build if not configured for use in lwipopts.h */ + +void icmp_input(struct pbuf *p, struct netif *inp); +void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t); +void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t); + +#endif /* LWIP_IPV4 && LWIP_ICMP */ + +#if LWIP_IPV4 && LWIP_IPV6 +#if LWIP_ICMP && LWIP_ICMP6 +#define icmp_port_unreach(isipv6, pbuf) ((isipv6) ? \ + icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) : \ + icmp_dest_unreach(pbuf, ICMP_DUR_PORT)) +#elif LWIP_ICMP +#define icmp_port_unreach(isipv6, pbuf) do{ if(!(isipv6)) { icmp_dest_unreach(pbuf, ICMP_DUR_PORT);}}while(0) +#elif LWIP_ICMP6 +#define icmp_port_unreach(isipv6, pbuf) do{ if(isipv6) { icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT);}}while(0) +#else +#define icmp_port_unreach(isipv6, pbuf) +#endif +#elif LWIP_IPV6 && LWIP_ICMP6 +#define icmp_port_unreach(isipv6, pbuf) icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) +#elif LWIP_IPV4 && LWIP_ICMP +#define icmp_port_unreach(isipv6, pbuf) icmp_dest_unreach(pbuf, ICMP_DUR_PORT) +#else /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) */ +#define icmp_port_unreach(isipv6, pbuf) +#endif /* (LWIP_IPV6 && LWIP_ICMP6) || (LWIP_IPV4 && LWIP_ICMP) LWIP_IPV4*/ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_ICMP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h new file mode 100644 index 0000000..0ccb789 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/icmp6.h @@ -0,0 +1,72 @@ +/** + * @file + * + * IPv6 version of ICMP, as per RFC 4443. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ +#ifndef LWIP_HDR_ICMP6_H +#define LWIP_HDR_ICMP6_H + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip6_addr.h" +#include "lwip/netif.h" +#include "lwip/prot/icmp6.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_ICMP6 && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +void icmp6_input(struct pbuf *p, struct netif *inp); +void icmp6_dest_unreach(struct pbuf *p, enum icmp6_dur_code c); +void icmp6_packet_too_big(struct pbuf *p, u32_t mtu); +void icmp6_time_exceeded(struct pbuf *p, enum icmp6_te_code c); +void icmp6_time_exceeded_with_addrs(struct pbuf *p, enum icmp6_te_code c, + const ip6_addr_t *src_addr, const ip6_addr_t *dest_addr); +void icmp6_param_problem(struct pbuf *p, enum icmp6_pp_code c, const void *pointer); + +#endif /* LWIP_ICMP6 && LWIP_IPV6 */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* LWIP_HDR_ICMP6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h b/Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h new file mode 100644 index 0000000..39017ab --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/if_api.h @@ -0,0 +1,68 @@ +/** + * @file + * Interface Identification APIs from: + * RFC 3493: Basic Socket Interface Extensions for IPv6 + * Section 4: Interface Identification + */ + +/* + * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Joel Cunningham + * + */ +#ifndef LWIP_HDR_IF_H +#define LWIP_HDR_IF_H + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IF_NAMESIZE NETIF_NAMESIZE + +char * lwip_if_indextoname(unsigned int ifindex, char *ifname); +unsigned int lwip_if_nametoindex(const char *ifname); + +#if LWIP_COMPAT_SOCKETS +#define if_indextoname(ifindex, ifname) lwip_if_indextoname(ifindex,ifname) +#define if_nametoindex(ifname) lwip_if_nametoindex(ifname) +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SOCKET */ + +#endif /* LWIP_HDR_IF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h new file mode 100644 index 0000000..ffd80e6 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/igmp.h @@ -0,0 +1,115 @@ +/** + * @file + * IGMP API + */ + +/* + * Copyright (c) 2002 CITEL Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of CITEL Technologies Ltd nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY CITEL TECHNOLOGIES AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL CITEL TECHNOLOGIES OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is a contribution to the lwIP TCP/IP stack. + * The Swedish Institute of Computer Science and Adam Dunkels + * are specifically granted permission to redistribute this + * source code. +*/ + +#ifndef LWIP_HDR_IGMP_H +#define LWIP_HDR_IGMP_H + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" + +#if LWIP_IPV4 && LWIP_IGMP /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* IGMP timer */ +#define IGMP_TMR_INTERVAL 100 /* Milliseconds */ +#define IGMP_V1_DELAYING_MEMBER_TMR (1000/IGMP_TMR_INTERVAL) +#define IGMP_JOIN_DELAYING_MEMBER_TMR (500 /IGMP_TMR_INTERVAL) + +/* Compatibility defines (don't use for new code) */ +#define IGMP_DEL_MAC_FILTER NETIF_DEL_MAC_FILTER +#define IGMP_ADD_MAC_FILTER NETIF_ADD_MAC_FILTER + +/** + * igmp group structure - there is + * a list of groups for each interface + * these should really be linked from the interface, but + * if we keep them separate we will not affect the lwip original code + * too much + * + * There will be a group for the all systems group address but this + * will not run the state machine as it is used to kick off reports + * from all the other groups + */ +struct igmp_group { + /** next link */ + struct igmp_group *next; + /** multicast address */ + ip4_addr_t group_address; + /** signifies we were the last person to report */ + u8_t last_reporter_flag; + /** current state of the group */ + u8_t group_state; + /** timer for reporting, negative is OFF */ + u16_t timer; + /** counter of simultaneous uses */ + u8_t use; +}; + +/* Prototypes */ +void igmp_init(void); +err_t igmp_start(struct netif *netif); +err_t igmp_stop(struct netif *netif); +void igmp_report_groups(struct netif *netif); +struct igmp_group *igmp_lookfor_group(struct netif *ifp, const ip4_addr_t *addr); +void igmp_input(struct pbuf *p, struct netif *inp, const ip4_addr_t *dest); +err_t igmp_joingroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr); +err_t igmp_joingroup_netif(struct netif *netif, const ip4_addr_t *groupaddr); +err_t igmp_leavegroup(const ip4_addr_t *ifaddr, const ip4_addr_t *groupaddr); +err_t igmp_leavegroup_netif(struct netif *netif, const ip4_addr_t *groupaddr); +void igmp_tmr(void); + +/** @ingroup igmp + * Get list head of IGMP groups for netif. + * Note: The allsystems group IP is contained in the list as first entry. + * @see @ref netif_set_igmp_mac_filter() + */ +#define netif_igmp_data(netif) ((struct igmp_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_IGMP)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV4 && LWIP_IGMP */ + +#endif /* LWIP_HDR_IGMP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/inet.h b/Middlewares/Third_Party/LwIP/src/include/lwip/inet.h new file mode 100644 index 0000000..2982a0f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/inet.h @@ -0,0 +1,169 @@ +/** + * @file + * This file (together with sockets.h) aims to provide structs and functions from + * - arpa/inet.h + * - netinet/in.h + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_INET_H +#define LWIP_HDR_INET_H + +#include "lwip/opt.h" +#include "lwip/def.h" +#include "lwip/ip_addr.h" +#include "lwip/ip6_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* If your port already typedef's in_addr_t, define IN_ADDR_T_DEFINED + to prevent this code from redefining it. */ +#if !defined(in_addr_t) && !defined(IN_ADDR_T_DEFINED) +typedef u32_t in_addr_t; +#endif + +struct in_addr { + in_addr_t s_addr; +}; + +struct in6_addr { + union { + u32_t u32_addr[4]; + u8_t u8_addr[16]; + } un; +#define s6_addr un.u8_addr +}; + +/** 255.255.255.255 */ +#define INADDR_NONE IPADDR_NONE +/** 127.0.0.1 */ +#define INADDR_LOOPBACK IPADDR_LOOPBACK +/** 0.0.0.0 */ +#define INADDR_ANY IPADDR_ANY +/** 255.255.255.255 */ +#define INADDR_BROADCAST IPADDR_BROADCAST + +/** This macro can be used to initialize a variable of type struct in6_addr + to the IPv6 wildcard address. */ +#define IN6ADDR_ANY_INIT {{{0,0,0,0}}} +/** This macro can be used to initialize a variable of type struct in6_addr + to the IPv6 loopback address. */ +#define IN6ADDR_LOOPBACK_INIT {{{0,0,0,PP_HTONL(1)}}} +/** This variable is initialized by the system to contain the wildcard IPv6 address. */ +extern const struct in6_addr in6addr_any; + +/* Definitions of the bits in an (IPv4) Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ +#define IN_CLASSA(a) IP_CLASSA(a) +#define IN_CLASSA_NET IP_CLASSA_NET +#define IN_CLASSA_NSHIFT IP_CLASSA_NSHIFT +#define IN_CLASSA_HOST IP_CLASSA_HOST +#define IN_CLASSA_MAX IP_CLASSA_MAX + +#define IN_CLASSB(b) IP_CLASSB(b) +#define IN_CLASSB_NET IP_CLASSB_NET +#define IN_CLASSB_NSHIFT IP_CLASSB_NSHIFT +#define IN_CLASSB_HOST IP_CLASSB_HOST +#define IN_CLASSB_MAX IP_CLASSB_MAX + +#define IN_CLASSC(c) IP_CLASSC(c) +#define IN_CLASSC_NET IP_CLASSC_NET +#define IN_CLASSC_NSHIFT IP_CLASSC_NSHIFT +#define IN_CLASSC_HOST IP_CLASSC_HOST +#define IN_CLASSC_MAX IP_CLASSC_MAX + +#define IN_CLASSD(d) IP_CLASSD(d) +#define IN_CLASSD_NET IP_CLASSD_NET /* These ones aren't really */ +#define IN_CLASSD_NSHIFT IP_CLASSD_NSHIFT /* net and host fields, but */ +#define IN_CLASSD_HOST IP_CLASSD_HOST /* routing needn't know. */ +#define IN_CLASSD_MAX IP_CLASSD_MAX + +#define IN_MULTICAST(a) IP_MULTICAST(a) + +#define IN_EXPERIMENTAL(a) IP_EXPERIMENTAL(a) +#define IN_BADCLASS(a) IP_BADCLASS(a) + +#define IN_LOOPBACKNET IP_LOOPBACKNET + + +#ifndef INET_ADDRSTRLEN +#define INET_ADDRSTRLEN IP4ADDR_STRLEN_MAX +#endif +#if LWIP_IPV6 +#ifndef INET6_ADDRSTRLEN +#define INET6_ADDRSTRLEN IP6ADDR_STRLEN_MAX +#endif +#endif + +#if LWIP_IPV4 + +#define inet_addr_from_ip4addr(target_inaddr, source_ipaddr) ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr)) +#define inet_addr_to_ip4addr(target_ipaddr, source_inaddr) (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr)) + +/* directly map this to the lwip internal functions */ +#define inet_addr(cp) ipaddr_addr(cp) +#define inet_aton(cp, addr) ip4addr_aton(cp, (ip4_addr_t*)addr) +#define inet_ntoa(addr) ip4addr_ntoa((const ip4_addr_t*)&(addr)) +#define inet_ntoa_r(addr, buf, buflen) ip4addr_ntoa_r((const ip4_addr_t*)&(addr), buf, buflen) + +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +#define inet6_addr_from_ip6addr(target_in6addr, source_ip6addr) {(target_in6addr)->un.u32_addr[0] = (source_ip6addr)->addr[0]; \ + (target_in6addr)->un.u32_addr[1] = (source_ip6addr)->addr[1]; \ + (target_in6addr)->un.u32_addr[2] = (source_ip6addr)->addr[2]; \ + (target_in6addr)->un.u32_addr[3] = (source_ip6addr)->addr[3];} +#define inet6_addr_to_ip6addr(target_ip6addr, source_in6addr) {(target_ip6addr)->addr[0] = (source_in6addr)->un.u32_addr[0]; \ + (target_ip6addr)->addr[1] = (source_in6addr)->un.u32_addr[1]; \ + (target_ip6addr)->addr[2] = (source_in6addr)->un.u32_addr[2]; \ + (target_ip6addr)->addr[3] = (source_in6addr)->un.u32_addr[3]; \ + ip6_addr_clear_zone(target_ip6addr);} + +/* directly map this to the lwip internal functions */ +#define inet6_aton(cp, addr) ip6addr_aton(cp, (ip6_addr_t*)addr) +#define inet6_ntoa(addr) ip6addr_ntoa((const ip6_addr_t*)&(addr)) +#define inet6_ntoa_r(addr, buf, buflen) ip6addr_ntoa_r((const ip6_addr_t*)&(addr), buf, buflen) + +#endif /* LWIP_IPV6 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_INET_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h b/Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h new file mode 100644 index 0000000..76893ef --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/inet_chksum.h @@ -0,0 +1,105 @@ +/** + * @file + * IP checksum calculation functions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_INET_CHKSUM_H +#define LWIP_HDR_INET_CHKSUM_H + +#include "lwip/opt.h" + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" + +/** Swap the bytes in an u16_t: much like lwip_htons() for little-endian */ +#ifndef SWAP_BYTES_IN_WORD +#define SWAP_BYTES_IN_WORD(w) (((w) & 0xff) << 8) | (((w) & 0xff00) >> 8) +#endif /* SWAP_BYTES_IN_WORD */ + +/** Split an u32_t in two u16_ts and add them up */ +#ifndef FOLD_U32T +#define FOLD_U32T(u) ((u32_t)(((u) >> 16) + ((u) & 0x0000ffffUL))) +#endif + +#if LWIP_CHECKSUM_ON_COPY +/** Function-like macro: same as MEMCPY but returns the checksum of copied data + as u16_t */ +# ifndef LWIP_CHKSUM_COPY +# define LWIP_CHKSUM_COPY(dst, src, len) lwip_chksum_copy(dst, src, len) +# ifndef LWIP_CHKSUM_COPY_ALGORITHM +# define LWIP_CHKSUM_COPY_ALGORITHM 1 +# endif /* LWIP_CHKSUM_COPY_ALGORITHM */ +# else /* LWIP_CHKSUM_COPY */ +# define LWIP_CHKSUM_COPY_ALGORITHM 0 +# endif /* LWIP_CHKSUM_COPY */ +#else /* LWIP_CHECKSUM_ON_COPY */ +# define LWIP_CHKSUM_COPY_ALGORITHM 0 +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#ifdef __cplusplus +extern "C" { +#endif + +u16_t inet_chksum(const void *dataptr, u16_t len); +u16_t inet_chksum_pbuf(struct pbuf *p); +#if LWIP_CHKSUM_COPY_ALGORITHM +u16_t lwip_chksum_copy(void *dst, const void *src, u16_t len); +#endif /* LWIP_CHKSUM_COPY_ALGORITHM */ + +#if LWIP_IPV4 +u16_t inet_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, + const ip4_addr_t *src, const ip4_addr_t *dest); +u16_t inet_chksum_pseudo_partial(struct pbuf *p, u8_t proto, + u16_t proto_len, u16_t chksum_len, const ip4_addr_t *src, const ip4_addr_t *dest); +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +u16_t ip6_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, + const ip6_addr_t *src, const ip6_addr_t *dest); +u16_t ip6_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, + u16_t chksum_len, const ip6_addr_t *src, const ip6_addr_t *dest); +#endif /* LWIP_IPV6 */ + + +u16_t ip_chksum_pseudo(struct pbuf *p, u8_t proto, u16_t proto_len, + const ip_addr_t *src, const ip_addr_t *dest); +u16_t ip_chksum_pseudo_partial(struct pbuf *p, u8_t proto, u16_t proto_len, + u16_t chksum_len, const ip_addr_t *src, const ip_addr_t *dest); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_INET_H */ + diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/init.h b/Middlewares/Third_Party/LwIP/src/include/lwip/init.h new file mode 100644 index 0000000..a149be1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/init.h @@ -0,0 +1,100 @@ +/** + * @file + * lwIP initialization API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_INIT_H +#define LWIP_HDR_INIT_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup lwip_version Version + * @ingroup lwip + * @{ + */ + +/** X.x.x: Major version of the stack */ +#define LWIP_VERSION_MAJOR 2 +/** x.X.x: Minor version of the stack */ +#define LWIP_VERSION_MINOR 1 +/** x.x.X: Revision of the stack */ +#define LWIP_VERSION_REVISION 2 +/** For release candidates, this is set to 1..254 + * For official releases, this is set to 255 (LWIP_RC_RELEASE) + * For development versions (Git), this is set to 0 (LWIP_RC_DEVELOPMENT) */ +#define LWIP_VERSION_RC LWIP_RC_RELEASE + +/** LWIP_VERSION_RC is set to LWIP_RC_RELEASE for official releases */ +#define LWIP_RC_RELEASE 255 +/** LWIP_VERSION_RC is set to LWIP_RC_DEVELOPMENT for Git versions */ +#define LWIP_RC_DEVELOPMENT 0 + +#define LWIP_VERSION_IS_RELEASE (LWIP_VERSION_RC == LWIP_RC_RELEASE) +#define LWIP_VERSION_IS_DEVELOPMENT (LWIP_VERSION_RC == LWIP_RC_DEVELOPMENT) +#define LWIP_VERSION_IS_RC ((LWIP_VERSION_RC != LWIP_RC_RELEASE) && (LWIP_VERSION_RC != LWIP_RC_DEVELOPMENT)) + +/* Some helper defines to get a version string */ +#define LWIP_VERSTR2(x) #x +#define LWIP_VERSTR(x) LWIP_VERSTR2(x) +#if LWIP_VERSION_IS_RELEASE +#define LWIP_VERSION_STRING_SUFFIX "" +#elif LWIP_VERSION_IS_DEVELOPMENT +#define LWIP_VERSION_STRING_SUFFIX "d" +#else +#define LWIP_VERSION_STRING_SUFFIX "rc" LWIP_VERSTR(LWIP_VERSION_RC) +#endif + +/** Provides the version of the stack */ +#define LWIP_VERSION ((LWIP_VERSION_MAJOR) << 24 | (LWIP_VERSION_MINOR) << 16 | \ + (LWIP_VERSION_REVISION) << 8 | (LWIP_VERSION_RC)) +/** Provides the version of the stack as string */ +#define LWIP_VERSION_STRING LWIP_VERSTR(LWIP_VERSION_MAJOR) "." LWIP_VERSTR(LWIP_VERSION_MINOR) "." LWIP_VERSTR(LWIP_VERSION_REVISION) LWIP_VERSION_STRING_SUFFIX + +/** + * @} + */ + +/* Modules initialization */ +void lwip_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_INIT_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip.h new file mode 100644 index 0000000..653c3b2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip.h @@ -0,0 +1,330 @@ +/** + * @file + * IP API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_IP_H +#define LWIP_HDR_IP_H + +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/netif.h" +#include "lwip/ip4.h" +#include "lwip/ip6.h" +#include "lwip/prot/ip.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* This is passed as the destination address to ip_output_if (not + to ip_output), meaning that an IP header already is constructed + in the pbuf. This is used when TCP retransmits. */ +#define LWIP_IP_HDRINCL NULL + +/** pbufs passed to IP must have a ref-count of 1 as their payload pointer + gets altered as the packet is passed down the stack */ +#ifndef LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX +#define LWIP_IP_CHECK_PBUF_REF_COUNT_FOR_TX(p) LWIP_ASSERT("p->ref == 1", (p)->ref == 1) +#endif + +#if LWIP_NETIF_USE_HINTS +#define IP_PCB_NETIFHINT ;struct netif_hint netif_hints +#else /* LWIP_NETIF_USE_HINTS */ +#define IP_PCB_NETIFHINT +#endif /* LWIP_NETIF_USE_HINTS */ + +/** This is the common part of all PCB types. It needs to be at the + beginning of a PCB type definition. It is located here so that + changes to this common part are made in one location instead of + having to change all PCB structs. */ +#define IP_PCB \ + /* ip addresses in network byte order */ \ + ip_addr_t local_ip; \ + ip_addr_t remote_ip; \ + /* Bound netif index */ \ + u8_t netif_idx; \ + /* Socket options */ \ + u8_t so_options; \ + /* Type Of Service */ \ + u8_t tos; \ + /* Time To Live */ \ + u8_t ttl \ + /* link layer address resolution hint */ \ + IP_PCB_NETIFHINT + +struct ip_pcb { + /* Common members of all PCB types */ + IP_PCB; +}; + +/* + * Option flags per-socket. These are the same like SO_XXX in sockets.h + */ +#define SOF_REUSEADDR 0x04U /* allow local address reuse */ +#define SOF_KEEPALIVE 0x08U /* keep connections alive */ +#define SOF_BROADCAST 0x20U /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ + +/* These flags are inherited (e.g. from a listen-pcb to a connection-pcb): */ +#define SOF_INHERITED (SOF_REUSEADDR|SOF_KEEPALIVE) + +/** Global variables of this module, kept in a struct for efficient access using base+index. */ +struct ip_globals +{ + /** The interface that accepted the packet for the current callback invocation. */ + struct netif *current_netif; + /** The interface that received the packet for the current callback invocation. */ + struct netif *current_input_netif; +#if LWIP_IPV4 + /** Header of the input packet currently being processed. */ + const struct ip_hdr *current_ip4_header; +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 + /** Header of the input IPv6 packet currently being processed. */ + struct ip6_hdr *current_ip6_header; +#endif /* LWIP_IPV6 */ + /** Total header length of current_ip4/6_header (i.e. after this, the UDP/TCP header starts) */ + u16_t current_ip_header_tot_len; + /** Source IP address of current_header */ + ip_addr_t current_iphdr_src; + /** Destination IP address of current_header */ + ip_addr_t current_iphdr_dest; +}; +extern struct ip_globals ip_data; + + +/** Get the interface that accepted the current packet. + * This may or may not be the receiving netif, depending on your netif/network setup. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_netif() (ip_data.current_netif) +/** Get the interface that received the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip_current_input_netif() (ip_data.current_input_netif) +/** Total header length of ip(6)_current_header() (i.e. after this, the UDP/TCP header starts) */ +#define ip_current_header_tot_len() (ip_data.current_ip_header_tot_len) +/** Source IP address of current_header */ +#define ip_current_src_addr() (&ip_data.current_iphdr_src) +/** Destination IP address of current_header */ +#define ip_current_dest_addr() (&ip_data.current_iphdr_dest) + +#if LWIP_IPV4 && LWIP_IPV6 +/** Get the IPv4 header of the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip4_current_header() ip_data.current_ip4_header +/** Get the IPv6 header of the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip6_current_header() ((const struct ip6_hdr*)(ip_data.current_ip6_header)) +/** Returns TRUE if the current IP input packet is IPv6, FALSE if it is IPv4 */ +#define ip_current_is_v6() (ip6_current_header() != NULL) +/** Source IPv6 address of current_header */ +#define ip6_current_src_addr() (ip_2_ip6(&ip_data.current_iphdr_src)) +/** Destination IPv6 address of current_header */ +#define ip6_current_dest_addr() (ip_2_ip6(&ip_data.current_iphdr_dest)) +/** Get the transport layer protocol */ +#define ip_current_header_proto() (ip_current_is_v6() ? \ + IP6H_NEXTH(ip6_current_header()) :\ + IPH_PROTO(ip4_current_header())) +/** Get the transport layer header */ +#define ip_next_header_ptr() ((const void*)((ip_current_is_v6() ? \ + (const u8_t*)ip6_current_header() : (const u8_t*)ip4_current_header()) + ip_current_header_tot_len())) + +/** Source IP4 address of current_header */ +#define ip4_current_src_addr() (ip_2_ip4(&ip_data.current_iphdr_src)) +/** Destination IP4 address of current_header */ +#define ip4_current_dest_addr() (ip_2_ip4(&ip_data.current_iphdr_dest)) + +#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */ + +/** Get the IPv4 header of the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip4_current_header() ip_data.current_ip4_header +/** Always returns FALSE when only supporting IPv4 only */ +#define ip_current_is_v6() 0 +/** Get the transport layer protocol */ +#define ip_current_header_proto() IPH_PROTO(ip4_current_header()) +/** Get the transport layer header */ +#define ip_next_header_ptr() ((const void*)((const u8_t*)ip4_current_header() + ip_current_header_tot_len())) +/** Source IP4 address of current_header */ +#define ip4_current_src_addr() (&ip_data.current_iphdr_src) +/** Destination IP4 address of current_header */ +#define ip4_current_dest_addr() (&ip_data.current_iphdr_dest) + +#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ + +/** Get the IPv6 header of the current packet. + * This function must only be called from a receive callback (udp_recv, + * raw_recv, tcp_accept). It will return NULL otherwise. */ +#define ip6_current_header() ((const struct ip6_hdr*)(ip_data.current_ip6_header)) +/** Always returns TRUE when only supporting IPv6 only */ +#define ip_current_is_v6() 1 +/** Get the transport layer protocol */ +#define ip_current_header_proto() IP6H_NEXTH(ip6_current_header()) +/** Get the transport layer header */ +#define ip_next_header_ptr() ((const void*)(((const u8_t*)ip6_current_header()) + ip_current_header_tot_len())) +/** Source IP6 address of current_header */ +#define ip6_current_src_addr() (&ip_data.current_iphdr_src) +/** Destination IP6 address of current_header */ +#define ip6_current_dest_addr() (&ip_data.current_iphdr_dest) + +#endif /* LWIP_IPV6 */ + +/** Union source address of current_header */ +#define ip_current_src_addr() (&ip_data.current_iphdr_src) +/** Union destination address of current_header */ +#define ip_current_dest_addr() (&ip_data.current_iphdr_dest) + +/** Gets an IP pcb option (SOF_* flags) */ +#define ip_get_option(pcb, opt) ((pcb)->so_options & (opt)) +/** Sets an IP pcb option (SOF_* flags) */ +#define ip_set_option(pcb, opt) ((pcb)->so_options = (u8_t)((pcb)->so_options | (opt))) +/** Resets an IP pcb option (SOF_* flags) */ +#define ip_reset_option(pcb, opt) ((pcb)->so_options = (u8_t)((pcb)->so_options & ~(opt))) + +#if LWIP_IPV4 && LWIP_IPV6 +/** + * @ingroup ip + * Output IP packet, netif is selected by source address + */ +#define ip_output(p, src, dest, ttl, tos, proto) \ + (IP_IS_V6(dest) ? \ + ip6_output(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto) : \ + ip4_output(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto)) +/** + * @ingroup ip + * Output IP packet to specified interface + */ +#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \ + (IP_IS_V6(dest) ? \ + ip6_output_if(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \ + ip4_output_if(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif)) +/** + * @ingroup ip + * Output IP packet to interface specifying source address + */ +#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \ + (IP_IS_V6(dest) ? \ + ip6_output_if_src(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif) : \ + ip4_output_if_src(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif)) +/** Output IP packet that already includes an IP header. */ +#define ip_output_if_hdrincl(p, src, dest, netif) \ + (IP_IS_V6(dest) ? \ + ip6_output_if(p, ip_2_ip6(src), LWIP_IP_HDRINCL, 0, 0, 0, netif) : \ + ip4_output_if(p, ip_2_ip4(src), LWIP_IP_HDRINCL, 0, 0, 0, netif)) +/** Output IP packet with netif_hint */ +#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \ + (IP_IS_V6(dest) ? \ + ip6_output_hinted(p, ip_2_ip6(src), ip_2_ip6(dest), ttl, tos, proto, netif_hint) : \ + ip4_output_hinted(p, ip_2_ip4(src), ip_2_ip4(dest), ttl, tos, proto, netif_hint)) +/** + * @ingroup ip + * Get netif for address combination. See \ref ip6_route and \ref ip4_route + */ +#define ip_route(src, dest) \ + (IP_IS_V6(dest) ? \ + ip6_route(ip_2_ip6(src), ip_2_ip6(dest)) : \ + ip4_route_src(ip_2_ip4(src), ip_2_ip4(dest))) +/** + * @ingroup ip + * Get netif for IP. + */ +#define ip_netif_get_local_ip(netif, dest) (IP_IS_V6(dest) ? \ + ip6_netif_get_local_ip(netif, ip_2_ip6(dest)) : \ + ip4_netif_get_local_ip(netif)) +#define ip_debug_print(is_ipv6, p) ((is_ipv6) ? ip6_debug_print(p) : ip4_debug_print(p)) + +err_t ip_input(struct pbuf *p, struct netif *inp); + +#elif LWIP_IPV4 /* LWIP_IPV4 && LWIP_IPV6 */ + +#define ip_output(p, src, dest, ttl, tos, proto) \ + ip4_output(p, src, dest, ttl, tos, proto) +#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \ + ip4_output_if(p, src, dest, ttl, tos, proto, netif) +#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \ + ip4_output_if_src(p, src, dest, ttl, tos, proto, netif) +#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \ + ip4_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) +#define ip_output_if_hdrincl(p, src, dest, netif) \ + ip4_output_if(p, src, LWIP_IP_HDRINCL, 0, 0, 0, netif) +#define ip_route(src, dest) \ + ip4_route_src(src, dest) +#define ip_netif_get_local_ip(netif, dest) \ + ip4_netif_get_local_ip(netif) +#define ip_debug_print(is_ipv6, p) ip4_debug_print(p) + +#define ip_input ip4_input + +#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ + +#define ip_output(p, src, dest, ttl, tos, proto) \ + ip6_output(p, src, dest, ttl, tos, proto) +#define ip_output_if(p, src, dest, ttl, tos, proto, netif) \ + ip6_output_if(p, src, dest, ttl, tos, proto, netif) +#define ip_output_if_src(p, src, dest, ttl, tos, proto, netif) \ + ip6_output_if_src(p, src, dest, ttl, tos, proto, netif) +#define ip_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) \ + ip6_output_hinted(p, src, dest, ttl, tos, proto, netif_hint) +#define ip_output_if_hdrincl(p, src, dest, netif) \ + ip6_output_if(p, src, LWIP_IP_HDRINCL, 0, 0, 0, netif) +#define ip_route(src, dest) \ + ip6_route(src, dest) +#define ip_netif_get_local_ip(netif, dest) \ + ip6_netif_get_local_ip(netif, dest) +#define ip_debug_print(is_ipv6, p) ip6_debug_print(p) + +#define ip_input ip6_input + +#endif /* LWIP_IPV6 */ + +#define ip_route_get_local_ip(src, dest, netif, ipaddr) do { \ + (netif) = ip_route(src, dest); \ + (ipaddr) = ip_netif_get_local_ip(netif, dest); \ +}while(0) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_IP_H */ + + diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h new file mode 100644 index 0000000..fd35a33 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip4.h @@ -0,0 +1,111 @@ +/** + * @file + * IPv4 API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_IP4_H +#define LWIP_HDR_IP4_H + +#include "lwip/opt.h" + +#if LWIP_IPV4 + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/ip4_addr.h" +#include "lwip/err.h" +#include "lwip/netif.h" +#include "lwip/prot/ip4.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef LWIP_HOOK_IP4_ROUTE_SRC +#define LWIP_IPV4_SRC_ROUTING 1 +#else +#define LWIP_IPV4_SRC_ROUTING 0 +#endif + +/** Currently, the function ip_output_if_opt() is only used with IGMP */ +#define IP_OPTIONS_SEND (LWIP_IPV4 && LWIP_IGMP) + +#define ip_init() /* Compatibility define, no init needed. */ +struct netif *ip4_route(const ip4_addr_t *dest); +#if LWIP_IPV4_SRC_ROUTING +struct netif *ip4_route_src(const ip4_addr_t *src, const ip4_addr_t *dest); +#else /* LWIP_IPV4_SRC_ROUTING */ +#define ip4_route_src(src, dest) ip4_route(dest) +#endif /* LWIP_IPV4_SRC_ROUTING */ +err_t ip4_input(struct pbuf *p, struct netif *inp); +err_t ip4_output(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto); +err_t ip4_output_if(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif); +err_t ip4_output_if_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif); +#if LWIP_NETIF_USE_HINTS +err_t ip4_output_hinted(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif_hint *netif_hint); +#endif /* LWIP_NETIF_USE_HINTS */ +#if IP_OPTIONS_SEND +err_t ip4_output_if_opt(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen); +err_t ip4_output_if_opt_src(struct pbuf *p, const ip4_addr_t *src, const ip4_addr_t *dest, + u8_t ttl, u8_t tos, u8_t proto, struct netif *netif, void *ip_options, + u16_t optlen); +#endif /* IP_OPTIONS_SEND */ + +#if LWIP_MULTICAST_TX_OPTIONS +void ip4_set_default_multicast_netif(struct netif* default_multicast_netif); +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + +#define ip4_netif_get_local_ip(netif) (((netif) != NULL) ? netif_ip_addr4(netif) : NULL) + +#if IP_DEBUG +void ip4_debug_print(struct pbuf *p); +#else +#define ip4_debug_print(p) +#endif /* IP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV4 */ + +#endif /* LWIP_HDR_IP_H */ + + diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h new file mode 100644 index 0000000..f244c4f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_addr.h @@ -0,0 +1,216 @@ +/** + * @file + * IPv4 address API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_IP4_ADDR_H +#define LWIP_HDR_IP4_ADDR_H + +#include "lwip/opt.h" +#include "lwip/def.h" + +#if LWIP_IPV4 + +#ifdef __cplusplus +extern "C" { +#endif + +/** This is the aligned version of ip4_addr_t, + used as local variable, on the stack, etc. */ +struct ip4_addr { + u32_t addr; +}; + +/** ip4_addr_t uses a struct for convenience only, so that the same defines can + * operate both on ip4_addr_t as well as on ip4_addr_p_t. */ +typedef struct ip4_addr ip4_addr_t; + +/* Forward declaration to not include netif.h */ +struct netif; + +/** 255.255.255.255 */ +#define IPADDR_NONE ((u32_t)0xffffffffUL) +/** 127.0.0.1 */ +#define IPADDR_LOOPBACK ((u32_t)0x7f000001UL) +/** 0.0.0.0 */ +#define IPADDR_ANY ((u32_t)0x00000000UL) +/** 255.255.255.255 */ +#define IPADDR_BROADCAST ((u32_t)0xffffffffUL) + +/* Definitions of the bits in an Internet address integer. + + On subnets, host and network parts are found according to + the subnet mask, not these masks. */ +#define IP_CLASSA(a) ((((u32_t)(a)) & 0x80000000UL) == 0) +#define IP_CLASSA_NET 0xff000000 +#define IP_CLASSA_NSHIFT 24 +#define IP_CLASSA_HOST (0xffffffff & ~IP_CLASSA_NET) +#define IP_CLASSA_MAX 128 + +#define IP_CLASSB(a) ((((u32_t)(a)) & 0xc0000000UL) == 0x80000000UL) +#define IP_CLASSB_NET 0xffff0000 +#define IP_CLASSB_NSHIFT 16 +#define IP_CLASSB_HOST (0xffffffff & ~IP_CLASSB_NET) +#define IP_CLASSB_MAX 65536 + +#define IP_CLASSC(a) ((((u32_t)(a)) & 0xe0000000UL) == 0xc0000000UL) +#define IP_CLASSC_NET 0xffffff00 +#define IP_CLASSC_NSHIFT 8 +#define IP_CLASSC_HOST (0xffffffff & ~IP_CLASSC_NET) + +#define IP_CLASSD(a) (((u32_t)(a) & 0xf0000000UL) == 0xe0000000UL) +#define IP_CLASSD_NET 0xf0000000 /* These ones aren't really */ +#define IP_CLASSD_NSHIFT 28 /* net and host fields, but */ +#define IP_CLASSD_HOST 0x0fffffff /* routing needn't know. */ +#define IP_MULTICAST(a) IP_CLASSD(a) + +#define IP_EXPERIMENTAL(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) +#define IP_BADCLASS(a) (((u32_t)(a) & 0xf0000000UL) == 0xf0000000UL) + +#define IP_LOOPBACKNET 127 /* official! */ + +/** Set an IP address given by the four byte-parts */ +#define IP4_ADDR(ipaddr, a,b,c,d) (ipaddr)->addr = PP_HTONL(LWIP_MAKEU32(a,b,c,d)) + +/** Copy IP address - faster than ip4_addr_set: no NULL check */ +#define ip4_addr_copy(dest, src) ((dest).addr = (src).addr) +/** Safely copy one IP address to another (src may be NULL) */ +#define ip4_addr_set(dest, src) ((dest)->addr = \ + ((src) == NULL ? 0 : \ + (src)->addr)) +/** Set complete address to zero */ +#define ip4_addr_set_zero(ipaddr) ((ipaddr)->addr = 0) +/** Set address to IPADDR_ANY (no need for lwip_htonl()) */ +#define ip4_addr_set_any(ipaddr) ((ipaddr)->addr = IPADDR_ANY) +/** Set address to loopback address */ +#define ip4_addr_set_loopback(ipaddr) ((ipaddr)->addr = PP_HTONL(IPADDR_LOOPBACK)) +/** Check if an address is in the loopback region */ +#define ip4_addr_isloopback(ipaddr) (((ipaddr)->addr & PP_HTONL(IP_CLASSA_NET)) == PP_HTONL(((u32_t)IP_LOOPBACKNET) << 24)) +/** Safely copy one IP address to another and change byte order + * from host- to network-order. */ +#define ip4_addr_set_hton(dest, src) ((dest)->addr = \ + ((src) == NULL ? 0:\ + lwip_htonl((src)->addr))) +/** IPv4 only: set the IP address given as an u32_t */ +#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32)) +/** IPv4 only: get the IP address as an u32_t */ +#define ip4_addr_get_u32(src_ipaddr) ((src_ipaddr)->addr) + +/** Get the network address by combining host address with netmask */ +#define ip4_addr_get_network(target, host, netmask) do { ((target)->addr = ((host)->addr) & ((netmask)->addr)); } while(0) + +/** + * Determine if two address are on the same network. + * + * @arg addr1 IP address 1 + * @arg addr2 IP address 2 + * @arg mask network identifier mask + * @return !0 if the network identifiers of both address match + */ +#define ip4_addr_netcmp(addr1, addr2, mask) (((addr1)->addr & \ + (mask)->addr) == \ + ((addr2)->addr & \ + (mask)->addr)) +#define ip4_addr_cmp(addr1, addr2) ((addr1)->addr == (addr2)->addr) + +#define ip4_addr_isany_val(addr1) ((addr1).addr == IPADDR_ANY) +#define ip4_addr_isany(addr1) ((addr1) == NULL || ip4_addr_isany_val(*(addr1))) + +#define ip4_addr_isbroadcast(addr1, netif) ip4_addr_isbroadcast_u32((addr1)->addr, netif) +u8_t ip4_addr_isbroadcast_u32(u32_t addr, const struct netif *netif); + +#define ip_addr_netmask_valid(netmask) ip4_addr_netmask_valid((netmask)->addr) +u8_t ip4_addr_netmask_valid(u32_t netmask); + +#define ip4_addr_ismulticast(addr1) (((addr1)->addr & PP_HTONL(0xf0000000UL)) == PP_HTONL(0xe0000000UL)) + +#define ip4_addr_islinklocal(addr1) (((addr1)->addr & PP_HTONL(0xffff0000UL)) == PP_HTONL(0xa9fe0000UL)) + +#define ip4_addr_debug_print_parts(debug, a, b, c, d) \ + LWIP_DEBUGF(debug, ("%" U16_F ".%" U16_F ".%" U16_F ".%" U16_F, a, b, c, d)) +#define ip4_addr_debug_print(debug, ipaddr) \ + ip4_addr_debug_print_parts(debug, \ + (u16_t)((ipaddr) != NULL ? ip4_addr1_16(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? ip4_addr2_16(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? ip4_addr3_16(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? ip4_addr4_16(ipaddr) : 0)) +#define ip4_addr_debug_print_val(debug, ipaddr) \ + ip4_addr_debug_print_parts(debug, \ + ip4_addr1_16_val(ipaddr), \ + ip4_addr2_16_val(ipaddr), \ + ip4_addr3_16_val(ipaddr), \ + ip4_addr4_16_val(ipaddr)) + +/* Get one byte from the 4-byte address */ +#define ip4_addr_get_byte(ipaddr, idx) (((const u8_t*)(&(ipaddr)->addr))[idx]) +#define ip4_addr1(ipaddr) ip4_addr_get_byte(ipaddr, 0) +#define ip4_addr2(ipaddr) ip4_addr_get_byte(ipaddr, 1) +#define ip4_addr3(ipaddr) ip4_addr_get_byte(ipaddr, 2) +#define ip4_addr4(ipaddr) ip4_addr_get_byte(ipaddr, 3) +/* Get one byte from the 4-byte address, but argument is 'ip4_addr_t', + * not a pointer */ +#define ip4_addr_get_byte_val(ipaddr, idx) ((u8_t)(((ipaddr).addr >> (idx * 8)) & 0xff)) +#define ip4_addr1_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 0) +#define ip4_addr2_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 1) +#define ip4_addr3_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 2) +#define ip4_addr4_val(ipaddr) ip4_addr_get_byte_val(ipaddr, 3) +/* These are cast to u16_t, with the intent that they are often arguments + * to printf using the U16_F format from cc.h. */ +#define ip4_addr1_16(ipaddr) ((u16_t)ip4_addr1(ipaddr)) +#define ip4_addr2_16(ipaddr) ((u16_t)ip4_addr2(ipaddr)) +#define ip4_addr3_16(ipaddr) ((u16_t)ip4_addr3(ipaddr)) +#define ip4_addr4_16(ipaddr) ((u16_t)ip4_addr4(ipaddr)) +#define ip4_addr1_16_val(ipaddr) ((u16_t)ip4_addr1_val(ipaddr)) +#define ip4_addr2_16_val(ipaddr) ((u16_t)ip4_addr2_val(ipaddr)) +#define ip4_addr3_16_val(ipaddr) ((u16_t)ip4_addr3_val(ipaddr)) +#define ip4_addr4_16_val(ipaddr) ((u16_t)ip4_addr4_val(ipaddr)) + +#define IP4ADDR_STRLEN_MAX 16 + +/** For backwards compatibility */ +#define ip_ntoa(ipaddr) ipaddr_ntoa(ipaddr) + +u32_t ipaddr_addr(const char *cp); +int ip4addr_aton(const char *cp, ip4_addr_t *addr); +/** returns ptr to static buffer; not reentrant! */ +char *ip4addr_ntoa(const ip4_addr_t *addr); +char *ip4addr_ntoa_r(const ip4_addr_t *addr, char *buf, int buflen); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV4 */ + +#endif /* LWIP_HDR_IP_ADDR_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h new file mode 100644 index 0000000..ed5bf14 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip4_frag.h @@ -0,0 +1,100 @@ +/** + * @file + * IP fragmentation/reassembly + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Jani Monoses + * + */ + +#ifndef LWIP_HDR_IP4_FRAG_H +#define LWIP_HDR_IP4_FRAG_H + +#include "lwip/opt.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" + +#if LWIP_IPV4 + +#ifdef __cplusplus +extern "C" { +#endif + +#if IP_REASSEMBLY +/* The IP reassembly timer interval in milliseconds. */ +#define IP_TMR_INTERVAL 1000 + +/** IP reassembly helper struct. + * This is exported because memp needs to know the size. + */ +struct ip_reassdata { + struct ip_reassdata *next; + struct pbuf *p; + struct ip_hdr iphdr; + u16_t datagram_len; + u8_t flags; + u8_t timer; +}; + +void ip_reass_init(void); +void ip_reass_tmr(void); +struct pbuf * ip4_reass(struct pbuf *p); +#endif /* IP_REASSEMBLY */ + +#if IP_FRAG +#if !LWIP_NETIF_TX_SINGLE_PBUF +#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED +#define LWIP_PBUF_CUSTOM_REF_DEFINED +/** A custom pbuf that holds a reference to another pbuf, which is freed + * when this custom pbuf is freed. This is used to create a custom PBUF_REF + * that points into the original pbuf. */ +struct pbuf_custom_ref { + /** 'base class' */ + struct pbuf_custom pc; + /** pointer to the original pbuf that is referenced */ + struct pbuf *original; +}; +#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */ +#endif /* !LWIP_NETIF_TX_SINGLE_PBUF */ + +err_t ip4_frag(struct pbuf *p, struct netif *netif, const ip4_addr_t *dest); +#endif /* IP_FRAG */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV4 */ + +#endif /* LWIP_HDR_IP4_FRAG_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h new file mode 100644 index 0000000..f894e06 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6.h @@ -0,0 +1,93 @@ +/** + * @file + * + * IPv6 layer. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ +#ifndef LWIP_HDR_IP6_H +#define LWIP_HDR_IP6_H + +#include "lwip/opt.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip6_addr.h" +#include "lwip/prot/ip6.h" +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/netif.h" + +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct netif *ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest); +const ip_addr_t *ip6_select_source_address(struct netif *netif, const ip6_addr_t * dest); +err_t ip6_input(struct pbuf *p, struct netif *inp); +err_t ip6_output(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, u8_t nexth); +err_t ip6_output_if(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, u8_t nexth, struct netif *netif); +err_t ip6_output_if_src(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, u8_t nexth, struct netif *netif); +#if LWIP_NETIF_USE_HINTS +err_t ip6_output_hinted(struct pbuf *p, const ip6_addr_t *src, const ip6_addr_t *dest, + u8_t hl, u8_t tc, u8_t nexth, struct netif_hint *netif_hint); +#endif /* LWIP_NETIF_USE_HINTS */ +#if LWIP_IPV6_MLD +err_t ip6_options_add_hbh_ra(struct pbuf * p, u8_t nexth, u8_t value); +#endif /* LWIP_IPV6_MLD */ + +#define ip6_netif_get_local_ip(netif, dest) (((netif) != NULL) ? \ + ip6_select_source_address(netif, dest) : NULL) + +#if IP6_DEBUG +void ip6_debug_print(struct pbuf *p); +#else +#define ip6_debug_print(p) +#endif /* IP6_DEBUG */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 */ + +#endif /* LWIP_HDR_IP6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h new file mode 100644 index 0000000..29c2a34 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_addr.h @@ -0,0 +1,352 @@ +/** + * @file + * + * IPv6 addresses. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * Structs and macros for handling IPv6 addresses. + * + * Please coordinate changes and requests with Ivan Delamer + * + */ +#ifndef LWIP_HDR_IP6_ADDR_H +#define LWIP_HDR_IP6_ADDR_H + +#include "lwip/opt.h" +#include "def.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip6_zone.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** This is the aligned version of ip6_addr_t, + used as local variable, on the stack, etc. */ +struct ip6_addr { + u32_t addr[4]; +#if LWIP_IPV6_SCOPES + u8_t zone; +#endif /* LWIP_IPV6_SCOPES */ +}; + +/** IPv6 address */ +typedef struct ip6_addr ip6_addr_t; + +/** Set an IPv6 partial address given by byte-parts */ +#define IP6_ADDR_PART(ip6addr, index, a,b,c,d) \ + (ip6addr)->addr[index] = PP_HTONL(LWIP_MAKEU32(a,b,c,d)) + +/** Set a full IPv6 address by passing the 4 u32_t indices in network byte order + (use PP_HTONL() for constants) */ +#define IP6_ADDR(ip6addr, idx0, idx1, idx2, idx3) do { \ + (ip6addr)->addr[0] = idx0; \ + (ip6addr)->addr[1] = idx1; \ + (ip6addr)->addr[2] = idx2; \ + (ip6addr)->addr[3] = idx3; \ + ip6_addr_clear_zone(ip6addr); } while(0) + +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK1(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xffff)) +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK2(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[0])) & 0xffff)) +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK3(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1]) >> 16) & 0xffff)) +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK4(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[1])) & 0xffff)) +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK5(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2]) >> 16) & 0xffff)) +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK6(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[2])) & 0xffff)) +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK7(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3]) >> 16) & 0xffff)) +/** Access address in 16-bit block */ +#define IP6_ADDR_BLOCK8(ip6addr) ((u16_t)((lwip_htonl((ip6addr)->addr[3])) & 0xffff)) + +/** Copy IPv6 address - faster than ip6_addr_set: no NULL check */ +#define ip6_addr_copy(dest, src) do{(dest).addr[0] = (src).addr[0]; \ + (dest).addr[1] = (src).addr[1]; \ + (dest).addr[2] = (src).addr[2]; \ + (dest).addr[3] = (src).addr[3]; \ + ip6_addr_copy_zone((dest), (src)); }while(0) +/** Safely copy one IPv6 address to another (src may be NULL) */ +#define ip6_addr_set(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : (src)->addr[0]; \ + (dest)->addr[1] = (src) == NULL ? 0 : (src)->addr[1]; \ + (dest)->addr[2] = (src) == NULL ? 0 : (src)->addr[2]; \ + (dest)->addr[3] = (src) == NULL ? 0 : (src)->addr[3]; \ + ip6_addr_set_zone((dest), (src) == NULL ? IP6_NO_ZONE : ip6_addr_zone(src)); }while(0) + +/** Copy packed IPv6 address to unpacked IPv6 address; zone is not set */ +#define ip6_addr_copy_from_packed(dest, src) do{(dest).addr[0] = (src).addr[0]; \ + (dest).addr[1] = (src).addr[1]; \ + (dest).addr[2] = (src).addr[2]; \ + (dest).addr[3] = (src).addr[3]; \ + ip6_addr_clear_zone(&dest); }while(0) + +/** Copy unpacked IPv6 address to packed IPv6 address; zone is lost */ +#define ip6_addr_copy_to_packed(dest, src) do{(dest).addr[0] = (src).addr[0]; \ + (dest).addr[1] = (src).addr[1]; \ + (dest).addr[2] = (src).addr[2]; \ + (dest).addr[3] = (src).addr[3]; }while(0) + +/** Set complete address to zero */ +#define ip6_addr_set_zero(ip6addr) do{(ip6addr)->addr[0] = 0; \ + (ip6addr)->addr[1] = 0; \ + (ip6addr)->addr[2] = 0; \ + (ip6addr)->addr[3] = 0; \ + ip6_addr_clear_zone(ip6addr);}while(0) + +/** Set address to ipv6 'any' (no need for lwip_htonl()) */ +#define ip6_addr_set_any(ip6addr) ip6_addr_set_zero(ip6addr) +/** Set address to ipv6 loopback address */ +#define ip6_addr_set_loopback(ip6addr) do{(ip6addr)->addr[0] = 0; \ + (ip6addr)->addr[1] = 0; \ + (ip6addr)->addr[2] = 0; \ + (ip6addr)->addr[3] = PP_HTONL(0x00000001UL); \ + ip6_addr_clear_zone(ip6addr);}while(0) +/** Safely copy one IPv6 address to another and change byte order + * from host- to network-order. */ +#define ip6_addr_set_hton(dest, src) do{(dest)->addr[0] = (src) == NULL ? 0 : lwip_htonl((src)->addr[0]); \ + (dest)->addr[1] = (src) == NULL ? 0 : lwip_htonl((src)->addr[1]); \ + (dest)->addr[2] = (src) == NULL ? 0 : lwip_htonl((src)->addr[2]); \ + (dest)->addr[3] = (src) == NULL ? 0 : lwip_htonl((src)->addr[3]); \ + ip6_addr_set_zone((dest), (src) == NULL ? IP6_NO_ZONE : ip6_addr_zone(src));}while(0) + + +/** Compare IPv6 networks, ignoring zone information. To be used sparingly! */ +#define ip6_addr_netcmp_zoneless(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \ + ((addr1)->addr[1] == (addr2)->addr[1])) + +/** + * Determine if two IPv6 address are on the same network. + * + * @param addr1 IPv6 address 1 + * @param addr2 IPv6 address 2 + * @return 1 if the network identifiers of both address match, 0 if not + */ +#define ip6_addr_netcmp(addr1, addr2) (ip6_addr_netcmp_zoneless((addr1), (addr2)) && \ + ip6_addr_cmp_zone((addr1), (addr2))) + +/* Exact-host comparison *after* ip6_addr_netcmp() succeeded, for efficiency. */ +#define ip6_addr_nethostcmp(addr1, addr2) (((addr1)->addr[2] == (addr2)->addr[2]) && \ + ((addr1)->addr[3] == (addr2)->addr[3])) + +/** Compare IPv6 addresses, ignoring zone information. To be used sparingly! */ +#define ip6_addr_cmp_zoneless(addr1, addr2) (((addr1)->addr[0] == (addr2)->addr[0]) && \ + ((addr1)->addr[1] == (addr2)->addr[1]) && \ + ((addr1)->addr[2] == (addr2)->addr[2]) && \ + ((addr1)->addr[3] == (addr2)->addr[3])) +/** + * Determine if two IPv6 addresses are the same. In particular, the address + * part of both must be the same, and the zone must be compatible. + * + * @param addr1 IPv6 address 1 + * @param addr2 IPv6 address 2 + * @return 1 if the addresses are considered equal, 0 if not + */ +#define ip6_addr_cmp(addr1, addr2) (ip6_addr_cmp_zoneless((addr1), (addr2)) && \ + ip6_addr_cmp_zone((addr1), (addr2))) + +/** Compare IPv6 address to packed address and zone */ +#define ip6_addr_cmp_packed(ip6addr, paddr, zone_idx) (((ip6addr)->addr[0] == (paddr)->addr[0]) && \ + ((ip6addr)->addr[1] == (paddr)->addr[1]) && \ + ((ip6addr)->addr[2] == (paddr)->addr[2]) && \ + ((ip6addr)->addr[3] == (paddr)->addr[3]) && \ + ip6_addr_equals_zone((ip6addr), (zone_idx))) + +#define ip6_get_subnet_id(ip6addr) (lwip_htonl((ip6addr)->addr[2]) & 0x0000ffffUL) + +#define ip6_addr_isany_val(ip6addr) (((ip6addr).addr[0] == 0) && \ + ((ip6addr).addr[1] == 0) && \ + ((ip6addr).addr[2] == 0) && \ + ((ip6addr).addr[3] == 0)) +#define ip6_addr_isany(ip6addr) (((ip6addr) == NULL) || ip6_addr_isany_val(*(ip6addr))) + +#define ip6_addr_isloopback(ip6addr) (((ip6addr)->addr[0] == 0UL) && \ + ((ip6addr)->addr[1] == 0UL) && \ + ((ip6addr)->addr[2] == 0UL) && \ + ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL))) + +#define ip6_addr_isglobal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xe0000000UL)) == PP_HTONL(0x20000000UL)) + +#define ip6_addr_islinklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfe800000UL)) + +#define ip6_addr_issitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xffc00000UL)) == PP_HTONL(0xfec00000UL)) + +#define ip6_addr_isuniquelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xfe000000UL)) == PP_HTONL(0xfc000000UL)) + +#define ip6_addr_isipv4mappedipv6(ip6addr) (((ip6addr)->addr[0] == 0) && ((ip6addr)->addr[1] == 0) && (((ip6addr)->addr[2]) == PP_HTONL(0x0000FFFFUL))) + +#define ip6_addr_ismulticast(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) +#define ip6_addr_multicast_transient_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00100000UL)) +#define ip6_addr_multicast_prefix_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00200000UL)) +#define ip6_addr_multicast_rendezvous_flag(ip6addr) ((ip6addr)->addr[0] & PP_HTONL(0x00400000UL)) +#define ip6_addr_multicast_scope(ip6addr) ((lwip_htonl((ip6addr)->addr[0]) >> 16) & 0xf) +#define IP6_MULTICAST_SCOPE_RESERVED 0x0 +#define IP6_MULTICAST_SCOPE_RESERVED0 0x0 +#define IP6_MULTICAST_SCOPE_INTERFACE_LOCAL 0x1 +#define IP6_MULTICAST_SCOPE_LINK_LOCAL 0x2 +#define IP6_MULTICAST_SCOPE_RESERVED3 0x3 +#define IP6_MULTICAST_SCOPE_ADMIN_LOCAL 0x4 +#define IP6_MULTICAST_SCOPE_SITE_LOCAL 0x5 +#define IP6_MULTICAST_SCOPE_ORGANIZATION_LOCAL 0x8 +#define IP6_MULTICAST_SCOPE_GLOBAL 0xe +#define IP6_MULTICAST_SCOPE_RESERVEDF 0xf +#define ip6_addr_ismulticast_iflocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff010000UL)) +#define ip6_addr_ismulticast_linklocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff020000UL)) +#define ip6_addr_ismulticast_adminlocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff040000UL)) +#define ip6_addr_ismulticast_sitelocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff050000UL)) +#define ip6_addr_ismulticast_orglocal(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff080000UL)) +#define ip6_addr_ismulticast_global(ip6addr) (((ip6addr)->addr[0] & PP_HTONL(0xff8f0000UL)) == PP_HTONL(0xff0e0000UL)) + +/* Scoping note: while interface-local and link-local multicast addresses do + * have a scope (i.e., they are meaningful only in the context of a particular + * interface), the following functions are not assigning or comparing zone + * indices. The reason for this is backward compatibility. Any call site that + * produces a non-global multicast address must assign a multicast address as + * appropriate itself. */ + +#define ip6_addr_isallnodes_iflocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff010000UL)) && \ + ((ip6addr)->addr[1] == 0UL) && \ + ((ip6addr)->addr[2] == 0UL) && \ + ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL))) + +#define ip6_addr_isallnodes_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ + ((ip6addr)->addr[1] == 0UL) && \ + ((ip6addr)->addr[2] == 0UL) && \ + ((ip6addr)->addr[3] == PP_HTONL(0x00000001UL))) +#define ip6_addr_set_allnodes_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \ + (ip6addr)->addr[1] = 0; \ + (ip6addr)->addr[2] = 0; \ + (ip6addr)->addr[3] = PP_HTONL(0x00000001UL); \ + ip6_addr_clear_zone(ip6addr); }while(0) + +#define ip6_addr_isallrouters_linklocal(ip6addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ + ((ip6addr)->addr[1] == 0UL) && \ + ((ip6addr)->addr[2] == 0UL) && \ + ((ip6addr)->addr[3] == PP_HTONL(0x00000002UL))) +#define ip6_addr_set_allrouters_linklocal(ip6addr) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \ + (ip6addr)->addr[1] = 0; \ + (ip6addr)->addr[2] = 0; \ + (ip6addr)->addr[3] = PP_HTONL(0x00000002UL); \ + ip6_addr_clear_zone(ip6addr); }while(0) + +#define ip6_addr_issolicitednode(ip6addr) ( ((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ + ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \ + (((ip6addr)->addr[3] & PP_HTONL(0xff000000UL)) == PP_HTONL(0xff000000UL)) ) + +#define ip6_addr_set_solicitednode(ip6addr, if_id) do{(ip6addr)->addr[0] = PP_HTONL(0xff020000UL); \ + (ip6addr)->addr[1] = 0; \ + (ip6addr)->addr[2] = PP_HTONL(0x00000001UL); \ + (ip6addr)->addr[3] = (PP_HTONL(0xff000000UL) | (if_id)); \ + ip6_addr_clear_zone(ip6addr); }while(0) + +#define ip6_addr_cmp_solicitednode(ip6addr, sn_addr) (((ip6addr)->addr[0] == PP_HTONL(0xff020000UL)) && \ + ((ip6addr)->addr[1] == 0) && \ + ((ip6addr)->addr[2] == PP_HTONL(0x00000001UL)) && \ + ((ip6addr)->addr[3] == (PP_HTONL(0xff000000UL) | (sn_addr)->addr[3]))) + +/* IPv6 address states. */ +#define IP6_ADDR_INVALID 0x00 +#define IP6_ADDR_TENTATIVE 0x08 +#define IP6_ADDR_TENTATIVE_1 0x09 /* 1 probe sent */ +#define IP6_ADDR_TENTATIVE_2 0x0a /* 2 probes sent */ +#define IP6_ADDR_TENTATIVE_3 0x0b /* 3 probes sent */ +#define IP6_ADDR_TENTATIVE_4 0x0c /* 4 probes sent */ +#define IP6_ADDR_TENTATIVE_5 0x0d /* 5 probes sent */ +#define IP6_ADDR_TENTATIVE_6 0x0e /* 6 probes sent */ +#define IP6_ADDR_TENTATIVE_7 0x0f /* 7 probes sent */ +#define IP6_ADDR_VALID 0x10 /* This bit marks an address as valid (preferred or deprecated) */ +#define IP6_ADDR_PREFERRED 0x30 +#define IP6_ADDR_DEPRECATED 0x10 /* Same as VALID (valid but not preferred) */ +#define IP6_ADDR_DUPLICATED 0x40 /* Failed DAD test, not valid */ + +#define IP6_ADDR_TENTATIVE_COUNT_MASK 0x07 /* 1-7 probes sent */ + +#define ip6_addr_isinvalid(addr_state) (addr_state == IP6_ADDR_INVALID) +#define ip6_addr_istentative(addr_state) (addr_state & IP6_ADDR_TENTATIVE) +#define ip6_addr_isvalid(addr_state) (addr_state & IP6_ADDR_VALID) /* Include valid, preferred, and deprecated. */ +#define ip6_addr_ispreferred(addr_state) (addr_state == IP6_ADDR_PREFERRED) +#define ip6_addr_isdeprecated(addr_state) (addr_state == IP6_ADDR_DEPRECATED) +#define ip6_addr_isduplicated(addr_state) (addr_state == IP6_ADDR_DUPLICATED) + +#if LWIP_IPV6_ADDRESS_LIFETIMES +#define IP6_ADDR_LIFE_STATIC (0) +#define IP6_ADDR_LIFE_INFINITE (0xffffffffUL) +#define ip6_addr_life_isstatic(addr_life) ((addr_life) == IP6_ADDR_LIFE_STATIC) +#define ip6_addr_life_isinfinite(addr_life) ((addr_life) == IP6_ADDR_LIFE_INFINITE) +#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ + +#define ip6_addr_debug_print_parts(debug, a, b, c, d, e, f, g, h) \ + LWIP_DEBUGF(debug, ("%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F ":%" X16_F, \ + a, b, c, d, e, f, g, h)) +#define ip6_addr_debug_print(debug, ipaddr) \ + ip6_addr_debug_print_parts(debug, \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK1(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK2(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK3(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK4(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK5(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK6(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK7(ipaddr) : 0), \ + (u16_t)((ipaddr) != NULL ? IP6_ADDR_BLOCK8(ipaddr) : 0)) +#define ip6_addr_debug_print_val(debug, ipaddr) \ + ip6_addr_debug_print_parts(debug, \ + IP6_ADDR_BLOCK1(&(ipaddr)), \ + IP6_ADDR_BLOCK2(&(ipaddr)), \ + IP6_ADDR_BLOCK3(&(ipaddr)), \ + IP6_ADDR_BLOCK4(&(ipaddr)), \ + IP6_ADDR_BLOCK5(&(ipaddr)), \ + IP6_ADDR_BLOCK6(&(ipaddr)), \ + IP6_ADDR_BLOCK7(&(ipaddr)), \ + IP6_ADDR_BLOCK8(&(ipaddr))) + +#define IP6ADDR_STRLEN_MAX 46 + +int ip6addr_aton(const char *cp, ip6_addr_t *addr); +/** returns ptr to static buffer; not reentrant! */ +char *ip6addr_ntoa(const ip6_addr_t *addr); +char *ip6addr_ntoa_r(const ip6_addr_t *addr, char *buf, int buflen); + + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 */ + +#endif /* LWIP_HDR_IP6_ADDR_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h new file mode 100644 index 0000000..87e0e86 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_frag.h @@ -0,0 +1,144 @@ +/** + * @file + * + * IPv6 fragmentation and reassembly. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ +#ifndef LWIP_HDR_IP6_FRAG_H +#define LWIP_HDR_IP6_FRAG_H + +#include "lwip/opt.h" +#include "lwip/pbuf.h" +#include "lwip/ip6_addr.h" +#include "lwip/ip6.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if LWIP_IPV6 && LWIP_IPV6_REASS /* don't build if not configured for use in lwipopts.h */ + +/** The IPv6 reassembly timer interval in milliseconds. */ +#define IP6_REASS_TMR_INTERVAL 1000 + +/** IP6_FRAG_COPYHEADER==1: for platforms where sizeof(void*) > 4, "struct + * ip6_reass_helper" is too large to be stored in the IPv6 fragment header, and + * will bleed into the header before it, which may be the IPv6 header or an + * extension header. This means that for each first fragment packet, we need to + * 1) make a copy of some IPv6 header fields (src+dest) that we need later on, + * just in case we do overwrite part of the IPv6 header, and 2) make a copy of + * the header data that we overwrote, so that we can restore it before either + * completing reassembly or sending an ICMPv6 reply. The last part is true even + * if this setting is disabled, but if it is enabled, we need to save a bit + * more data (up to the size of a pointer) because we overwrite more. */ +#ifndef IPV6_FRAG_COPYHEADER +#define IPV6_FRAG_COPYHEADER 0 +#endif + +/* With IPV6_FRAG_COPYHEADER==1, a helper structure may (or, depending on the + * presence of extensions, may not) overwrite part of the IP header. Therefore, + * we copy the fields that we need from the IP header for as long as the helper + * structure may still be in place. This is easier than temporarily restoring + * those fields in the IP header each time we need to perform checks on them. */ +#if IPV6_FRAG_COPYHEADER +#define IPV6_FRAG_SRC(ipr) ((ipr)->src) +#define IPV6_FRAG_DEST(ipr) ((ipr)->dest) +#else /* IPV6_FRAG_COPYHEADER */ +#define IPV6_FRAG_SRC(ipr) ((ipr)->iphdr->src) +#define IPV6_FRAG_DEST(ipr) ((ipr)->iphdr->dest) +#endif /* IPV6_FRAG_COPYHEADER */ + +/** IPv6 reassembly helper struct. + * This is exported because memp needs to know the size. + */ +struct ip6_reassdata { + struct ip6_reassdata *next; + struct pbuf *p; + struct ip6_hdr *iphdr; /* pointer to the first (original) IPv6 header */ +#if IPV6_FRAG_COPYHEADER + ip6_addr_p_t src; /* copy of the source address in the IP header */ + ip6_addr_p_t dest; /* copy of the destination address in the IP header */ + /* This buffer (for the part of the original header that we overwrite) will + * be slightly oversized, but we cannot compute the exact size from here. */ + u8_t orig_hdr[sizeof(struct ip6_frag_hdr) + sizeof(void*)]; +#else /* IPV6_FRAG_COPYHEADER */ + /* In this case we still need the buffer, for sending ICMPv6 replies. */ + u8_t orig_hdr[sizeof(struct ip6_frag_hdr)]; +#endif /* IPV6_FRAG_COPYHEADER */ + u32_t identification; + u16_t datagram_len; + u8_t nexth; + u8_t timer; +#if LWIP_IPV6_SCOPES + u8_t src_zone; /* zone of original packet's source address */ + u8_t dest_zone; /* zone of original packet's destination address */ +#endif /* LWIP_IPV6_SCOPES */ +}; + +#define ip6_reass_init() /* Compatibility define */ +void ip6_reass_tmr(void); +struct pbuf *ip6_reass(struct pbuf *p); + +#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */ + +#if LWIP_IPV6 && LWIP_IPV6_FRAG /* don't build if not configured for use in lwipopts.h */ + +#ifndef LWIP_PBUF_CUSTOM_REF_DEFINED +#define LWIP_PBUF_CUSTOM_REF_DEFINED +/** A custom pbuf that holds a reference to another pbuf, which is freed + * when this custom pbuf is freed. This is used to create a custom PBUF_REF + * that points into the original pbuf. */ +struct pbuf_custom_ref { + /** 'base class' */ + struct pbuf_custom pc; + /** pointer to the original pbuf that is referenced */ + struct pbuf *original; +}; +#endif /* LWIP_PBUF_CUSTOM_REF_DEFINED */ + +err_t ip6_frag(struct pbuf *p, struct netif *netif, const ip6_addr_t *dest); + +#endif /* LWIP_IPV6 && LWIP_IPV6_FRAG */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_IP6_FRAG_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h new file mode 100644 index 0000000..525790e --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip6_zone.h @@ -0,0 +1,304 @@ +/** + * @file + * + * IPv6 address scopes, zones, and scoping policy. + * + * This header provides the means to implement support for IPv6 address scopes, + * as per RFC 4007. An address scope can be either global or more constrained. + * In lwIP, we say that an address "has a scope" or "is scoped" when its scope + * is constrained, in which case the address is meaningful only in a specific + * "zone." For unicast addresses, only link-local addresses have a scope; in + * that case, the scope is the link. For multicast addresses, there are various + * scopes defined by RFC 4007 and others. For any constrained scope, a system + * must establish a (potentially one-to-many) mapping between zones and local + * interfaces. For example, a link-local address is valid on only one link (its + * zone). That link may be attached to one or more local interfaces. The + * decisions on which scopes are constrained and the mapping between zones and + * interfaces is together what we refer to as the "scoping policy" - more on + * this in a bit. + * + * In lwIP, each IPv6 address has an associated zone index. This zone index may + * be set to "no zone" (IP6_NO_ZONE, 0) or an actual zone. We say that an + * address "has a zone" or "is zoned" when its zone index is *not* set to "no + * zone." In lwIP, in principle, each address should be "properly zoned," which + * means that if the address has a zone if and only if has a scope. As such, it + * is a rule that an unscoped (e.g., global) address must never have a zone. + * Even though one could argue that there is always one zone even for global + * scopes, this rule exists for implementation simplicity. Violation of the + * rule will trigger assertions or otherwise result in undesired behavior. + * + * Backward compatibility prevents us from requiring that applications always + * provide properly zoned addresses. We do enforce the rule that the in the + * lwIP link layer (everything below netif->output_ip6() and in particular ND6) + * *all* addresses are properly zoned. Thus, on the output paths down the + * stack, various places deal with the case of addresses that lack a zone. + * Some of them are best-effort for efficiency (e.g. the PCB bind and connect + * API calls' attempts to add missing zones); ultimately the IPv6 output + * handler (@ref ip6_output_if_src) will set a zone if necessary. + * + * Aside from dealing with scoped addresses lacking a zone, a proper IPv6 + * implementation must also ensure that a packet with a scoped source and/or + * destination address does not leave its zone. This is currently implemented + * in the input and forward functions. However, for output, these checks are + * deliberately omitted in order to keep the implementation lightweight. The + * routing algorithm in @ref ip6_route will take decisions such that it will + * not cause zone violations unless the application sets bad addresses, though. + * + * In terms of scoping policy, lwIP implements the default policy from RFC 4007 + * using macros in this file. This policy considers link-local unicast + * addresses and (only) interface-local and link-local multicast addresses as + * having a scope. For all these addresses, the zone is equal to the interface. + * As shown below in this file, it is possible to implement a custom policy. + */ + +/* + * Copyright (c) 2017 The MINIX 3 Project. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: David van Moolenbroek + * + */ +#ifndef LWIP_HDR_IP6_ZONE_H +#define LWIP_HDR_IP6_ZONE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup ip6_zones IPv6 Zones + * @ingroup ip6 + * @{ + */ + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +/** Identifier for "no zone". */ +#define IP6_NO_ZONE 0 + +#if LWIP_IPV6_SCOPES + +/** Zone initializer for static IPv6 address initialization, including comma. */ +#define IPADDR6_ZONE_INIT , IP6_NO_ZONE + +/** Return the zone index of the given IPv6 address; possibly "no zone". */ +#define ip6_addr_zone(ip6addr) ((ip6addr)->zone) + +/** Does the given IPv6 address have a zone set? (0/1) */ +#define ip6_addr_has_zone(ip6addr) (ip6_addr_zone(ip6addr) != IP6_NO_ZONE) + +/** Set the zone field of an IPv6 address to a particular value. */ +#define ip6_addr_set_zone(ip6addr, zone_idx) ((ip6addr)->zone = (zone_idx)) + +/** Clear the zone field of an IPv6 address, setting it to "no zone". */ +#define ip6_addr_clear_zone(ip6addr) ((ip6addr)->zone = IP6_NO_ZONE) + +/** Copy the zone field from the second IPv6 address to the first one. */ +#define ip6_addr_copy_zone(ip6addr1, ip6addr2) ((ip6addr1).zone = (ip6addr2).zone) + +/** Is the zone field of the given IPv6 address equal to the given zone index? (0/1) */ +#define ip6_addr_equals_zone(ip6addr, zone_idx) ((ip6addr)->zone == (zone_idx)) + +/** Are the zone fields of the given IPv6 addresses equal? (0/1) + * This macro must only be used on IPv6 addresses of the same scope. */ +#define ip6_addr_cmp_zone(ip6addr1, ip6addr2) ((ip6addr1)->zone == (ip6addr2)->zone) + +/** Symbolic constants for the 'type' parameters in some of the macros. + * These exist for efficiency only, allowing the macros to avoid certain tests + * when the address is known not to be of a certain type. Dead code elimination + * will do the rest. IP6_MULTICAST is supported but currently not optimized. + * @see ip6_addr_has_scope, ip6_addr_assign_zone, ip6_addr_lacks_zone. + */ +enum lwip_ipv6_scope_type +{ + /** Unknown */ + IP6_UNKNOWN = 0, + /** Unicast */ + IP6_UNICAST = 1, + /** Multicast */ + IP6_MULTICAST = 2 +}; + +/** IPV6_CUSTOM_SCOPES: together, the following three macro definitions, + * @ref ip6_addr_has_scope, @ref ip6_addr_assign_zone, and + * @ref ip6_addr_test_zone, completely define the lwIP scoping policy. + * The definitions below implement the default policy from RFC 4007 Sec. 6. + * Should an implementation desire to implement a different policy, it can + * define IPV6_CUSTOM_SCOPES to 1 and supply its own definitions for the three + * macros instead. + */ +#ifndef IPV6_CUSTOM_SCOPES +#define IPV6_CUSTOM_SCOPES 0 +#endif /* !IPV6_CUSTOM_SCOPES */ + +#if !IPV6_CUSTOM_SCOPES + +/** + * Determine whether an IPv6 address has a constrained scope, and as such is + * meaningful only if accompanied by a zone index to identify the scope's zone. + * The given address type may be used to eliminate at compile time certain + * checks that will evaluate to false at run time anyway. + * + * This default implementation follows the default model of RFC 4007, where + * only interface-local and link-local scopes are defined. + * + * Even though the unicast loopback address does have an implied link-local + * scope, in this implementation it does not have an explicitly assigned zone + * index. As such it should not be tested for in this macro. + * + * @param ip6addr the IPv6 address (const); only its address part is examined. + * @param type address type; see @ref lwip_ipv6_scope_type. + * @return 1 if the address has a constrained scope, 0 if it does not. + */ +#define ip6_addr_has_scope(ip6addr, type) \ + (ip6_addr_islinklocal(ip6addr) || (((type) != IP6_UNICAST) && \ + (ip6_addr_ismulticast_iflocal(ip6addr) || \ + ip6_addr_ismulticast_linklocal(ip6addr)))) + +/** + * Assign a zone index to an IPv6 address, based on a network interface. If the + * given address has a scope, the assigned zone index is that scope's zone of + * the given netif; otherwise, the assigned zone index is "no zone". + * + * This default implementation follows the default model of RFC 4007, where + * only interface-local and link-local scopes are defined, and the zone index + * of both of those scopes always equals the index of the network interface. + * As such, this default implementation need not distinguish between different + * constrained scopes when assigning the zone. + * + * @param ip6addr the IPv6 address; its address part is examined, and its zone + * index is assigned. + * @param type address type; see @ref lwip_ipv6_scope_type. + * @param netif the network interface (const). + */ +#define ip6_addr_assign_zone(ip6addr, type, netif) \ + (ip6_addr_set_zone((ip6addr), \ + ip6_addr_has_scope((ip6addr), (type)) ? netif_get_index(netif) : 0)) + +/** + * Test whether an IPv6 address is "zone-compatible" with a network interface. + * That is, test whether the network interface is part of the zone associated + * with the address. For efficiency, this macro is only ever called if the + * given address is either scoped or zoned, and thus, it need not test this. + * If an address is scoped but not zoned, or zoned and not scoped, it is + * considered not zone-compatible with any netif. + * + * This default implementation follows the default model of RFC 4007, where + * only interface-local and link-local scopes are defined, and the zone index + * of both of those scopes always equals the index of the network interface. + * As such, there is always only one matching netif for a specific zone index, + * but all call sites of this macro currently support multiple matching netifs + * as well (at no additional expense in the common case). + * + * @param ip6addr the IPv6 address (const). + * @param netif the network interface (const). + * @return 1 if the address is scope-compatible with the netif, 0 if not. + */ +#define ip6_addr_test_zone(ip6addr, netif) \ + (ip6_addr_equals_zone((ip6addr), netif_get_index(netif))) + +#endif /* !IPV6_CUSTOM_SCOPES */ + +/** Does the given IPv6 address have a scope, and as such should also have a + * zone to be meaningful, but does not actually have a zone? (0/1) */ +#define ip6_addr_lacks_zone(ip6addr, type) \ + (!ip6_addr_has_zone(ip6addr) && ip6_addr_has_scope((ip6addr), (type))) + +/** + * Try to select a zone for a scoped address that does not yet have a zone. + * Called from PCB bind and connect routines, for two reasons: 1) to save on + * this (relatively expensive) selection for every individual packet route + * operation and 2) to allow the application to obtain the selected zone from + * the PCB as is customary for e.g. getsockname/getpeername BSD socket calls. + * + * Ideally, callers would always supply a properly zoned address, in which case + * this function would not be needed. It exists both for compatibility with the + * BSD socket API (which accepts zoneless destination addresses) and for + * backward compatibility with pre-scoping lwIP code. + * + * It may be impossible to select a zone, e.g. if there are no netifs. In that + * case, the address's zone field will be left as is. + * + * @param dest the IPv6 address for which to select and set a zone. + * @param src source IPv6 address (const); may be equal to dest. + */ +#define ip6_addr_select_zone(dest, src) do { struct netif *selected_netif; \ + selected_netif = ip6_route((src), (dest)); \ + if (selected_netif != NULL) { \ + ip6_addr_assign_zone((dest), IP6_UNKNOWN, selected_netif); \ + } } while (0) + +/** + * @} + */ + +#else /* LWIP_IPV6_SCOPES */ + +#define IPADDR6_ZONE_INIT +#define ip6_addr_zone(ip6addr) (IP6_NO_ZONE) +#define ip6_addr_has_zone(ip6addr) (0) +#define ip6_addr_set_zone(ip6addr, zone_idx) +#define ip6_addr_clear_zone(ip6addr) +#define ip6_addr_copy_zone(ip6addr1, ip6addr2) +#define ip6_addr_equals_zone(ip6addr, zone_idx) (1) +#define ip6_addr_cmp_zone(ip6addr1, ip6addr2) (1) +#define IPV6_CUSTOM_SCOPES 0 +#define ip6_addr_has_scope(ip6addr, type) (0) +#define ip6_addr_assign_zone(ip6addr, type, netif) +#define ip6_addr_test_zone(ip6addr, netif) (1) +#define ip6_addr_lacks_zone(ip6addr, type) (0) +#define ip6_addr_select_zone(ip6addr, src) + +#endif /* LWIP_IPV6_SCOPES */ + +#if LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG + +/** Verify that the given IPv6 address is properly zoned. */ +#define IP6_ADDR_ZONECHECK(ip6addr) LWIP_ASSERT("IPv6 zone check failed", \ + ip6_addr_has_scope(ip6addr, IP6_UNKNOWN) == ip6_addr_has_zone(ip6addr)) + +/** Verify that the given IPv6 address is properly zoned for the given netif. */ +#define IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif) LWIP_ASSERT("IPv6 netif zone check failed", \ + ip6_addr_has_scope(ip6addr, IP6_UNKNOWN) ? \ + (ip6_addr_has_zone(ip6addr) && \ + (((netif) == NULL) || ip6_addr_test_zone((ip6addr), (netif)))) : \ + !ip6_addr_has_zone(ip6addr)) + +#else /* LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG */ + +#define IP6_ADDR_ZONECHECK(ip6addr) +#define IP6_ADDR_ZONECHECK_NETIF(ip6addr, netif) + +#endif /* LWIP_IPV6_SCOPES && LWIP_IPV6_SCOPES_DEBUG */ + +#endif /* LWIP_IPV6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_IP6_ZONE_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h b/Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h new file mode 100644 index 0000000..2f97770 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/ip_addr.h @@ -0,0 +1,438 @@ +/** + * @file + * IP address API (common IPv4 and IPv6) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_IP_ADDR_H +#define LWIP_HDR_IP_ADDR_H + +#include "lwip/opt.h" +#include "lwip/def.h" + +#include "lwip/ip4_addr.h" +#include "lwip/ip6_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @ingroup ipaddr + * IP address types for use in ip_addr_t.type member. + * @see tcp_new_ip_type(), udp_new_ip_type(), raw_new_ip_type(). + */ +enum lwip_ip_addr_type { + /** IPv4 */ + IPADDR_TYPE_V4 = 0U, + /** IPv6 */ + IPADDR_TYPE_V6 = 6U, + /** IPv4+IPv6 ("dual-stack") */ + IPADDR_TYPE_ANY = 46U +}; + +#if LWIP_IPV4 && LWIP_IPV6 +/** + * @ingroup ipaddr + * A union struct for both IP version's addresses. + * ATTENTION: watch out for its size when adding IPv6 address scope! + */ +typedef struct ip_addr { + union { + ip6_addr_t ip6; + ip4_addr_t ip4; + } u_addr; + /** @ref lwip_ip_addr_type */ + u8_t type; +} ip_addr_t; + +extern const ip_addr_t ip_addr_any_type; + +/** @ingroup ip4addr */ +#define IPADDR4_INIT(u32val) { { { { u32val, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V4 } +/** @ingroup ip4addr */ +#define IPADDR4_INIT_BYTES(a,b,c,d) IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d))) + +/** @ingroup ip6addr */ +#define IPADDR6_INIT(a, b, c, d) { { { { a, b, c, d } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V6 } +/** @ingroup ip6addr */ +#define IPADDR6_INIT_HOST(a, b, c, d) { { { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_V6 } + +/** @ingroup ipaddr */ +#define IP_IS_ANY_TYPE_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_ANY) +/** @ingroup ipaddr */ +#define IPADDR_ANY_TYPE_INIT { { { { 0ul, 0ul, 0ul, 0ul } IPADDR6_ZONE_INIT } }, IPADDR_TYPE_ANY } + +/** @ingroup ip4addr */ +#define IP_IS_V4_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4) +/** @ingroup ip6addr */ +#define IP_IS_V6_VAL(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V6) +/** @ingroup ip4addr */ +#define IP_IS_V4(ipaddr) (((ipaddr) == NULL) || IP_IS_V4_VAL(*(ipaddr))) +/** @ingroup ip6addr */ +#define IP_IS_V6(ipaddr) (((ipaddr) != NULL) && IP_IS_V6_VAL(*(ipaddr))) + +#define IP_SET_TYPE_VAL(ipaddr, iptype) do { (ipaddr).type = (iptype); }while(0) +#define IP_SET_TYPE(ipaddr, iptype) do { if((ipaddr) != NULL) { IP_SET_TYPE_VAL(*(ipaddr), iptype); }}while(0) +#define IP_GET_TYPE(ipaddr) ((ipaddr)->type) + +#define IP_ADDR_RAW_SIZE(ipaddr) (IP_GET_TYPE(&ipaddr) == IPADDR_TYPE_V4 ? sizeof(ip4_addr_t) : sizeof(ip6_addr_t)) + +#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) (IP_GET_TYPE(&pcb->local_ip) == IP_GET_TYPE(ipaddr)) +#define IP_ADDR_PCB_VERSION_MATCH(pcb, ipaddr) (IP_IS_ANY_TYPE_VAL(pcb->local_ip) || IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr)) + +/** @ingroup ip6addr + * Convert generic ip address to specific protocol version + */ +#define ip_2_ip6(ipaddr) (&((ipaddr)->u_addr.ip6)) +/** @ingroup ip4addr + * Convert generic ip address to specific protocol version + */ +#define ip_2_ip4(ipaddr) (&((ipaddr)->u_addr.ip4)) + +/** @ingroup ip4addr */ +#define IP_ADDR4(ipaddr,a,b,c,d) do { IP4_ADDR(ip_2_ip4(ipaddr),a,b,c,d); \ + IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V4); } while(0) +/** @ingroup ip6addr */ +#define IP_ADDR6(ipaddr,i0,i1,i2,i3) do { IP6_ADDR(ip_2_ip6(ipaddr),i0,i1,i2,i3); \ + IP_SET_TYPE_VAL(*(ipaddr), IPADDR_TYPE_V6); } while(0) +/** @ingroup ip6addr */ +#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3) IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3)) + +#define ip_clear_no4(ipaddr) do { ip_2_ip6(ipaddr)->addr[1] = \ + ip_2_ip6(ipaddr)->addr[2] = \ + ip_2_ip6(ipaddr)->addr[3] = 0; \ + ip6_addr_clear_zone(ip_2_ip6(ipaddr)); }while(0) + +/** @ingroup ipaddr */ +#define ip_addr_copy(dest, src) do{ IP_SET_TYPE_VAL(dest, IP_GET_TYPE(&src)); if(IP_IS_V6_VAL(src)){ \ + ip6_addr_copy(*ip_2_ip6(&(dest)), *ip_2_ip6(&(src))); }else{ \ + ip4_addr_copy(*ip_2_ip4(&(dest)), *ip_2_ip4(&(src))); ip_clear_no4(&dest); }}while(0) +/** @ingroup ip6addr */ +#define ip_addr_copy_from_ip6(dest, src) do{ \ + ip6_addr_copy(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0) +/** @ingroup ip6addr */ +#define ip_addr_copy_from_ip6_packed(dest, src) do{ \ + ip6_addr_copy_from_packed(*ip_2_ip6(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V6); }while(0) +/** @ingroup ip4addr */ +#define ip_addr_copy_from_ip4(dest, src) do{ \ + ip4_addr_copy(*ip_2_ip4(&(dest)), src); IP_SET_TYPE_VAL(dest, IPADDR_TYPE_V4); ip_clear_no4(&dest); }while(0) +/** @ingroup ip4addr */ +#define ip_addr_set_ip4_u32(ipaddr, val) do{if(ipaddr){ip4_addr_set_u32(ip_2_ip4(ipaddr), val); \ + IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0) +/** @ingroup ip4addr */ +#define ip_addr_set_ip4_u32_val(ipaddr, val) do{ ip4_addr_set_u32(ip_2_ip4(&(ipaddr)), val); \ + IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }while(0) +/** @ingroup ip4addr */ +#define ip_addr_get_ip4_u32(ipaddr) (((ipaddr) && IP_IS_V4(ipaddr)) ? \ + ip4_addr_get_u32(ip_2_ip4(ipaddr)) : 0) +/** @ingroup ipaddr */ +#define ip_addr_set(dest, src) do{ IP_SET_TYPE(dest, IP_GET_TYPE(src)); if(IP_IS_V6(src)){ \ + ip6_addr_set(ip_2_ip6(dest), ip_2_ip6(src)); }else{ \ + ip4_addr_set(ip_2_ip4(dest), ip_2_ip4(src)); ip_clear_no4(dest); }}while(0) +/** @ingroup ipaddr */ +#define ip_addr_set_ipaddr(dest, src) ip_addr_set(dest, src) +/** @ingroup ipaddr */ +#define ip_addr_set_zero(ipaddr) do{ \ + ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, 0); }while(0) +/** @ingroup ip5addr */ +#define ip_addr_set_zero_ip4(ipaddr) do{ \ + ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); }while(0) +/** @ingroup ip6addr */ +#define ip_addr_set_zero_ip6(ipaddr) do{ \ + ip6_addr_set_zero(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }while(0) +/** @ingroup ipaddr */ +#define ip_addr_set_any(is_ipv6, ipaddr) do{if(is_ipv6){ \ + ip6_addr_set_any(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \ + ip4_addr_set_any(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0) +/** @ingroup ipaddr */ +#define ip_addr_set_any_val(is_ipv6, ipaddr) do{if(is_ipv6){ \ + ip6_addr_set_any(ip_2_ip6(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V6); }else{ \ + ip4_addr_set_any(ip_2_ip4(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }}while(0) +/** @ingroup ipaddr */ +#define ip_addr_set_loopback(is_ipv6, ipaddr) do{if(is_ipv6){ \ + ip6_addr_set_loopback(ip_2_ip6(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V6); }else{ \ + ip4_addr_set_loopback(ip_2_ip4(ipaddr)); IP_SET_TYPE(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0) +/** @ingroup ipaddr */ +#define ip_addr_set_loopback_val(is_ipv6, ipaddr) do{if(is_ipv6){ \ + ip6_addr_set_loopback(ip_2_ip6(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V6); }else{ \ + ip4_addr_set_loopback(ip_2_ip4(&(ipaddr))); IP_SET_TYPE_VAL(ipaddr, IPADDR_TYPE_V4); ip_clear_no4(&ipaddr); }}while(0) +/** @ingroup ipaddr */ +#define ip_addr_set_hton(dest, src) do{if(IP_IS_V6(src)){ \ + ip6_addr_set_hton(ip_2_ip6(dest), ip_2_ip6(src)); IP_SET_TYPE(dest, IPADDR_TYPE_V6); }else{ \ + ip4_addr_set_hton(ip_2_ip4(dest), ip_2_ip4(src)); IP_SET_TYPE(dest, IPADDR_TYPE_V4); ip_clear_no4(ipaddr); }}while(0) +/** @ingroup ipaddr */ +#define ip_addr_get_network(target, host, netmask) do{if(IP_IS_V6(host)){ \ + ip4_addr_set_zero(ip_2_ip4(target)); IP_SET_TYPE(target, IPADDR_TYPE_V6); } else { \ + ip4_addr_get_network(ip_2_ip4(target), ip_2_ip4(host), ip_2_ip4(netmask)); IP_SET_TYPE(target, IPADDR_TYPE_V4); }}while(0) +/** @ingroup ipaddr */ +#define ip_addr_netcmp(addr1, addr2, mask) ((IP_IS_V6(addr1) && IP_IS_V6(addr2)) ? \ + 0 : \ + ip4_addr_netcmp(ip_2_ip4(addr1), ip_2_ip4(addr2), mask)) +/** @ingroup ipaddr */ +#define ip_addr_cmp(addr1, addr2) ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \ + ip6_addr_cmp(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \ + ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2)))) +/** @ingroup ipaddr */ +#define ip_addr_cmp_zoneless(addr1, addr2) ((IP_GET_TYPE(addr1) != IP_GET_TYPE(addr2)) ? 0 : (IP_IS_V6_VAL(*(addr1)) ? \ + ip6_addr_cmp_zoneless(ip_2_ip6(addr1), ip_2_ip6(addr2)) : \ + ip4_addr_cmp(ip_2_ip4(addr1), ip_2_ip4(addr2)))) +/** @ingroup ipaddr */ +#define ip_addr_isany(ipaddr) (((ipaddr) == NULL) ? 1 : ((IP_IS_V6(ipaddr)) ? \ + ip6_addr_isany(ip_2_ip6(ipaddr)) : \ + ip4_addr_isany(ip_2_ip4(ipaddr)))) +/** @ingroup ipaddr */ +#define ip_addr_isany_val(ipaddr) ((IP_IS_V6_VAL(ipaddr)) ? \ + ip6_addr_isany_val(*ip_2_ip6(&(ipaddr))) : \ + ip4_addr_isany_val(*ip_2_ip4(&(ipaddr)))) +/** @ingroup ipaddr */ +#define ip_addr_isbroadcast(ipaddr, netif) ((IP_IS_V6(ipaddr)) ? \ + 0 : \ + ip4_addr_isbroadcast(ip_2_ip4(ipaddr), netif)) +/** @ingroup ipaddr */ +#define ip_addr_ismulticast(ipaddr) ((IP_IS_V6(ipaddr)) ? \ + ip6_addr_ismulticast(ip_2_ip6(ipaddr)) : \ + ip4_addr_ismulticast(ip_2_ip4(ipaddr))) +/** @ingroup ipaddr */ +#define ip_addr_isloopback(ipaddr) ((IP_IS_V6(ipaddr)) ? \ + ip6_addr_isloopback(ip_2_ip6(ipaddr)) : \ + ip4_addr_isloopback(ip_2_ip4(ipaddr))) +/** @ingroup ipaddr */ +#define ip_addr_islinklocal(ipaddr) ((IP_IS_V6(ipaddr)) ? \ + ip6_addr_islinklocal(ip_2_ip6(ipaddr)) : \ + ip4_addr_islinklocal(ip_2_ip4(ipaddr))) +#define ip_addr_debug_print(debug, ipaddr) do { if(IP_IS_V6(ipaddr)) { \ + ip6_addr_debug_print(debug, ip_2_ip6(ipaddr)); } else { \ + ip4_addr_debug_print(debug, ip_2_ip4(ipaddr)); }}while(0) +#define ip_addr_debug_print_val(debug, ipaddr) do { if(IP_IS_V6_VAL(ipaddr)) { \ + ip6_addr_debug_print_val(debug, *ip_2_ip6(&(ipaddr))); } else { \ + ip4_addr_debug_print_val(debug, *ip_2_ip4(&(ipaddr))); }}while(0) +char *ipaddr_ntoa(const ip_addr_t *addr); +char *ipaddr_ntoa_r(const ip_addr_t *addr, char *buf, int buflen); +int ipaddr_aton(const char *cp, ip_addr_t *addr); + +/** @ingroup ipaddr */ +#define IPADDR_STRLEN_MAX IP6ADDR_STRLEN_MAX + +/** @ingroup ipaddr */ +#define ip4_2_ipv4_mapped_ipv6(ip6addr, ip4addr) do { \ + (ip6addr)->addr[3] = (ip4addr)->addr; \ + (ip6addr)->addr[2] = PP_HTONL(0x0000FFFFUL); \ + (ip6addr)->addr[1] = 0; \ + (ip6addr)->addr[0] = 0; \ + ip6_addr_clear_zone(ip6addr); } while(0); + +/** @ingroup ipaddr */ +#define unmap_ipv4_mapped_ipv6(ip4addr, ip6addr) \ + (ip4addr)->addr = (ip6addr)->addr[3]; + +#define IP46_ADDR_ANY(type) (((type) == IPADDR_TYPE_V6)? IP6_ADDR_ANY : IP4_ADDR_ANY) + +#else /* LWIP_IPV4 && LWIP_IPV6 */ + +#define IP_ADDR_PCB_VERSION_MATCH(addr, pcb) 1 +#define IP_ADDR_PCB_VERSION_MATCH_EXACT(pcb, ipaddr) 1 + +#define ip_addr_set_any_val(is_ipv6, ipaddr) ip_addr_set_any(is_ipv6, &(ipaddr)) +#define ip_addr_set_loopback_val(is_ipv6, ipaddr) ip_addr_set_loopback(is_ipv6, &(ipaddr)) + +#if LWIP_IPV4 + +typedef ip4_addr_t ip_addr_t; +#define IPADDR4_INIT(u32val) { u32val } +#define IPADDR4_INIT_BYTES(a,b,c,d) IPADDR4_INIT(PP_HTONL(LWIP_MAKEU32(a,b,c,d))) +#define IP_IS_V4_VAL(ipaddr) 1 +#define IP_IS_V6_VAL(ipaddr) 0 +#define IP_IS_V4(ipaddr) 1 +#define IP_IS_V6(ipaddr) 0 +#define IP_IS_ANY_TYPE_VAL(ipaddr) 0 +#define IP_SET_TYPE_VAL(ipaddr, iptype) +#define IP_SET_TYPE(ipaddr, iptype) +#define IP_GET_TYPE(ipaddr) IPADDR_TYPE_V4 +#define IP_ADDR_RAW_SIZE(ipaddr) sizeof(ip4_addr_t) +#define ip_2_ip4(ipaddr) (ipaddr) +#define IP_ADDR4(ipaddr,a,b,c,d) IP4_ADDR(ipaddr,a,b,c,d) + +#define ip_addr_copy(dest, src) ip4_addr_copy(dest, src) +#define ip_addr_copy_from_ip4(dest, src) ip4_addr_copy(dest, src) +#define ip_addr_set_ip4_u32(ipaddr, val) ip4_addr_set_u32(ip_2_ip4(ipaddr), val) +#define ip_addr_set_ip4_u32_val(ipaddr, val) ip_addr_set_ip4_u32(&(ipaddr), val) +#define ip_addr_get_ip4_u32(ipaddr) ip4_addr_get_u32(ip_2_ip4(ipaddr)) +#define ip_addr_set(dest, src) ip4_addr_set(dest, src) +#define ip_addr_set_ipaddr(dest, src) ip4_addr_set(dest, src) +#define ip_addr_set_zero(ipaddr) ip4_addr_set_zero(ipaddr) +#define ip_addr_set_zero_ip4(ipaddr) ip4_addr_set_zero(ipaddr) +#define ip_addr_set_any(is_ipv6, ipaddr) ip4_addr_set_any(ipaddr) +#define ip_addr_set_loopback(is_ipv6, ipaddr) ip4_addr_set_loopback(ipaddr) +#define ip_addr_set_hton(dest, src) ip4_addr_set_hton(dest, src) +#define ip_addr_get_network(target, host, mask) ip4_addr_get_network(target, host, mask) +#define ip_addr_netcmp(addr1, addr2, mask) ip4_addr_netcmp(addr1, addr2, mask) +#define ip_addr_cmp(addr1, addr2) ip4_addr_cmp(addr1, addr2) +#define ip_addr_isany(ipaddr) ip4_addr_isany(ipaddr) +#define ip_addr_isany_val(ipaddr) ip4_addr_isany_val(ipaddr) +#define ip_addr_isloopback(ipaddr) ip4_addr_isloopback(ipaddr) +#define ip_addr_islinklocal(ipaddr) ip4_addr_islinklocal(ipaddr) +#define ip_addr_isbroadcast(addr, netif) ip4_addr_isbroadcast(addr, netif) +#define ip_addr_ismulticast(ipaddr) ip4_addr_ismulticast(ipaddr) +#define ip_addr_debug_print(debug, ipaddr) ip4_addr_debug_print(debug, ipaddr) +#define ip_addr_debug_print_val(debug, ipaddr) ip4_addr_debug_print_val(debug, ipaddr) +#define ipaddr_ntoa(ipaddr) ip4addr_ntoa(ipaddr) +#define ipaddr_ntoa_r(ipaddr, buf, buflen) ip4addr_ntoa_r(ipaddr, buf, buflen) +#define ipaddr_aton(cp, addr) ip4addr_aton(cp, addr) + +#define IPADDR_STRLEN_MAX IP4ADDR_STRLEN_MAX + +#define IP46_ADDR_ANY(type) (IP4_ADDR_ANY) + +#else /* LWIP_IPV4 */ + +typedef ip6_addr_t ip_addr_t; +#define IPADDR6_INIT(a, b, c, d) { { a, b, c, d } IPADDR6_ZONE_INIT } +#define IPADDR6_INIT_HOST(a, b, c, d) { { PP_HTONL(a), PP_HTONL(b), PP_HTONL(c), PP_HTONL(d) } IPADDR6_ZONE_INIT } +#define IP_IS_V4_VAL(ipaddr) 0 +#define IP_IS_V6_VAL(ipaddr) 1 +#define IP_IS_V4(ipaddr) 0 +#define IP_IS_V6(ipaddr) 1 +#define IP_IS_ANY_TYPE_VAL(ipaddr) 0 +#define IP_SET_TYPE_VAL(ipaddr, iptype) +#define IP_SET_TYPE(ipaddr, iptype) +#define IP_GET_TYPE(ipaddr) IPADDR_TYPE_V6 +#define IP_ADDR_RAW_SIZE(ipaddr) sizeof(ip6_addr_t) +#define ip_2_ip6(ipaddr) (ipaddr) +#define IP_ADDR6(ipaddr,i0,i1,i2,i3) IP6_ADDR(ipaddr,i0,i1,i2,i3) +#define IP_ADDR6_HOST(ipaddr,i0,i1,i2,i3) IP_ADDR6(ipaddr,PP_HTONL(i0),PP_HTONL(i1),PP_HTONL(i2),PP_HTONL(i3)) + +#define ip_addr_copy(dest, src) ip6_addr_copy(dest, src) +#define ip_addr_copy_from_ip6(dest, src) ip6_addr_copy(dest, src) +#define ip_addr_copy_from_ip6_packed(dest, src) ip6_addr_copy_from_packed(dest, src) +#define ip_addr_set(dest, src) ip6_addr_set(dest, src) +#define ip_addr_set_ipaddr(dest, src) ip6_addr_set(dest, src) +#define ip_addr_set_zero(ipaddr) ip6_addr_set_zero(ipaddr) +#define ip_addr_set_zero_ip6(ipaddr) ip6_addr_set_zero(ipaddr) +#define ip_addr_set_any(is_ipv6, ipaddr) ip6_addr_set_any(ipaddr) +#define ip_addr_set_loopback(is_ipv6, ipaddr) ip6_addr_set_loopback(ipaddr) +#define ip_addr_set_hton(dest, src) ip6_addr_set_hton(dest, src) +#define ip_addr_get_network(target, host, mask) ip6_addr_set_zero(target) +#define ip_addr_netcmp(addr1, addr2, mask) 0 +#define ip_addr_cmp(addr1, addr2) ip6_addr_cmp(addr1, addr2) +#define ip_addr_cmp_zoneless(addr1, addr2) ip6_addr_cmp_zoneless(addr1, addr2) +#define ip_addr_isany(ipaddr) ip6_addr_isany(ipaddr) +#define ip_addr_isany_val(ipaddr) ip6_addr_isany_val(ipaddr) +#define ip_addr_isloopback(ipaddr) ip6_addr_isloopback(ipaddr) +#define ip_addr_islinklocal(ipaddr) ip6_addr_islinklocal(ipaddr) +#define ip_addr_isbroadcast(addr, netif) 0 +#define ip_addr_ismulticast(ipaddr) ip6_addr_ismulticast(ipaddr) +#define ip_addr_debug_print(debug, ipaddr) ip6_addr_debug_print(debug, ipaddr) +#define ip_addr_debug_print_val(debug, ipaddr) ip6_addr_debug_print_val(debug, ipaddr) +#define ipaddr_ntoa(ipaddr) ip6addr_ntoa(ipaddr) +#define ipaddr_ntoa_r(ipaddr, buf, buflen) ip6addr_ntoa_r(ipaddr, buf, buflen) +#define ipaddr_aton(cp, addr) ip6addr_aton(cp, addr) + +#define IPADDR_STRLEN_MAX IP6ADDR_STRLEN_MAX + +#define IP46_ADDR_ANY(type) (IP6_ADDR_ANY) + +#endif /* LWIP_IPV4 */ +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +#if LWIP_IPV4 + +extern const ip_addr_t ip_addr_any; +extern const ip_addr_t ip_addr_broadcast; + +/** + * @ingroup ip4addr + * Can be used as a fixed/const ip_addr_t + * for the IP wildcard. + * Defined to @ref IP4_ADDR_ANY when IPv4 is enabled. + * Defined to @ref IP6_ADDR_ANY in IPv6 only systems. + * Use this if you can handle IPv4 _AND_ IPv6 addresses. + * Use @ref IP4_ADDR_ANY or @ref IP6_ADDR_ANY when the IP + * type matters. + */ +#define IP_ADDR_ANY IP4_ADDR_ANY +/** + * @ingroup ip4addr + * Can be used as a fixed/const ip_addr_t + * for the IPv4 wildcard and the broadcast address + */ +#define IP4_ADDR_ANY (&ip_addr_any) +/** + * @ingroup ip4addr + * Can be used as a fixed/const ip4_addr_t + * for the wildcard and the broadcast address + */ +#define IP4_ADDR_ANY4 (ip_2_ip4(&ip_addr_any)) + +/** @ingroup ip4addr */ +#define IP_ADDR_BROADCAST (&ip_addr_broadcast) +/** @ingroup ip4addr */ +#define IP4_ADDR_BROADCAST (ip_2_ip4(&ip_addr_broadcast)) + +#endif /* LWIP_IPV4*/ + +#if LWIP_IPV6 + +extern const ip_addr_t ip6_addr_any; + +/** + * @ingroup ip6addr + * IP6_ADDR_ANY can be used as a fixed ip_addr_t + * for the IPv6 wildcard address + */ +#define IP6_ADDR_ANY (&ip6_addr_any) +/** + * @ingroup ip6addr + * IP6_ADDR_ANY6 can be used as a fixed ip6_addr_t + * for the IPv6 wildcard address + */ +#define IP6_ADDR_ANY6 (ip_2_ip6(&ip6_addr_any)) + +#if !LWIP_IPV4 +/** IPv6-only configurations */ +#define IP_ADDR_ANY IP6_ADDR_ANY +#endif /* !LWIP_IPV4 */ + +#endif + +#if LWIP_IPV4 && LWIP_IPV6 +/** @ingroup ipaddr */ +#define IP_ANY_TYPE (&ip_addr_any_type) +#else +#define IP_ANY_TYPE IP_ADDR_ANY +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_IP_ADDR_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/mem.h b/Middlewares/Third_Party/LwIP/src/include/lwip/mem.h new file mode 100644 index 0000000..ff208d2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/mem.h @@ -0,0 +1,82 @@ +/** + * @file + * Heap API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_MEM_H +#define LWIP_HDR_MEM_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if MEM_LIBC_MALLOC + +#include "lwip/arch.h" + +typedef size_t mem_size_t; +#define MEM_SIZE_F SZT_F + +#elif MEM_USE_POOLS + +typedef u16_t mem_size_t; +#define MEM_SIZE_F U16_F + +#else + +/* MEM_SIZE would have to be aligned, but using 64000 here instead of + * 65535 leaves some room for alignment... + */ +#if MEM_SIZE > 64000L +typedef u32_t mem_size_t; +#define MEM_SIZE_F U32_F +#else +typedef u16_t mem_size_t; +#define MEM_SIZE_F U16_F +#endif /* MEM_SIZE > 64000 */ +#endif + +void mem_init(void); +void *mem_trim(void *mem, mem_size_t size); +void *mem_malloc(mem_size_t size); +void *mem_calloc(mem_size_t count, mem_size_t size); +void mem_free(void *mem); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_MEM_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/memp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/memp.h new file mode 100644 index 0000000..1630b26 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/memp.h @@ -0,0 +1,155 @@ +/** + * @file + * Memory pool API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef LWIP_HDR_MEMP_H +#define LWIP_HDR_MEMP_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* run once with empty definition to handle all custom includes in lwippools.h */ +#define LWIP_MEMPOOL(name,num,size,desc) +#include "lwip/priv/memp_std.h" + +/** Create the list of all memory pools managed by memp. MEMP_MAX represents a NULL pool at the end */ +typedef enum { +#define LWIP_MEMPOOL(name,num,size,desc) MEMP_##name, +#include "lwip/priv/memp_std.h" + MEMP_MAX +} memp_t; + +#include "lwip/priv/memp_priv.h" +#include "lwip/stats.h" + +extern const struct memp_desc* const memp_pools[MEMP_MAX]; + +/** + * @ingroup mempool + * Declare prototype for private memory pool if it is used in multiple files + */ +#define LWIP_MEMPOOL_PROTOTYPE(name) extern const struct memp_desc memp_ ## name + +#if MEMP_MEM_MALLOC + +#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \ + LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \ + const struct memp_desc memp_ ## name = { \ + DECLARE_LWIP_MEMPOOL_DESC(desc) \ + LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \ + LWIP_MEM_ALIGN_SIZE(size) \ + }; + +#else /* MEMP_MEM_MALLOC */ + +/** + * @ingroup mempool + * Declare a private memory pool + * Private mempools example: + * .h: only when pool is used in multiple .c files: LWIP_MEMPOOL_PROTOTYPE(my_private_pool); + * .c: + * - in global variables section: LWIP_MEMPOOL_DECLARE(my_private_pool, 10, sizeof(foo), "Some description") + * - call ONCE before using pool (e.g. in some init() function): LWIP_MEMPOOL_INIT(my_private_pool); + * - allocate: void* my_new_mem = LWIP_MEMPOOL_ALLOC(my_private_pool); + * - free: LWIP_MEMPOOL_FREE(my_private_pool, my_new_mem); + * + * To relocate a pool, declare it as extern in cc.h. Example for GCC: + * extern u8_t \_\_attribute\_\_((section(".onchip_mem"))) memp_memory_my_private_pool_base[]; + */ +#define LWIP_MEMPOOL_DECLARE(name,num,size,desc) \ + LWIP_DECLARE_MEMORY_ALIGNED(memp_memory_ ## name ## _base, ((num) * (MEMP_SIZE + MEMP_ALIGN_SIZE(size)))); \ + \ + LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(memp_stats_ ## name) \ + \ + static struct memp *memp_tab_ ## name; \ + \ + const struct memp_desc memp_ ## name = { \ + DECLARE_LWIP_MEMPOOL_DESC(desc) \ + LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(memp_stats_ ## name) \ + LWIP_MEM_ALIGN_SIZE(size), \ + (num), \ + memp_memory_ ## name ## _base, \ + &memp_tab_ ## name \ + }; + +#endif /* MEMP_MEM_MALLOC */ + +/** + * @ingroup mempool + * Initialize a private memory pool + */ +#define LWIP_MEMPOOL_INIT(name) memp_init_pool(&memp_ ## name) +/** + * @ingroup mempool + * Allocate from a private memory pool + */ +#define LWIP_MEMPOOL_ALLOC(name) memp_malloc_pool(&memp_ ## name) +/** + * @ingroup mempool + * Free element from a private memory pool + */ +#define LWIP_MEMPOOL_FREE(name, x) memp_free_pool(&memp_ ## name, (x)) + +#if MEM_USE_POOLS +/** This structure is used to save the pool one element came from. + * This has to be defined here as it is required for pool size calculation. */ +struct memp_malloc_helper +{ + memp_t poolnr; +#if MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) + u16_t size; +#endif /* MEMP_OVERFLOW_CHECK || (LWIP_STATS && MEM_STATS) */ +}; +#endif /* MEM_USE_POOLS */ + +void memp_init(void); + +#if MEMP_OVERFLOW_CHECK +void *memp_malloc_fn(memp_t type, const char* file, const int line); +#define memp_malloc(t) memp_malloc_fn((t), __FILE__, __LINE__) +#else +void *memp_malloc(memp_t type); +#endif +void memp_free(memp_t type, void *mem); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_MEMP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h new file mode 100644 index 0000000..7fa0797 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/mld6.h @@ -0,0 +1,99 @@ +/** + * @file + * + * Multicast listener discovery for IPv6. Aims to be compliant with RFC 2710. + * No support for MLDv2. + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#ifndef LWIP_HDR_MLD6_H +#define LWIP_HDR_MLD6_H + +#include "lwip/opt.h" + +#if LWIP_IPV6_MLD && LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** MLD group */ +struct mld_group { + /** next link */ + struct mld_group *next; + /** multicast address */ + ip6_addr_t group_address; + /** signifies we were the last person to report */ + u8_t last_reporter_flag; + /** current state of the group */ + u8_t group_state; + /** timer for reporting */ + u16_t timer; + /** counter of simultaneous uses */ + u8_t use; +}; + +#define MLD6_TMR_INTERVAL 100 /* Milliseconds */ + +err_t mld6_stop(struct netif *netif); +void mld6_report_groups(struct netif *netif); +void mld6_tmr(void); +struct mld_group *mld6_lookfor_group(struct netif *ifp, const ip6_addr_t *addr); +void mld6_input(struct pbuf *p, struct netif *inp); +err_t mld6_joingroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr); +err_t mld6_joingroup_netif(struct netif *netif, const ip6_addr_t *groupaddr); +err_t mld6_leavegroup(const ip6_addr_t *srcaddr, const ip6_addr_t *groupaddr); +err_t mld6_leavegroup_netif(struct netif *netif, const ip6_addr_t *groupaddr); + +/** @ingroup mld6 + * Get list head of MLD6 groups for netif. + * Note: The allnodes group IP is NOT in the list, since it must always + * be received for correct IPv6 operation. + * @see @ref netif_set_mld_mac_filter() + */ +#define netif_mld6_data(netif) ((struct mld_group *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_MLD6)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6_MLD && LWIP_IPV6 */ + +#endif /* LWIP_HDR_MLD6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h new file mode 100644 index 0000000..c30e624 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/nd6.h @@ -0,0 +1,90 @@ +/** + * @file + * + * Neighbor discovery and stateless address autoconfiguration for IPv6. + * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 + * (Address autoconfiguration). + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#ifndef LWIP_HDR_ND6_H +#define LWIP_HDR_ND6_H + +#include "lwip/opt.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip6_addr.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** 1 second period */ +#define ND6_TMR_INTERVAL 1000 + +/** Router solicitations are sent in 4 second intervals (see RFC 4861, ch. 6.3.7) */ +#ifndef ND6_RTR_SOLICITATION_INTERVAL +#define ND6_RTR_SOLICITATION_INTERVAL 4000 +#endif + +struct pbuf; +struct netif; + +void nd6_tmr(void); +void nd6_input(struct pbuf *p, struct netif *inp); +void nd6_clear_destination_cache(void); +struct netif *nd6_find_route(const ip6_addr_t *ip6addr); +err_t nd6_get_next_hop_addr_or_queue(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr, const u8_t **hwaddrp); +u16_t nd6_get_destination_mtu(const ip6_addr_t *ip6addr, struct netif *netif); +#if LWIP_ND6_TCP_REACHABILITY_HINTS +void nd6_reachability_hint(const ip6_addr_t *ip6addr); +#endif /* LWIP_ND6_TCP_REACHABILITY_HINTS */ +void nd6_cleanup_netif(struct netif *netif); +#if LWIP_IPV6_MLD +void nd6_adjust_mld_membership(struct netif *netif, s8_t addr_idx, u8_t new_state); +#endif /* LWIP_IPV6_MLD */ +void nd6_restart_netif(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 */ + +#endif /* LWIP_HDR_ND6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h b/Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h new file mode 100644 index 0000000..42a911b --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/netbuf.h @@ -0,0 +1,116 @@ +/** + * @file + * netbuf API (for netconn API) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_NETBUF_H +#define LWIP_HDR_NETBUF_H + +#include "lwip/opt.h" + +#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ +/* Note: Netconn API is always available when sockets are enabled - + * sockets are implemented on top of them */ + +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/ip6_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** This netbuf has dest-addr/port set */ +#define NETBUF_FLAG_DESTADDR 0x01 +/** This netbuf includes a checksum */ +#define NETBUF_FLAG_CHKSUM 0x02 + +/** "Network buffer" - contains data and addressing info */ +struct netbuf { + struct pbuf *p, *ptr; + ip_addr_t addr; + u16_t port; +#if LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY + u8_t flags; + u16_t toport_chksum; +#if LWIP_NETBUF_RECVINFO + ip_addr_t toaddr; +#endif /* LWIP_NETBUF_RECVINFO */ +#endif /* LWIP_NETBUF_RECVINFO || LWIP_CHECKSUM_ON_COPY */ +}; + +/* Network buffer functions: */ +struct netbuf * netbuf_new (void); +void netbuf_delete (struct netbuf *buf); +void * netbuf_alloc (struct netbuf *buf, u16_t size); +void netbuf_free (struct netbuf *buf); +err_t netbuf_ref (struct netbuf *buf, + const void *dataptr, u16_t size); +void netbuf_chain (struct netbuf *head, struct netbuf *tail); + +err_t netbuf_data (struct netbuf *buf, + void **dataptr, u16_t *len); +s8_t netbuf_next (struct netbuf *buf); +void netbuf_first (struct netbuf *buf); + + +#define netbuf_copy_partial(buf, dataptr, len, offset) \ + pbuf_copy_partial((buf)->p, (dataptr), (len), (offset)) +#define netbuf_copy(buf,dataptr,len) netbuf_copy_partial(buf, dataptr, len, 0) +#define netbuf_take(buf, dataptr, len) pbuf_take((buf)->p, dataptr, len) +#define netbuf_len(buf) ((buf)->p->tot_len) +#define netbuf_fromaddr(buf) (&((buf)->addr)) +#define netbuf_set_fromaddr(buf, fromaddr) ip_addr_set(&((buf)->addr), fromaddr) +#define netbuf_fromport(buf) ((buf)->port) +#if LWIP_NETBUF_RECVINFO +#define netbuf_destaddr(buf) (&((buf)->toaddr)) +#define netbuf_set_destaddr(buf, destaddr) ip_addr_set(&((buf)->toaddr), destaddr) +#if LWIP_CHECKSUM_ON_COPY +#define netbuf_destport(buf) (((buf)->flags & NETBUF_FLAG_DESTADDR) ? (buf)->toport_chksum : 0) +#else /* LWIP_CHECKSUM_ON_COPY */ +#define netbuf_destport(buf) ((buf)->toport_chksum) +#endif /* LWIP_CHECKSUM_ON_COPY */ +#endif /* LWIP_NETBUF_RECVINFO */ +#if LWIP_CHECKSUM_ON_COPY +#define netbuf_set_chksum(buf, chksum) do { (buf)->flags = NETBUF_FLAG_CHKSUM; \ + (buf)->toport_chksum = chksum; } while(0) +#endif /* LWIP_CHECKSUM_ON_COPY */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETCONN || LWIP_SOCKET */ + +#endif /* LWIP_HDR_NETBUF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h b/Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h new file mode 100644 index 0000000..d3d15df --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/netdb.h @@ -0,0 +1,150 @@ +/** + * @file + * NETDB API (sockets) + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_NETDB_H +#define LWIP_HDR_NETDB_H + +#include "lwip/opt.h" + +#if LWIP_DNS && LWIP_SOCKET + +#include "lwip/arch.h" +#include "lwip/inet.h" +#include "lwip/sockets.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* some rarely used options */ +#ifndef LWIP_DNS_API_DECLARE_H_ERRNO +#define LWIP_DNS_API_DECLARE_H_ERRNO 1 +#endif + +#ifndef LWIP_DNS_API_DEFINE_ERRORS +#define LWIP_DNS_API_DEFINE_ERRORS 1 +#endif + +#ifndef LWIP_DNS_API_DEFINE_FLAGS +#define LWIP_DNS_API_DEFINE_FLAGS 1 +#endif + +#ifndef LWIP_DNS_API_DECLARE_STRUCTS +#define LWIP_DNS_API_DECLARE_STRUCTS 1 +#endif + +#if LWIP_DNS_API_DEFINE_ERRORS +/** Errors used by the DNS API functions, h_errno can be one of them */ +#define EAI_NONAME 200 +#define EAI_SERVICE 201 +#define EAI_FAIL 202 +#define EAI_MEMORY 203 +#define EAI_FAMILY 204 + +#define HOST_NOT_FOUND 210 +#define NO_DATA 211 +#define NO_RECOVERY 212 +#define TRY_AGAIN 213 +#endif /* LWIP_DNS_API_DEFINE_ERRORS */ + +#if LWIP_DNS_API_DEFINE_FLAGS +/* input flags for struct addrinfo */ +#define AI_PASSIVE 0x01 +#define AI_CANONNAME 0x02 +#define AI_NUMERICHOST 0x04 +#define AI_NUMERICSERV 0x08 +#define AI_V4MAPPED 0x10 +#define AI_ALL 0x20 +#define AI_ADDRCONFIG 0x40 +#endif /* LWIP_DNS_API_DEFINE_FLAGS */ + +#if LWIP_DNS_API_DECLARE_STRUCTS +struct hostent { + char *h_name; /* Official name of the host. */ + char **h_aliases; /* A pointer to an array of pointers to alternative host names, + terminated by a null pointer. */ + int h_addrtype; /* Address type. */ + int h_length; /* The length, in bytes, of the address. */ + char **h_addr_list; /* A pointer to an array of pointers to network addresses (in + network byte order) for the host, terminated by a null pointer. */ +#define h_addr h_addr_list[0] /* for backward compatibility */ +}; + +struct addrinfo { + int ai_flags; /* Input flags. */ + int ai_family; /* Address family of socket. */ + int ai_socktype; /* Socket type. */ + int ai_protocol; /* Protocol of socket. */ + socklen_t ai_addrlen; /* Length of socket address. */ + struct sockaddr *ai_addr; /* Socket address of socket. */ + char *ai_canonname; /* Canonical name of service location. */ + struct addrinfo *ai_next; /* Pointer to next in list. */ +}; +#endif /* LWIP_DNS_API_DECLARE_STRUCTS */ + +#define NETDB_ELEM_SIZE (sizeof(struct addrinfo) + sizeof(struct sockaddr_storage) + DNS_MAX_NAME_LENGTH + 1) + +#if LWIP_DNS_API_DECLARE_H_ERRNO +/* application accessible error code set by the DNS API functions */ +extern int h_errno; +#endif /* LWIP_DNS_API_DECLARE_H_ERRNO*/ + +struct hostent *lwip_gethostbyname(const char *name); +int lwip_gethostbyname_r(const char *name, struct hostent *ret, char *buf, + size_t buflen, struct hostent **result, int *h_errnop); +void lwip_freeaddrinfo(struct addrinfo *ai); +int lwip_getaddrinfo(const char *nodename, + const char *servname, + const struct addrinfo *hints, + struct addrinfo **res); + +#if LWIP_COMPAT_SOCKETS +/** @ingroup netdbapi */ +#define gethostbyname(name) lwip_gethostbyname(name) +/** @ingroup netdbapi */ +#define gethostbyname_r(name, ret, buf, buflen, result, h_errnop) \ + lwip_gethostbyname_r(name, ret, buf, buflen, result, h_errnop) +/** @ingroup netdbapi */ +#define freeaddrinfo(addrinfo) lwip_freeaddrinfo(addrinfo) +/** @ingroup netdbapi */ +#define getaddrinfo(nodname, servname, hints, res) \ + lwip_getaddrinfo(nodname, servname, hints, res) +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_DNS && LWIP_SOCKET */ + +#endif /* LWIP_HDR_NETDB_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/netif.h b/Middlewares/Third_Party/LwIP/src/include/lwip/netif.h new file mode 100644 index 0000000..911196a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/netif.h @@ -0,0 +1,669 @@ +/** + * @file + * netif API (to be used from TCPIP thread) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_NETIF_H +#define LWIP_HDR_NETIF_H + +#include "lwip/opt.h" + +#define ENABLE_LOOPBACK (LWIP_NETIF_LOOPBACK || LWIP_HAVE_LOOPIF) + +#include "lwip/err.h" + +#include "lwip/ip_addr.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Throughout this file, IP addresses are expected to be in + * the same byte order as in IP_PCB. */ + +/** Must be the maximum of all used hardware address lengths + across all types of interfaces in use. + This does not have to be changed, normally. */ +#ifndef NETIF_MAX_HWADDR_LEN +#define NETIF_MAX_HWADDR_LEN 6U +#endif + +/** The size of a fully constructed netif name which the + * netif can be identified by in APIs. Composed of + * 2 chars, 3 (max) digits, and 1 \0 + */ +#define NETIF_NAMESIZE 6 + +/** + * @defgroup netif_flags Flags + * @ingroup netif + * @{ + */ + +/** Whether the network interface is 'up'. This is + * a software flag used to control whether this network + * interface is enabled and processes traffic. + * It must be set by the startup code before this netif can be used + * (also for dhcp/autoip). + */ +#define NETIF_FLAG_UP 0x01U +/** If set, the netif has broadcast capability. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_BROADCAST 0x02U +/** If set, the interface has an active link + * (set by the network interface driver). + * Either set by the netif driver in its init function (if the link + * is up at that time) or at a later point once the link comes up + * (if link detection is supported by the hardware). */ +#define NETIF_FLAG_LINK_UP 0x04U +/** If set, the netif is an ethernet device using ARP. + * Set by the netif driver in its init function. + * Used to check input packet types and use of DHCP. */ +#define NETIF_FLAG_ETHARP 0x08U +/** If set, the netif is an ethernet device. It might not use + * ARP or TCP/IP if it is used for PPPoE only. + */ +#define NETIF_FLAG_ETHERNET 0x10U +/** If set, the netif has IGMP capability. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_IGMP 0x20U +/** If set, the netif has MLD6 capability. + * Set by the netif driver in its init function. */ +#define NETIF_FLAG_MLD6 0x40U + +/** + * @} + */ + +enum lwip_internal_netif_client_data_index +{ +#if LWIP_IPV4 +#if LWIP_DHCP + LWIP_NETIF_CLIENT_DATA_INDEX_DHCP, +#endif +#if LWIP_AUTOIP + LWIP_NETIF_CLIENT_DATA_INDEX_AUTOIP, +#endif +#if LWIP_IGMP + LWIP_NETIF_CLIENT_DATA_INDEX_IGMP, +#endif +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 +#if LWIP_IPV6_DHCP6 + LWIP_NETIF_CLIENT_DATA_INDEX_DHCP6, +#endif +#if LWIP_IPV6_MLD + LWIP_NETIF_CLIENT_DATA_INDEX_MLD6, +#endif +#endif /* LWIP_IPV6 */ + LWIP_NETIF_CLIENT_DATA_INDEX_MAX +}; + +#if LWIP_CHECKSUM_CTRL_PER_NETIF +#define NETIF_CHECKSUM_GEN_IP 0x0001 +#define NETIF_CHECKSUM_GEN_UDP 0x0002 +#define NETIF_CHECKSUM_GEN_TCP 0x0004 +#define NETIF_CHECKSUM_GEN_ICMP 0x0008 +#define NETIF_CHECKSUM_GEN_ICMP6 0x0010 +#define NETIF_CHECKSUM_CHECK_IP 0x0100 +#define NETIF_CHECKSUM_CHECK_UDP 0x0200 +#define NETIF_CHECKSUM_CHECK_TCP 0x0400 +#define NETIF_CHECKSUM_CHECK_ICMP 0x0800 +#define NETIF_CHECKSUM_CHECK_ICMP6 0x1000 +#define NETIF_CHECKSUM_ENABLE_ALL 0xFFFF +#define NETIF_CHECKSUM_DISABLE_ALL 0x0000 +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ + +struct netif; + +/** MAC Filter Actions, these are passed to a netif's igmp_mac_filter or + * mld_mac_filter callback function. */ +enum netif_mac_filter_action { + /** Delete a filter entry */ + NETIF_DEL_MAC_FILTER = 0, + /** Add a filter entry */ + NETIF_ADD_MAC_FILTER = 1 +}; + +/** Function prototype for netif init functions. Set up flags and output/linkoutput + * callback functions in this function. + * + * @param netif The netif to initialize + */ +typedef err_t (*netif_init_fn)(struct netif *netif); +/** Function prototype for netif->input functions. This function is saved as 'input' + * callback function in the netif struct. Call it when a packet has been received. + * + * @param p The received packet, copied into a pbuf + * @param inp The netif which received the packet + * @return ERR_OK if the packet was handled + * != ERR_OK is the packet was NOT handled, in this case, the caller has + * to free the pbuf + */ +typedef err_t (*netif_input_fn)(struct pbuf *p, struct netif *inp); + +#if LWIP_IPV4 +/** Function prototype for netif->output functions. Called by lwIP when a packet + * shall be sent. For ethernet netif, set this to 'etharp_output' and set + * 'linkoutput'. + * + * @param netif The netif which shall send a packet + * @param p The packet to send (p->payload points to IP header) + * @param ipaddr The IP address to which the packet shall be sent + */ +typedef err_t (*netif_output_fn)(struct netif *netif, struct pbuf *p, + const ip4_addr_t *ipaddr); +#endif /* LWIP_IPV4*/ + +#if LWIP_IPV6 +/** Function prototype for netif->output_ip6 functions. Called by lwIP when a packet + * shall be sent. For ethernet netif, set this to 'ethip6_output' and set + * 'linkoutput'. + * + * @param netif The netif which shall send a packet + * @param p The packet to send (p->payload points to IP header) + * @param ipaddr The IPv6 address to which the packet shall be sent + */ +typedef err_t (*netif_output_ip6_fn)(struct netif *netif, struct pbuf *p, + const ip6_addr_t *ipaddr); +#endif /* LWIP_IPV6 */ + +/** Function prototype for netif->linkoutput functions. Only used for ethernet + * netifs. This function is called by ARP when a packet shall be sent. + * + * @param netif The netif which shall send a packet + * @param p The packet to send (raw ethernet packet) + */ +typedef err_t (*netif_linkoutput_fn)(struct netif *netif, struct pbuf *p); +/** Function prototype for netif status- or link-callback functions. */ +typedef void (*netif_status_callback_fn)(struct netif *netif); +#if LWIP_IPV4 && LWIP_IGMP +/** Function prototype for netif igmp_mac_filter functions */ +typedef err_t (*netif_igmp_mac_filter_fn)(struct netif *netif, + const ip4_addr_t *group, enum netif_mac_filter_action action); +#endif /* LWIP_IPV4 && LWIP_IGMP */ +#if LWIP_IPV6 && LWIP_IPV6_MLD +/** Function prototype for netif mld_mac_filter functions */ +typedef err_t (*netif_mld_mac_filter_fn)(struct netif *netif, + const ip6_addr_t *group, enum netif_mac_filter_action action); +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + +#if LWIP_DHCP || LWIP_AUTOIP || LWIP_IGMP || LWIP_IPV6_MLD || LWIP_IPV6_DHCP6 || (LWIP_NUM_NETIF_CLIENT_DATA > 0) +#if LWIP_NUM_NETIF_CLIENT_DATA > 0 +u8_t netif_alloc_client_data_id(void); +#endif +/** @ingroup netif_cd + * Set client data. Obtain ID from netif_alloc_client_data_id(). + */ +#define netif_set_client_data(netif, id, data) netif_get_client_data(netif, id) = (data) +/** @ingroup netif_cd + * Get client data. Obtain ID from netif_alloc_client_data_id(). + */ +#define netif_get_client_data(netif, id) (netif)->client_data[(id)] +#endif + +#if (LWIP_IPV4 && LWIP_ARP && (ARP_TABLE_SIZE > 0x7f)) || (LWIP_IPV6 && (LWIP_ND6_NUM_DESTINATIONS > 0x7f)) +typedef u16_t netif_addr_idx_t; +#define NETIF_ADDR_IDX_MAX 0x7FFF +#else +typedef u8_t netif_addr_idx_t; +#define NETIF_ADDR_IDX_MAX 0x7F +#endif + +#if LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_USE_HINTS 1 +struct netif_hint { + netif_addr_idx_t addr_hint; +}; +#else /* LWIP_NETIF_HWADDRHINT */ +#define LWIP_NETIF_USE_HINTS 0 +#endif /* LWIP_NETIF_HWADDRHINT */ + +/** Generic data structure used for all lwIP network interfaces. + * The following fields should be filled in by the initialization + * function for the device driver: hwaddr_len, hwaddr[], mtu, flags */ +struct netif { +#if !LWIP_SINGLE_NETIF + /** pointer to next in linked list */ + struct netif *next; +#endif + +#if LWIP_IPV4 + /** IP address configuration in network byte order */ + ip_addr_t ip_addr; + ip_addr_t netmask; + ip_addr_t gw; +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 + /** Array of IPv6 addresses for this netif. */ + ip_addr_t ip6_addr[LWIP_IPV6_NUM_ADDRESSES]; + /** The state of each IPv6 address (Tentative, Preferred, etc). + * @see ip6_addr.h */ + u8_t ip6_addr_state[LWIP_IPV6_NUM_ADDRESSES]; +#if LWIP_IPV6_ADDRESS_LIFETIMES + /** Remaining valid and preferred lifetime of each IPv6 address, in seconds. + * For valid lifetimes, the special value of IP6_ADDR_LIFE_STATIC (0) + * indicates the address is static and has no lifetimes. */ + u32_t ip6_addr_valid_life[LWIP_IPV6_NUM_ADDRESSES]; + u32_t ip6_addr_pref_life[LWIP_IPV6_NUM_ADDRESSES]; +#endif /* LWIP_IPV6_ADDRESS_LIFETIMES */ +#endif /* LWIP_IPV6 */ + /** This function is called by the network device driver + * to pass a packet up the TCP/IP stack. */ + netif_input_fn input; +#if LWIP_IPV4 + /** This function is called by the IP module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. + * For ethernet physical layer, this is usually etharp_output() */ + netif_output_fn output; +#endif /* LWIP_IPV4 */ + /** This function is called by ethernet_output() when it wants + * to send a packet on the interface. This function outputs + * the pbuf as-is on the link medium. */ + netif_linkoutput_fn linkoutput; +#if LWIP_IPV6 + /** This function is called by the IPv6 module when it wants + * to send a packet on the interface. This function typically + * first resolves the hardware address, then sends the packet. + * For ethernet physical layer, this is usually ethip6_output() */ + netif_output_ip6_fn output_ip6; +#endif /* LWIP_IPV6 */ +#if LWIP_NETIF_STATUS_CALLBACK + /** This function is called when the netif state is set to up or down + */ + netif_status_callback_fn status_callback; +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_LINK_CALLBACK + /** This function is called when the netif link is set to up or down + */ + netif_status_callback_fn link_callback; +#endif /* LWIP_NETIF_LINK_CALLBACK */ +#if LWIP_NETIF_REMOVE_CALLBACK + /** This function is called when the netif has been removed */ + netif_status_callback_fn remove_callback; +#endif /* LWIP_NETIF_REMOVE_CALLBACK */ + /** This field can be set by the device driver and could point + * to state information for the device. */ + void *state; +#ifdef netif_get_client_data + void* client_data[LWIP_NETIF_CLIENT_DATA_INDEX_MAX + LWIP_NUM_NETIF_CLIENT_DATA]; +#endif +#if LWIP_NETIF_HOSTNAME + /* the hostname for this netif, NULL is a valid value */ + const char* hostname; +#endif /* LWIP_NETIF_HOSTNAME */ +#if LWIP_CHECKSUM_CTRL_PER_NETIF + u16_t chksum_flags; +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF*/ + /** maximum transfer unit (in bytes) */ + u16_t mtu; +#if LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES + /** maximum transfer unit (in bytes), updated by RA */ + u16_t mtu6; +#endif /* LWIP_IPV6 && LWIP_ND6_ALLOW_RA_UPDATES */ + /** link level hardware address of this interface */ + u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; + /** number of bytes used in hwaddr */ + u8_t hwaddr_len; + /** flags (@see @ref netif_flags) */ + u8_t flags; + /** descriptive abbreviation */ + char name[2]; + /** number of this interface. Used for @ref if_api and @ref netifapi_netif, + * as well as for IPv6 zones */ + u8_t num; +#if LWIP_IPV6_AUTOCONFIG + /** is this netif enabled for IPv6 autoconfiguration */ + u8_t ip6_autoconfig_enabled; +#endif /* LWIP_IPV6_AUTOCONFIG */ +#if LWIP_IPV6_SEND_ROUTER_SOLICIT + /** Number of Router Solicitation messages that remain to be sent. */ + u8_t rs_count; +#endif /* LWIP_IPV6_SEND_ROUTER_SOLICIT */ +#if MIB2_STATS + /** link type (from "snmp_ifType" enum from snmp_mib2.h) */ + u8_t link_type; + /** (estimate) link speed */ + u32_t link_speed; + /** timestamp at last change made (up/down) */ + u32_t ts; + /** counters */ + struct stats_mib2_netif_ctrs mib2_counters; +#endif /* MIB2_STATS */ +#if LWIP_IPV4 && LWIP_IGMP + /** This function could be called to add or delete an entry in the multicast + filter table of the ethernet MAC.*/ + netif_igmp_mac_filter_fn igmp_mac_filter; +#endif /* LWIP_IPV4 && LWIP_IGMP */ +#if LWIP_IPV6 && LWIP_IPV6_MLD + /** This function could be called to add or delete an entry in the IPv6 multicast + filter table of the ethernet MAC. */ + netif_mld_mac_filter_fn mld_mac_filter; +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ +#if LWIP_NETIF_USE_HINTS + struct netif_hint *hints; +#endif /* LWIP_NETIF_USE_HINTS */ +#if ENABLE_LOOPBACK + /* List of packets to be queued for ourselves. */ + struct pbuf *loop_first; + struct pbuf *loop_last; +#if LWIP_LOOPBACK_MAX_PBUFS + u16_t loop_cnt_current; +#endif /* LWIP_LOOPBACK_MAX_PBUFS */ +#endif /* ENABLE_LOOPBACK */ +}; + +#if LWIP_CHECKSUM_CTRL_PER_NETIF +#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) do { \ + (netif)->chksum_flags = chksumflags; } while(0) +#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) if (((netif) == NULL) || (((netif)->chksum_flags & (chksumflag)) != 0)) +#else /* LWIP_CHECKSUM_CTRL_PER_NETIF */ +#define NETIF_SET_CHECKSUM_CTRL(netif, chksumflags) +#define IF__NETIF_CHECKSUM_ENABLED(netif, chksumflag) +#endif /* LWIP_CHECKSUM_CTRL_PER_NETIF */ + +#if LWIP_SINGLE_NETIF +#define NETIF_FOREACH(netif) if (((netif) = netif_default) != NULL) +#else /* LWIP_SINGLE_NETIF */ +/** The list of network interfaces. */ +extern struct netif *netif_list; +#define NETIF_FOREACH(netif) for ((netif) = netif_list; (netif) != NULL; (netif) = (netif)->next) +#endif /* LWIP_SINGLE_NETIF */ +/** The default network interface. */ +extern struct netif *netif_default; + +void netif_init(void); + +struct netif *netif_add_noaddr(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input); + +#if LWIP_IPV4 +struct netif *netif_add(struct netif *netif, + const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, + void *state, netif_init_fn init, netif_input_fn input); +void netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, + const ip4_addr_t *gw); +#else /* LWIP_IPV4 */ +struct netif *netif_add(struct netif *netif, void *state, netif_init_fn init, netif_input_fn input); +#endif /* LWIP_IPV4 */ +void netif_remove(struct netif * netif); + +/* Returns a network interface given its name. The name is of the form + "et0", where the first two letters are the "name" field in the + netif structure, and the digit is in the num field in the same + structure. */ +struct netif *netif_find(const char *name); + +void netif_set_default(struct netif *netif); + +#if LWIP_IPV4 +void netif_set_ipaddr(struct netif *netif, const ip4_addr_t *ipaddr); +void netif_set_netmask(struct netif *netif, const ip4_addr_t *netmask); +void netif_set_gw(struct netif *netif, const ip4_addr_t *gw); +/** @ingroup netif_ip4 */ +#define netif_ip4_addr(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->ip_addr))) +/** @ingroup netif_ip4 */ +#define netif_ip4_netmask(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->netmask))) +/** @ingroup netif_ip4 */ +#define netif_ip4_gw(netif) ((const ip4_addr_t*)ip_2_ip4(&((netif)->gw))) +/** @ingroup netif_ip4 */ +#define netif_ip_addr4(netif) ((const ip_addr_t*)&((netif)->ip_addr)) +/** @ingroup netif_ip4 */ +#define netif_ip_netmask4(netif) ((const ip_addr_t*)&((netif)->netmask)) +/** @ingroup netif_ip4 */ +#define netif_ip_gw4(netif) ((const ip_addr_t*)&((netif)->gw)) +#endif /* LWIP_IPV4 */ + +#define netif_set_flags(netif, set_flags) do { (netif)->flags = (u8_t)((netif)->flags | (set_flags)); } while(0) +#define netif_clear_flags(netif, clr_flags) do { (netif)->flags = (u8_t)((netif)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0) +#define netif_is_flag_set(nefif, flag) (((netif)->flags & (flag)) != 0) + +void netif_set_up(struct netif *netif); +void netif_set_down(struct netif *netif); +/** @ingroup netif + * Ask if an interface is up + */ +#define netif_is_up(netif) (((netif)->flags & NETIF_FLAG_UP) ? (u8_t)1 : (u8_t)0) + +#if LWIP_NETIF_STATUS_CALLBACK +void netif_set_status_callback(struct netif *netif, netif_status_callback_fn status_callback); +#endif /* LWIP_NETIF_STATUS_CALLBACK */ +#if LWIP_NETIF_REMOVE_CALLBACK +void netif_set_remove_callback(struct netif *netif, netif_status_callback_fn remove_callback); +#endif /* LWIP_NETIF_REMOVE_CALLBACK */ + +void netif_set_link_up(struct netif *netif); +void netif_set_link_down(struct netif *netif); +/** Ask if a link is up */ +#define netif_is_link_up(netif) (((netif)->flags & NETIF_FLAG_LINK_UP) ? (u8_t)1 : (u8_t)0) + +#if LWIP_NETIF_LINK_CALLBACK +void netif_set_link_callback(struct netif *netif, netif_status_callback_fn link_callback); +#endif /* LWIP_NETIF_LINK_CALLBACK */ + +#if LWIP_NETIF_HOSTNAME +/** @ingroup netif */ +#define netif_set_hostname(netif, name) do { if((netif) != NULL) { (netif)->hostname = name; }}while(0) +/** @ingroup netif */ +#define netif_get_hostname(netif) (((netif) != NULL) ? ((netif)->hostname) : NULL) +#endif /* LWIP_NETIF_HOSTNAME */ + +#if LWIP_IGMP +/** @ingroup netif */ +#define netif_set_igmp_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->igmp_mac_filter = function; }}while(0) +#define netif_get_igmp_mac_filter(netif) (((netif) != NULL) ? ((netif)->igmp_mac_filter) : NULL) +#endif /* LWIP_IGMP */ + +#if LWIP_IPV6 && LWIP_IPV6_MLD +/** @ingroup netif */ +#define netif_set_mld_mac_filter(netif, function) do { if((netif) != NULL) { (netif)->mld_mac_filter = function; }}while(0) +#define netif_get_mld_mac_filter(netif) (((netif) != NULL) ? ((netif)->mld_mac_filter) : NULL) +#define netif_mld_mac_filter(netif, addr, action) do { if((netif) && (netif)->mld_mac_filter) { (netif)->mld_mac_filter((netif), (addr), (action)); }}while(0) +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + +#if ENABLE_LOOPBACK +err_t netif_loop_output(struct netif *netif, struct pbuf *p); +void netif_poll(struct netif *netif); +#if !LWIP_NETIF_LOOPBACK_MULTITHREADING +void netif_poll_all(void); +#endif /* !LWIP_NETIF_LOOPBACK_MULTITHREADING */ +#endif /* ENABLE_LOOPBACK */ + +err_t netif_input(struct pbuf *p, struct netif *inp); + +#if LWIP_IPV6 +/** @ingroup netif_ip6 */ +#define netif_ip_addr6(netif, i) ((const ip_addr_t*)(&((netif)->ip6_addr[i]))) +/** @ingroup netif_ip6 */ +#define netif_ip6_addr(netif, i) ((const ip6_addr_t*)ip_2_ip6(&((netif)->ip6_addr[i]))) +void netif_ip6_addr_set(struct netif *netif, s8_t addr_idx, const ip6_addr_t *addr6); +void netif_ip6_addr_set_parts(struct netif *netif, s8_t addr_idx, u32_t i0, u32_t i1, u32_t i2, u32_t i3); +#define netif_ip6_addr_state(netif, i) ((netif)->ip6_addr_state[i]) +void netif_ip6_addr_set_state(struct netif* netif, s8_t addr_idx, u8_t state); +s8_t netif_get_ip6_addr_match(struct netif *netif, const ip6_addr_t *ip6addr); +void netif_create_ip6_linklocal_address(struct netif *netif, u8_t from_mac_48bit); +err_t netif_add_ip6_address(struct netif *netif, const ip6_addr_t *ip6addr, s8_t *chosen_idx); +#define netif_set_ip6_autoconfig_enabled(netif, action) do { if(netif) { (netif)->ip6_autoconfig_enabled = (action); }}while(0) +#if LWIP_IPV6_ADDRESS_LIFETIMES +#define netif_ip6_addr_valid_life(netif, i) \ + (((netif) != NULL) ? ((netif)->ip6_addr_valid_life[i]) : IP6_ADDR_LIFE_STATIC) +#define netif_ip6_addr_set_valid_life(netif, i, secs) \ + do { if (netif != NULL) { (netif)->ip6_addr_valid_life[i] = (secs); }} while (0) +#define netif_ip6_addr_pref_life(netif, i) \ + (((netif) != NULL) ? ((netif)->ip6_addr_pref_life[i]) : IP6_ADDR_LIFE_STATIC) +#define netif_ip6_addr_set_pref_life(netif, i, secs) \ + do { if (netif != NULL) { (netif)->ip6_addr_pref_life[i] = (secs); }} while (0) +#define netif_ip6_addr_isstatic(netif, i) \ + (netif_ip6_addr_valid_life((netif), (i)) == IP6_ADDR_LIFE_STATIC) +#else /* !LWIP_IPV6_ADDRESS_LIFETIMES */ +#define netif_ip6_addr_isstatic(netif, i) (1) /* all addresses are static */ +#endif /* !LWIP_IPV6_ADDRESS_LIFETIMES */ +#if LWIP_ND6_ALLOW_RA_UPDATES +#define netif_mtu6(netif) ((netif)->mtu6) +#else /* LWIP_ND6_ALLOW_RA_UPDATES */ +#define netif_mtu6(netif) ((netif)->mtu) +#endif /* LWIP_ND6_ALLOW_RA_UPDATES */ +#endif /* LWIP_IPV6 */ + +#if LWIP_NETIF_USE_HINTS +#define NETIF_SET_HINTS(netif, netifhint) (netif)->hints = (netifhint) +#define NETIF_RESET_HINTS(netif) (netif)->hints = NULL +#else /* LWIP_NETIF_USE_HINTS */ +#define NETIF_SET_HINTS(netif, netifhint) +#define NETIF_RESET_HINTS(netif) +#endif /* LWIP_NETIF_USE_HINTS */ + +u8_t netif_name_to_index(const char *name); +char * netif_index_to_name(u8_t idx, char *name); +struct netif* netif_get_by_index(u8_t idx); + +/* Interface indexes always start at 1 per RFC 3493, section 4, num starts at 0 (internal index is 0..254)*/ +#define netif_get_index(netif) ((u8_t)((netif)->num + 1)) +#define NETIF_NO_INDEX (0) + +/** + * @ingroup netif + * Extended netif status callback (NSC) reasons flags. + * May be extended in the future! + */ +typedef u16_t netif_nsc_reason_t; + +/* used for initialization only */ +#define LWIP_NSC_NONE 0x0000 +/** netif was added. arg: NULL. Called AFTER netif was added. */ +#define LWIP_NSC_NETIF_ADDED 0x0001 +/** netif was removed. arg: NULL. Called BEFORE netif is removed. */ +#define LWIP_NSC_NETIF_REMOVED 0x0002 +/** link changed */ +#define LWIP_NSC_LINK_CHANGED 0x0004 +/** netif administrative status changed.\n + * up is called AFTER netif is set up.\n + * down is called BEFORE the netif is actually set down. */ +#define LWIP_NSC_STATUS_CHANGED 0x0008 +/** IPv4 address has changed */ +#define LWIP_NSC_IPV4_ADDRESS_CHANGED 0x0010 +/** IPv4 gateway has changed */ +#define LWIP_NSC_IPV4_GATEWAY_CHANGED 0x0020 +/** IPv4 netmask has changed */ +#define LWIP_NSC_IPV4_NETMASK_CHANGED 0x0040 +/** called AFTER IPv4 address/gateway/netmask changes have been applied */ +#define LWIP_NSC_IPV4_SETTINGS_CHANGED 0x0080 +/** IPv6 address was added */ +#define LWIP_NSC_IPV6_SET 0x0100 +/** IPv6 address state has changed */ +#define LWIP_NSC_IPV6_ADDR_STATE_CHANGED 0x0200 + +/** @ingroup netif + * Argument supplied to netif_ext_callback_fn. + */ +typedef union +{ + /** Args to LWIP_NSC_LINK_CHANGED callback */ + struct link_changed_s + { + /** 1: up; 0: down */ + u8_t state; + } link_changed; + /** Args to LWIP_NSC_STATUS_CHANGED callback */ + struct status_changed_s + { + /** 1: up; 0: down */ + u8_t state; + } status_changed; + /** Args to LWIP_NSC_IPV4_ADDRESS_CHANGED|LWIP_NSC_IPV4_GATEWAY_CHANGED|LWIP_NSC_IPV4_NETMASK_CHANGED|LWIP_NSC_IPV4_SETTINGS_CHANGED callback */ + struct ipv4_changed_s + { + /** Old IPv4 address */ + const ip_addr_t* old_address; + const ip_addr_t* old_netmask; + const ip_addr_t* old_gw; + } ipv4_changed; + /** Args to LWIP_NSC_IPV6_SET callback */ + struct ipv6_set_s + { + /** Index of changed IPv6 address */ + s8_t addr_index; + /** Old IPv6 address */ + const ip_addr_t* old_address; + } ipv6_set; + /** Args to LWIP_NSC_IPV6_ADDR_STATE_CHANGED callback */ + struct ipv6_addr_state_changed_s + { + /** Index of affected IPv6 address */ + s8_t addr_index; + /** Old IPv6 address state */ + u8_t old_state; + /** Affected IPv6 address */ + const ip_addr_t* address; + } ipv6_addr_state_changed; +} netif_ext_callback_args_t; + +/** + * @ingroup netif + * Function used for extended netif status callbacks + * Note: When parsing reason argument, keep in mind that more reasons may be added in the future! + * @param netif netif that is affected by change + * @param reason change reason + * @param args depends on reason, see reason description + */ +typedef void (*netif_ext_callback_fn)(struct netif* netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t* args); + +#if LWIP_NETIF_EXT_STATUS_CALLBACK +struct netif_ext_callback; +typedef struct netif_ext_callback +{ + netif_ext_callback_fn callback_fn; + struct netif_ext_callback* next; +} netif_ext_callback_t; + +#define NETIF_DECLARE_EXT_CALLBACK(name) static netif_ext_callback_t name; +void netif_add_ext_callback(netif_ext_callback_t* callback, netif_ext_callback_fn fn); +void netif_remove_ext_callback(netif_ext_callback_t* callback); +void netif_invoke_ext_callback(struct netif* netif, netif_nsc_reason_t reason, const netif_ext_callback_args_t* args); +#else +#define NETIF_DECLARE_EXT_CALLBACK(name) +#define netif_add_ext_callback(callback, fn) +#define netif_remove_ext_callback(callback) +#define netif_invoke_ext_callback(netif, reason, args) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_NETIF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h b/Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h new file mode 100644 index 0000000..e063179 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/netifapi.h @@ -0,0 +1,161 @@ +/** + * @file + * netif API (to be used from non-TCPIP threads) + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ +#ifndef LWIP_HDR_NETIFAPI_H +#define LWIP_HDR_NETIFAPI_H + +#include "lwip/opt.h" + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/netif.h" +#include "lwip/dhcp.h" +#include "lwip/autoip.h" +#include "lwip/priv/tcpip_priv.h" +#include "lwip/priv/api_msg.h" +#include "lwip/prot/ethernet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* API for application */ +#if LWIP_ARP && LWIP_IPV4 +/* Used for netfiapi_arp_* APIs */ +enum netifapi_arp_entry { + NETIFAPI_ARP_PERM /* Permanent entry */ + /* Other entry types can be added here */ +}; + +/** @ingroup netifapi_arp */ +err_t netifapi_arp_add(const ip4_addr_t *ipaddr, struct eth_addr *ethaddr, enum netifapi_arp_entry type); +/** @ingroup netifapi_arp */ +err_t netifapi_arp_remove(const ip4_addr_t *ipaddr, enum netifapi_arp_entry type); +#endif /* LWIP_ARP && LWIP_IPV4 */ + +err_t netifapi_netif_add(struct netif *netif, +#if LWIP_IPV4 + const ip4_addr_t *ipaddr, const ip4_addr_t *netmask, const ip4_addr_t *gw, +#endif /* LWIP_IPV4 */ + void *state, netif_init_fn init, netif_input_fn input); + +#if LWIP_IPV4 +err_t netifapi_netif_set_addr(struct netif *netif, const ip4_addr_t *ipaddr, + const ip4_addr_t *netmask, const ip4_addr_t *gw); +#endif /* LWIP_IPV4*/ + +err_t netifapi_netif_common(struct netif *netif, netifapi_void_fn voidfunc, + netifapi_errt_fn errtfunc); + +/** @ingroup netifapi_netif */ +err_t netifapi_netif_name_to_index(const char *name, u8_t *index); +/** @ingroup netifapi_netif */ +err_t netifapi_netif_index_to_name(u8_t index, char *name); + +/** @ingroup netifapi_netif + * @see netif_remove() + */ +#define netifapi_netif_remove(n) netifapi_netif_common(n, netif_remove, NULL) +/** @ingroup netifapi_netif + * @see netif_set_up() + */ +#define netifapi_netif_set_up(n) netifapi_netif_common(n, netif_set_up, NULL) +/** @ingroup netifapi_netif + * @see netif_set_down() + */ +#define netifapi_netif_set_down(n) netifapi_netif_common(n, netif_set_down, NULL) +/** @ingroup netifapi_netif + * @see netif_set_default() + */ +#define netifapi_netif_set_default(n) netifapi_netif_common(n, netif_set_default, NULL) +/** @ingroup netifapi_netif + * @see netif_set_link_up() + */ +#define netifapi_netif_set_link_up(n) netifapi_netif_common(n, netif_set_link_up, NULL) +/** @ingroup netifapi_netif + * @see netif_set_link_down() + */ +#define netifapi_netif_set_link_down(n) netifapi_netif_common(n, netif_set_link_down, NULL) + +/** + * @defgroup netifapi_dhcp4 DHCPv4 + * @ingroup netifapi + * To be called from non-TCPIP threads + */ +/** @ingroup netifapi_dhcp4 + * @see dhcp_start() + */ +#define netifapi_dhcp_start(n) netifapi_netif_common(n, NULL, dhcp_start) +/** + * @ingroup netifapi_dhcp4 + * @deprecated Use netifapi_dhcp_release_and_stop() instead. + */ +#define netifapi_dhcp_stop(n) netifapi_netif_common(n, dhcp_stop, NULL) +/** @ingroup netifapi_dhcp4 + * @see dhcp_inform() + */ +#define netifapi_dhcp_inform(n) netifapi_netif_common(n, dhcp_inform, NULL) +/** @ingroup netifapi_dhcp4 + * @see dhcp_renew() + */ +#define netifapi_dhcp_renew(n) netifapi_netif_common(n, NULL, dhcp_renew) +/** + * @ingroup netifapi_dhcp4 + * @deprecated Use netifapi_dhcp_release_and_stop() instead. + */ +#define netifapi_dhcp_release(n) netifapi_netif_common(n, NULL, dhcp_release) +/** @ingroup netifapi_dhcp4 + * @see dhcp_release_and_stop() + */ +#define netifapi_dhcp_release_and_stop(n) netifapi_netif_common(n, dhcp_release_and_stop, NULL) + +/** + * @defgroup netifapi_autoip AUTOIP + * @ingroup netifapi + * To be called from non-TCPIP threads + */ +/** @ingroup netifapi_autoip + * @see autoip_start() + */ +#define netifapi_autoip_start(n) netifapi_netif_common(n, NULL, autoip_start) +/** @ingroup netifapi_autoip + * @see autoip_stop() + */ +#define netifapi_autoip_stop(n) netifapi_netif_common(n, NULL, autoip_stop) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_NETIF_API */ + +#endif /* LWIP_HDR_NETIFAPI_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/opt.h b/Middlewares/Third_Party/LwIP/src/include/lwip/opt.h new file mode 100644 index 0000000..82c420c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/opt.h @@ -0,0 +1,3519 @@ +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* + * NOTE: || defined __DOXYGEN__ is a workaround for doxygen bug - + * without this, doxygen does not see the actual #define + */ + +#if !defined LWIP_HDR_OPT_H +#define LWIP_HDR_OPT_H + +/* + * Include user defined options first. Anything not defined in these files + * will be set to standard values. Override anything you don't like! + */ +#include "lwipopts.h" +#include "lwip/debug.h" + +/** + * @defgroup lwip_opts Options (lwipopts.h) + * @ingroup lwip + * + * @defgroup lwip_opts_debug Debugging + * @ingroup lwip_opts + * + * @defgroup lwip_opts_infrastructure Infrastructure + * @ingroup lwip_opts + * + * @defgroup lwip_opts_callback Callback-style APIs + * @ingroup lwip_opts + * + * @defgroup lwip_opts_threadsafe_apis Thread-safe APIs + * @ingroup lwip_opts + */ + + /* + ------------------------------------ + -------------- NO SYS -------------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_nosys NO_SYS + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * NO_SYS==1: Use lwIP without OS-awareness (no thread, semaphores, mutexes or + * mboxes). This means threaded APIs cannot be used (socket, netconn, + * i.e. everything in the 'api' folder), only the callback-style raw API is + * available (and you have to watch out for yourself that you don't access + * lwIP functions/structures from more than one context at a time!) + */ +#if !defined NO_SYS || defined __DOXYGEN__ +#define NO_SYS 0 +#endif +/** + * @} + */ + +/** + * @defgroup lwip_opts_timers Timers + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_TIMERS==0: Drop support for sys_timeout and lwip-internal cyclic timers. + * (the array of lwip-internal cyclic timers is still provided) + * (check NO_SYS_NO_TIMERS for compatibility to old versions) + */ +#if !defined LWIP_TIMERS || defined __DOXYGEN__ +#ifdef NO_SYS_NO_TIMERS +#define LWIP_TIMERS (!NO_SYS || (NO_SYS && !NO_SYS_NO_TIMERS)) +#else +#define LWIP_TIMERS 1 +#endif +#endif + +/** + * LWIP_TIMERS_CUSTOM==1: Provide your own timer implementation. + * Function prototypes in timeouts.h and the array of lwip-internal cyclic timers + * are still included, but the implementation is not. The following functions + * will be required: sys_timeouts_init(), sys_timeout(), sys_untimeout(), + * sys_timeouts_mbox_fetch() + */ +#if !defined LWIP_TIMERS_CUSTOM || defined __DOXYGEN__ +#define LWIP_TIMERS_CUSTOM 0 +#endif +/** + * @} + */ + +/** + * @defgroup lwip_opts_memcpy memcpy + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#if !defined MEMCPY || defined __DOXYGEN__ +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#if !defined SMEMCPY || defined __DOXYGEN__ +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * MEMMOVE: override this if you have a faster implementation at hand than the + * one included in your C library. lwIP currently uses MEMMOVE only when IPv6 + * fragmentation support is enabled. + */ +#if !defined MEMMOVE || defined __DOXYGEN__ +#define MEMMOVE(dst,src,len) memmove(dst,src,len) +#endif +/** + * @} + */ + +/* + ------------------------------------ + ----------- Core locking ----------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_lock Core locking and MPU + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_MPU_COMPATIBLE: enables special memory management mechanism + * which makes lwip able to work on MPU (Memory Protection Unit) system + * by not passing stack-pointers to other threads + * (this decreases performance as memory is allocated from pools instead + * of keeping it on the stack) + */ +#if !defined LWIP_MPU_COMPATIBLE || defined __DOXYGEN__ +#define LWIP_MPU_COMPATIBLE 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING + * Creates a global mutex that is held during TCPIP thread operations. + * Can be locked by client code to perform lwIP operations without changing + * into TCPIP thread using callbacks. See LOCK_TCPIP_CORE() and + * UNLOCK_TCPIP_CORE(). + * Your system should provide mutexes supporting priority inversion to use this. + */ +#if !defined LWIP_TCPIP_CORE_LOCKING || defined __DOXYGEN__ +#define LWIP_TCPIP_CORE_LOCKING 1 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: when LWIP_TCPIP_CORE_LOCKING is enabled, + * this lets tcpip_input() grab the mutex for input packets as well, + * instead of allocating a message and passing it to tcpip_thread. + * + * ATTENTION: this does not work when tcpip_input() is called from + * interrupt context! + */ +#if !defined LWIP_TCPIP_CORE_LOCKING_INPUT || defined __DOXYGEN__ +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * SYS_LIGHTWEIGHT_PROT==1: enable inter-task protection (and task-vs-interrupt + * protection) for certain critical regions during buffer allocation, deallocation + * and memory allocation and deallocation. + * ATTENTION: This is required when using lwIP from more than one context! If + * you disable this, you must be sure what you are doing! + */ +#if !defined SYS_LIGHTWEIGHT_PROT || defined __DOXYGEN__ +#define SYS_LIGHTWEIGHT_PROT 1 +#endif + +/** + * Macro/function to check whether lwIP's threading/locking + * requirements are satisfied during current function call. + * This macro usually calls a function that is implemented in the OS-dependent + * sys layer and performs the following checks: + * - Not in ISR (this should be checked for NO_SYS==1, too!) + * - If @ref LWIP_TCPIP_CORE_LOCKING = 1: TCPIP core lock is held + * - If @ref LWIP_TCPIP_CORE_LOCKING = 0: function is called from TCPIP thread + * @see @ref multithreading + */ +#if !defined LWIP_ASSERT_CORE_LOCKED || defined __DOXYGEN__ +#define LWIP_ASSERT_CORE_LOCKED() +#endif + +/** + * Called as first thing in the lwIP TCPIP thread. Can be used in conjunction + * with @ref LWIP_ASSERT_CORE_LOCKED to check core locking. + * @see @ref multithreading + */ +#if !defined LWIP_MARK_TCPIP_THREAD || defined __DOXYGEN__ +#define LWIP_MARK_TCPIP_THREAD() +#endif +/** + * @} + */ + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_mem Heap and memory pools + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#if !defined MEM_LIBC_MALLOC || defined __DOXYGEN__ +#define MEM_LIBC_MALLOC 0 +#endif + +/** + * MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. + * Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution + * speed (heap alloc can be much slower than pool alloc) and usage from interrupts + * (especially if your netif driver allocates PBUF_POOL pbufs for received frames + * from interrupt)! + * ATTENTION: Currently, this uses the heap for ALL pools (also for private pools, + * not only for internal pools defined in memp_std.h)! + */ +#if !defined MEMP_MEM_MALLOC || defined __DOXYGEN__ +#define MEMP_MEM_MALLOC 0 +#endif + +/** + * MEMP_MEM_INIT==1: Force use of memset to initialize pool memory. + * Useful if pool are moved in uninitialized section of memory. This will ensure + * default values in pcbs struct are well initialized in all conditions. + */ +#if !defined MEMP_MEM_INIT || defined __DOXYGEN__ +#define MEMP_MEM_INIT 0 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> \#define MEM_ALIGNMENT 4 + * 2 byte alignment -> \#define MEM_ALIGNMENT 2 + */ +#if !defined MEM_ALIGNMENT || defined __DOXYGEN__ +#define MEM_ALIGNMENT 1 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#if !defined MEM_SIZE || defined __DOXYGEN__ +#define MEM_SIZE 1600 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#if !defined MEMP_OVERFLOW_CHECK || defined __DOXYGEN__ +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#if !defined MEMP_SANITY_CHECK || defined __DOXYGEN__ +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_OVERFLOW_CHECK: mem overflow protection reserves a configurable + * amount of bytes before and after each heap allocation chunk and fills + * it with a prominent default value. + * MEM_OVERFLOW_CHECK == 0 no checking + * MEM_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEM_OVERFLOW_CHECK >= 2 checks all heap elements every time + * mem_malloc() or mem_free() is called (useful but slow!) + */ +#if !defined MEM_OVERFLOW_CHECK || defined __DOXYGEN__ +#define MEM_OVERFLOW_CHECK 0 +#endif + +/** + * MEM_SANITY_CHECK==1: run a sanity check after each mem_free() to make + * sure that the linked list of heap elements is not corrupted. + */ +#if !defined MEM_SANITY_CHECK || defined __DOXYGEN__ +#define MEM_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#if !defined MEM_USE_POOLS || defined __DOXYGEN__ +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#if !defined MEM_USE_POOLS_TRY_BIGGER_POOL || defined __DOXYGEN__ +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * include path somewhere. + */ +#if !defined MEMP_USE_CUSTOM_POOLS || defined __DOXYGEN__ +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#if !defined LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT || defined __DOXYGEN__ +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif +/** + * @} + */ + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * @defgroup lwip_opts_memp Internal memory pools + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#if !defined MEMP_NUM_PBUF || defined __DOXYGEN__ +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#if !defined MEMP_NUM_RAW_PCB || defined __DOXYGEN__ +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#if !defined MEMP_NUM_UDP_PCB || defined __DOXYGEN__ +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections. + * (requires the LWIP_TCP option) + */ +#if !defined MEMP_NUM_TCP_PCB || defined __DOXYGEN__ +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#if !defined MEMP_NUM_TCP_PCB_LISTEN || defined __DOXYGEN__ +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#if !defined MEMP_NUM_TCP_SEG || defined __DOXYGEN__ +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_ALTCP_PCB: the number of simultaneously active altcp layer pcbs. + * (requires the LWIP_ALTCP option) + * Connections with multiple layers require more than one altcp_pcb (e.g. TLS + * over TCP requires 2 altcp_pcbs, one for TLS and one for TCP). + */ +#if !defined MEMP_NUM_ALTCP_PCB || defined __DOXYGEN__ +#define MEMP_NUM_ALTCP_PCB MEMP_NUM_TCP_PCB +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#if !defined MEMP_NUM_REASSDATA || defined __DOXYGEN__ +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 + * with DMA-enabled MACs where the packet is not yet sent when netif->output + * returns. + */ +#if !defined MEMP_NUM_FRAG_PBUF || defined __DOXYGEN__ +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simultaneously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#if !defined MEMP_NUM_ARP_QUEUE || defined __DOXYGEN__ +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members at the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#if !defined MEMP_NUM_IGMP_GROUP || defined __DOXYGEN__ +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * The number of sys timeouts used by the core stack (not apps) + * The default number of timeouts is calculated here for all enabled modules. + */ +#define LWIP_NUM_SYS_TIMEOUT_INTERNAL (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_NUM_TIMEOUTS + (LWIP_IPV6 * (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD))) + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simultaneously active timeouts. + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#if !defined MEMP_NUM_SYS_TIMEOUT || defined __DOXYGEN__ +#define MEMP_NUM_SYS_TIMEOUT LWIP_NUM_SYS_TIMEOUT_INTERNAL +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#if !defined MEMP_NUM_NETBUF || defined __DOXYGEN__ +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#if !defined MEMP_NUM_NETCONN || defined __DOXYGEN__ +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_SELECT_CB: the number of struct lwip_select_cb. + * (Only needed if you have LWIP_MPU_COMPATIBLE==1 and use the socket API. + * In that case, you need one per thread calling lwip_select.) + */ +#if !defined MEMP_NUM_SELECT_CB || defined __DOXYGEN__ +#define MEMP_NUM_SELECT_CB 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#if !defined MEMP_NUM_TCPIP_MSG_API || defined __DOXYGEN__ +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#if !defined MEMP_NUM_TCPIP_MSG_INPKT || defined __DOXYGEN__ +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#if !defined MEMP_NUM_NETDB || defined __DOXYGEN__ +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#if !defined MEMP_NUM_LOCALHOSTLIST || defined __DOXYGEN__ +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#if !defined PBUF_POOL_SIZE || defined __DOXYGEN__ +#define PBUF_POOL_SIZE 16 +#endif + +/** MEMP_NUM_API_MSG: the number of concurrently active calls to various + * socket, netconn, and tcpip functions + */ +#if !defined MEMP_NUM_API_MSG || defined __DOXYGEN__ +#define MEMP_NUM_API_MSG MEMP_NUM_TCPIP_MSG_API +#endif + +/** MEMP_NUM_DNS_API_MSG: the number of concurrently active calls to netconn_gethostbyname + */ +#if !defined MEMP_NUM_DNS_API_MSG || defined __DOXYGEN__ +#define MEMP_NUM_DNS_API_MSG MEMP_NUM_TCPIP_MSG_API +#endif + +/** MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA: the number of concurrently active calls + * to getsockopt/setsockopt + */ +#if !defined MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA || defined __DOXYGEN__ +#define MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA MEMP_NUM_TCPIP_MSG_API +#endif + +/** MEMP_NUM_NETIFAPI_MSG: the number of concurrently active calls to the + * netifapi functions + */ +#if !defined MEMP_NUM_NETIFAPI_MSG || defined __DOXYGEN__ +#define MEMP_NUM_NETIFAPI_MSG MEMP_NUM_TCPIP_MSG_API +#endif +/** + * @} + */ + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_arp ARP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#if !defined LWIP_ARP || defined __DOXYGEN__ +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#if !defined ARP_TABLE_SIZE || defined __DOXYGEN__ +#define ARP_TABLE_SIZE 10 +#endif + +/** the time an ARP entry stays valid after its last update, + * for ARP_TMR_INTERVAL = 1000, this is + * (60 * 5) seconds = 5 minutes. + */ +#if !defined ARP_MAXAGE || defined __DOXYGEN__ +#define ARP_MAXAGE 300 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#if !defined ARP_QUEUEING || defined __DOXYGEN__ +#define ARP_QUEUEING 0 +#endif + +/** The maximum number of packets which may be queued for each + * unresolved address by other network layers. Defaults to 3, 0 means disabled. + * Old packets are dropped, new packets are queued. + */ +#if !defined ARP_QUEUE_LEN || defined __DOXYGEN__ +#define ARP_QUEUE_LEN 3 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving and sending ethernet packets with + * VLAN header. See the description of LWIP_HOOK_VLAN_CHECK and + * LWIP_HOOK_VLAN_SET hooks to check/set VLAN headers. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#if !defined ETHARP_SUPPORT_VLAN || defined __DOXYGEN__ +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support even though ARP might be disabled + */ +#if !defined LWIP_ETHERNET || defined __DOXYGEN__ +#define LWIP_ETHERNET LWIP_ARP +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#if !defined ETH_PAD_SIZE || defined __DOXYGEN__ +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#if !defined ETHARP_SUPPORT_STATIC_ENTRIES || defined __DOXYGEN__ +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + +/** ETHARP_TABLE_MATCH_NETIF==1: Match netif for ARP table entries. + * If disabled, duplicate IP address on multiple netifs are not supported + * (but this should only occur for AutoIP). + */ +#if !defined ETHARP_TABLE_MATCH_NETIF || defined __DOXYGEN__ +#define ETHARP_TABLE_MATCH_NETIF !LWIP_SINGLE_NETIF +#endif +/** + * @} + */ + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * @defgroup lwip_opts_ipv4 IPv4 + * @ingroup lwip_opts + * @{ + */ +/** + * LWIP_IPV4==1: Enable IPv4 + */ +#if !defined LWIP_IPV4 || defined __DOXYGEN__ +#define LWIP_IPV4 1 +#endif + +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#if !defined IP_FORWARD || defined __DOXYGEN__ +#define IP_FORWARD 0 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#if !defined IP_REASSEMBLY || defined __DOXYGEN__ +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#if !defined IP_FRAG || defined __DOXYGEN__ +#define IP_FRAG 1 +#endif + +#if !LWIP_IPV4 +/* disable IPv4 extensions when IPv4 is disabled */ +#undef IP_FORWARD +#define IP_FORWARD 0 +#undef IP_REASSEMBLY +#define IP_REASSEMBLY 0 +#undef IP_FRAG +#define IP_FRAG 0 +#endif /* !LWIP_IPV4 */ + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#if !defined IP_OPTIONS_ALLOWED || defined __DOXYGEN__ +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#if !defined IP_REASS_MAXAGE || defined __DOXYGEN__ +#define IP_REASS_MAXAGE 15 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + * When IPv4 *and* IPv6 are enabled, this even changes to + * (PBUF_POOL_SIZE > 2 * IP_REASS_MAX_PBUFS)! + */ +#if !defined IP_REASS_MAX_PBUFS || defined __DOXYGEN__ +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#if !defined IP_DEFAULT_TTL || defined __DOXYGEN__ +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#if !defined IP_SOF_BROADCAST || defined __DOXYGEN__ +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#if !defined IP_SOF_BROADCAST_RECV || defined __DOXYGEN__ +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#if !defined IP_FORWARD_ALLOW_TX_ON_RX_NETIF || defined __DOXYGEN__ +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif +/** + * @} + */ + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_icmp ICMP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#if !defined LWIP_ICMP || defined __DOXYGEN__ +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#if !defined ICMP_TTL || defined __DOXYGEN__ +#define ICMP_TTL IP_DEFAULT_TTL +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#if !defined LWIP_BROADCAST_PING || defined __DOXYGEN__ +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#if !defined LWIP_MULTICAST_PING || defined __DOXYGEN__ +#define LWIP_MULTICAST_PING 0 +#endif +/** + * @} + */ + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_raw RAW + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#if !defined LWIP_RAW || defined __DOXYGEN__ +#define LWIP_RAW 0 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#if !defined RAW_TTL || defined __DOXYGEN__ +#define RAW_TTL IP_DEFAULT_TTL +#endif +/** + * @} + */ + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_dhcp DHCP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#if !defined LWIP_DHCP || defined __DOXYGEN__ +#define LWIP_DHCP 0 +#endif +#if !LWIP_IPV4 +/* disable DHCP when IPv4 is disabled */ +#undef LWIP_DHCP +#define LWIP_DHCP 0 +#endif /* !LWIP_IPV4 */ + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#if !defined DHCP_DOES_ARP_CHECK || defined __DOXYGEN__ +#define DHCP_DOES_ARP_CHECK (LWIP_DHCP && LWIP_ARP) +#endif + +/** + * LWIP_DHCP_BOOTP_FILE==1: Store offered_si_addr and boot_file_name. + */ +#if !defined LWIP_DHCP_BOOTP_FILE || defined __DOXYGEN__ +#define LWIP_DHCP_BOOTP_FILE 0 +#endif + +/** + * LWIP_DHCP_GETS_NTP==1: Request NTP servers with discover/select. For each + * response packet, an callback is called, which has to be provided by the port: + * void dhcp_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs); +*/ +#if !defined LWIP_DHCP_GET_NTP_SRV || defined __DOXYGEN__ +#define LWIP_DHCP_GET_NTP_SRV 0 +#endif + +/** + * The maximum of NTP servers requested + */ +#if !defined LWIP_DHCP_MAX_NTP_SERVERS || defined __DOXYGEN__ +#define LWIP_DHCP_MAX_NTP_SERVERS 1 +#endif + +/** + * LWIP_DHCP_MAX_DNS_SERVERS > 0: Request DNS servers with discover/select. + * DNS servers received in the response are passed to DNS via @ref dns_setserver() + * (up to the maximum limit defined here). + */ +#if !defined LWIP_DHCP_MAX_DNS_SERVERS || defined __DOXYGEN__ +#define LWIP_DHCP_MAX_DNS_SERVERS DNS_MAX_SERVERS +#endif +/** + * @} + */ + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_autoip AUTOIP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#if !defined LWIP_AUTOIP || defined __DOXYGEN__ +#define LWIP_AUTOIP 0 +#endif +#if !LWIP_IPV4 +/* disable AUTOIP when IPv4 is disabled */ +#undef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif /* !LWIP_IPV4 */ + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#if !defined LWIP_DHCP_AUTOIP_COOP || defined __DOXYGEN__ +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP (the DHCP client keeps + * running in this case). This can be set as low as 1 to get an AutoIP address + * very quickly, but you should be prepared to handle a changing IP address + * when DHCP overrides AutoIP. + */ +#if !defined LWIP_DHCP_AUTOIP_COOP_TRIES || defined __DOXYGEN__ +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif +/** + * @} + */ + +/* + ---------------------------------- + ----- SNMP MIB2 support ----- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_mib2 SNMP MIB2 callbacks + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_MIB2_CALLBACKS==1: Turn on SNMP MIB2 callbacks. + * Turn this on to get callbacks needed to implement MIB2. + * Usually MIB2_STATS should be enabled, too. + */ +#if !defined LWIP_MIB2_CALLBACKS || defined __DOXYGEN__ +#define LWIP_MIB2_CALLBACKS 0 +#endif +/** + * @} + */ + +/* + ---------------------------------- + -------- Multicast options ------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_multicast Multicast + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_MULTICAST_TX_OPTIONS==1: Enable multicast TX support like the socket options + * IP_MULTICAST_TTL/IP_MULTICAST_IF/IP_MULTICAST_LOOP, as well as (currently only) + * core support for the corresponding IPv6 options. + */ +#if !defined LWIP_MULTICAST_TX_OPTIONS || defined __DOXYGEN__ +#define LWIP_MULTICAST_TX_OPTIONS ((LWIP_IGMP || LWIP_IPV6_MLD) && (LWIP_UDP || LWIP_RAW)) +#endif +/** + * @} + */ + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_igmp IGMP + * @ingroup lwip_opts_ipv4 + * @{ + */ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#if !defined LWIP_IGMP || defined __DOXYGEN__ +#define LWIP_IGMP 0 +#endif +#if !LWIP_IPV4 +#undef LWIP_IGMP +#define LWIP_IGMP 0 +#endif +/** + * @} + */ + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_dns DNS + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#if !defined LWIP_DNS || defined __DOXYGEN__ +#define LWIP_DNS 0 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#if !defined DNS_TABLE_SIZE || defined __DOXYGEN__ +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#if !defined DNS_MAX_NAME_LENGTH || defined __DOXYGEN__ +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers + * The first server can be initialized automatically by defining + * DNS_SERVER_ADDRESS(ipaddr), where 'ipaddr' is an 'ip_addr_t*' + */ +#if !defined DNS_MAX_SERVERS || defined __DOXYGEN__ +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS maximum number of retries when asking for a name, before "timeout". */ +#if !defined DNS_MAX_RETRIES || defined __DOXYGEN__ +#define DNS_MAX_RETRIES 4 +#endif + +/** DNS do a name checking between the query and the response. */ +#if !defined DNS_DOES_NAME_CHECK || defined __DOXYGEN__ +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** LWIP_DNS_SECURE: controls the security level of the DNS implementation + * Use all DNS security features by default. + * This is overridable but should only be needed by very small targets + * or when using against non standard DNS servers. */ +#if !defined LWIP_DNS_SECURE || defined __DOXYGEN__ +#define LWIP_DNS_SECURE (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) +#endif + +/* A list of DNS security features follows */ +#define LWIP_DNS_SECURE_RAND_XID 1 +#define LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING 2 +#define LWIP_DNS_SECURE_RAND_SRC_PORT 4 + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, you have to define an initializer: + * \#define DNS_LOCAL_HOSTLIST_INIT {DNS_LOCAL_HOSTLIST_ELEM("host_ip4", IPADDR4_INIT_BYTES(1,2,3,4)), \ + * DNS_LOCAL_HOSTLIST_ELEM("host_ip6", IPADDR6_INIT_HOST(123, 234, 345, 456)} + * + * Instead, you can also use an external function: + * \#define DNS_LOOKUP_LOCAL_EXTERN(x) extern err_t my_lookup_function(const char *name, ip_addr_t *addr, u8_t dns_addrtype) + * that looks up the IP address and returns ERR_OK if found (LWIP_DNS_ADDRTYPE_xxx is passed in dns_addrtype). + */ +#if !defined DNS_LOCAL_HOSTLIST || defined __DOXYGEN__ +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#if !defined DNS_LOCAL_HOSTLIST_IS_DYNAMIC || defined __DOXYGEN__ +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/** Set this to 1 to enable querying ".local" names via mDNS + * using a One-Shot Multicast DNS Query */ +#if !defined LWIP_DNS_SUPPORT_MDNS_QUERIES || defined __DOXYGEN__ +#define LWIP_DNS_SUPPORT_MDNS_QUERIES 0 +#endif +/** + * @} + */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_udp UDP + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#if !defined LWIP_UDP || defined __DOXYGEN__ +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#if !defined LWIP_UDPLITE || defined __DOXYGEN__ +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#if !defined UDP_TTL || defined __DOXYGEN__ +#define UDP_TTL IP_DEFAULT_TTL +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#if !defined LWIP_NETBUF_RECVINFO || defined __DOXYGEN__ +#define LWIP_NETBUF_RECVINFO 0 +#endif +/** + * @} + */ + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * @defgroup lwip_opts_tcp TCP + * @ingroup lwip_opts_callback + * @{ + */ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#if !defined LWIP_TCP || defined __DOXYGEN__ +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#if !defined TCP_TTL || defined __DOXYGEN__ +#define TCP_TTL IP_DEFAULT_TTL +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well. + * ATTENTION: when using TCP_RCV_SCALE, TCP_WND is the total size + * with scaling applied. Maximum window value in the TCP header + * will be TCP_WND >> TCP_RCV_SCALE + */ +#if !defined TCP_WND || defined __DOXYGEN__ +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#if !defined TCP_MAXRTX || defined __DOXYGEN__ +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#if !defined TCP_SYNMAXRTX || defined __DOXYGEN__ +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#if !defined TCP_QUEUE_OOSEQ || defined __DOXYGEN__ +#define TCP_QUEUE_OOSEQ LWIP_TCP +#endif + +/** + * LWIP_TCP_SACK_OUT==1: TCP will support sending selective acknowledgements (SACKs). + */ +#if !defined LWIP_TCP_SACK_OUT || defined __DOXYGEN__ +#define LWIP_TCP_SACK_OUT 0 +#endif + +/** + * LWIP_TCP_MAX_SACK_NUM: The maximum number of SACK values to include in TCP segments. + * Must be at least 1, but is only used if LWIP_TCP_SACK_OUT is enabled. + * NOTE: Even though we never send more than 3 or 4 SACK ranges in a single segment + * (depending on other options), setting this option to values greater than 4 is not pointless. + * This is basically the max number of SACK ranges we want to keep track of. + * As new data is delivered, some of the SACK ranges may be removed or merged. + * In that case some of those older SACK ranges may be used again. + * The amount of memory used to store SACK ranges is LWIP_TCP_MAX_SACK_NUM * 8 bytes for each TCP PCB. + */ +#if !defined LWIP_TCP_MAX_SACK_NUM || defined __DOXYGEN__ +#define LWIP_TCP_MAX_SACK_NUM 4 +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#if !defined TCP_MSS || defined __DOXYGEN__ +#define TCP_MSS 536 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#if !defined TCP_CALCULATE_EFF_SEND_MSS || defined __DOXYGEN__ +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#if !defined TCP_SND_BUF || defined __DOXYGEN__ +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#if !defined TCP_SND_QUEUELEN || defined __DOXYGEN__ +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#if !defined TCP_SNDLOWAT || defined __DOXYGEN__ +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#if !defined TCP_SNDQUEUELOWAT || defined __DOXYGEN__ +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The default maximum number of bytes queued on ooseq per + * pcb if TCP_OOSEQ_BYTES_LIMIT is not defined. Default is 0 (no limit). + * Only valid for TCP_QUEUE_OOSEQ==1. + */ +#if !defined TCP_OOSEQ_MAX_BYTES || defined __DOXYGEN__ +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_BYTES_LIMIT(pcb): Return the maximum number of bytes to be queued + * on ooseq per pcb, given the pcb. Only valid for TCP_QUEUE_OOSEQ==1 && + * TCP_OOSEQ_MAX_BYTES==1. + * Use this to override TCP_OOSEQ_MAX_BYTES to a dynamic value per pcb. + */ +#if !defined TCP_OOSEQ_BYTES_LIMIT +#if TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_BYTES_LIMIT(pcb) TCP_OOSEQ_MAX_BYTES +#elif defined __DOXYGEN__ +#define TCP_OOSEQ_BYTES_LIMIT(pcb) +#endif +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The default maximum number of pbufs queued on ooseq per + * pcb if TCP_OOSEQ_BYTES_LIMIT is not defined. Default is 0 (no limit). + * Only valid for TCP_QUEUE_OOSEQ==1. + */ +#if !defined TCP_OOSEQ_MAX_PBUFS || defined __DOXYGEN__ +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_OOSEQ_PBUFS_LIMIT(pcb): Return the maximum number of pbufs to be queued + * on ooseq per pcb, given the pcb. Only valid for TCP_QUEUE_OOSEQ==1 && + * TCP_OOSEQ_MAX_PBUFS==1. + * Use this to override TCP_OOSEQ_MAX_PBUFS to a dynamic value per pcb. + */ +#if !defined TCP_OOSEQ_PBUFS_LIMIT +#if TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_PBUFS_LIMIT(pcb) TCP_OOSEQ_MAX_PBUFS +#elif defined __DOXYGEN__ +#define TCP_OOSEQ_PBUFS_LIMIT(pcb) +#endif +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#if !defined TCP_LISTEN_BACKLOG || defined __DOXYGEN__ +#define TCP_LISTEN_BACKLOG 0 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#if !defined TCP_DEFAULT_LISTEN_BACKLOG || defined __DOXYGEN__ +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#if !defined TCP_OVERSIZE || defined __DOXYGEN__ +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + * The timestamp option is currently only used to help remote hosts, it is not + * really used locally. Therefore, it is only enabled when a TS option is + * received in the initial SYN packet from a remote host. + */ +#if !defined LWIP_TCP_TIMESTAMPS || defined __DOXYGEN__ +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#if !defined TCP_WND_UPDATE_THRESHOLD || defined __DOXYGEN__ +#define TCP_WND_UPDATE_THRESHOLD LWIP_MIN((TCP_WND / 4), (TCP_MSS * 4)) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) || defined __DOXYGEN__ +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#else +#ifndef LWIP_EVENT_API +#define LWIP_EVENT_API 0 +#endif +#ifndef LWIP_CALLBACK_API +#define LWIP_CALLBACK_API 0 +#endif +#endif + +/** + * LWIP_WND_SCALE and TCP_RCV_SCALE: + * Set LWIP_WND_SCALE to 1 to enable window scaling. + * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the + * range of [0..14]). + * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large + * send window while having a small receive window only. + */ +#if !defined LWIP_WND_SCALE || defined __DOXYGEN__ +#define LWIP_WND_SCALE 0 +#define TCP_RCV_SCALE 0 +#endif + +/** + * LWIP_TCP_PCB_NUM_EXT_ARGS: + * When this is > 0, every tcp pcb (including listen pcb) includes a number of + * additional argument entries in an array (see tcp_ext_arg_alloc_id) + */ +#if !defined LWIP_TCP_PCB_NUM_EXT_ARGS || defined __DOXYGEN__ +#define LWIP_TCP_PCB_NUM_EXT_ARGS 0 +#endif + +/** LWIP_ALTCP==1: enable the altcp API. + * altcp is an abstraction layer that prevents applications linking against the + * tcp.h functions but provides the same functionality. It is used to e.g. add + * SSL/TLS or proxy-connect support to an application written for the tcp callback + * API without that application knowing the protocol details. + * + * With LWIP_ALTCP==0, applications written against the altcp API can still be + * compiled but are directly linked against the tcp.h callback API and then + * cannot use layered protocols. + * + * See @ref altcp_api + */ +#if !defined LWIP_ALTCP || defined __DOXYGEN__ +#define LWIP_ALTCP 0 +#endif + +/** LWIP_ALTCP_TLS==1: enable TLS support for altcp API. + * This needs a port of the functions in altcp_tls.h to a TLS library. + * A port to ARM mbedtls is provided with lwIP, see apps/altcp_tls/ directory + * and LWIP_ALTCP_TLS_MBEDTLS option. + */ +#if !defined LWIP_ALTCP_TLS || defined __DOXYGEN__ +#define LWIP_ALTCP_TLS 0 +#endif + +/** + * @} + */ + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * @defgroup lwip_opts_pbuf PBUF + * @ingroup lwip_opts + * @{ + */ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#if !defined PBUF_LINK_HLEN || defined __DOXYGEN__ +#if defined LWIP_HOOK_VLAN_SET && !defined __DOXYGEN__ +#define PBUF_LINK_HLEN (18 + ETH_PAD_SIZE) +#else /* LWIP_HOOK_VLAN_SET */ +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif /* LWIP_HOOK_VLAN_SET */ +#endif + +/** + * PBUF_LINK_ENCAPSULATION_HLEN: the number of bytes that should be allocated + * for an additional encapsulation header before ethernet headers (e.g. 802.11) + */ +#if !defined PBUF_LINK_ENCAPSULATION_HLEN || defined __DOXYGEN__ +#define PBUF_LINK_ENCAPSULATION_HLEN 0 +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accommodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#if !defined PBUF_POOL_BUFSIZE || defined __DOXYGEN__ +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_ENCAPSULATION_HLEN+PBUF_LINK_HLEN) +#endif + +/** + * LWIP_PBUF_REF_T: Refcount type in pbuf. + * Default width of u8_t can be increased if 255 refs are not enough for you. + */ +#if !defined LWIP_PBUF_REF_T || defined __DOXYGEN__ +#define LWIP_PBUF_REF_T u8_t +#endif +/** + * @} + */ + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * @defgroup lwip_opts_netif NETIF + * @ingroup lwip_opts + * @{ + */ +/** + * LWIP_SINGLE_NETIF==1: use a single netif only. This is the common case for + * small real-life targets. Some code like routing etc. can be left out. + */ +#if !defined LWIP_SINGLE_NETIF || defined __DOXYGEN__ +#define LWIP_SINGLE_NETIF 0 +#endif + +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#if !defined LWIP_NETIF_HOSTNAME || defined __DOXYGEN__ +#define LWIP_NETIF_HOSTNAME 0 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#if !defined LWIP_NETIF_API || defined __DOXYGEN__ +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquisition) + */ +#if !defined LWIP_NETIF_STATUS_CALLBACK || defined __DOXYGEN__ +#define LWIP_NETIF_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_EXT_STATUS_CALLBACK==1: Support an extended callback function + * for several netif related event that supports multiple subscribers. + * @see netif_ext_status_callback + */ +#if !defined LWIP_NETIF_EXT_STATUS_CALLBACK || defined __DOXYGEN__ +#define LWIP_NETIF_EXT_STATUS_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#if !defined LWIP_NETIF_LINK_CALLBACK || defined __DOXYGEN__ +#define LWIP_NETIF_LINK_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#if !defined LWIP_NETIF_REMOVE_CALLBACK || defined __DOXYGEN__ +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#if !defined LWIP_NETIF_HWADDRHINT || defined __DOXYGEN__ +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP *tries* to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * ATTENTION: a driver should *NOT* rely on getting single pbufs but check TX + * pbufs for being in one piece. If not, @ref pbuf_clone can be used to get + * a single pbuf: + * if (p->next != NULL) { + * struct pbuf *q = pbuf_clone(PBUF_RAW, PBUF_RAM, p); + * if (q == NULL) { + * return ERR_MEM; + * } + * p = q; ATTENTION: do NOT free the old 'p' as the ref belongs to the caller! + * } + */ +#if !defined LWIP_NETIF_TX_SINGLE_PBUF || defined __DOXYGEN__ +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/** + * LWIP_NUM_NETIF_CLIENT_DATA: Number of clients that may store + * data in client_data member array of struct netif (max. 256). + */ +#if !defined LWIP_NUM_NETIF_CLIENT_DATA || defined __DOXYGEN__ +#define LWIP_NUM_NETIF_CLIENT_DATA 0 +#endif +/** + * @} + */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_loop Loopback interface + * @ingroup lwip_opts_netif + * @{ + */ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1). + * This is only needed when no real netifs are available. If at least one other + * netif is available, loopback traffic uses this netif. + */ +#if !defined LWIP_HAVE_LOOPIF || defined __DOXYGEN__ +#define LWIP_HAVE_LOOPIF (LWIP_NETIF_LOOPBACK && !LWIP_SINGLE_NETIF) +#endif + +/** + * LWIP_LOOPIF_MULTICAST==1: Support multicast/IGMP on loop interface (127.0.0.1). + */ +#if !defined LWIP_LOOPIF_MULTICAST || defined __DOXYGEN__ +#define LWIP_LOOPIF_MULTICAST 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#if !defined LWIP_NETIF_LOOPBACK || defined __DOXYGEN__ +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#if !defined LWIP_LOOPBACK_MAX_PBUFS || defined __DOXYGEN__ +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#if !defined LWIP_NETIF_LOOPBACK_MULTITHREADING || defined __DOXYGEN__ +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif +/** + * @} + */ + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_thread Threading + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#if !defined TCPIP_THREAD_NAME || defined __DOXYGEN__ +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#if !defined TCPIP_THREAD_STACKSIZE || defined __DOXYGEN__ +#define TCPIP_THREAD_STACKSIZE 0 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#if !defined TCPIP_THREAD_PRIO || defined __DOXYGEN__ +#define TCPIP_THREAD_PRIO 1 +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#if !defined TCPIP_MBOX_SIZE || defined __DOXYGEN__ +#define TCPIP_MBOX_SIZE 0 +#endif + +/** + * Define this to something that triggers a watchdog. This is called from + * tcpip_thread after processing a message. + */ +#if !defined LWIP_TCPIP_THREAD_ALIVE || defined __DOXYGEN__ +#define LWIP_TCPIP_THREAD_ALIVE() +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#if !defined SLIPIF_THREAD_NAME || defined __DOXYGEN__ +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#if !defined SLIPIF_THREAD_STACKSIZE || defined __DOXYGEN__ +#define SLIPIF_THREAD_STACKSIZE 0 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#if !defined SLIPIF_THREAD_PRIO || defined __DOXYGEN__ +#define SLIPIF_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#if !defined DEFAULT_THREAD_NAME || defined __DOXYGEN__ +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#if !defined DEFAULT_THREAD_STACKSIZE || defined __DOXYGEN__ +#define DEFAULT_THREAD_STACKSIZE 0 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#if !defined DEFAULT_THREAD_PRIO || defined __DOXYGEN__ +#define DEFAULT_THREAD_PRIO 1 +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#if !defined DEFAULT_RAW_RECVMBOX_SIZE || defined __DOXYGEN__ +#define DEFAULT_RAW_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#if !defined DEFAULT_UDP_RECVMBOX_SIZE || defined __DOXYGEN__ +#define DEFAULT_UDP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#if !defined DEFAULT_TCP_RECVMBOX_SIZE || defined __DOXYGEN__ +#define DEFAULT_TCP_RECVMBOX_SIZE 0 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#if !defined DEFAULT_ACCEPTMBOX_SIZE || defined __DOXYGEN__ +#define DEFAULT_ACCEPTMBOX_SIZE 0 +#endif +/** + * @} + */ + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * @defgroup lwip_opts_netconn Netconn + * @ingroup lwip_opts_threadsafe_apis + * @{ + */ +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#if !defined LWIP_NETCONN || defined __DOXYGEN__ +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout to create + * timers running in tcpip_thread from another thread. + */ +#if !defined LWIP_TCPIP_TIMEOUT || defined __DOXYGEN__ +#define LWIP_TCPIP_TIMEOUT 0 +#endif + +/** LWIP_NETCONN_SEM_PER_THREAD==1: Use one (thread-local) semaphore per + * thread calling socket/netconn functions instead of allocating one + * semaphore per netconn (and per select etc.) + * ATTENTION: a thread-local semaphore for API calls is needed: + * - LWIP_NETCONN_THREAD_SEM_GET() returning a sys_sem_t* + * - LWIP_NETCONN_THREAD_SEM_ALLOC() creating the semaphore + * - LWIP_NETCONN_THREAD_SEM_FREE() freeing the semaphore + * The latter 2 can be invoked up by calling netconn_thread_init()/netconn_thread_cleanup(). + * Ports may call these for threads created with sys_thread_new(). + */ +#if !defined LWIP_NETCONN_SEM_PER_THREAD || defined __DOXYGEN__ +#define LWIP_NETCONN_SEM_PER_THREAD 0 +#endif + +/** LWIP_NETCONN_FULLDUPLEX==1: Enable code that allows reading from one thread, + * writing from a 2nd thread and closing from a 3rd thread at the same time. + * ATTENTION: This is currently really alpha! Some requirements: + * - LWIP_NETCONN_SEM_PER_THREAD==1 is required to use one socket/netconn from + * multiple threads at once + * - sys_mbox_free() has to unblock receive tasks waiting on recvmbox/acceptmbox + * and prevent a task pending on this during/after deletion + */ +#if !defined LWIP_NETCONN_FULLDUPLEX || defined __DOXYGEN__ +#define LWIP_NETCONN_FULLDUPLEX 0 +#endif +/** + * @} + */ + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * @defgroup lwip_opts_socket Sockets + * @ingroup lwip_opts_threadsafe_apis + * @{ + */ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#if !defined LWIP_SOCKET || defined __DOXYGEN__ +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names through defines. + * LWIP_COMPAT_SOCKETS==2: Same as ==1 but correctly named functions are created. + * While this helps code completion, it might conflict with existing libraries. + * (only used if you use sockets.c) + */ +#if !defined LWIP_COMPAT_SOCKETS || defined __DOXYGEN__ +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#if !defined LWIP_POSIX_SOCKETS_IO_NAMES || defined __DOXYGEN__ +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_SOCKET_OFFSET==n: Increases the file descriptor number created by LwIP with n. + * This can be useful when there are multiple APIs which create file descriptors. + * When they all start with a different offset and you won't make them overlap you can + * re implement read/write/close/ioctl/fnctl to send the requested action to the right + * library (sharing select will need more work though). + */ +#if !defined LWIP_SOCKET_OFFSET || defined __DOXYGEN__ +#define LWIP_SOCKET_OFFSET 0 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#if !defined LWIP_TCP_KEEPALIVE || defined __DOXYGEN__ +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#if !defined LWIP_SO_SNDTIMEO || defined __DOXYGEN__ +#define LWIP_SO_SNDTIMEO 0 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#if !defined LWIP_SO_RCVTIMEO || defined __DOXYGEN__ +#define LWIP_SO_RCVTIMEO 0 +#endif + +/** + * LWIP_SO_SNDRCVTIMEO_NONSTANDARD==1: SO_RCVTIMEO/SO_SNDTIMEO take an int + * (milliseconds, much like winsock does) instead of a struct timeval (default). + */ +#if !defined LWIP_SO_SNDRCVTIMEO_NONSTANDARD || defined __DOXYGEN__ +#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0 +#endif + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#if !defined LWIP_SO_RCVBUF || defined __DOXYGEN__ +#define LWIP_SO_RCVBUF 0 +#endif + +/** + * LWIP_SO_LINGER==1: Enable SO_LINGER processing. + */ +#if !defined LWIP_SO_LINGER || defined __DOXYGEN__ +#define LWIP_SO_LINGER 0 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#if !defined RECV_BUFSIZE_DEFAULT || defined __DOXYGEN__ +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * By default, TCP socket/netconn close waits 20 seconds max to send the FIN + */ +#if !defined LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT || defined __DOXYGEN__ +#define LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT 20000 +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#if !defined SO_REUSE || defined __DOXYGEN__ +#define SO_REUSE 0 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#if !defined SO_REUSE_RXTOALL || defined __DOXYGEN__ +#define SO_REUSE_RXTOALL 0 +#endif + +/** + * LWIP_FIONREAD_LINUXMODE==0 (default): ioctl/FIONREAD returns the amount of + * pending data in the network buffer. This is the way windows does it. It's + * the default for lwIP since it is smaller. + * LWIP_FIONREAD_LINUXMODE==1: ioctl/FIONREAD returns the size of the next + * pending datagram in bytes. This is the way linux does it. This code is only + * here for compatibility. + */ +#if !defined LWIP_FIONREAD_LINUXMODE || defined __DOXYGEN__ +#define LWIP_FIONREAD_LINUXMODE 0 +#endif + +/** + * LWIP_SOCKET_SELECT==1 (default): enable select() for sockets (uses a netconn + * callback to keep track of events). + * This saves RAM (counters per socket) and code (netconn event callback), which + * should improve performance a bit). + */ +#if !defined LWIP_SOCKET_SELECT || defined __DOXYGEN__ +#define LWIP_SOCKET_SELECT 1 +#endif + +/** + * LWIP_SOCKET_POLL==1 (default): enable poll() for sockets (including + * struct pollfd, nfds_t, and constants) + */ +#if !defined LWIP_SOCKET_POLL || defined __DOXYGEN__ +#define LWIP_SOCKET_POLL 1 +#endif +/** + * @} + */ + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * @defgroup lwip_opts_stats Statistics + * @ingroup lwip_opts_debug + * @{ + */ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#if !defined LWIP_STATS || defined __DOXYGEN__ +#define LWIP_STATS 1 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#if !defined LWIP_STATS_DISPLAY || defined __DOXYGEN__ +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#if !defined LINK_STATS || defined __DOXYGEN__ +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#if !defined ETHARP_STATS || defined __DOXYGEN__ +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#if !defined IP_STATS || defined __DOXYGEN__ +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#if !defined IPFRAG_STATS || defined __DOXYGEN__ +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#if !defined ICMP_STATS || defined __DOXYGEN__ +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#if !defined IGMP_STATS || defined __DOXYGEN__ +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#if !defined UDP_STATS || defined __DOXYGEN__ +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#if !defined TCP_STATS || defined __DOXYGEN__ +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#if !defined MEM_STATS || defined __DOXYGEN__ +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#if !defined MEMP_STATS || defined __DOXYGEN__ +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#if !defined SYS_STATS || defined __DOXYGEN__ +#define SYS_STATS (NO_SYS == 0) +#endif + +/** + * IP6_STATS==1: Enable IPv6 stats. + */ +#if !defined IP6_STATS || defined __DOXYGEN__ +#define IP6_STATS (LWIP_IPV6) +#endif + +/** + * ICMP6_STATS==1: Enable ICMP for IPv6 stats. + */ +#if !defined ICMP6_STATS || defined __DOXYGEN__ +#define ICMP6_STATS (LWIP_IPV6 && LWIP_ICMP6) +#endif + +/** + * IP6_FRAG_STATS==1: Enable IPv6 fragmentation stats. + */ +#if !defined IP6_FRAG_STATS || defined __DOXYGEN__ +#define IP6_FRAG_STATS (LWIP_IPV6 && (LWIP_IPV6_FRAG || LWIP_IPV6_REASS)) +#endif + +/** + * MLD6_STATS==1: Enable MLD for IPv6 stats. + */ +#if !defined MLD6_STATS || defined __DOXYGEN__ +#define MLD6_STATS (LWIP_IPV6 && LWIP_IPV6_MLD) +#endif + +/** + * ND6_STATS==1: Enable Neighbor discovery for IPv6 stats. + */ +#if !defined ND6_STATS || defined __DOXYGEN__ +#define ND6_STATS (LWIP_IPV6) +#endif + +/** + * MIB2_STATS==1: Stats for SNMP MIB2. + */ +#if !defined MIB2_STATS || defined __DOXYGEN__ +#define MIB2_STATS 0 +#endif + +#else + +#define LINK_STATS 0 +#define ETHARP_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 +#define IP6_STATS 0 +#define ICMP6_STATS 0 +#define IP6_FRAG_STATS 0 +#define MLD6_STATS 0 +#define ND6_STATS 0 +#define MIB2_STATS 0 + +#endif /* LWIP_STATS */ +/** + * @} + */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * @defgroup lwip_opts_checksum Checksum + * @ingroup lwip_opts_infrastructure + * @{ + */ +/** + * LWIP_CHECKSUM_CTRL_PER_NETIF==1: Checksum generation/check can be enabled/disabled + * per netif. + * ATTENTION: if enabled, the CHECKSUM_GEN_* and CHECKSUM_CHECK_* defines must be enabled! + */ +#if !defined LWIP_CHECKSUM_CTRL_PER_NETIF || defined __DOXYGEN__ +#define LWIP_CHECKSUM_CTRL_PER_NETIF 0 +#endif + +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#if !defined CHECKSUM_GEN_IP || defined __DOXYGEN__ +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#if !defined CHECKSUM_GEN_UDP || defined __DOXYGEN__ +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#if !defined CHECKSUM_GEN_TCP || defined __DOXYGEN__ +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#if !defined CHECKSUM_GEN_ICMP || defined __DOXYGEN__ +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP6==1: Generate checksums in software for outgoing ICMP6 packets. + */ +#if !defined CHECKSUM_GEN_ICMP6 || defined __DOXYGEN__ +#define CHECKSUM_GEN_ICMP6 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#if !defined CHECKSUM_CHECK_IP || defined __DOXYGEN__ +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#if !defined CHECKSUM_CHECK_UDP || defined __DOXYGEN__ +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#if !defined CHECKSUM_CHECK_TCP || defined __DOXYGEN__ +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * CHECKSUM_CHECK_ICMP==1: Check checksums in software for incoming ICMP packets. + */ +#if !defined CHECKSUM_CHECK_ICMP || defined __DOXYGEN__ +#define CHECKSUM_CHECK_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_ICMP6==1: Check checksums in software for incoming ICMPv6 packets + */ +#if !defined CHECKSUM_CHECK_ICMP6 || defined __DOXYGEN__ +#define CHECKSUM_CHECK_ICMP6 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#if !defined LWIP_CHECKSUM_ON_COPY || defined __DOXYGEN__ +#define LWIP_CHECKSUM_ON_COPY 0 +#endif +/** + * @} + */ + +/* + --------------------------------------- + ---------- IPv6 options --------------- + --------------------------------------- +*/ +/** + * @defgroup lwip_opts_ipv6 IPv6 + * @ingroup lwip_opts + * @{ + */ +/** + * LWIP_IPV6==1: Enable IPv6 + */ +#if !defined LWIP_IPV6 || defined __DOXYGEN__ +#define LWIP_IPV6 0 +#endif + +/** + * IPV6_REASS_MAXAGE: Maximum time (in multiples of IP6_REASS_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#if !defined IPV6_REASS_MAXAGE || defined __DOXYGEN__ +#define IPV6_REASS_MAXAGE 60 +#endif + +/** + * LWIP_IPV6_SCOPES==1: Enable support for IPv6 address scopes, ensuring that + * e.g. link-local addresses are really treated as link-local. Disable this + * setting only for single-interface configurations. + * All addresses that have a scope according to the default policy (link-local + * unicast addresses, interface-local and link-local multicast addresses) should + * now have a zone set on them before being passed to the core API, although + * lwIP will currently attempt to select a zone on the caller's behalf when + * necessary. Applications that directly assign IPv6 addresses to interfaces + * (which is NOT recommended) must now ensure that link-local addresses carry + * the netif's zone. See the new ip6_zone.h header file for more information and + * relevant macros. For now it is still possible to turn off scopes support + * through the new LWIP_IPV6_SCOPES option. When upgrading an implementation that + * uses the core API directly, it is highly recommended to enable + * LWIP_IPV6_SCOPES_DEBUG at least for a while, to ensure e.g. proper address + * initialization. + */ +#if !defined LWIP_IPV6_SCOPES || defined __DOXYGEN__ +#define LWIP_IPV6_SCOPES (LWIP_IPV6 && !LWIP_SINGLE_NETIF) +#endif + +/** + * LWIP_IPV6_SCOPES_DEBUG==1: Perform run-time checks to verify that addresses + * are properly zoned (see ip6_zone.h on what that means) where it matters. + * Enabling this setting is highly recommended when upgrading from an existing + * installation that is not yet scope-aware; otherwise it may be too expensive. + */ +#if !defined LWIP_IPV6_SCOPES_DEBUG || defined __DOXYGEN__ +#define LWIP_IPV6_SCOPES_DEBUG 0 +#endif + +/** + * LWIP_IPV6_NUM_ADDRESSES: Number of IPv6 addresses per netif. + */ +#if !defined LWIP_IPV6_NUM_ADDRESSES || defined __DOXYGEN__ +#define LWIP_IPV6_NUM_ADDRESSES 3 +#endif + +/** + * LWIP_IPV6_FORWARD==1: Forward IPv6 packets across netifs + */ +#if !defined LWIP_IPV6_FORWARD || defined __DOXYGEN__ +#define LWIP_IPV6_FORWARD 0 +#endif + +/** + * LWIP_IPV6_FRAG==1: Fragment outgoing IPv6 packets that are too big. + */ +#if !defined LWIP_IPV6_FRAG || defined __DOXYGEN__ +#define LWIP_IPV6_FRAG 1 +#endif + +/** + * LWIP_IPV6_REASS==1: reassemble incoming IPv6 packets that fragmented + */ +#if !defined LWIP_IPV6_REASS || defined __DOXYGEN__ +#define LWIP_IPV6_REASS LWIP_IPV6 +#endif + +/** + * LWIP_IPV6_SEND_ROUTER_SOLICIT==1: Send router solicitation messages during + * network startup. + */ +#if !defined LWIP_IPV6_SEND_ROUTER_SOLICIT || defined __DOXYGEN__ +#define LWIP_IPV6_SEND_ROUTER_SOLICIT 1 +#endif + +/** + * LWIP_IPV6_AUTOCONFIG==1: Enable stateless address autoconfiguration as per RFC 4862. + */ +#if !defined LWIP_IPV6_AUTOCONFIG || defined __DOXYGEN__ +#define LWIP_IPV6_AUTOCONFIG LWIP_IPV6 +#endif + +/** + * LWIP_IPV6_ADDRESS_LIFETIMES==1: Keep valid and preferred lifetimes for each + * IPv6 address. Required for LWIP_IPV6_AUTOCONFIG. May still be enabled + * otherwise, in which case the application may assign address lifetimes with + * the appropriate macros. Addresses with no lifetime are assumed to be static. + * If this option is disabled, all addresses are assumed to be static. + */ +#if !defined LWIP_IPV6_ADDRESS_LIFETIMES || defined __DOXYGEN__ +#define LWIP_IPV6_ADDRESS_LIFETIMES LWIP_IPV6_AUTOCONFIG +#endif + +/** + * LWIP_IPV6_DUP_DETECT_ATTEMPTS=[0..7]: Number of duplicate address detection attempts. + */ +#if !defined LWIP_IPV6_DUP_DETECT_ATTEMPTS || defined __DOXYGEN__ +#define LWIP_IPV6_DUP_DETECT_ATTEMPTS 1 +#endif +/** + * @} + */ + +/** + * @defgroup lwip_opts_icmp6 ICMP6 + * @ingroup lwip_opts_ipv6 + * @{ + */ +/** + * LWIP_ICMP6==1: Enable ICMPv6 (mandatory per RFC) + */ +#if !defined LWIP_ICMP6 || defined __DOXYGEN__ +#define LWIP_ICMP6 LWIP_IPV6 +#endif + +/** + * LWIP_ICMP6_DATASIZE: bytes from original packet to send back in + * ICMPv6 error messages. + */ +#if !defined LWIP_ICMP6_DATASIZE || defined __DOXYGEN__ +#define LWIP_ICMP6_DATASIZE 8 +#endif + +/** + * LWIP_ICMP6_HL: default hop limit for ICMPv6 messages + */ +#if !defined LWIP_ICMP6_HL || defined __DOXYGEN__ +#define LWIP_ICMP6_HL 255 +#endif +/** + * @} + */ + +/** + * @defgroup lwip_opts_mld6 Multicast listener discovery + * @ingroup lwip_opts_ipv6 + * @{ + */ +/** + * LWIP_IPV6_MLD==1: Enable multicast listener discovery protocol. + * If LWIP_IPV6 is enabled but this setting is disabled, the MAC layer must + * indiscriminately pass all inbound IPv6 multicast traffic to lwIP. + */ +#if !defined LWIP_IPV6_MLD || defined __DOXYGEN__ +#define LWIP_IPV6_MLD LWIP_IPV6 +#endif + +/** + * MEMP_NUM_MLD6_GROUP: Max number of IPv6 multicast groups that can be joined. + * There must be enough groups so that each netif can join the solicited-node + * multicast group for each of its local addresses, plus one for MDNS if + * applicable, plus any number of groups to be joined on UDP sockets. + */ +#if !defined MEMP_NUM_MLD6_GROUP || defined __DOXYGEN__ +#define MEMP_NUM_MLD6_GROUP 4 +#endif +/** + * @} + */ + +/** + * @defgroup lwip_opts_nd6 Neighbor discovery + * @ingroup lwip_opts_ipv6 + * @{ + */ +/** + * LWIP_ND6_QUEUEING==1: queue outgoing IPv6 packets while MAC address + * is being resolved. + */ +#if !defined LWIP_ND6_QUEUEING || defined __DOXYGEN__ +#define LWIP_ND6_QUEUEING LWIP_IPV6 +#endif + +/** + * MEMP_NUM_ND6_QUEUE: Max number of IPv6 packets to queue during MAC resolution. + */ +#if !defined MEMP_NUM_ND6_QUEUE || defined __DOXYGEN__ +#define MEMP_NUM_ND6_QUEUE 20 +#endif + +/** + * LWIP_ND6_NUM_NEIGHBORS: Number of entries in IPv6 neighbor cache + */ +#if !defined LWIP_ND6_NUM_NEIGHBORS || defined __DOXYGEN__ +#define LWIP_ND6_NUM_NEIGHBORS 10 +#endif + +/** + * LWIP_ND6_NUM_DESTINATIONS: number of entries in IPv6 destination cache + */ +#if !defined LWIP_ND6_NUM_DESTINATIONS || defined __DOXYGEN__ +#define LWIP_ND6_NUM_DESTINATIONS 10 +#endif + +/** + * LWIP_ND6_NUM_PREFIXES: number of entries in IPv6 on-link prefixes cache + */ +#if !defined LWIP_ND6_NUM_PREFIXES || defined __DOXYGEN__ +#define LWIP_ND6_NUM_PREFIXES 5 +#endif + +/** + * LWIP_ND6_NUM_ROUTERS: number of entries in IPv6 default router cache + */ +#if !defined LWIP_ND6_NUM_ROUTERS || defined __DOXYGEN__ +#define LWIP_ND6_NUM_ROUTERS 3 +#endif + +/** + * LWIP_ND6_MAX_MULTICAST_SOLICIT: max number of multicast solicit messages to send + * (neighbor solicit and router solicit) + */ +#if !defined LWIP_ND6_MAX_MULTICAST_SOLICIT || defined __DOXYGEN__ +#define LWIP_ND6_MAX_MULTICAST_SOLICIT 3 +#endif + +/** + * LWIP_ND6_MAX_UNICAST_SOLICIT: max number of unicast neighbor solicitation messages + * to send during neighbor reachability detection. + */ +#if !defined LWIP_ND6_MAX_UNICAST_SOLICIT || defined __DOXYGEN__ +#define LWIP_ND6_MAX_UNICAST_SOLICIT 3 +#endif + +/** + * Unused: See ND RFC (time in milliseconds). + */ +#if !defined LWIP_ND6_MAX_ANYCAST_DELAY_TIME || defined __DOXYGEN__ +#define LWIP_ND6_MAX_ANYCAST_DELAY_TIME 1000 +#endif + +/** + * Unused: See ND RFC + */ +#if !defined LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT || defined __DOXYGEN__ +#define LWIP_ND6_MAX_NEIGHBOR_ADVERTISEMENT 3 +#endif + +/** + * LWIP_ND6_REACHABLE_TIME: default neighbor reachable time (in milliseconds). + * May be updated by router advertisement messages. + */ +#if !defined LWIP_ND6_REACHABLE_TIME || defined __DOXYGEN__ +#define LWIP_ND6_REACHABLE_TIME 30000 +#endif + +/** + * LWIP_ND6_RETRANS_TIMER: default retransmission timer for solicitation messages + */ +#if !defined LWIP_ND6_RETRANS_TIMER || defined __DOXYGEN__ +#define LWIP_ND6_RETRANS_TIMER 1000 +#endif + +/** + * LWIP_ND6_DELAY_FIRST_PROBE_TIME: Delay before first unicast neighbor solicitation + * message is sent, during neighbor reachability detection. + */ +#if !defined LWIP_ND6_DELAY_FIRST_PROBE_TIME || defined __DOXYGEN__ +#define LWIP_ND6_DELAY_FIRST_PROBE_TIME 5000 +#endif + +/** + * LWIP_ND6_ALLOW_RA_UPDATES==1: Allow Router Advertisement messages to update + * Reachable time and retransmission timers, and netif MTU. + */ +#if !defined LWIP_ND6_ALLOW_RA_UPDATES || defined __DOXYGEN__ +#define LWIP_ND6_ALLOW_RA_UPDATES 1 +#endif + +/** + * LWIP_ND6_TCP_REACHABILITY_HINTS==1: Allow TCP to provide Neighbor Discovery + * with reachability hints for connected destinations. This helps avoid sending + * unicast neighbor solicitation messages. + */ +#if !defined LWIP_ND6_TCP_REACHABILITY_HINTS || defined __DOXYGEN__ +#define LWIP_ND6_TCP_REACHABILITY_HINTS 1 +#endif + +/** + * LWIP_ND6_RDNSS_MAX_DNS_SERVERS > 0: Use IPv6 Router Advertisement Recursive + * DNS Server Option (as per RFC 6106) to copy a defined maximum number of DNS + * servers to the DNS module. + */ +#if !defined LWIP_ND6_RDNSS_MAX_DNS_SERVERS || defined __DOXYGEN__ +#define LWIP_ND6_RDNSS_MAX_DNS_SERVERS 0 +#endif +/** + * @} + */ + +/** + * @defgroup lwip_opts_dhcpv6 DHCPv6 + * @ingroup lwip_opts_ipv6 + * @{ + */ +/** + * LWIP_IPV6_DHCP6==1: enable DHCPv6 stateful/stateless address autoconfiguration. + */ +#if !defined LWIP_IPV6_DHCP6 || defined __DOXYGEN__ +#define LWIP_IPV6_DHCP6 0 +#endif + +/** + * LWIP_IPV6_DHCP6_STATEFUL==1: enable DHCPv6 stateful address autoconfiguration. + * (not supported, yet!) + */ +#if !defined LWIP_IPV6_DHCP6_STATEFUL || defined __DOXYGEN__ +#define LWIP_IPV6_DHCP6_STATEFUL 0 +#endif + +/** + * LWIP_IPV6_DHCP6_STATELESS==1: enable DHCPv6 stateless address autoconfiguration. + */ +#if !defined LWIP_IPV6_DHCP6_STATELESS || defined __DOXYGEN__ +#define LWIP_IPV6_DHCP6_STATELESS LWIP_IPV6_DHCP6 +#endif + +/** + * LWIP_DHCP6_GETS_NTP==1: Request NTP servers via DHCPv6. For each + * response packet, a callback is called, which has to be provided by the port: + * void dhcp6_set_ntp_servers(u8_t num_ntp_servers, ip_addr_t* ntp_server_addrs); +*/ +#if !defined LWIP_DHCP6_GET_NTP_SRV || defined __DOXYGEN__ +#define LWIP_DHCP6_GET_NTP_SRV 0 +#endif + +/** + * The maximum of NTP servers requested + */ +#if !defined LWIP_DHCP6_MAX_NTP_SERVERS || defined __DOXYGEN__ +#define LWIP_DHCP6_MAX_NTP_SERVERS 1 +#endif + +/** + * LWIP_DHCP6_MAX_DNS_SERVERS > 0: Request DNS servers via DHCPv6. + * DNS servers received in the response are passed to DNS via @ref dns_setserver() + * (up to the maximum limit defined here). + */ +#if !defined LWIP_DHCP6_MAX_DNS_SERVERS || defined __DOXYGEN__ +#define LWIP_DHCP6_MAX_DNS_SERVERS DNS_MAX_SERVERS +#endif +/** + * @} + */ + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/** + * @defgroup lwip_opts_hooks Hooks + * @ingroup lwip_opts_infrastructure + * Hooks are undefined by default, define them to a function if you need them. + * @{ + */ + +/** + * LWIP_HOOK_FILENAME: Custom filename to \#include in files that provide hooks. + * Declare your hook function prototypes in there, you may also \#include all headers + * providing data types that are need in this file. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_FILENAME "path/to/my/lwip_hooks.h" +#endif + +/** + * LWIP_HOOK_TCP_ISN: + * Hook for generation of the Initial Sequence Number (ISN) for a new TCP + * connection. The default lwIP ISN generation algorithm is very basic and may + * allow for TCP spoofing attacks. This hook provides the means to implement + * the standardized ISN generation algorithm from RFC 6528 (see contrib/adons/tcp_isn), + * or any other desired algorithm as a replacement. + * Called from tcp_connect() and tcp_listen_input() when an ISN is needed for + * a new TCP connection, if TCP support (@ref LWIP_TCP) is enabled.\n + * Signature:\code{.c} + * u32_t my_hook_tcp_isn(const ip_addr_t* local_ip, u16_t local_port, const ip_addr_t* remote_ip, u16_t remote_port); + * \endcode + * - it may be necessary to use "struct ip_addr" (ip4_addr, ip6_addr) instead of "ip_addr_t" in function declarations\n + * Arguments: + * - local_ip: pointer to the local IP address of the connection + * - local_port: local port number of the connection (host-byte order) + * - remote_ip: pointer to the remote IP address of the connection + * - remote_port: remote port number of the connection (host-byte order)\n + * Return value: + * - the 32-bit Initial Sequence Number to use for the new TCP connection. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_TCP_ISN(local_ip, local_port, remote_ip, remote_port) +#endif + +/** + * LWIP_HOOK_TCP_INPACKET_PCB: + * Hook for intercepting incoming packets before they are passed to a pcb. This + * allows updating some state or even dropping a packet. + * Signature:\code{.c} + * err_t my_hook_tcp_inpkt(struct tcp_pcb *pcb, struct tcp_hdr *hdr, u16_t optlen, u16_t opt1len, u8_t *opt2, struct pbuf *p); + * \endcode + * Arguments: + * - pcb: tcp_pcb selected for input of this packet (ATTENTION: this may be + * struct tcp_pcb_listen if pcb->state == LISTEN) + * - hdr: pointer to tcp header (ATTENTION: tcp options may not be in one piece!) + * - optlen: tcp option length + * - opt1len: tcp option length 1st part + * - opt2: if this is != NULL, tcp options are split among 2 pbufs. In that case, + * options start at right after the tcp header ('(u8_t*)(hdr + 1)') for + * the first 'opt1len' bytes and the rest starts at 'opt2'. opt2len can + * be simply calculated: 'opt2len = optlen - opt1len;' + * - p: input packet, p->payload points to application data (that's why tcp hdr + * and options are passed in seperately) + * Return value: + * - ERR_OK: continue input of this packet as normal + * - != ERR_OK: drop this packet for input (don't continue input processing) + * + * ATTENTION: don't call any tcp api functions that might change tcp state (pcb + * state or any pcb lists) from this callback! + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_TCP_INPACKET_PCB(pcb, hdr, optlen, opt1len, opt2, p) +#endif + +/** + * LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH: + * Hook for increasing the size of the options allocated with a tcp header. + * Together with LWIP_HOOK_TCP_OUT_ADD_TCPOPTS, this can be used to add custom + * options to outgoing tcp segments. + * Signature:\code{.c} + * u8_t my_hook_tcp_out_tcpopt_length(const struct tcp_pcb *pcb, u8_t internal_option_length); + * \endcode + * Arguments: + * - pcb: tcp_pcb that transmits (ATTENTION: this may be NULL or + * struct tcp_pcb_listen if pcb->state == LISTEN) + * - internal_option_length: tcp option length used by the stack internally + * Return value: + * - a number of bytes to allocate for tcp options (internal_option_length <= ret <= 40) + * + * ATTENTION: don't call any tcp api functions that might change tcp state (pcb + * state or any pcb lists) from this callback! + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH(pcb, internal_len) +#endif + +/** + * LWIP_HOOK_TCP_OUT_ADD_TCPOPTS: + * Hook for adding custom options to outgoing tcp segments. + * Space for these custom options has to be reserved via LWIP_HOOK_TCP_OUT_TCPOPT_LENGTH. + * Signature:\code{.c} + * u32_t *my_hook_tcp_out_add_tcpopts(struct pbuf *p, struct tcp_hdr *hdr, const struct tcp_pcb *pcb, u32_t *opts); + * \endcode + * Arguments: + * - p: output packet, p->payload pointing to tcp header, data follows + * - hdr: tcp header + * - pcb: tcp_pcb that transmits (ATTENTION: this may be NULL or + * struct tcp_pcb_listen if pcb->state == LISTEN) + * - opts: pointer where to add the custom options (there may already be options + * between the header and these) + * Return value: + * - pointer pointing directly after the inserted options + * + * ATTENTION: don't call any tcp api functions that might change tcp state (pcb + * state or any pcb lists) from this callback! + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_TCP_OUT_ADD_TCPOPTS(p, hdr, pcb, opts) +#endif + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * Called from ip_input() (IPv4) + * Signature:\code{.c} + * int my_hook(struct pbuf *pbuf, struct netif *input_netif); + * \endcode + * Arguments: + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_IP4_INPUT(pbuf, input_netif) +#endif + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * Called from ip_route() (IPv4) + * Signature:\code{.c} + * struct netif *my_hook(const ip4_addr_t *dest); + * \endcode + * Arguments: + * - dest: destination IPv4 address + * Returns values: + * - the destination netif + * - NULL if no destination netif is found. In that case, ip_route() continues as normal. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_IP4_ROUTE() +#endif + +/** + * LWIP_HOOK_IP4_ROUTE_SRC(src, dest): + * Source-based routing for IPv4 - called from ip_route() (IPv4) + * Signature:\code{.c} + * struct netif *my_hook(const ip4_addr_t *src, const ip4_addr_t *dest); + * \endcode + * Arguments: + * - src: local/source IPv4 address + * - dest: destination IPv4 address + * Returns values: + * - the destination netif + * - NULL if no destination netif is found. In that case, ip_route() continues as normal. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_IP4_ROUTE_SRC(src, dest) +#endif + +/** + * LWIP_HOOK_IP4_CANFORWARD(src, dest): + * Check if an IPv4 can be forwarded - called from: + * ip4_input() -> ip4_forward() -> ip4_canforward() (IPv4) + * - source address is available via ip4_current_src_addr() + * - calling an output function in this context (e.g. multicast router) is allowed + * Signature:\code{.c} + * int my_hook(struct pbuf *p, u32_t dest_addr_hostorder); + * \endcode + * Arguments: + * - p: packet to forward + * - dest: destination IPv4 address + * Returns values: + * - 1: forward + * - 0: don't forward + * - -1: no decision. In that case, ip4_canforward() continues as normal. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_IP4_CANFORWARD(src, dest) +#endif + +/** + * LWIP_HOOK_ETHARP_GET_GW(netif, dest): + * Called from etharp_output() (IPv4) + * Signature:\code{.c} + * const ip4_addr_t *my_hook(struct netif *netif, const ip4_addr_t *dest); + * \endcode + * Arguments: + * - netif: the netif used for sending + * - dest: the destination IPv4 address + * Return values: + * - the IPv4 address of the gateway to handle the specified destination IPv4 address + * - NULL, in which case the netif's default gateway is used + * + * The returned address MUST be directly reachable on the specified netif! + * This function is meant to implement advanced IPv4 routing together with + * LWIP_HOOK_IP4_ROUTE(). The actual routing/gateway table implementation is + * not part of lwIP but can e.g. be hidden in the netif's state argument. +*/ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_ETHARP_GET_GW(netif, dest) +#endif + +/** + * LWIP_HOOK_IP6_INPUT(pbuf, input_netif): + * Called from ip6_input() (IPv6) + * Signature:\code{.c} + * int my_hook(struct pbuf *pbuf, struct netif *input_netif); + * \endcode + * Arguments: + * - pbuf: received struct pbuf passed to ip6_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_IP6_INPUT(pbuf, input_netif) +#endif + +/** + * LWIP_HOOK_IP6_ROUTE(src, dest): + * Called from ip_route() (IPv6) + * Signature:\code{.c} + * struct netif *my_hook(const ip6_addr_t *dest, const ip6_addr_t *src); + * \endcode + * Arguments: + * - src: source IPv6 address + * - dest: destination IPv6 address + * Return values: + * - the destination netif + * - NULL if no destination netif is found. In that case, ip6_route() continues as normal. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_IP6_ROUTE(src, dest) +#endif + +/** + * LWIP_HOOK_ND6_GET_GW(netif, dest): + * Called from nd6_get_next_hop_entry() (IPv6) + * Signature:\code{.c} + * const ip6_addr_t *my_hook(struct netif *netif, const ip6_addr_t *dest); + * \endcode + * Arguments: + * - netif: the netif used for sending + * - dest: the destination IPv6 address + * Return values: + * - the IPv6 address of the next hop to handle the specified destination IPv6 address + * - NULL, in which case a NDP-discovered router is used instead + * + * The returned address MUST be directly reachable on the specified netif! + * This function is meant to implement advanced IPv6 routing together with + * LWIP_HOOK_IP6_ROUTE(). The actual routing/gateway table implementation is + * not part of lwIP but can e.g. be hidden in the netif's state argument. +*/ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_ND6_GET_GW(netif, dest) +#endif + +/** + * LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr): + * Called from ethernet_input() if VLAN support is enabled + * Signature:\code{.c} + * int my_hook(struct netif *netif, struct eth_hdr *eth_hdr, struct eth_vlan_hdr *vlan_hdr); + * \endcode + * Arguments: + * - netif: struct netif on which the packet has been received + * - eth_hdr: struct eth_hdr of the packet + * - vlan_hdr: struct eth_vlan_hdr of the packet + * Return values: + * - 0: Packet must be dropped. + * - != 0: Packet must be accepted. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_VLAN_CHECK(netif, eth_hdr, vlan_hdr) +#endif + +/** + * LWIP_HOOK_VLAN_SET: + * Hook can be used to set prio_vid field of vlan_hdr. If you need to store data + * on per-netif basis to implement this callback, see @ref netif_cd. + * Called from ethernet_output() if VLAN support (@ref ETHARP_SUPPORT_VLAN) is enabled.\n + * Signature:\code{.c} + * s32_t my_hook_vlan_set(struct netif* netif, struct pbuf* pbuf, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type);\n + * \endcode + * Arguments: + * - netif: struct netif that the packet will be sent through + * - p: struct pbuf packet to be sent + * - src: source eth address + * - dst: destination eth address + * - eth_type: ethernet type to packet to be sent\n + * + * + * Return values: + * - <0: Packet shall not contain VLAN header. + * - 0 <= return value <= 0xFFFF: Packet shall contain VLAN header. Return value is prio_vid in host byte order. + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type) +#endif + +/** + * LWIP_HOOK_MEMP_AVAILABLE(memp_t_type): + * Called from memp_free() when a memp pool was empty and an item is now available + * Signature:\code{.c} + * void my_hook(memp_t type); + * \endcode + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_MEMP_AVAILABLE(memp_t_type) +#endif + +/** + * LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif): + * Called from ethernet_input() when an unknown eth type is encountered. + * Signature:\code{.c} + * err_t my_hook(struct pbuf* pbuf, struct netif* netif); + * \endcode + * Arguments: + * - p: rx packet with unknown eth type + * - netif: netif on which the packet has been received + * Return values: + * - ERR_OK if packet is accepted (hook function now owns the pbuf) + * - any error code otherwise (pbuf is freed) + * + * Payload points to ethernet header! + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(pbuf, netif) +#endif + +/** + * LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr): + * Called from various dhcp functions when sending a DHCP message. + * This hook is called just before the DHCP message trailer is added, so the + * options are at the end of a DHCP message. + * Signature:\code{.c} + * void my_hook(struct netif *netif, struct dhcp *dhcp, u8_t state, struct dhcp_msg *msg, + * u8_t msg_type, u16_t *options_len_ptr); + * \endcode + * Arguments: + * - netif: struct netif that the packet will be sent through + * - dhcp: struct dhcp on that netif + * - state: current dhcp state (dhcp_state_enum_t as an u8_t) + * - msg: struct dhcp_msg that will be sent + * - msg_type: dhcp message type to be sent (u8_t) + * - options_len_ptr: pointer to the current length of options in the dhcp_msg "msg" + * (must be increased when options are added!) + * + * Options need to appended like this: + * LWIP_ASSERT("dhcp option overflow", *options_len_ptr + option_len + 2 <= DHCP_OPTIONS_LEN); + * msg->options[(*options_len_ptr)++] = <option_number>; + * msg->options[(*options_len_ptr)++] = <option_len>; + * msg->options[(*options_len_ptr)++] = <option_bytes>; + * [...] + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_DHCP_APPEND_OPTIONS(netif, dhcp, state, msg, msg_type, options_len_ptr) +#endif + +/** + * LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, option_value_offset): + * Called from dhcp_parse_reply when receiving a DHCP message. + * This hook is called for every option in the received message that is not handled internally. + * Signature:\code{.c} + * void my_hook(struct netif *netif, struct dhcp *dhcp, u8_t state, struct dhcp_msg *msg, + * u8_t msg_type, u8_t option, u8_t option_len, struct pbuf *pbuf, u16_t option_value_offset); + * \endcode + * Arguments: + * - netif: struct netif that the packet will be sent through + * - dhcp: struct dhcp on that netif + * - state: current dhcp state (dhcp_state_enum_t as an u8_t) + * - msg: struct dhcp_msg that was received + * - msg_type: dhcp message type received (u8_t, ATTENTION: only valid after + * the message type option has been parsed!) + * - option: option value (u8_t) + * - len: option data length (u8_t) + * - pbuf: pbuf where option data is contained + * - option_value_offset: offset in pbuf where option data begins + * + * A nice way to get the option contents is pbuf_get_contiguous(): + * u8_t buf[32]; + * u8_t *ptr = (u8_t*)pbuf_get_contiguous(p, buf, sizeof(buf), LWIP_MIN(option_len, sizeof(buf)), offset); + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_DHCP_PARSE_OPTION(netif, dhcp, state, msg, msg_type, option, len, pbuf, offset) +#endif + +/** + * LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len): + * Called from various dhcp6 functions when sending a DHCP6 message. + * This hook is called just before the DHCP6 message is sent, so the + * options are at the end of a DHCP6 message. + * Signature:\code{.c} + * void my_hook(struct netif *netif, struct dhcp6 *dhcp, u8_t state, struct dhcp6_msg *msg, + * u8_t msg_type, u16_t *options_len_ptr); + * \endcode + * Arguments: + * - netif: struct netif that the packet will be sent through + * - dhcp6: struct dhcp6 on that netif + * - state: current dhcp6 state (dhcp6_state_enum_t as an u8_t) + * - msg: struct dhcp6_msg that will be sent + * - msg_type: dhcp6 message type to be sent (u8_t) + * - options_len_ptr: pointer to the current length of options in the dhcp6_msg "msg" + * (must be increased when options are added!) + * + * Options need to appended like this: + * u8_t *options = (u8_t *)(msg + 1); + * LWIP_ASSERT("dhcp option overflow", sizeof(struct dhcp6_msg) + *options_len_ptr + newoptlen <= max_len); + * options[(*options_len_ptr)++] = <option_data>; + * [...] + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_DHCP6_APPEND_OPTIONS(netif, dhcp6, state, msg, msg_type, options_len_ptr, max_len) +#endif + +/** + * LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, err) + * Called from socket API to implement setsockopt() for options not provided by lwIP. + * Core lock is held when this hook is called. + * Signature:\code{.c} + * int my_hook(int s, struct lwip_sock *sock, int level, int optname, const void *optval, socklen_t optlen, int *err) + * \endcode + * Arguments: + * - s: socket file descriptor + * - sock: internal socket descriptor (see lwip/priv/sockets_priv.h) + * - level: protocol level at which the option resides + * - optname: option to set + * - optval: value to set + * - optlen: size of optval + * - err: output error + * Return values: + * - 0: Hook has not consumed the option, code continues as normal (to internal options) + * - != 0: Hook has consumed the option, 'err' is returned + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_SOCKETS_SETSOCKOPT(s, sock, level, optname, optval, optlen, err) +#endif + +/** + * LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, err) + * Called from socket API to implement getsockopt() for options not provided by lwIP. + * Core lock is held when this hook is called. + * Signature:\code{.c} + * int my_hook(int s, struct lwip_sock *sock, int level, int optname, void *optval, socklen_t *optlen, int *err) + * \endcode + * Arguments: + * - s: socket file descriptor + * - sock: internal socket descriptor (see lwip/priv/sockets_priv.h) + * - level: protocol level at which the option resides + * - optname: option to get + * - optval: value to get + * - optlen: size of optval + * - err: output error + * Return values: + * - 0: Hook has not consumed the option, code continues as normal (to internal options) + * - != 0: Hook has consumed the option, 'err' is returned + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_SOCKETS_GETSOCKOPT(s, sock, level, optname, optval, optlen, err) +#endif + +/** + * LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, addrtype, err) + * Called from netconn APIs (not usable with callback apps) allowing an + * external DNS resolver (which uses sequential API) to handle the query. + * Signature:\code{.c} + * int my_hook(const char *name, ip_addr_t *addr, u8_t addrtype, err_t *err) + * \endcode + * Arguments: + * - name: hostname to resolve + * - addr: output host address + * - addrtype: type of address to query + * - err: output error + * Return values: + * - 0: Hook has not consumed hostname query, query continues into DNS module + * - != 0: Hook has consumed the query + * + * err must also be checked to determine if the hook consumed the query, but + * the query failed + */ +#ifdef __DOXYGEN__ +#define LWIP_HOOK_NETCONN_EXTERNAL_RESOLVE(name, addr, addrtype, err) +#endif +/** + * @} + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * @defgroup lwip_opts_debugmsg Debug messages + * @ingroup lwip_opts_debug + * @{ + */ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + * @see debugging_levels + */ +#if !defined LWIP_DBG_MIN_LEVEL || defined __DOXYGEN__ +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + * @see debugging_levels + */ +#if !defined LWIP_DBG_TYPES_ON || defined __DOXYGEN__ +#define LWIP_DBG_TYPES_ON LWIP_DBG_ON +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#if !defined ETHARP_DEBUG || defined __DOXYGEN__ +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#if !defined NETIF_DEBUG || defined __DOXYGEN__ +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#if !defined PBUF_DEBUG || defined __DOXYGEN__ +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#if !defined API_LIB_DEBUG || defined __DOXYGEN__ +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#if !defined API_MSG_DEBUG || defined __DOXYGEN__ +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#if !defined SOCKETS_DEBUG || defined __DOXYGEN__ +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#if !defined ICMP_DEBUG || defined __DOXYGEN__ +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#if !defined IGMP_DEBUG || defined __DOXYGEN__ +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#if !defined INET_DEBUG || defined __DOXYGEN__ +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#if !defined IP_DEBUG || defined __DOXYGEN__ +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#if !defined IP_REASS_DEBUG || defined __DOXYGEN__ +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#if !defined RAW_DEBUG || defined __DOXYGEN__ +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#if !defined MEM_DEBUG || defined __DOXYGEN__ +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#if !defined MEMP_DEBUG || defined __DOXYGEN__ +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#if !defined SYS_DEBUG || defined __DOXYGEN__ +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#if !defined TIMERS_DEBUG || defined __DOXYGEN__ +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#if !defined TCP_DEBUG || defined __DOXYGEN__ +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#if !defined TCP_INPUT_DEBUG || defined __DOXYGEN__ +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#if !defined TCP_FR_DEBUG || defined __DOXYGEN__ +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#if !defined TCP_RTO_DEBUG || defined __DOXYGEN__ +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#if !defined TCP_CWND_DEBUG || defined __DOXYGEN__ +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#if !defined TCP_WND_DEBUG || defined __DOXYGEN__ +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#if !defined TCP_OUTPUT_DEBUG || defined __DOXYGEN__ +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#if !defined TCP_RST_DEBUG || defined __DOXYGEN__ +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#if !defined TCP_QLEN_DEBUG || defined __DOXYGEN__ +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#if !defined UDP_DEBUG || defined __DOXYGEN__ +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#if !defined TCPIP_DEBUG || defined __DOXYGEN__ +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#if !defined SLIP_DEBUG || defined __DOXYGEN__ +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#if !defined DHCP_DEBUG || defined __DOXYGEN__ +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#if !defined AUTOIP_DEBUG || defined __DOXYGEN__ +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#if !defined DNS_DEBUG || defined __DOXYGEN__ +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP6_DEBUG: Enable debugging for IPv6. + */ +#if !defined IP6_DEBUG || defined __DOXYGEN__ +#define IP6_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP6_DEBUG: Enable debugging in dhcp6.c. + */ +#if !defined DHCP6_DEBUG || defined __DOXYGEN__ +#define DHCP6_DEBUG LWIP_DBG_OFF +#endif +/** + * @} + */ + +/** + * LWIP_TESTMODE: Changes to make unit test possible + */ +#if !defined LWIP_TESTMODE +#define LWIP_TESTMODE 0 +#endif + +/* + -------------------------------------------------- + ---------- Performance tracking options ---------- + -------------------------------------------------- +*/ +/** + * @defgroup lwip_opts_perf Performance + * @ingroup lwip_opts_debug + * @{ + */ +/** + * LWIP_PERF: Enable performance testing for lwIP + * (if enabled, arch/perf.h is included) + */ +#if !defined LWIP_PERF || defined __DOXYGEN__ +#define LWIP_PERF 0 +#endif +/** + * @} + */ + +#endif /* LWIP_HDR_OPT_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h b/Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h new file mode 100644 index 0000000..82902a4 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/pbuf.h @@ -0,0 +1,322 @@ +/** + * @file + * pbuf API + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef LWIP_HDR_PBUF_H +#define LWIP_HDR_PBUF_H + +#include "lwip/opt.h" +#include "lwip/err.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** LWIP_SUPPORT_CUSTOM_PBUF==1: Custom pbufs behave much like their pbuf type + * but they are allocated by external code (initialised by calling + * pbuf_alloced_custom()) and when pbuf_free gives up their last reference, they + * are freed by calling pbuf_custom->custom_free_function(). + * Currently, the pbuf_custom code is only needed for one specific configuration + * of IP_FRAG, unless required by external driver/application code. */ +#ifndef LWIP_SUPPORT_CUSTOM_PBUF +#define LWIP_SUPPORT_CUSTOM_PBUF ((IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG)) +#endif + +/** @ingroup pbuf + * PBUF_NEEDS_COPY(p): return a boolean value indicating whether the given + * pbuf needs to be copied in order to be kept around beyond the current call + * stack without risking being corrupted. The default setting provides safety: + * it will make a copy iof any pbuf chain that does not consist entirely of + * PBUF_ROM type pbufs. For setups with zero-copy support, it may be redefined + * to evaluate to true in all cases, for example. However, doing so also has an + * effect on the application side: any buffers that are *not* copied must also + * *not* be reused by the application after passing them to lwIP. For example, + * when setting PBUF_NEEDS_COPY to (0), after using udp_send() with a PBUF_RAM + * pbuf, the application must free the pbuf immediately, rather than reusing it + * for other purposes. For more background information on this, see tasks #6735 + * and #7896, and bugs #11400 and #49914. */ +#ifndef PBUF_NEEDS_COPY +#define PBUF_NEEDS_COPY(p) ((p)->type_internal & PBUF_TYPE_FLAG_DATA_VOLATILE) +#endif /* PBUF_NEEDS_COPY */ + +/* @todo: We need a mechanism to prevent wasting memory in every pbuf + (TCP vs. UDP, IPv4 vs. IPv6: UDP/IPv4 packets may waste up to 28 bytes) */ + +#define PBUF_TRANSPORT_HLEN 20 +#if LWIP_IPV6 +#define PBUF_IP_HLEN 40 +#else +#define PBUF_IP_HLEN 20 +#endif + +/** + * @ingroup pbuf + * Enumeration of pbuf layers + */ +typedef enum { + /** Includes spare room for transport layer header, e.g. UDP header. + * Use this if you intend to pass the pbuf to functions like udp_send(). + */ + PBUF_TRANSPORT = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN + PBUF_TRANSPORT_HLEN, + /** Includes spare room for IP header. + * Use this if you intend to pass the pbuf to functions like raw_send(). + */ + PBUF_IP = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN + PBUF_IP_HLEN, + /** Includes spare room for link layer header (ethernet header). + * Use this if you intend to pass the pbuf to functions like ethernet_output(). + * @see PBUF_LINK_HLEN + */ + PBUF_LINK = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN, + /** Includes spare room for additional encapsulation header before ethernet + * headers (e.g. 802.11). + * Use this if you intend to pass the pbuf to functions like netif->linkoutput(). + * @see PBUF_LINK_ENCAPSULATION_HLEN + */ + PBUF_RAW_TX = PBUF_LINK_ENCAPSULATION_HLEN, + /** Use this for input packets in a netif driver when calling netif->input() + * in the most common case - ethernet-layer netif driver. */ + PBUF_RAW = 0 +} pbuf_layer; + + +/* Base flags for pbuf_type definitions: */ + +/** Indicates that the payload directly follows the struct pbuf. + * This makes @ref pbuf_header work in both directions. */ +#define PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS 0x80 +/** Indicates the data stored in this pbuf can change. If this pbuf needs + * to be queued, it must be copied/duplicated. */ +#define PBUF_TYPE_FLAG_DATA_VOLATILE 0x40 +/** 4 bits are reserved for 16 allocation sources (e.g. heap, pool1, pool2, etc) + * Internally, we use: 0=heap, 1=MEMP_PBUF, 2=MEMP_PBUF_POOL -> 13 types free*/ +#define PBUF_TYPE_ALLOC_SRC_MASK 0x0F +/** Indicates this pbuf is used for RX (if not set, indicates use for TX). + * This information can be used to keep some spare RX buffers e.g. for + * receiving TCP ACKs to unblock a connection) */ +#define PBUF_ALLOC_FLAG_RX 0x0100 +/** Indicates the application needs the pbuf payload to be in one piece */ +#define PBUF_ALLOC_FLAG_DATA_CONTIGUOUS 0x0200 + +#define PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP 0x00 +#define PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF 0x01 +#define PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL 0x02 +/** First pbuf allocation type for applications */ +#define PBUF_TYPE_ALLOC_SRC_MASK_APP_MIN 0x03 +/** Last pbuf allocation type for applications */ +#define PBUF_TYPE_ALLOC_SRC_MASK_APP_MAX PBUF_TYPE_ALLOC_SRC_MASK + +/** + * @ingroup pbuf + * Enumeration of pbuf types + */ +typedef enum { + /** pbuf data is stored in RAM, used for TX mostly, struct pbuf and its payload + are allocated in one piece of contiguous memory (so the first payload byte + can be calculated from struct pbuf). + pbuf_alloc() allocates PBUF_RAM pbufs as unchained pbufs (although that might + change in future versions). + This should be used for all OUTGOING packets (TX).*/ + PBUF_RAM = (PBUF_ALLOC_FLAG_DATA_CONTIGUOUS | PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_ALLOC_SRC_MASK_STD_HEAP), + /** pbuf data is stored in ROM, i.e. struct pbuf and its payload are located in + totally different memory areas. Since it points to ROM, payload does not + have to be copied when queued for transmission. */ + PBUF_ROM = PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF, + /** pbuf comes from the pbuf pool. Much like PBUF_ROM but payload might change + so it has to be duplicated when queued before transmitting, depending on + who has a 'ref' to it. */ + PBUF_REF = (PBUF_TYPE_FLAG_DATA_VOLATILE | PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF), + /** pbuf payload refers to RAM. This one comes from a pool and should be used + for RX. Payload can be chained (scatter-gather RX) but like PBUF_RAM, struct + pbuf and its payload are allocated in one piece of contiguous memory (so + the first payload byte can be calculated from struct pbuf). + Don't use this for TX, if the pool becomes empty e.g. because of TCP queuing, + you are unable to receive TCP acks! */ + PBUF_POOL = (PBUF_ALLOC_FLAG_RX | PBUF_TYPE_FLAG_STRUCT_DATA_CONTIGUOUS | PBUF_TYPE_ALLOC_SRC_MASK_STD_MEMP_PBUF_POOL) +} pbuf_type; + + +/** indicates this packet's data should be immediately passed to the application */ +#define PBUF_FLAG_PUSH 0x01U +/** indicates this is a custom pbuf: pbuf_free calls pbuf_custom->custom_free_function() + when the last reference is released (plus custom PBUF_RAM cannot be trimmed) */ +#define PBUF_FLAG_IS_CUSTOM 0x02U +/** indicates this pbuf is UDP multicast to be looped back */ +#define PBUF_FLAG_MCASTLOOP 0x04U +/** indicates this pbuf was received as link-level broadcast */ +#define PBUF_FLAG_LLBCAST 0x08U +/** indicates this pbuf was received as link-level multicast */ +#define PBUF_FLAG_LLMCAST 0x10U +/** indicates this pbuf includes a TCP FIN flag */ +#define PBUF_FLAG_TCP_FIN 0x20U + +/** Main packet buffer struct */ +struct pbuf { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + void *payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + u16_t tot_len; + + /** length of this buffer */ + u16_t len; + + /** a bit field indicating pbuf type and allocation sources + (see PBUF_TYPE_FLAG_*, PBUF_ALLOC_FLAG_* and PBUF_TYPE_ALLOC_SRC_MASK) + */ + u8_t type_internal; + + /** misc flags */ + u8_t flags; + + /** + * the reference count always equals the number of pointers + * that refer to this pbuf. This can be pointers from an application, + * the stack itself, or pbuf->next pointers from a chain. + */ + LWIP_PBUF_REF_T ref; + + /** For incoming packets, this contains the input netif's index */ + u8_t if_idx; +}; + + +/** Helper struct for const-correctness only. + * The only meaning of this one is to provide a const payload pointer + * for PBUF_ROM type. + */ +struct pbuf_rom { + /** next pbuf in singly linked pbuf chain */ + struct pbuf *next; + + /** pointer to the actual data in the buffer */ + const void *payload; +}; + +#if LWIP_SUPPORT_CUSTOM_PBUF +/** Prototype for a function to free a custom pbuf */ +typedef void (*pbuf_free_custom_fn)(struct pbuf *p); + +/** A custom pbuf: like a pbuf, but following a function pointer to free it. */ +struct pbuf_custom { + /** The actual pbuf */ + struct pbuf pbuf; + /** This function is called when pbuf_free deallocates this pbuf(_custom) */ + pbuf_free_custom_fn custom_free_function; +}; +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ + +/** Define this to 0 to prevent freeing ooseq pbufs when the PBUF_POOL is empty */ +#ifndef PBUF_POOL_FREE_OOSEQ +#define PBUF_POOL_FREE_OOSEQ 1 +#endif /* PBUF_POOL_FREE_OOSEQ */ +#if LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ +extern volatile u8_t pbuf_free_ooseq_pending; +void pbuf_free_ooseq(void); +/** When not using sys_check_timeouts(), call PBUF_CHECK_FREE_OOSEQ() + at regular intervals from main level to check if ooseq pbufs need to be + freed! */ +#define PBUF_CHECK_FREE_OOSEQ() do { if(pbuf_free_ooseq_pending) { \ + /* pbuf_alloc() reported PBUF_POOL to be empty -> try to free some \ + ooseq queued pbufs now */ \ + pbuf_free_ooseq(); }}while(0) +#else /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ */ + /* Otherwise declare an empty PBUF_CHECK_FREE_OOSEQ */ + #define PBUF_CHECK_FREE_OOSEQ() +#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && NO_SYS && PBUF_POOL_FREE_OOSEQ*/ + +/* Initializes the pbuf module. This call is empty for now, but may not be in future. */ +#define pbuf_init() + +struct pbuf *pbuf_alloc(pbuf_layer l, u16_t length, pbuf_type type); +struct pbuf *pbuf_alloc_reference(void *payload, u16_t length, pbuf_type type); +#if LWIP_SUPPORT_CUSTOM_PBUF +struct pbuf *pbuf_alloced_custom(pbuf_layer l, u16_t length, pbuf_type type, + struct pbuf_custom *p, void *payload_mem, + u16_t payload_mem_len); +#endif /* LWIP_SUPPORT_CUSTOM_PBUF */ +void pbuf_realloc(struct pbuf *p, u16_t size); +#define pbuf_get_allocsrc(p) ((p)->type_internal & PBUF_TYPE_ALLOC_SRC_MASK) +#define pbuf_match_allocsrc(p, type) (pbuf_get_allocsrc(p) == ((type) & PBUF_TYPE_ALLOC_SRC_MASK)) +#define pbuf_match_type(p, type) pbuf_match_allocsrc(p, type) +u8_t pbuf_header(struct pbuf *p, s16_t header_size); +u8_t pbuf_header_force(struct pbuf *p, s16_t header_size); +u8_t pbuf_add_header(struct pbuf *p, size_t header_size_increment); +u8_t pbuf_add_header_force(struct pbuf *p, size_t header_size_increment); +u8_t pbuf_remove_header(struct pbuf *p, size_t header_size); +struct pbuf *pbuf_free_header(struct pbuf *q, u16_t size); +void pbuf_ref(struct pbuf *p); +u8_t pbuf_free(struct pbuf *p); +u16_t pbuf_clen(const struct pbuf *p); +void pbuf_cat(struct pbuf *head, struct pbuf *tail); +void pbuf_chain(struct pbuf *head, struct pbuf *tail); +struct pbuf *pbuf_dechain(struct pbuf *p); +err_t pbuf_copy(struct pbuf *p_to, const struct pbuf *p_from); +u16_t pbuf_copy_partial(const struct pbuf *p, void *dataptr, u16_t len, u16_t offset); +void *pbuf_get_contiguous(const struct pbuf *p, void *buffer, size_t bufsize, u16_t len, u16_t offset); +err_t pbuf_take(struct pbuf *buf, const void *dataptr, u16_t len); +err_t pbuf_take_at(struct pbuf *buf, const void *dataptr, u16_t len, u16_t offset); +struct pbuf *pbuf_skip(struct pbuf* in, u16_t in_offset, u16_t* out_offset); +struct pbuf *pbuf_coalesce(struct pbuf *p, pbuf_layer layer); +struct pbuf *pbuf_clone(pbuf_layer l, pbuf_type type, struct pbuf *p); +#if LWIP_CHECKSUM_ON_COPY +err_t pbuf_fill_chksum(struct pbuf *p, u16_t start_offset, const void *dataptr, + u16_t len, u16_t *chksum); +#endif /* LWIP_CHECKSUM_ON_COPY */ +#if LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE +void pbuf_split_64k(struct pbuf *p, struct pbuf **rest); +#endif /* LWIP_TCP && TCP_QUEUE_OOSEQ && LWIP_WND_SCALE */ + +u8_t pbuf_get_at(const struct pbuf* p, u16_t offset); +int pbuf_try_get_at(const struct pbuf* p, u16_t offset); +void pbuf_put_at(struct pbuf* p, u16_t offset, u8_t data); +u16_t pbuf_memcmp(const struct pbuf* p, u16_t offset, const void* s2, u16_t n); +u16_t pbuf_memfind(const struct pbuf* p, const void* mem, u16_t mem_len, u16_t start_offset); +u16_t pbuf_strstr(const struct pbuf* p, const char* substr); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PBUF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h new file mode 100644 index 0000000..2d3b2fd --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/altcp_priv.h @@ -0,0 +1,146 @@ +/** + * @file + * Application layered TCP connection API (to be used from TCPIP thread)\n + * This interface mimics the tcp callback API to the application while preventing + * direct linking (much like virtual functions). + * This way, an application can make use of other application layer protocols + * on top of TCP without knowing the details (e.g. TLS, proxy connection). + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_ALTCP_PRIV_H +#define LWIP_HDR_ALTCP_PRIV_H + +#include "lwip/opt.h" + +#if LWIP_ALTCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/altcp.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct altcp_pcb *altcp_alloc(void); +void altcp_free(struct altcp_pcb *conn); + +/* Function prototypes for application layers */ +typedef void (*altcp_set_poll_fn)(struct altcp_pcb *conn, u8_t interval); +typedef void (*altcp_recved_fn)(struct altcp_pcb *conn, u16_t len); +typedef err_t (*altcp_bind_fn)(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port); +typedef err_t (*altcp_connect_fn)(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port, altcp_connected_fn connected); + +typedef struct altcp_pcb *(*altcp_listen_fn)(struct altcp_pcb *conn, u8_t backlog, err_t *err); + +typedef void (*altcp_abort_fn)(struct altcp_pcb *conn); +typedef err_t (*altcp_close_fn)(struct altcp_pcb *conn); +typedef err_t (*altcp_shutdown_fn)(struct altcp_pcb *conn, int shut_rx, int shut_tx); + +typedef err_t (*altcp_write_fn)(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags); +typedef err_t (*altcp_output_fn)(struct altcp_pcb *conn); + +typedef u16_t (*altcp_mss_fn)(struct altcp_pcb *conn); +typedef u16_t (*altcp_sndbuf_fn)(struct altcp_pcb *conn); +typedef u16_t (*altcp_sndqueuelen_fn)(struct altcp_pcb *conn); +typedef void (*altcp_nagle_disable_fn)(struct altcp_pcb *conn); +typedef void (*altcp_nagle_enable_fn)(struct altcp_pcb *conn); +typedef int (*altcp_nagle_disabled_fn)(struct altcp_pcb *conn); + +typedef void (*altcp_setprio_fn)(struct altcp_pcb *conn, u8_t prio); + +typedef void (*altcp_dealloc_fn)(struct altcp_pcb *conn); + +typedef err_t (*altcp_get_tcp_addrinfo_fn)(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port); +typedef ip_addr_t *(*altcp_get_ip_fn)(struct altcp_pcb *conn, int local); +typedef u16_t (*altcp_get_port_fn)(struct altcp_pcb *conn, int local); + +#ifdef LWIP_DEBUG +typedef enum tcp_state (*altcp_dbg_get_tcp_state_fn)(struct altcp_pcb *conn); +#endif + +struct altcp_functions { + altcp_set_poll_fn set_poll; + altcp_recved_fn recved; + altcp_bind_fn bind; + altcp_connect_fn connect; + altcp_listen_fn listen; + altcp_abort_fn abort; + altcp_close_fn close; + altcp_shutdown_fn shutdown; + altcp_write_fn write; + altcp_output_fn output; + altcp_mss_fn mss; + altcp_sndbuf_fn sndbuf; + altcp_sndqueuelen_fn sndqueuelen; + altcp_nagle_disable_fn nagle_disable; + altcp_nagle_enable_fn nagle_enable; + altcp_nagle_disabled_fn nagle_disabled; + altcp_setprio_fn setprio; + altcp_dealloc_fn dealloc; + altcp_get_tcp_addrinfo_fn addrinfo; + altcp_get_ip_fn getip; + altcp_get_port_fn getport; +#ifdef LWIP_DEBUG + altcp_dbg_get_tcp_state_fn dbg_get_tcp_state; +#endif +}; + +void altcp_default_set_poll(struct altcp_pcb *conn, u8_t interval); +void altcp_default_recved(struct altcp_pcb *conn, u16_t len); +err_t altcp_default_bind(struct altcp_pcb *conn, const ip_addr_t *ipaddr, u16_t port); +err_t altcp_default_shutdown(struct altcp_pcb *conn, int shut_rx, int shut_tx); +err_t altcp_default_write(struct altcp_pcb *conn, const void *dataptr, u16_t len, u8_t apiflags); +err_t altcp_default_output(struct altcp_pcb *conn); +u16_t altcp_default_mss(struct altcp_pcb *conn); +u16_t altcp_default_sndbuf(struct altcp_pcb *conn); +u16_t altcp_default_sndqueuelen(struct altcp_pcb *conn); +void altcp_default_nagle_disable(struct altcp_pcb *conn); +void altcp_default_nagle_enable(struct altcp_pcb *conn); +int altcp_default_nagle_disabled(struct altcp_pcb *conn); +void altcp_default_setprio(struct altcp_pcb *conn, u8_t prio); +void altcp_default_dealloc(struct altcp_pcb *conn); +err_t altcp_default_get_tcp_addrinfo(struct altcp_pcb *conn, int local, ip_addr_t *addr, u16_t *port); +ip_addr_t *altcp_default_get_ip(struct altcp_pcb *conn, int local); +u16_t altcp_default_get_port(struct altcp_pcb *conn, int local); +#ifdef LWIP_DEBUG +enum tcp_state altcp_default_dbg_get_tcp_state(struct altcp_pcb *conn); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_ALTCP */ + +#endif /* LWIP_HDR_ALTCP_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h new file mode 100644 index 0000000..9e8ffc9 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/api_msg.h @@ -0,0 +1,272 @@ +/** + * @file + * netconn API lwIP internal implementations (do not use in application code) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_API_MSG_H +#define LWIP_HDR_API_MSG_H + +#include "lwip/opt.h" + +#include "lwip/arch.h" +#include "lwip/ip_addr.h" +#include "lwip/err.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/api.h" +#include "lwip/priv/tcpip_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_NETCONN || LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ +/* Note: Netconn API is always available when sockets are enabled - + * sockets are implemented on top of them */ + +#if LWIP_MPU_COMPATIBLE +#if LWIP_NETCONN_SEM_PER_THREAD +#define API_MSG_M_DEF_SEM(m) *m +#else +#define API_MSG_M_DEF_SEM(m) API_MSG_M_DEF(m) +#endif +#else /* LWIP_MPU_COMPATIBLE */ +#define API_MSG_M_DEF_SEM(m) API_MSG_M_DEF(m) +#endif /* LWIP_MPU_COMPATIBLE */ + +/* For the netconn API, these values are use as a bitmask! */ +#define NETCONN_SHUT_RD 1 +#define NETCONN_SHUT_WR 2 +#define NETCONN_SHUT_RDWR (NETCONN_SHUT_RD | NETCONN_SHUT_WR) + +/* IP addresses and port numbers are expected to be in + * the same byte order as in the corresponding pcb. + */ +/** This struct includes everything that is necessary to execute a function + for a netconn in another thread context (mainly used to process netconns + in the tcpip_thread context to be thread safe). */ +struct api_msg { + /** The netconn which to process - always needed: it includes the semaphore + which is used to block the application thread until the function finished. */ + struct netconn *conn; + /** The return value of the function executed in tcpip_thread. */ + err_t err; + /** Depending on the executed function, one of these union members is used */ + union { + /** used for lwip_netconn_do_send */ + struct netbuf *b; + /** used for lwip_netconn_do_newconn */ + struct { + u8_t proto; + } n; + /** used for lwip_netconn_do_bind and lwip_netconn_do_connect */ + struct { + API_MSG_M_DEF_C(ip_addr_t, ipaddr); + u16_t port; + u8_t if_idx; + } bc; + /** used for lwip_netconn_do_getaddr */ + struct { + ip_addr_t API_MSG_M_DEF(ipaddr); + u16_t API_MSG_M_DEF(port); + u8_t local; + } ad; + /** used for lwip_netconn_do_write */ + struct { + /** current vector to write */ + const struct netvector *vector; + /** number of unwritten vectors */ + u16_t vector_cnt; + /** offset into current vector */ + size_t vector_off; + /** total length across vectors */ + size_t len; + /** offset into total length/output of bytes written when err == ERR_OK */ + size_t offset; + u8_t apiflags; +#if LWIP_SO_SNDTIMEO + u32_t time_started; +#endif /* LWIP_SO_SNDTIMEO */ + } w; + /** used for lwip_netconn_do_recv */ + struct { + size_t len; + } r; +#if LWIP_TCP + /** used for lwip_netconn_do_close (/shutdown) */ + struct { + u8_t shut; +#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER + u32_t time_started; +#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + u8_t polls_left; +#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + } sd; +#endif /* LWIP_TCP */ +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) + /** used for lwip_netconn_do_join_leave_group */ + struct { + API_MSG_M_DEF_C(ip_addr_t, multiaddr); + API_MSG_M_DEF_C(ip_addr_t, netif_addr); + u8_t if_idx; + enum netconn_igmp join_or_leave; + } jl; +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ +#if TCP_LISTEN_BACKLOG + struct { + u8_t backlog; + } lb; +#endif /* TCP_LISTEN_BACKLOG */ + } msg; +#if LWIP_NETCONN_SEM_PER_THREAD + sys_sem_t* op_completed_sem; +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ +}; + +#if LWIP_NETCONN_SEM_PER_THREAD +#define LWIP_API_MSG_SEM(msg) ((msg)->op_completed_sem) +#else /* LWIP_NETCONN_SEM_PER_THREAD */ +#define LWIP_API_MSG_SEM(msg) (&(msg)->conn->op_completed) +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + +#if LWIP_DNS +/** As lwip_netconn_do_gethostbyname requires more arguments but doesn't require a netconn, + it has its own struct (to avoid struct api_msg getting bigger than necessary). + lwip_netconn_do_gethostbyname must be called using tcpip_callback instead of tcpip_apimsg + (see netconn_gethostbyname). */ +struct dns_api_msg { + /** Hostname to query or dotted IP address string */ +#if LWIP_MPU_COMPATIBLE + char name[DNS_MAX_NAME_LENGTH]; +#else /* LWIP_MPU_COMPATIBLE */ + const char *name; +#endif /* LWIP_MPU_COMPATIBLE */ + /** The resolved address is stored here */ + ip_addr_t API_MSG_M_DEF(addr); +#if LWIP_IPV4 && LWIP_IPV6 + /** Type of resolve call */ + u8_t dns_addrtype; +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + /** This semaphore is posted when the name is resolved, the application thread + should wait on it. */ + sys_sem_t API_MSG_M_DEF_SEM(sem); + /** Errors are given back here */ + err_t API_MSG_M_DEF(err); +}; +#endif /* LWIP_DNS */ + +#if LWIP_NETCONN_FULLDUPLEX +int lwip_netconn_is_deallocated_msg(void *msg); +#endif +int lwip_netconn_is_err_msg(void *msg, err_t *err); +void lwip_netconn_do_newconn (void *m); +void lwip_netconn_do_delconn (void *m); +void lwip_netconn_do_bind (void *m); +void lwip_netconn_do_bind_if (void *m); +void lwip_netconn_do_connect (void *m); +void lwip_netconn_do_disconnect (void *m); +void lwip_netconn_do_listen (void *m); +void lwip_netconn_do_send (void *m); +void lwip_netconn_do_recv (void *m); +#if TCP_LISTEN_BACKLOG +void lwip_netconn_do_accepted (void *m); +#endif /* TCP_LISTEN_BACKLOG */ +void lwip_netconn_do_write (void *m); +void lwip_netconn_do_getaddr (void *m); +void lwip_netconn_do_close (void *m); +void lwip_netconn_do_shutdown (void *m); +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) +void lwip_netconn_do_join_leave_group(void *m); +void lwip_netconn_do_join_leave_group_netif(void *m); +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ + +#if LWIP_DNS +void lwip_netconn_do_gethostbyname(void *arg); +#endif /* LWIP_DNS */ + +struct netconn* netconn_alloc(enum netconn_type t, netconn_callback callback); +void netconn_free(struct netconn *conn); + +#endif /* LWIP_NETCONN || LWIP_SOCKET */ + +#if LWIP_NETIF_API /* don't build if not configured for use in lwipopts.h */ + +/* netifapi related lwIP internal definitions */ + +#if LWIP_MPU_COMPATIBLE +#define NETIFAPI_IPADDR_DEF(type, m) type m +#else /* LWIP_MPU_COMPATIBLE */ +#define NETIFAPI_IPADDR_DEF(type, m) const type * m +#endif /* LWIP_MPU_COMPATIBLE */ + +typedef void (*netifapi_void_fn)(struct netif *netif); +typedef err_t (*netifapi_errt_fn)(struct netif *netif); + +struct netifapi_msg { + struct tcpip_api_call_data call; + struct netif *netif; + union { + struct { +#if LWIP_IPV4 + NETIFAPI_IPADDR_DEF(ip4_addr_t, ipaddr); + NETIFAPI_IPADDR_DEF(ip4_addr_t, netmask); + NETIFAPI_IPADDR_DEF(ip4_addr_t, gw); +#endif /* LWIP_IPV4 */ + void *state; + netif_init_fn init; + netif_input_fn input; + } add; + struct { + netifapi_void_fn voidfunc; + netifapi_errt_fn errtfunc; + } common; + struct { +#if LWIP_MPU_COMPATIBLE + char name[NETIF_NAMESIZE]; +#else /* LWIP_MPU_COMPATIBLE */ + char *name; +#endif /* LWIP_MPU_COMPATIBLE */ + u8_t index; + } ifs; + } msg; +}; + +#endif /* LWIP_NETIF_API */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_API_MSG_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h new file mode 100644 index 0000000..8630d75 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/mem_priv.h @@ -0,0 +1,84 @@ +/** + * @file + * lwIP internal memory implementations (do not use in application code) + */ + +/* + * Copyright (c) 2018 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#ifndef LWIP_HDR_MEM_PRIV_H +#define LWIP_HDR_MEM_PRIV_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwip/mem.h" + +#if MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK +/* if MEM_OVERFLOW_CHECK or MEMP_OVERFLOW_CHECK is turned on, we reserve some + * bytes at the beginning and at the end of each element, initialize them as + * 0xcd and check them later. + * If MEM(P)_OVERFLOW_CHECK is >= 2, on every call to mem(p)_malloc or mem(p)_free, + * every single element in each pool/heap is checked! + * This is VERY SLOW but also very helpful. + * MEM_SANITY_REGION_BEFORE and MEM_SANITY_REGION_AFTER can be overridden in + * lwipopts.h to change the amount reserved for checking. */ +#ifndef MEM_SANITY_REGION_BEFORE +#define MEM_SANITY_REGION_BEFORE 16 +#endif /* MEM_SANITY_REGION_BEFORE*/ +#if MEM_SANITY_REGION_BEFORE > 0 +#define MEM_SANITY_REGION_BEFORE_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SANITY_REGION_BEFORE) +#else +#define MEM_SANITY_REGION_BEFORE_ALIGNED 0 +#endif /* MEM_SANITY_REGION_BEFORE*/ +#ifndef MEM_SANITY_REGION_AFTER +#define MEM_SANITY_REGION_AFTER 16 +#endif /* MEM_SANITY_REGION_AFTER*/ +#if MEM_SANITY_REGION_AFTER > 0 +#define MEM_SANITY_REGION_AFTER_ALIGNED LWIP_MEM_ALIGN_SIZE(MEM_SANITY_REGION_AFTER) +#else +#define MEM_SANITY_REGION_AFTER_ALIGNED 0 +#endif /* MEM_SANITY_REGION_AFTER*/ + +void mem_overflow_init_raw(void *p, size_t size); +void mem_overflow_check_raw(void *p, size_t size, const char *descr1, const char *descr2); + +#endif /* MEM_OVERFLOW_CHECK || MEMP_OVERFLOW_CHECK */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_MEMP_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h new file mode 100644 index 0000000..1f14cb1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_priv.h @@ -0,0 +1,161 @@ +/** + * @file + * memory pools lwIP internal implementations (do not use in application code) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef LWIP_HDR_MEMP_PRIV_H +#define LWIP_HDR_MEMP_PRIV_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include "lwip/mem.h" +#include "lwip/priv/mem_priv.h" + +#if MEMP_OVERFLOW_CHECK + + +/* MEMP_SIZE: save space for struct memp and for sanity check */ +#define MEMP_SIZE (LWIP_MEM_ALIGN_SIZE(sizeof(struct memp)) + MEM_SANITY_REGION_BEFORE_ALIGNED) +#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x) + MEM_SANITY_REGION_AFTER_ALIGNED) + +#else /* MEMP_OVERFLOW_CHECK */ + +/* No sanity checks + * We don't need to preserve the struct memp while not allocated, so we + * can save a little space and set MEMP_SIZE to 0. + */ +#define MEMP_SIZE 0 +#define MEMP_ALIGN_SIZE(x) (LWIP_MEM_ALIGN_SIZE(x)) + +#endif /* MEMP_OVERFLOW_CHECK */ + +#if !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK +struct memp { + struct memp *next; +#if MEMP_OVERFLOW_CHECK + const char *file; + int line; +#endif /* MEMP_OVERFLOW_CHECK */ +}; +#endif /* !MEMP_MEM_MALLOC || MEMP_OVERFLOW_CHECK */ + +#if MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS +/* Use a helper type to get the start and end of the user "memory pools" for mem_malloc */ +typedef enum { + /* Get the first (via: + MEMP_POOL_HELPER_START = ((u8_t) 1*MEMP_POOL_A + 0*MEMP_POOL_B + 0*MEMP_POOL_C + 0)*/ + MEMP_POOL_HELPER_FIRST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START 1 +#define LWIP_MALLOC_MEMPOOL(num, size) * MEMP_POOL_##size + 0 +#define LWIP_MALLOC_MEMPOOL_END +#include "lwip/priv/memp_std.h" + ) , + /* Get the last (via: + MEMP_POOL_HELPER_END = ((u8_t) 0 + MEMP_POOL_A*0 + MEMP_POOL_B*0 + MEMP_POOL_C*1) */ + MEMP_POOL_HELPER_LAST = ((u8_t) +#define LWIP_MEMPOOL(name,num,size,desc) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL(num, size) 0 + MEMP_POOL_##size * +#define LWIP_MALLOC_MEMPOOL_END 1 +#include "lwip/priv/memp_std.h" + ) +} memp_pool_helper_t; + +/* The actual start and stop values are here (cast them over) + We use this helper type and these defines so we can avoid using const memp_t values */ +#define MEMP_POOL_FIRST ((memp_t) MEMP_POOL_HELPER_FIRST) +#define MEMP_POOL_LAST ((memp_t) MEMP_POOL_HELPER_LAST) +#endif /* MEM_USE_POOLS && MEMP_USE_CUSTOM_POOLS */ + +/** Memory pool descriptor */ +struct memp_desc { +#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY + /** Textual description */ + const char *desc; +#endif /* LWIP_DEBUG || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY */ +#if MEMP_STATS + /** Statistics */ + struct stats_mem *stats; +#endif + + /** Element size */ + u16_t size; + +#if !MEMP_MEM_MALLOC + /** Number of elements */ + u16_t num; + + /** Base address */ + u8_t *base; + + /** First free element of each pool. Elements form a linked list. */ + struct memp **tab; +#endif /* MEMP_MEM_MALLOC */ +}; + +#if defined(LWIP_DEBUG) || MEMP_OVERFLOW_CHECK || LWIP_STATS_DISPLAY +#define DECLARE_LWIP_MEMPOOL_DESC(desc) (desc), +#else +#define DECLARE_LWIP_MEMPOOL_DESC(desc) +#endif + +#if MEMP_STATS +#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name) static struct stats_mem name; +#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name) &name, +#else +#define LWIP_MEMPOOL_DECLARE_STATS_INSTANCE(name) +#define LWIP_MEMPOOL_DECLARE_STATS_REFERENCE(name) +#endif + +void memp_init_pool(const struct memp_desc *desc); + +#if MEMP_OVERFLOW_CHECK +void *memp_malloc_pool_fn(const struct memp_desc* desc, const char* file, const int line); +#define memp_malloc_pool(d) memp_malloc_pool_fn((d), __FILE__, __LINE__) +#else +void *memp_malloc_pool(const struct memp_desc *desc); +#endif +void memp_free_pool(const struct memp_desc* desc, void *mem); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_MEMP_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h new file mode 100644 index 0000000..669ad4d --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/memp_std.h @@ -0,0 +1,153 @@ +/** + * @file + * lwIP internal memory pools (do not use in application code) + * This file is deliberately included multiple times: once with empty + * definition of LWIP_MEMPOOL() to handle all includes and multiple times + * to build up various lists of mem pools. + */ + +/* + * SETUP: Make sure we define everything we will need. + * + * We have create three types of pools: + * 1) MEMPOOL - standard pools + * 2) MALLOC_MEMPOOL - to be used by mem_malloc in mem.c + * 3) PBUF_MEMPOOL - a mempool of pbuf's, so include space for the pbuf struct + * + * If the include'r doesn't require any special treatment of each of the types + * above, then will declare #2 & #3 to be just standard mempools. + */ +#ifndef LWIP_MALLOC_MEMPOOL +/* This treats "malloc pools" just like any other pool. + The pools are a little bigger to provide 'size' as the amount of user data. */ +#define LWIP_MALLOC_MEMPOOL(num, size) LWIP_MEMPOOL(POOL_##size, num, (size + LWIP_MEM_ALIGN_SIZE(sizeof(struct memp_malloc_helper))), "MALLOC_"#size) +#define LWIP_MALLOC_MEMPOOL_START +#define LWIP_MALLOC_MEMPOOL_END +#endif /* LWIP_MALLOC_MEMPOOL */ + +#ifndef LWIP_PBUF_MEMPOOL +/* This treats "pbuf pools" just like any other pool. + * Allocates buffers for a pbuf struct AND a payload size */ +#define LWIP_PBUF_MEMPOOL(name, num, payload, desc) LWIP_MEMPOOL(name, num, (LWIP_MEM_ALIGN_SIZE(sizeof(struct pbuf)) + LWIP_MEM_ALIGN_SIZE(payload)), desc) +#endif /* LWIP_PBUF_MEMPOOL */ + + +/* + * A list of internal pools used by LWIP. + * + * LWIP_MEMPOOL(pool_name, number_elements, element_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + */ +#if LWIP_RAW +LWIP_MEMPOOL(RAW_PCB, MEMP_NUM_RAW_PCB, sizeof(struct raw_pcb), "RAW_PCB") +#endif /* LWIP_RAW */ + +#if LWIP_UDP +LWIP_MEMPOOL(UDP_PCB, MEMP_NUM_UDP_PCB, sizeof(struct udp_pcb), "UDP_PCB") +#endif /* LWIP_UDP */ + +#if LWIP_TCP +LWIP_MEMPOOL(TCP_PCB, MEMP_NUM_TCP_PCB, sizeof(struct tcp_pcb), "TCP_PCB") +LWIP_MEMPOOL(TCP_PCB_LISTEN, MEMP_NUM_TCP_PCB_LISTEN, sizeof(struct tcp_pcb_listen), "TCP_PCB_LISTEN") +LWIP_MEMPOOL(TCP_SEG, MEMP_NUM_TCP_SEG, sizeof(struct tcp_seg), "TCP_SEG") +#endif /* LWIP_TCP */ + +#if LWIP_ALTCP && LWIP_TCP +LWIP_MEMPOOL(ALTCP_PCB, MEMP_NUM_ALTCP_PCB, sizeof(struct altcp_pcb), "ALTCP_PCB") +#endif /* LWIP_ALTCP && LWIP_TCP */ + +#if LWIP_IPV4 && IP_REASSEMBLY +LWIP_MEMPOOL(REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip_reassdata), "REASSDATA") +#endif /* LWIP_IPV4 && IP_REASSEMBLY */ +#if (IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF) || (LWIP_IPV6 && LWIP_IPV6_FRAG) +LWIP_MEMPOOL(FRAG_PBUF, MEMP_NUM_FRAG_PBUF, sizeof(struct pbuf_custom_ref),"FRAG_PBUF") +#endif /* IP_FRAG && !LWIP_NETIF_TX_SINGLE_PBUF || (LWIP_IPV6 && LWIP_IPV6_FRAG) */ + +#if LWIP_NETCONN || LWIP_SOCKET +LWIP_MEMPOOL(NETBUF, MEMP_NUM_NETBUF, sizeof(struct netbuf), "NETBUF") +LWIP_MEMPOOL(NETCONN, MEMP_NUM_NETCONN, sizeof(struct netconn), "NETCONN") +#endif /* LWIP_NETCONN || LWIP_SOCKET */ + +#if NO_SYS==0 +LWIP_MEMPOOL(TCPIP_MSG_API, MEMP_NUM_TCPIP_MSG_API, sizeof(struct tcpip_msg), "TCPIP_MSG_API") +#if LWIP_MPU_COMPATIBLE +LWIP_MEMPOOL(API_MSG, MEMP_NUM_API_MSG, sizeof(struct api_msg), "API_MSG") +#if LWIP_DNS +LWIP_MEMPOOL(DNS_API_MSG, MEMP_NUM_DNS_API_MSG, sizeof(struct dns_api_msg), "DNS_API_MSG") +#endif +#if LWIP_SOCKET && !LWIP_TCPIP_CORE_LOCKING +LWIP_MEMPOOL(SOCKET_SETGETSOCKOPT_DATA, MEMP_NUM_SOCKET_SETGETSOCKOPT_DATA, sizeof(struct lwip_setgetsockopt_data), "SOCKET_SETGETSOCKOPT_DATA") +#endif +#if LWIP_SOCKET && (LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL) +LWIP_MEMPOOL(SELECT_CB, MEMP_NUM_SELECT_CB, sizeof(struct lwip_select_cb), "SELECT_CB") +#endif /* LWIP_SOCKET && (LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL) */ +#if LWIP_NETIF_API +LWIP_MEMPOOL(NETIFAPI_MSG, MEMP_NUM_NETIFAPI_MSG, sizeof(struct netifapi_msg), "NETIFAPI_MSG") +#endif +#endif /* LWIP_MPU_COMPATIBLE */ +#if !LWIP_TCPIP_CORE_LOCKING_INPUT +LWIP_MEMPOOL(TCPIP_MSG_INPKT,MEMP_NUM_TCPIP_MSG_INPKT, sizeof(struct tcpip_msg), "TCPIP_MSG_INPKT") +#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ +#endif /* NO_SYS==0 */ + +#if LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING +LWIP_MEMPOOL(ARP_QUEUE, MEMP_NUM_ARP_QUEUE, sizeof(struct etharp_q_entry), "ARP_QUEUE") +#endif /* LWIP_IPV4 && LWIP_ARP && ARP_QUEUEING */ + +#if LWIP_IGMP +LWIP_MEMPOOL(IGMP_GROUP, MEMP_NUM_IGMP_GROUP, sizeof(struct igmp_group), "IGMP_GROUP") +#endif /* LWIP_IGMP */ + +#if LWIP_TIMERS && !LWIP_TIMERS_CUSTOM +LWIP_MEMPOOL(SYS_TIMEOUT, MEMP_NUM_SYS_TIMEOUT, sizeof(struct sys_timeo), "SYS_TIMEOUT") +#endif /* LWIP_TIMERS && !LWIP_TIMERS_CUSTOM */ + +#if LWIP_DNS && LWIP_SOCKET +LWIP_MEMPOOL(NETDB, MEMP_NUM_NETDB, NETDB_ELEM_SIZE, "NETDB") +#endif /* LWIP_DNS && LWIP_SOCKET */ +#if LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC +LWIP_MEMPOOL(LOCALHOSTLIST, MEMP_NUM_LOCALHOSTLIST, LOCALHOSTLIST_ELEM_SIZE, "LOCALHOSTLIST") +#endif /* LWIP_DNS && DNS_LOCAL_HOSTLIST && DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +#if LWIP_IPV6 && LWIP_ND6_QUEUEING +LWIP_MEMPOOL(ND6_QUEUE, MEMP_NUM_ND6_QUEUE, sizeof(struct nd6_q_entry), "ND6_QUEUE") +#endif /* LWIP_IPV6 && LWIP_ND6_QUEUEING */ + +#if LWIP_IPV6 && LWIP_IPV6_REASS +LWIP_MEMPOOL(IP6_REASSDATA, MEMP_NUM_REASSDATA, sizeof(struct ip6_reassdata), "IP6_REASSDATA") +#endif /* LWIP_IPV6 && LWIP_IPV6_REASS */ + +#if LWIP_IPV6 && LWIP_IPV6_MLD +LWIP_MEMPOOL(MLD6_GROUP, MEMP_NUM_MLD6_GROUP, sizeof(struct mld_group), "MLD6_GROUP") +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + + +/* + * A list of pools of pbuf's used by LWIP. + * + * LWIP_PBUF_MEMPOOL(pool_name, number_elements, pbuf_payload_size, pool_description) + * creates a pool name MEMP_pool_name. description is used in stats.c + * This allocates enough space for the pbuf struct and a payload. + * (Example: pbuf_payload_size=0 allocates only size for the struct) + */ +LWIP_MEMPOOL(PBUF, MEMP_NUM_PBUF, sizeof(struct pbuf), "PBUF_REF/ROM") +LWIP_PBUF_MEMPOOL(PBUF_POOL, PBUF_POOL_SIZE, PBUF_POOL_BUFSIZE, "PBUF_POOL") + + +/* + * Allow for user-defined pools; this must be explicitly set in lwipopts.h + * since the default is to NOT look for lwippools.h + */ +#if MEMP_USE_CUSTOM_POOLS +#include "lwippools.h" +#endif /* MEMP_USE_CUSTOM_POOLS */ + +/* + * REQUIRED CLEANUP: Clear up so we don't get "multiply defined" error later + * (#undef is ignored for something that is not defined) + */ +#undef LWIP_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL +#undef LWIP_MALLOC_MEMPOOL_START +#undef LWIP_MALLOC_MEMPOOL_END +#undef LWIP_PBUF_MEMPOOL diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h new file mode 100644 index 0000000..cc3007d --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/nd6_priv.h @@ -0,0 +1,142 @@ +/** + * @file + * + * Neighbor discovery and stateless address autoconfiguration for IPv6. + * Aims to be compliant with RFC 4861 (Neighbor discovery) and RFC 4862 + * (Address autoconfiguration). + */ + +/* + * Copyright (c) 2010 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#ifndef LWIP_HDR_ND6_PRIV_H +#define LWIP_HDR_ND6_PRIV_H + +#include "lwip/opt.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip6_addr.h" +#include "lwip/netif.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_ND6_QUEUEING +/** struct for queueing outgoing packets for unknown address + * defined here to be accessed by memp.h + */ +struct nd6_q_entry { + struct nd6_q_entry *next; + struct pbuf *p; +}; +#endif /* LWIP_ND6_QUEUEING */ + +/** Struct for tables. */ +struct nd6_neighbor_cache_entry { + ip6_addr_t next_hop_address; + struct netif *netif; + u8_t lladdr[NETIF_MAX_HWADDR_LEN]; + /*u32_t pmtu;*/ +#if LWIP_ND6_QUEUEING + /** Pointer to queue of pending outgoing packets on this entry. */ + struct nd6_q_entry *q; +#else /* LWIP_ND6_QUEUEING */ + /** Pointer to a single pending outgoing packet on this entry. */ + struct pbuf *q; +#endif /* LWIP_ND6_QUEUEING */ + u8_t state; + u8_t isrouter; + union { + u32_t reachable_time; /* in seconds */ + u32_t delay_time; /* ticks (ND6_TMR_INTERVAL) */ + u32_t probes_sent; + u32_t stale_time; /* ticks (ND6_TMR_INTERVAL) */ + } counter; +}; + +struct nd6_destination_cache_entry { + ip6_addr_t destination_addr; + ip6_addr_t next_hop_addr; + u16_t pmtu; + u32_t age; +}; + +struct nd6_prefix_list_entry { + ip6_addr_t prefix; + struct netif *netif; + u32_t invalidation_timer; /* in seconds */ +}; + +struct nd6_router_list_entry { + struct nd6_neighbor_cache_entry *neighbor_entry; + u32_t invalidation_timer; /* in seconds */ + u8_t flags; +}; + +enum nd6_neighbor_cache_entry_state { + ND6_NO_ENTRY = 0, + ND6_INCOMPLETE, + ND6_REACHABLE, + ND6_STALE, + ND6_DELAY, + ND6_PROBE +}; + +#define ND6_HOPLIM 255 /* maximum hop limit, required in all ND packets */ + +#define ND6_2HRS 7200 /* two hours, expressed in number of seconds */ + +/* Router tables. */ +/* @todo make these static? and entries accessible through API? */ +extern struct nd6_neighbor_cache_entry neighbor_cache[]; +extern struct nd6_destination_cache_entry destination_cache[]; +extern struct nd6_prefix_list_entry prefix_list[]; +extern struct nd6_router_list_entry default_router_list[]; + +/* Default values, can be updated by a RA message. */ +extern u32_t reachable_time; +extern u32_t retrans_timer; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 */ + +#endif /* LWIP_HDR_ND6_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h new file mode 100644 index 0000000..d4561d4 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/raw_priv.h @@ -0,0 +1,69 @@ +/** + * @file + * raw API internal implementations (do not use in application code) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_RAW_PRIV_H +#define LWIP_HDR_RAW_PRIV_H + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/raw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** return codes for raw_input */ +typedef enum raw_input_state +{ + RAW_INPUT_NONE = 0, /* pbuf did not match any pcbs */ + RAW_INPUT_EATEN, /* pbuf handed off and delivered to pcb */ + RAW_INPUT_DELIVERED /* pbuf only delivered to pcb (pbuf can still be referenced) */ +} raw_input_state_t; + +/* The following functions are the lower layer interface to RAW. */ +raw_input_state_t raw_input(struct pbuf *p, struct netif *inp); + +void raw_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_RAW */ + +#endif /* LWIP_HDR_RAW_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h new file mode 100644 index 0000000..d8f9904 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/sockets_priv.h @@ -0,0 +1,175 @@ +/** + * @file + * Sockets API internal implementations (do not use in application code) + */ + +/* + * Copyright (c) 2017 Joel Cunningham, Garmin International, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Joel Cunningham + * + */ +#ifndef LWIP_HDR_SOCKETS_PRIV_H +#define LWIP_HDR_SOCKETS_PRIV_H + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/err.h" +#include "lwip/sockets.h" +#include "lwip/sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NUM_SOCKETS MEMP_NUM_NETCONN + +/** This is overridable for the rare case where more than 255 threads + * select on the same socket... + */ +#ifndef SELWAIT_T +#define SELWAIT_T u8_t +#endif + +union lwip_sock_lastdata { + struct netbuf *netbuf; + struct pbuf *pbuf; +}; + +/** Contains all internal pointers and states used for a socket */ +struct lwip_sock { + /** sockets currently are built on netconns, each socket has one netconn */ + struct netconn *conn; + /** data that was left from the previous read */ + union lwip_sock_lastdata lastdata; +#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL + /** number of times data was received, set by event_callback(), + tested by the receive and select functions */ + s16_t rcvevent; + /** number of times data was ACKed (free send buffer), set by event_callback(), + tested by select */ + u16_t sendevent; + /** error happened for this socket, set by event_callback(), tested by select */ + u16_t errevent; + /** counter of how many threads are waiting for this socket using select */ + SELWAIT_T select_waiting; +#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */ +#if LWIP_NETCONN_FULLDUPLEX + /* counter of how many threads are using a struct lwip_sock (not the 'int') */ + u8_t fd_used; + /* status of pending close/delete actions */ + u8_t fd_free_pending; +#define LWIP_SOCK_FD_FREE_TCP 1 +#define LWIP_SOCK_FD_FREE_FREE 2 +#endif +}; + +#ifndef set_errno +#define set_errno(err) do { if (err) { errno = (err); } } while(0) +#endif + +#if !LWIP_TCPIP_CORE_LOCKING +/** Maximum optlen used by setsockopt/getsockopt */ +#define LWIP_SETGETSOCKOPT_MAXOPTLEN LWIP_MAX(16, sizeof(struct ifreq)) + +/** This struct is used to pass data to the set/getsockopt_internal + * functions running in tcpip_thread context (only a void* is allowed) */ +struct lwip_setgetsockopt_data { + /** socket index for which to change options */ + int s; + /** level of the option to process */ + int level; + /** name of the option to process */ + int optname; + /** set: value to set the option to + * get: value of the option is stored here */ +#if LWIP_MPU_COMPATIBLE + u8_t optval[LWIP_SETGETSOCKOPT_MAXOPTLEN]; +#else + union { + void *p; + const void *pc; + } optval; +#endif + /** size of *optval */ + socklen_t optlen; + /** if an error occurs, it is temporarily stored here */ + int err; + /** semaphore to wake up the calling task */ + void* completed_sem; +}; +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + +#ifdef __cplusplus +} +#endif + +struct lwip_sock* lwip_socket_dbg_get_socket(int fd); + +#if LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL + +#if LWIP_NETCONN_SEM_PER_THREAD +#define SELECT_SEM_T sys_sem_t* +#define SELECT_SEM_PTR(sem) (sem) +#else /* LWIP_NETCONN_SEM_PER_THREAD */ +#define SELECT_SEM_T sys_sem_t +#define SELECT_SEM_PTR(sem) (&(sem)) +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + +/** Description for a task waiting in select */ +struct lwip_select_cb { + /** Pointer to the next waiting task */ + struct lwip_select_cb *next; + /** Pointer to the previous waiting task */ + struct lwip_select_cb *prev; +#if LWIP_SOCKET_SELECT + /** readset passed to select */ + fd_set *readset; + /** writeset passed to select */ + fd_set *writeset; + /** unimplemented: exceptset passed to select */ + fd_set *exceptset; +#endif /* LWIP_SOCKET_SELECT */ +#if LWIP_SOCKET_POLL + /** fds passed to poll; NULL if select */ + struct pollfd *poll_fds; + /** nfds passed to poll; 0 if select */ + nfds_t poll_nfds; +#endif /* LWIP_SOCKET_POLL */ + /** don't signal the same semaphore twice: set to 1 when signalled */ + int sem_signalled; + /** semaphore to wake up a task waiting for select */ + SELECT_SEM_T sem; +}; +#endif /* LWIP_SOCKET_SELECT || LWIP_SOCKET_POLL */ + +#endif /* LWIP_SOCKET */ + +#endif /* LWIP_HDR_SOCKETS_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h new file mode 100644 index 0000000..72f9126 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcp_priv.h @@ -0,0 +1,523 @@ +/** + * @file + * TCP internal implementations (do not use in application code) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_TCP_PRIV_H +#define LWIP_HDR_TCP_PRIV_H + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcp.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" +#include "lwip/prot/tcp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Functions for interfacing with TCP: */ + +/* Lower layer interface to TCP: */ +void tcp_init (void); /* Initialize this module. */ +void tcp_tmr (void); /* Must be called every + TCP_TMR_INTERVAL + ms. (Typically 250 ms). */ +/* It is also possible to call these two functions at the right + intervals (instead of calling tcp_tmr()). */ +void tcp_slowtmr (void); +void tcp_fasttmr (void); + +/* Call this from a netif driver (watch out for threading issues!) that has + returned a memory error on transmit and now has free buffers to send more. + This iterates all active pcbs that had an error and tries to call + tcp_output, so use this with care as it might slow down the system. */ +void tcp_txnow (void); + +/* Only used by IP to pass a TCP segment to TCP: */ +void tcp_input (struct pbuf *p, struct netif *inp); +/* Used within the TCP code only: */ +struct tcp_pcb * tcp_alloc (u8_t prio); +void tcp_free (struct tcp_pcb *pcb); +void tcp_abandon (struct tcp_pcb *pcb, int reset); +err_t tcp_send_empty_ack(struct tcp_pcb *pcb); +err_t tcp_rexmit (struct tcp_pcb *pcb); +err_t tcp_rexmit_rto_prepare(struct tcp_pcb *pcb); +void tcp_rexmit_rto_commit(struct tcp_pcb *pcb); +void tcp_rexmit_rto (struct tcp_pcb *pcb); +void tcp_rexmit_fast (struct tcp_pcb *pcb); +u32_t tcp_update_rcv_ann_wnd(struct tcp_pcb *pcb); +err_t tcp_process_refused_data(struct tcp_pcb *pcb); + +/** + * This is the Nagle algorithm: try to combine user data to send as few TCP + * segments as possible. Only send if + * - no previously transmitted data on the connection remains unacknowledged or + * - the TF_NODELAY flag is set (nagle algorithm turned off for this pcb) or + * - the only unsent segment is at least pcb->mss bytes long (or there is more + * than one unsent segment - with lwIP, this can happen although unsent->len < mss) + * - or if we are in fast-retransmit (TF_INFR) + */ +#define tcp_do_output_nagle(tpcb) ((((tpcb)->unacked == NULL) || \ + ((tpcb)->flags & (TF_NODELAY | TF_INFR)) || \ + (((tpcb)->unsent != NULL) && (((tpcb)->unsent->next != NULL) || \ + ((tpcb)->unsent->len >= (tpcb)->mss))) || \ + ((tcp_sndbuf(tpcb) == 0) || (tcp_sndqueuelen(tpcb) >= TCP_SND_QUEUELEN)) \ + ) ? 1 : 0) +#define tcp_output_nagle(tpcb) (tcp_do_output_nagle(tpcb) ? tcp_output(tpcb) : ERR_OK) + + +#define TCP_SEQ_LT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) < 0) +#define TCP_SEQ_LEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) <= 0) +#define TCP_SEQ_GT(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) > 0) +#define TCP_SEQ_GEQ(a,b) ((s32_t)((u32_t)(a) - (u32_t)(b)) >= 0) +/* is b<=a<=c? */ +#if 0 /* see bug #10548 */ +#define TCP_SEQ_BETWEEN(a,b,c) ((c)-(b) >= (a)-(b)) +#endif +#define TCP_SEQ_BETWEEN(a,b,c) (TCP_SEQ_GEQ(a,b) && TCP_SEQ_LEQ(a,c)) + +#ifndef TCP_TMR_INTERVAL +#define TCP_TMR_INTERVAL 250 /* The TCP timer interval in milliseconds. */ +#endif /* TCP_TMR_INTERVAL */ + +#ifndef TCP_FAST_INTERVAL +#define TCP_FAST_INTERVAL TCP_TMR_INTERVAL /* the fine grained timeout in milliseconds */ +#endif /* TCP_FAST_INTERVAL */ + +#ifndef TCP_SLOW_INTERVAL +#define TCP_SLOW_INTERVAL (2*TCP_TMR_INTERVAL) /* the coarse grained timeout in milliseconds */ +#endif /* TCP_SLOW_INTERVAL */ + +#define TCP_FIN_WAIT_TIMEOUT 20000 /* milliseconds */ +#define TCP_SYN_RCVD_TIMEOUT 20000 /* milliseconds */ + +#define TCP_OOSEQ_TIMEOUT 6U /* x RTO */ + +#ifndef TCP_MSL +#define TCP_MSL 60000UL /* The maximum segment lifetime in milliseconds */ +#endif + +/* Keepalive values, compliant with RFC 1122. Don't change this unless you know what you're doing */ +#ifndef TCP_KEEPIDLE_DEFAULT +#define TCP_KEEPIDLE_DEFAULT 7200000UL /* Default KEEPALIVE timer in milliseconds */ +#endif + +#ifndef TCP_KEEPINTVL_DEFAULT +#define TCP_KEEPINTVL_DEFAULT 75000UL /* Default Time between KEEPALIVE probes in milliseconds */ +#endif + +#ifndef TCP_KEEPCNT_DEFAULT +#define TCP_KEEPCNT_DEFAULT 9U /* Default Counter for KEEPALIVE probes */ +#endif + +#define TCP_MAXIDLE TCP_KEEPCNT_DEFAULT * TCP_KEEPINTVL_DEFAULT /* Maximum KEEPALIVE probe time */ + +#define TCP_TCPLEN(seg) ((seg)->len + (((TCPH_FLAGS((seg)->tcphdr) & (TCP_FIN | TCP_SYN)) != 0) ? 1U : 0U)) + +/** Flags used on input processing, not on pcb->flags +*/ +#define TF_RESET (u8_t)0x08U /* Connection was reset. */ +#define TF_CLOSED (u8_t)0x10U /* Connection was successfully closed. */ +#define TF_GOT_FIN (u8_t)0x20U /* Connection was closed by the remote end. */ + + +#if LWIP_EVENT_API + +#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) ret = lwip_tcp_event(arg, (pcb),\ + LWIP_EVENT_ACCEPT, NULL, 0, err) +#define TCP_EVENT_SENT(pcb,space,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_SENT, NULL, space, ERR_OK) +#define TCP_EVENT_RECV(pcb,p,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, (p), 0, (err)) +#define TCP_EVENT_CLOSED(pcb,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_RECV, NULL, 0, ERR_OK) +#define TCP_EVENT_CONNECTED(pcb,err,ret) ret = lwip_tcp_event((pcb)->callback_arg, (pcb),\ + LWIP_EVENT_CONNECTED, NULL, 0, (err)) +#define TCP_EVENT_POLL(pcb,ret) do { if ((pcb)->state != SYN_RCVD) { \ + ret = lwip_tcp_event((pcb)->callback_arg, (pcb), LWIP_EVENT_POLL, NULL, 0, ERR_OK); \ + } else { \ + ret = ERR_ARG; } } while(0) +/* For event API, last state SYN_RCVD must be excluded here: the application + has not seen this pcb, yet! */ +#define TCP_EVENT_ERR(last_state,errf,arg,err) do { if (last_state != SYN_RCVD) { \ + lwip_tcp_event((arg), NULL, LWIP_EVENT_ERR, NULL, 0, (err)); } } while(0) + +#else /* LWIP_EVENT_API */ + +#define TCP_EVENT_ACCEPT(lpcb,pcb,arg,err,ret) \ + do { \ + if((lpcb)->accept != NULL) \ + (ret) = (lpcb)->accept((arg),(pcb),(err)); \ + else (ret) = ERR_ARG; \ + } while (0) + +#define TCP_EVENT_SENT(pcb,space,ret) \ + do { \ + if((pcb)->sent != NULL) \ + (ret) = (pcb)->sent((pcb)->callback_arg,(pcb),(space)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_RECV(pcb,p,err,ret) \ + do { \ + if((pcb)->recv != NULL) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),(p),(err));\ + } else { \ + (ret) = tcp_recv_null(NULL, (pcb), (p), (err)); \ + } \ + } while (0) + +#define TCP_EVENT_CLOSED(pcb,ret) \ + do { \ + if(((pcb)->recv != NULL)) { \ + (ret) = (pcb)->recv((pcb)->callback_arg,(pcb),NULL,ERR_OK);\ + } else { \ + (ret) = ERR_OK; \ + } \ + } while (0) + +#define TCP_EVENT_CONNECTED(pcb,err,ret) \ + do { \ + if((pcb)->connected != NULL) \ + (ret) = (pcb)->connected((pcb)->callback_arg,(pcb),(err)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_POLL(pcb,ret) \ + do { \ + if((pcb)->poll != NULL) \ + (ret) = (pcb)->poll((pcb)->callback_arg,(pcb)); \ + else (ret) = ERR_OK; \ + } while (0) + +#define TCP_EVENT_ERR(last_state,errf,arg,err) \ + do { \ + LWIP_UNUSED_ARG(last_state); \ + if((errf) != NULL) \ + (errf)((arg),(err)); \ + } while (0) + +#endif /* LWIP_EVENT_API */ + +/** Enabled extra-check for TCP_OVERSIZE if LWIP_DEBUG is enabled */ +#if TCP_OVERSIZE && defined(LWIP_DEBUG) +#define TCP_OVERSIZE_DBGCHECK 1 +#else +#define TCP_OVERSIZE_DBGCHECK 0 +#endif + +/** Don't generate checksum on copy if CHECKSUM_GEN_TCP is disabled */ +#define TCP_CHECKSUM_ON_COPY (LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_TCP) + +/* This structure represents a TCP segment on the unsent, unacked and ooseq queues */ +struct tcp_seg { + struct tcp_seg *next; /* used when putting segments on a queue */ + struct pbuf *p; /* buffer containing data + TCP header */ + u16_t len; /* the TCP length of this segment */ +#if TCP_OVERSIZE_DBGCHECK + u16_t oversize_left; /* Extra bytes available at the end of the last + pbuf in unsent (used for asserting vs. + tcp_pcb.unsent_oversize only) */ +#endif /* TCP_OVERSIZE_DBGCHECK */ +#if TCP_CHECKSUM_ON_COPY + u16_t chksum; + u8_t chksum_swapped; +#endif /* TCP_CHECKSUM_ON_COPY */ + u8_t flags; +#define TF_SEG_OPTS_MSS (u8_t)0x01U /* Include MSS option (only used in SYN segments) */ +#define TF_SEG_OPTS_TS (u8_t)0x02U /* Include timestamp option. */ +#define TF_SEG_DATA_CHECKSUMMED (u8_t)0x04U /* ALL data (not the header) is + checksummed into 'chksum' */ +#define TF_SEG_OPTS_WND_SCALE (u8_t)0x08U /* Include WND SCALE option (only used in SYN segments) */ +#define TF_SEG_OPTS_SACK_PERM (u8_t)0x10U /* Include SACK Permitted option (only used in SYN segments) */ + struct tcp_hdr *tcphdr; /* the TCP header */ +}; + +#define LWIP_TCP_OPT_EOL 0 +#define LWIP_TCP_OPT_NOP 1 +#define LWIP_TCP_OPT_MSS 2 +#define LWIP_TCP_OPT_WS 3 +#define LWIP_TCP_OPT_SACK_PERM 4 +#define LWIP_TCP_OPT_TS 8 + +#define LWIP_TCP_OPT_LEN_MSS 4 +#if LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_OPT_LEN_TS 10 +#define LWIP_TCP_OPT_LEN_TS_OUT 12 /* aligned for output (includes NOP padding) */ +#else +#define LWIP_TCP_OPT_LEN_TS_OUT 0 +#endif +#if LWIP_WND_SCALE +#define LWIP_TCP_OPT_LEN_WS 3 +#define LWIP_TCP_OPT_LEN_WS_OUT 4 /* aligned for output (includes NOP padding) */ +#else +#define LWIP_TCP_OPT_LEN_WS_OUT 0 +#endif + +#if LWIP_TCP_SACK_OUT +#define LWIP_TCP_OPT_LEN_SACK_PERM 2 +#define LWIP_TCP_OPT_LEN_SACK_PERM_OUT 4 /* aligned for output (includes NOP padding) */ +#else +#define LWIP_TCP_OPT_LEN_SACK_PERM_OUT 0 +#endif + +#define LWIP_TCP_OPT_LENGTH(flags) \ + ((flags) & TF_SEG_OPTS_MSS ? LWIP_TCP_OPT_LEN_MSS : 0) + \ + ((flags) & TF_SEG_OPTS_TS ? LWIP_TCP_OPT_LEN_TS_OUT : 0) + \ + ((flags) & TF_SEG_OPTS_WND_SCALE ? LWIP_TCP_OPT_LEN_WS_OUT : 0) + \ + ((flags) & TF_SEG_OPTS_SACK_PERM ? LWIP_TCP_OPT_LEN_SACK_PERM_OUT : 0) + +/** This returns a TCP header option for MSS in an u32_t */ +#define TCP_BUILD_MSS_OPTION(mss) lwip_htonl(0x02040000 | ((mss) & 0xFFFF)) + +#if LWIP_WND_SCALE +#define TCPWNDSIZE_F U32_F +#define TCPWND_MAX 0xFFFFFFFFU +#define TCPWND_CHECK16(x) LWIP_ASSERT("window size > 0xFFFF", (x) <= 0xFFFF) +#define TCPWND_MIN16(x) ((u16_t)LWIP_MIN((x), 0xFFFF)) +#else /* LWIP_WND_SCALE */ +#define TCPWNDSIZE_F U16_F +#define TCPWND_MAX 0xFFFFU +#define TCPWND_CHECK16(x) +#define TCPWND_MIN16(x) x +#endif /* LWIP_WND_SCALE */ + +/* Global variables: */ +extern struct tcp_pcb *tcp_input_pcb; +extern u32_t tcp_ticks; +extern u8_t tcp_active_pcbs_changed; + +/* The TCP PCB lists. */ +union tcp_listen_pcbs_t { /* List of all TCP PCBs in LISTEN state. */ + struct tcp_pcb_listen *listen_pcbs; + struct tcp_pcb *pcbs; +}; +extern struct tcp_pcb *tcp_bound_pcbs; +extern union tcp_listen_pcbs_t tcp_listen_pcbs; +extern struct tcp_pcb *tcp_active_pcbs; /* List of all TCP PCBs that are in a + state in which they accept or send + data. */ +extern struct tcp_pcb *tcp_tw_pcbs; /* List of all TCP PCBs in TIME-WAIT. */ + +#define NUM_TCP_PCB_LISTS_NO_TIME_WAIT 3 +#define NUM_TCP_PCB_LISTS 4 +extern struct tcp_pcb ** const tcp_pcb_lists[NUM_TCP_PCB_LISTS]; + +/* Axioms about the above lists: + 1) Every TCP PCB that is not CLOSED is in one of the lists. + 2) A PCB is only in one of the lists. + 3) All PCBs in the tcp_listen_pcbs list is in LISTEN state. + 4) All PCBs in the tcp_tw_pcbs list is in TIME-WAIT state. +*/ +/* Define two macros, TCP_REG and TCP_RMV that registers a TCP PCB + with a PCB list or removes a PCB from a list, respectively. */ +#ifndef TCP_DEBUG_PCB_LISTS +#define TCP_DEBUG_PCB_LISTS 0 +#endif +#if TCP_DEBUG_PCB_LISTS +#define TCP_REG(pcbs, npcb) do {\ + struct tcp_pcb *tcp_tmp_pcb; \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_REG %p local port %"U16_F"\n", (void *)(npcb), (npcb)->local_port)); \ + for (tcp_tmp_pcb = *(pcbs); \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + LWIP_ASSERT("TCP_REG: already registered\n", tcp_tmp_pcb != (npcb)); \ + } \ + LWIP_ASSERT("TCP_REG: pcb->state != CLOSED", ((pcbs) == &tcp_bound_pcbs) || ((npcb)->state != CLOSED)); \ + (npcb)->next = *(pcbs); \ + LWIP_ASSERT("TCP_REG: npcb->next != npcb", (npcb)->next != (npcb)); \ + *(pcbs) = (npcb); \ + LWIP_ASSERT("TCP_REG: tcp_pcbs sane", tcp_pcbs_sane()); \ + tcp_timer_needed(); \ + } while(0) +#define TCP_RMV(pcbs, npcb) do { \ + struct tcp_pcb *tcp_tmp_pcb; \ + LWIP_ASSERT("TCP_RMV: pcbs != NULL", *(pcbs) != NULL); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removing %p from %p\n", (void *)(npcb), (void *)(*(pcbs)))); \ + if(*(pcbs) == (npcb)) { \ + *(pcbs) = (*pcbs)->next; \ + } else for (tcp_tmp_pcb = *(pcbs); tcp_tmp_pcb != NULL; tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == (npcb)) { \ + tcp_tmp_pcb->next = (npcb)->next; \ + break; \ + } \ + } \ + (npcb)->next = NULL; \ + LWIP_ASSERT("TCP_RMV: tcp_pcbs sane", tcp_pcbs_sane()); \ + LWIP_DEBUGF(TCP_DEBUG, ("TCP_RMV: removed %p from %p\n", (void *)(npcb), (void *)(*(pcbs)))); \ + } while(0) + +#else /* LWIP_DEBUG */ + +#define TCP_REG(pcbs, npcb) \ + do { \ + (npcb)->next = *pcbs; \ + *(pcbs) = (npcb); \ + tcp_timer_needed(); \ + } while (0) + +#define TCP_RMV(pcbs, npcb) \ + do { \ + if(*(pcbs) == (npcb)) { \ + (*(pcbs)) = (*pcbs)->next; \ + } \ + else { \ + struct tcp_pcb *tcp_tmp_pcb; \ + for (tcp_tmp_pcb = *pcbs; \ + tcp_tmp_pcb != NULL; \ + tcp_tmp_pcb = tcp_tmp_pcb->next) { \ + if(tcp_tmp_pcb->next == (npcb)) { \ + tcp_tmp_pcb->next = (npcb)->next; \ + break; \ + } \ + } \ + } \ + (npcb)->next = NULL; \ + } while(0) + +#endif /* LWIP_DEBUG */ + +#define TCP_REG_ACTIVE(npcb) \ + do { \ + TCP_REG(&tcp_active_pcbs, npcb); \ + tcp_active_pcbs_changed = 1; \ + } while (0) + +#define TCP_RMV_ACTIVE(npcb) \ + do { \ + TCP_RMV(&tcp_active_pcbs, npcb); \ + tcp_active_pcbs_changed = 1; \ + } while (0) + +#define TCP_PCB_REMOVE_ACTIVE(pcb) \ + do { \ + tcp_pcb_remove(&tcp_active_pcbs, pcb); \ + tcp_active_pcbs_changed = 1; \ + } while (0) + + +/* Internal functions: */ +struct tcp_pcb *tcp_pcb_copy(struct tcp_pcb *pcb); +void tcp_pcb_purge(struct tcp_pcb *pcb); +void tcp_pcb_remove(struct tcp_pcb **pcblist, struct tcp_pcb *pcb); + +void tcp_segs_free(struct tcp_seg *seg); +void tcp_seg_free(struct tcp_seg *seg); +struct tcp_seg *tcp_seg_copy(struct tcp_seg *seg); + +#define tcp_ack(pcb) \ + do { \ + if((pcb)->flags & TF_ACK_DELAY) { \ + tcp_clear_flags(pcb, TF_ACK_DELAY); \ + tcp_ack_now(pcb); \ + } \ + else { \ + tcp_set_flags(pcb, TF_ACK_DELAY); \ + } \ + } while (0) + +#define tcp_ack_now(pcb) \ + tcp_set_flags(pcb, TF_ACK_NOW) + +err_t tcp_send_fin(struct tcp_pcb *pcb); +err_t tcp_enqueue_flags(struct tcp_pcb *pcb, u8_t flags); + +void tcp_rexmit_seg(struct tcp_pcb *pcb, struct tcp_seg *seg); + +void tcp_rst(const struct tcp_pcb* pcb, u32_t seqno, u32_t ackno, + const ip_addr_t *local_ip, const ip_addr_t *remote_ip, + u16_t local_port, u16_t remote_port); + +u32_t tcp_next_iss(struct tcp_pcb *pcb); + +err_t tcp_keepalive(struct tcp_pcb *pcb); +err_t tcp_split_unsent_seg(struct tcp_pcb *pcb, u16_t split); +err_t tcp_zero_window_probe(struct tcp_pcb *pcb); +void tcp_trigger_input_pcb_close(void); + +#if TCP_CALCULATE_EFF_SEND_MSS +u16_t tcp_eff_send_mss_netif(u16_t sendmss, struct netif *outif, + const ip_addr_t *dest); +#define tcp_eff_send_mss(sendmss, src, dest) \ + tcp_eff_send_mss_netif(sendmss, ip_route(src, dest), dest) +#endif /* TCP_CALCULATE_EFF_SEND_MSS */ + +#if LWIP_CALLBACK_API +err_t tcp_recv_null(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err); +#endif /* LWIP_CALLBACK_API */ + +#if TCP_DEBUG || TCP_INPUT_DEBUG || TCP_OUTPUT_DEBUG +void tcp_debug_print(struct tcp_hdr *tcphdr); +void tcp_debug_print_flags(u8_t flags); +void tcp_debug_print_state(enum tcp_state s); +void tcp_debug_print_pcbs(void); +s16_t tcp_pcbs_sane(void); +#else +# define tcp_debug_print(tcphdr) +# define tcp_debug_print_flags(flags) +# define tcp_debug_print_state(s) +# define tcp_debug_print_pcbs() +# define tcp_pcbs_sane() 1 +#endif /* TCP_DEBUG */ + +/** External function (implemented in timers.c), called when TCP detects + * that a timer is needed (i.e. active- or time-wait-pcb found). */ +void tcp_timer_needed(void); + +void tcp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr); + +#if TCP_QUEUE_OOSEQ +void tcp_free_ooseq(struct tcp_pcb *pcb); +#endif + +#if LWIP_TCP_PCB_NUM_EXT_ARGS +err_t tcp_ext_arg_invoke_callbacks_passive_open(struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* LWIP_HDR_TCP_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h new file mode 100644 index 0000000..74be634 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/priv/tcpip_priv.h @@ -0,0 +1,170 @@ +/** + * @file + * TCPIP API internal implementations (do not use in application code) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_TCPIP_PRIV_H +#define LWIP_HDR_TCPIP_PRIV_H + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcpip.h" +#include "lwip/sys.h" +#include "lwip/timeouts.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct pbuf; +struct netif; + +#if LWIP_MPU_COMPATIBLE +#define API_VAR_REF(name) (*(name)) +#define API_VAR_DECLARE(type, name) type * name +#define API_VAR_ALLOC_EXT(type, pool, name, errorblock) do { \ + name = (type *)memp_malloc(pool); \ + if (name == NULL) { \ + errorblock; \ + } \ + } while(0) +#define API_VAR_ALLOC(type, pool, name, errorval) API_VAR_ALLOC_EXT(type, pool, name, return errorval) +#define API_VAR_ALLOC_POOL(type, pool, name, errorval) do { \ + name = (type *)LWIP_MEMPOOL_ALLOC(pool); \ + if (name == NULL) { \ + return errorval; \ + } \ + } while(0) +#define API_VAR_FREE(pool, name) memp_free(pool, name) +#define API_VAR_FREE_POOL(pool, name) LWIP_MEMPOOL_FREE(pool, name) +#define API_EXPR_REF(expr) (&(expr)) +#if LWIP_NETCONN_SEM_PER_THREAD +#define API_EXPR_REF_SEM(expr) (expr) +#else +#define API_EXPR_REF_SEM(expr) API_EXPR_REF(expr) +#endif +#define API_EXPR_DEREF(expr) expr +#define API_MSG_M_DEF(m) m +#define API_MSG_M_DEF_C(t, m) t m +#else /* LWIP_MPU_COMPATIBLE */ +#define API_VAR_REF(name) name +#define API_VAR_DECLARE(type, name) type name +#define API_VAR_ALLOC_EXT(type, pool, name, errorblock) +#define API_VAR_ALLOC(type, pool, name, errorval) +#define API_VAR_ALLOC_POOL(type, pool, name, errorval) +#define API_VAR_FREE(pool, name) +#define API_VAR_FREE_POOL(pool, name) +#define API_EXPR_REF(expr) expr +#define API_EXPR_REF_SEM(expr) API_EXPR_REF(expr) +#define API_EXPR_DEREF(expr) (*(expr)) +#define API_MSG_M_DEF(m) *m +#define API_MSG_M_DEF_C(t, m) const t * m +#endif /* LWIP_MPU_COMPATIBLE */ + +err_t tcpip_send_msg_wait_sem(tcpip_callback_fn fn, void *apimsg, sys_sem_t* sem); + +struct tcpip_api_call_data +{ +#if !LWIP_TCPIP_CORE_LOCKING + err_t err; +#if !LWIP_NETCONN_SEM_PER_THREAD + sys_sem_t sem; +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ +#else /* !LWIP_TCPIP_CORE_LOCKING */ + u8_t dummy; /* avoid empty struct :-( */ +#endif /* !LWIP_TCPIP_CORE_LOCKING */ +}; +typedef err_t (*tcpip_api_call_fn)(struct tcpip_api_call_data* call); +err_t tcpip_api_call(tcpip_api_call_fn fn, struct tcpip_api_call_data *call); + +enum tcpip_msg_type { +#if !LWIP_TCPIP_CORE_LOCKING + TCPIP_MSG_API, + TCPIP_MSG_API_CALL, +#endif /* !LWIP_TCPIP_CORE_LOCKING */ +#if !LWIP_TCPIP_CORE_LOCKING_INPUT + TCPIP_MSG_INPKT, +#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ +#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS + TCPIP_MSG_TIMEOUT, + TCPIP_MSG_UNTIMEOUT, +#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ + TCPIP_MSG_CALLBACK, + TCPIP_MSG_CALLBACK_STATIC +}; + +struct tcpip_msg { + enum tcpip_msg_type type; + union { +#if !LWIP_TCPIP_CORE_LOCKING + struct { + tcpip_callback_fn function; + void* msg; + } api_msg; + struct { + tcpip_api_call_fn function; + struct tcpip_api_call_data *arg; + sys_sem_t *sem; + } api_call; +#endif /* LWIP_TCPIP_CORE_LOCKING */ +#if !LWIP_TCPIP_CORE_LOCKING_INPUT + struct { + struct pbuf *p; + struct netif *netif; + netif_input_fn input_fn; + } inp; +#endif /* !LWIP_TCPIP_CORE_LOCKING_INPUT */ + struct { + tcpip_callback_fn function; + void *ctx; + } cb; +#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS + struct { + u32_t msecs; + sys_timeout_handler h; + void *arg; + } tmo; +#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ + } msg; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* !NO_SYS */ + +#endif /* LWIP_HDR_TCPIP_PRIV_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h new file mode 100644 index 0000000..fd3af8a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/autoip.h @@ -0,0 +1,78 @@ +/** + * @file + * AutoIP protocol definitions + */ + +/* + * + * Copyright (c) 2007 Dominik Spies + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Dominik Spies + * + * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform + * with RFC 3927. + * + */ + +#ifndef LWIP_HDR_PROT_AUTOIP_H +#define LWIP_HDR_PROT_AUTOIP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* 169.254.0.0 */ +#define AUTOIP_NET 0xA9FE0000 +/* 169.254.1.0 */ +#define AUTOIP_RANGE_START (AUTOIP_NET | 0x0100) +/* 169.254.254.255 */ +#define AUTOIP_RANGE_END (AUTOIP_NET | 0xFEFF) + +/* RFC 3927 Constants */ +#define PROBE_WAIT 1 /* second (initial random delay) */ +#define PROBE_MIN 1 /* second (minimum delay till repeated probe) */ +#define PROBE_MAX 2 /* seconds (maximum delay till repeated probe) */ +#define PROBE_NUM 3 /* (number of probe packets) */ +#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ +#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ +#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ +#define MAX_CONFLICTS 10 /* (max conflicts before rate limiting) */ +#define RATE_LIMIT_INTERVAL 60 /* seconds (delay between successive attempts) */ +#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ + +/* AutoIP client states */ +typedef enum { + AUTOIP_STATE_OFF = 0, + AUTOIP_STATE_PROBING = 1, + AUTOIP_STATE_ANNOUNCING = 2, + AUTOIP_STATE_BOUND = 3 +} autoip_state_enum_t; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_AUTOIP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h new file mode 100644 index 0000000..ab18dca --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp.h @@ -0,0 +1,178 @@ +/** + * @file + * DHCP protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Leon Woestenberg + * Copyright (c) 2001-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Leon Woestenberg + * + */ +#ifndef LWIP_HDR_PROT_DHCP_H +#define LWIP_HDR_PROT_DHCP_H + +#include "lwip/opt.h" +#include "lwip/arch.h" +#include "lwip/prot/ip4.h" + +#ifdef __cplusplus +extern "C" { +#endif + + /* DHCP message item offsets and length */ +#define DHCP_CHADDR_LEN 16U +#define DHCP_SNAME_OFS 44U +#define DHCP_SNAME_LEN 64U +#define DHCP_FILE_OFS 108U +#define DHCP_FILE_LEN 128U +#define DHCP_MSG_LEN 236U +#define DHCP_OPTIONS_OFS (DHCP_MSG_LEN + 4U) /* 4 byte: cookie */ + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCP message */ +struct dhcp_msg +{ + PACK_STRUCT_FLD_8(u8_t op); + PACK_STRUCT_FLD_8(u8_t htype); + PACK_STRUCT_FLD_8(u8_t hlen); + PACK_STRUCT_FLD_8(u8_t hops); + PACK_STRUCT_FIELD(u32_t xid); + PACK_STRUCT_FIELD(u16_t secs); + PACK_STRUCT_FIELD(u16_t flags); + PACK_STRUCT_FLD_S(ip4_addr_p_t ciaddr); + PACK_STRUCT_FLD_S(ip4_addr_p_t yiaddr); + PACK_STRUCT_FLD_S(ip4_addr_p_t siaddr); + PACK_STRUCT_FLD_S(ip4_addr_p_t giaddr); + PACK_STRUCT_FLD_8(u8_t chaddr[DHCP_CHADDR_LEN]); + PACK_STRUCT_FLD_8(u8_t sname[DHCP_SNAME_LEN]); + PACK_STRUCT_FLD_8(u8_t file[DHCP_FILE_LEN]); + PACK_STRUCT_FIELD(u32_t cookie); +#define DHCP_MIN_OPTIONS_LEN 68U +/** make sure user does not configure this too small */ +#if ((defined(DHCP_OPTIONS_LEN)) && (DHCP_OPTIONS_LEN < DHCP_MIN_OPTIONS_LEN)) +# undef DHCP_OPTIONS_LEN +#endif +/** allow this to be configured in lwipopts.h, but not too small */ +#if (!defined(DHCP_OPTIONS_LEN)) +/** set this to be sufficient for your options in outgoing DHCP msgs */ +# define DHCP_OPTIONS_LEN DHCP_MIN_OPTIONS_LEN +#endif + PACK_STRUCT_FLD_8(u8_t options[DHCP_OPTIONS_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + + +/* DHCP client states */ +typedef enum { + DHCP_STATE_OFF = 0, + DHCP_STATE_REQUESTING = 1, + DHCP_STATE_INIT = 2, + DHCP_STATE_REBOOTING = 3, + DHCP_STATE_REBINDING = 4, + DHCP_STATE_RENEWING = 5, + DHCP_STATE_SELECTING = 6, + DHCP_STATE_INFORMING = 7, + DHCP_STATE_CHECKING = 8, + DHCP_STATE_PERMANENT = 9, /* not yet implemented */ + DHCP_STATE_BOUND = 10, + DHCP_STATE_RELEASING = 11, /* not yet implemented */ + DHCP_STATE_BACKING_OFF = 12 +} dhcp_state_enum_t; + +/* DHCP op codes */ +#define DHCP_BOOTREQUEST 1 +#define DHCP_BOOTREPLY 2 + +/* DHCP message types */ +#define DHCP_DISCOVER 1 +#define DHCP_OFFER 2 +#define DHCP_REQUEST 3 +#define DHCP_DECLINE 4 +#define DHCP_ACK 5 +#define DHCP_NAK 6 +#define DHCP_RELEASE 7 +#define DHCP_INFORM 8 + +#define DHCP_MAGIC_COOKIE 0x63825363UL + +/* This is a list of options for BOOTP and DHCP, see RFC 2132 for descriptions */ + +/* BootP options */ +#define DHCP_OPTION_PAD 0 +#define DHCP_OPTION_SUBNET_MASK 1 /* RFC 2132 3.3 */ +#define DHCP_OPTION_ROUTER 3 +#define DHCP_OPTION_DNS_SERVER 6 +#define DHCP_OPTION_HOSTNAME 12 +#define DHCP_OPTION_IP_TTL 23 +#define DHCP_OPTION_MTU 26 +#define DHCP_OPTION_BROADCAST 28 +#define DHCP_OPTION_TCP_TTL 37 +#define DHCP_OPTION_NTP 42 +#define DHCP_OPTION_END 255 + +/* DHCP options */ +#define DHCP_OPTION_REQUESTED_IP 50 /* RFC 2132 9.1, requested IP address */ +#define DHCP_OPTION_LEASE_TIME 51 /* RFC 2132 9.2, time in seconds, in 4 bytes */ +#define DHCP_OPTION_OVERLOAD 52 /* RFC2132 9.3, use file and/or sname field for options */ + +#define DHCP_OPTION_MESSAGE_TYPE 53 /* RFC 2132 9.6, important for DHCP */ +#define DHCP_OPTION_MESSAGE_TYPE_LEN 1 + +#define DHCP_OPTION_SERVER_ID 54 /* RFC 2132 9.7, server IP address */ +#define DHCP_OPTION_PARAMETER_REQUEST_LIST 55 /* RFC 2132 9.8, requested option types */ + +#define DHCP_OPTION_MAX_MSG_SIZE 57 /* RFC 2132 9.10, message size accepted >= 576 */ +#define DHCP_OPTION_MAX_MSG_SIZE_LEN 2 + +#define DHCP_OPTION_T1 58 /* T1 renewal time */ +#define DHCP_OPTION_T2 59 /* T2 rebinding time */ +#define DHCP_OPTION_US 60 +#define DHCP_OPTION_CLIENT_ID 61 +#define DHCP_OPTION_TFTP_SERVERNAME 66 +#define DHCP_OPTION_BOOTFILE 67 + +/* possible combinations of overloading the file and sname fields with options */ +#define DHCP_OVERLOAD_NONE 0 +#define DHCP_OVERLOAD_FILE 1 +#define DHCP_OVERLOAD_SNAME 2 +#define DHCP_OVERLOAD_SNAME_FILE 3 + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_DHCP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h new file mode 100644 index 0000000..0754c91 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dhcp6.h @@ -0,0 +1,138 @@ +/** + * @file + * DHCPv6 protocol definitions + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_PROT_DHCP6_H +#define LWIP_HDR_PROT_DHCP6_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DHCP6_CLIENT_PORT 546 +#define DHCP6_SERVER_PORT 547 + + + /* DHCPv6 message item offsets and length */ +#define DHCP6_TRANSACTION_ID_LEN 3 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** minimum set of fields of any DHCPv6 message */ +struct dhcp6_msg +{ + PACK_STRUCT_FLD_8(u8_t msgtype); + PACK_STRUCT_FLD_8(u8_t transaction_id[DHCP6_TRANSACTION_ID_LEN]); + /* options follow */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + + +/* DHCP6 client states */ +typedef enum { + DHCP6_STATE_OFF = 0, + DHCP6_STATE_STATELESS_IDLE = 1, + DHCP6_STATE_REQUESTING_CONFIG = 2 +} dhcp6_state_enum_t; + +/* DHCPv6 message types */ +#define DHCP6_SOLICIT 1 +#define DHCP6_ADVERTISE 2 +#define DHCP6_REQUEST 3 +#define DHCP6_CONFIRM 4 +#define DHCP6_RENEW 5 +#define DHCP6_REBIND 6 +#define DHCP6_REPLY 7 +#define DHCP6_RELEASE 8 +#define DHCP6_DECLINE 9 +#define DHCP6_RECONFIGURE 10 +#define DHCP6_INFOREQUEST 11 +#define DHCP6_RELAYFORW 12 +#define DHCP6_RELAYREPL 13 +/* More message types see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */ + +/** DHCPv6 status codes */ +#define DHCP6_STATUS_SUCCESS 0 /* Success. */ +#define DHCP6_STATUS_UNSPECFAIL 1 /* Failure, reason unspecified; this status code is sent by either a client or a server to indicate a failure not explicitly specified in this document. */ +#define DHCP6_STATUS_NOADDRSAVAIL 2 /* Server has no addresses available to assign to the IA(s). */ +#define DHCP6_STATUS_NOBINDING 3 /* Client record (binding) unavailable. */ +#define DHCP6_STATUS_NOTONLINK 4 /* The prefix for the address is not appropriate for the link to which the client is attached. */ +#define DHCP6_STATUS_USEMULTICAST 5 /* Sent by a server to a client to force the client to send messages to the server using the All_DHCP_Relay_Agents_and_Servers address. */ +/* More status codes see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */ + +/** DHCPv6 DUID types */ +#define DHCP6_DUID_LLT 1 /* LLT: Link-layer Address Plus Time */ +#define DHCP6_DUID_EN 2 /* EN: Enterprise number */ +#define DHCP6_DUID_LL 3 /* LL: Link-layer Address */ +#define DHCP6_DUID_UUID 4 /* UUID (RFC 6355) */ + +/* DHCPv6 options */ +#define DHCP6_OPTION_CLIENTID 1 +#define DHCP6_OPTION_SERVERID 2 +#define DHCP6_OPTION_IA_NA 3 +#define DHCP6_OPTION_IA_TA 4 +#define DHCP6_OPTION_IAADDR 5 +#define DHCP6_OPTION_ORO 6 +#define DHCP6_OPTION_PREFERENCE 7 +#define DHCP6_OPTION_ELAPSED_TIME 8 +#define DHCP6_OPTION_RELAY_MSG 9 +#define DHCP6_OPTION_AUTH 11 +#define DHCP6_OPTION_UNICAST 12 +#define DHCP6_OPTION_STATUS_CODE 13 +#define DHCP6_OPTION_RAPID_COMMIT 14 +#define DHCP6_OPTION_USER_CLASS 15 +#define DHCP6_OPTION_VENDOR_CLASS 16 +#define DHCP6_OPTION_VENDOR_OPTS 17 +#define DHCP6_OPTION_INTERFACE_ID 18 +#define DHCP6_OPTION_RECONF_MSG 19 +#define DHCP6_OPTION_RECONF_ACCEPT 20 +/* More options see https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml */ +#define DHCP6_OPTION_DNS_SERVERS 23 /* RFC 3646 */ +#define DHCP6_OPTION_DOMAIN_LIST 24 /* RFC 3646 */ +#define DHCP6_OPTION_SNTP_SERVERS 31 /* RFC 4075 */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_DHCP6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h new file mode 100644 index 0000000..94782d6 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/dns.h @@ -0,0 +1,140 @@ +/** + * @file + * DNS - host name to IP address resolver. + */ + +/* + * Port to lwIP from uIP + * by Jim Pettinato April 2007 + * + * security fixes and more by Simon Goldschmidt + * + * uIP version Copyright (c) 2002-2003, Adam Dunkels. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LWIP_HDR_PROT_DNS_H +#define LWIP_HDR_PROT_DNS_H + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** DNS server port address */ +#ifndef DNS_SERVER_PORT +#define DNS_SERVER_PORT 53 +#endif + +/* DNS field TYPE used for "Resource Records" */ +#define DNS_RRTYPE_A 1 /* a host address */ +#define DNS_RRTYPE_NS 2 /* an authoritative name server */ +#define DNS_RRTYPE_MD 3 /* a mail destination (Obsolete - use MX) */ +#define DNS_RRTYPE_MF 4 /* a mail forwarder (Obsolete - use MX) */ +#define DNS_RRTYPE_CNAME 5 /* the canonical name for an alias */ +#define DNS_RRTYPE_SOA 6 /* marks the start of a zone of authority */ +#define DNS_RRTYPE_MB 7 /* a mailbox domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_MG 8 /* a mail group member (EXPERIMENTAL) */ +#define DNS_RRTYPE_MR 9 /* a mail rename domain name (EXPERIMENTAL) */ +#define DNS_RRTYPE_NULL 10 /* a null RR (EXPERIMENTAL) */ +#define DNS_RRTYPE_WKS 11 /* a well known service description */ +#define DNS_RRTYPE_PTR 12 /* a domain name pointer */ +#define DNS_RRTYPE_HINFO 13 /* host information */ +#define DNS_RRTYPE_MINFO 14 /* mailbox or mail list information */ +#define DNS_RRTYPE_MX 15 /* mail exchange */ +#define DNS_RRTYPE_TXT 16 /* text strings */ +#define DNS_RRTYPE_AAAA 28 /* IPv6 address */ +#define DNS_RRTYPE_SRV 33 /* service location */ +#define DNS_RRTYPE_ANY 255 /* any type */ + +/* DNS field CLASS used for "Resource Records" */ +#define DNS_RRCLASS_IN 1 /* the Internet */ +#define DNS_RRCLASS_CS 2 /* the CSNET class (Obsolete - used only for examples in some obsolete RFCs) */ +#define DNS_RRCLASS_CH 3 /* the CHAOS class */ +#define DNS_RRCLASS_HS 4 /* Hesiod [Dyer 87] */ +#define DNS_RRCLASS_ANY 255 /* any class */ +#define DNS_RRCLASS_FLUSH 0x800 /* Flush bit */ + +/* DNS protocol flags */ +#define DNS_FLAG1_RESPONSE 0x80 +#define DNS_FLAG1_OPCODE_STATUS 0x10 +#define DNS_FLAG1_OPCODE_INVERSE 0x08 +#define DNS_FLAG1_OPCODE_STANDARD 0x00 +#define DNS_FLAG1_AUTHORATIVE 0x04 +#define DNS_FLAG1_TRUNC 0x02 +#define DNS_FLAG1_RD 0x01 +#define DNS_FLAG2_RA 0x80 +#define DNS_FLAG2_ERR_MASK 0x0f +#define DNS_FLAG2_ERR_NONE 0x00 +#define DNS_FLAG2_ERR_NAME 0x03 + +#define DNS_HDR_GET_OPCODE(hdr) ((((hdr)->flags1) >> 3) & 0xF) + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** DNS message header */ +struct dns_hdr { + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FLD_8(u8_t flags1); + PACK_STRUCT_FLD_8(u8_t flags2); + PACK_STRUCT_FIELD(u16_t numquestions); + PACK_STRUCT_FIELD(u16_t numanswers); + PACK_STRUCT_FIELD(u16_t numauthrr); + PACK_STRUCT_FIELD(u16_t numextrarr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define SIZEOF_DNS_HDR 12 + + +/* Multicast DNS definitions */ + +/** UDP port for multicast DNS queries */ +#ifndef DNS_MQUERY_PORT +#define DNS_MQUERY_PORT 5353 +#endif + +/* IPv4 group for multicast DNS queries: 224.0.0.251 */ +#ifndef DNS_MQUERY_IPV4_GROUP_INIT +#define DNS_MQUERY_IPV4_GROUP_INIT IPADDR4_INIT_BYTES(224,0,0,251) +#endif + +/* IPv6 group for multicast DNS queries: FF02::FB */ +#ifndef DNS_MQUERY_IPV6_GROUP_INIT +#define DNS_MQUERY_IPV6_GROUP_INIT IPADDR6_INIT_HOST(0xFF020000,0,0,0xFB) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_DNS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h new file mode 100644 index 0000000..811c228 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/etharp.h @@ -0,0 +1,114 @@ +/** + * @file + * ARP protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_ETHARP_H +#define LWIP_HDR_PROT_ETHARP_H + +#include "lwip/arch.h" +#include "lwip/prot/ethernet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ETHARP_HWADDR_LEN +#define ETHARP_HWADDR_LEN ETH_HWADDR_LEN +#endif + +/** + * struct ip4_addr_wordaligned is used in the definition of the ARP packet format in + * order to support compilers that don't have structure packing. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip4_addr_wordaligned { + PACK_STRUCT_FIELD(u16_t addrw[2]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** MEMCPY-like copying of IP addresses where addresses are known to be + * 16-bit-aligned if the port is correctly configured (so a port could define + * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */ +#ifndef IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T +#define IPADDR_WORDALIGNED_COPY_TO_IP4_ADDR_T(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t)) +#endif + + /** MEMCPY-like copying of IP addresses where addresses are known to be + * 16-bit-aligned if the port is correctly configured (so a port could define + * this to copying 2 u16_t's) - no NULL-pointer-checking needed. */ +#ifndef IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T +#define IPADDR_WORDALIGNED_COPY_FROM_IP4_ADDR_T(dest, src) SMEMCPY(dest, src, sizeof(ip4_addr_t)) +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** the ARP message, see RFC 826 ("Packet format") */ +struct etharp_hdr { + PACK_STRUCT_FIELD(u16_t hwtype); + PACK_STRUCT_FIELD(u16_t proto); + PACK_STRUCT_FLD_8(u8_t hwlen); + PACK_STRUCT_FLD_8(u8_t protolen); + PACK_STRUCT_FIELD(u16_t opcode); + PACK_STRUCT_FLD_S(struct eth_addr shwaddr); + PACK_STRUCT_FLD_S(struct ip4_addr_wordaligned sipaddr); + PACK_STRUCT_FLD_S(struct eth_addr dhwaddr); + PACK_STRUCT_FLD_S(struct ip4_addr_wordaligned dipaddr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETHARP_HDR 28 + +/* ARP message types (opcodes) */ +enum etharp_opcode { + ARP_REQUEST = 1, + ARP_REPLY = 2 +}; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_ETHARP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h new file mode 100644 index 0000000..309e574 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ethernet.h @@ -0,0 +1,125 @@ +/** + * @file + * Ethernet protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_ETHERNET_H +#define LWIP_HDR_PROT_ETHERNET_H + +#include "lwip/arch.h" +#include "lwip/prot/ieee.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef ETH_HWADDR_LEN +#ifdef ETHARP_HWADDR_LEN +#define ETH_HWADDR_LEN ETHARP_HWADDR_LEN /* compatibility mode */ +#else +#define ETH_HWADDR_LEN 6 +#endif +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** An Ethernet MAC address */ +struct eth_addr { + PACK_STRUCT_FLD_8(u8_t addr[ETH_HWADDR_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Initialize a struct eth_addr with its 6 bytes (takes care of correct braces) */ +#define ETH_ADDR(b0, b1, b2, b3, b4, b5) {{b0, b1, b2, b3, b4, b5}} + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** Ethernet header */ +struct eth_hdr { +#if ETH_PAD_SIZE + PACK_STRUCT_FLD_8(u8_t padding[ETH_PAD_SIZE]); +#endif + PACK_STRUCT_FLD_S(struct eth_addr dest); + PACK_STRUCT_FLD_S(struct eth_addr src); + PACK_STRUCT_FIELD(u16_t type); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_ETH_HDR (14 + ETH_PAD_SIZE) + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** VLAN header inserted between ethernet header and payload + * if 'type' in ethernet header is ETHTYPE_VLAN. + * See IEEE802.Q */ +struct eth_vlan_hdr { + PACK_STRUCT_FIELD(u16_t prio_vid); + PACK_STRUCT_FIELD(u16_t tpid); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_VLAN_HDR 4 +#define VLAN_ID(vlan_hdr) (lwip_htons((vlan_hdr)->prio_vid) & 0xFFF) + +/** The 24-bit IANA IPv4-multicast OUI is 01-00-5e: */ +#define LL_IP4_MULTICAST_ADDR_0 0x01 +#define LL_IP4_MULTICAST_ADDR_1 0x00 +#define LL_IP4_MULTICAST_ADDR_2 0x5e + +/** IPv6 multicast uses this prefix */ +#define LL_IP6_MULTICAST_ADDR_0 0x33 +#define LL_IP6_MULTICAST_ADDR_1 0x33 + +#define eth_addr_cmp(addr1, addr2) (memcmp((addr1)->addr, (addr2)->addr, ETH_HWADDR_LEN) == 0) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_ETHERNET_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h new file mode 100644 index 0000000..32890cc --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/iana.h @@ -0,0 +1,97 @@ +/** + * @file + * IANA assigned numbers (RFC 1700 and successors) + * + * @defgroup iana IANA assigned numbers + * @ingroup infrastructure + */ + +/* + * Copyright (c) 2017 Dirk Ziegelmeier. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Dirk Ziegelmeier + * + */ + +#ifndef LWIP_HDR_PROT_IANA_H +#define LWIP_HDR_PROT_IANA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup iana + * Hardware types + */ +enum lwip_iana_hwtype { + /** Ethernet */ + LWIP_IANA_HWTYPE_ETHERNET = 1 +}; + +/** + * @ingroup iana + * Port numbers + * https://www.iana.org/assignments/service-names-port-numbers/service-names-port-numbers.txt + */ +enum lwip_iana_port_number { + /** SMTP */ + LWIP_IANA_PORT_SMTP = 25, + /** DHCP server */ + LWIP_IANA_PORT_DHCP_SERVER = 67, + /** DHCP client */ + LWIP_IANA_PORT_DHCP_CLIENT = 68, + /** TFTP */ + LWIP_IANA_PORT_TFTP = 69, + /** HTTP */ + LWIP_IANA_PORT_HTTP = 80, + /** SNTP */ + LWIP_IANA_PORT_SNTP = 123, + /** NETBIOS */ + LWIP_IANA_PORT_NETBIOS = 137, + /** SNMP */ + LWIP_IANA_PORT_SNMP = 161, + /** SNMP traps */ + LWIP_IANA_PORT_SNMP_TRAP = 162, + /** HTTPS */ + LWIP_IANA_PORT_HTTPS = 443, + /** SMTPS */ + LWIP_IANA_PORT_SMTPS = 465, + /** MQTT */ + LWIP_IANA_PORT_MQTT = 1883, + /** MDNS */ + LWIP_IANA_PORT_MDNS = 5353, + /** Secure MQTT */ + LWIP_IANA_PORT_SECURE_MQTT = 8883 +}; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_IANA_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h new file mode 100644 index 0000000..7d19385 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp.h @@ -0,0 +1,91 @@ +/** + * @file + * ICMP protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_ICMP_H +#define LWIP_HDR_PROT_ICMP_H + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ICMP_ER 0 /* echo reply */ +#define ICMP_DUR 3 /* destination unreachable */ +#define ICMP_SQ 4 /* source quench */ +#define ICMP_RD 5 /* redirect */ +#define ICMP_ECHO 8 /* echo */ +#define ICMP_TE 11 /* time exceeded */ +#define ICMP_PP 12 /* parameter problem */ +#define ICMP_TS 13 /* timestamp */ +#define ICMP_TSR 14 /* timestamp reply */ +#define ICMP_IRQ 15 /* information request */ +#define ICMP_IR 16 /* information reply */ +#define ICMP_AM 17 /* address mask request */ +#define ICMP_AMR 18 /* address mask reply */ + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +/** This is the standard ICMP header only that the u32_t data + * is split to two u16_t like ICMP echo needs it. + * This header is also used for other ICMP types that do not + * use the data part. + */ +PACK_STRUCT_BEGIN +struct icmp_echo_hdr { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* Compatibility defines, old versions used to combine type and code to an u16_t */ +#define ICMPH_TYPE(hdr) ((hdr)->type) +#define ICMPH_CODE(hdr) ((hdr)->code) +#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t)) +#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_ICMP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h new file mode 100644 index 0000000..3461120 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/icmp6.h @@ -0,0 +1,170 @@ +/** + * @file + * ICMP6 protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_ICMP6_H +#define LWIP_HDR_PROT_ICMP6_H + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** ICMP type */ +enum icmp6_type { + /** Destination unreachable */ + ICMP6_TYPE_DUR = 1, + /** Packet too big */ + ICMP6_TYPE_PTB = 2, + /** Time exceeded */ + ICMP6_TYPE_TE = 3, + /** Parameter problem */ + ICMP6_TYPE_PP = 4, + /** Private experimentation */ + ICMP6_TYPE_PE1 = 100, + /** Private experimentation */ + ICMP6_TYPE_PE2 = 101, + /** Reserved for expansion of error messages */ + ICMP6_TYPE_RSV_ERR = 127, + + /** Echo request */ + ICMP6_TYPE_EREQ = 128, + /** Echo reply */ + ICMP6_TYPE_EREP = 129, + /** Multicast listener query */ + ICMP6_TYPE_MLQ = 130, + /** Multicast listener report */ + ICMP6_TYPE_MLR = 131, + /** Multicast listener done */ + ICMP6_TYPE_MLD = 132, + /** Router solicitation */ + ICMP6_TYPE_RS = 133, + /** Router advertisement */ + ICMP6_TYPE_RA = 134, + /** Neighbor solicitation */ + ICMP6_TYPE_NS = 135, + /** Neighbor advertisement */ + ICMP6_TYPE_NA = 136, + /** Redirect */ + ICMP6_TYPE_RD = 137, + /** Multicast router advertisement */ + ICMP6_TYPE_MRA = 151, + /** Multicast router solicitation */ + ICMP6_TYPE_MRS = 152, + /** Multicast router termination */ + ICMP6_TYPE_MRT = 153, + /** Private experimentation */ + ICMP6_TYPE_PE3 = 200, + /** Private experimentation */ + ICMP6_TYPE_PE4 = 201, + /** Reserved for expansion of informational messages */ + ICMP6_TYPE_RSV_INF = 255 +}; + +/** ICMP destination unreachable codes */ +enum icmp6_dur_code { + /** No route to destination */ + ICMP6_DUR_NO_ROUTE = 0, + /** Communication with destination administratively prohibited */ + ICMP6_DUR_PROHIBITED = 1, + /** Beyond scope of source address */ + ICMP6_DUR_SCOPE = 2, + /** Address unreachable */ + ICMP6_DUR_ADDRESS = 3, + /** Port unreachable */ + ICMP6_DUR_PORT = 4, + /** Source address failed ingress/egress policy */ + ICMP6_DUR_POLICY = 5, + /** Reject route to destination */ + ICMP6_DUR_REJECT_ROUTE = 6 +}; + +/** ICMP time exceeded codes */ +enum icmp6_te_code { + /** Hop limit exceeded in transit */ + ICMP6_TE_HL = 0, + /** Fragment reassembly time exceeded */ + ICMP6_TE_FRAG = 1 +}; + +/** ICMP parameter code */ +enum icmp6_pp_code { + /** Erroneous header field encountered */ + ICMP6_PP_FIELD = 0, + /** Unrecognized next header type encountered */ + ICMP6_PP_HEADER = 1, + /** Unrecognized IPv6 option encountered */ + ICMP6_PP_OPTION = 2 +}; + +/** This is the standard ICMP6 header. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct icmp6_hdr { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t data); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** This is the ICMP6 header adapted for echo req/resp. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct icmp6_echo_hdr { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t id); + PACK_STRUCT_FIELD(u16_t seqno); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_ICMP6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h new file mode 100644 index 0000000..abbb9e3 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ieee.h @@ -0,0 +1,91 @@ +/** + * @file + * IEEE assigned numbers + * + * @defgroup ieee IEEE assigned numbers + * @ingroup infrastructure + */ + +/* + * Copyright (c) 2017 Dirk Ziegelmeier. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Dirk Ziegelmeier + * + */ + +#ifndef LWIP_HDR_PROT_IEEE_H +#define LWIP_HDR_PROT_IEEE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup ieee + * A list of often ethtypes (although lwIP does not use all of them). + */ +enum lwip_ieee_eth_type { + /** Internet protocol v4 */ + ETHTYPE_IP = 0x0800U, + /** Address resolution protocol */ + ETHTYPE_ARP = 0x0806U, + /** Wake on lan */ + ETHTYPE_WOL = 0x0842U, + /** RARP */ + ETHTYPE_RARP = 0x8035U, + /** Virtual local area network */ + ETHTYPE_VLAN = 0x8100U, + /** Internet protocol v6 */ + ETHTYPE_IPV6 = 0x86DDU, + /** PPP Over Ethernet Discovery Stage */ + ETHTYPE_PPPOEDISC = 0x8863U, + /** PPP Over Ethernet Session Stage */ + ETHTYPE_PPPOE = 0x8864U, + /** Jumbo Frames */ + ETHTYPE_JUMBO = 0x8870U, + /** Process field network */ + ETHTYPE_PROFINET = 0x8892U, + /** Ethernet for control automation technology */ + ETHTYPE_ETHERCAT = 0x88A4U, + /** Link layer discovery protocol */ + ETHTYPE_LLDP = 0x88CCU, + /** Serial real-time communication system */ + ETHTYPE_SERCOS = 0x88CDU, + /** Media redundancy protocol */ + ETHTYPE_MRP = 0x88E3U, + /** Precision time protocol */ + ETHTYPE_PTP = 0x88F7U, + /** Q-in-Q, 802.1ad */ + ETHTYPE_QINQ = 0x9100U +}; + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_IEEE_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h new file mode 100644 index 0000000..46b81a9 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/igmp.h @@ -0,0 +1,90 @@ +/** + * @file + * IGMP protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_IGMP_H +#define LWIP_HDR_PROT_IGMP_H + +#include "lwip/arch.h" +#include "lwip/prot/ip4.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IGMP constants + */ +#define IGMP_TTL 1 +#define IGMP_MINLEN 8 +#define ROUTER_ALERT 0x9404U +#define ROUTER_ALERTLEN 4 + +/* + * IGMP message types, including version number. + */ +#define IGMP_MEMB_QUERY 0x11 /* Membership query */ +#define IGMP_V1_MEMB_REPORT 0x12 /* Ver. 1 membership report */ +#define IGMP_V2_MEMB_REPORT 0x16 /* Ver. 2 membership report */ +#define IGMP_LEAVE_GROUP 0x17 /* Leave-group message */ + +/* Group membership states */ +#define IGMP_GROUP_NON_MEMBER 0 +#define IGMP_GROUP_DELAYING_MEMBER 1 +#define IGMP_GROUP_IDLE_MEMBER 2 + +/** + * IGMP packet format. + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct igmp_msg { + PACK_STRUCT_FLD_8(u8_t igmp_msgtype); + PACK_STRUCT_FLD_8(u8_t igmp_maxresp); + PACK_STRUCT_FIELD(u16_t igmp_checksum); + PACK_STRUCT_FLD_S(ip4_addr_p_t igmp_group_address); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_IGMP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h new file mode 100644 index 0000000..223158f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip.h @@ -0,0 +1,59 @@ +/** + * @file + * IP protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_IP_H +#define LWIP_HDR_PROT_IP_H + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define IP_PROTO_ICMP 1 +#define IP_PROTO_IGMP 2 +#define IP_PROTO_UDP 17 +#define IP_PROTO_UDPLITE 136 +#define IP_PROTO_TCP 6 + +/** This operates on a void* by loading the first byte */ +#define IP_HDR_GET_VERSION(ptr) ((*(u8_t*)(ptr)) >> 4) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_IP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h new file mode 100644 index 0000000..9347461 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip4.h @@ -0,0 +1,131 @@ +/** + * @file + * IPv4 protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_IP4_H +#define LWIP_HDR_PROT_IP4_H + +#include "lwip/arch.h" +#include "lwip/ip4_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** This is the packed version of ip4_addr_t, + used in network headers that are itself packed */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip4_addr_packed { + PACK_STRUCT_FIELD(u32_t addr); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +typedef struct ip4_addr_packed ip4_addr_p_t; + +/* Size of the IPv4 header. Same as 'sizeof(struct ip_hdr)'. */ +#define IP_HLEN 20 +/* Maximum size of the IPv4 header with options. */ +#define IP_HLEN_MAX 60 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/* The IPv4 header */ +struct ip_hdr { + /* version / header length */ + PACK_STRUCT_FLD_8(u8_t _v_hl); + /* type of service */ + PACK_STRUCT_FLD_8(u8_t _tos); + /* total length */ + PACK_STRUCT_FIELD(u16_t _len); + /* identification */ + PACK_STRUCT_FIELD(u16_t _id); + /* fragment offset field */ + PACK_STRUCT_FIELD(u16_t _offset); +#define IP_RF 0x8000U /* reserved fragment flag */ +#define IP_DF 0x4000U /* don't fragment flag */ +#define IP_MF 0x2000U /* more fragments flag */ +#define IP_OFFMASK 0x1fffU /* mask for fragmenting bits */ + /* time to live */ + PACK_STRUCT_FLD_8(u8_t _ttl); + /* protocol*/ + PACK_STRUCT_FLD_8(u8_t _proto); + /* checksum */ + PACK_STRUCT_FIELD(u16_t _chksum); + /* source and destination IP addresses */ + PACK_STRUCT_FLD_S(ip4_addr_p_t src); + PACK_STRUCT_FLD_S(ip4_addr_p_t dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* Macros to get struct ip_hdr fields: */ +#define IPH_V(hdr) ((hdr)->_v_hl >> 4) +#define IPH_HL(hdr) ((hdr)->_v_hl & 0x0f) +#define IPH_HL_BYTES(hdr) ((u8_t)(IPH_HL(hdr) * 4)) +#define IPH_TOS(hdr) ((hdr)->_tos) +#define IPH_LEN(hdr) ((hdr)->_len) +#define IPH_ID(hdr) ((hdr)->_id) +#define IPH_OFFSET(hdr) ((hdr)->_offset) +#define IPH_OFFSET_BYTES(hdr) ((u16_t)((lwip_ntohs(IPH_OFFSET(hdr)) & IP_OFFMASK) * 8U)) +#define IPH_TTL(hdr) ((hdr)->_ttl) +#define IPH_PROTO(hdr) ((hdr)->_proto) +#define IPH_CHKSUM(hdr) ((hdr)->_chksum) + +/* Macros to set struct ip_hdr fields: */ +#define IPH_VHL_SET(hdr, v, hl) (hdr)->_v_hl = (u8_t)((((v) << 4) | (hl))) +#define IPH_TOS_SET(hdr, tos) (hdr)->_tos = (tos) +#define IPH_LEN_SET(hdr, len) (hdr)->_len = (len) +#define IPH_ID_SET(hdr, id) (hdr)->_id = (id) +#define IPH_OFFSET_SET(hdr, off) (hdr)->_offset = (off) +#define IPH_TTL_SET(hdr, ttl) (hdr)->_ttl = (u8_t)(ttl) +#define IPH_PROTO_SET(hdr, proto) (hdr)->_proto = (u8_t)(proto) +#define IPH_CHKSUM_SET(hdr, chksum) (hdr)->_chksum = (chksum) + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_IP4_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h new file mode 100644 index 0000000..0f6de45 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/ip6.h @@ -0,0 +1,233 @@ +/** + * @file + * IPv6 protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_IP6_H +#define LWIP_HDR_PROT_IP6_H + +#include "lwip/arch.h" +#include "lwip/ip6_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** This is the packed version of ip6_addr_t, + used in network headers that are itself packed */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_addr_packed { + PACK_STRUCT_FIELD(u32_t addr[4]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +typedef struct ip6_addr_packed ip6_addr_p_t; + +#define IP6_HLEN 40 + +#define IP6_NEXTH_HOPBYHOP 0 +#define IP6_NEXTH_TCP 6 +#define IP6_NEXTH_UDP 17 +#define IP6_NEXTH_ENCAPS 41 +#define IP6_NEXTH_ROUTING 43 +#define IP6_NEXTH_FRAGMENT 44 +#define IP6_NEXTH_ICMP6 58 +#define IP6_NEXTH_NONE 59 +#define IP6_NEXTH_DESTOPTS 60 +#define IP6_NEXTH_UDPLITE 136 + +/** The IPv6 header. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_hdr { + /** version / traffic class / flow label */ + PACK_STRUCT_FIELD(u32_t _v_tc_fl); + /** payload length */ + PACK_STRUCT_FIELD(u16_t _plen); + /** next header */ + PACK_STRUCT_FLD_8(u8_t _nexth); + /** hop limit */ + PACK_STRUCT_FLD_8(u8_t _hoplim); + /** source and destination IP addresses */ + PACK_STRUCT_FLD_S(ip6_addr_p_t src); + PACK_STRUCT_FLD_S(ip6_addr_p_t dest); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define IP6H_V(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 28) & 0x0f) +#define IP6H_TC(hdr) ((lwip_ntohl((hdr)->_v_tc_fl) >> 20) & 0xff) +#define IP6H_FL(hdr) (lwip_ntohl((hdr)->_v_tc_fl) & 0x000fffff) +#define IP6H_PLEN(hdr) (lwip_ntohs((hdr)->_plen)) +#define IP6H_NEXTH(hdr) ((hdr)->_nexth) +#define IP6H_NEXTH_P(hdr) ((u8_t *)(hdr) + 6) +#define IP6H_HOPLIM(hdr) ((hdr)->_hoplim) +#define IP6H_VTCFL_SET(hdr, v, tc, fl) (hdr)->_v_tc_fl = (lwip_htonl((((u32_t)(v)) << 28) | (((u32_t)(tc)) << 20) | (fl))) +#define IP6H_PLEN_SET(hdr, plen) (hdr)->_plen = lwip_htons(plen) +#define IP6H_NEXTH_SET(hdr, nexth) (hdr)->_nexth = (nexth) +#define IP6H_HOPLIM_SET(hdr, hl) (hdr)->_hoplim = (u8_t)(hl) + +/* ipv6 extended options header */ +#define IP6_PAD1_OPTION 0 +#define IP6_PADN_OPTION 1 +#define IP6_ROUTER_ALERT_OPTION 5 +#define IP6_JUMBO_OPTION 194 +#define IP6_HOME_ADDRESS_OPTION 201 +#define IP6_ROUTER_ALERT_DLEN 2 +#define IP6_ROUTER_ALERT_VALUE_MLD 0 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_opt_hdr { + /* router alert option type */ + PACK_STRUCT_FLD_8(u8_t _opt_type); + /* router alert option data len */ + PACK_STRUCT_FLD_8(u8_t _opt_dlen); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define IP6_OPT_HLEN 2 +#define IP6_OPT_TYPE_ACTION(hdr) ((((hdr)->_opt_type) >> 6) & 0x3) +#define IP6_OPT_TYPE_CHANGE(hdr) ((((hdr)->_opt_type) >> 5) & 0x1) +#define IP6_OPT_TYPE(hdr) ((hdr)->_opt_type) +#define IP6_OPT_DLEN(hdr) ((hdr)->_opt_dlen) + +/* Hop-by-Hop header. */ +#define IP6_HBH_HLEN 2 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_hbh_hdr { + /* next header */ + PACK_STRUCT_FLD_8(u8_t _nexth); + /* header length in 8-octet units */ + PACK_STRUCT_FLD_8(u8_t _hlen); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define IP6_HBH_NEXTH(hdr) ((hdr)->_nexth) + +/* Destination header. */ +#define IP6_DEST_HLEN 2 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_dest_hdr { + /* next header */ + PACK_STRUCT_FLD_8(u8_t _nexth); + /* header length in 8-octet units */ + PACK_STRUCT_FLD_8(u8_t _hlen); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define IP6_DEST_NEXTH(hdr) ((hdr)->_nexth) + +/* Routing header */ +#define IP6_ROUT_TYPE2 2 +#define IP6_ROUT_RPL 3 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_rout_hdr { + /* next header */ + PACK_STRUCT_FLD_8(u8_t _nexth); + /* reserved */ + PACK_STRUCT_FLD_8(u8_t _hlen); + /* fragment offset */ + PACK_STRUCT_FIELD(u8_t _routing_type); + /* fragmented packet identification */ + PACK_STRUCT_FIELD(u8_t _segments_left); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define IP6_ROUT_NEXTH(hdr) ((hdr)->_nexth) +#define IP6_ROUT_TYPE(hdr) ((hdr)->_routing_type) +#define IP6_ROUT_SEG_LEFT(hdr) ((hdr)->_segments_left) + +/* Fragment header. */ +#define IP6_FRAG_HLEN 8 +#define IP6_FRAG_OFFSET_MASK 0xfff8 +#define IP6_FRAG_MORE_FLAG 0x0001 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ip6_frag_hdr { + /* next header */ + PACK_STRUCT_FLD_8(u8_t _nexth); + /* reserved */ + PACK_STRUCT_FLD_8(u8_t reserved); + /* fragment offset */ + PACK_STRUCT_FIELD(u16_t _fragment_offset); + /* fragmented packet identification */ + PACK_STRUCT_FIELD(u32_t _identification); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define IP6_FRAG_NEXTH(hdr) ((hdr)->_nexth) +#define IP6_FRAG_MBIT(hdr) (lwip_ntohs((hdr)->_fragment_offset) & 0x1) +#define IP6_FRAG_ID(hdr) (lwip_ntohl((hdr)->_identification)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_IP6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h new file mode 100644 index 0000000..71f1dcb --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/mld6.h @@ -0,0 +1,71 @@ +/** + * @file + * MLD6 protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_MLD6_H +#define LWIP_HDR_PROT_MLD6_H + +#include "lwip/arch.h" +#include "lwip/prot/ip6.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MLD6_HBH_HLEN 8 +/** Multicast listener report/query/done message header. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct mld_header { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t max_resp_delay); + PACK_STRUCT_FIELD(u16_t reserved); + PACK_STRUCT_FLD_S(ip6_addr_p_t multicast_address); + /* Options follow. */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_MLD6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h new file mode 100644 index 0000000..c270d07 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/nd6.h @@ -0,0 +1,274 @@ +/** + * @file + * ND6 protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_ND6_H +#define LWIP_HDR_PROT_ND6_H + +#include "lwip/arch.h" +#include "lwip/ip6_addr.h" +#include "lwip/prot/ip6.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Neighbor solicitation message header. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ns_header { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t reserved); + PACK_STRUCT_FLD_S(ip6_addr_p_t target_address); + /* Options follow. */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Neighbor advertisement message header. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct na_header { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FLD_8(u8_t flags); + PACK_STRUCT_FLD_8(u8_t reserved[3]); + PACK_STRUCT_FLD_S(ip6_addr_p_t target_address); + /* Options follow. */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#define ND6_FLAG_ROUTER (0x80) +#define ND6_FLAG_SOLICITED (0x40) +#define ND6_FLAG_OVERRIDE (0x20) + +/** Router solicitation message header. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct rs_header { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t reserved); + /* Options follow. */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Router advertisement message header. */ +#define ND6_RA_FLAG_MANAGED_ADDR_CONFIG (0x80) +#define ND6_RA_FLAG_OTHER_CONFIG (0x40) +#define ND6_RA_FLAG_HOME_AGENT (0x20) +#define ND6_RA_PREFERENCE_MASK (0x18) +#define ND6_RA_PREFERENCE_HIGH (0x08) +#define ND6_RA_PREFERENCE_MEDIUM (0x00) +#define ND6_RA_PREFERENCE_LOW (0x18) +#define ND6_RA_PREFERENCE_DISABLED (0x10) +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct ra_header { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FLD_8(u8_t current_hop_limit); + PACK_STRUCT_FLD_8(u8_t flags); + PACK_STRUCT_FIELD(u16_t router_lifetime); + PACK_STRUCT_FIELD(u32_t reachable_time); + PACK_STRUCT_FIELD(u32_t retrans_timer); + /* Options follow. */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Redirect message header. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct redirect_header { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u32_t reserved); + PACK_STRUCT_FLD_S(ip6_addr_p_t target_address); + PACK_STRUCT_FLD_S(ip6_addr_p_t destination_address); + /* Options follow. */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Link-layer address option. */ +#define ND6_OPTION_TYPE_SOURCE_LLADDR (0x01) +#define ND6_OPTION_TYPE_TARGET_LLADDR (0x02) +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct lladdr_option { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t length); + PACK_STRUCT_FLD_8(u8_t addr[NETIF_MAX_HWADDR_LEN]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Prefix information option. */ +#define ND6_OPTION_TYPE_PREFIX_INFO (0x03) +#define ND6_PREFIX_FLAG_ON_LINK (0x80) +#define ND6_PREFIX_FLAG_AUTONOMOUS (0x40) +#define ND6_PREFIX_FLAG_ROUTER_ADDRESS (0x20) +#define ND6_PREFIX_FLAG_SITE_PREFIX (0x10) +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct prefix_option { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t length); + PACK_STRUCT_FLD_8(u8_t prefix_length); + PACK_STRUCT_FLD_8(u8_t flags); + PACK_STRUCT_FIELD(u32_t valid_lifetime); + PACK_STRUCT_FIELD(u32_t preferred_lifetime); + PACK_STRUCT_FLD_8(u8_t reserved2[3]); + PACK_STRUCT_FLD_8(u8_t site_prefix_length); + PACK_STRUCT_FLD_S(ip6_addr_p_t prefix); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Redirected header option. */ +#define ND6_OPTION_TYPE_REDIR_HDR (0x04) +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct redirected_header_option { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t length); + PACK_STRUCT_FLD_8(u8_t reserved[6]); + /* Portion of redirected packet follows. */ + /* PACK_STRUCT_FLD_8(u8_t redirected[8]); */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** MTU option. */ +#define ND6_OPTION_TYPE_MTU (0x05) +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct mtu_option { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t length); + PACK_STRUCT_FIELD(u16_t reserved); + PACK_STRUCT_FIELD(u32_t mtu); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Route information option. */ +#define ND6_OPTION_TYPE_ROUTE_INFO (24) +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct route_option { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t length); + PACK_STRUCT_FLD_8(u8_t prefix_length); + PACK_STRUCT_FLD_8(u8_t preference); + PACK_STRUCT_FIELD(u32_t route_lifetime); + PACK_STRUCT_FLD_S(ip6_addr_p_t prefix); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/** Recursive DNS Server Option. */ +#define ND6_OPTION_TYPE_RDNSS (25) +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct rdnss_option { + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t length); + PACK_STRUCT_FIELD(u16_t reserved); + PACK_STRUCT_FIELD(u32_t lifetime); + PACK_STRUCT_FLD_S(ip6_addr_p_t rdnss_address[1]); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#define SIZEOF_RDNSS_OPTION_BASE 8 /* size without addresses */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_ND6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h new file mode 100644 index 0000000..c1d7de1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/tcp.h @@ -0,0 +1,100 @@ +/** + * @file + * TCP protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_TCP_H +#define LWIP_HDR_PROT_TCP_H + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Length of the TCP header, excluding options. */ +#define TCP_HLEN 20 + +/* Fields are (of course) in network byte order. + * Some fields are converted to host byte order in tcp_input(). + */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct tcp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); + PACK_STRUCT_FIELD(u32_t seqno); + PACK_STRUCT_FIELD(u32_t ackno); + PACK_STRUCT_FIELD(u16_t _hdrlen_rsvd_flags); + PACK_STRUCT_FIELD(u16_t wnd); + PACK_STRUCT_FIELD(u16_t chksum); + PACK_STRUCT_FIELD(u16_t urgp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* TCP header flags bits */ +#define TCP_FIN 0x01U +#define TCP_SYN 0x02U +#define TCP_RST 0x04U +#define TCP_PSH 0x08U +#define TCP_ACK 0x10U +#define TCP_URG 0x20U +#define TCP_ECE 0x40U +#define TCP_CWR 0x80U +/* Valid TCP header flags */ +#define TCP_FLAGS 0x3fU + +#define TCP_MAX_OPTION_BYTES 40 + +#define TCPH_HDRLEN(phdr) ((u16_t)(lwip_ntohs((phdr)->_hdrlen_rsvd_flags) >> 12)) +#define TCPH_HDRLEN_BYTES(phdr) ((u8_t)(TCPH_HDRLEN(phdr) << 2)) +#define TCPH_FLAGS(phdr) ((u8_t)((lwip_ntohs((phdr)->_hdrlen_rsvd_flags) & TCP_FLAGS))) + +#define TCPH_HDRLEN_SET(phdr, len) (phdr)->_hdrlen_rsvd_flags = lwip_htons(((len) << 12) | TCPH_FLAGS(phdr)) +#define TCPH_FLAGS_SET(phdr, flags) (phdr)->_hdrlen_rsvd_flags = (((phdr)->_hdrlen_rsvd_flags & PP_HTONS(~TCP_FLAGS)) | lwip_htons(flags)) +#define TCPH_HDRLEN_FLAGS_SET(phdr, len, flags) (phdr)->_hdrlen_rsvd_flags = (u16_t)(lwip_htons((u16_t)((len) << 12) | (flags))) + +#define TCPH_SET_FLAG(phdr, flags ) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags | lwip_htons(flags)) +#define TCPH_UNSET_FLAG(phdr, flags) (phdr)->_hdrlen_rsvd_flags = ((phdr)->_hdrlen_rsvd_flags & ~lwip_htons(flags)) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_TCP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h new file mode 100644 index 0000000..664f19a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/prot/udp.h @@ -0,0 +1,68 @@ +/** + * @file + * UDP protocol definitions + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_PROT_UDP_H +#define LWIP_HDR_PROT_UDP_H + +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDP_HLEN 8 + +/* Fields are (of course) in network byte order. */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct udp_hdr { + PACK_STRUCT_FIELD(u16_t src); + PACK_STRUCT_FIELD(u16_t dest); /* src/dest UDP ports */ + PACK_STRUCT_FIELD(u16_t len); + PACK_STRUCT_FIELD(u16_t chksum); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_PROT_UDP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/raw.h b/Middlewares/Third_Party/LwIP/src/include/lwip/raw.h new file mode 100644 index 0000000..b129bd3 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/raw.h @@ -0,0 +1,143 @@ +/** + * @file + * raw API (to be used from TCPIP thread)\n + * See also @ref raw_raw + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_RAW_H +#define LWIP_HDR_RAW_H + +#include "lwip/opt.h" + +#if LWIP_RAW /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/def.h" +#include "lwip/ip.h" +#include "lwip/ip_addr.h" +#include "lwip/ip6_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define RAW_FLAGS_CONNECTED 0x01U +#define RAW_FLAGS_HDRINCL 0x02U +#define RAW_FLAGS_MULTICAST_LOOP 0x04U + +struct raw_pcb; + +/** Function prototype for raw pcb receive callback functions. + * @param arg user supplied argument (raw_pcb.recv_arg) + * @param pcb the raw_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @return 1 if the packet was 'eaten' (aka. deleted), + * 0 if the packet lives on + * If returning 1, the callback is responsible for freeing the pbuf + * if it's not used any more. + */ +typedef u8_t (*raw_recv_fn)(void *arg, struct raw_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr); + +/** the RAW protocol control block */ +struct raw_pcb { + /* Common members of all PCB types */ + IP_PCB; + + struct raw_pcb *next; + + u8_t protocol; + u8_t flags; + +#if LWIP_MULTICAST_TX_OPTIONS + /** outgoing network interface for multicast packets, by interface index (if nonzero) */ + u8_t mcast_ifindex; + /** TTL for outgoing multicast packets */ + u8_t mcast_ttl; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + + /** receive callback function */ + raw_recv_fn recv; + /* user-supplied argument for the recv callback */ + void *recv_arg; +#if LWIP_IPV6 + /* fields for handling checksum computations as per RFC3542. */ + u16_t chksum_offset; + u8_t chksum_reqd; +#endif +}; + +/* The following functions is the application layer interface to the + RAW code. */ +struct raw_pcb * raw_new (u8_t proto); +struct raw_pcb * raw_new_ip_type(u8_t type, u8_t proto); +void raw_remove (struct raw_pcb *pcb); +err_t raw_bind (struct raw_pcb *pcb, const ip_addr_t *ipaddr); +void raw_bind_netif (struct raw_pcb *pcb, const struct netif *netif); +err_t raw_connect (struct raw_pcb *pcb, const ip_addr_t *ipaddr); +void raw_disconnect (struct raw_pcb *pcb); + +err_t raw_sendto (struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *ipaddr); +err_t raw_sendto_if_src(struct raw_pcb *pcb, struct pbuf *p, const ip_addr_t *dst_ip, struct netif *netif, const ip_addr_t *src_ip); +err_t raw_send (struct raw_pcb *pcb, struct pbuf *p); + +void raw_recv (struct raw_pcb *pcb, raw_recv_fn recv, void *recv_arg); + +#define raw_flags(pcb) ((pcb)->flags) +#define raw_setflags(pcb,f) ((pcb)->flags = (f)) + +#define raw_set_flags(pcb, set_flags) do { (pcb)->flags = (u8_t)((pcb)->flags | (set_flags)); } while(0) +#define raw_clear_flags(pcb, clr_flags) do { (pcb)->flags = (u8_t)((pcb)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0) +#define raw_is_flag_set(pcb, flag) (((pcb)->flags & (flag)) != 0) + +#define raw_init() /* Compatibility define, no init needed. */ + +/* for compatibility with older implementation */ +#define raw_new_ip6(proto) raw_new_ip_type(IPADDR_TYPE_V6, proto) + +#if LWIP_MULTICAST_TX_OPTIONS +#define raw_set_multicast_netif_index(pcb, idx) ((pcb)->mcast_ifindex = (idx)) +#define raw_get_multicast_netif_index(pcb) ((pcb)->mcast_ifindex) +#define raw_set_multicast_ttl(pcb, value) ((pcb)->mcast_ttl = (value)) +#define raw_get_multicast_ttl(pcb) ((pcb)->mcast_ttl) +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_RAW */ + +#endif /* LWIP_HDR_RAW_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/sio.h b/Middlewares/Third_Party/LwIP/src/include/lwip/sio.h new file mode 100644 index 0000000..7643e19 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/sio.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + */ + +/* + * This is the interface to the platform specific serial IO module + * It needs to be implemented by those platforms which need SLIP or PPP + */ + +#ifndef SIO_H +#define SIO_H + +#include "lwip/arch.h" +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* If you want to define sio_fd_t elsewhere or differently, + define this in your cc.h file. */ +#ifndef __sio_fd_t_defined +typedef void * sio_fd_t; +#endif + +/* The following functions can be defined to something else in your cc.h file + or be implemented in your custom sio.c file. */ + +#ifndef sio_open +/** + * Opens a serial device for communication. + * + * @param devnum device number + * @return handle to serial device if successful, NULL otherwise + */ +sio_fd_t sio_open(u8_t devnum); +#endif + +#ifndef sio_send +/** + * Sends a single character to the serial device. + * + * @param c character to send + * @param fd serial device handle + * + * @note This function will block until the character can be sent. + */ +void sio_send(u8_t c, sio_fd_t fd); +#endif + +#ifndef sio_recv +/** + * Receives a single character from the serial device. + * + * @param fd serial device handle + * + * @note This function will block until a character is received. + */ +u8_t sio_recv(sio_fd_t fd); +#endif + +#ifndef sio_read +/** + * Reads from the serial device. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received - may be 0 if aborted by sio_read_abort + * + * @note This function will block until data can be received. The blocking + * can be cancelled by calling sio_read_abort(). + */ +u32_t sio_read(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_tryread +/** + * Tries to read from the serial device. Same as sio_read but returns + * immediately if no data is available and never blocks. + * + * @param fd serial device handle + * @param data pointer to data buffer for receiving + * @param len maximum length (in bytes) of data to receive + * @return number of bytes actually received + */ +u32_t sio_tryread(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_write +/** + * Writes to the serial device. + * + * @param fd serial device handle + * @param data pointer to data to send + * @param len length (in bytes) of data to send + * @return number of bytes actually sent + * + * @note This function will block until all data can be sent. + */ +u32_t sio_write(sio_fd_t fd, u8_t *data, u32_t len); +#endif + +#ifndef sio_read_abort +/** + * Aborts a blocking sio_read() call. + * + * @param fd serial device handle + */ +void sio_read_abort(sio_fd_t fd); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SIO_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h new file mode 100644 index 0000000..8704d0b --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/snmp.h @@ -0,0 +1,213 @@ +/** + * @file + * SNMP support API for implementing netifs and statitics for MIB2 + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Dirk Ziegelmeier + * + */ +#ifndef LWIP_HDR_SNMP_H +#define LWIP_HDR_SNMP_H + +#include "lwip/opt.h" +#include "lwip/ip_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct udp_pcb; +struct netif; + +/** + * @defgroup netif_mib2 MIB2 statistics + * @ingroup netif + */ + +/* MIB2 statistics functions */ +#if MIB2_STATS /* don't build if not configured for use in lwipopts.h */ +/** + * @ingroup netif_mib2 + * @see RFC1213, "MIB-II, 6. Definitions" + */ +enum snmp_ifType { + snmp_ifType_other=1, /* none of the following */ + snmp_ifType_regular1822, + snmp_ifType_hdh1822, + snmp_ifType_ddn_x25, + snmp_ifType_rfc877_x25, + snmp_ifType_ethernet_csmacd, + snmp_ifType_iso88023_csmacd, + snmp_ifType_iso88024_tokenBus, + snmp_ifType_iso88025_tokenRing, + snmp_ifType_iso88026_man, + snmp_ifType_starLan, + snmp_ifType_proteon_10Mbit, + snmp_ifType_proteon_80Mbit, + snmp_ifType_hyperchannel, + snmp_ifType_fddi, + snmp_ifType_lapb, + snmp_ifType_sdlc, + snmp_ifType_ds1, /* T-1 */ + snmp_ifType_e1, /* european equiv. of T-1 */ + snmp_ifType_basicISDN, + snmp_ifType_primaryISDN, /* proprietary serial */ + snmp_ifType_propPointToPointSerial, + snmp_ifType_ppp, + snmp_ifType_softwareLoopback, + snmp_ifType_eon, /* CLNP over IP [11] */ + snmp_ifType_ethernet_3Mbit, + snmp_ifType_nsip, /* XNS over IP */ + snmp_ifType_slip, /* generic SLIP */ + snmp_ifType_ultra, /* ULTRA technologies */ + snmp_ifType_ds3, /* T-3 */ + snmp_ifType_sip, /* SMDS */ + snmp_ifType_frame_relay +}; + +/** This macro has a precision of ~49 days because sys_now returns u32_t. \#define your own if you want ~490 days. */ +#ifndef MIB2_COPY_SYSUPTIME_TO +#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) (*(ptrToVal) = (sys_now() / 10)) +#endif + +/** + * @ingroup netif_mib2 + * Increment stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs) + */ +#define MIB2_STATS_NETIF_INC(n, x) do { ++(n)->mib2_counters.x; } while(0) +/** + * @ingroup netif_mib2 + * Add value to stats member for SNMP MIB2 stats (struct stats_mib2_netif_ctrs) + */ +#define MIB2_STATS_NETIF_ADD(n, x, val) do { (n)->mib2_counters.x += (val); } while(0) + +/** + * @ingroup netif_mib2 + * Init MIB2 statistic counters in netif + * @param netif Netif to init + * @param type one of enum @ref snmp_ifType + * @param speed your link speed here (units: bits per second) + */ +#define MIB2_INIT_NETIF(netif, type, speed) do { \ + (netif)->link_type = (type); \ + (netif)->link_speed = (speed);\ + (netif)->ts = 0; \ + (netif)->mib2_counters.ifinoctets = 0; \ + (netif)->mib2_counters.ifinucastpkts = 0; \ + (netif)->mib2_counters.ifinnucastpkts = 0; \ + (netif)->mib2_counters.ifindiscards = 0; \ + (netif)->mib2_counters.ifinerrors = 0; \ + (netif)->mib2_counters.ifinunknownprotos = 0; \ + (netif)->mib2_counters.ifoutoctets = 0; \ + (netif)->mib2_counters.ifoutucastpkts = 0; \ + (netif)->mib2_counters.ifoutnucastpkts = 0; \ + (netif)->mib2_counters.ifoutdiscards = 0; \ + (netif)->mib2_counters.ifouterrors = 0; } while(0) +#else /* MIB2_STATS */ +#ifndef MIB2_COPY_SYSUPTIME_TO +#define MIB2_COPY_SYSUPTIME_TO(ptrToVal) +#endif +#define MIB2_INIT_NETIF(netif, type, speed) +#define MIB2_STATS_NETIF_INC(n, x) +#define MIB2_STATS_NETIF_ADD(n, x, val) +#endif /* MIB2_STATS */ + +/* LWIP MIB2 callbacks */ +#if LWIP_MIB2_CALLBACKS /* don't build if not configured for use in lwipopts.h */ +/* network interface */ +void mib2_netif_added(struct netif *ni); +void mib2_netif_removed(struct netif *ni); + +#if LWIP_IPV4 && LWIP_ARP +/* ARP (for atTable and ipNetToMediaTable) */ +void mib2_add_arp_entry(struct netif *ni, ip4_addr_t *ip); +void mib2_remove_arp_entry(struct netif *ni, ip4_addr_t *ip); +#else /* LWIP_IPV4 && LWIP_ARP */ +#define mib2_add_arp_entry(ni,ip) +#define mib2_remove_arp_entry(ni,ip) +#endif /* LWIP_IPV4 && LWIP_ARP */ + +/* IP */ +#if LWIP_IPV4 +void mib2_add_ip4(struct netif *ni); +void mib2_remove_ip4(struct netif *ni); +void mib2_add_route_ip4(u8_t dflt, struct netif *ni); +void mib2_remove_route_ip4(u8_t dflt, struct netif *ni); +#endif /* LWIP_IPV4 */ + +/* UDP */ +#if LWIP_UDP +void mib2_udp_bind(struct udp_pcb *pcb); +void mib2_udp_unbind(struct udp_pcb *pcb); +#endif /* LWIP_UDP */ + +#else /* LWIP_MIB2_CALLBACKS */ +/* LWIP_MIB2_CALLBACKS support not available */ +/* define everything to be empty */ + +/* network interface */ +#define mib2_netif_added(ni) +#define mib2_netif_removed(ni) + +/* ARP */ +#define mib2_add_arp_entry(ni,ip) +#define mib2_remove_arp_entry(ni,ip) + +/* IP */ +#define mib2_add_ip4(ni) +#define mib2_remove_ip4(ni) +#define mib2_add_route_ip4(dflt, ni) +#define mib2_remove_route_ip4(dflt, ni) + +/* UDP */ +#define mib2_udp_bind(pcb) +#define mib2_udp_unbind(pcb) +#endif /* LWIP_MIB2_CALLBACKS */ + +/* for source-code compatibility reasons only, can be removed (not used internally) */ +#define NETIF_INIT_SNMP MIB2_INIT_NETIF +#define snmp_add_ifinoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifinoctets, value) +#define snmp_inc_ifinucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifinucastpkts) +#define snmp_inc_ifinnucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifinnucastpkts) +#define snmp_inc_ifindiscards(ni) MIB2_STATS_NETIF_INC(ni, ifindiscards) +#define snmp_inc_ifinerrors(ni) MIB2_STATS_NETIF_INC(ni, ifinerrors) +#define snmp_inc_ifinunknownprotos(ni) MIB2_STATS_NETIF_INC(ni, ifinunknownprotos) +#define snmp_add_ifoutoctets(ni,value) MIB2_STATS_NETIF_ADD(ni, ifoutoctets, value) +#define snmp_inc_ifoutucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifoutucastpkts) +#define snmp_inc_ifoutnucastpkts(ni) MIB2_STATS_NETIF_INC(ni, ifoutnucastpkts) +#define snmp_inc_ifoutdiscards(ni) MIB2_STATS_NETIF_INC(ni, ifoutdiscards) +#define snmp_inc_ifouterrors(ni) MIB2_STATS_NETIF_INC(ni, ifouterrors) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_SNMP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h b/Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h new file mode 100644 index 0000000..d70d36c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/sockets.h @@ -0,0 +1,688 @@ +/** + * @file + * Socket API (to be used from non-TCPIP threads) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + + +#ifndef LWIP_HDR_SOCKETS_H +#define LWIP_HDR_SOCKETS_H + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/err.h" +#include "lwip/inet.h" +#include "lwip/errno.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* If your port already typedef's sa_family_t, define SA_FAMILY_T_DEFINED + to prevent this code from redefining it. */ +#if !defined(sa_family_t) && !defined(SA_FAMILY_T_DEFINED) +typedef u8_t sa_family_t; +#endif +/* If your port already typedef's in_port_t, define IN_PORT_T_DEFINED + to prevent this code from redefining it. */ +#if !defined(in_port_t) && !defined(IN_PORT_T_DEFINED) +typedef u16_t in_port_t; +#endif + +#if LWIP_IPV4 +/* members are in network byte order */ +struct sockaddr_in { + u8_t sin_len; + sa_family_t sin_family; + in_port_t sin_port; + struct in_addr sin_addr; +#define SIN_ZERO_LEN 8 + char sin_zero[SIN_ZERO_LEN]; +}; +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +struct sockaddr_in6 { + u8_t sin6_len; /* length of this structure */ + sa_family_t sin6_family; /* AF_INET6 */ + in_port_t sin6_port; /* Transport layer port # */ + u32_t sin6_flowinfo; /* IPv6 flow information */ + struct in6_addr sin6_addr; /* IPv6 address */ + u32_t sin6_scope_id; /* Set of interfaces for scope */ +}; +#endif /* LWIP_IPV6 */ + +struct sockaddr { + u8_t sa_len; + sa_family_t sa_family; + char sa_data[14]; +}; + +struct sockaddr_storage { + u8_t s2_len; + sa_family_t ss_family; + char s2_data1[2]; + u32_t s2_data2[3]; +#if LWIP_IPV6 + u32_t s2_data3[3]; +#endif /* LWIP_IPV6 */ +}; + +/* If your port already typedef's socklen_t, define SOCKLEN_T_DEFINED + to prevent this code from redefining it. */ +#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED) +typedef u32_t socklen_t; +#endif + +#if !defined IOV_MAX +#define IOV_MAX 0xFFFF +#elif IOV_MAX > 0xFFFF +#error "IOV_MAX larger than supported by LwIP" +#endif /* IOV_MAX */ + +#if !defined(iovec) +struct iovec { + void *iov_base; + size_t iov_len; +}; +#endif + +struct msghdr { + void *msg_name; + socklen_t msg_namelen; + struct iovec *msg_iov; + int msg_iovlen; + void *msg_control; + socklen_t msg_controllen; + int msg_flags; +}; + +/* struct msghdr->msg_flags bit field values */ +#define MSG_TRUNC 0x04 +#define MSG_CTRUNC 0x08 + +/* RFC 3542, Section 20: Ancillary Data */ +struct cmsghdr { + socklen_t cmsg_len; /* number of bytes, including header */ + int cmsg_level; /* originating protocol */ + int cmsg_type; /* protocol-specific type */ +}; +/* Data section follows header and possible padding, typically referred to as + unsigned char cmsg_data[]; */ + +/* cmsg header/data alignment. NOTE: we align to native word size (double word +size on 16-bit arch) so structures are not placed at an unaligned address. +16-bit arch needs double word to ensure 32-bit alignment because socklen_t +could be 32 bits. If we ever have cmsg data with a 64-bit variable, alignment +will need to increase long long */ +#define ALIGN_H(size) (((size) + sizeof(long) - 1U) & ~(sizeof(long)-1U)) +#define ALIGN_D(size) ALIGN_H(size) + +#define CMSG_FIRSTHDR(mhdr) \ + ((mhdr)->msg_controllen >= sizeof(struct cmsghdr) ? \ + (struct cmsghdr *)(mhdr)->msg_control : \ + (struct cmsghdr *)NULL) + +#define CMSG_NXTHDR(mhdr, cmsg) \ + (((cmsg) == NULL) ? CMSG_FIRSTHDR(mhdr) : \ + (((u8_t *)(cmsg) + ALIGN_H((cmsg)->cmsg_len) \ + + ALIGN_D(sizeof(struct cmsghdr)) > \ + (u8_t *)((mhdr)->msg_control) + (mhdr)->msg_controllen) ? \ + (struct cmsghdr *)NULL : \ + (struct cmsghdr *)((void*)((u8_t *)(cmsg) + \ + ALIGN_H((cmsg)->cmsg_len))))) + +#define CMSG_DATA(cmsg) ((void*)((u8_t *)(cmsg) + \ + ALIGN_D(sizeof(struct cmsghdr)))) + +#define CMSG_SPACE(length) (ALIGN_D(sizeof(struct cmsghdr)) + \ + ALIGN_H(length)) + +#define CMSG_LEN(length) (ALIGN_D(sizeof(struct cmsghdr)) + \ + length) + +/* Set socket options argument */ +#define IFNAMSIZ NETIF_NAMESIZE +struct ifreq { + char ifr_name[IFNAMSIZ]; /* Interface name */ +}; + +/* Socket protocol types (TCP/UDP/RAW) */ +#define SOCK_STREAM 1 +#define SOCK_DGRAM 2 +#define SOCK_RAW 3 + +/* + * Option flags per-socket. These must match the SOF_ flags in ip.h (checked in init.c) + */ +#define SO_REUSEADDR 0x0004 /* Allow local address reuse */ +#define SO_KEEPALIVE 0x0008 /* keep connections alive */ +#define SO_BROADCAST 0x0020 /* permit to send and to receive broadcast messages (see IP_SOF_BROADCAST option) */ + + +/* + * Additional options, not kept in so_options. + */ +#define SO_DEBUG 0x0001 /* Unimplemented: turn on debugging info recording */ +#define SO_ACCEPTCONN 0x0002 /* socket has had listen() */ +#define SO_DONTROUTE 0x0010 /* Unimplemented: just use interface addresses */ +#define SO_USELOOPBACK 0x0040 /* Unimplemented: bypass hardware when possible */ +#define SO_LINGER 0x0080 /* linger on close if data present */ +#define SO_DONTLINGER ((int)(~SO_LINGER)) +#define SO_OOBINLINE 0x0100 /* Unimplemented: leave received OOB data in line */ +#define SO_REUSEPORT 0x0200 /* Unimplemented: allow local address & port reuse */ +#define SO_SNDBUF 0x1001 /* Unimplemented: send buffer size */ +#define SO_RCVBUF 0x1002 /* receive buffer size */ +#define SO_SNDLOWAT 0x1003 /* Unimplemented: send low-water mark */ +#define SO_RCVLOWAT 0x1004 /* Unimplemented: receive low-water mark */ +#define SO_SNDTIMEO 0x1005 /* send timeout */ +#define SO_RCVTIMEO 0x1006 /* receive timeout */ +#define SO_ERROR 0x1007 /* get error status and clear */ +#define SO_TYPE 0x1008 /* get socket type */ +#define SO_CONTIMEO 0x1009 /* Unimplemented: connect timeout */ +#define SO_NO_CHECK 0x100a /* don't create UDP checksum */ +#define SO_BINDTODEVICE 0x100b /* bind to device */ + +/* + * Structure used for manipulating linger option. + */ +struct linger { + int l_onoff; /* option on/off */ + int l_linger; /* linger time in seconds */ +}; + +/* + * Level number for (get/set)sockopt() to apply to socket itself. + */ +#define SOL_SOCKET 0xfff /* options for socket level */ + + +#define AF_UNSPEC 0 +#define AF_INET 2 +#if LWIP_IPV6 +#define AF_INET6 10 +#else /* LWIP_IPV6 */ +#define AF_INET6 AF_UNSPEC +#endif /* LWIP_IPV6 */ +#define PF_INET AF_INET +#define PF_INET6 AF_INET6 +#define PF_UNSPEC AF_UNSPEC + +#define IPPROTO_IP 0 +#define IPPROTO_ICMP 1 +#define IPPROTO_TCP 6 +#define IPPROTO_UDP 17 +#if LWIP_IPV6 +#define IPPROTO_IPV6 41 +#define IPPROTO_ICMPV6 58 +#endif /* LWIP_IPV6 */ +#define IPPROTO_UDPLITE 136 +#define IPPROTO_RAW 255 + +/* Flags we can use with send and recv. */ +#define MSG_PEEK 0x01 /* Peeks at an incoming message */ +#define MSG_WAITALL 0x02 /* Unimplemented: Requests that the function block until the full amount of data requested can be returned */ +#define MSG_OOB 0x04 /* Unimplemented: Requests out-of-band data. The significance and semantics of out-of-band data are protocol-specific */ +#define MSG_DONTWAIT 0x08 /* Nonblocking i/o for this operation only */ +#define MSG_MORE 0x10 /* Sender will send more */ +#define MSG_NOSIGNAL 0x20 /* Uninmplemented: Requests not to send the SIGPIPE signal if an attempt to send is made on a stream-oriented socket that is no longer connected. */ + + +/* + * Options for level IPPROTO_IP + */ +#define IP_TOS 1 +#define IP_TTL 2 +#define IP_PKTINFO 8 + +#if LWIP_TCP +/* + * Options for level IPPROTO_TCP + */ +#define TCP_NODELAY 0x01 /* don't delay send to coalesce packets */ +#define TCP_KEEPALIVE 0x02 /* send KEEPALIVE probes when idle for pcb->keep_idle milliseconds */ +#define TCP_KEEPIDLE 0x03 /* set pcb->keep_idle - Same as TCP_KEEPALIVE, but use seconds for get/setsockopt */ +#define TCP_KEEPINTVL 0x04 /* set pcb->keep_intvl - Use seconds for get/setsockopt */ +#define TCP_KEEPCNT 0x05 /* set pcb->keep_cnt - Use number of probes sent for get/setsockopt */ +#endif /* LWIP_TCP */ + +#if LWIP_IPV6 +/* + * Options for level IPPROTO_IPV6 + */ +#define IPV6_CHECKSUM 7 /* RFC3542: calculate and insert the ICMPv6 checksum for raw sockets. */ +#define IPV6_V6ONLY 27 /* RFC3493: boolean control to restrict AF_INET6 sockets to IPv6 communications only. */ +#endif /* LWIP_IPV6 */ + +#if LWIP_UDP && LWIP_UDPLITE +/* + * Options for level IPPROTO_UDPLITE + */ +#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */ +#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */ +#endif /* LWIP_UDP && LWIP_UDPLITE*/ + + +#if LWIP_MULTICAST_TX_OPTIONS +/* + * Options and types for UDP multicast traffic handling + */ +#define IP_MULTICAST_TTL 5 +#define IP_MULTICAST_IF 6 +#define IP_MULTICAST_LOOP 7 +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + +#if LWIP_IGMP +/* + * Options and types related to multicast membership + */ +#define IP_ADD_MEMBERSHIP 3 +#define IP_DROP_MEMBERSHIP 4 + +typedef struct ip_mreq { + struct in_addr imr_multiaddr; /* IP multicast address of group */ + struct in_addr imr_interface; /* local IP address of interface */ +} ip_mreq; +#endif /* LWIP_IGMP */ + +#if LWIP_IPV4 +struct in_pktinfo { + unsigned int ipi_ifindex; /* Interface index */ + struct in_addr ipi_addr; /* Destination (from header) address */ +}; +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6_MLD +/* + * Options and types related to IPv6 multicast membership + */ +#define IPV6_JOIN_GROUP 12 +#define IPV6_ADD_MEMBERSHIP IPV6_JOIN_GROUP +#define IPV6_LEAVE_GROUP 13 +#define IPV6_DROP_MEMBERSHIP IPV6_LEAVE_GROUP + +typedef struct ipv6_mreq { + struct in6_addr ipv6mr_multiaddr; /* IPv6 multicast addr */ + unsigned int ipv6mr_interface; /* interface index, or 0 */ +} ipv6_mreq; +#endif /* LWIP_IPV6_MLD */ + +/* + * The Type of Service provides an indication of the abstract + * parameters of the quality of service desired. These parameters are + * to be used to guide the selection of the actual service parameters + * when transmitting a datagram through a particular network. Several + * networks offer service precedence, which somehow treats high + * precedence traffic as more important than other traffic (generally + * by accepting only traffic above a certain precedence at time of high + * load). The major choice is a three way tradeoff between low-delay, + * high-reliability, and high-throughput. + * The use of the Delay, Throughput, and Reliability indications may + * increase the cost (in some sense) of the service. In many networks + * better performance for one of these parameters is coupled with worse + * performance on another. Except for very unusual cases at most two + * of these three indications should be set. + */ +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos) & IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_LOWCOST 0x02 +#define IPTOS_MINCOST IPTOS_LOWCOST + +/* + * The Network Control precedence designation is intended to be used + * within a network only. The actual use and control of that + * designation is up to each network. The Internetwork Control + * designation is intended for use by gateway control originators only. + * If the actual use of these precedence designations is of concern to + * a particular network, it is the responsibility of that network to + * control the access to, and use of, those precedence designations. + */ +#define IPTOS_PREC_MASK 0xe0 +#define IPTOS_PREC(tos) ((tos) & IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* + * Commands for ioctlsocket(), taken from the BSD file fcntl.h. + * lwip_ioctl only supports FIONREAD and FIONBIO, for now + * + * Ioctl's have the command encoded in the lower word, + * and the size of any in or out parameters in the upper + * word. The high 2 bits of the upper word are used + * to encode the in/out status of the parameter; for now + * we restrict parameters to at most 128 bytes. + */ +#if !defined(FIONREAD) || !defined(FIONBIO) +#define IOCPARM_MASK 0x7fU /* parameters must be < 128 bytes */ +#define IOC_VOID 0x20000000UL /* no parameters */ +#define IOC_OUT 0x40000000UL /* copy out parameters */ +#define IOC_IN 0x80000000UL /* copy in parameters */ +#define IOC_INOUT (IOC_IN|IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define _IO(x,y) ((long)(IOC_VOID|((x)<<8)|(y))) + +#define _IOR(x,y,t) ((long)(IOC_OUT|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))) + +#define _IOW(x,y,t) ((long)(IOC_IN|((sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y))) +#endif /* !defined(FIONREAD) || !defined(FIONBIO) */ + +#ifndef FIONREAD +#define FIONREAD _IOR('f', 127, unsigned long) /* get # bytes to read */ +#endif +#ifndef FIONBIO +#define FIONBIO _IOW('f', 126, unsigned long) /* set/clear non-blocking i/o */ +#endif + +/* Socket I/O Controls: unimplemented */ +#ifndef SIOCSHIWAT +#define SIOCSHIWAT _IOW('s', 0, unsigned long) /* set high watermark */ +#define SIOCGHIWAT _IOR('s', 1, unsigned long) /* get high watermark */ +#define SIOCSLOWAT _IOW('s', 2, unsigned long) /* set low watermark */ +#define SIOCGLOWAT _IOR('s', 3, unsigned long) /* get low watermark */ +#define SIOCATMARK _IOR('s', 7, unsigned long) /* at oob mark? */ +#endif + +/* commands for fnctl */ +#ifndef F_GETFL +#define F_GETFL 3 +#endif +#ifndef F_SETFL +#define F_SETFL 4 +#endif + +/* File status flags and file access modes for fnctl, + these are bits in an int. */ +#ifndef O_NONBLOCK +#define O_NONBLOCK 1 /* nonblocking I/O */ +#endif +#ifndef O_NDELAY +#define O_NDELAY O_NONBLOCK /* same as O_NONBLOCK, for compatibility */ +#endif +#ifndef O_RDONLY +#define O_RDONLY 2 +#endif +#ifndef O_WRONLY +#define O_WRONLY 4 +#endif +#ifndef O_RDWR +#define O_RDWR (O_RDONLY|O_WRONLY) +#endif + +#ifndef SHUT_RD + #define SHUT_RD 0 + #define SHUT_WR 1 + #define SHUT_RDWR 2 +#endif + +/* FD_SET used for lwip_select */ +#ifndef FD_SET +#undef FD_SETSIZE +/* Make FD_SETSIZE match NUM_SOCKETS in socket.c */ +#define FD_SETSIZE MEMP_NUM_NETCONN +#define LWIP_SELECT_MAXNFDS (FD_SETSIZE + LWIP_SOCKET_OFFSET) +#define FDSETSAFESET(n, code) do { \ + if (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0)) { \ + code; }} while(0) +#define FDSETSAFEGET(n, code) (((n) - LWIP_SOCKET_OFFSET < MEMP_NUM_NETCONN) && (((int)(n) - LWIP_SOCKET_OFFSET) >= 0) ?\ + (code) : 0) +#define FD_SET(n, p) FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] = (u8_t)((p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] | (1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))) +#define FD_CLR(n, p) FDSETSAFESET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] = (u8_t)((p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] & ~(1 << (((n)-LWIP_SOCKET_OFFSET) & 7)))) +#define FD_ISSET(n,p) FDSETSAFEGET(n, (p)->fd_bits[((n)-LWIP_SOCKET_OFFSET)/8] & (1 << (((n)-LWIP_SOCKET_OFFSET) & 7))) +#define FD_ZERO(p) memset((void*)(p), 0, sizeof(*(p))) + +typedef struct fd_set +{ + unsigned char fd_bits [(FD_SETSIZE+7)/8]; +} fd_set; + +#elif FD_SETSIZE < (LWIP_SOCKET_OFFSET + MEMP_NUM_NETCONN) +#error "external FD_SETSIZE too small for number of sockets" +#else +#define LWIP_SELECT_MAXNFDS FD_SETSIZE +#endif /* FD_SET */ + +/* poll-related defines and types */ +/* @todo: find a better way to guard the definition of these defines and types if already defined */ +#if !defined(POLLIN) && !defined(POLLOUT) +#define POLLIN 0x1 +#define POLLOUT 0x2 +#define POLLERR 0x4 +#define POLLNVAL 0x8 +/* Below values are unimplemented */ +#define POLLRDNORM 0x10 +#define POLLRDBAND 0x20 +#define POLLPRI 0x40 +#define POLLWRNORM 0x80 +#define POLLWRBAND 0x100 +#define POLLHUP 0x200 +typedef unsigned int nfds_t; +struct pollfd +{ + int fd; + short events; + short revents; +}; +#endif + +/** LWIP_TIMEVAL_PRIVATE: if you want to use the struct timeval provided + * by your system, set this to 0 and include in cc.h */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 1 +#endif + +#if LWIP_TIMEVAL_PRIVATE +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; +#endif /* LWIP_TIMEVAL_PRIVATE */ + +#define lwip_socket_init() /* Compatibility define, no init needed. */ +void lwip_socket_thread_init(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */ +void lwip_socket_thread_cleanup(void); /* LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */ + +#if LWIP_COMPAT_SOCKETS == 2 +/* This helps code parsers/code completion by not having the COMPAT functions as defines */ +#define lwip_accept accept +#define lwip_bind bind +#define lwip_shutdown shutdown +#define lwip_getpeername getpeername +#define lwip_getsockname getsockname +#define lwip_setsockopt setsockopt +#define lwip_getsockopt getsockopt +#define lwip_close closesocket +#define lwip_connect connect +#define lwip_listen listen +#define lwip_recv recv +#define lwip_recvmsg recvmsg +#define lwip_recvfrom recvfrom +#define lwip_send send +#define lwip_sendmsg sendmsg +#define lwip_sendto sendto +#define lwip_socket socket +#if LWIP_SOCKET_SELECT +#define lwip_select select +#endif +#if LWIP_SOCKET_POLL +#define lwip_poll poll +#endif +#define lwip_ioctl ioctlsocket +#define lwip_inet_ntop inet_ntop +#define lwip_inet_pton inet_pton + +#if LWIP_POSIX_SOCKETS_IO_NAMES +#define lwip_read read +#define lwip_readv readv +#define lwip_write write +#define lwip_writev writev +#undef lwip_close +#define lwip_close close +#define closesocket(s) close(s) +int fcntl(int s, int cmd, ...); +#undef lwip_ioctl +#define lwip_ioctl ioctl +#define ioctlsocket ioctl +#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ +#endif /* LWIP_COMPAT_SOCKETS == 2 */ + +int lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen); +int lwip_bind(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_shutdown(int s, int how); +int lwip_getpeername (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockname (int s, struct sockaddr *name, socklen_t *namelen); +int lwip_getsockopt (int s, int level, int optname, void *optval, socklen_t *optlen); +int lwip_setsockopt (int s, int level, int optname, const void *optval, socklen_t optlen); + int lwip_close(int s); +int lwip_connect(int s, const struct sockaddr *name, socklen_t namelen); +int lwip_listen(int s, int backlog); +ssize_t lwip_recv(int s, void *mem, size_t len, int flags); +ssize_t lwip_read(int s, void *mem, size_t len); +ssize_t lwip_readv(int s, const struct iovec *iov, int iovcnt); +ssize_t lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen); +ssize_t lwip_recvmsg(int s, struct msghdr *message, int flags); +ssize_t lwip_send(int s, const void *dataptr, size_t size, int flags); +ssize_t lwip_sendmsg(int s, const struct msghdr *message, int flags); +ssize_t lwip_sendto(int s, const void *dataptr, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen); +int lwip_socket(int domain, int type, int protocol); +ssize_t lwip_write(int s, const void *dataptr, size_t size); +ssize_t lwip_writev(int s, const struct iovec *iov, int iovcnt); +#if LWIP_SOCKET_SELECT +int lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout); +#endif +#if LWIP_SOCKET_POLL +int lwip_poll(struct pollfd *fds, nfds_t nfds, int timeout); +#endif +int lwip_ioctl(int s, long cmd, void *argp); +int lwip_fcntl(int s, int cmd, int val); +const char *lwip_inet_ntop(int af, const void *src, char *dst, socklen_t size); +int lwip_inet_pton(int af, const char *src, void *dst); + +#if LWIP_COMPAT_SOCKETS +#if LWIP_COMPAT_SOCKETS != 2 +/** @ingroup socket */ +#define accept(s,addr,addrlen) lwip_accept(s,addr,addrlen) +/** @ingroup socket */ +#define bind(s,name,namelen) lwip_bind(s,name,namelen) +/** @ingroup socket */ +#define shutdown(s,how) lwip_shutdown(s,how) +/** @ingroup socket */ +#define getpeername(s,name,namelen) lwip_getpeername(s,name,namelen) +/** @ingroup socket */ +#define getsockname(s,name,namelen) lwip_getsockname(s,name,namelen) +/** @ingroup socket */ +#define setsockopt(s,level,optname,opval,optlen) lwip_setsockopt(s,level,optname,opval,optlen) +/** @ingroup socket */ +#define getsockopt(s,level,optname,opval,optlen) lwip_getsockopt(s,level,optname,opval,optlen) +/** @ingroup socket */ +#define closesocket(s) lwip_close(s) +/** @ingroup socket */ +#define connect(s,name,namelen) lwip_connect(s,name,namelen) +/** @ingroup socket */ +#define listen(s,backlog) lwip_listen(s,backlog) +/** @ingroup socket */ +#define recv(s,mem,len,flags) lwip_recv(s,mem,len,flags) +/** @ingroup socket */ +#define recvmsg(s,message,flags) lwip_recvmsg(s,message,flags) +/** @ingroup socket */ +#define recvfrom(s,mem,len,flags,from,fromlen) lwip_recvfrom(s,mem,len,flags,from,fromlen) +/** @ingroup socket */ +#define send(s,dataptr,size,flags) lwip_send(s,dataptr,size,flags) +/** @ingroup socket */ +#define sendmsg(s,message,flags) lwip_sendmsg(s,message,flags) +/** @ingroup socket */ +#define sendto(s,dataptr,size,flags,to,tolen) lwip_sendto(s,dataptr,size,flags,to,tolen) +/** @ingroup socket */ +#define socket(domain,type,protocol) lwip_socket(domain,type,protocol) +#if LWIP_SOCKET_SELECT +/** @ingroup socket */ +#define select(maxfdp1,readset,writeset,exceptset,timeout) lwip_select(maxfdp1,readset,writeset,exceptset,timeout) +#endif +#if LWIP_SOCKET_POLL +/** @ingroup socket */ +#define poll(fds,nfds,timeout) lwip_poll(fds,nfds,timeout) +#endif +/** @ingroup socket */ +#define ioctlsocket(s,cmd,argp) lwip_ioctl(s,cmd,argp) +/** @ingroup socket */ +#define inet_ntop(af,src,dst,size) lwip_inet_ntop(af,src,dst,size) +/** @ingroup socket */ +#define inet_pton(af,src,dst) lwip_inet_pton(af,src,dst) + +#if LWIP_POSIX_SOCKETS_IO_NAMES +/** @ingroup socket */ +#define read(s,mem,len) lwip_read(s,mem,len) +/** @ingroup socket */ +#define readv(s,iov,iovcnt) lwip_readv(s,iov,iovcnt) +/** @ingroup socket */ +#define write(s,dataptr,len) lwip_write(s,dataptr,len) +/** @ingroup socket */ +#define writev(s,iov,iovcnt) lwip_writev(s,iov,iovcnt) +/** @ingroup socket */ +#define close(s) lwip_close(s) +/** @ingroup socket */ +#define fcntl(s,cmd,val) lwip_fcntl(s,cmd,val) +/** @ingroup socket */ +#define ioctl(s,cmd,argp) lwip_ioctl(s,cmd,argp) +#endif /* LWIP_POSIX_SOCKETS_IO_NAMES */ +#endif /* LWIP_COMPAT_SOCKETS != 2 */ + +#endif /* LWIP_COMPAT_SOCKETS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_SOCKET */ + +#endif /* LWIP_HDR_SOCKETS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/stats.h b/Middlewares/Third_Party/LwIP/src/include/lwip/stats.h new file mode 100644 index 0000000..b570dba --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/stats.h @@ -0,0 +1,491 @@ +/** + * @file + * Statistics API (to be used from TCPIP thread) + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_STATS_H +#define LWIP_HDR_STATS_H + +#include "lwip/opt.h" + +#include "lwip/mem.h" +#include "lwip/memp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_STATS + +#ifndef LWIP_STATS_LARGE +#define LWIP_STATS_LARGE 0 +#endif + +#if LWIP_STATS_LARGE +#define STAT_COUNTER u32_t +#define STAT_COUNTER_F U32_F +#else +#define STAT_COUNTER u16_t +#define STAT_COUNTER_F U16_F +#endif + +/** Protocol related stats */ +struct stats_proto { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER fw; /* Forwarded packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER rterr; /* Routing error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER opterr; /* Error in options. */ + STAT_COUNTER err; /* Misc error. */ + STAT_COUNTER cachehit; +}; + +/** IGMP stats */ +struct stats_igmp { + STAT_COUNTER xmit; /* Transmitted packets. */ + STAT_COUNTER recv; /* Received packets. */ + STAT_COUNTER drop; /* Dropped packets. */ + STAT_COUNTER chkerr; /* Checksum error. */ + STAT_COUNTER lenerr; /* Invalid length error. */ + STAT_COUNTER memerr; /* Out of memory error. */ + STAT_COUNTER proterr; /* Protocol error. */ + STAT_COUNTER rx_v1; /* Received v1 frames. */ + STAT_COUNTER rx_group; /* Received group-specific queries. */ + STAT_COUNTER rx_general; /* Received general queries. */ + STAT_COUNTER rx_report; /* Received reports. */ + STAT_COUNTER tx_join; /* Sent joins. */ + STAT_COUNTER tx_leave; /* Sent leaves. */ + STAT_COUNTER tx_report; /* Sent reports. */ +}; + +/** Memory stats */ +struct stats_mem { +#if defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY + const char *name; +#endif /* defined(LWIP_DEBUG) || LWIP_STATS_DISPLAY */ + STAT_COUNTER err; + mem_size_t avail; + mem_size_t used; + mem_size_t max; + STAT_COUNTER illegal; +}; + +/** System element stats */ +struct stats_syselem { + STAT_COUNTER used; + STAT_COUNTER max; + STAT_COUNTER err; +}; + +/** System stats */ +struct stats_sys { + struct stats_syselem sem; + struct stats_syselem mutex; + struct stats_syselem mbox; +}; + +/** SNMP MIB2 stats */ +struct stats_mib2 { + /* IP */ + u32_t ipinhdrerrors; + u32_t ipinaddrerrors; + u32_t ipinunknownprotos; + u32_t ipindiscards; + u32_t ipindelivers; + u32_t ipoutrequests; + u32_t ipoutdiscards; + u32_t ipoutnoroutes; + u32_t ipreasmoks; + u32_t ipreasmfails; + u32_t ipfragoks; + u32_t ipfragfails; + u32_t ipfragcreates; + u32_t ipreasmreqds; + u32_t ipforwdatagrams; + u32_t ipinreceives; + + /* TCP */ + u32_t tcpactiveopens; + u32_t tcppassiveopens; + u32_t tcpattemptfails; + u32_t tcpestabresets; + u32_t tcpoutsegs; + u32_t tcpretranssegs; + u32_t tcpinsegs; + u32_t tcpinerrs; + u32_t tcpoutrsts; + + /* UDP */ + u32_t udpindatagrams; + u32_t udpnoports; + u32_t udpinerrors; + u32_t udpoutdatagrams; + + /* ICMP */ + u32_t icmpinmsgs; + u32_t icmpinerrors; + u32_t icmpindestunreachs; + u32_t icmpintimeexcds; + u32_t icmpinparmprobs; + u32_t icmpinsrcquenchs; + u32_t icmpinredirects; + u32_t icmpinechos; + u32_t icmpinechoreps; + u32_t icmpintimestamps; + u32_t icmpintimestampreps; + u32_t icmpinaddrmasks; + u32_t icmpinaddrmaskreps; + u32_t icmpoutmsgs; + u32_t icmpouterrors; + u32_t icmpoutdestunreachs; + u32_t icmpouttimeexcds; + u32_t icmpoutechos; /* can be incremented by user application ('ping') */ + u32_t icmpoutechoreps; +}; + +/** + * @ingroup netif_mib2 + * SNMP MIB2 interface stats + */ +struct stats_mib2_netif_ctrs { + /** The total number of octets received on the interface, including framing characters */ + u32_t ifinoctets; + /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were + * not addressed to a multicast or broadcast address at this sub-layer */ + u32_t ifinucastpkts; + /** The number of packets, delivered by this sub-layer to a higher (sub-)layer, which were + * addressed to a multicast or broadcast address at this sub-layer */ + u32_t ifinnucastpkts; + /** The number of inbound packets which were chosen to be discarded even though no errors had + * been detected to prevent their being deliverable to a higher-layer protocol. One possible + * reason for discarding such a packet could be to free up buffer space */ + u32_t ifindiscards; + /** For packet-oriented interfaces, the number of inbound packets that contained errors + * preventing them from being deliverable to a higher-layer protocol. For character- + * oriented or fixed-length interfaces, the number of inbound transmission units that + * contained errors preventing them from being deliverable to a higher-layer protocol. */ + u32_t ifinerrors; + /** For packet-oriented interfaces, the number of packets received via the interface which + * were discarded because of an unknown or unsupported protocol. For character-oriented + * or fixed-length interfaces that support protocol multiplexing the number of transmission + * units received via the interface which were discarded because of an unknown or unsupported + * protocol. For any interface that does not support protocol multiplexing, this counter will + * always be 0 */ + u32_t ifinunknownprotos; + /** The total number of octets transmitted out of the interface, including framing characters. */ + u32_t ifoutoctets; + /** The total number of packets that higher-level protocols requested be transmitted, and + * which were not addressed to a multicast or broadcast address at this sub-layer, including + * those that were discarded or not sent. */ + u32_t ifoutucastpkts; + /** The total number of packets that higher-level protocols requested be transmitted, and which + * were addressed to a multicast or broadcast address at this sub-layer, including + * those that were discarded or not sent. */ + u32_t ifoutnucastpkts; + /** The number of outbound packets which were chosen to be discarded even though no errors had + * been detected to prevent their being transmitted. One possible reason for discarding + * such a packet could be to free up buffer space. */ + u32_t ifoutdiscards; + /** For packet-oriented interfaces, the number of outbound packets that could not be transmitted + * because of errors. For character-oriented or fixed-length interfaces, the number of outbound + * transmission units that could not be transmitted because of errors. */ + u32_t ifouterrors; +}; + +/** lwIP stats container */ +struct stats_ { +#if LINK_STATS + /** Link level */ + struct stats_proto link; +#endif +#if ETHARP_STATS + /** ARP */ + struct stats_proto etharp; +#endif +#if IPFRAG_STATS + /** Fragmentation */ + struct stats_proto ip_frag; +#endif +#if IP_STATS + /** IP */ + struct stats_proto ip; +#endif +#if ICMP_STATS + /** ICMP */ + struct stats_proto icmp; +#endif +#if IGMP_STATS + /** IGMP */ + struct stats_igmp igmp; +#endif +#if UDP_STATS + /** UDP */ + struct stats_proto udp; +#endif +#if TCP_STATS + /** TCP */ + struct stats_proto tcp; +#endif +#if MEM_STATS + /** Heap */ + struct stats_mem mem; +#endif +#if MEMP_STATS + /** Internal memory pools */ + struct stats_mem *memp[MEMP_MAX]; +#endif +#if SYS_STATS + /** System */ + struct stats_sys sys; +#endif +#if IP6_STATS + /** IPv6 */ + struct stats_proto ip6; +#endif +#if ICMP6_STATS + /** ICMP6 */ + struct stats_proto icmp6; +#endif +#if IP6_FRAG_STATS + /** IPv6 fragmentation */ + struct stats_proto ip6_frag; +#endif +#if MLD6_STATS + /** Multicast listener discovery */ + struct stats_igmp mld6; +#endif +#if ND6_STATS + /** Neighbor discovery */ + struct stats_proto nd6; +#endif +#if MIB2_STATS + /** SNMP MIB2 */ + struct stats_mib2 mib2; +#endif +}; + +/** Global variable containing lwIP internal statistics. Add this to your debugger's watchlist. */ +extern struct stats_ lwip_stats; + +/** Init statistics */ +void stats_init(void); + +#define STATS_INC(x) ++lwip_stats.x +#define STATS_DEC(x) --lwip_stats.x +#define STATS_INC_USED(x, y, type) do { lwip_stats.x.used = (type)(lwip_stats.x.used + y); \ + if (lwip_stats.x.max < lwip_stats.x.used) { \ + lwip_stats.x.max = lwip_stats.x.used; \ + } \ + } while(0) +#define STATS_GET(x) lwip_stats.x +#else /* LWIP_STATS */ +#define stats_init() +#define STATS_INC(x) +#define STATS_DEC(x) +#define STATS_INC_USED(x, y, type) +#endif /* LWIP_STATS */ + +#if TCP_STATS +#define TCP_STATS_INC(x) STATS_INC(x) +#define TCP_STATS_DISPLAY() stats_display_proto(&lwip_stats.tcp, "TCP") +#else +#define TCP_STATS_INC(x) +#define TCP_STATS_DISPLAY() +#endif + +#if UDP_STATS +#define UDP_STATS_INC(x) STATS_INC(x) +#define UDP_STATS_DISPLAY() stats_display_proto(&lwip_stats.udp, "UDP") +#else +#define UDP_STATS_INC(x) +#define UDP_STATS_DISPLAY() +#endif + +#if ICMP_STATS +#define ICMP_STATS_INC(x) STATS_INC(x) +#define ICMP_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp, "ICMP") +#else +#define ICMP_STATS_INC(x) +#define ICMP_STATS_DISPLAY() +#endif + +#if IGMP_STATS +#define IGMP_STATS_INC(x) STATS_INC(x) +#define IGMP_STATS_DISPLAY() stats_display_igmp(&lwip_stats.igmp, "IGMP") +#else +#define IGMP_STATS_INC(x) +#define IGMP_STATS_DISPLAY() +#endif + +#if IP_STATS +#define IP_STATS_INC(x) STATS_INC(x) +#define IP_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip, "IP") +#else +#define IP_STATS_INC(x) +#define IP_STATS_DISPLAY() +#endif + +#if IPFRAG_STATS +#define IPFRAG_STATS_INC(x) STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip_frag, "IP_FRAG") +#else +#define IPFRAG_STATS_INC(x) +#define IPFRAG_STATS_DISPLAY() +#endif + +#if ETHARP_STATS +#define ETHARP_STATS_INC(x) STATS_INC(x) +#define ETHARP_STATS_DISPLAY() stats_display_proto(&lwip_stats.etharp, "ETHARP") +#else +#define ETHARP_STATS_INC(x) +#define ETHARP_STATS_DISPLAY() +#endif + +#if LINK_STATS +#define LINK_STATS_INC(x) STATS_INC(x) +#define LINK_STATS_DISPLAY() stats_display_proto(&lwip_stats.link, "LINK") +#else +#define LINK_STATS_INC(x) +#define LINK_STATS_DISPLAY() +#endif + +#if MEM_STATS +#define MEM_STATS_AVAIL(x, y) lwip_stats.mem.x = y +#define MEM_STATS_INC(x) STATS_INC(mem.x) +#define MEM_STATS_INC_USED(x, y) STATS_INC_USED(mem, y, mem_size_t) +#define MEM_STATS_DEC_USED(x, y) lwip_stats.mem.x = (mem_size_t)((lwip_stats.mem.x) - (y)) +#define MEM_STATS_DISPLAY() stats_display_mem(&lwip_stats.mem, "HEAP") +#else +#define MEM_STATS_AVAIL(x, y) +#define MEM_STATS_INC(x) +#define MEM_STATS_INC_USED(x, y) +#define MEM_STATS_DEC_USED(x, y) +#define MEM_STATS_DISPLAY() +#endif + + #if MEMP_STATS +#define MEMP_STATS_DEC(x, i) STATS_DEC(memp[i]->x) +#define MEMP_STATS_DISPLAY(i) stats_display_memp(lwip_stats.memp[i], i) +#define MEMP_STATS_GET(x, i) STATS_GET(memp[i]->x) + #else +#define MEMP_STATS_DEC(x, i) +#define MEMP_STATS_DISPLAY(i) +#define MEMP_STATS_GET(x, i) 0 +#endif + +#if SYS_STATS +#define SYS_STATS_INC(x) STATS_INC(sys.x) +#define SYS_STATS_DEC(x) STATS_DEC(sys.x) +#define SYS_STATS_INC_USED(x) STATS_INC_USED(sys.x, 1, STAT_COUNTER) +#define SYS_STATS_DISPLAY() stats_display_sys(&lwip_stats.sys) +#else +#define SYS_STATS_INC(x) +#define SYS_STATS_DEC(x) +#define SYS_STATS_INC_USED(x) +#define SYS_STATS_DISPLAY() +#endif + +#if IP6_STATS +#define IP6_STATS_INC(x) STATS_INC(x) +#define IP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6, "IPv6") +#else +#define IP6_STATS_INC(x) +#define IP6_STATS_DISPLAY() +#endif + +#if ICMP6_STATS +#define ICMP6_STATS_INC(x) STATS_INC(x) +#define ICMP6_STATS_DISPLAY() stats_display_proto(&lwip_stats.icmp6, "ICMPv6") +#else +#define ICMP6_STATS_INC(x) +#define ICMP6_STATS_DISPLAY() +#endif + +#if IP6_FRAG_STATS +#define IP6_FRAG_STATS_INC(x) STATS_INC(x) +#define IP6_FRAG_STATS_DISPLAY() stats_display_proto(&lwip_stats.ip6_frag, "IPv6 FRAG") +#else +#define IP6_FRAG_STATS_INC(x) +#define IP6_FRAG_STATS_DISPLAY() +#endif + +#if MLD6_STATS +#define MLD6_STATS_INC(x) STATS_INC(x) +#define MLD6_STATS_DISPLAY() stats_display_igmp(&lwip_stats.mld6, "MLDv1") +#else +#define MLD6_STATS_INC(x) +#define MLD6_STATS_DISPLAY() +#endif + +#if ND6_STATS +#define ND6_STATS_INC(x) STATS_INC(x) +#define ND6_STATS_DISPLAY() stats_display_proto(&lwip_stats.nd6, "ND") +#else +#define ND6_STATS_INC(x) +#define ND6_STATS_DISPLAY() +#endif + +#if MIB2_STATS +#define MIB2_STATS_INC(x) STATS_INC(x) +#else +#define MIB2_STATS_INC(x) +#endif + +/* Display of statistics */ +#if LWIP_STATS_DISPLAY +void stats_display(void); +void stats_display_proto(struct stats_proto *proto, const char *name); +void stats_display_igmp(struct stats_igmp *igmp, const char *name); +void stats_display_mem(struct stats_mem *mem, const char *name); +void stats_display_memp(struct stats_mem *mem, int index); +void stats_display_sys(struct stats_sys *sys); +#else /* LWIP_STATS_DISPLAY */ +#define stats_display() +#define stats_display_proto(proto, name) +#define stats_display_igmp(igmp, name) +#define stats_display_mem(mem, name) +#define stats_display_memp(mem, index) +#define stats_display_sys(sys) +#endif /* LWIP_STATS_DISPLAY */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_STATS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/sys.h b/Middlewares/Third_Party/LwIP/src/include/lwip/sys.h new file mode 100644 index 0000000..168e465 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/sys.h @@ -0,0 +1,560 @@ +/** + * @file + * OS abstraction layer + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + */ + +#ifndef LWIP_HDR_SYS_H +#define LWIP_HDR_SYS_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if NO_SYS + +/* For a totally minimal and standalone system, we provide null + definitions of the sys_ functions. */ +typedef u8_t sys_sem_t; +typedef u8_t sys_mutex_t; +typedef u8_t sys_mbox_t; + +#define sys_sem_new(s, c) ERR_OK +#define sys_sem_signal(s) +#define sys_sem_wait(s) +#define sys_arch_sem_wait(s,t) +#define sys_sem_free(s) +#define sys_sem_valid(s) 0 +#define sys_sem_valid_val(s) 0 +#define sys_sem_set_invalid(s) +#define sys_sem_set_invalid_val(s) +#define sys_mutex_new(mu) ERR_OK +#define sys_mutex_lock(mu) +#define sys_mutex_unlock(mu) +#define sys_mutex_free(mu) +#define sys_mutex_valid(mu) 0 +#define sys_mutex_set_invalid(mu) +#define sys_mbox_new(m, s) ERR_OK +#define sys_mbox_fetch(m,d) +#define sys_mbox_tryfetch(m,d) +#define sys_mbox_post(m,d) +#define sys_mbox_trypost(m,d) +#define sys_mbox_free(m) +#define sys_mbox_valid(m) +#define sys_mbox_valid_val(m) +#define sys_mbox_set_invalid(m) +#define sys_mbox_set_invalid_val(m) + +#define sys_thread_new(n,t,a,s,p) + +#define sys_msleep(t) + +#else /* NO_SYS */ + +/** Return code for timeouts from sys_arch_mbox_fetch and sys_arch_sem_wait */ +#define SYS_ARCH_TIMEOUT 0xffffffffUL + +/** sys_mbox_tryfetch() returns SYS_MBOX_EMPTY if appropriate. + * For now we use the same magic value, but we allow this to change in future. + */ +#define SYS_MBOX_EMPTY SYS_ARCH_TIMEOUT + +#include "lwip/err.h" +#include "arch/sys_arch.h" + +/** Function prototype for thread functions */ +typedef void (*lwip_thread_fn)(void *arg); + +/* Function prototypes for functions to be implemented by platform ports + (in sys_arch.c) */ + +/* Mutex functions: */ + +/** Define LWIP_COMPAT_MUTEX if the port has no mutexes and binary semaphores + should be used instead */ +#ifndef LWIP_COMPAT_MUTEX +#define LWIP_COMPAT_MUTEX 0 +#endif + +#if LWIP_COMPAT_MUTEX +/* for old ports that don't have mutexes: define them to binary semaphores */ +#define sys_mutex_t sys_sem_t +#define sys_mutex_new(mutex) sys_sem_new(mutex, 1) +#define sys_mutex_lock(mutex) sys_sem_wait(mutex) +#define sys_mutex_unlock(mutex) sys_sem_signal(mutex) +#define sys_mutex_free(mutex) sys_sem_free(mutex) +#define sys_mutex_valid(mutex) sys_sem_valid(mutex) +#define sys_mutex_set_invalid(mutex) sys_sem_set_invalid(mutex) + +#else /* LWIP_COMPAT_MUTEX */ + +/** + * @ingroup sys_mutex + * Create a new mutex. + * Note that mutexes are expected to not be taken recursively by the lwIP code, + * so both implementation types (recursive or non-recursive) should work. + * The mutex is allocated to the memory that 'mutex' + * points to (which can be both a pointer or the actual OS structure). + * If the mutex has been created, ERR_OK should be returned. Returning any + * other error will provide a hint what went wrong, but except for assertions, + * no real error handling is implemented. + * + * @param mutex pointer to the mutex to create + * @return ERR_OK if successful, another err_t otherwise + */ +err_t sys_mutex_new(sys_mutex_t *mutex); +/** + * @ingroup sys_mutex + * Blocks the thread until the mutex can be grabbed. + * @param mutex the mutex to lock + */ +void sys_mutex_lock(sys_mutex_t *mutex); +/** + * @ingroup sys_mutex + * Releases the mutex previously locked through 'sys_mutex_lock()'. + * @param mutex the mutex to unlock + */ +void sys_mutex_unlock(sys_mutex_t *mutex); +/** + * @ingroup sys_mutex + * Deallocates a mutex. + * @param mutex the mutex to delete + */ +void sys_mutex_free(sys_mutex_t *mutex); +#ifndef sys_mutex_valid +/** + * @ingroup sys_mutex + * Returns 1 if the mutes is valid, 0 if it is not valid. + * When using pointers, a simple way is to check the pointer for != NULL. + * When directly using OS structures, implementing this may be more complex. + * This may also be a define, in which case the function is not prototyped. + */ +int sys_mutex_valid(sys_mutex_t *mutex); +#endif +#ifndef sys_mutex_set_invalid +/** + * @ingroup sys_mutex + * Invalidate a mutex so that sys_mutex_valid() returns 0. + * ATTENTION: This does NOT mean that the mutex shall be deallocated: + * sys_mutex_free() is always called before calling this function! + * This may also be a define, in which case the function is not prototyped. + */ +void sys_mutex_set_invalid(sys_mutex_t *mutex); +#endif +#endif /* LWIP_COMPAT_MUTEX */ + +/* Semaphore functions: */ + +/** + * @ingroup sys_sem + * Create a new semaphore + * Creates a new semaphore. The semaphore is allocated to the memory that 'sem' + * points to (which can be both a pointer or the actual OS structure). + * The "count" argument specifies the initial state of the semaphore (which is + * either 0 or 1). + * If the semaphore has been created, ERR_OK should be returned. Returning any + * other error will provide a hint what went wrong, but except for assertions, + * no real error handling is implemented. + * + * @param sem pointer to the semaphore to create + * @param count initial count of the semaphore + * @return ERR_OK if successful, another err_t otherwise + */ +err_t sys_sem_new(sys_sem_t *sem, u8_t count); +/** + * @ingroup sys_sem + * Signals a semaphore + * @param sem the semaphore to signal + */ +void sys_sem_signal(sys_sem_t *sem); +/** + * @ingroup sys_sem + * Blocks the thread while waiting for the semaphore to be signaled. If the + * "timeout" argument is non-zero, the thread should only be blocked for the + * specified time (measured in milliseconds). If the "timeout" argument is zero, + * the thread should be blocked until the semaphore is signalled. + * + * The return value is SYS_ARCH_TIMEOUT if the semaphore wasn't signaled within + * the specified time or any other value if it was signaled (with or without + * waiting). + * Notice that lwIP implements a function with a similar name, + * sys_sem_wait(), that uses the sys_arch_sem_wait() function. + * + * @param sem the semaphore to wait for + * @param timeout timeout in milliseconds to wait (0 = wait forever) + * @return SYS_ARCH_TIMEOUT on timeout, any other value on success + */ +u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout); +/** + * @ingroup sys_sem + * Deallocates a semaphore. + * @param sem semaphore to delete + */ +void sys_sem_free(sys_sem_t *sem); +/** Wait for a semaphore - forever/no timeout */ +#define sys_sem_wait(sem) sys_arch_sem_wait(sem, 0) +#ifndef sys_sem_valid +/** + * @ingroup sys_sem + * Returns 1 if the semaphore is valid, 0 if it is not valid. + * When using pointers, a simple way is to check the pointer for != NULL. + * When directly using OS structures, implementing this may be more complex. + * This may also be a define, in which case the function is not prototyped. + */ +int sys_sem_valid(sys_sem_t *sem); +#endif +#ifndef sys_sem_set_invalid +/** + * @ingroup sys_sem + * Invalidate a semaphore so that sys_sem_valid() returns 0. + * ATTENTION: This does NOT mean that the semaphore shall be deallocated: + * sys_sem_free() is always called before calling this function! + * This may also be a define, in which case the function is not prototyped. + */ +void sys_sem_set_invalid(sys_sem_t *sem); +#endif +#ifndef sys_sem_valid_val +/** + * Same as sys_sem_valid() but taking a value, not a pointer + */ +#define sys_sem_valid_val(sem) sys_sem_valid(&(sem)) +#endif +#ifndef sys_sem_set_invalid_val +/** + * Same as sys_sem_set_invalid() but taking a value, not a pointer + */ +#define sys_sem_set_invalid_val(sem) sys_sem_set_invalid(&(sem)) +#endif + +#ifndef sys_msleep +/** + * @ingroup sys_misc + * Sleep for specified number of ms + */ +void sys_msleep(u32_t ms); /* only has a (close to) 1 ms resolution. */ +#endif + +/* Mailbox functions. */ + +/** + * @ingroup sys_mbox + * Creates an empty mailbox for maximum "size" elements. Elements stored + * in mailboxes are pointers. You have to define macros "_MBOX_SIZE" + * in your lwipopts.h, or ignore this parameter in your implementation + * and use a default size. + * If the mailbox has been created, ERR_OK should be returned. Returning any + * other error will provide a hint what went wrong, but except for assertions, + * no real error handling is implemented. + * + * @param mbox pointer to the mbox to create + * @param size (minimum) number of messages in this mbox + * @return ERR_OK if successful, another err_t otherwise + */ +err_t sys_mbox_new(sys_mbox_t *mbox, int size); +/** + * @ingroup sys_mbox + * Post a message to an mbox - may not fail + * -> blocks if full, only to be used from tasks NOT from ISR! + * + * @param mbox mbox to posts the message + * @param msg message to post (ATTENTION: can be NULL) + */ +void sys_mbox_post(sys_mbox_t *mbox, void *msg); +/** + * @ingroup sys_mbox + * Try to post a message to an mbox - may fail if full. + * Can be used from ISR (if the sys arch layer allows this). + * Returns ERR_MEM if it is full, else, ERR_OK if the "msg" is posted. + * + * @param mbox mbox to posts the message + * @param msg message to post (ATTENTION: can be NULL) + */ +err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg); +/** + * @ingroup sys_mbox + * Try to post a message to an mbox - may fail if full. + * To be be used from ISR. + * Returns ERR_MEM if it is full, else, ERR_OK if the "msg" is posted. + * + * @param mbox mbox to posts the message + * @param msg message to post (ATTENTION: can be NULL) + */ +err_t sys_mbox_trypost_fromisr(sys_mbox_t *mbox, void *msg); +/** + * @ingroup sys_mbox + * Blocks the thread until a message arrives in the mailbox, but does + * not block the thread longer than "timeout" milliseconds (similar to + * the sys_arch_sem_wait() function). If "timeout" is 0, the thread should + * be blocked until a message arrives. The "msg" argument is a result + * parameter that is set by the function (i.e., by doing "*msg = + * ptr"). The "msg" parameter maybe NULL to indicate that the message + * should be dropped. + * The return values are the same as for the sys_arch_sem_wait() function: + * SYS_ARCH_TIMEOUT if there was a timeout, any other value if a messages + * is received. + * + * Note that a function with a similar name, sys_mbox_fetch(), is + * implemented by lwIP. + * + * @param mbox mbox to get a message from + * @param msg pointer where the message is stored + * @param timeout maximum time (in milliseconds) to wait for a message (0 = wait forever) + * @return SYS_ARCH_TIMEOUT on timeout, any other value if a message has been received + */ +u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout); +/* Allow port to override with a macro, e.g. special timeout for sys_arch_mbox_fetch() */ +#ifndef sys_arch_mbox_tryfetch +/** + * @ingroup sys_mbox + * This is similar to sys_arch_mbox_fetch, however if a message is not + * present in the mailbox, it immediately returns with the code + * SYS_MBOX_EMPTY. On success 0 is returned. + * To allow for efficient implementations, this can be defined as a + * function-like macro in sys_arch.h instead of a normal function. For + * example, a naive implementation could be: + * \#define sys_arch_mbox_tryfetch(mbox,msg) sys_arch_mbox_fetch(mbox,msg,1) + * although this would introduce unnecessary delays. + * + * @param mbox mbox to get a message from + * @param msg pointer where the message is stored + * @return 0 (milliseconds) if a message has been received + * or SYS_MBOX_EMPTY if the mailbox is empty + */ +u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg); +#endif +/** + * For now, we map straight to sys_arch implementation. + */ +#define sys_mbox_tryfetch(mbox, msg) sys_arch_mbox_tryfetch(mbox, msg) +/** + * @ingroup sys_mbox + * Deallocates a mailbox. If there are messages still present in the + * mailbox when the mailbox is deallocated, it is an indication of a + * programming error in lwIP and the developer should be notified. + * + * @param mbox mbox to delete + */ +void sys_mbox_free(sys_mbox_t *mbox); +#define sys_mbox_fetch(mbox, msg) sys_arch_mbox_fetch(mbox, msg, 0) +#ifndef sys_mbox_valid +/** + * @ingroup sys_mbox + * Returns 1 if the mailbox is valid, 0 if it is not valid. + * When using pointers, a simple way is to check the pointer for != NULL. + * When directly using OS structures, implementing this may be more complex. + * This may also be a define, in which case the function is not prototyped. + */ +int sys_mbox_valid(sys_mbox_t *mbox); +#endif +#ifndef sys_mbox_set_invalid +/** + * @ingroup sys_mbox + * Invalidate a mailbox so that sys_mbox_valid() returns 0. + * ATTENTION: This does NOT mean that the mailbox shall be deallocated: + * sys_mbox_free() is always called before calling this function! + * This may also be a define, in which case the function is not prototyped. + */ +void sys_mbox_set_invalid(sys_mbox_t *mbox); +#endif +#ifndef sys_mbox_valid_val +/** + * Same as sys_mbox_valid() but taking a value, not a pointer + */ +#define sys_mbox_valid_val(mbox) sys_mbox_valid(&(mbox)) +#endif +#ifndef sys_mbox_set_invalid_val +/** + * Same as sys_mbox_set_invalid() but taking a value, not a pointer + */ +#define sys_mbox_set_invalid_val(mbox) sys_mbox_set_invalid(&(mbox)) +#endif + + +/** + * @ingroup sys_misc + * The only thread function: + * Starts a new thread named "name" with priority "prio" that will begin its + * execution in the function "thread()". The "arg" argument will be passed as an + * argument to the thread() function. The stack size to used for this thread is + * the "stacksize" parameter. The id of the new thread is returned. Both the id + * and the priority are system dependent. + * ATTENTION: although this function returns a value, it MUST NOT FAIL (ports have to assert this!) + * + * @param name human-readable name for the thread (used for debugging purposes) + * @param thread thread-function + * @param arg parameter passed to 'thread' + * @param stacksize stack size in bytes for the new thread (may be ignored by ports) + * @param prio priority of the new thread (may be ignored by ports) */ +sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio); + +#endif /* NO_SYS */ + +/** + * @ingroup sys_misc + * sys_init() must be called before anything else. + * Initialize the sys_arch layer. + */ +void sys_init(void); + +#ifndef sys_jiffies +/** + * Ticks/jiffies since power up. + */ +u32_t sys_jiffies(void); +#endif + +/** + * @ingroup sys_time + * Returns the current time in milliseconds, + * may be the same as sys_jiffies or at least based on it. + * Don't care for wraparound, this is only used for time diffs. + * Not implementing this function means you cannot use some modules (e.g. TCP + * timestamps, internal timeouts for NO_SYS==1). + */ +u32_t sys_now(void); + +/* Critical Region Protection */ +/* These functions must be implemented in the sys_arch.c file. + In some implementations they can provide a more light-weight protection + mechanism than using semaphores. Otherwise semaphores can be used for + implementation */ +#ifndef SYS_ARCH_PROTECT +/** SYS_LIGHTWEIGHT_PROT + * define SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection + * for certain critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#if SYS_LIGHTWEIGHT_PROT + +/** + * @ingroup sys_prot + * SYS_ARCH_DECL_PROTECT + * declare a protection variable. This macro will default to defining a variable of + * type sys_prot_t. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h. + */ +#define SYS_ARCH_DECL_PROTECT(lev) sys_prot_t lev +/** + * @ingroup sys_prot + * SYS_ARCH_PROTECT + * Perform a "fast" protect. This could be implemented by + * disabling interrupts for an embedded system or by using a semaphore or + * mutex. The implementation should allow calling SYS_ARCH_PROTECT when + * already protected. The old protection level is returned in the variable + * "lev". This macro will default to calling the sys_arch_protect() function + * which should be implemented in sys_arch.c. If a particular port needs a + * different implementation, then this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_PROTECT(lev) lev = sys_arch_protect() +/** + * @ingroup sys_prot + * SYS_ARCH_UNPROTECT + * Perform a "fast" set of the protection level to "lev". This could be + * implemented by setting the interrupt level to "lev" within the MACRO or by + * using a semaphore or mutex. This macro will default to calling the + * sys_arch_unprotect() function which should be implemented in + * sys_arch.c. If a particular port needs a different implementation, then + * this macro may be defined in sys_arch.h + */ +#define SYS_ARCH_UNPROTECT(lev) sys_arch_unprotect(lev) +sys_prot_t sys_arch_protect(void); +void sys_arch_unprotect(sys_prot_t pval); + +#else + +#define SYS_ARCH_DECL_PROTECT(lev) +#define SYS_ARCH_PROTECT(lev) +#define SYS_ARCH_UNPROTECT(lev) + +#endif /* SYS_LIGHTWEIGHT_PROT */ + +#endif /* SYS_ARCH_PROTECT */ + +/* + * Macros to set/get and increase/decrease variables in a thread-safe way. + * Use these for accessing variable that are used from more than one thread. + */ + +#ifndef SYS_ARCH_INC +#define SYS_ARCH_INC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var += val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_INC */ + +#ifndef SYS_ARCH_DEC +#define SYS_ARCH_DEC(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var -= val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_DEC */ + +#ifndef SYS_ARCH_GET +#define SYS_ARCH_GET(var, ret) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + ret = var; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_GET */ + +#ifndef SYS_ARCH_SET +#define SYS_ARCH_SET(var, val) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + var = val; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_SET */ + +#ifndef SYS_ARCH_LOCKED +#define SYS_ARCH_LOCKED(code) do { \ + SYS_ARCH_DECL_PROTECT(old_level); \ + SYS_ARCH_PROTECT(old_level); \ + code; \ + SYS_ARCH_UNPROTECT(old_level); \ + } while(0) +#endif /* SYS_ARCH_LOCKED */ + + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_SYS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h new file mode 100644 index 0000000..daf7599 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/tcp.h @@ -0,0 +1,500 @@ +/** + * @file + * TCP API (to be used from TCPIP thread)\n + * See also @ref tcp_raw + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_TCP_H +#define LWIP_HDR_TCP_H + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/tcpbase.h" +#include "lwip/mem.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/icmp.h" +#include "lwip/err.h" +#include "lwip/ip6.h" +#include "lwip/ip6_addr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct tcp_pcb; +struct tcp_pcb_listen; + +/** Function prototype for tcp accept callback functions. Called when a new + * connection can be accepted on a listening pcb. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param newpcb The new connection pcb + * @param err An error code if there has been an error accepting. + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_accept_fn)(void *arg, struct tcp_pcb *newpcb, err_t err); + +/** Function prototype for tcp receive callback functions. Called when data has + * been received. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb which received data + * @param p The received data (or NULL when the connection has been closed!) + * @param err An error code if there has been an error receiving + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_recv_fn)(void *arg, struct tcp_pcb *tpcb, + struct pbuf *p, err_t err); + +/** Function prototype for tcp sent callback functions. Called when sent data has + * been acknowledged by the remote side. Use it to free corresponding resources. + * This also means that the pcb has now space available to send new data. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb for which data has been acknowledged + * @param len The amount of bytes acknowledged + * @return ERR_OK: try to send some data by calling tcp_output + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_sent_fn)(void *arg, struct tcp_pcb *tpcb, + u16_t len); + +/** Function prototype for tcp poll callback functions. Called periodically as + * specified by @see tcp_poll. + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb tcp pcb + * @return ERR_OK: try to send some data by calling tcp_output + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + */ +typedef err_t (*tcp_poll_fn)(void *arg, struct tcp_pcb *tpcb); + +/** Function prototype for tcp error callback functions. Called when the pcb + * receives a RST or is unexpectedly closed for any other reason. + * + * @note The corresponding pcb is already freed when this callback is called! + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param err Error code to indicate why the pcb has been closed + * ERR_ABRT: aborted through tcp_abort or by a TCP timer + * ERR_RST: the connection was reset by the remote host + */ +typedef void (*tcp_err_fn)(void *arg, err_t err); + +/** Function prototype for tcp connected callback functions. Called when a pcb + * is connected to the remote side after initiating a connection attempt by + * calling tcp_connect(). + * + * @param arg Additional argument to pass to the callback function (@see tcp_arg()) + * @param tpcb The connection pcb which is connected + * @param err An unused error code, always ERR_OK currently ;-) @todo! + * Only return ERR_ABRT if you have called tcp_abort from within the + * callback function! + * + * @note When a connection attempt fails, the error callback is currently called! + */ +typedef err_t (*tcp_connected_fn)(void *arg, struct tcp_pcb *tpcb, err_t err); + +#if LWIP_WND_SCALE +#define RCV_WND_SCALE(pcb, wnd) (((wnd) >> (pcb)->rcv_scale)) +#define SND_WND_SCALE(pcb, wnd) (((wnd) << (pcb)->snd_scale)) +#define TCPWND16(x) ((u16_t)LWIP_MIN((x), 0xFFFF)) +#define TCP_WND_MAX(pcb) ((tcpwnd_size_t)(((pcb)->flags & TF_WND_SCALE) ? TCP_WND : TCPWND16(TCP_WND))) +#else +#define RCV_WND_SCALE(pcb, wnd) (wnd) +#define SND_WND_SCALE(pcb, wnd) (wnd) +#define TCPWND16(x) (x) +#define TCP_WND_MAX(pcb) TCP_WND +#endif +/* Increments a tcpwnd_size_t and holds at max value rather than rollover */ +#define TCP_WND_INC(wnd, inc) do { \ + if ((tcpwnd_size_t)(wnd + inc) >= wnd) { \ + wnd = (tcpwnd_size_t)(wnd + inc); \ + } else { \ + wnd = (tcpwnd_size_t)-1; \ + } \ + } while(0) + +#if LWIP_TCP_SACK_OUT +/** SACK ranges to include in ACK packets. + * SACK entry is invalid if left==right. */ +struct tcp_sack_range { + /** Left edge of the SACK: the first acknowledged sequence number. */ + u32_t left; + /** Right edge of the SACK: the last acknowledged sequence number +1 (so first NOT acknowledged). */ + u32_t right; +}; +#endif /* LWIP_TCP_SACK_OUT */ + +/** Function prototype for deallocation of arguments. Called *just before* the + * pcb is freed, so don't expect to be able to do anything with this pcb! + * + * @param id ext arg id (allocated via @ref tcp_ext_arg_alloc_id) + * @param data pointer to the data (set via @ref tcp_ext_arg_set before) + */ +typedef void (*tcp_extarg_callback_pcb_destroyed_fn)(u8_t id, void *data); + +/** Function prototype to transition arguments from a listening pcb to an accepted pcb + * + * @param id ext arg id (allocated via @ref tcp_ext_arg_alloc_id) + * @param lpcb the listening pcb accepting a connection + * @param cpcb the newly allocated connection pcb + * @return ERR_OK if OK, any error if connection should be dropped + */ +typedef err_t (*tcp_extarg_callback_passive_open_fn)(u8_t id, struct tcp_pcb_listen *lpcb, struct tcp_pcb *cpcb); + +/** A table of callback functions that is invoked for ext arguments */ +struct tcp_ext_arg_callbacks { + /** @ref tcp_extarg_callback_pcb_destroyed_fn */ + tcp_extarg_callback_pcb_destroyed_fn destroy; + /** @ref tcp_extarg_callback_passive_open_fn */ + tcp_extarg_callback_passive_open_fn passive_open; +}; + +#define LWIP_TCP_PCB_NUM_EXT_ARG_ID_INVALID 0xFF + +#if LWIP_TCP_PCB_NUM_EXT_ARGS +/* This is the structure for ext args in tcp pcbs (used as array) */ +struct tcp_pcb_ext_args { + const struct tcp_ext_arg_callbacks *callbacks; + void *data; +}; +/* This is a helper define to prevent zero size arrays if disabled */ +#define TCP_PCB_EXTARGS struct tcp_pcb_ext_args ext_args[LWIP_TCP_PCB_NUM_EXT_ARGS]; +#else +#define TCP_PCB_EXTARGS +#endif + +typedef u16_t tcpflags_t; +#define TCP_ALLFLAGS 0xffffU + +/** + * members common to struct tcp_pcb and struct tcp_listen_pcb + */ +#define TCP_PCB_COMMON(type) \ + type *next; /* for the linked list */ \ + void *callback_arg; \ + TCP_PCB_EXTARGS \ + enum tcp_state state; /* TCP state */ \ + u8_t prio; \ + /* ports are in host byte order */ \ + u16_t local_port + + +/** the TCP protocol control block for listening pcbs */ +struct tcp_pcb_listen { +/** Common members of all PCB types */ + IP_PCB; +/** Protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb_listen); + +#if LWIP_CALLBACK_API + /* Function to call when a listener has been connected. */ + tcp_accept_fn accept; +#endif /* LWIP_CALLBACK_API */ + +#if TCP_LISTEN_BACKLOG + u8_t backlog; + u8_t accepts_pending; +#endif /* TCP_LISTEN_BACKLOG */ +}; + + +/** the TCP protocol control block */ +struct tcp_pcb { +/** common PCB members */ + IP_PCB; +/** protocol specific PCB members */ + TCP_PCB_COMMON(struct tcp_pcb); + + /* ports are in host byte order */ + u16_t remote_port; + + tcpflags_t flags; +#define TF_ACK_DELAY 0x01U /* Delayed ACK. */ +#define TF_ACK_NOW 0x02U /* Immediate ACK. */ +#define TF_INFR 0x04U /* In fast recovery. */ +#define TF_CLOSEPEND 0x08U /* If this is set, tcp_close failed to enqueue the FIN (retried in tcp_tmr) */ +#define TF_RXCLOSED 0x10U /* rx closed by tcp_shutdown */ +#define TF_FIN 0x20U /* Connection was closed locally (FIN segment enqueued). */ +#define TF_NODELAY 0x40U /* Disable Nagle algorithm */ +#define TF_NAGLEMEMERR 0x80U /* nagle enabled, memerr, try to output to prevent delayed ACK to happen */ +#if LWIP_WND_SCALE +#define TF_WND_SCALE 0x0100U /* Window Scale option enabled */ +#endif +#if TCP_LISTEN_BACKLOG +#define TF_BACKLOGPEND 0x0200U /* If this is set, a connection pcb has increased the backlog on its listener */ +#endif +#if LWIP_TCP_TIMESTAMPS +#define TF_TIMESTAMP 0x0400U /* Timestamp option enabled */ +#endif +#define TF_RTO 0x0800U /* RTO timer has fired, in-flight data moved to unsent and being retransmitted */ +#if LWIP_TCP_SACK_OUT +#define TF_SACK 0x1000U /* Selective ACKs enabled */ +#endif + + /* the rest of the fields are in host byte order + as we have to do some math with them */ + + /* Timers */ + u8_t polltmr, pollinterval; + u8_t last_timer; + u32_t tmr; + + /* receiver variables */ + u32_t rcv_nxt; /* next seqno expected */ + tcpwnd_size_t rcv_wnd; /* receiver window available */ + tcpwnd_size_t rcv_ann_wnd; /* receiver window to announce */ + u32_t rcv_ann_right_edge; /* announced right edge of window */ + +#if LWIP_TCP_SACK_OUT + /* SACK ranges to include in ACK packets (entry is invalid if left==right) */ + struct tcp_sack_range rcv_sacks[LWIP_TCP_MAX_SACK_NUM]; +#define LWIP_TCP_SACK_VALID(pcb, idx) ((pcb)->rcv_sacks[idx].left != (pcb)->rcv_sacks[idx].right) +#endif /* LWIP_TCP_SACK_OUT */ + + /* Retransmission timer. */ + s16_t rtime; + + u16_t mss; /* maximum segment size */ + + /* RTT (round trip time) estimation variables */ + u32_t rttest; /* RTT estimate in 500ms ticks */ + u32_t rtseq; /* sequence number being timed */ + s16_t sa, sv; /* @see "Congestion Avoidance and Control" by Van Jacobson and Karels */ + + s16_t rto; /* retransmission time-out (in ticks of TCP_SLOW_INTERVAL) */ + u8_t nrtx; /* number of retransmissions */ + + /* fast retransmit/recovery */ + u8_t dupacks; + u32_t lastack; /* Highest acknowledged seqno. */ + + /* congestion avoidance/control variables */ + tcpwnd_size_t cwnd; + tcpwnd_size_t ssthresh; + + /* first byte following last rto byte */ + u32_t rto_end; + + /* sender variables */ + u32_t snd_nxt; /* next new seqno to be sent */ + u32_t snd_wl1, snd_wl2; /* Sequence and acknowledgement numbers of last + window update. */ + u32_t snd_lbb; /* Sequence number of next byte to be buffered. */ + tcpwnd_size_t snd_wnd; /* sender window */ + tcpwnd_size_t snd_wnd_max; /* the maximum sender window announced by the remote host */ + + tcpwnd_size_t snd_buf; /* Available buffer space for sending (in bytes). */ +#define TCP_SNDQUEUELEN_OVERFLOW (0xffffU-3) + u16_t snd_queuelen; /* Number of pbufs currently in the send buffer. */ + +#if TCP_OVERSIZE + /* Extra bytes available at the end of the last pbuf in unsent. */ + u16_t unsent_oversize; +#endif /* TCP_OVERSIZE */ + + tcpwnd_size_t bytes_acked; + + /* These are ordered by sequence number: */ + struct tcp_seg *unsent; /* Unsent (queued) segments. */ + struct tcp_seg *unacked; /* Sent but unacknowledged segments. */ +#if TCP_QUEUE_OOSEQ + struct tcp_seg *ooseq; /* Received out of sequence segments. */ +#endif /* TCP_QUEUE_OOSEQ */ + + struct pbuf *refused_data; /* Data previously received but not yet taken by upper layer */ + +#if LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG + struct tcp_pcb_listen* listener; +#endif /* LWIP_CALLBACK_API || TCP_LISTEN_BACKLOG */ + +#if LWIP_CALLBACK_API + /* Function to be called when more send buffer space is available. */ + tcp_sent_fn sent; + /* Function to be called when (in-sequence) data has arrived. */ + tcp_recv_fn recv; + /* Function to be called when a connection has been set up. */ + tcp_connected_fn connected; + /* Function which is called periodically. */ + tcp_poll_fn poll; + /* Function to be called whenever a fatal error occurs. */ + tcp_err_fn errf; +#endif /* LWIP_CALLBACK_API */ + +#if LWIP_TCP_TIMESTAMPS + u32_t ts_lastacksent; + u32_t ts_recent; +#endif /* LWIP_TCP_TIMESTAMPS */ + + /* idle time before KEEPALIVE is sent */ + u32_t keep_idle; +#if LWIP_TCP_KEEPALIVE + u32_t keep_intvl; + u32_t keep_cnt; +#endif /* LWIP_TCP_KEEPALIVE */ + + /* Persist timer counter */ + u8_t persist_cnt; + /* Persist timer back-off */ + u8_t persist_backoff; + /* Number of persist probes */ + u8_t persist_probe; + + /* KEEPALIVE counter */ + u8_t keep_cnt_sent; + +#if LWIP_WND_SCALE + u8_t snd_scale; + u8_t rcv_scale; +#endif +}; + +#if LWIP_EVENT_API + +enum lwip_event { + LWIP_EVENT_ACCEPT, + LWIP_EVENT_SENT, + LWIP_EVENT_RECV, + LWIP_EVENT_CONNECTED, + LWIP_EVENT_POLL, + LWIP_EVENT_ERR +}; + +err_t lwip_tcp_event(void *arg, struct tcp_pcb *pcb, + enum lwip_event, + struct pbuf *p, + u16_t size, + err_t err); + +#endif /* LWIP_EVENT_API */ + +/* Application program's interface: */ +struct tcp_pcb * tcp_new (void); +struct tcp_pcb * tcp_new_ip_type (u8_t type); + +void tcp_arg (struct tcp_pcb *pcb, void *arg); +#if LWIP_CALLBACK_API +void tcp_recv (struct tcp_pcb *pcb, tcp_recv_fn recv); +void tcp_sent (struct tcp_pcb *pcb, tcp_sent_fn sent); +void tcp_err (struct tcp_pcb *pcb, tcp_err_fn err); +void tcp_accept (struct tcp_pcb *pcb, tcp_accept_fn accept); +#endif /* LWIP_CALLBACK_API */ +void tcp_poll (struct tcp_pcb *pcb, tcp_poll_fn poll, u8_t interval); + +#define tcp_set_flags(pcb, set_flags) do { (pcb)->flags = (tcpflags_t)((pcb)->flags | (set_flags)); } while(0) +#define tcp_clear_flags(pcb, clr_flags) do { (pcb)->flags = (tcpflags_t)((pcb)->flags & (tcpflags_t)(~(clr_flags) & TCP_ALLFLAGS)); } while(0) +#define tcp_is_flag_set(pcb, flag) (((pcb)->flags & (flag)) != 0) + +#if LWIP_TCP_TIMESTAMPS +#define tcp_mss(pcb) (((pcb)->flags & TF_TIMESTAMP) ? ((pcb)->mss - 12) : (pcb)->mss) +#else /* LWIP_TCP_TIMESTAMPS */ +/** @ingroup tcp_raw */ +#define tcp_mss(pcb) ((pcb)->mss) +#endif /* LWIP_TCP_TIMESTAMPS */ +/** @ingroup tcp_raw */ +#define tcp_sndbuf(pcb) (TCPWND16((pcb)->snd_buf)) +/** @ingroup tcp_raw */ +#define tcp_sndqueuelen(pcb) ((pcb)->snd_queuelen) +/** @ingroup tcp_raw */ +#define tcp_nagle_disable(pcb) tcp_set_flags(pcb, TF_NODELAY) +/** @ingroup tcp_raw */ +#define tcp_nagle_enable(pcb) tcp_clear_flags(pcb, TF_NODELAY) +/** @ingroup tcp_raw */ +#define tcp_nagle_disabled(pcb) tcp_is_flag_set(pcb, TF_NODELAY) + +#if TCP_LISTEN_BACKLOG +#define tcp_backlog_set(pcb, new_backlog) do { \ + LWIP_ASSERT("pcb->state == LISTEN (called for wrong pcb?)", (pcb)->state == LISTEN); \ + ((struct tcp_pcb_listen *)(pcb))->backlog = ((new_backlog) ? (new_backlog) : 1); } while(0) +void tcp_backlog_delayed(struct tcp_pcb* pcb); +void tcp_backlog_accepted(struct tcp_pcb* pcb); +#else /* TCP_LISTEN_BACKLOG */ +#define tcp_backlog_set(pcb, new_backlog) +#define tcp_backlog_delayed(pcb) +#define tcp_backlog_accepted(pcb) +#endif /* TCP_LISTEN_BACKLOG */ +#define tcp_accepted(pcb) do { LWIP_UNUSED_ARG(pcb); } while(0) /* compatibility define, not needed any more */ + +void tcp_recved (struct tcp_pcb *pcb, u16_t len); +err_t tcp_bind (struct tcp_pcb *pcb, const ip_addr_t *ipaddr, + u16_t port); +void tcp_bind_netif(struct tcp_pcb *pcb, const struct netif *netif); +err_t tcp_connect (struct tcp_pcb *pcb, const ip_addr_t *ipaddr, + u16_t port, tcp_connected_fn connected); + +struct tcp_pcb * tcp_listen_with_backlog_and_err(struct tcp_pcb *pcb, u8_t backlog, err_t *err); +struct tcp_pcb * tcp_listen_with_backlog(struct tcp_pcb *pcb, u8_t backlog); +/** @ingroup tcp_raw */ +#define tcp_listen(pcb) tcp_listen_with_backlog(pcb, TCP_DEFAULT_LISTEN_BACKLOG) + +void tcp_abort (struct tcp_pcb *pcb); +err_t tcp_close (struct tcp_pcb *pcb); +err_t tcp_shutdown(struct tcp_pcb *pcb, int shut_rx, int shut_tx); + +err_t tcp_write (struct tcp_pcb *pcb, const void *dataptr, u16_t len, + u8_t apiflags); + +void tcp_setprio (struct tcp_pcb *pcb, u8_t prio); + +err_t tcp_output (struct tcp_pcb *pcb); + +err_t tcp_tcp_get_tcp_addrinfo(struct tcp_pcb *pcb, int local, ip_addr_t *addr, u16_t *port); + +#define tcp_dbg_get_tcp_state(pcb) ((pcb)->state) + +/* for compatibility with older implementation */ +#define tcp_new_ip6() tcp_new_ip_type(IPADDR_TYPE_V6) + +#if LWIP_TCP_PCB_NUM_EXT_ARGS +u8_t tcp_ext_arg_alloc_id(void); +void tcp_ext_arg_set_callbacks(struct tcp_pcb *pcb, uint8_t id, const struct tcp_ext_arg_callbacks * const callbacks); +void tcp_ext_arg_set(struct tcp_pcb *pcb, uint8_t id, void *arg); +void *tcp_ext_arg_get(const struct tcp_pcb *pcb, uint8_t id); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* LWIP_HDR_TCP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h b/Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h new file mode 100644 index 0000000..0023074 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/tcpbase.h @@ -0,0 +1,88 @@ +/** + * @file + * Base TCP API definitions shared by TCP and ALTCP\n + * See also @ref tcp_raw + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_TCPBASE_H +#define LWIP_HDR_TCPBASE_H + +#include "lwip/opt.h" + +#if LWIP_TCP /* don't build if not configured for use in lwipopts.h */ + +#ifdef __cplusplus +extern "C" { +#endif + + +#if LWIP_WND_SCALE +typedef u32_t tcpwnd_size_t; +#else +typedef u16_t tcpwnd_size_t; +#endif + +enum tcp_state { + CLOSED = 0, + LISTEN = 1, + SYN_SENT = 2, + SYN_RCVD = 3, + ESTABLISHED = 4, + FIN_WAIT_1 = 5, + FIN_WAIT_2 = 6, + CLOSE_WAIT = 7, + CLOSING = 8, + LAST_ACK = 9, + TIME_WAIT = 10 +}; +/* ATTENTION: this depends on state number ordering! */ +#define TCP_STATE_IS_CLOSING(state) ((state) >= FIN_WAIT_1) + +/* Flags for "apiflags" parameter in tcp_write */ +#define TCP_WRITE_FLAG_COPY 0x01 +#define TCP_WRITE_FLAG_MORE 0x02 + +#define TCP_PRIO_MIN 1 +#define TCP_PRIO_NORMAL 64 +#define TCP_PRIO_MAX 127 + +const char* tcp_debug_state_str(enum tcp_state s); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_TCP */ + +#endif /* LWIP_HDR_TCPBASE_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h b/Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h new file mode 100644 index 0000000..0b8880a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/tcpip.h @@ -0,0 +1,113 @@ +/** + * @file + * Functions to sync with TCPIP thread + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_TCPIP_H +#define LWIP_HDR_TCPIP_H + +#include "lwip/opt.h" + +#if !NO_SYS /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/err.h" +#include "lwip/timeouts.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_TCPIP_CORE_LOCKING +/** The global semaphore to lock the stack. */ +extern sys_mutex_t lock_tcpip_core; +#if !defined LOCK_TCPIP_CORE || defined __DOXYGEN__ +/** Lock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */ +#define LOCK_TCPIP_CORE() sys_mutex_lock(&lock_tcpip_core) +/** Unlock lwIP core mutex (needs @ref LWIP_TCPIP_CORE_LOCKING 1) */ +#define UNLOCK_TCPIP_CORE() sys_mutex_unlock(&lock_tcpip_core) +#endif /* LOCK_TCPIP_CORE */ +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define LOCK_TCPIP_CORE() +#define UNLOCK_TCPIP_CORE() +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +struct pbuf; +struct netif; + +/** Function prototype for the init_done function passed to tcpip_init */ +typedef void (*tcpip_init_done_fn)(void *arg); +/** Function prototype for functions passed to tcpip_callback() */ +typedef void (*tcpip_callback_fn)(void *ctx); + +/* Forward declarations */ +struct tcpip_callback_msg; + +void tcpip_init(tcpip_init_done_fn tcpip_init_done, void *arg); + +err_t tcpip_inpkt(struct pbuf *p, struct netif *inp, netif_input_fn input_fn); +err_t tcpip_input(struct pbuf *p, struct netif *inp); + +err_t tcpip_try_callback(tcpip_callback_fn function, void *ctx); +err_t tcpip_callback(tcpip_callback_fn function, void *ctx); +/** @ingroup lwip_os + * @deprecated use tcpip_try_callback() or tcpip_callback() instead + */ +#define tcpip_callback_with_block(function, ctx, block) ((block != 0)? tcpip_callback(function, ctx) : tcpip_try_callback(function, ctx)) + +struct tcpip_callback_msg* tcpip_callbackmsg_new(tcpip_callback_fn function, void *ctx); +void tcpip_callbackmsg_delete(struct tcpip_callback_msg* msg); +err_t tcpip_callbackmsg_trycallback(struct tcpip_callback_msg* msg); +err_t tcpip_callbackmsg_trycallback_fromisr(struct tcpip_callback_msg* msg); + +/* free pbufs or heap memory from another context without blocking */ +err_t pbuf_free_callback(struct pbuf *p); +err_t mem_free_callback(void *m); + +#if LWIP_TCPIP_TIMEOUT && LWIP_TIMERS +err_t tcpip_timeout(u32_t msecs, sys_timeout_handler h, void *arg); +err_t tcpip_untimeout(sys_timeout_handler h, void *arg); +#endif /* LWIP_TCPIP_TIMEOUT && LWIP_TIMERS */ + +#ifdef TCPIP_THREAD_TEST +int tcpip_thread_poll_one(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !NO_SYS */ + +#endif /* LWIP_HDR_TCPIP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h b/Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h new file mode 100644 index 0000000..b601f9e --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/timeouts.h @@ -0,0 +1,128 @@ +/** + * @file + * Timer implementations + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_TIMEOUTS_H +#define LWIP_HDR_TIMEOUTS_H + +#include "lwip/opt.h" +#include "lwip/err.h" +#if !NO_SYS +#include "lwip/sys.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef LWIP_DEBUG_TIMERNAMES +#ifdef LWIP_DEBUG +#define LWIP_DEBUG_TIMERNAMES SYS_DEBUG +#else /* LWIP_DEBUG */ +#define LWIP_DEBUG_TIMERNAMES 0 +#endif /* LWIP_DEBUG*/ +#endif + +/** Returned by sys_timeouts_sleeptime() to indicate there is no timer, so we + * can sleep forever. + */ +#define SYS_TIMEOUTS_SLEEPTIME_INFINITE 0xFFFFFFFF + +/** Function prototype for a stack-internal timer function that has to be + * called at a defined interval */ +typedef void (* lwip_cyclic_timer_handler)(void); + +/** This struct contains information about a stack-internal timer function + that has to be called at a defined interval */ +struct lwip_cyclic_timer { + u32_t interval_ms; + lwip_cyclic_timer_handler handler; +#if LWIP_DEBUG_TIMERNAMES + const char* handler_name; +#endif /* LWIP_DEBUG_TIMERNAMES */ +}; + +/** This array contains all stack-internal cyclic timers. To get the number of + * timers, use lwip_num_cyclic_timers */ +extern const struct lwip_cyclic_timer lwip_cyclic_timers[]; +/** Array size of lwip_cyclic_timers[] */ +extern const int lwip_num_cyclic_timers; + +#if LWIP_TIMERS + +/** Function prototype for a timeout callback function. Register such a function + * using sys_timeout(). + * + * @param arg Additional argument to pass to the function - set up by sys_timeout() + */ +typedef void (* sys_timeout_handler)(void *arg); + +struct sys_timeo { + struct sys_timeo *next; + u32_t time; + sys_timeout_handler h; + void *arg; +#if LWIP_DEBUG_TIMERNAMES + const char* handler_name; +#endif /* LWIP_DEBUG_TIMERNAMES */ +}; + +void sys_timeouts_init(void); + +#if LWIP_DEBUG_TIMERNAMES +void sys_timeout_debug(u32_t msecs, sys_timeout_handler handler, void *arg, const char* handler_name); +#define sys_timeout(msecs, handler, arg) sys_timeout_debug(msecs, handler, arg, #handler) +#else /* LWIP_DEBUG_TIMERNAMES */ +void sys_timeout(u32_t msecs, sys_timeout_handler handler, void *arg); +#endif /* LWIP_DEBUG_TIMERNAMES */ + +void sys_untimeout(sys_timeout_handler handler, void *arg); +void sys_restart_timeouts(void); +void sys_check_timeouts(void); +u32_t sys_timeouts_sleeptime(void); + +#if LWIP_TESTMODE +struct sys_timeo** sys_timeouts_get_next_timeout(void); +void lwip_cyclic_timer(void *arg); +#endif + +#endif /* LWIP_TIMERS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_TIMEOUTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/lwip/udp.h b/Middlewares/Third_Party/LwIP/src/include/lwip/udp.h new file mode 100644 index 0000000..b1c78e5 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/lwip/udp.h @@ -0,0 +1,195 @@ +/** + * @file + * UDP API (to be used from TCPIP thread)\n + * See also @ref udp_raw + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_UDP_H +#define LWIP_HDR_UDP_H + +#include "lwip/opt.h" + +#if LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/ip_addr.h" +#include "lwip/ip.h" +#include "lwip/ip6_addr.h" +#include "lwip/prot/udp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDP_FLAGS_NOCHKSUM 0x01U +#define UDP_FLAGS_UDPLITE 0x02U +#define UDP_FLAGS_CONNECTED 0x04U +#define UDP_FLAGS_MULTICAST_LOOP 0x08U + +struct udp_pcb; + +/** Function prototype for udp pcb receive callback functions + * addr and port are in same byte order as in the pcb + * The callback is responsible for freeing the pbuf + * if it's not used any more. + * + * ATTENTION: Be aware that 'addr' might point into the pbuf 'p' so freeing this pbuf + * can make 'addr' invalid, too. + * + * @param arg user supplied argument (udp_pcb.recv_arg) + * @param pcb the udp_pcb which received data + * @param p the packet buffer that was received + * @param addr the remote IP address from which the packet was received + * @param port the remote port from which the packet was received + */ +typedef void (*udp_recv_fn)(void *arg, struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr, u16_t port); + +/** the UDP protocol control block */ +struct udp_pcb { +/** Common members of all PCB types */ + IP_PCB; + +/* Protocol specific PCB members */ + + struct udp_pcb *next; + + u8_t flags; + /** ports are in host byte order */ + u16_t local_port, remote_port; + +#if LWIP_MULTICAST_TX_OPTIONS +#if LWIP_IPV4 + /** outgoing network interface for multicast packets, by IPv4 address (if not 'any') */ + ip4_addr_t mcast_ip4; +#endif /* LWIP_IPV4 */ + /** outgoing network interface for multicast packets, by interface index (if nonzero) */ + u8_t mcast_ifindex; + /** TTL for outgoing multicast packets */ + u8_t mcast_ttl; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + +#if LWIP_UDPLITE + /** used for UDP_LITE only */ + u16_t chksum_len_rx, chksum_len_tx; +#endif /* LWIP_UDPLITE */ + + /** receive callback function */ + udp_recv_fn recv; + /** user-supplied argument for the recv callback */ + void *recv_arg; +}; +/* udp_pcbs export for external reference (e.g. SNMP agent) */ +extern struct udp_pcb *udp_pcbs; + +/* The following functions is the application layer interface to the + UDP code. */ +struct udp_pcb * udp_new (void); +struct udp_pcb * udp_new_ip_type(u8_t type); +void udp_remove (struct udp_pcb *pcb); +err_t udp_bind (struct udp_pcb *pcb, const ip_addr_t *ipaddr, + u16_t port); +void udp_bind_netif (struct udp_pcb *pcb, const struct netif* netif); +err_t udp_connect (struct udp_pcb *pcb, const ip_addr_t *ipaddr, + u16_t port); +void udp_disconnect (struct udp_pcb *pcb); +void udp_recv (struct udp_pcb *pcb, udp_recv_fn recv, + void *recv_arg); +err_t udp_sendto_if (struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, + struct netif *netif); +err_t udp_sendto_if_src(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, + struct netif *netif, const ip_addr_t *src_ip); +err_t udp_sendto (struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port); +err_t udp_send (struct udp_pcb *pcb, struct pbuf *p); + +#if LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP +err_t udp_sendto_if_chksum(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, + struct netif *netif, u8_t have_chksum, + u16_t chksum); +err_t udp_sendto_chksum(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, + u8_t have_chksum, u16_t chksum); +err_t udp_send_chksum(struct udp_pcb *pcb, struct pbuf *p, + u8_t have_chksum, u16_t chksum); +err_t udp_sendto_if_src_chksum(struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *dst_ip, u16_t dst_port, struct netif *netif, + u8_t have_chksum, u16_t chksum, const ip_addr_t *src_ip); +#endif /* LWIP_CHECKSUM_ON_COPY && CHECKSUM_GEN_UDP */ + +#define udp_flags(pcb) ((pcb)->flags) +#define udp_setflags(pcb, f) ((pcb)->flags = (f)) + +#define udp_set_flags(pcb, set_flags) do { (pcb)->flags = (u8_t)((pcb)->flags | (set_flags)); } while(0) +#define udp_clear_flags(pcb, clr_flags) do { (pcb)->flags = (u8_t)((pcb)->flags & (u8_t)(~(clr_flags) & 0xff)); } while(0) +#define udp_is_flag_set(pcb, flag) (((pcb)->flags & (flag)) != 0) + +/* The following functions are the lower layer interface to UDP. */ +void udp_input (struct pbuf *p, struct netif *inp); + +void udp_init (void); + +/* for compatibility with older implementation */ +#define udp_new_ip6() udp_new_ip_type(IPADDR_TYPE_V6) + +#if LWIP_MULTICAST_TX_OPTIONS +#if LWIP_IPV4 +#define udp_set_multicast_netif_addr(pcb, ip4addr) ip4_addr_copy((pcb)->mcast_ip4, *(ip4addr)) +#define udp_get_multicast_netif_addr(pcb) (&(pcb)->mcast_ip4) +#endif /* LWIP_IPV4 */ +#define udp_set_multicast_netif_index(pcb, idx) ((pcb)->mcast_ifindex = (idx)) +#define udp_get_multicast_netif_index(pcb) ((pcb)->mcast_ifindex) +#define udp_set_multicast_ttl(pcb, value) ((pcb)->mcast_ttl = (value)) +#define udp_get_multicast_ttl(pcb) ((pcb)->mcast_ttl) +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + +#if UDP_DEBUG +void udp_debug_print(struct udp_hdr *udphdr); +#else +#define udp_debug_print(udphdr) +#endif + +void udp_netif_ip_addr_changed(const ip_addr_t* old_addr, const ip_addr_t* new_addr); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_UDP */ + +#endif /* LWIP_HDR_UDP_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h b/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h new file mode 100644 index 0000000..f4f8cf1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif.h @@ -0,0 +1,127 @@ +/** + * @file + * lwIP netif implementing an IEEE 802.1D MAC Bridge + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_NETIF_BRIDGEIF_H +#define LWIP_HDR_NETIF_BRIDGEIF_H + +#include "netif/bridgeif_opts.h" + +#include "lwip/err.h" +#include "lwip/prot/ethernet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct netif; + +#if (BRIDGEIF_MAX_PORTS < 0) || (BRIDGEIF_MAX_PORTS >= 64) +#error BRIDGEIF_MAX_PORTS must be [1..63] +#elif BRIDGEIF_MAX_PORTS < 8 +typedef u8_t bridgeif_portmask_t; +#elif BRIDGEIF_MAX_PORTS < 16 +typedef u16_t bridgeif_portmask_t; +#elif BRIDGEIF_MAX_PORTS < 32 +typedef u32_t bridgeif_portmask_t; +#elif BRIDGEIF_MAX_PORTS < 64 +typedef u64_t bridgeif_portmask_t; +#endif + +#define BR_FLOOD ((bridgeif_portmask_t)-1) + +/** @ingroup bridgeif + * Initialisation data for @ref bridgeif_init. + * An instance of this type must be passed as parameter 'state' to @ref netif_add + * when the bridge is added. + */ +typedef struct bridgeif_initdata_s { + /** MAC address of the bridge (cannot use the netif's addresses) */ + struct eth_addr ethaddr; + /** Maximum number of ports in the bridge (ports are stored in an array, this + influences memory allocated for netif->state of the bridge netif). */ + u8_t max_ports; + /** Maximum number of dynamic/learning entries in the bridge's forwarding database. + In the default implementation, this controls memory consumption only. */ + u16_t max_fdb_dynamic_entries; + /** Maximum number of static forwarding entries. Influences memory consumption! */ + u16_t max_fdb_static_entries; +} bridgeif_initdata_t; + +/** @ingroup bridgeif + * Use this for constant initialization of a bridgeif_initdat_t + * (ethaddr must be passed as ETH_ADDR()) + */ +#define BRIDGEIF_INITDATA1(max_ports, max_fdb_dynamic_entries, max_fdb_static_entries, ethaddr) {ethaddr, max_ports, max_fdb_dynamic_entries, max_fdb_static_entries} +/** @ingroup bridgeif + * Use this for constant initialization of a bridgeif_initdat_t + * (each byte of ethaddr must be passed) + */ +#define BRIDGEIF_INITDATA2(max_ports, max_fdb_dynamic_entries, max_fdb_static_entries, e0, e1, e2, e3, e4, e5) {{e0, e1, e2, e3, e4, e5}, max_ports, max_fdb_dynamic_entries, max_fdb_static_entries} + +err_t bridgeif_init(struct netif *netif); +err_t bridgeif_add_port(struct netif *bridgeif, struct netif *portif); +err_t bridgeif_fdb_add(struct netif *bridgeif, const struct eth_addr *addr, bridgeif_portmask_t ports); +err_t bridgeif_fdb_remove(struct netif *bridgeif, const struct eth_addr *addr); + +/* FDB interface, can be replaced by own implementation */ +void bridgeif_fdb_update_src(void *fdb_ptr, struct eth_addr *src_addr, u8_t port_idx); +bridgeif_portmask_t bridgeif_fdb_get_dst_ports(void *fdb_ptr, struct eth_addr *dst_addr); +void* bridgeif_fdb_init(u16_t max_fdb_entries); + +#if BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT +#ifndef BRIDGEIF_DECL_PROTECT +/* define bridgeif protection to sys_arch_protect... */ +#include "lwip/sys.h" +#define BRIDGEIF_DECL_PROTECT(lev) SYS_ARCH_DECL_PROTECT(lev) +#define BRIDGEIF_READ_PROTECT(lev) SYS_ARCH_PROTECT(lev) +#define BRIDGEIF_READ_UNPROTECT(lev) SYS_ARCH_UNPROTECT(lev) +#define BRIDGEIF_WRITE_PROTECT(lev) +#define BRIDGEIF_WRITE_UNPROTECT(lev) +#endif +#else /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */ +#include "lwip/tcpip.h" +#define BRIDGEIF_DECL_PROTECT(lev) +#define BRIDGEIF_READ_PROTECT(lev) +#define BRIDGEIF_READ_UNPROTECT(lev) +#define BRIDGEIF_WRITE_PROTECT(lev) +#define BRIDGEIF_WRITE_UNPROTECT(lev) +#endif /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_NETIF_BRIDGEIF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h b/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h new file mode 100644 index 0000000..b85c301 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/bridgeif_opts.h @@ -0,0 +1,90 @@ +/** + * @file + * lwIP netif implementing an IEEE 802.1D MAC Bridge + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#ifndef LWIP_HDR_NETIF_BRIDGEIF_OPTS_H +#define LWIP_HDR_NETIF_BRIDGEIF_OPTS_H + +#include "lwip/opt.h" + +/** + * @defgroup bridgeif_opts Options + * @ingroup bridgeif + * @{ + */ + +/** BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT==1: set port netif's 'input' function + * to call directly into bridgeif code and on top of that, directly call into + * the selected forwarding port's 'linkoutput' function. + * This means that the bridgeif input/output path is protected from concurrent access + * but as well, *all* bridge port netif's drivers must correctly handle concurrent access! + * == 0: get into tcpip_thread for every input packet (no multithreading) + * ATTENTION: as ==0 relies on tcpip.h, the default depends on NO_SYS setting + */ +#ifndef BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT +#define BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT NO_SYS +#endif + +/** BRIDGEIF_MAX_PORTS: this is used to create a typedef used for forwarding + * bit-fields: the number of bits required is this + 1 (for the internal/cpu port) + * (63 is the maximum, resulting in an u64_t for the bit mask) + * ATTENTION: this controls the maximum number of the implementation only! + * The max. number of ports per bridge must still be passed via netif_add parameter! + */ +#ifndef BRIDGEIF_MAX_PORTS +#define BRIDGEIF_MAX_PORTS 7 +#endif + +/** BRIDGEIF_DEBUG: Enable generic debugging in bridgeif.c. */ +#ifndef BRIDGEIF_DEBUG +#define BRIDGEIF_DEBUG LWIP_DBG_OFF +#endif + +/** BRIDGEIF_DEBUG: Enable FDB debugging in bridgeif.c. */ +#ifndef BRIDGEIF_FDB_DEBUG +#define BRIDGEIF_FDB_DEBUG LWIP_DBG_OFF +#endif + +/** BRIDGEIF_DEBUG: Enable forwarding debugging in bridgeif.c. */ +#ifndef BRIDGEIF_FW_DEBUG +#define BRIDGEIF_FW_DEBUG LWIP_DBG_OFF +#endif + +/** + * @} + */ + +#endif /* LWIP_HDR_NETIF_BRIDGEIF_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/etharp.h b/Middlewares/Third_Party/LwIP/src/include/netif/etharp.h new file mode 100644 index 0000000..b536fd2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/etharp.h @@ -0,0 +1,3 @@ +/* ARP has been moved to core/ipv4, provide this #include for compatibility only */ +#include "lwip/etharp.h" +#include "netif/ethernet.h" diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h b/Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h new file mode 100644 index 0000000..49649cb --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ethernet.h @@ -0,0 +1,77 @@ +/** + * @file + * Ethernet input function - handles INCOMING ethernet level traffic + * To be used in most low-level netif implementations + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef LWIP_HDR_NETIF_ETHERNET_H +#define LWIP_HDR_NETIF_ETHERNET_H + +#include "lwip/opt.h" + +#include "lwip/pbuf.h" +#include "lwip/netif.h" +#include "lwip/prot/ethernet.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if LWIP_ARP || LWIP_ETHERNET + +/** Define this to 1 and define LWIP_ARP_FILTER_NETIF_FN(pbuf, netif, type) + * to a filter function that returns the correct netif when using multiple + * netifs on one hardware interface where the netif's low-level receive + * routine cannot decide for the correct netif (e.g. when mapping multiple + * IP addresses to one hardware interface). + */ +#ifndef LWIP_ARP_FILTER_NETIF +#define LWIP_ARP_FILTER_NETIF 0 +#endif + +err_t ethernet_input(struct pbuf *p, struct netif *netif); +err_t ethernet_output(struct netif* netif, struct pbuf* p, const struct eth_addr* src, const struct eth_addr* dst, u16_t eth_type); + +extern const struct eth_addr ethbroadcast, ethzero; + +#endif /* LWIP_ARP || LWIP_ETHERNET */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_NETIF_ETHERNET_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h b/Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h new file mode 100644 index 0000000..54e019f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ieee802154.h @@ -0,0 +1,112 @@ +/** + * @file + * Definitions for IEEE 802.15.4 MAC frames + */ + +/* + * Copyright (c) 2018 Simon Goldschmidt. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef LWIP_HDR_NETIF_IEEE802154_H +#define LWIP_HDR_NETIF_IEEE802154_H + +#include "lwip/opt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +/** General MAC frame format + * This shows the full featured header, mainly for documentation. + * Some fields are omitted or shortened to achieve frame compression. + */ +struct ieee_802154_hdr { + /** See IEEE_802154_FC_* defines */ + PACK_STRUCT_FIELD(u16_t frame_control); + /** Sequence number is omitted if IEEE_802154_FC_SEQNO_SUPPR is set in frame_control */ + PACK_STRUCT_FLD_8(u8_t sequence_number); + /** Destination PAN ID is omitted if Destination Addressing Mode is 0 */ + PACK_STRUCT_FIELD(u16_t destination_pan_id); + /** Destination Address is omitted if Destination Addressing Mode is 0 */ + PACK_STRUCT_FLD_8(u8_t destination_address[8]); + /** Source PAN ID is omitted if Source Addressing Mode is 0 + or if IEEE_802154_FC_PANID_COMPR is set in frame control*/ + PACK_STRUCT_FIELD(u16_t source_pan_id); + /** Source Address is omitted if Source Addressing Mode is 0 */ + PACK_STRUCT_FLD_8(u8_t source_address[8]); + /* The rest is variable */ +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* Addressing modes (2 bits) */ +#define IEEE_802154_ADDR_MODE_NO_ADDR 0x00 /* PAN ID and address fields are not present */ +#define IEEE_802154_ADDR_MODE_RESERVED 0x01 /* Reserved */ +#define IEEE_802154_ADDR_MODE_SHORT 0x02 /* Address field contains a short address (16 bit) */ +#define IEEE_802154_ADDR_MODE_EXT 0x03 /* Address field contains an extended address (64 bit) */ + +/* IEEE 802.15.4 Frame Control definitions (2 bytes; see IEEE 802.15.4-2015 ch. 7.2.1) */ +#define IEEE_802154_FC_FT_MASK 0x0007 /* bits 0..2: Frame Type */ +#define IEEE_802154_FC_FT_BEACON 0x00 +#define IEEE_802154_FC_FT_DATA 0x01 +#define IEEE_802154_FC_FT_ACK 0x02 +#define IEEE_802154_FC_FT_MAC_CMD 0x03 +#define IEEE_802154_FC_FT_RESERVED 0x04 +#define IEEE_802154_FC_FT_MULTIPURPOSE 0x05 +#define IEEE_802154_FC_FT_FRAG 0x06 +#define IEEE_802154_FC_FT_EXT 0x07 +#define IEEE_802154_FC_SEC_EN 0x0008 /* bit 3: Security Enabled */ +#define IEEE_802154_FC_FRAME_PEND 0x0010 /* bit 4: Frame Pending */ +#define IEEE_802154_FC_ACK_REQ 0x0020 /* bit 5: AR (ACK required) */ +#define IEEE_802154_FC_PANID_COMPR 0x0040 /* bit 6: PAN ID Compression (src and dst are equal, src PAN ID omitted) */ +#define IEEE_802154_FC_RESERVED 0x0080 +#define IEEE_802154_FC_SEQNO_SUPPR 0x0100 /* bit 8: Sequence Number Suppression */ +#define IEEE_802154_FC_IE_PRESENT 0x0200 /* bit 9: IE Present */ +#define IEEE_802154_FC_DST_ADDR_MODE_MASK 0x0c00 /* bits 10..11: Destination Addressing Mode */ +#define IEEE_802154_FC_DST_ADDR_MODE_NO_ADDR (IEEE_802154_ADDR_MODE_NO_ADDR << 10) +#define IEEE_802154_FC_DST_ADDR_MODE_SHORT (IEEE_802154_ADDR_MODE_SHORT << 10) +#define IEEE_802154_FC_DST_ADDR_MODE_EXT (IEEE_802154_ADDR_MODE_EXT << 10) +#define IEEE_802154_FC_FRAME_VERSION_MASK 0x3000 /* bits 12..13: Frame Version */ +#define IEEE_802154_FC_FRAME_VERSION_GET(x) (((x) & IEEE_802154_FC_FRAME_VERSION_MASK) >> 12) +#define IEEE_802154_FC_SRC_ADDR_MODE_MASK 0xc000 /* bits 14..15: Source Addressing Mode */ +#define IEEE_802154_FC_SRC_ADDR_MODE_SHORT (IEEE_802154_ADDR_MODE_SHORT << 14) +#define IEEE_802154_FC_SRC_ADDR_MODE_EXT (IEEE_802154_ADDR_MODE_EXT << 14) + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_NETIF_IEEE802154_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h new file mode 100644 index 0000000..ecff24b --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6.h @@ -0,0 +1,89 @@ +/** + * @file + * + * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units. + */ + +/* + * Copyright (c) 2015 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#ifndef LWIP_HDR_LOWPAN6_H +#define LWIP_HDR_LOWPAN6_H + +#include "netif/lowpan6_opts.h" + +#if LWIP_IPV6 + +#include "netif/lowpan6_common.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** 1 second period for reassembly */ +#define LOWPAN6_TMR_INTERVAL 1000 + +void lowpan6_tmr(void); + +err_t lowpan6_set_context(u8_t idx, const ip6_addr_t * context); +err_t lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low); + +#if LWIP_IPV4 +err_t lowpan4_output(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr); +#endif /* LWIP_IPV4 */ +err_t lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr); +err_t lowpan6_input(struct pbuf * p, struct netif *netif); +err_t lowpan6_if_init(struct netif *netif); + +/* pan_id in network byte order. */ +err_t lowpan6_set_pan_id(u16_t pan_id); + +u16_t lowpan6_calc_crc(const void *buf, u16_t len); + +#if !NO_SYS +err_t tcpip_6lowpan_input(struct pbuf *p, struct netif *inp); +#endif /* !NO_SYS */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 */ + +#endif /* LWIP_HDR_LOWPAN6_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h new file mode 100644 index 0000000..01896a7 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_ble.h @@ -0,0 +1,78 @@ +/** + * @file + * 6LowPAN over BLE for IPv6 (RFC7668). + */ + +/* + * Copyright (c) 2017 Benjamin Aigner + * Copyright (c) 2015 Inico Technologies Ltd. , Author: Ivan Delamer + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Benjamin Aigner + * + * Based on the original 6lowpan implementation of lwIP ( @see 6lowpan.c) + */ + +#ifndef LWIP_HDR_LOWPAN6_BLE_H +#define LWIP_HDR_LOWPAN6_BLE_H + +#include "netif/lowpan6_opts.h" + +#if LWIP_IPV6 /* don't build if not configured for use in lwipopts.h */ + +#include "netif/lowpan6_common.h" +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +err_t rfc7668_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr); +err_t rfc7668_input(struct pbuf * p, struct netif *netif); +err_t rfc7668_set_local_addr_eui64(struct netif *netif, const u8_t *local_addr, size_t local_addr_len); +err_t rfc7668_set_local_addr_mac48(struct netif *netif, const u8_t *local_addr, size_t local_addr_len, int is_public_addr); +err_t rfc7668_set_peer_addr_eui64(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len); +err_t rfc7668_set_peer_addr_mac48(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len, int is_public_addr); +err_t rfc7668_set_context(u8_t index, const ip6_addr_t * context); +err_t rfc7668_if_init(struct netif *netif); + +#if !NO_SYS +err_t tcpip_rfc7668_input(struct pbuf *p, struct netif *inp); +#endif + +void ble_addr_to_eui64(uint8_t *dst, const uint8_t *src, int public_addr); +void eui64_to_ble_addr(uint8_t *dst, const uint8_t *src); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 */ + +#endif /* LWIP_HDR_LOWPAN6_BLE_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h new file mode 100644 index 0000000..0dc13ab --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_common.h @@ -0,0 +1,82 @@ +/** + * @file + * + * Common 6LowPAN routines for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units. + */ + +/* + * Copyright (c) 2015 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#ifndef LWIP_HDR_LOWPAN6_COMMON_H +#define LWIP_HDR_LOWPAN6_COMMON_H + +#include "netif/lowpan6_opts.h" + +#if LWIP_IPV6 /* don't build if IPv6 is disabled in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/ip.h" +#include "lwip/ip6_addr.h" +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Helper define for a link layer address, which can be encoded as 0, 2 or 8 bytes */ +struct lowpan6_link_addr { + /* encoded length of the address */ + u8_t addr_len; + /* address bytes */ + u8_t addr[8]; +}; + +s8_t lowpan6_get_address_mode(const ip6_addr_t *ip6addr, const struct lowpan6_link_addr *mac_addr); + +#if LWIP_6LOWPAN_IPHC +err_t lowpan6_compress_headers(struct netif *netif, u8_t *inbuf, size_t inbuf_size, u8_t *outbuf, size_t outbuf_size, + u8_t *lowpan6_header_len_out, u8_t *hidden_header_len_out, ip6_addr_t *lowpan6_contexts, + const struct lowpan6_link_addr *src, const struct lowpan6_link_addr *dst); +struct pbuf *lowpan6_decompress(struct pbuf *p, u16_t datagram_size, ip6_addr_t *lowpan6_contexts, + struct lowpan6_link_addr *src, struct lowpan6_link_addr *dest); +#endif /* LWIP_6LOWPAN_IPHC */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 */ + +#endif /* LWIP_HDR_LOWPAN6_COMMON_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h new file mode 100644 index 0000000..17d46cd --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/lowpan6_opts.h @@ -0,0 +1,122 @@ +/** + * @file + * 6LowPAN options list + */ + +/* + * Copyright (c) 2015 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +#ifndef LWIP_HDR_LOWPAN6_OPTS_H +#define LWIP_HDR_LOWPAN6_OPTS_H + +#include "lwip/opt.h" + +/** LWIP_6LOWPAN_NUM_CONTEXTS: define the number of compression + * contexts per netif type + */ +#ifndef LWIP_6LOWPAN_NUM_CONTEXTS +#define LWIP_6LOWPAN_NUM_CONTEXTS 10 +#endif + +/** LWIP_6LOWPAN_INFER_SHORT_ADDRESS: set this to 0 to disable creating + * short addresses for matching addresses (debug only) + */ +#ifndef LWIP_6LOWPAN_INFER_SHORT_ADDRESS +#define LWIP_6LOWPAN_INFER_SHORT_ADDRESS 1 +#endif + +/** LWIP_6LOWPAN_IPHC: set this to 0 to disable IP header compression as per + * RFC 6282 (which is mandatory for BLE) + */ +#ifndef LWIP_6LOWPAN_IPHC +#define LWIP_6LOWPAN_IPHC 1 +#endif + +/** Set this to 1 if your IEEE 802.15.4 interface can calculate and check the + * CRC in hardware. This means TX packets get 2 zero bytes added on transmission + * which are to be filled with the CRC. + */ +#ifndef LWIP_6LOWPAN_802154_HW_CRC +#define LWIP_6LOWPAN_802154_HW_CRC 0 +#endif + +/** If LWIP_6LOWPAN_802154_HW_CRC==0, this can override the default slow + * implementation of the CRC used for 6LoWPAN over IEEE 802.15.4 (which uses + * a shift register). + */ +#ifndef LWIP_6LOWPAN_CALC_CRC +#define LWIP_6LOWPAN_CALC_CRC(buf, len) lowpan6_calc_crc(buf, len) +#endif + +/** Debug level for 6LoWPAN in general */ +#ifndef LWIP_LOWPAN6_DEBUG +#define LWIP_LOWPAN6_DEBUG LWIP_DBG_OFF +#endif + +/** Debug level for 6LoWPAN over IEEE 802.15.4 */ +#ifndef LWIP_LOWPAN6_802154_DEBUG +#define LWIP_LOWPAN6_802154_DEBUG LWIP_DBG_OFF +#endif + +/** LWIP_LOWPAN6_IP_COMPRESSED_DEBUG: enable compressed IP frame + * output debugging + */ +#ifndef LWIP_LOWPAN6_IP_COMPRESSED_DEBUG +#define LWIP_LOWPAN6_IP_COMPRESSED_DEBUG LWIP_DBG_OFF +#endif + +/** LWIP_LOWPAN6_DECOMPRESSION_DEBUG: enable decompression debug output + */ +#ifndef LWIP_LOWPAN6_DECOMPRESSION_DEBUG +#define LWIP_LOWPAN6_DECOMPRESSION_DEBUG LWIP_DBG_OFF +#endif + +/** LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG: enable decompressed IP frame + * output debugging */ +#ifndef LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG +#define LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG LWIP_DBG_OFF +#endif + +/** LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS: + * Currently, the linux kernel driver for 6lowpan sets/clears a bit in + * the address, depending on the BD address (either public or not). + * Might not be RFC7668 conform, so you may select to do that (=1) or + * not (=0) */ +#ifndef LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS +#define LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS 1 +#endif + + +#endif /* LWIP_HDR_LOWPAN6_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h new file mode 100644 index 0000000..b228522 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ccp.h @@ -0,0 +1,164 @@ +/* + * ccp.h - Definitions for PPP Compression Control Protocol. + * + * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: ccp.h,v 1.12 2004/11/04 10:02:26 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && CCP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef CCP_H +#define CCP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CCP codes. + */ + +#define CCP_CONFREQ 1 +#define CCP_CONFACK 2 +#define CCP_TERMREQ 5 +#define CCP_TERMACK 6 +#define CCP_RESETREQ 14 +#define CCP_RESETACK 15 + +/* + * Max # bytes for a CCP option + */ + +#define CCP_MAX_OPTION_LENGTH 32 + +/* + * Parts of a CCP packet. + */ + +#define CCP_CODE(dp) ((dp)[0]) +#define CCP_ID(dp) ((dp)[1]) +#define CCP_LENGTH(dp) (((dp)[2] << 8) + (dp)[3]) +#define CCP_HDRLEN 4 + +#define CCP_OPT_CODE(dp) ((dp)[0]) +#define CCP_OPT_LENGTH(dp) ((dp)[1]) +#define CCP_OPT_MINLEN 2 + +#if BSDCOMPRESS_SUPPORT +/* + * Definitions for BSD-Compress. + */ + +#define CI_BSD_COMPRESS 21 /* config. option for BSD-Compress */ +#define CILEN_BSD_COMPRESS 3 /* length of config. option */ + +/* Macros for handling the 3rd byte of the BSD-Compress config option. */ +#define BSD_NBITS(x) ((x) & 0x1F) /* number of bits requested */ +#define BSD_VERSION(x) ((x) >> 5) /* version of option format */ +#define BSD_CURRENT_VERSION 1 /* current version number */ +#define BSD_MAKE_OPT(v, n) (((v) << 5) | (n)) + +#define BSD_MIN_BITS 9 /* smallest code size supported */ +#define BSD_MAX_BITS 15 /* largest code size supported */ +#endif /* BSDCOMPRESS_SUPPORT */ + +#if DEFLATE_SUPPORT +/* + * Definitions for Deflate. + */ + +#define CI_DEFLATE 26 /* config option for Deflate */ +#define CI_DEFLATE_DRAFT 24 /* value used in original draft RFC */ +#define CILEN_DEFLATE 4 /* length of its config option */ + +#define DEFLATE_MIN_SIZE 9 +#define DEFLATE_MAX_SIZE 15 +#define DEFLATE_METHOD_VAL 8 +#define DEFLATE_SIZE(x) (((x) >> 4) + 8) +#define DEFLATE_METHOD(x) ((x) & 0x0F) +#define DEFLATE_MAKE_OPT(w) ((((w) - 8) << 4) + DEFLATE_METHOD_VAL) +#define DEFLATE_CHK_SEQUENCE 0 +#endif /* DEFLATE_SUPPORT */ + +#if MPPE_SUPPORT +/* + * Definitions for MPPE. + */ + +#define CI_MPPE 18 /* config option for MPPE */ +#define CILEN_MPPE 6 /* length of config option */ +#endif /* MPPE_SUPPORT */ + +#if PREDICTOR_SUPPORT +/* + * Definitions for other, as yet unsupported, compression methods. + */ + +#define CI_PREDICTOR_1 1 /* config option for Predictor-1 */ +#define CILEN_PREDICTOR_1 2 /* length of its config option */ +#define CI_PREDICTOR_2 2 /* config option for Predictor-2 */ +#define CILEN_PREDICTOR_2 2 /* length of its config option */ +#endif /* PREDICTOR_SUPPORT */ + +typedef struct ccp_options { +#if DEFLATE_SUPPORT + unsigned int deflate :1; /* do Deflate? */ + unsigned int deflate_correct :1; /* use correct code for deflate? */ + unsigned int deflate_draft :1; /* use draft RFC code for deflate? */ +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + unsigned int bsd_compress :1; /* do BSD Compress? */ +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + unsigned int predictor_1 :1; /* do Predictor-1? */ + unsigned int predictor_2 :1; /* do Predictor-2? */ +#endif /* PREDICTOR_SUPPORT */ + +#if MPPE_SUPPORT + u8_t mppe; /* MPPE bitfield */ +#endif /* MPPE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + u_short bsd_bits; /* # bits/code for BSD Compress */ +#endif /* BSDCOMPRESS_SUPPORT */ +#if DEFLATE_SUPPORT + u_short deflate_size; /* lg(window size) for Deflate */ +#endif /* DEFLATE_SUPPORT */ + u8_t method; /* code for chosen compression method */ +} ccp_options; + +extern const struct protent ccp_protent; + +void ccp_resetrequest(ppp_pcb *pcb); /* Issue a reset-request. */ + +#ifdef __cplusplus +} +#endif + +#endif /* CCP_H */ +#endif /* PPP_SUPPORT && CCP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h new file mode 100644 index 0000000..eb0269f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-md5.h @@ -0,0 +1,36 @@ +/* + * chap-md5.h - New CHAP/MD5 implementation. + * + * Copyright (c) 2003 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +extern const struct chap_digest_type md5_digest; + +#endif /* PPP_SUPPORT && CHAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h new file mode 100644 index 0000000..2d8cd9c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap-new.h @@ -0,0 +1,200 @@ +/* + * chap-new.c - New CHAP implementation. + * + * Copyright (c) 2003 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef CHAP_H +#define CHAP_H + +#include "ppp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * CHAP packets begin with a standard header with code, id, len (2 bytes). + */ +#define CHAP_HDRLEN 4 + +/* + * Values for the code field. + */ +#define CHAP_CHALLENGE 1 +#define CHAP_RESPONSE 2 +#define CHAP_SUCCESS 3 +#define CHAP_FAILURE 4 + +/* + * CHAP digest codes. + */ +#define CHAP_MD5 5 +#if MSCHAP_SUPPORT +#define CHAP_MICROSOFT 0x80 +#define CHAP_MICROSOFT_V2 0x81 +#endif /* MSCHAP_SUPPORT */ + +/* + * Semi-arbitrary limits on challenge and response fields. + */ +#define MAX_CHALLENGE_LEN 64 +#define MAX_RESPONSE_LEN 64 + +/* + * These limits apply to challenge and response packets we send. + * The +4 is the +1 that we actually need rounded up. + */ +#define CHAL_MAX_PKTLEN (PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_CHALLENGE_LEN + MAXNAMELEN) +#define RESP_MAX_PKTLEN (PPP_HDRLEN + CHAP_HDRLEN + 4 + MAX_RESPONSE_LEN + MAXNAMELEN) + +/* bitmask of supported algorithms */ +#if MSCHAP_SUPPORT +#define MDTYPE_MICROSOFT_V2 0x1 +#define MDTYPE_MICROSOFT 0x2 +#endif /* MSCHAP_SUPPORT */ +#define MDTYPE_MD5 0x4 +#define MDTYPE_NONE 0 + +#if MSCHAP_SUPPORT +/* Return the digest alg. ID for the most preferred digest type. */ +#define CHAP_DIGEST(mdtype) \ + ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \ + ((mdtype) & MDTYPE_MICROSOFT_V2)? CHAP_MICROSOFT_V2: \ + ((mdtype) & MDTYPE_MICROSOFT)? CHAP_MICROSOFT: \ + 0 +#else /* !MSCHAP_SUPPORT */ +#define CHAP_DIGEST(mdtype) \ + ((mdtype) & MDTYPE_MD5)? CHAP_MD5: \ + 0 +#endif /* MSCHAP_SUPPORT */ + +/* Return the bit flag (lsb set) for our most preferred digest type. */ +#define CHAP_MDTYPE(mdtype) ((mdtype) ^ ((mdtype) - 1)) & (mdtype) + +/* Return the bit flag for a given digest algorithm ID. */ +#if MSCHAP_SUPPORT +#define CHAP_MDTYPE_D(digest) \ + ((digest) == CHAP_MICROSOFT_V2)? MDTYPE_MICROSOFT_V2: \ + ((digest) == CHAP_MICROSOFT)? MDTYPE_MICROSOFT: \ + ((digest) == CHAP_MD5)? MDTYPE_MD5: \ + 0 +#else /* !MSCHAP_SUPPORT */ +#define CHAP_MDTYPE_D(digest) \ + ((digest) == CHAP_MD5)? MDTYPE_MD5: \ + 0 +#endif /* MSCHAP_SUPPORT */ + +/* Can we do the requested digest? */ +#if MSCHAP_SUPPORT +#define CHAP_CANDIGEST(mdtype, digest) \ + ((digest) == CHAP_MICROSOFT_V2)? (mdtype) & MDTYPE_MICROSOFT_V2: \ + ((digest) == CHAP_MICROSOFT)? (mdtype) & MDTYPE_MICROSOFT: \ + ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \ + 0 +#else /* !MSCHAP_SUPPORT */ +#define CHAP_CANDIGEST(mdtype, digest) \ + ((digest) == CHAP_MD5)? (mdtype) & MDTYPE_MD5: \ + 0 +#endif /* MSCHAP_SUPPORT */ + +/* + * The code for each digest type has to supply one of these. + */ +struct chap_digest_type { + int code; + +#if PPP_SERVER + /* + * Note: challenge and response arguments below are formatted as + * a length byte followed by the actual challenge/response data. + */ + void (*generate_challenge)(ppp_pcb *pcb, unsigned char *challenge); + int (*verify_response)(ppp_pcb *pcb, int id, const char *name, + const unsigned char *secret, int secret_len, + const unsigned char *challenge, const unsigned char *response, + char *message, int message_space); +#endif /* PPP_SERVER */ + void (*make_response)(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name, + const unsigned char *challenge, const char *secret, int secret_len, + unsigned char *priv); + int (*check_success)(ppp_pcb *pcb, unsigned char *pkt, int len, unsigned char *priv); + void (*handle_failure)(ppp_pcb *pcb, unsigned char *pkt, int len); +}; + +/* + * Each interface is described by chap structure. + */ +#if CHAP_SUPPORT +typedef struct chap_client_state { + u8_t flags; + const char *name; + const struct chap_digest_type *digest; + unsigned char priv[64]; /* private area for digest's use */ +} chap_client_state; + +#if PPP_SERVER +typedef struct chap_server_state { + u8_t flags; + u8_t id; + const char *name; + const struct chap_digest_type *digest; + int challenge_xmits; + int challenge_pktlen; + unsigned char challenge[CHAL_MAX_PKTLEN]; +} chap_server_state; +#endif /* PPP_SERVER */ +#endif /* CHAP_SUPPORT */ + +#if 0 /* UNUSED */ +/* Hook for a plugin to validate CHAP challenge */ +extern int (*chap_verify_hook)(char *name, char *ourname, int id, + const struct chap_digest_type *digest, + unsigned char *challenge, unsigned char *response, + char *message, int message_space); +#endif /* UNUSED */ + +#if PPP_SERVER +/* Called by authentication code to start authenticating the peer. */ +extern void chap_auth_peer(ppp_pcb *pcb, const char *our_name, int digest_code); +#endif /* PPP_SERVER */ + +/* Called by auth. code to start authenticating us to the peer. */ +extern void chap_auth_with_peer(ppp_pcb *pcb, const char *our_name, int digest_code); + +/* Represents the CHAP protocol to the main pppd code */ +extern const struct protent chap_protent; + +#ifdef __cplusplus +} +#endif + +#endif /* CHAP_H */ +#endif /* PPP_SUPPORT && CHAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h new file mode 100644 index 0000000..0795291 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/chap_ms.h @@ -0,0 +1,44 @@ +/* + * chap_ms.h - Challenge Handshake Authentication Protocol definitions. + * + * Copyright (c) 1995 Eric Rosenquist. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: chap_ms.h,v 1.13 2004/11/15 22:13:26 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef CHAPMS_INCLUDE +#define CHAPMS_INCLUDE + +extern const struct chap_digest_type chapms_digest; +extern const struct chap_digest_type chapms2_digest; + +#endif /* CHAPMS_INCLUDE */ + +#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h new file mode 100644 index 0000000..3ee9aaf --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eap.h @@ -0,0 +1,169 @@ +/* + * eap.h - Extensible Authentication Protocol for PPP (RFC 2284) + * + * Copyright (c) 2001 by Sun Microsystems, Inc. + * All rights reserved. + * + * Non-exclusive rights to redistribute, modify, translate, and use + * this software in source and binary forms, in whole or in part, is + * hereby granted, provided that the above copyright notice is + * duplicated in any source form, and that neither the name of the + * copyright holder nor the author is used to endorse or promote + * products derived from this software. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Original version by James Carlson + * + * $Id: eap.h,v 1.2 2003/06/11 23:56:26 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && EAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef PPP_EAP_H +#define PPP_EAP_H + +#include "ppp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Packet header = Code, id, length. + */ +#define EAP_HEADERLEN 4 + + +/* EAP message codes. */ +#define EAP_REQUEST 1 +#define EAP_RESPONSE 2 +#define EAP_SUCCESS 3 +#define EAP_FAILURE 4 + +/* EAP types */ +#define EAPT_IDENTITY 1 +#define EAPT_NOTIFICATION 2 +#define EAPT_NAK 3 /* (response only) */ +#define EAPT_MD5CHAP 4 +#define EAPT_OTP 5 /* One-Time Password; RFC 1938 */ +#define EAPT_TOKEN 6 /* Generic Token Card */ +/* 7 and 8 are unassigned. */ +#define EAPT_RSA 9 /* RSA Public Key Authentication */ +#define EAPT_DSS 10 /* DSS Unilateral */ +#define EAPT_KEA 11 /* KEA */ +#define EAPT_KEA_VALIDATE 12 /* KEA-VALIDATE */ +#define EAPT_TLS 13 /* EAP-TLS */ +#define EAPT_DEFENDER 14 /* Defender Token (AXENT) */ +#define EAPT_W2K 15 /* Windows 2000 EAP */ +#define EAPT_ARCOT 16 /* Arcot Systems */ +#define EAPT_CISCOWIRELESS 17 /* Cisco Wireless */ +#define EAPT_NOKIACARD 18 /* Nokia IP smart card */ +#define EAPT_SRP 19 /* Secure Remote Password */ +/* 20 is deprecated */ + +/* EAP SRP-SHA1 Subtypes */ +#define EAPSRP_CHALLENGE 1 /* Request 1 - Challenge */ +#define EAPSRP_CKEY 1 /* Response 1 - Client Key */ +#define EAPSRP_SKEY 2 /* Request 2 - Server Key */ +#define EAPSRP_CVALIDATOR 2 /* Response 2 - Client Validator */ +#define EAPSRP_SVALIDATOR 3 /* Request 3 - Server Validator */ +#define EAPSRP_ACK 3 /* Response 3 - final ack */ +#define EAPSRP_LWRECHALLENGE 4 /* Req/resp 4 - Lightweight rechal */ + +#define SRPVAL_EBIT 0x00000001 /* Use shared key for ECP */ + +#define SRP_PSEUDO_ID "pseudo_" +#define SRP_PSEUDO_LEN 7 + +#define MD5_SIGNATURE_SIZE 16 +#define EAP_MIN_CHALLENGE_LENGTH 17 +#define EAP_MAX_CHALLENGE_LENGTH 24 +#define EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH 3 /* 2^3-1 = 7, 17+7 = 24 */ + +#define EAP_STATES \ + "Initial", "Pending", "Closed", "Listen", "Identify", \ + "SRP1", "SRP2", "SRP3", "MD5Chall", "Open", "SRP4", "BadAuth" + +#define eap_client_active(pcb) ((pcb)->eap.es_client.ea_state == eapListen) +#if PPP_SERVER +#define eap_server_active(pcb) \ + ((pcb)->eap.es_server.ea_state >= eapIdentify && \ + (pcb)->eap.es_server.ea_state <= eapMD5Chall) +#endif /* PPP_SERVER */ + +/* + * Complete EAP state for one PPP session. + */ +enum eap_state_code { + eapInitial = 0, /* No EAP authentication yet requested */ + eapPending, /* Waiting for LCP (no timer) */ + eapClosed, /* Authentication not in use */ + eapListen, /* Client ready (and timer running) */ + eapIdentify, /* EAP Identify sent */ + eapSRP1, /* Sent EAP SRP-SHA1 Subtype 1 */ + eapSRP2, /* Sent EAP SRP-SHA1 Subtype 2 */ + eapSRP3, /* Sent EAP SRP-SHA1 Subtype 3 */ + eapMD5Chall, /* Sent MD5-Challenge */ + eapOpen, /* Completed authentication */ + eapSRP4, /* Sent EAP SRP-SHA1 Subtype 4 */ + eapBadAuth /* Failed authentication */ +}; + +struct eap_auth { + const char *ea_name; /* Our name */ + char ea_peer[MAXNAMELEN +1]; /* Peer's name */ + void *ea_session; /* Authentication library linkage */ + u_char *ea_skey; /* Shared encryption key */ + u_short ea_namelen; /* Length of our name */ + u_short ea_peerlen; /* Length of peer's name */ + enum eap_state_code ea_state; + u_char ea_id; /* Current id */ + u_char ea_requests; /* Number of Requests sent/received */ + u_char ea_responses; /* Number of Responses */ + u_char ea_type; /* One of EAPT_* */ + u32_t ea_keyflags; /* SRP shared key usage flags */ +}; + +#ifndef EAP_MAX_CHALLENGE_LENGTH +#define EAP_MAX_CHALLENGE_LENGTH 24 +#endif +typedef struct eap_state { + struct eap_auth es_client; /* Client (authenticatee) data */ +#if PPP_SERVER + struct eap_auth es_server; /* Server (authenticator) data */ +#endif /* PPP_SERVER */ + int es_savedtime; /* Saved timeout */ + int es_rechallenge; /* EAP rechallenge interval */ + int es_lwrechallenge; /* SRP lightweight rechallenge inter */ + u8_t es_usepseudo; /* Use SRP Pseudonym if offered one */ + int es_usedpseudo; /* Set if we already sent PN */ + int es_challen; /* Length of challenge string */ + u_char es_challenge[EAP_MAX_CHALLENGE_LENGTH]; +} eap_state; + +/* + * Timeouts. + */ +#if 0 /* moved to ppp_opts.h */ +#define EAP_DEFTIMEOUT 3 /* Timeout (seconds) for rexmit */ +#define EAP_DEFTRANSMITS 10 /* max # times to transmit */ +#define EAP_DEFREQTIME 20 /* Time to wait for peer request */ +#define EAP_DEFALLOWREQ 20 /* max # times to accept requests */ +#endif /* moved to ppp_opts.h */ + +void eap_authwithpeer(ppp_pcb *pcb, const char *localname); +void eap_authpeer(ppp_pcb *pcb, const char *localname); + +extern const struct protent eap_protent; + +#ifdef __cplusplus +} +#endif + +#endif /* PPP_EAP_H */ + +#endif /* PPP_SUPPORT && EAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h new file mode 100644 index 0000000..d8808c3 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ecp.h @@ -0,0 +1,62 @@ +/* + * ecp.h - Definitions for PPP Encryption Control Protocol. + * + * Copyright (c) 2002 Google, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: ecp.h,v 1.2 2003/01/10 07:12:36 fcusack Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && ECP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef ECP_H +#define ECP_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct ecp_options { + bool required; /* Is ECP required? */ + unsigned enctype; /* Encryption type */ +} ecp_options; + +extern fsm ecp_fsm[]; +extern ecp_options ecp_wantoptions[]; +extern ecp_options ecp_gotoptions[]; +extern ecp_options ecp_allowoptions[]; +extern ecp_options ecp_hisoptions[]; + +extern const struct protent ecp_protent; + +#ifdef __cplusplus +} +#endif + +#endif /* ECP_H */ +#endif /* PPP_SUPPORT && ECP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h new file mode 100644 index 0000000..5adeb48 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/eui64.h @@ -0,0 +1,102 @@ +/* + * eui64.h - EUI64 routines for IPv6CP. + * + * Copyright (c) 1999 Tommi Komulainen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Tommi Komulainen + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: eui64.h,v 1.6 2002/12/04 23:03:32 paulus Exp $ +*/ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPP_IPV6_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef EUI64_H +#define EUI64_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * @todo: + * + * Maybe this should be done by processing struct in6_addr directly... + */ +typedef union +{ + u8_t e8[8]; + u16_t e16[4]; + u32_t e32[2]; +} eui64_t; + +#define eui64_iszero(e) (((e).e32[0] | (e).e32[1]) == 0) +#define eui64_equals(e, o) (((e).e32[0] == (o).e32[0]) && \ + ((e).e32[1] == (o).e32[1])) +#define eui64_zero(e) (e).e32[0] = (e).e32[1] = 0; + +#define eui64_copy(s, d) memcpy(&(d), &(s), sizeof(eui64_t)) + +#define eui64_magic(e) do { \ + (e).e32[0] = magic(); \ + (e).e32[1] = magic(); \ + (e).e8[0] &= ~2; \ + } while (0) +#define eui64_magic_nz(x) do { \ + eui64_magic(x); \ + } while (eui64_iszero(x)) +#define eui64_magic_ne(x, y) do { \ + eui64_magic(x); \ + } while (eui64_equals(x, y)) + +#define eui64_get(ll, cp) do { \ + eui64_copy((*cp), (ll)); \ + (cp) += sizeof(eui64_t); \ + } while (0) + +#define eui64_put(ll, cp) do { \ + eui64_copy((ll), (*cp)); \ + (cp) += sizeof(eui64_t); \ + } while (0) + +#define eui64_set32(e, l) do { \ + (e).e32[0] = 0; \ + (e).e32[1] = lwip_htonl(l); \ + } while (0) +#define eui64_setlo32(e, l) eui64_set32(e, l) + +char *eui64_ntoa(eui64_t); /* Returns ascii representation of id */ + +#ifdef __cplusplus +} +#endif + +#endif /* EUI64_H */ +#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h new file mode 100644 index 0000000..8dec700 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/fsm.h @@ -0,0 +1,182 @@ +/* + * fsm.h - {Link, IP} Control Protocol Finite State Machine definitions. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: fsm.h,v 1.10 2004/11/13 02:28:15 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef FSM_H +#define FSM_H + +#include "ppp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Packet header = Code, id, length. + */ +#define HEADERLEN 4 + + +/* + * CP (LCP, IPCP, etc.) codes. + */ +#define CONFREQ 1 /* Configuration Request */ +#define CONFACK 2 /* Configuration Ack */ +#define CONFNAK 3 /* Configuration Nak */ +#define CONFREJ 4 /* Configuration Reject */ +#define TERMREQ 5 /* Termination Request */ +#define TERMACK 6 /* Termination Ack */ +#define CODEREJ 7 /* Code Reject */ + + +/* + * Each FSM is described by an fsm structure and fsm callbacks. + */ +typedef struct fsm { + ppp_pcb *pcb; /* PPP Interface */ + const struct fsm_callbacks *callbacks; /* Callback routines */ + const char *term_reason; /* Reason for closing protocol */ + u8_t seen_ack; /* Have received valid Ack/Nak/Rej to Req */ + /* -- This is our only flag, we might use u_int :1 if we have more flags */ + u16_t protocol; /* Data Link Layer Protocol field value */ + u8_t state; /* State */ + u8_t flags; /* Contains option bits */ + u8_t id; /* Current id */ + u8_t reqid; /* Current request id */ + u8_t retransmits; /* Number of retransmissions left */ + u8_t nakloops; /* Number of nak loops since last ack */ + u8_t rnakloops; /* Number of naks received */ + u8_t maxnakloops; /* Maximum number of nak loops tolerated + (necessary because IPCP require a custom large max nak loops value) */ + u8_t term_reason_len; /* Length of term_reason */ +} fsm; + + +typedef struct fsm_callbacks { + void (*resetci) /* Reset our Configuration Information */ + (fsm *); + int (*cilen) /* Length of our Configuration Information */ + (fsm *); + void (*addci) /* Add our Configuration Information */ + (fsm *, u_char *, int *); + int (*ackci) /* ACK our Configuration Information */ + (fsm *, u_char *, int); + int (*nakci) /* NAK our Configuration Information */ + (fsm *, u_char *, int, int); + int (*rejci) /* Reject our Configuration Information */ + (fsm *, u_char *, int); + int (*reqci) /* Request peer's Configuration Information */ + (fsm *, u_char *, int *, int); + void (*up) /* Called when fsm reaches PPP_FSM_OPENED state */ + (fsm *); + void (*down) /* Called when fsm leaves PPP_FSM_OPENED state */ + (fsm *); + void (*starting) /* Called when we want the lower layer */ + (fsm *); + void (*finished) /* Called when we don't want the lower layer */ + (fsm *); + void (*protreject) /* Called when Protocol-Reject received */ + (int); + void (*retransmit) /* Retransmission is necessary */ + (fsm *); + int (*extcode) /* Called when unknown code received */ + (fsm *, int, int, u_char *, int); + const char *proto_name; /* String name for protocol (for messages) */ +} fsm_callbacks; + + +/* + * Link states. + */ +#define PPP_FSM_INITIAL 0 /* Down, hasn't been opened */ +#define PPP_FSM_STARTING 1 /* Down, been opened */ +#define PPP_FSM_CLOSED 2 /* Up, hasn't been opened */ +#define PPP_FSM_STOPPED 3 /* Open, waiting for down event */ +#define PPP_FSM_CLOSING 4 /* Terminating the connection, not open */ +#define PPP_FSM_STOPPING 5 /* Terminating, but open */ +#define PPP_FSM_REQSENT 6 /* We've sent a Config Request */ +#define PPP_FSM_ACKRCVD 7 /* We've received a Config Ack */ +#define PPP_FSM_ACKSENT 8 /* We've sent a Config Ack */ +#define PPP_FSM_OPENED 9 /* Connection available */ + + +/* + * Flags - indicate options controlling FSM operation + */ +#define OPT_PASSIVE 1 /* Don't die if we don't get a response */ +#define OPT_RESTART 2 /* Treat 2nd OPEN as DOWN, UP */ +#define OPT_SILENT 4 /* Wait for peer to speak first */ + + +/* + * Timeouts. + */ +#if 0 /* moved to ppp_opts.h */ +#define DEFTIMEOUT 3 /* Timeout time in seconds */ +#define DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#define DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#define DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif /* moved to ppp_opts.h */ + + +/* + * Prototypes + */ +void fsm_init(fsm *f); +void fsm_lowerup(fsm *f); +void fsm_lowerdown(fsm *f); +void fsm_open(fsm *f); +void fsm_close(fsm *f, const char *reason); +void fsm_input(fsm *f, u_char *inpacket, int l); +void fsm_protreject(fsm *f); +void fsm_sdata(fsm *f, u_char code, u_char id, const u_char *data, int datalen); + +#ifdef __cplusplus +} +#endif + +#endif /* FSM_H */ +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h new file mode 100644 index 0000000..32fdd1c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipcp.h @@ -0,0 +1,134 @@ +/* + * ipcp.h - IP Control Protocol definitions. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: ipcp.h,v 1.14 2002/12/04 23:03:32 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPP_IPV4_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef IPCP_H +#define IPCP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Options. + */ +#define CI_ADDRS 1 /* IP Addresses */ +#if VJ_SUPPORT +#define CI_COMPRESSTYPE 2 /* Compression Type */ +#endif /* VJ_SUPPORT */ +#define CI_ADDR 3 + +#if LWIP_DNS +#define CI_MS_DNS1 129 /* Primary DNS value */ +#define CI_MS_DNS2 131 /* Secondary DNS value */ +#endif /* LWIP_DNS */ +#if 0 /* UNUSED - WINS */ +#define CI_MS_WINS1 130 /* Primary WINS value */ +#define CI_MS_WINS2 132 /* Secondary WINS value */ +#endif /* UNUSED - WINS */ + +#if VJ_SUPPORT +#define MAX_STATES 16 /* from slcompress.h */ + +#define IPCP_VJMODE_OLD 1 /* "old" mode (option # = 0x0037) */ +#define IPCP_VJMODE_RFC1172 2 /* "old-rfc"mode (option # = 0x002d) */ +#define IPCP_VJMODE_RFC1332 3 /* "new-rfc"mode (option # = 0x002d, */ + /* maxslot and slot number compression) */ + +#define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/ +#define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ + /* compression option*/ +#endif /* VJ_SUPPORT */ + +typedef struct ipcp_options { + unsigned int neg_addr :1; /* Negotiate IP Address? */ + unsigned int old_addrs :1; /* Use old (IP-Addresses) option? */ + unsigned int req_addr :1; /* Ask peer to send IP address? */ +#if 0 /* UNUSED */ + unsigned int default_route :1; /* Assign default route through interface? */ + unsigned int replace_default_route :1; /* Replace default route through interface? */ +#endif /* UNUSED */ +#if 0 /* UNUSED - PROXY ARP */ + unsigned int proxy_arp :1; /* Make proxy ARP entry for peer? */ +#endif /* UNUSED - PROXY ARP */ +#if VJ_SUPPORT + unsigned int neg_vj :1; /* Van Jacobson Compression? */ + unsigned int old_vj :1; /* use old (short) form of VJ option? */ + unsigned int cflag :1; +#endif /* VJ_SUPPORT */ + unsigned int accept_local :1; /* accept peer's value for ouraddr */ + unsigned int accept_remote :1; /* accept peer's value for hisaddr */ +#if LWIP_DNS + unsigned int req_dns1 :1; /* Ask peer to send primary DNS address? */ + unsigned int req_dns2 :1; /* Ask peer to send secondary DNS address? */ +#endif /* LWIP_DNS */ + + u32_t ouraddr, hisaddr; /* Addresses in NETWORK BYTE ORDER */ +#if LWIP_DNS + u32_t dnsaddr[2]; /* Primary and secondary MS DNS entries */ +#endif /* LWIP_DNS */ +#if 0 /* UNUSED - WINS */ + u32_t winsaddr[2]; /* Primary and secondary MS WINS entries */ +#endif /* UNUSED - WINS */ + +#if VJ_SUPPORT + u16_t vj_protocol; /* protocol value to use in VJ option */ + u8_t maxslotindex; /* values for RFC1332 VJ compression neg. */ +#endif /* VJ_SUPPORT */ +} ipcp_options; + +#if 0 /* UNUSED, already defined by lwIP */ +char *ip_ntoa (u32_t); +#endif /* UNUSED, already defined by lwIP */ + +extern const struct protent ipcp_protent; + +#ifdef __cplusplus +} +#endif + +#endif /* IPCP_H */ +#endif /* PPP_SUPPORT && PPP_IPV4_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h new file mode 100644 index 0000000..9099973 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ipv6cp.h @@ -0,0 +1,191 @@ +/* + * ipv6cp.h - PPP IPV6 Control Protocol. + * + * Copyright (c) 1999 Tommi Komulainen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Tommi Komulainen + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* Original version, based on RFC2023 : + + Copyright (c) 1995, 1996, 1997 Francis.Dupont@inria.fr, INRIA Rocquencourt, + Alain.Durand@imag.fr, IMAG, + Jean-Luc.Richier@imag.fr, IMAG-LSR. + + Copyright (c) 1998, 1999 Francis.Dupont@inria.fr, GIE DYADE, + Alain.Durand@imag.fr, IMAG, + Jean-Luc.Richier@imag.fr, IMAG-LSR. + + Ce travail a été fait au sein du GIE DYADE (Groupement d'Intérêt + Économique ayant pour membres BULL S.A. et l'INRIA). + + Ce logiciel informatique est disponible aux conditions + usuelles dans la recherche, c'est-à-dire qu'il peut + être utilisé, copié, modifié, distribué à l'unique + condition que ce texte soit conservé afin que + l'origine de ce logiciel soit reconnue. + + Le nom de l'Institut National de Recherche en Informatique + et en Automatique (INRIA), de l'IMAG, ou d'une personne morale + ou physique ayant participé à l'élaboration de ce logiciel ne peut + être utilisé sans son accord préalable explicite. + + Ce logiciel est fourni tel quel sans aucune garantie, + support ou responsabilité d'aucune sorte. + Ce logiciel est dérivé de sources d'origine + "University of California at Berkeley" et + "Digital Equipment Corporation" couvertes par des copyrights. + + L'Institut d'Informatique et de Mathématiques Appliquées de Grenoble (IMAG) + est une fédération d'unités mixtes de recherche du CNRS, de l'Institut National + Polytechnique de Grenoble et de l'Université Joseph Fourier regroupant + sept laboratoires dont le laboratoire Logiciels, Systèmes, Réseaux (LSR). + + This work has been done in the context of GIE DYADE (joint R & D venture + between BULL S.A. and INRIA). + + This software is available with usual "research" terms + with the aim of retain credits of the software. + Permission to use, copy, modify and distribute this software for any + purpose and without fee is hereby granted, provided that the above + copyright notice and this permission notice appear in all copies, + and the name of INRIA, IMAG, or any contributor not be used in advertising + or publicity pertaining to this material without the prior explicit + permission. The software is provided "as is" without any + warranties, support or liabilities of any kind. + This software is derived from source code from + "University of California at Berkeley" and + "Digital Equipment Corporation" protected by copyrights. + + Grenoble's Institute of Computer Science and Applied Mathematics (IMAG) + is a federation of seven research units funded by the CNRS, National + Polytechnic Institute of Grenoble and University Joseph Fourier. + The research unit in Software, Systems, Networks (LSR) is member of IMAG. +*/ + +/* + * Derived from : + * + * + * ipcp.h - IP Control Protocol definitions. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: ipv6cp.h,v 1.7 2002/12/04 23:03:32 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPP_IPV6_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef IPV6CP_H +#define IPV6CP_H + +#include "eui64.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Options. + */ +#define CI_IFACEID 1 /* Interface Identifier */ +#ifdef IPV6CP_COMP +#define CI_COMPRESSTYPE 2 /* Compression Type */ +#endif /* IPV6CP_COMP */ + +/* No compression types yet defined. + *#define IPV6CP_COMP 0x004f + */ +typedef struct ipv6cp_options { + unsigned int neg_ifaceid :1; /* Negotiate interface identifier? */ + unsigned int req_ifaceid :1; /* Ask peer to send interface identifier? */ + unsigned int accept_local :1; /* accept peer's value for iface id? */ + unsigned int opt_local :1; /* ourtoken set by option */ + unsigned int opt_remote :1; /* histoken set by option */ + unsigned int use_ip :1; /* use IP as interface identifier */ +#if 0 + unsigned int use_persistent :1; /* use uniquely persistent value for address */ +#endif +#ifdef IPV6CP_COMP + unsigned int neg_vj :1; /* Van Jacobson Compression? */ +#endif /* IPV6CP_COMP */ + +#ifdef IPV6CP_COMP + u_short vj_protocol; /* protocol value to use in VJ option */ +#endif /* IPV6CP_COMP */ + eui64_t ourid, hisid; /* Interface identifiers */ +} ipv6cp_options; + +extern const struct protent ipv6cp_protent; + +#ifdef __cplusplus +} +#endif + +#endif /* IPV6CP_H */ +#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h new file mode 100644 index 0000000..18ad1cb --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/lcp.h @@ -0,0 +1,179 @@ +/* + * lcp.h - Link Control Protocol definitions. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: lcp.h,v 1.20 2004/11/14 22:53:42 carlsonj Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef LCP_H +#define LCP_H + +#include "ppp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Options. + */ +#define CI_VENDOR 0 /* Vendor Specific */ +#define CI_MRU 1 /* Maximum Receive Unit */ +#define CI_ASYNCMAP 2 /* Async Control Character Map */ +#define CI_AUTHTYPE 3 /* Authentication Type */ +#define CI_QUALITY 4 /* Quality Protocol */ +#define CI_MAGICNUMBER 5 /* Magic Number */ +#define CI_PCOMPRESSION 7 /* Protocol Field Compression */ +#define CI_ACCOMPRESSION 8 /* Address/Control Field Compression */ +#define CI_FCSALTERN 9 /* FCS-Alternatives */ +#define CI_SDP 10 /* Self-Describing-Pad */ +#define CI_NUMBERED 11 /* Numbered-Mode */ +#define CI_CALLBACK 13 /* callback */ +#define CI_MRRU 17 /* max reconstructed receive unit; multilink */ +#define CI_SSNHF 18 /* short sequence numbers for multilink */ +#define CI_EPDISC 19 /* endpoint discriminator */ +#define CI_MPPLUS 22 /* Multi-Link-Plus-Procedure */ +#define CI_LDISC 23 /* Link-Discriminator */ +#define CI_LCPAUTH 24 /* LCP Authentication */ +#define CI_COBS 25 /* Consistent Overhead Byte Stuffing */ +#define CI_PREFELIS 26 /* Prefix Elision */ +#define CI_MPHDRFMT 27 /* MP Header Format */ +#define CI_I18N 28 /* Internationalization */ +#define CI_SDL 29 /* Simple Data Link */ + +/* + * LCP-specific packet types (code numbers). + */ +#define PROTREJ 8 /* Protocol Reject */ +#define ECHOREQ 9 /* Echo Request */ +#define ECHOREP 10 /* Echo Reply */ +#define DISCREQ 11 /* Discard Request */ +#define IDENTIF 12 /* Identification */ +#define TIMEREM 13 /* Time Remaining */ + +/* Value used as data for CI_CALLBACK option */ +#define CBCP_OPT 6 /* Use callback control protocol */ + +#if 0 /* moved to ppp_opts.h */ +#define DEFMRU 1500 /* Try for this */ +#define MINMRU 128 /* No MRUs below this */ +#define MAXMRU 16384 /* Normally limit MRU to this */ +#endif /* moved to ppp_opts.h */ + +/* An endpoint discriminator, used with multilink. */ +#define MAX_ENDP_LEN 20 /* maximum length of discriminator value */ +struct epdisc { + unsigned char class_; /* -- The word "class" is reserved in C++. */ + unsigned char length; + unsigned char value[MAX_ENDP_LEN]; +}; + +/* + * The state of options is described by an lcp_options structure. + */ +typedef struct lcp_options { + unsigned int passive :1; /* Don't die if we don't get a response */ + unsigned int silent :1; /* Wait for the other end to start first */ +#if 0 /* UNUSED */ + unsigned int restart :1; /* Restart vs. exit after close */ +#endif /* UNUSED */ + unsigned int neg_mru :1; /* Negotiate the MRU? */ + unsigned int neg_asyncmap :1; /* Negotiate the async map? */ +#if PAP_SUPPORT + unsigned int neg_upap :1; /* Ask for UPAP authentication? */ +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + unsigned int neg_chap :1; /* Ask for CHAP authentication? */ +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + unsigned int neg_eap :1; /* Ask for EAP authentication? */ +#endif /* EAP_SUPPORT */ + unsigned int neg_magicnumber :1; /* Ask for magic number? */ + unsigned int neg_pcompression :1; /* HDLC Protocol Field Compression? */ + unsigned int neg_accompression :1; /* HDLC Address/Control Field Compression? */ +#if LQR_SUPPORT + unsigned int neg_lqr :1; /* Negotiate use of Link Quality Reports */ +#endif /* LQR_SUPPORT */ + unsigned int neg_cbcp :1; /* Negotiate use of CBCP */ +#ifdef HAVE_MULTILINK + unsigned int neg_mrru :1; /* negotiate multilink MRRU */ +#endif /* HAVE_MULTILINK */ + unsigned int neg_ssnhf :1; /* negotiate short sequence numbers */ + unsigned int neg_endpoint :1; /* negotiate endpoint discriminator */ + + u16_t mru; /* Value of MRU */ +#ifdef HAVE_MULTILINK + u16_t mrru; /* Value of MRRU, and multilink enable */ +#endif /* MULTILINK */ +#if CHAP_SUPPORT + u8_t chap_mdtype; /* which MD types (hashing algorithm) */ +#endif /* CHAP_SUPPORT */ + u32_t asyncmap; /* Value of async map */ + u32_t magicnumber; + u8_t numloops; /* Number of loops during magic number neg. */ +#if LQR_SUPPORT + u32_t lqr_period; /* Reporting period for LQR 1/100ths second */ +#endif /* LQR_SUPPORT */ + struct epdisc endpoint; /* endpoint discriminator */ +} lcp_options; + +void lcp_open(ppp_pcb *pcb); +void lcp_close(ppp_pcb *pcb, const char *reason); +void lcp_lowerup(ppp_pcb *pcb); +void lcp_lowerdown(ppp_pcb *pcb); +void lcp_sprotrej(ppp_pcb *pcb, u_char *p, int len); /* send protocol reject */ + +extern const struct protent lcp_protent; + +#if 0 /* moved to ppp_opts.h */ +/* Default number of times we receive our magic number from the peer + before deciding the link is looped-back. */ +#define DEFLOOPBACKFAIL 10 +#endif /* moved to ppp_opts.h */ + +#ifdef __cplusplus +} +#endif + +#endif /* LCP_H */ +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h new file mode 100644 index 0000000..a165e18 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/magic.h @@ -0,0 +1,130 @@ +/* + * magic.h - PPP Magic Number definitions. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: magic.h,v 1.5 2003/06/11 23:56:26 paulus Exp $ + */ +/***************************************************************************** +* randm.h - Random number generator header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-05-29 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef MAGIC_H +#define MAGIC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************** +*** PUBLIC FUNCTIONS *** +***********************/ + +/* + * Initialize the random number generator. + */ +void magic_init(void); + +/* + * Randomize our random seed value. To be called for truely random events + * such as user operations and network traffic. + */ +void magic_randomize(void); + +/* + * Return a new random number. + */ +u32_t magic(void); /* Returns the next magic number */ + +/* + * Fill buffer with random bytes + * + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using magic_churnrand(). + * Thus it's important to make sure that the results of this are not + * published directly because one could predict the next result to at + * least some degree. Also, it's important to get a good seed before + * the first use. + */ +void magic_random_bytes(unsigned char *buf, u32_t buf_len); + +/* + * Return a new random number between 0 and (2^pow)-1 included. + */ +u32_t magic_pow(u8_t pow); + +#ifdef __cplusplus +} +#endif + +#endif /* MAGIC_H */ + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h new file mode 100644 index 0000000..5de1128 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/mppe.h @@ -0,0 +1,181 @@ +/* + * mppe.h - Definitions for MPPE + * + * Copyright (c) 2008 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && MPPE_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef MPPE_H +#define MPPE_H + +#include "netif/ppp/pppcrypt.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MPPE_PAD 4 /* MPPE growth per frame */ +#define MPPE_MAX_KEY_LEN 16 /* largest key length (128-bit) */ + +/* option bits for ccp_options.mppe */ +#define MPPE_OPT_40 0x01 /* 40 bit */ +#define MPPE_OPT_128 0x02 /* 128 bit */ +#define MPPE_OPT_STATEFUL 0x04 /* stateful mode */ +/* unsupported opts */ +#define MPPE_OPT_56 0x08 /* 56 bit */ +#define MPPE_OPT_MPPC 0x10 /* MPPC compression */ +#define MPPE_OPT_D 0x20 /* Unknown */ +#define MPPE_OPT_UNSUPPORTED (MPPE_OPT_56|MPPE_OPT_MPPC|MPPE_OPT_D) +#define MPPE_OPT_UNKNOWN 0x40 /* Bits !defined in RFC 3078 were set */ + +/* + * This is not nice ... the alternative is a bitfield struct though. + * And unfortunately, we cannot share the same bits for the option + * names above since C and H are the same bit. We could do a u_int32 + * but then we have to do a lwip_htonl() all the time and/or we still need + * to know which octet is which. + */ +#define MPPE_C_BIT 0x01 /* MPPC */ +#define MPPE_D_BIT 0x10 /* Obsolete, usage unknown */ +#define MPPE_L_BIT 0x20 /* 40-bit */ +#define MPPE_S_BIT 0x40 /* 128-bit */ +#define MPPE_M_BIT 0x80 /* 56-bit, not supported */ +#define MPPE_H_BIT 0x01 /* Stateless (in a different byte) */ + +/* Does not include H bit; used for least significant octet only. */ +#define MPPE_ALL_BITS (MPPE_D_BIT|MPPE_L_BIT|MPPE_S_BIT|MPPE_M_BIT|MPPE_H_BIT) + +/* Build a CI from mppe opts (see RFC 3078) */ +#define MPPE_OPTS_TO_CI(opts, ci) \ + do { \ + u_char *ptr = ci; /* u_char[4] */ \ + \ + /* H bit */ \ + if (opts & MPPE_OPT_STATEFUL) \ + *ptr++ = 0x0; \ + else \ + *ptr++ = MPPE_H_BIT; \ + *ptr++ = 0; \ + *ptr++ = 0; \ + \ + /* S,L bits */ \ + *ptr = 0; \ + if (opts & MPPE_OPT_128) \ + *ptr |= MPPE_S_BIT; \ + if (opts & MPPE_OPT_40) \ + *ptr |= MPPE_L_BIT; \ + /* M,D,C bits not supported */ \ + } while (/* CONSTCOND */ 0) + +/* The reverse of the above */ +#define MPPE_CI_TO_OPTS(ci, opts) \ + do { \ + const u_char *ptr = ci; /* u_char[4] */ \ + \ + opts = 0; \ + \ + /* H bit */ \ + if (!(ptr[0] & MPPE_H_BIT)) \ + opts |= MPPE_OPT_STATEFUL; \ + \ + /* S,L bits */ \ + if (ptr[3] & MPPE_S_BIT) \ + opts |= MPPE_OPT_128; \ + if (ptr[3] & MPPE_L_BIT) \ + opts |= MPPE_OPT_40; \ + \ + /* M,D,C bits */ \ + if (ptr[3] & MPPE_M_BIT) \ + opts |= MPPE_OPT_56; \ + if (ptr[3] & MPPE_D_BIT) \ + opts |= MPPE_OPT_D; \ + if (ptr[3] & MPPE_C_BIT) \ + opts |= MPPE_OPT_MPPC; \ + \ + /* Other bits */ \ + if (ptr[0] & ~MPPE_H_BIT) \ + opts |= MPPE_OPT_UNKNOWN; \ + if (ptr[1] || ptr[2]) \ + opts |= MPPE_OPT_UNKNOWN; \ + if (ptr[3] & ~MPPE_ALL_BITS) \ + opts |= MPPE_OPT_UNKNOWN; \ + } while (/* CONSTCOND */ 0) + +/* Shared MPPE padding between MSCHAP and MPPE */ +#define SHA1_PAD_SIZE 40 + +static const u8_t mppe_sha1_pad1[SHA1_PAD_SIZE] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +static const u8_t mppe_sha1_pad2[SHA1_PAD_SIZE] = { + 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, + 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, + 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, + 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2, 0xf2 +}; + +/* + * State for an MPPE (de)compressor. + */ +typedef struct ppp_mppe_state { + lwip_arc4_context arc4; + u8_t master_key[MPPE_MAX_KEY_LEN]; + u8_t session_key[MPPE_MAX_KEY_LEN]; + u8_t keylen; /* key length in bytes */ + /* NB: 128-bit == 16, 40-bit == 8! + * If we want to support 56-bit, the unit has to change to bits + */ + u8_t bits; /* MPPE control bits */ + u16_t ccount; /* 12-bit coherency count (seqno) */ + u16_t sanity_errors; /* take down LCP if too many */ + unsigned int stateful :1; /* stateful mode flag */ + unsigned int discard :1; /* stateful mode packet loss flag */ +} ppp_mppe_state; + +void mppe_set_key(ppp_pcb *pcb, ppp_mppe_state *state, u8_t *key); +void mppe_init(ppp_pcb *pcb, ppp_mppe_state *state, u8_t options); +void mppe_comp_reset(ppp_pcb *pcb, ppp_mppe_state *state); +err_t mppe_compress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb, u16_t protocol); +void mppe_decomp_reset(ppp_pcb *pcb, ppp_mppe_state *state); +err_t mppe_decompress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb); + +#ifdef __cplusplus +} +#endif + +#endif /* MPPE_H */ +#endif /* PPP_SUPPORT && MPPE_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h new file mode 100644 index 0000000..3d73c36 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp.h @@ -0,0 +1,698 @@ +/***************************************************************************** +* ppp.h - Network Point to Point Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef PPP_H +#define PPP_H + +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/mem.h" +#include "lwip/netif.h" +#include "lwip/sys.h" +#include "lwip/timeouts.h" +#if PPP_IPV6_SUPPORT +#include "lwip/ip6_addr.h" +#endif /* PPP_IPV6_SUPPORT */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Disable non-working or rarely used PPP feature, so rarely that we don't want to bloat ppp_opts.h with them */ +#ifndef PPP_OPTIONS +#define PPP_OPTIONS 0 +#endif + +#ifndef PPP_NOTIFY +#define PPP_NOTIFY 0 +#endif + +#ifndef PPP_REMOTENAME +#define PPP_REMOTENAME 0 +#endif + +#ifndef PPP_IDLETIMELIMIT +#define PPP_IDLETIMELIMIT 0 +#endif + +#ifndef PPP_LCP_ADAPTIVE +#define PPP_LCP_ADAPTIVE 0 +#endif + +#ifndef PPP_MAXCONNECT +#define PPP_MAXCONNECT 0 +#endif + +#ifndef PPP_ALLOWED_ADDRS +#define PPP_ALLOWED_ADDRS 0 +#endif + +#ifndef PPP_PROTOCOLNAME +#define PPP_PROTOCOLNAME 0 +#endif + +#ifndef PPP_STATS_SUPPORT +#define PPP_STATS_SUPPORT 0 +#endif + +#ifndef DEFLATE_SUPPORT +#define DEFLATE_SUPPORT 0 +#endif + +#ifndef BSDCOMPRESS_SUPPORT +#define BSDCOMPRESS_SUPPORT 0 +#endif + +#ifndef PREDICTOR_SUPPORT +#define PREDICTOR_SUPPORT 0 +#endif + +/************************* +*** PUBLIC DEFINITIONS *** +*************************/ + +/* + * The basic PPP frame. + */ +#define PPP_HDRLEN 4 /* octets for standard ppp header */ +#define PPP_FCSLEN 2 /* octets for FCS */ + +/* + * Values for phase. + */ +#define PPP_PHASE_DEAD 0 +#define PPP_PHASE_MASTER 1 +#define PPP_PHASE_HOLDOFF 2 +#define PPP_PHASE_INITIALIZE 3 +#define PPP_PHASE_SERIALCONN 4 +#define PPP_PHASE_DORMANT 5 +#define PPP_PHASE_ESTABLISH 6 +#define PPP_PHASE_AUTHENTICATE 7 +#define PPP_PHASE_CALLBACK 8 +#define PPP_PHASE_NETWORK 9 +#define PPP_PHASE_RUNNING 10 +#define PPP_PHASE_TERMINATE 11 +#define PPP_PHASE_DISCONNECT 12 + +/* Error codes. */ +#define PPPERR_NONE 0 /* No error. */ +#define PPPERR_PARAM 1 /* Invalid parameter. */ +#define PPPERR_OPEN 2 /* Unable to open PPP session. */ +#define PPPERR_DEVICE 3 /* Invalid I/O device for PPP. */ +#define PPPERR_ALLOC 4 /* Unable to allocate resources. */ +#define PPPERR_USER 5 /* User interrupt. */ +#define PPPERR_CONNECT 6 /* Connection lost. */ +#define PPPERR_AUTHFAIL 7 /* Failed authentication challenge. */ +#define PPPERR_PROTOCOL 8 /* Failed to meet protocol. */ +#define PPPERR_PEERDEAD 9 /* Connection timeout */ +#define PPPERR_IDLETIMEOUT 10 /* Idle Timeout */ +#define PPPERR_CONNECTTIME 11 /* Max connect time reached */ +#define PPPERR_LOOPBACK 12 /* Loopback detected */ + +/* Whether auth support is enabled at all */ +#define PPP_AUTH_SUPPORT (PAP_SUPPORT || CHAP_SUPPORT || EAP_SUPPORT) + +/************************ +*** PUBLIC DATA TYPES *** +************************/ + +/* + * Other headers require ppp_pcb definition for prototypes, but ppp_pcb + * require some structure definition from other headers as well, we are + * fixing the dependency loop here by declaring the ppp_pcb type then + * by including headers containing necessary struct definition for ppp_pcb + */ +typedef struct ppp_pcb_s ppp_pcb; + +/* Type definitions for BSD code. */ +#ifndef __u_char_defined +typedef unsigned long u_long; +typedef unsigned int u_int; +typedef unsigned short u_short; +typedef unsigned char u_char; +#endif + +#include "fsm.h" +#include "lcp.h" +#if CCP_SUPPORT +#include "ccp.h" +#endif /* CCP_SUPPORT */ +#if MPPE_SUPPORT +#include "mppe.h" +#endif /* MPPE_SUPPORT */ +#if PPP_IPV4_SUPPORT +#include "ipcp.h" +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT +#include "ipv6cp.h" +#endif /* PPP_IPV6_SUPPORT */ +#if PAP_SUPPORT +#include "upap.h" +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT +#include "chap-new.h" +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT +#include "eap.h" +#endif /* EAP_SUPPORT */ +#if VJ_SUPPORT +#include "vj.h" +#endif /* VJ_SUPPORT */ + +/* Link status callback function prototype */ +typedef void (*ppp_link_status_cb_fn)(ppp_pcb *pcb, int err_code, void *ctx); + +/* + * PPP configuration. + */ +typedef struct ppp_settings_s { + +#if PPP_SERVER && PPP_AUTH_SUPPORT + unsigned int auth_required :1; /* Peer is required to authenticate */ + unsigned int null_login :1; /* Username of "" and a password of "" are acceptable */ +#endif /* PPP_SERVER && PPP_AUTH_SUPPORT */ +#if PPP_REMOTENAME + unsigned int explicit_remote :1; /* remote_name specified with remotename opt */ +#endif /* PPP_REMOTENAME */ +#if PAP_SUPPORT + unsigned int refuse_pap :1; /* Don't proceed auth. with PAP */ +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + unsigned int refuse_chap :1; /* Don't proceed auth. with CHAP */ +#endif /* CHAP_SUPPORT */ +#if MSCHAP_SUPPORT + unsigned int refuse_mschap :1; /* Don't proceed auth. with MS-CHAP */ + unsigned int refuse_mschap_v2 :1; /* Don't proceed auth. with MS-CHAPv2 */ +#endif /* MSCHAP_SUPPORT */ +#if EAP_SUPPORT + unsigned int refuse_eap :1; /* Don't proceed auth. with EAP */ +#endif /* EAP_SUPPORT */ +#if LWIP_DNS + unsigned int usepeerdns :1; /* Ask peer for DNS adds */ +#endif /* LWIP_DNS */ + unsigned int persist :1; /* Persist mode, always try to open the connection */ +#if PRINTPKT_SUPPORT + unsigned int hide_password :1; /* Hide password in dumped packets */ +#endif /* PRINTPKT_SUPPORT */ + unsigned int noremoteip :1; /* Let him have no IP address */ + unsigned int lax_recv :1; /* accept control chars in asyncmap */ + unsigned int noendpoint :1; /* don't send/accept endpoint discriminator */ +#if PPP_LCP_ADAPTIVE + unsigned int lcp_echo_adaptive :1; /* request echo only if the link was idle */ +#endif /* PPP_LCP_ADAPTIVE */ +#if MPPE_SUPPORT + unsigned int require_mppe :1; /* Require MPPE (Microsoft Point to Point Encryption) */ + unsigned int refuse_mppe_40 :1; /* Allow MPPE 40-bit mode? */ + unsigned int refuse_mppe_128 :1; /* Allow MPPE 128-bit mode? */ + unsigned int refuse_mppe_stateful :1; /* Allow MPPE stateful mode? */ +#endif /* MPPE_SUPPORT */ + + u16_t listen_time; /* time to listen first (ms), waiting for peer to send LCP packet */ + +#if PPP_IDLETIMELIMIT + u16_t idle_time_limit; /* Disconnect if idle for this many seconds */ +#endif /* PPP_IDLETIMELIMIT */ +#if PPP_MAXCONNECT + u32_t maxconnect; /* Maximum connect time (seconds) */ +#endif /* PPP_MAXCONNECT */ + +#if PPP_AUTH_SUPPORT + /* auth data */ + const char *user; /* Username for PAP */ + const char *passwd; /* Password for PAP, secret for CHAP */ +#if PPP_REMOTENAME + char remote_name[MAXNAMELEN + 1]; /* Peer's name for authentication */ +#endif /* PPP_REMOTENAME */ + +#if PAP_SUPPORT + u8_t pap_timeout_time; /* Timeout (seconds) for auth-req retrans. */ + u8_t pap_max_transmits; /* Number of auth-reqs sent */ +#if PPP_SERVER + u8_t pap_req_timeout; /* Time to wait for auth-req from peer */ +#endif /* PPP_SERVER */ +#endif /* PAP_SUPPPORT */ + +#if CHAP_SUPPORT + u8_t chap_timeout_time; /* Timeout (seconds) for retransmitting req */ + u8_t chap_max_transmits; /* max # times to send challenge */ +#if PPP_SERVER + u8_t chap_rechallenge_time; /* Time to wait for auth-req from peer */ +#endif /* PPP_SERVER */ +#endif /* CHAP_SUPPPORT */ + +#if EAP_SUPPORT + u8_t eap_req_time; /* Time to wait (for retransmit/fail) */ + u8_t eap_allow_req; /* Max Requests allowed */ +#if PPP_SERVER + u8_t eap_timeout_time; /* Time to wait (for retransmit/fail) */ + u8_t eap_max_transmits; /* Max Requests allowed */ +#endif /* PPP_SERVER */ +#endif /* EAP_SUPPORT */ + +#endif /* PPP_AUTH_SUPPORT */ + + u8_t fsm_timeout_time; /* Timeout time in seconds */ + u8_t fsm_max_conf_req_transmits; /* Maximum Configure-Request transmissions */ + u8_t fsm_max_term_transmits; /* Maximum Terminate-Request transmissions */ + u8_t fsm_max_nak_loops; /* Maximum number of nak loops tolerated */ + + u8_t lcp_loopbackfail; /* Number of times we receive our magic number from the peer + before deciding the link is looped-back. */ + u8_t lcp_echo_interval; /* Interval between LCP echo-requests */ + u8_t lcp_echo_fails; /* Tolerance to unanswered echo-requests */ + +} ppp_settings; + +#if PPP_SERVER +struct ppp_addrs { +#if PPP_IPV4_SUPPORT + ip4_addr_t our_ipaddr, his_ipaddr, netmask; +#if LWIP_DNS + ip4_addr_t dns1, dns2; +#endif /* LWIP_DNS */ +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT + ip6_addr_t our6_ipaddr, his6_ipaddr; +#endif /* PPP_IPV6_SUPPORT */ +}; +#endif /* PPP_SERVER */ + +/* + * PPP interface control block. + */ +struct ppp_pcb_s { + ppp_settings settings; + const struct link_callbacks *link_cb; + void *link_ctx_cb; + void (*link_status_cb)(ppp_pcb *pcb, int err_code, void *ctx); /* Status change callback */ +#if PPP_NOTIFY_PHASE + void (*notify_phase_cb)(ppp_pcb *pcb, u8_t phase, void *ctx); /* Notify phase callback */ +#endif /* PPP_NOTIFY_PHASE */ + void *ctx_cb; /* Callbacks optional pointer */ + struct netif *netif; /* PPP interface */ + u8_t phase; /* where the link is at */ + u8_t err_code; /* Code indicating why interface is down. */ + + /* flags */ +#if PPP_IPV4_SUPPORT + unsigned int ask_for_local :1; /* request our address from peer */ + unsigned int ipcp_is_open :1; /* haven't called np_finished() */ + unsigned int ipcp_is_up :1; /* have called ipcp_up() */ + unsigned int if4_up :1; /* True when the IPv4 interface is up. */ +#if 0 /* UNUSED - PROXY ARP */ + unsigned int proxy_arp_set :1; /* Have created proxy arp entry */ +#endif /* UNUSED - PROXY ARP */ +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT + unsigned int ipv6cp_is_up :1; /* have called ip6cp_up() */ + unsigned int if6_up :1; /* True when the IPv6 interface is up. */ +#endif /* PPP_IPV6_SUPPORT */ + unsigned int lcp_echo_timer_running :1; /* set if a timer is running */ +#if VJ_SUPPORT + unsigned int vj_enabled :1; /* Flag indicating VJ compression enabled. */ +#endif /* VJ_SUPPORT */ +#if CCP_SUPPORT + unsigned int ccp_all_rejected :1; /* we rejected all peer's options */ +#endif /* CCP_SUPPORT */ +#if MPPE_SUPPORT + unsigned int mppe_keys_set :1; /* Have the MPPE keys been set? */ +#endif /* MPPE_SUPPORT */ + +#if PPP_AUTH_SUPPORT + /* auth data */ +#if PPP_SERVER && defined(HAVE_MULTILINK) + char peer_authname[MAXNAMELEN + 1]; /* The name by which the peer authenticated itself to us. */ +#endif /* PPP_SERVER && defined(HAVE_MULTILINK) */ + u16_t auth_pending; /* Records which authentication operations haven't completed yet. */ + u16_t auth_done; /* Records which authentication operations have been completed. */ + +#if PAP_SUPPORT + upap_state upap; /* PAP data */ +#endif /* PAP_SUPPORT */ + +#if CHAP_SUPPORT + chap_client_state chap_client; /* CHAP client data */ +#if PPP_SERVER + chap_server_state chap_server; /* CHAP server data */ +#endif /* PPP_SERVER */ +#endif /* CHAP_SUPPORT */ + +#if EAP_SUPPORT + eap_state eap; /* EAP data */ +#endif /* EAP_SUPPORT */ +#endif /* PPP_AUTH_SUPPORT */ + + fsm lcp_fsm; /* LCP fsm structure */ + lcp_options lcp_wantoptions; /* Options that we want to request */ + lcp_options lcp_gotoptions; /* Options that peer ack'd */ + lcp_options lcp_allowoptions; /* Options we allow peer to request */ + lcp_options lcp_hisoptions; /* Options that we ack'd */ + u16_t peer_mru; /* currently negotiated peer MRU */ + u8_t lcp_echos_pending; /* Number of outstanding echo msgs */ + u8_t lcp_echo_number; /* ID number of next echo frame */ + + u8_t num_np_open; /* Number of network protocols which we have opened. */ + u8_t num_np_up; /* Number of network protocols which have come up. */ + +#if VJ_SUPPORT + struct vjcompress vj_comp; /* Van Jacobson compression header. */ +#endif /* VJ_SUPPORT */ + +#if CCP_SUPPORT + fsm ccp_fsm; /* CCP fsm structure */ + ccp_options ccp_wantoptions; /* what to request the peer to use */ + ccp_options ccp_gotoptions; /* what the peer agreed to do */ + ccp_options ccp_allowoptions; /* what we'll agree to do */ + ccp_options ccp_hisoptions; /* what we agreed to do */ + u8_t ccp_localstate; /* Local state (mainly for handling reset-reqs and reset-acks). */ + u8_t ccp_receive_method; /* Method chosen on receive path */ + u8_t ccp_transmit_method; /* Method chosen on transmit path */ +#if MPPE_SUPPORT + ppp_mppe_state mppe_comp; /* MPPE "compressor" structure */ + ppp_mppe_state mppe_decomp; /* MPPE "decompressor" structure */ +#endif /* MPPE_SUPPORT */ +#endif /* CCP_SUPPORT */ + +#if PPP_IPV4_SUPPORT + fsm ipcp_fsm; /* IPCP fsm structure */ + ipcp_options ipcp_wantoptions; /* Options that we want to request */ + ipcp_options ipcp_gotoptions; /* Options that peer ack'd */ + ipcp_options ipcp_allowoptions; /* Options we allow peer to request */ + ipcp_options ipcp_hisoptions; /* Options that we ack'd */ +#endif /* PPP_IPV4_SUPPORT */ + +#if PPP_IPV6_SUPPORT + fsm ipv6cp_fsm; /* IPV6CP fsm structure */ + ipv6cp_options ipv6cp_wantoptions; /* Options that we want to request */ + ipv6cp_options ipv6cp_gotoptions; /* Options that peer ack'd */ + ipv6cp_options ipv6cp_allowoptions; /* Options we allow peer to request */ + ipv6cp_options ipv6cp_hisoptions; /* Options that we ack'd */ +#endif /* PPP_IPV6_SUPPORT */ +}; + +/************************ + *** PUBLIC FUNCTIONS *** + ************************/ + +/* + * WARNING: For multi-threads environment, all ppp_set_* functions most + * only be called while the PPP is in the dead phase (i.e. disconnected). + */ + +#if PPP_AUTH_SUPPORT +/* + * Set PPP authentication. + * + * Warning: Using PPPAUTHTYPE_ANY might have security consequences. + * RFC 1994 says: + * + * In practice, within or associated with each PPP server, there is a + * database which associates "user" names with authentication + * information ("secrets"). It is not anticipated that a particular + * named user would be authenticated by multiple methods. This would + * make the user vulnerable to attacks which negotiate the least secure + * method from among a set (such as PAP rather than CHAP). If the same + * secret was used, PAP would reveal the secret to be used later with + * CHAP. + * + * Instead, for each user name there should be an indication of exactly + * one method used to authenticate that user name. If a user needs to + * make use of different authentication methods under different + * circumstances, then distinct user names SHOULD be employed, each of + * which identifies exactly one authentication method. + * + * Default is none auth type, unset (NULL) user and passwd. + */ +#define PPPAUTHTYPE_NONE 0x00 +#define PPPAUTHTYPE_PAP 0x01 +#define PPPAUTHTYPE_CHAP 0x02 +#define PPPAUTHTYPE_MSCHAP 0x04 +#define PPPAUTHTYPE_MSCHAP_V2 0x08 +#define PPPAUTHTYPE_EAP 0x10 +#define PPPAUTHTYPE_ANY 0xff +void ppp_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd); + +/* + * If set, peer is required to authenticate. This is mostly necessary for PPP server support. + * + * Default is false. + */ +#define ppp_set_auth_required(ppp, boolval) (ppp->settings.auth_required = boolval) +#endif /* PPP_AUTH_SUPPORT */ + +#if PPP_IPV4_SUPPORT +/* + * Set PPP interface "our" and "his" IPv4 addresses. This is mostly necessary for PPP server + * support but it can also be used on a PPP link where each side choose its own IP address. + * + * Default is unset (0.0.0.0). + */ +#define ppp_set_ipcp_ouraddr(ppp, addr) do { ppp->ipcp_wantoptions.ouraddr = ip4_addr_get_u32(addr); \ + ppp->ask_for_local = ppp->ipcp_wantoptions.ouraddr != 0; } while(0) +#define ppp_set_ipcp_hisaddr(ppp, addr) (ppp->ipcp_wantoptions.hisaddr = ip4_addr_get_u32(addr)) +#if LWIP_DNS +/* + * Set DNS server addresses that are sent if the peer asks for them. This is mostly necessary + * for PPP server support. + * + * Default is unset (0.0.0.0). + */ +#define ppp_set_ipcp_dnsaddr(ppp, index, addr) (ppp->ipcp_allowoptions.dnsaddr[index] = ip4_addr_get_u32(addr)) + +/* + * If set, we ask the peer for up to 2 DNS server addresses. Received DNS server addresses are + * registered using the dns_setserver() function. + * + * Default is false. + */ +#define ppp_set_usepeerdns(ppp, boolval) (ppp->settings.usepeerdns = boolval) +#endif /* LWIP_DNS */ +#endif /* PPP_IPV4_SUPPORT */ + +#if MPPE_SUPPORT +/* Disable MPPE (Microsoft Point to Point Encryption). This parameter is exclusive. */ +#define PPP_MPPE_DISABLE 0x00 +/* Require the use of MPPE (Microsoft Point to Point Encryption). */ +#define PPP_MPPE_ENABLE 0x01 +/* Allow MPPE to use stateful mode. Stateless mode is still attempted first. */ +#define PPP_MPPE_ALLOW_STATEFUL 0x02 +/* Refuse the use of MPPE with 40-bit encryption. Conflict with PPP_MPPE_REFUSE_128. */ +#define PPP_MPPE_REFUSE_40 0x04 +/* Refuse the use of MPPE with 128-bit encryption. Conflict with PPP_MPPE_REFUSE_40. */ +#define PPP_MPPE_REFUSE_128 0x08 +/* + * Set MPPE configuration + * + * Default is disabled. + */ +void ppp_set_mppe(ppp_pcb *pcb, u8_t flags); +#endif /* MPPE_SUPPORT */ + +/* + * Wait for up to intval milliseconds for a valid PPP packet from the peer. + * At the end of this time, or when a valid PPP packet is received from the + * peer, we commence negotiation by sending our first LCP packet. + * + * Default is 0. + */ +#define ppp_set_listen_time(ppp, intval) (ppp->settings.listen_time = intval) + +/* + * If set, we will attempt to initiate a connection but if no reply is received from + * the peer, we will then just wait passively for a valid LCP packet from the peer. + * + * Default is false. + */ +#define ppp_set_passive(ppp, boolval) (ppp->lcp_wantoptions.passive = boolval) + +/* + * If set, we will not transmit LCP packets to initiate a connection until a valid + * LCP packet is received from the peer. This is what we usually call the server mode. + * + * Default is false. + */ +#define ppp_set_silent(ppp, boolval) (ppp->lcp_wantoptions.silent = boolval) + +/* + * If set, enable protocol field compression negotiation in both the receive and + * the transmit direction. + * + * Default is true. + */ +#define ppp_set_neg_pcomp(ppp, boolval) (ppp->lcp_wantoptions.neg_pcompression = \ + ppp->lcp_allowoptions.neg_pcompression = boolval) + +/* + * If set, enable Address/Control compression in both the receive and the transmit + * direction. + * + * Default is true. + */ +#define ppp_set_neg_accomp(ppp, boolval) (ppp->lcp_wantoptions.neg_accompression = \ + ppp->lcp_allowoptions.neg_accompression = boolval) + +/* + * If set, enable asyncmap negotiation. Otherwise forcing all control characters to + * be escaped for both the transmit and the receive direction. + * + * Default is true. + */ +#define ppp_set_neg_asyncmap(ppp, boolval) (ppp->lcp_wantoptions.neg_asyncmap = \ + ppp->lcp_allowoptions.neg_asyncmap = boolval) + +/* + * This option sets the Async-Control-Character-Map (ACCM) for this end of the link. + * The ACCM is a set of 32 bits, one for each of the ASCII control characters with + * values from 0 to 31, where a 1 bit indicates that the corresponding control + * character should not be used in PPP packets sent to this system. The map is + * an unsigned 32 bits integer where the least significant bit (00000001) represents + * character 0 and the most significant bit (80000000) represents character 31. + * We will then ask the peer to send these characters as a 2-byte escape sequence. + * + * Default is 0. + */ +#define ppp_set_asyncmap(ppp, intval) (ppp->lcp_wantoptions.asyncmap = intval) + +/* + * Set a PPP interface as the default network interface + * (used to output all packets for which no specific route is found). + */ +#define ppp_set_default(ppp) netif_set_default(ppp->netif) + +#if PPP_NOTIFY_PHASE +/* + * Set a PPP notify phase callback. + * + * This can be used for example to set a LED pattern depending on the + * current phase of the PPP session. + */ +typedef void (*ppp_notify_phase_cb_fn)(ppp_pcb *pcb, u8_t phase, void *ctx); +void ppp_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb); +#endif /* PPP_NOTIFY_PHASE */ + +/* + * Initiate a PPP connection. + * + * This can only be called if PPP is in the dead phase. + * + * Holdoff is the time to wait (in seconds) before initiating + * the connection. + * + * If this port connects to a modem, the modem connection must be + * established before calling this. + */ +err_t ppp_connect(ppp_pcb *pcb, u16_t holdoff); + +#if PPP_SERVER +/* + * Listen for an incoming PPP connection. + * + * This can only be called if PPP is in the dead phase. + * + * If this port connects to a modem, the modem connection must be + * established before calling this. + */ +err_t ppp_listen(ppp_pcb *pcb); +#endif /* PPP_SERVER */ + +/* + * Initiate the end of a PPP connection. + * Any outstanding packets in the queues are dropped. + * + * Setting nocarrier to 1 close the PPP connection without initiating the + * shutdown procedure. Always using nocarrier = 0 is still recommended, + * this is going to take a little longer time if your link is down, but + * is a safer choice for the PPP state machine. + * + * Return 0 on success, an error code on failure. + */ +err_t ppp_close(ppp_pcb *pcb, u8_t nocarrier); + +/* + * Release the control block. + * + * This can only be called if PPP is in the dead phase. + * + * You must use ppp_close() before if you wish to terminate + * an established PPP session. + * + * Return 0 on success, an error code on failure. + */ +err_t ppp_free(ppp_pcb *pcb); + +/* + * PPP IOCTL commands. + * + * Get the up status - 0 for down, non-zero for up. The argument must + * point to an int. + */ +#define PPPCTLG_UPSTATUS 0 + +/* + * Get the PPP error code. The argument must point to an int. + * Returns a PPPERR_* value. + */ +#define PPPCTLG_ERRCODE 1 + +/* + * Get the fd associated with a PPP over serial + */ +#define PPPCTLG_FD 2 + +/* + * Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. + */ +err_t ppp_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg); + +/* Get the PPP netif interface */ +#define ppp_netif(ppp) (ppp->netif) + +/* Set an lwIP-style status-callback for the selected PPP device */ +#define ppp_set_netif_statuscallback(ppp, status_cb) \ + netif_set_status_callback(ppp->netif, status_cb); + +/* Set an lwIP-style link-callback for the selected PPP device */ +#define ppp_set_netif_linkcallback(ppp, link_cb) \ + netif_set_link_callback(ppp->netif, link_cb); + +#ifdef __cplusplus +} +#endif + +#endif /* PPP_H */ + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h new file mode 100644 index 0000000..40843d5 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_impl.h @@ -0,0 +1,722 @@ +/***************************************************************************** +* ppp.h - Network Point to Point Protocol header file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original derived from BSD codes. +*****************************************************************************/ +#ifndef LWIP_HDR_PPP_IMPL_H +#define LWIP_HDR_PPP_IMPL_H + +#include "netif/ppp/ppp_opts.h" + +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifdef PPP_INCLUDE_SETTINGS_HEADER +#include "ppp_settings.h" +#endif + +#include /* formats */ +#include +#include +#include /* strtol() */ + +#include "lwip/netif.h" +#include "lwip/def.h" +#include "lwip/timeouts.h" + +#include "ppp.h" +#include "pppdebug.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Memory used for control packets. + * + * PPP_CTRL_PBUF_MAX_SIZE is the amount of memory we allocate when we + * cannot figure out how much we are going to use before filling the buffer. + */ +#if PPP_USE_PBUF_RAM +#define PPP_CTRL_PBUF_TYPE PBUF_RAM +#define PPP_CTRL_PBUF_MAX_SIZE 512 +#else /* PPP_USE_PBUF_RAM */ +#define PPP_CTRL_PBUF_TYPE PBUF_POOL +#define PPP_CTRL_PBUF_MAX_SIZE PBUF_POOL_BUFSIZE +#endif /* PPP_USE_PBUF_RAM */ + +/* + * The basic PPP frame. + */ +#define PPP_ADDRESS(p) (((u_char *)(p))[0]) +#define PPP_CONTROL(p) (((u_char *)(p))[1]) +#define PPP_PROTOCOL(p) ((((u_char *)(p))[2] << 8) + ((u_char *)(p))[3]) + +/* + * Significant octet values. + */ +#define PPP_ALLSTATIONS 0xff /* All-Stations broadcast address */ +#define PPP_UI 0x03 /* Unnumbered Information */ +#define PPP_FLAG 0x7e /* Flag Sequence */ +#define PPP_ESCAPE 0x7d /* Asynchronous Control Escape */ +#define PPP_TRANS 0x20 /* Asynchronous transparency modifier */ + +/* + * Protocol field values. + */ +#define PPP_IP 0x21 /* Internet Protocol */ +#if 0 /* UNUSED */ +#define PPP_AT 0x29 /* AppleTalk Protocol */ +#define PPP_IPX 0x2b /* IPX protocol */ +#endif /* UNUSED */ +#if VJ_SUPPORT +#define PPP_VJC_COMP 0x2d /* VJ compressed TCP */ +#define PPP_VJC_UNCOMP 0x2f /* VJ uncompressed TCP */ +#endif /* VJ_SUPPORT */ +#if PPP_IPV6_SUPPORT +#define PPP_IPV6 0x57 /* Internet Protocol Version 6 */ +#endif /* PPP_IPV6_SUPPORT */ +#if CCP_SUPPORT +#define PPP_COMP 0xfd /* compressed packet */ +#endif /* CCP_SUPPORT */ +#define PPP_IPCP 0x8021 /* IP Control Protocol */ +#if 0 /* UNUSED */ +#define PPP_ATCP 0x8029 /* AppleTalk Control Protocol */ +#define PPP_IPXCP 0x802b /* IPX Control Protocol */ +#endif /* UNUSED */ +#if PPP_IPV6_SUPPORT +#define PPP_IPV6CP 0x8057 /* IPv6 Control Protocol */ +#endif /* PPP_IPV6_SUPPORT */ +#if CCP_SUPPORT +#define PPP_CCP 0x80fd /* Compression Control Protocol */ +#endif /* CCP_SUPPORT */ +#if ECP_SUPPORT +#define PPP_ECP 0x8053 /* Encryption Control Protocol */ +#endif /* ECP_SUPPORT */ +#define PPP_LCP 0xc021 /* Link Control Protocol */ +#if PAP_SUPPORT +#define PPP_PAP 0xc023 /* Password Authentication Protocol */ +#endif /* PAP_SUPPORT */ +#if LQR_SUPPORT +#define PPP_LQR 0xc025 /* Link Quality Report protocol */ +#endif /* LQR_SUPPORT */ +#if CHAP_SUPPORT +#define PPP_CHAP 0xc223 /* Cryptographic Handshake Auth. Protocol */ +#endif /* CHAP_SUPPORT */ +#if CBCP_SUPPORT +#define PPP_CBCP 0xc029 /* Callback Control Protocol */ +#endif /* CBCP_SUPPORT */ +#if EAP_SUPPORT +#define PPP_EAP 0xc227 /* Extensible Authentication Protocol */ +#endif /* EAP_SUPPORT */ + +/* + * The following struct gives the addresses of procedures to call + * for a particular lower link level protocol. + */ +struct link_callbacks { + /* Start a connection (e.g. Initiate discovery phase) */ + void (*connect) (ppp_pcb *pcb, void *ctx); +#if PPP_SERVER + /* Listen for an incoming connection (Passive mode) */ + void (*listen) (ppp_pcb *pcb, void *ctx); +#endif /* PPP_SERVER */ + /* End a connection (i.e. initiate disconnect phase) */ + void (*disconnect) (ppp_pcb *pcb, void *ctx); + /* Free lower protocol control block */ + err_t (*free) (ppp_pcb *pcb, void *ctx); + /* Write a pbuf to a ppp link, only used from PPP functions to send PPP packets. */ + err_t (*write)(ppp_pcb *pcb, void *ctx, struct pbuf *p); + /* Send a packet from lwIP core (IPv4 or IPv6) */ + err_t (*netif_output)(ppp_pcb *pcb, void *ctx, struct pbuf *p, u_short protocol); + /* configure the transmit-side characteristics of the PPP interface */ + void (*send_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp); + /* confire the receive-side characteristics of the PPP interface */ + void (*recv_config)(ppp_pcb *pcb, void *ctx, u32_t accm, int pcomp, int accomp); +}; + +/* + * What to do with network protocol (NP) packets. + */ +enum NPmode { + NPMODE_PASS, /* pass the packet through */ + NPMODE_DROP, /* silently drop the packet */ + NPMODE_ERROR, /* return an error */ + NPMODE_QUEUE /* save it up for later. */ +}; + +/* + * Statistics. + */ +#if PPP_STATS_SUPPORT +struct pppstat { + unsigned int ppp_ibytes; /* bytes received */ + unsigned int ppp_ipackets; /* packets received */ + unsigned int ppp_ierrors; /* receive errors */ + unsigned int ppp_obytes; /* bytes sent */ + unsigned int ppp_opackets; /* packets sent */ + unsigned int ppp_oerrors; /* transmit errors */ +}; + +#if VJ_SUPPORT +struct vjstat { + unsigned int vjs_packets; /* outbound packets */ + unsigned int vjs_compressed; /* outbound compressed packets */ + unsigned int vjs_searches; /* searches for connection state */ + unsigned int vjs_misses; /* times couldn't find conn. state */ + unsigned int vjs_uncompressedin; /* inbound uncompressed packets */ + unsigned int vjs_compressedin; /* inbound compressed packets */ + unsigned int vjs_errorin; /* inbound unknown type packets */ + unsigned int vjs_tossed; /* inbound packets tossed because of error */ +}; +#endif /* VJ_SUPPORT */ + +struct ppp_stats { + struct pppstat p; /* basic PPP statistics */ +#if VJ_SUPPORT + struct vjstat vj; /* VJ header compression statistics */ +#endif /* VJ_SUPPORT */ +}; + +#if CCP_SUPPORT +struct compstat { + unsigned int unc_bytes; /* total uncompressed bytes */ + unsigned int unc_packets; /* total uncompressed packets */ + unsigned int comp_bytes; /* compressed bytes */ + unsigned int comp_packets; /* compressed packets */ + unsigned int inc_bytes; /* incompressible bytes */ + unsigned int inc_packets; /* incompressible packets */ + unsigned int ratio; /* recent compression ratio << 8 */ +}; + +struct ppp_comp_stats { + struct compstat c; /* packet compression statistics */ + struct compstat d; /* packet decompression statistics */ +}; +#endif /* CCP_SUPPORT */ + +#endif /* PPP_STATS_SUPPORT */ + +#if PPP_IDLETIMELIMIT +/* + * The following structure records the time in seconds since + * the last NP packet was sent or received. + */ +struct ppp_idle { + time_t xmit_idle; /* time since last NP packet sent */ + time_t recv_idle; /* time since last NP packet received */ +}; +#endif /* PPP_IDLETIMELIMIT */ + +/* values for epdisc.class */ +#define EPD_NULL 0 /* null discriminator, no data */ +#define EPD_LOCAL 1 +#define EPD_IP 2 +#define EPD_MAC 3 +#define EPD_MAGIC 4 +#define EPD_PHONENUM 5 + +/* + * Global variables. + */ +#ifdef HAVE_MULTILINK +extern u8_t multilink; /* enable multilink operation */ +extern u8_t doing_multilink; +extern u8_t multilink_master; +extern u8_t bundle_eof; +extern u8_t bundle_terminating; +#endif + +#ifdef MAXOCTETS +extern unsigned int maxoctets; /* Maximum octetes per session (in bytes) */ +extern int maxoctets_dir; /* Direction : + 0 - in+out (default) + 1 - in + 2 - out + 3 - max(in,out) */ +extern int maxoctets_timeout; /* Timeout for check of octets limit */ +#define PPP_OCTETS_DIRECTION_SUM 0 +#define PPP_OCTETS_DIRECTION_IN 1 +#define PPP_OCTETS_DIRECTION_OUT 2 +#define PPP_OCTETS_DIRECTION_MAXOVERAL 3 +/* same as previos, but little different on RADIUS side */ +#define PPP_OCTETS_DIRECTION_MAXSESSION 4 +#endif + +/* Data input may be used by CCP and ECP, remove this entry + * from struct protent to save some flash + */ +#define PPP_DATAINPUT 0 + +/* + * The following struct gives the addresses of procedures to call + * for a particular protocol. + */ +struct protent { + u_short protocol; /* PPP protocol number */ + /* Initialization procedure */ + void (*init) (ppp_pcb *pcb); + /* Process a received packet */ + void (*input) (ppp_pcb *pcb, u_char *pkt, int len); + /* Process a received protocol-reject */ + void (*protrej) (ppp_pcb *pcb); + /* Lower layer has come up */ + void (*lowerup) (ppp_pcb *pcb); + /* Lower layer has gone down */ + void (*lowerdown) (ppp_pcb *pcb); + /* Open the protocol */ + void (*open) (ppp_pcb *pcb); + /* Close the protocol */ + void (*close) (ppp_pcb *pcb, const char *reason); +#if PRINTPKT_SUPPORT + /* Print a packet in readable form */ + int (*printpkt) (const u_char *pkt, int len, + void (*printer) (void *, const char *, ...), + void *arg); +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + /* Process a received data packet */ + void (*datainput) (ppp_pcb *pcb, u_char *pkt, int len); +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + const char *name; /* Text name of protocol */ + const char *data_name; /* Text name of corresponding data protocol */ +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + option_t *options; /* List of command-line options */ + /* Check requested options, assign defaults */ + void (*check_options) (void); +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + /* Configure interface for demand-dial */ + int (*demand_conf) (int unit); + /* Say whether to bring up link for this pkt */ + int (*active_pkt) (u_char *pkt, int len); +#endif /* DEMAND_SUPPORT */ +}; + +/* Table of pointers to supported protocols */ +extern const struct protent* const protocols[]; + + +/* Values for auth_pending, auth_done */ +#if PAP_SUPPORT +#define PAP_WITHPEER 0x1 +#define PAP_PEER 0x2 +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT +#define CHAP_WITHPEER 0x4 +#define CHAP_PEER 0x8 +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT +#define EAP_WITHPEER 0x10 +#define EAP_PEER 0x20 +#endif /* EAP_SUPPORT */ + +/* Values for auth_done only */ +#if CHAP_SUPPORT +#define CHAP_MD5_WITHPEER 0x40 +#define CHAP_MD5_PEER 0x80 +#if MSCHAP_SUPPORT +#define CHAP_MS_SHIFT 8 /* LSB position for MS auths */ +#define CHAP_MS_WITHPEER 0x100 +#define CHAP_MS_PEER 0x200 +#define CHAP_MS2_WITHPEER 0x400 +#define CHAP_MS2_PEER 0x800 +#endif /* MSCHAP_SUPPORT */ +#endif /* CHAP_SUPPORT */ + +/* Supported CHAP protocols */ +#if CHAP_SUPPORT + +#if MSCHAP_SUPPORT +#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MICROSOFT_V2 | MDTYPE_MICROSOFT | MDTYPE_MD5) +#else /* MSCHAP_SUPPORT */ +#define CHAP_MDTYPE_SUPPORTED (MDTYPE_MD5) +#endif /* MSCHAP_SUPPORT */ + +#else /* CHAP_SUPPORT */ +#define CHAP_MDTYPE_SUPPORTED (MDTYPE_NONE) +#endif /* CHAP_SUPPORT */ + +#if PPP_STATS_SUPPORT +/* + * PPP statistics structure + */ +struct pppd_stats { + unsigned int bytes_in; + unsigned int bytes_out; + unsigned int pkts_in; + unsigned int pkts_out; +}; +#endif /* PPP_STATS_SUPPORT */ + + +/* + * PPP private functions + */ + + +/* + * Functions called from lwIP core. + */ + +/* initialize the PPP subsystem */ +int ppp_init(void); + +/* + * Functions called from PPP link protocols. + */ + +/* Create a new PPP control block */ +ppp_pcb *ppp_new(struct netif *pppif, const struct link_callbacks *callbacks, void *link_ctx_cb, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb); + +/* Initiate LCP open request */ +void ppp_start(ppp_pcb *pcb); + +/* Called when link failed to setup */ +void ppp_link_failed(ppp_pcb *pcb); + +/* Called when link is normally down (i.e. it was asked to end) */ +void ppp_link_end(ppp_pcb *pcb); + +/* function called to process input packet */ +void ppp_input(ppp_pcb *pcb, struct pbuf *pb); + + +/* + * Functions called by PPP protocols. + */ + +/* function called by all PPP subsystems to send packets */ +err_t ppp_write(ppp_pcb *pcb, struct pbuf *p); + +/* functions called by auth.c link_terminated() */ +void ppp_link_terminated(ppp_pcb *pcb); + +void new_phase(ppp_pcb *pcb, int p); + +int ppp_send_config(ppp_pcb *pcb, int mtu, u32_t accm, int pcomp, int accomp); +int ppp_recv_config(ppp_pcb *pcb, int mru, u32_t accm, int pcomp, int accomp); + +#if PPP_IPV4_SUPPORT +int sifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr, u32_t netmask); +int cifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr); +#if 0 /* UNUSED - PROXY ARP */ +int sifproxyarp(ppp_pcb *pcb, u32_t his_adr); +int cifproxyarp(ppp_pcb *pcb, u32_t his_adr); +#endif /* UNUSED - PROXY ARP */ +#if LWIP_DNS +int sdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2); +int cdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2); +#endif /* LWIP_DNS */ +#if VJ_SUPPORT +int sifvjcomp(ppp_pcb *pcb, int vjcomp, int cidcomp, int maxcid); +#endif /* VJ_SUPPORT */ +int sifup(ppp_pcb *pcb); +int sifdown (ppp_pcb *pcb); +u32_t get_mask(u32_t addr); +#endif /* PPP_IPV4_SUPPORT */ + +#if PPP_IPV6_SUPPORT +int sif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64); +int cif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64); +int sif6up(ppp_pcb *pcb); +int sif6down (ppp_pcb *pcb); +#endif /* PPP_IPV6_SUPPORT */ + +#if DEMAND_SUPPORT +int sifnpmode(ppp_pcb *pcb, int proto, enum NPmode mode); +#endif /* DEMAND_SUPPORt */ + +void netif_set_mtu(ppp_pcb *pcb, int mtu); +int netif_get_mtu(ppp_pcb *pcb); + +#if CCP_SUPPORT +#if 0 /* unused */ +int ccp_test(ppp_pcb *pcb, u_char *opt_ptr, int opt_len, int for_transmit); +#endif /* unused */ +void ccp_set(ppp_pcb *pcb, u8_t isopen, u8_t isup, u8_t receive_method, u8_t transmit_method); +void ccp_reset_comp(ppp_pcb *pcb); +void ccp_reset_decomp(ppp_pcb *pcb); +#if 0 /* unused */ +int ccp_fatal_error(ppp_pcb *pcb); +#endif /* unused */ +#endif /* CCP_SUPPORT */ + +#if PPP_IDLETIMELIMIT +int get_idle_time(ppp_pcb *pcb, struct ppp_idle *ip); +#endif /* PPP_IDLETIMELIMIT */ + +#if DEMAND_SUPPORT +int get_loop_output(void); +#endif /* DEMAND_SUPPORT */ + +/* Optional protocol names list, to make our messages a little more informative. */ +#if PPP_PROTOCOLNAME +const char * protocol_name(int proto); +#endif /* PPP_PROTOCOLNAME */ + +/* Optional stats support, to get some statistics on the PPP interface */ +#if PPP_STATS_SUPPORT +void print_link_stats(void); /* Print stats, if available */ +void reset_link_stats(int u); /* Reset (init) stats when link goes up */ +void update_link_stats(int u); /* Get stats at link termination */ +#endif /* PPP_STATS_SUPPORT */ + + + +/* + * Inline versions of get/put char/short/long. + * Pointer is advanced; we assume that both arguments + * are lvalues and will already be in registers. + * cp MUST be u_char *. + */ +#define GETCHAR(c, cp) { \ + (c) = *(cp)++; \ +} +#define PUTCHAR(c, cp) { \ + *(cp)++ = (u_char) (c); \ +} +#define GETSHORT(s, cp) { \ + (s) = *(cp)++ << 8; \ + (s) |= *(cp)++; \ +} +#define PUTSHORT(s, cp) { \ + *(cp)++ = (u_char) ((s) >> 8); \ + *(cp)++ = (u_char) (s); \ +} +#define GETLONG(l, cp) { \ + (l) = *(cp)++ << 8; \ + (l) |= *(cp)++; (l) <<= 8; \ + (l) |= *(cp)++; (l) <<= 8; \ + (l) |= *(cp)++; \ +} +#define PUTLONG(l, cp) { \ + *(cp)++ = (u_char) ((l) >> 24); \ + *(cp)++ = (u_char) ((l) >> 16); \ + *(cp)++ = (u_char) ((l) >> 8); \ + *(cp)++ = (u_char) (l); \ +} + +#define INCPTR(n, cp) ((cp) += (n)) +#define DECPTR(n, cp) ((cp) -= (n)) + +/* + * System dependent definitions for user-level 4.3BSD UNIX implementation. + */ +#define TIMEOUT(f, a, t) do { sys_untimeout((f), (a)); sys_timeout((t)*1000, (f), (a)); } while(0) +#define TIMEOUTMS(f, a, t) do { sys_untimeout((f), (a)); sys_timeout((t), (f), (a)); } while(0) +#define UNTIMEOUT(f, a) sys_untimeout((f), (a)) + +#define BZERO(s, n) memset(s, 0, n) +#define BCMP(s1, s2, l) memcmp(s1, s2, l) + +#define PRINTMSG(m, l) { ppp_info("Remote message: %0.*v", l, m); } + +/* + * MAKEHEADER - Add Header fields to a packet. + */ +#define MAKEHEADER(p, t) { \ + PUTCHAR(PPP_ALLSTATIONS, p); \ + PUTCHAR(PPP_UI, p); \ + PUTSHORT(t, p); } + +/* Procedures exported from auth.c */ +void link_required(ppp_pcb *pcb); /* we are starting to use the link */ +void link_terminated(ppp_pcb *pcb); /* we are finished with the link */ +void link_down(ppp_pcb *pcb); /* the LCP layer has left the Opened state */ +void upper_layers_down(ppp_pcb *pcb); /* take all NCPs down */ +void link_established(ppp_pcb *pcb); /* the link is up; authenticate now */ +void start_networks(ppp_pcb *pcb); /* start all the network control protos */ +void continue_networks(ppp_pcb *pcb); /* start network [ip, etc] control protos */ +#if PPP_AUTH_SUPPORT +#if PPP_SERVER +int auth_check_passwd(ppp_pcb *pcb, char *auser, int userlen, char *apasswd, int passwdlen, const char **msg, int *msglen); + /* check the user name and passwd against configuration */ +void auth_peer_fail(ppp_pcb *pcb, int protocol); + /* peer failed to authenticate itself */ +void auth_peer_success(ppp_pcb *pcb, int protocol, int prot_flavor, const char *name, int namelen); + /* peer successfully authenticated itself */ +#endif /* PPP_SERVER */ +void auth_withpeer_fail(ppp_pcb *pcb, int protocol); + /* we failed to authenticate ourselves */ +void auth_withpeer_success(ppp_pcb *pcb, int protocol, int prot_flavor); + /* we successfully authenticated ourselves */ +#endif /* PPP_AUTH_SUPPORT */ +void np_up(ppp_pcb *pcb, int proto); /* a network protocol has come up */ +void np_down(ppp_pcb *pcb, int proto); /* a network protocol has gone down */ +void np_finished(ppp_pcb *pcb, int proto); /* a network protocol no longer needs link */ +#if PPP_AUTH_SUPPORT +int get_secret(ppp_pcb *pcb, const char *client, const char *server, char *secret, int *secret_len, int am_server); + /* get "secret" for chap */ +#endif /* PPP_AUTH_SUPPORT */ + +/* Procedures exported from ipcp.c */ +/* int parse_dotted_ip (char *, u32_t *); */ + +/* Procedures exported from demand.c */ +#if DEMAND_SUPPORT +void demand_conf (void); /* config interface(s) for demand-dial */ +void demand_block (void); /* set all NPs to queue up packets */ +void demand_unblock (void); /* set all NPs to pass packets */ +void demand_discard (void); /* set all NPs to discard packets */ +void demand_rexmit (int, u32_t); /* retransmit saved frames for an NP*/ +int loop_chars (unsigned char *, int); /* process chars from loopback */ +int loop_frame (unsigned char *, int); /* should we bring link up? */ +#endif /* DEMAND_SUPPORT */ + +/* Procedures exported from multilink.c */ +#ifdef HAVE_MULTILINK +void mp_check_options (void); /* Check multilink-related options */ +int mp_join_bundle (void); /* join our link to an appropriate bundle */ +void mp_exit_bundle (void); /* have disconnected our link from bundle */ +void mp_bundle_terminated (void); +char *epdisc_to_str (struct epdisc *); /* string from endpoint discrim. */ +int str_to_epdisc (struct epdisc *, char *); /* endpt disc. from str */ +#else +#define mp_bundle_terminated() /* nothing */ +#define mp_exit_bundle() /* nothing */ +#define doing_multilink 0 +#define multilink_master 0 +#endif + +/* Procedures exported from utils.c. */ +void ppp_print_string(const u_char *p, int len, void (*printer) (void *, const char *, ...), void *arg); /* Format a string for output */ +int ppp_slprintf(char *buf, int buflen, const char *fmt, ...); /* sprintf++ */ +int ppp_vslprintf(char *buf, int buflen, const char *fmt, va_list args); /* vsprintf++ */ +size_t ppp_strlcpy(char *dest, const char *src, size_t len); /* safe strcpy */ +size_t ppp_strlcat(char *dest, const char *src, size_t len); /* safe strncpy */ +void ppp_dbglog(const char *fmt, ...); /* log a debug message */ +void ppp_info(const char *fmt, ...); /* log an informational message */ +void ppp_notice(const char *fmt, ...); /* log a notice-level message */ +void ppp_warn(const char *fmt, ...); /* log a warning message */ +void ppp_error(const char *fmt, ...); /* log an error message */ +void ppp_fatal(const char *fmt, ...); /* log an error message and die(1) */ +#if PRINTPKT_SUPPORT +void ppp_dump_packet(ppp_pcb *pcb, const char *tag, unsigned char *p, int len); + /* dump packet to debug log if interesting */ +#endif /* PRINTPKT_SUPPORT */ + +/* + * Number of necessary timers analysis. + * + * PPP use at least one timer per each of its protocol, but not all protocols are + * active at the same time, thus the number of necessary timeouts is actually + * lower than enabled protocols. Here is the actual necessary timeouts based + * on code analysis. + * + * Note that many features analysed here are not working at all and are only + * there for a comprehensive analysis of necessary timers in order to prevent + * having to redo that each time we add a feature. + * + * Timer list + * + * | holdoff timeout + * | low level protocol timeout (PPPoE or PPPoL2P) + * | LCP delayed UP + * | LCP retransmit (FSM) + * | LCP Echo timer + * .| PAP or CHAP or EAP authentication + * . | ECP retransmit (FSM) + * . | CCP retransmit (FSM) when MPPE is enabled + * . | CCP retransmit (FSM) when MPPE is NOT enabled + * . | IPCP retransmit (FSM) + * . .| IP6CP retransmit (FSM) + * . . | Idle time limit + * . . | Max connect time + * . . | Max octets + * . . | CCP RACK timeout + * . . . + * PPP_PHASE_DEAD + * PPP_PHASE_HOLDOFF + * | . . . + * PPP_PHASE_INITIALIZE + * | . . . + * PPP_PHASE_ESTABLISH + * | . . . + * |. . . + * | . . + * PPP_PHASE_AUTHENTICATE + * | . . + * || . . + * PPP_PHASE_NETWORK + * | || . . + * | ||| . + * PPP_PHASE_RUNNING + * | .||||| + * | . |||| + * PPP_PHASE_TERMINATE + * | . |||| + * PPP_PHASE_NETWORK + * |. . + * PPP_PHASE_ESTABLISH + * PPP_PHASE_DISCONNECT + * PPP_PHASE_DEAD + * + * Alright, PPP basic retransmission and LCP Echo consume one timer. + * 1 + * + * If authentication is enabled one timer is necessary during authentication. + * 1 + PPP_AUTH_SUPPORT + * + * If ECP is enabled one timer is necessary before IPCP and/or IP6CP, one more + * is necessary if CCP is enabled (only with MPPE support but we don't care much + * up to this detail level). + * 1 + ECP_SUPPORT + CCP_SUPPORT + * + * If CCP is enabled it might consume a timer during IPCP or IP6CP, thus + * we might use IPCP, IP6CP and CCP timers simultaneously. + * 1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT + * + * When entering running phase, IPCP or IP6CP is still running. If idle time limit + * is enabled one more timer is necessary. Same for max connect time and max + * octets features. Furthermore CCP RACK might be used past this point. + * 1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS + CCP_SUPPORT + * + * IPv4 or IPv6 must be enabled, therefore we don't need to take care the authentication + * and the CCP + ECP case, thus reducing overall complexity. + * 1 + LWIP_MAX(PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT, PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS + CCP_SUPPORT) + * + * We don't support PPP_IDLETIMELIMIT + PPP_MAXCONNECT + MAXOCTETS features + * and adding those defines to ppp_opts.h just for having the value always + * defined to 0 isn't worth it. + * 1 + LWIP_MAX(PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT, PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT -1 + CCP_SUPPORT) + * + * Thus, the following is enough for now. + * 1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PPP_SUPPORT */ +#endif /* LWIP_HDR_PPP_IMPL_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h new file mode 100644 index 0000000..6702bec --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/ppp_opts.h @@ -0,0 +1,610 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#ifndef LWIP_PPP_OPTS_H +#define LWIP_PPP_OPTS_H + +#include "lwip/opt.h" + +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOL2TP_SUPPORT==1: Enable PPP Over L2TP + */ +#ifndef PPPOL2TP_SUPPORT +#define PPPOL2TP_SUPPORT 0 +#endif + +/** + * PPPOL2TP_AUTH_SUPPORT==1: Enable PPP Over L2TP Auth (enable MD5 support) + */ +#ifndef PPPOL2TP_AUTH_SUPPORT +#define PPPOL2TP_AUTH_SUPPORT PPPOL2TP_SUPPORT +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +/** + * LWIP_PPP_API==1: Enable PPP API (in pppapi.c) + */ +#ifndef LWIP_PPP_API +#define LWIP_PPP_API (PPP_SUPPORT && (NO_SYS == 0)) +#endif + +#if PPP_SUPPORT + +/** + * MEMP_NUM_PPP_PCB: the number of simultaneously active PPP + * connections (requires the PPP_SUPPORT option) + */ +#ifndef MEMP_NUM_PPP_PCB +#define MEMP_NUM_PPP_PCB 1 +#endif + +/** + * PPP_NUM_TIMEOUTS_PER_PCB: the number of sys_timeouts running in parallel per + * ppp_pcb. See the detailed explanation at the end of ppp_impl.h about simultaneous + * timers analysis. + */ +#ifndef PPP_NUM_TIMEOUTS_PER_PCB +#define PPP_NUM_TIMEOUTS_PER_PCB (1 + PPP_IPV4_SUPPORT + PPP_IPV6_SUPPORT + CCP_SUPPORT) +#endif + +/* The number of sys_timeouts required for the PPP module */ +#define PPP_NUM_TIMEOUTS (PPP_SUPPORT * PPP_NUM_TIMEOUTS_PER_PCB * MEMP_NUM_PPP_PCB) + +/** + * MEMP_NUM_PPPOS_INTERFACES: the number of concurrently active PPPoS + * interfaces (only used with PPPOS_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOS_INTERFACES +#define MEMP_NUM_PPPOS_INTERFACES MEMP_NUM_PPP_PCB +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * MEMP_NUM_PPPOL2TP_INTERFACES: the number of concurrently active PPPoL2TP + * interfaces (only used with PPPOL2TP_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOL2TP_INTERFACES +#define MEMP_NUM_PPPOL2TP_INTERFACES 1 +#endif + +/** + * MEMP_NUM_PPP_API_MSG: Number of concurrent PPP API messages (in pppapi.c) + */ +#ifndef MEMP_NUM_PPP_API_MSG +#define MEMP_NUM_PPP_API_MSG 5 +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_INPROC_IRQ_SAFE==1 call pppos_input() using tcpip_callback(). + * + * Please read the "PPPoS input path" chapter in the PPP documentation about this option. + */ +#ifndef PPP_INPROC_IRQ_SAFE +#define PPP_INPROC_IRQ_SAFE 0 +#endif + +/** + * PRINTPKT_SUPPORT==1: Enable PPP print packet support + * + * Mandatory for debugging, it displays exchanged packet content in debug trace. + */ +#ifndef PRINTPKT_SUPPORT +#define PRINTPKT_SUPPORT 0 +#endif + +/** + * PPP_IPV4_SUPPORT==1: Enable PPP IPv4 support + */ +#ifndef PPP_IPV4_SUPPORT +#define PPP_IPV4_SUPPORT (LWIP_IPV4) +#endif + +/** + * PPP_IPV6_SUPPORT==1: Enable PPP IPv6 support + */ +#ifndef PPP_IPV6_SUPPORT +#define PPP_IPV6_SUPPORT (LWIP_IPV6) +#endif + +/** + * PPP_NOTIFY_PHASE==1: Support PPP notify phase support + * + * PPP notify phase support allows you to set a callback which is + * called on change of the internal PPP state machine. + * + * This can be used for example to set a LED pattern depending on the + * current phase of the PPP session. + */ +#ifndef PPP_NOTIFY_PHASE +#define PPP_NOTIFY_PHASE 0 +#endif + +/** + * pbuf_type PPP is using for LCP, PAP, CHAP, EAP, CCP, IPCP and IP6CP packets. + * + * Memory allocated must be single buffered for PPP to works, it requires pbuf + * that are not going to be chained when allocated. This requires setting + * PBUF_POOL_BUFSIZE to at least 512 bytes, which is quite huge for small systems. + * + * Setting PPP_USE_PBUF_RAM to 1 makes PPP use memory from heap where continuous + * buffers are required, allowing you to use a smaller PBUF_POOL_BUFSIZE. + */ +#ifndef PPP_USE_PBUF_RAM +#define PPP_USE_PBUF_RAM 0 +#endif + +/** + * PPP_FCS_TABLE: Keep a 256*2 byte table to speed up FCS calculation for PPPoS + */ +#ifndef PPP_FCS_TABLE +#define PPP_FCS_TABLE 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif +#if MSCHAP_SUPPORT +/* MSCHAP requires CHAP support */ +#undef CHAP_SUPPORT +#define CHAP_SUPPORT 1 +#endif /* MSCHAP_SUPPORT */ + +/** + * EAP_SUPPORT==1: Support EAP. + */ +#ifndef EAP_SUPPORT +#define EAP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * MPPE_SUPPORT==1: Support MPPE. + */ +#ifndef MPPE_SUPPORT +#define MPPE_SUPPORT 0 +#endif +#if MPPE_SUPPORT +/* MPPE requires CCP support */ +#undef CCP_SUPPORT +#define CCP_SUPPORT 1 +/* MPPE requires MSCHAP support */ +#undef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 1 +/* MSCHAP requires CHAP support */ +#undef CHAP_SUPPORT +#define CHAP_SUPPORT 1 +#endif /* MPPE_SUPPORT */ + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * ECP_SUPPORT==1: Support ECP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef ECP_SUPPORT +#define ECP_SUPPORT 0 +#endif + +/** + * DEMAND_SUPPORT==1: Support dial on demand. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef DEMAND_SUPPORT +#define DEMAND_SUPPORT 0 +#endif + +/** + * LQR_SUPPORT==1: Support Link Quality Report. Do nothing except exchanging some LCP packets. + */ +#ifndef LQR_SUPPORT +#define LQR_SUPPORT 0 +#endif + +/** + * PPP_SERVER==1: Enable PPP server support (waiting for incoming PPP session). + * + * Currently only supported for PPPoS. + */ +#ifndef PPP_SERVER +#define PPP_SERVER 0 +#endif + +#if PPP_SERVER +/* + * PPP_OUR_NAME: Our name for authentication purposes + */ +#ifndef PPP_OUR_NAME +#define PPP_OUR_NAME "lwIP" +#endif +#endif /* PPP_SERVER */ + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 1 +#endif +/* VJ compression is only supported for TCP over IPv4 over PPPoS. */ +#if !PPPOS_SUPPORT || !PPP_IPV4_SUPPORT || !LWIP_TCP +#undef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif /* !PPPOS_SUPPORT */ + +/** + * PPP_MD5_RANDM==1: Use MD5 for better randomness. + * Enabled by default if CHAP, EAP, or L2TP AUTH support is enabled. + */ +#ifndef PPP_MD5_RANDM +#define PPP_MD5_RANDM (CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT) +#endif + +/** + * PolarSSL embedded library + * + * + * lwIP contains some files fetched from the latest BSD release of + * the PolarSSL project (PolarSSL 0.10.1-bsd) for ciphers and encryption + * methods we need for lwIP PPP support. + * + * The PolarSSL files were cleaned to contain only the necessary struct + * fields and functions needed for lwIP. + * + * The PolarSSL API was not changed at all, so if you are already using + * PolarSSL you can choose to skip the compilation of the included PolarSSL + * library into lwIP. + * + * If you are not using the embedded copy you must include external + * libraries into your arch/cc.h port file. + * + * Beware of the stack requirements which can be a lot larger if you are not + * using our cleaned PolarSSL library. + */ + +/** + * LWIP_USE_EXTERNAL_POLARSSL: Use external PolarSSL library + */ +#ifndef LWIP_USE_EXTERNAL_POLARSSL +#define LWIP_USE_EXTERNAL_POLARSSL 0 +#endif + +/** + * LWIP_USE_EXTERNAL_MBEDTLS: Use external mbed TLS library + */ +#ifndef LWIP_USE_EXTERNAL_MBEDTLS +#define LWIP_USE_EXTERNAL_MBEDTLS 0 +#endif + +/* + * PPP Timeouts + */ + +/** + * FSM_DEFTIMEOUT: Timeout time in seconds + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 +#endif + +/** + * FSM_DEFMAXTERMREQS: Maximum Terminate-Request transmissions + */ +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 +#endif + +/** + * FSM_DEFMAXCONFREQS: Maximum Configure-Request transmissions + */ +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 +#endif + +/** + * FSM_DEFMAXNAKLOOPS: Maximum number of nak loops + */ +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 +#endif + +/** + * UPAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req + */ +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 +#endif + +/** + * UPAP_DEFTRANSMITS: Maximum number of auth-reqs to send + */ +#ifndef UPAP_DEFTRANSMITS +#define UPAP_DEFTRANSMITS 10 +#endif + +#if PPP_SERVER +/** + * UPAP_DEFREQTIME: Time to wait for auth-req from peer + */ +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 +#endif +#endif /* PPP_SERVER */ + +/** + * CHAP_DEFTIMEOUT: Timeout (seconds) for retransmitting req + */ +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 +#endif + +/** + * CHAP_DEFTRANSMITS: max # times to send challenge + */ +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 +#endif + +#if PPP_SERVER +/** + * CHAP_DEFRECHALLENGETIME: If this option is > 0, rechallenge the peer every n seconds + */ +#ifndef CHAP_DEFRECHALLENGETIME +#define CHAP_DEFRECHALLENGETIME 0 +#endif +#endif /* PPP_SERVER */ + +/** + * EAP_DEFREQTIME: Time to wait for peer request + */ +#ifndef EAP_DEFREQTIME +#define EAP_DEFREQTIME 6 +#endif + +/** + * EAP_DEFALLOWREQ: max # times to accept requests + */ +#ifndef EAP_DEFALLOWREQ +#define EAP_DEFALLOWREQ 10 +#endif + +#if PPP_SERVER +/** + * EAP_DEFTIMEOUT: Timeout (seconds) for rexmit + */ +#ifndef EAP_DEFTIMEOUT +#define EAP_DEFTIMEOUT 6 +#endif + +/** + * EAP_DEFTRANSMITS: max # times to transmit + */ +#ifndef EAP_DEFTRANSMITS +#define EAP_DEFTRANSMITS 10 +#endif +#endif /* PPP_SERVER */ + +/** + * LCP_DEFLOOPBACKFAIL: Default number of times we receive our magic number from the peer + * before deciding the link is looped-back. + */ +#ifndef LCP_DEFLOOPBACKFAIL +#define LCP_DEFLOOPBACKFAIL 10 +#endif + +/** + * LCP_ECHOINTERVAL: Interval in seconds between keepalive echo requests, 0 to disable. + */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/** + * LCP_MAXECHOFAILS: Number of unanswered echo requests before failure. + */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/** + * PPP_MAXIDLEFLAG: Max Xmit idle time (in ms) before resend flag char. + */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/** + * PPP Packet sizes + */ + +/** + * PPP_MRU: Default MRU + */ +#ifndef PPP_MRU +#define PPP_MRU 1500 +#endif + +/** + * PPP_DEFMRU: Default MRU to try + */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 1500 +#endif + +/** + * PPP_MAXMRU: Normally limit MRU to this (pppd default = 16384) + */ +#ifndef PPP_MAXMRU +#define PPP_MAXMRU 1500 +#endif + +/** + * PPP_MINMRU: No MRUs below this + */ +#ifndef PPP_MINMRU +#define PPP_MINMRU 128 +#endif + +/** + * PPPOL2TP_DEFMRU: Default MTU and MRU for L2TP + * Default = 1500 - PPPoE(6) - PPP Protocol(2) - IPv4 header(20) - UDP Header(8) + * - L2TP Header(6) - HDLC Header(2) - PPP Protocol(2) - MPPE Header(2) - PPP Protocol(2) + */ +#if PPPOL2TP_SUPPORT +#ifndef PPPOL2TP_DEFMRU +#define PPPOL2TP_DEFMRU 1450 +#endif +#endif /* PPPOL2TP_SUPPORT */ + +/** + * MAXNAMELEN: max length of hostname or name for auth + */ +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 +#endif + +/** + * MAXSECRETLEN: max length of password or secret + */ +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 +#endif + +/* ------------------------------------------------------------------------- */ + +/* + * Build triggers for embedded PolarSSL + */ +#if !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS + +/* CHAP, EAP, L2TP AUTH and MD5 Random require MD5 support */ +#if CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM +#define LWIP_INCLUDED_POLARSSL_MD5 1 +#endif /* CHAP_SUPPORT || EAP_SUPPORT || PPPOL2TP_AUTH_SUPPORT || PPP_MD5_RANDM */ + +#if MSCHAP_SUPPORT + +/* MSCHAP require MD4 support */ +#define LWIP_INCLUDED_POLARSSL_MD4 1 +/* MSCHAP require SHA1 support */ +#define LWIP_INCLUDED_POLARSSL_SHA1 1 +/* MSCHAP require DES support */ +#define LWIP_INCLUDED_POLARSSL_DES 1 + +/* MS-CHAP support is required for MPPE */ +#if MPPE_SUPPORT +/* MPPE require ARC4 support */ +#define LWIP_INCLUDED_POLARSSL_ARC4 1 +#endif /* MPPE_SUPPORT */ + +#endif /* MSCHAP_SUPPORT */ + +#endif /* !LWIP_USE_EXTERNAL_POLARSSL && !LWIP_USE_EXTERNAL_MBEDTLS */ + +/* Default value if unset */ +#ifndef LWIP_INCLUDED_POLARSSL_MD4 +#define LWIP_INCLUDED_POLARSSL_MD4 0 +#endif /* LWIP_INCLUDED_POLARSSL_MD4 */ +#ifndef LWIP_INCLUDED_POLARSSL_MD5 +#define LWIP_INCLUDED_POLARSSL_MD5 0 +#endif /* LWIP_INCLUDED_POLARSSL_MD5 */ +#ifndef LWIP_INCLUDED_POLARSSL_SHA1 +#define LWIP_INCLUDED_POLARSSL_SHA1 0 +#endif /* LWIP_INCLUDED_POLARSSL_SHA1 */ +#ifndef LWIP_INCLUDED_POLARSSL_DES +#define LWIP_INCLUDED_POLARSSL_DES 0 +#endif /* LWIP_INCLUDED_POLARSSL_DES */ +#ifndef LWIP_INCLUDED_POLARSSL_ARC4 +#define LWIP_INCLUDED_POLARSSL_ARC4 0 +#endif /* LWIP_INCLUDED_POLARSSL_ARC4 */ + +#endif /* PPP_SUPPORT */ + +/* Default value if unset */ +#ifndef PPP_NUM_TIMEOUTS +#define PPP_NUM_TIMEOUTS 0 +#endif /* PPP_NUM_TIMEOUTS */ + +#endif /* LWIP_PPP_OPTS_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h new file mode 100644 index 0000000..913d93f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppapi.h @@ -0,0 +1,137 @@ +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#ifndef LWIP_PPPAPI_H +#define LWIP_PPPAPI_H + +#include "netif/ppp/ppp_opts.h" + +#if LWIP_PPP_API /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sys.h" +#include "lwip/netif.h" +#include "lwip/priv/tcpip_priv.h" +#include "netif/ppp/ppp.h" +#if PPPOS_SUPPORT +#include "netif/ppp/pppos.h" +#endif /* PPPOS_SUPPORT */ + +#ifdef __cplusplus +extern "C" { +#endif + +struct pppapi_msg_msg { + ppp_pcb *ppp; + union { +#if PPP_NOTIFY_PHASE + struct { + ppp_notify_phase_cb_fn notify_phase_cb; + } setnotifyphasecb; +#endif /* PPP_NOTIFY_PHASE */ +#if PPPOS_SUPPORT + struct { + struct netif *pppif; + pppos_output_cb_fn output_cb; + ppp_link_status_cb_fn link_status_cb; + void *ctx_cb; + } serialcreate; +#endif /* PPPOS_SUPPORT */ +#if PPPOE_SUPPORT + struct { + struct netif *pppif; + struct netif *ethif; + const char *service_name; + const char *concentrator_name; + ppp_link_status_cb_fn link_status_cb; + void *ctx_cb; + } ethernetcreate; +#endif /* PPPOE_SUPPORT */ +#if PPPOL2TP_SUPPORT + struct { + struct netif *pppif; + struct netif *netif; + API_MSG_M_DEF_C(ip_addr_t, ipaddr); + u16_t port; +#if PPPOL2TP_AUTH_SUPPORT + const u8_t *secret; + u8_t secret_len; +#endif /* PPPOL2TP_AUTH_SUPPORT */ + ppp_link_status_cb_fn link_status_cb; + void *ctx_cb; + } l2tpcreate; +#endif /* PPPOL2TP_SUPPORT */ + struct { + u16_t holdoff; + } connect; + struct { + u8_t nocarrier; + } close; + struct { + u8_t cmd; + void *arg; + } ioctl; + } msg; +}; + +struct pppapi_msg { + struct tcpip_api_call_data call; + struct pppapi_msg_msg msg; +}; + +/* API for application */ +err_t pppapi_set_default(ppp_pcb *pcb); +#if PPP_NOTIFY_PHASE +err_t pppapi_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb); +#endif /* PPP_NOTIFY_PHASE */ +#if PPPOS_SUPPORT +ppp_pcb *pppapi_pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, ppp_link_status_cb_fn link_status_cb, void *ctx_cb); +#endif /* PPPOS_SUPPORT */ +#if PPPOE_SUPPORT +ppp_pcb *pppapi_pppoe_create(struct netif *pppif, struct netif *ethif, const char *service_name, + const char *concentrator_name, ppp_link_status_cb_fn link_status_cb, + void *ctx_cb); +#endif /* PPPOE_SUPPORT */ +#if PPPOL2TP_SUPPORT +ppp_pcb *pppapi_pppol2tp_create(struct netif *pppif, struct netif *netif, ip_addr_t *ipaddr, u16_t port, + const u8_t *secret, u8_t secret_len, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb); +#endif /* PPPOL2TP_SUPPORT */ +err_t pppapi_connect(ppp_pcb *pcb, u16_t holdoff); +#if PPP_SERVER +err_t pppapi_listen(ppp_pcb *pcb); +#endif /* PPP_SERVER */ +err_t pppapi_close(ppp_pcb *pcb, u8_t nocarrier); +err_t pppapi_free(ppp_pcb *pcb); +err_t pppapi_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_PPP_API */ + +#endif /* LWIP_PPPAPI_H */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h new file mode 100644 index 0000000..c0230bb --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppcrypt.h @@ -0,0 +1,144 @@ +/* + * pppcrypt.c - PPP/DES linkage for MS-CHAP and EAP SRP-SHA1 + * + * Extracted from chap_ms.c by James Carlson. + * + * Copyright (c) 1995 Eric Rosenquist. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +/* This header file is included in all PPP modules needing hashes and/or ciphers */ + +#ifndef PPPCRYPT_H +#define PPPCRYPT_H + +/* + * If included PolarSSL copy is not used, user is expected to include + * external libraries in arch/cc.h (which is included by lwip/arch.h). + */ +#include "lwip/arch.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Map hashes and ciphers functions to PolarSSL + */ +#if !LWIP_USE_EXTERNAL_MBEDTLS + +#include "netif/ppp/polarssl/md4.h" +#define lwip_md4_context md4_context +#define lwip_md4_init(context) +#define lwip_md4_starts md4_starts +#define lwip_md4_update md4_update +#define lwip_md4_finish md4_finish +#define lwip_md4_free(context) + +#include "netif/ppp/polarssl/md5.h" +#define lwip_md5_context md5_context +#define lwip_md5_init(context) +#define lwip_md5_starts md5_starts +#define lwip_md5_update md5_update +#define lwip_md5_finish md5_finish +#define lwip_md5_free(context) + +#include "netif/ppp/polarssl/sha1.h" +#define lwip_sha1_context sha1_context +#define lwip_sha1_init(context) +#define lwip_sha1_starts sha1_starts +#define lwip_sha1_update sha1_update +#define lwip_sha1_finish sha1_finish +#define lwip_sha1_free(context) + +#include "netif/ppp/polarssl/des.h" +#define lwip_des_context des_context +#define lwip_des_init(context) +#define lwip_des_setkey_enc des_setkey_enc +#define lwip_des_crypt_ecb des_crypt_ecb +#define lwip_des_free(context) + +#include "netif/ppp/polarssl/arc4.h" +#define lwip_arc4_context arc4_context +#define lwip_arc4_init(context) +#define lwip_arc4_setup arc4_setup +#define lwip_arc4_crypt arc4_crypt +#define lwip_arc4_free(context) + +#endif /* !LWIP_USE_EXTERNAL_MBEDTLS */ + +/* + * Map hashes and ciphers functions to mbed TLS + */ +#if LWIP_USE_EXTERNAL_MBEDTLS + +#define lwip_md4_context mbedtls_md4_context +#define lwip_md4_init mbedtls_md4_init +#define lwip_md4_starts mbedtls_md4_starts +#define lwip_md4_update mbedtls_md4_update +#define lwip_md4_finish mbedtls_md4_finish +#define lwip_md4_free mbedtls_md4_free + +#define lwip_md5_context mbedtls_md5_context +#define lwip_md5_init mbedtls_md5_init +#define lwip_md5_starts mbedtls_md5_starts +#define lwip_md5_update mbedtls_md5_update +#define lwip_md5_finish mbedtls_md5_finish +#define lwip_md5_free mbedtls_md5_free + +#define lwip_sha1_context mbedtls_sha1_context +#define lwip_sha1_init mbedtls_sha1_init +#define lwip_sha1_starts mbedtls_sha1_starts +#define lwip_sha1_update mbedtls_sha1_update +#define lwip_sha1_finish mbedtls_sha1_finish +#define lwip_sha1_free mbedtls_sha1_free + +#define lwip_des_context mbedtls_des_context +#define lwip_des_init mbedtls_des_init +#define lwip_des_setkey_enc mbedtls_des_setkey_enc +#define lwip_des_crypt_ecb mbedtls_des_crypt_ecb +#define lwip_des_free mbedtls_des_free + +#define lwip_arc4_context mbedtls_arc4_context +#define lwip_arc4_init mbedtls_arc4_init +#define lwip_arc4_setup mbedtls_arc4_setup +#define lwip_arc4_crypt(context, buffer, length) mbedtls_arc4_crypt(context, length, buffer, buffer) +#define lwip_arc4_free mbedtls_arc4_free + +#endif /* LWIP_USE_EXTERNAL_MBEDTLS */ + +void pppcrypt_56_to_64_bit_key(u_char *key, u_char *des_key); + +#ifdef __cplusplus +} +#endif + +#endif /* PPPCRYPT_H */ + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h new file mode 100644 index 0000000..36ee4f9 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppdebug.h @@ -0,0 +1,88 @@ +/***************************************************************************** +* pppdebug.h - System debugging utilities. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1998 Global Election Systems Inc. +* portions Copyright (c) 2001 by Cognizant Pty Ltd. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY (please don't use tabs!) +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-07-29 Guy Lancaster , Global Election Systems Inc. +* Original. +* +***************************************************************************** +*/ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef PPPDEBUG_H +#define PPPDEBUG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Trace levels. */ +#define LOG_CRITICAL (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE) +#define LOG_ERR (PPP_DEBUG | LWIP_DBG_LEVEL_SEVERE) +#define LOG_NOTICE (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING) +#define LOG_WARNING (PPP_DEBUG | LWIP_DBG_LEVEL_WARNING) +#define LOG_INFO (PPP_DEBUG) +#define LOG_DETAIL (PPP_DEBUG) +#define LOG_DEBUG (PPP_DEBUG) + +#if PPP_DEBUG + +#define MAINDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define SYSDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define FSMDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define LCPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define IPCPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define IPV6CPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define UPAPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define CHAPDEBUG(a) LWIP_DEBUGF(LWIP_DBG_LEVEL_WARNING, a) +#define PPPDEBUG(a, b) LWIP_DEBUGF(a, b) + +#else /* PPP_DEBUG */ + +#define MAINDEBUG(a) +#define SYSDEBUG(a) +#define FSMDEBUG(a) +#define LCPDEBUG(a) +#define IPCPDEBUG(a) +#define IPV6CPDEBUG(a) +#define UPAPDEBUG(a) +#define CHAPDEBUG(a) +#define PPPDEBUG(a, b) + +#endif /* PPP_DEBUG */ + +#ifdef __cplusplus +} +#endif + +#endif /* PPPDEBUG_H */ + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h new file mode 100644 index 0000000..08ab7ab --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppoe.h @@ -0,0 +1,187 @@ +/***************************************************************************** +* pppoe.h - PPP Over Ethernet implementation for lwIP. +* +* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 06-01-01 Marc Boucher +* Ported to lwIP. +*****************************************************************************/ + + + +/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Martin Husemann . + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef PPP_OE_H +#define PPP_OE_H + +#include "ppp.h" +#include "lwip/etharp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoehdr { + PACK_STRUCT_FLD_8(u8_t vertype); + PACK_STRUCT_FLD_8(u8_t code); + PACK_STRUCT_FIELD(u16_t session); + PACK_STRUCT_FIELD(u16_t plen); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppoetag { + PACK_STRUCT_FIELD(u16_t tag); + PACK_STRUCT_FIELD(u16_t len); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + + +#define PPPOE_STATE_INITIAL 0 +#define PPPOE_STATE_PADI_SENT 1 +#define PPPOE_STATE_PADR_SENT 2 +#define PPPOE_STATE_SESSION 3 +/* passive */ +#define PPPOE_STATE_PADO_SENT 1 + +#define PPPOE_HEADERLEN sizeof(struct pppoehdr) +#define PPPOE_VERTYPE 0x11 /* VER=1, TYPE = 1 */ + +#define PPPOE_TAG_EOL 0x0000 /* end of list */ +#define PPPOE_TAG_SNAME 0x0101 /* service name */ +#define PPPOE_TAG_ACNAME 0x0102 /* access concentrator name */ +#define PPPOE_TAG_HUNIQUE 0x0103 /* host unique */ +#define PPPOE_TAG_ACCOOKIE 0x0104 /* AC cookie */ +#define PPPOE_TAG_VENDOR 0x0105 /* vendor specific */ +#define PPPOE_TAG_RELAYSID 0x0110 /* relay session id */ +#define PPPOE_TAG_SNAME_ERR 0x0201 /* service name error */ +#define PPPOE_TAG_ACSYS_ERR 0x0202 /* AC system error */ +#define PPPOE_TAG_GENERIC_ERR 0x0203 /* gerneric error */ + +#define PPPOE_CODE_PADI 0x09 /* Active Discovery Initiation */ +#define PPPOE_CODE_PADO 0x07 /* Active Discovery Offer */ +#define PPPOE_CODE_PADR 0x19 /* Active Discovery Request */ +#define PPPOE_CODE_PADS 0x65 /* Active Discovery Session confirmation */ +#define PPPOE_CODE_PADT 0xA7 /* Active Discovery Terminate */ + +#ifndef PPPOE_MAX_AC_COOKIE_LEN +#define PPPOE_MAX_AC_COOKIE_LEN 64 +#endif + +struct pppoe_softc { + struct pppoe_softc *next; + struct netif *sc_ethif; /* ethernet interface we are using */ + ppp_pcb *pcb; /* PPP PCB */ + + struct eth_addr sc_dest; /* hardware address of concentrator */ + u16_t sc_session; /* PPPoE session id */ + u8_t sc_state; /* discovery phase or session connected */ + +#ifdef PPPOE_TODO + u8_t *sc_service_name; /* if != NULL: requested name of service */ + u8_t *sc_concentrator_name; /* if != NULL: requested concentrator id */ +#endif /* PPPOE_TODO */ + u8_t sc_ac_cookie[PPPOE_MAX_AC_COOKIE_LEN]; /* content of AC cookie we must echo back */ + u8_t sc_ac_cookie_len; /* length of cookie data */ +#ifdef PPPOE_SERVER + u8_t *sc_hunique; /* content of host unique we must echo back */ + u8_t sc_hunique_len; /* length of host unique */ +#endif + u8_t sc_padi_retried; /* number of PADI retries already done */ + u8_t sc_padr_retried; /* number of PADR retries already done */ +}; + + +#define pppoe_init() /* compatibility define, no initialization needed */ + +ppp_pcb *pppoe_create(struct netif *pppif, + struct netif *ethif, + const char *service_name, const char *concentrator_name, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb); + +/* + * Functions called from lwIP + * DO NOT CALL FROM lwIP USER APPLICATION. + */ +void pppoe_disc_input(struct netif *netif, struct pbuf *p); +void pppoe_data_input(struct netif *netif, struct pbuf *p); + +#ifdef __cplusplus +} +#endif + +#endif /* PPP_OE_H */ + +#endif /* PPP_SUPPORT && PPPOE_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h new file mode 100644 index 0000000..1221ca1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppol2tp.h @@ -0,0 +1,209 @@ +/** + * @file + * Network Point to Point Protocol over Layer 2 Tunneling Protocol header file. + * + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPPOL2TP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef PPPOL2TP_H +#define PPPOL2TP_H + +#include "ppp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Timeout */ +#define PPPOL2TP_CONTROL_TIMEOUT (5*1000) /* base for quick timeout calculation */ +#define PPPOL2TP_SLOW_RETRY (60*1000) /* persistent retry interval */ + +#define PPPOL2TP_MAXSCCRQ 4 /* retry SCCRQ four times (quickly) */ +#define PPPOL2TP_MAXICRQ 4 /* retry IRCQ four times */ +#define PPPOL2TP_MAXICCN 4 /* retry ICCN four times */ + +/* L2TP header flags */ +#define PPPOL2TP_HEADERFLAG_CONTROL 0x8000 +#define PPPOL2TP_HEADERFLAG_LENGTH 0x4000 +#define PPPOL2TP_HEADERFLAG_SEQUENCE 0x0800 +#define PPPOL2TP_HEADERFLAG_OFFSET 0x0200 +#define PPPOL2TP_HEADERFLAG_PRIORITY 0x0100 +#define PPPOL2TP_HEADERFLAG_VERSION 0x0002 + +/* Mandatory bits for control: Control, Length, Sequence, Version 2 */ +#define PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY (PPPOL2TP_HEADERFLAG_CONTROL|PPPOL2TP_HEADERFLAG_LENGTH|PPPOL2TP_HEADERFLAG_SEQUENCE|PPPOL2TP_HEADERFLAG_VERSION) +/* Forbidden bits for control: Offset, Priority */ +#define PPPOL2TP_HEADERFLAG_CONTROL_FORBIDDEN (PPPOL2TP_HEADERFLAG_OFFSET|PPPOL2TP_HEADERFLAG_PRIORITY) + +/* Mandatory bits for data: Version 2 */ +#define PPPOL2TP_HEADERFLAG_DATA_MANDATORY (PPPOL2TP_HEADERFLAG_VERSION) + +/* AVP (Attribute Value Pair) header */ +#define PPPOL2TP_AVPHEADERFLAG_MANDATORY 0x8000 +#define PPPOL2TP_AVPHEADERFLAG_HIDDEN 0x4000 +#define PPPOL2TP_AVPHEADERFLAG_LENGTHMASK 0x03ff + +/* -- AVP - Message type */ +#define PPPOL2TP_AVPTYPE_MESSAGE 0 /* Message type */ + +/* Control Connection Management */ +#define PPPOL2TP_MESSAGETYPE_SCCRQ 1 /* Start Control Connection Request */ +#define PPPOL2TP_MESSAGETYPE_SCCRP 2 /* Start Control Connection Reply */ +#define PPPOL2TP_MESSAGETYPE_SCCCN 3 /* Start Control Connection Connected */ +#define PPPOL2TP_MESSAGETYPE_STOPCCN 4 /* Stop Control Connection Notification */ +#define PPPOL2TP_MESSAGETYPE_HELLO 6 /* Hello */ +/* Call Management */ +#define PPPOL2TP_MESSAGETYPE_OCRQ 7 /* Outgoing Call Request */ +#define PPPOL2TP_MESSAGETYPE_OCRP 8 /* Outgoing Call Reply */ +#define PPPOL2TP_MESSAGETYPE_OCCN 9 /* Outgoing Call Connected */ +#define PPPOL2TP_MESSAGETYPE_ICRQ 10 /* Incoming Call Request */ +#define PPPOL2TP_MESSAGETYPE_ICRP 11 /* Incoming Call Reply */ +#define PPPOL2TP_MESSAGETYPE_ICCN 12 /* Incoming Call Connected */ +#define PPPOL2TP_MESSAGETYPE_CDN 14 /* Call Disconnect Notify */ +/* Error reporting */ +#define PPPOL2TP_MESSAGETYPE_WEN 15 /* WAN Error Notify */ +/* PPP Session Control */ +#define PPPOL2TP_MESSAGETYPE_SLI 16 /* Set Link Info */ + +/* -- AVP - Result code */ +#define PPPOL2TP_AVPTYPE_RESULTCODE 1 /* Result code */ +#define PPPOL2TP_RESULTCODE 1 /* General request to clear control connection */ + +/* -- AVP - Protocol version (!= L2TP Header version) */ +#define PPPOL2TP_AVPTYPE_VERSION 2 +#define PPPOL2TP_VERSION 0x0100 /* L2TP Protocol version 1, revision 0 */ + +/* -- AVP - Framing capabilities */ +#define PPPOL2TP_AVPTYPE_FRAMINGCAPABILITIES 3 /* Bearer capabilities */ +#define PPPOL2TP_FRAMINGCAPABILITIES 0x00000003 /* Async + Sync framing */ + +/* -- AVP - Bearer capabilities */ +#define PPPOL2TP_AVPTYPE_BEARERCAPABILITIES 4 /* Bearer capabilities */ +#define PPPOL2TP_BEARERCAPABILITIES 0x00000003 /* Analog + Digital Access */ + +/* -- AVP - Tie breaker */ +#define PPPOL2TP_AVPTYPE_TIEBREAKER 5 + +/* -- AVP - Host name */ +#define PPPOL2TP_AVPTYPE_HOSTNAME 7 /* Host name */ +#define PPPOL2TP_HOSTNAME "lwIP" /* FIXME: make it configurable */ + +/* -- AVP - Vendor name */ +#define PPPOL2TP_AVPTYPE_VENDORNAME 8 /* Vendor name */ +#define PPPOL2TP_VENDORNAME "lwIP" /* FIXME: make it configurable */ + +/* -- AVP - Assign tunnel ID */ +#define PPPOL2TP_AVPTYPE_TUNNELID 9 /* Assign Tunnel ID */ + +/* -- AVP - Receive window size */ +#define PPPOL2TP_AVPTYPE_RECEIVEWINDOWSIZE 10 /* Receive window size */ +#define PPPOL2TP_RECEIVEWINDOWSIZE 8 /* FIXME: make it configurable */ + +/* -- AVP - Challenge */ +#define PPPOL2TP_AVPTYPE_CHALLENGE 11 /* Challenge */ + +/* -- AVP - Cause code */ +#define PPPOL2TP_AVPTYPE_CAUSECODE 12 /* Cause code*/ + +/* -- AVP - Challenge response */ +#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE 13 /* Challenge response */ +#define PPPOL2TP_AVPTYPE_CHALLENGERESPONSE_SIZE 16 + +/* -- AVP - Assign session ID */ +#define PPPOL2TP_AVPTYPE_SESSIONID 14 /* Assign Session ID */ + +/* -- AVP - Call serial number */ +#define PPPOL2TP_AVPTYPE_CALLSERIALNUMBER 15 /* Call Serial Number */ + +/* -- AVP - Framing type */ +#define PPPOL2TP_AVPTYPE_FRAMINGTYPE 19 /* Framing Type */ +#define PPPOL2TP_FRAMINGTYPE 0x00000001 /* Sync framing */ + +/* -- AVP - TX Connect Speed */ +#define PPPOL2TP_AVPTYPE_TXCONNECTSPEED 24 /* TX Connect Speed */ +#define PPPOL2TP_TXCONNECTSPEED 100000000 /* Connect speed: 100 Mbits/s */ + +/* L2TP Session state */ +#define PPPOL2TP_STATE_INITIAL 0 +#define PPPOL2TP_STATE_SCCRQ_SENT 1 +#define PPPOL2TP_STATE_ICRQ_SENT 2 +#define PPPOL2TP_STATE_ICCN_SENT 3 +#define PPPOL2TP_STATE_DATA 4 + +#define PPPOL2TP_OUTPUT_DATA_HEADER_LEN 6 /* Our data header len */ + +/* + * PPPoL2TP interface control block. + */ +typedef struct pppol2tp_pcb_s pppol2tp_pcb; +struct pppol2tp_pcb_s { + ppp_pcb *ppp; /* PPP PCB */ + u8_t phase; /* L2TP phase */ + struct udp_pcb *udp; /* UDP L2TP Socket */ + struct netif *netif; /* Output interface, used as a default route */ + ip_addr_t remote_ip; /* LNS IP Address */ + u16_t remote_port; /* LNS port */ +#if PPPOL2TP_AUTH_SUPPORT + const u8_t *secret; /* Secret string */ + u8_t secret_len; /* Secret string length */ + u8_t secret_rv[16]; /* Random vector */ + u8_t challenge_hash[16]; /* Challenge response */ + u8_t send_challenge; /* Boolean whether the next sent packet should contains a challenge response */ +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + u16_t tunnel_port; /* Tunnel port */ + u16_t our_ns; /* NS to peer */ + u16_t peer_nr; /* NR from peer */ + u16_t peer_ns; /* Expected NS from peer */ + u16_t source_tunnel_id; /* Tunnel ID assigned by peer */ + u16_t remote_tunnel_id; /* Tunnel ID assigned to peer */ + u16_t source_session_id; /* Session ID assigned by peer */ + u16_t remote_session_id; /* Session ID assigned to peer */ + + u8_t sccrq_retried; /* number of SCCRQ retries already done */ + u8_t icrq_retried; /* number of ICRQ retries already done */ + u8_t iccn_retried; /* number of ICCN retries already done */ +}; + + +/* Create a new L2TP session. */ +ppp_pcb *pppol2tp_create(struct netif *pppif, + struct netif *netif, const ip_addr_t *ipaddr, u16_t port, + const u8_t *secret, u8_t secret_len, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb); + +#ifdef __cplusplus +} +#endif + +#endif /* PPPOL2TP_H */ +#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h new file mode 100644 index 0000000..380a965 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/pppos.h @@ -0,0 +1,126 @@ +/** + * @file + * Network Point to Point Protocol over Serial header file. + * + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPPOS_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef PPPOS_H +#define PPPOS_H + +#include "lwip/sys.h" + +#include "ppp.h" +#include "vj.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* PPP packet parser states. Current state indicates operation yet to be + * completed. */ +enum { + PDIDLE = 0, /* Idle state - waiting. */ + PDSTART, /* Process start flag. */ + PDADDRESS, /* Process address field. */ + PDCONTROL, /* Process control field. */ + PDPROTOCOL1, /* Process protocol field 1. */ + PDPROTOCOL2, /* Process protocol field 2. */ + PDDATA /* Process data byte. */ +}; + +/* PPPoS serial output callback function prototype */ +typedef u32_t (*pppos_output_cb_fn)(ppp_pcb *pcb, u8_t *data, u32_t len, void *ctx); + +/* + * Extended asyncmap - allows any character to be escaped. + */ +typedef u8_t ext_accm[32]; + +/* + * PPPoS interface control block. + */ +typedef struct pppos_pcb_s pppos_pcb; +struct pppos_pcb_s { + /* -- below are data that will NOT be cleared between two sessions */ + ppp_pcb *ppp; /* PPP PCB */ + pppos_output_cb_fn output_cb; /* PPP serial output callback */ + + /* -- below are data that will be cleared between two sessions + * + * last_xmit must be the first member of cleared members, because it is + * used to know which part must not be cleared. + */ + u32_t last_xmit; /* Time of last transmission. */ + ext_accm out_accm; /* Async-Ctl-Char-Map for output. */ + + /* flags */ + unsigned int open :1; /* Set if PPPoS is open */ + unsigned int pcomp :1; /* Does peer accept protocol compression? */ + unsigned int accomp :1; /* Does peer accept addr/ctl compression? */ + + /* PPPoS rx */ + ext_accm in_accm; /* Async-Ctl-Char-Map for input. */ + struct pbuf *in_head, *in_tail; /* The input packet. */ + u16_t in_protocol; /* The input protocol code. */ + u16_t in_fcs; /* Input Frame Check Sequence value. */ + u8_t in_state; /* The input process state. */ + u8_t in_escaped; /* Escape next character. */ +}; + +/* Create a new PPPoS session. */ +ppp_pcb *pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb); + +#if !NO_SYS && !PPP_INPROC_IRQ_SAFE +/* Pass received raw characters to PPPoS to be decoded through lwIP TCPIP thread. */ +err_t pppos_input_tcpip(ppp_pcb *ppp, u8_t *s, int l); +#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */ + +/* PPP over Serial: this is the input function to be called for received data. */ +void pppos_input(ppp_pcb *ppp, u8_t* data, int len); + + +/* + * Functions called from lwIP + * DO NOT CALL FROM lwIP USER APPLICATION. + */ +#if !NO_SYS && !PPP_INPROC_IRQ_SAFE +err_t pppos_input_sys(struct pbuf *p, struct netif *inp); +#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */ + +#ifdef __cplusplus +} +#endif + +#endif /* PPPOS_H */ +#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h new file mode 100644 index 0000000..540d981 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/upap.h @@ -0,0 +1,131 @@ +/* + * upap.h - User/Password Authentication Protocol definitions. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: upap.h,v 1.8 2002/12/04 23:03:33 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef UPAP_H +#define UPAP_H + +#include "ppp.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Packet header = Code, id, length. + */ +#define UPAP_HEADERLEN 4 + + +/* + * UPAP codes. + */ +#define UPAP_AUTHREQ 1 /* Authenticate-Request */ +#define UPAP_AUTHACK 2 /* Authenticate-Ack */ +#define UPAP_AUTHNAK 3 /* Authenticate-Nak */ + + +/* + * Client states. + */ +#define UPAPCS_INITIAL 0 /* Connection down */ +#define UPAPCS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPCS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPCS_AUTHREQ 3 /* We've sent an Authenticate-Request */ +#define UPAPCS_OPEN 4 /* We've received an Ack */ +#define UPAPCS_BADAUTH 5 /* We've received a Nak */ + +/* + * Server states. + */ +#define UPAPSS_INITIAL 0 /* Connection down */ +#define UPAPSS_CLOSED 1 /* Connection up, haven't requested auth */ +#define UPAPSS_PENDING 2 /* Connection down, have requested auth */ +#define UPAPSS_LISTEN 3 /* Listening for an Authenticate */ +#define UPAPSS_OPEN 4 /* We've sent an Ack */ +#define UPAPSS_BADAUTH 5 /* We've sent a Nak */ + + +/* + * Timeouts. + */ +#if 0 /* moved to ppp_opts.h */ +#define UPAP_DEFTIMEOUT 3 /* Timeout (seconds) for retransmitting req */ +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif /* moved to ppp_opts.h */ + +/* + * Each interface is described by upap structure. + */ +#if PAP_SUPPORT +typedef struct upap_state { + const char *us_user; /* User */ + u8_t us_userlen; /* User length */ + const char *us_passwd; /* Password */ + u8_t us_passwdlen; /* Password length */ + u8_t us_clientstate; /* Client state */ +#if PPP_SERVER + u8_t us_serverstate; /* Server state */ +#endif /* PPP_SERVER */ + u8_t us_id; /* Current id */ + u8_t us_transmits; /* Number of auth-reqs sent */ +} upap_state; +#endif /* PAP_SUPPORT */ + + +void upap_authwithpeer(ppp_pcb *pcb, const char *user, const char *password); +#if PPP_SERVER +void upap_authpeer(ppp_pcb *pcb); +#endif /* PPP_SERVER */ + +extern const struct protent pap_protent; + +#ifdef __cplusplus +} +#endif + +#endif /* UPAP_H */ +#endif /* PPP_SUPPORT && PAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h new file mode 100644 index 0000000..77d9976 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/ppp/vj.h @@ -0,0 +1,169 @@ +/* + * Definitions for tcp compression routines. + * + * $Id: vj.h,v 1.7 2010/02/22 17:52:09 goldsimon Exp $ + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * - Initial distribution. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && VJ_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#ifndef VJ_H +#define VJ_H + +#include "lwip/ip.h" +#include "lwip/priv/tcp_priv.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_SLOTS 16 /* must be > 2 and < 256 */ +#define MAX_HDR 128 + +/* + * Compressed packet format: + * + * The first octet contains the packet type (top 3 bits), TCP + * 'push' bit, and flags that indicate which of the 4 TCP sequence + * numbers have changed (bottom 5 bits). The next octet is a + * conversation number that associates a saved IP/TCP header with + * the compressed packet. The next two octets are the TCP checksum + * from the original datagram. The next 0 to 15 octets are + * sequence number changes, one change per bit set in the header + * (there may be no changes and there are two special cases where + * the receiver implicitly knows what changed -- see below). + * + * There are 5 numbers which can change (they are always inserted + * in the following order): TCP urgent pointer, window, + * acknowlegement, sequence number and IP ID. (The urgent pointer + * is different from the others in that its value is sent, not the + * change in value.) Since typical use of SLIP links is biased + * toward small packets (see comments on MTU/MSS below), changes + * use a variable length coding with one octet for numbers in the + * range 1 - 255 and 3 octets (0, MSB, LSB) for numbers in the + * range 256 - 65535 or 0. (If the change in sequence number or + * ack is more than 65535, an uncompressed packet is sent.) + */ + +/* + * Packet types (must not conflict with IP protocol version) + * + * The top nibble of the first octet is the packet type. There are + * three possible types: IP (not proto TCP or tcp with one of the + * control flags set); uncompressed TCP (a normal IP/TCP packet but + * with the 8-bit protocol field replaced by an 8-bit connection id -- + * this type of packet syncs the sender & receiver); and compressed + * TCP (described above). + * + * LSB of 4-bit field is TCP "PUSH" bit (a worthless anachronism) and + * is logically part of the 4-bit "changes" field that follows. Top + * three bits are actual packet type. For backward compatibility + * and in the interest of conserving bits, numbers are chosen so the + * IP protocol version number (4) which normally appears in this nibble + * means "IP packet". + */ + +/* packet types */ +#define TYPE_IP 0x40 +#define TYPE_UNCOMPRESSED_TCP 0x70 +#define TYPE_COMPRESSED_TCP 0x80 +#define TYPE_ERROR 0x00 + +/* Bits in first octet of compressed packet */ +#define NEW_C 0x40 /* flag bits for what changed in a packet */ +#define NEW_I 0x20 +#define NEW_S 0x08 +#define NEW_A 0x04 +#define NEW_W 0x02 +#define NEW_U 0x01 + +/* reserved, special-case values of above */ +#define SPECIAL_I (NEW_S|NEW_W|NEW_U) /* echoed interactive traffic */ +#define SPECIAL_D (NEW_S|NEW_A|NEW_W|NEW_U) /* unidirectional data */ +#define SPECIALS_MASK (NEW_S|NEW_A|NEW_W|NEW_U) + +#define TCP_PUSH_BIT 0x10 + + +/* + * "state" data for each active tcp conversation on the wire. This is + * basically a copy of the entire IP/TCP header from the last packet + * we saw from the conversation together with a small identifier + * the transmit & receive ends of the line use to locate saved header. + */ +struct cstate { + struct cstate *cs_next; /* next most recently used state (xmit only) */ + u16_t cs_hlen; /* size of hdr (receive only) */ + u8_t cs_id; /* connection # associated with this state */ + u8_t cs_filler; + union { + char csu_hdr[MAX_HDR]; + struct ip_hdr csu_ip; /* ip/tcp hdr from most recent packet */ + } vjcs_u; +}; +#define cs_ip vjcs_u.csu_ip +#define cs_hdr vjcs_u.csu_hdr + + +struct vjstat { + u32_t vjs_packets; /* outbound packets */ + u32_t vjs_compressed; /* outbound compressed packets */ + u32_t vjs_searches; /* searches for connection state */ + u32_t vjs_misses; /* times couldn't find conn. state */ + u32_t vjs_uncompressedin; /* inbound uncompressed packets */ + u32_t vjs_compressedin; /* inbound compressed packets */ + u32_t vjs_errorin; /* inbound unknown type packets */ + u32_t vjs_tossed; /* inbound packets tossed because of error */ +}; + +/* + * all the state data for one serial line (we need one of these per line). + */ +struct vjcompress { + struct cstate *last_cs; /* most recently used tstate */ + u8_t last_recv; /* last rcvd conn. id */ + u8_t last_xmit; /* last sent conn. id */ + u16_t flags; + u8_t maxSlotIndex; + u8_t compressSlot; /* Flag indicating OK to compress slot ID. */ +#if LINK_STATS + struct vjstat stats; +#endif + struct cstate tstate[MAX_SLOTS]; /* xmit connection states */ + struct cstate rstate[MAX_SLOTS]; /* receive connection states */ +}; + +/* flag values */ +#define VJF_TOSS 1U /* tossing rcvd frames because of input err */ + +extern void vj_compress_init (struct vjcompress *comp); +extern u8_t vj_compress_tcp (struct vjcompress *comp, struct pbuf **pb); +extern void vj_uncompress_err (struct vjcompress *comp); +extern int vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp); +extern int vj_uncompress_tcp (struct pbuf **nb, struct vjcompress *comp); + +#ifdef __cplusplus +} +#endif + +#endif /* VJ_H */ + +#endif /* PPP_SUPPORT && VJ_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/slipif.h b/Middlewares/Third_Party/LwIP/src/include/netif/slipif.h new file mode 100644 index 0000000..65ba31f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/slipif.h @@ -0,0 +1,87 @@ +/** + * @file + * + * SLIP netif API + */ + +/* + * Copyright (c) 2001, Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef LWIP_HDR_NETIF_SLIPIF_H +#define LWIP_HDR_NETIF_SLIPIF_H + +#include "lwip/opt.h" +#include "lwip/netif.h" + +/** Set this to 1 to start a thread that blocks reading on the serial line + * (using sio_read()). + */ +#ifndef SLIP_USE_RX_THREAD +#define SLIP_USE_RX_THREAD !NO_SYS +#endif + +/** Set this to 1 to enable functions to pass in RX bytes from ISR context. + * If enabled, slipif_received_byte[s]() process incoming bytes and put assembled + * packets on a queue, which is fed into lwIP from slipif_poll(). + * If disabled, slipif_poll() polls the serial line (using sio_tryread()). + */ +#ifndef SLIP_RX_FROM_ISR +#define SLIP_RX_FROM_ISR 0 +#endif + +/** Set this to 1 (default for SLIP_RX_FROM_ISR) to queue incoming packets + * received by slipif_received_byte[s]() as long as PBUF_POOL pbufs are available. + * If disabled, packets will be dropped if more than one packet is received. + */ +#ifndef SLIP_RX_QUEUE +#define SLIP_RX_QUEUE SLIP_RX_FROM_ISR +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +err_t slipif_init(struct netif * netif); +void slipif_poll(struct netif *netif); +#if SLIP_RX_FROM_ISR +void slipif_process_rxqueue(struct netif *netif); +void slipif_received_byte(struct netif *netif, u8_t data); +void slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len); +#endif /* SLIP_RX_FROM_ISR */ + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_HDR_NETIF_SLIPIF_H */ + diff --git a/Middlewares/Third_Party/LwIP/src/include/netif/zepif.h b/Middlewares/Third_Party/LwIP/src/include/netif/zepif.h new file mode 100644 index 0000000..2a801b4 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/include/netif/zepif.h @@ -0,0 +1,81 @@ +/** + * @file + * + * A netif implementing the ZigBee Eencapsulation Protocol (ZEP). + * This is used to tunnel 6LowPAN over UDP. + */ + +/* + * Copyright (c) 2018 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#ifndef LWIP_HDR_ZEPIF_H +#define LWIP_HDR_ZEPIF_H + +#include "lwip/opt.h" +#include "netif/lowpan6.h" + +#if LWIP_IPV6 && LWIP_UDP /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/netif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ZEPIF_DEFAULT_UDP_PORT 17754 + +/** Pass this struct as 'state' to netif_add to control the behaviour + * of this netif. If NULL is passed, default behaviour is chosen */ +struct zepif_init { + /** The UDP port used to ZEP frames from (0 = default) */ + u16_t zep_src_udp_port; + /** The UDP port used to ZEP frames to (0 = default) */ + u16_t zep_dst_udp_port; + /** The IP address to sed ZEP frames from (NULL = ANY) */ + const ip_addr_t *zep_src_ip_addr; + /** The IP address to sed ZEP frames to (NULL = BROADCAST) */ + const ip_addr_t *zep_dst_ip_addr; + /** If != NULL, the udp pcb is bound to this netif */ + const struct netif *zep_netif; + /** MAC address of the 6LowPAN device */ + u8_t addr[6]; +}; + +err_t zepif_init(struct netif *netif); + +#ifdef __cplusplus +} +#endif + +#endif /* LWIP_IPV6 && LWIP_UDP */ + +#endif /* LWIP_HDR_ZEPIF_H */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/bridgeif.c b/Middlewares/Third_Party/LwIP/src/netif/bridgeif.c new file mode 100644 index 0000000..8a97bce --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/bridgeif.c @@ -0,0 +1,563 @@ +/** + * @file + * lwIP netif implementing an IEEE 802.1D MAC Bridge + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +/** + * @defgroup bridgeif IEEE 802.1D bridge + * @ingroup netifs + * This file implements an IEEE 802.1D bridge by using a multilayer netif approach + * (one hardware-independent netif for the bridge that uses hardware netifs for its ports). + * On transmit, the bridge selects the outgoing port(s). + * On receive, the port netif calls into the bridge (via its netif->input function) and + * the bridge selects the port(s) (and/or its netif->input function) to pass the received pbuf to. + * + * Usage: + * - add the port netifs just like you would when using them as dedicated netif without a bridge + * - only NETIF_FLAG_ETHARP/NETIF_FLAG_ETHERNET netifs are supported as bridge ports + * - add the bridge port netifs without IPv4 addresses (i.e. pass 'NULL, NULL, NULL') + * - don't add IPv6 addresses to the port netifs! + * - set up the bridge configuration in a global variable of type 'bridgeif_initdata_t' that contains + * - the MAC address of the bridge + * - some configuration options controlling the memory consumption (maximum number of ports + * and FDB entries) + * - e.g. for a bridge MAC address 00-01-02-03-04-05, 2 bridge ports, 1024 FDB entries + 16 static MAC entries: + * bridgeif_initdata_t mybridge_initdata = BRIDGEIF_INITDATA1(2, 1024, 16, ETH_ADDR(0, 1, 2, 3, 4, 5)); + * - add the bridge netif (with IPv4 config): + * struct netif bridge_netif; + * netif_add(&bridge_netif, &my_ip, &my_netmask, &my_gw, &mybridge_initdata, bridgeif_init, tcpip_input); + * NOTE: the passed 'input' function depends on BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT setting, + * which controls where the forwarding is done (netif low level input context vs. tcpip_thread) + * - set up all ports netifs and the bridge netif + * + * - When adding a port netif, NETIF_FLAG_ETHARP flag will be removed from a port + * to prevent ETHARP working on that port netif (we only want one IP per bridge not per port). + * - When adding a port netif, its input function is changed to call into the bridge. + * + * + * @todo: + * - compact static FDB entries (instead of walking the whole array) + * - add FDB query/read access + * - add FDB change callback (when learning or dropping auto-learned entries) + * - prefill FDB with MAC classes that should never be forwarded + * - multicast snooping? (and only forward group addresses to interested ports) + * - support removing ports + * - check SNMP integration + * - VLAN handling / trunk ports + * - priority handling? (although that largely depends on TX queue limitations and lwIP doesn't provide tx-done handling) + */ + +#include "netif/bridgeif.h" +#include "lwip/netif.h" +#include "lwip/sys.h" +#include "lwip/etharp.h" +#include "lwip/ethip6.h" +#include "lwip/snmp.h" +#include "lwip/timeouts.h" +#include + +#if LWIP_NUM_NETIF_CLIENT_DATA + +/* Define those to better describe your network interface. */ +#define IFNAME0 'b' +#define IFNAME1 'r' + +struct bridgeif_private_s; +typedef struct bridgeif_port_private_s { + struct bridgeif_private_s *bridge; + struct netif *port_netif; + u8_t port_num; +} bridgeif_port_t; + +typedef struct bridgeif_fdb_static_entry_s { + u8_t used; + bridgeif_portmask_t dst_ports; + struct eth_addr addr; +} bridgeif_fdb_static_entry_t; + +typedef struct bridgeif_private_s { + struct netif *netif; + struct eth_addr ethaddr; + u8_t max_ports; + u8_t num_ports; + bridgeif_port_t *ports; + u16_t max_fdbs_entries; + bridgeif_fdb_static_entry_t *fdbs; + u16_t max_fdbd_entries; + void *fdbd; +} bridgeif_private_t; + +/* netif data index to get the bridge on input */ +u8_t bridgeif_netif_client_id = 0xff; + +/** + * @ingroup bridgeif + * Add a static entry to the forwarding database. + * A static entry marks where frames to a specific eth address (unicast or group address) are + * forwarded. + * bits [0..(BRIDGEIF_MAX_PORTS-1)]: hw ports + * bit [BRIDGEIF_MAX_PORTS]: cpu port + * 0: drop + */ +err_t +bridgeif_fdb_add(struct netif *bridgeif, const struct eth_addr *addr, bridgeif_portmask_t ports) +{ + int i; + bridgeif_private_t *br; + BRIDGEIF_DECL_PROTECT(lev); + LWIP_ASSERT("invalid netif", bridgeif != NULL); + br = (bridgeif_private_t *)bridgeif->state; + LWIP_ASSERT("invalid state", br != NULL); + + BRIDGEIF_READ_PROTECT(lev); + for (i = 0; i < br->max_fdbs_entries; i++) { + if (!br->fdbs[i].used) { + BRIDGEIF_WRITE_PROTECT(lev); + if (!br->fdbs[i].used) { + br->fdbs[i].used = 1; + br->fdbs[i].dst_ports = ports; + memcpy(&br->fdbs[i].addr, addr, sizeof(struct eth_addr)); + BRIDGEIF_WRITE_UNPROTECT(lev); + BRIDGEIF_READ_UNPROTECT(lev); + return ERR_OK; + } + BRIDGEIF_WRITE_UNPROTECT(lev); + } + } + BRIDGEIF_READ_UNPROTECT(lev); + return ERR_MEM; +} + +/** + * @ingroup bridgeif + * Remove a static entry from the forwarding database + */ +err_t +bridgeif_fdb_remove(struct netif *bridgeif, const struct eth_addr *addr) +{ + int i; + bridgeif_private_t *br; + BRIDGEIF_DECL_PROTECT(lev); + LWIP_ASSERT("invalid netif", bridgeif != NULL); + br = (bridgeif_private_t *)bridgeif->state; + LWIP_ASSERT("invalid state", br != NULL); + + BRIDGEIF_READ_PROTECT(lev); + for (i = 0; i < br->max_fdbs_entries; i++) { + if (br->fdbs[i].used && !memcmp(&br->fdbs[i].addr, addr, sizeof(struct eth_addr))) { + BRIDGEIF_WRITE_PROTECT(lev); + if (br->fdbs[i].used && !memcmp(&br->fdbs[i].addr, addr, sizeof(struct eth_addr))) { + memset(&br->fdbs[i], 0, sizeof(bridgeif_fdb_static_entry_t)); + BRIDGEIF_WRITE_UNPROTECT(lev); + BRIDGEIF_READ_UNPROTECT(lev); + return ERR_OK; + } + BRIDGEIF_WRITE_UNPROTECT(lev); + } + } + BRIDGEIF_READ_UNPROTECT(lev); + return ERR_VAL; +} + +/** Get the forwarding port(s) (as bit mask) for the specified destination mac address */ +static bridgeif_portmask_t +bridgeif_find_dst_ports(bridgeif_private_t *br, struct eth_addr *dst_addr) +{ + int i; + BRIDGEIF_DECL_PROTECT(lev); + BRIDGEIF_READ_PROTECT(lev); + /* first check for static entries */ + for (i = 0; i < br->max_fdbs_entries; i++) { + if (br->fdbs[i].used) { + if (!memcmp(&br->fdbs[i].addr, dst_addr, sizeof(struct eth_addr))) { + bridgeif_portmask_t ret = br->fdbs[i].dst_ports; + BRIDGEIF_READ_UNPROTECT(lev); + return ret; + } + } + } + if (dst_addr->addr[0] & 1) { + /* no match found: flood remaining group address */ + BRIDGEIF_READ_UNPROTECT(lev); + return BR_FLOOD; + } + BRIDGEIF_READ_UNPROTECT(lev); + /* no match found: check dynamic fdb for port or fall back to flooding */ + return bridgeif_fdb_get_dst_ports(br->fdbd, dst_addr); +} + +/** Helper function to see if a destination mac belongs to the bridge + * (bridge netif or one of the port netifs), in which case the frame + * is sent to the cpu only. + */ +static int +bridgeif_is_local_mac(bridgeif_private_t *br, struct eth_addr *addr) +{ + int i; + BRIDGEIF_DECL_PROTECT(lev); + if (!memcmp(br->netif->hwaddr, addr, sizeof(struct eth_addr))) { + return 1; + } + BRIDGEIF_READ_PROTECT(lev); + for (i = 0; i < br->num_ports; i++) { + struct netif *portif = br->ports[i].port_netif; + if (portif != NULL) { + if (!memcmp(portif->hwaddr, addr, sizeof(struct eth_addr))) { + BRIDGEIF_READ_UNPROTECT(lev); + return 1; + } + } + } + BRIDGEIF_READ_UNPROTECT(lev); + return 0; +} + +/* Output helper function */ +static err_t +bridgeif_send_to_port(bridgeif_private_t *br, struct pbuf *p, u8_t dstport_idx) +{ + if (dstport_idx < BRIDGEIF_MAX_PORTS) { + /* possibly an external port */ + if (dstport_idx < br->max_ports) { + struct netif *portif = br->ports[dstport_idx].port_netif; + if ((portif != NULL) && (portif->linkoutput != NULL)) { + /* prevent sending out to rx port */ + if (netif_get_index(portif) != p->if_idx) { + if (netif_is_link_up(portif)) { + LWIP_DEBUGF(BRIDGEIF_FW_DEBUG, ("br -> flood(%p:%d) -> %d\n", (void *)p, p->if_idx, netif_get_index(portif))); + return portif->linkoutput(portif, p); + } + } + } + } + } else { + LWIP_ASSERT("invalid port index", dstport_idx == BRIDGEIF_MAX_PORTS); + } + return ERR_OK; +} + +/** Helper function to pass a pbuf to all ports marked in 'dstports' + */ +static err_t +bridgeif_send_to_ports(bridgeif_private_t *br, struct pbuf *p, bridgeif_portmask_t dstports) +{ + err_t err, ret_err = ERR_OK; + u8_t i; + bridgeif_portmask_t mask = 1; + BRIDGEIF_DECL_PROTECT(lev); + BRIDGEIF_READ_PROTECT(lev); + for (i = 0; i < BRIDGEIF_MAX_PORTS; i++, mask = (bridgeif_portmask_t)(mask << 1)) { + if (dstports & mask) { + err = bridgeif_send_to_port(br, p, i); + if (err != ERR_OK) { + ret_err = err; + } + } + } + BRIDGEIF_READ_UNPROTECT(lev); + return ret_err; +} + +/** Output function of the application port of the bridge (the one with an ip address). + * The forwarding port(s) where this pbuf is sent on is/are automatically selected + * from the FDB. + */ +static err_t +bridgeif_output(struct netif *netif, struct pbuf *p) +{ + err_t err; + bridgeif_private_t *br = (bridgeif_private_t *)netif->state; + struct eth_addr *dst = (struct eth_addr *)(p->payload); + + bridgeif_portmask_t dstports = bridgeif_find_dst_ports(br, dst); + err = bridgeif_send_to_ports(br, p, dstports); + + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len); + if (((u8_t *)p->payload)[0] & 1) { + /* broadcast or multicast packet*/ + MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); + } else { + /* unicast packet */ + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + } + /* increase ifoutdiscards or ifouterrors on error */ + + LINK_STATS_INC(link.xmit); + + return err; +} + +/** The actual bridge input function. Port netif's input is changed to call + * here. This function decides where the frame is forwarded. + */ +static err_t +bridgeif_input(struct pbuf *p, struct netif *netif) +{ + u8_t rx_idx; + bridgeif_portmask_t dstports; + struct eth_addr *src, *dst; + bridgeif_private_t *br; + bridgeif_port_t *port; + if (p == NULL || netif == NULL) { + return ERR_VAL; + } + port = (bridgeif_port_t *)netif_get_client_data(netif, bridgeif_netif_client_id); + LWIP_ASSERT("port data not set", port != NULL); + if (port == NULL || port->bridge == NULL) { + return ERR_VAL; + } + br = (bridgeif_private_t *)port->bridge; + rx_idx = netif_get_index(netif); + /* store receive index in pbuf */ + p->if_idx = rx_idx; + + dst = (struct eth_addr *)p->payload; + src = (struct eth_addr *)(((u8_t *)p->payload) + sizeof(struct eth_addr)); + + if ((src->addr[0] & 1) == 0) { + /* update src for all non-group addresses */ + bridgeif_fdb_update_src(br->fdbd, src, port->port_num); + } + + if (dst->addr[0] & 1) { + /* group address -> flood + cpu? */ + dstports = bridgeif_find_dst_ports(br, dst); + bridgeif_send_to_ports(br, p, dstports); + if (dstports & (1 << BRIDGEIF_MAX_PORTS)) { + /* we pass the reference to ->input or have to free it */ + LWIP_DEBUGF(BRIDGEIF_FW_DEBUG, ("br -> input(%p)\n", (void *)p)); + if (br->netif->input(p, br->netif) != ERR_OK) { + pbuf_free(p); + } + } else { + /* all references done */ + pbuf_free(p); + } + /* always return ERR_OK here to prevent the caller freeing the pbuf */ + return ERR_OK; + } else { + /* is this for one of the local ports? */ + if (bridgeif_is_local_mac(br, dst)) { + /* yes, send to cpu port only */ + LWIP_DEBUGF(BRIDGEIF_FW_DEBUG, ("br -> input(%p)\n", (void *)p)); + return br->netif->input(p, br->netif); + } + + /* get dst port */ + dstports = bridgeif_find_dst_ports(br, dst); + bridgeif_send_to_ports(br, p, dstports); + /* no need to send to cpu, flooding is for external ports only */ + /* by this, we consumed the pbuf */ + pbuf_free(p); + /* always return ERR_OK here to prevent the caller freeing the pbuf */ + return ERR_OK; + } +} + +#if !BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT +/** Input function for port netifs used to synchronize into tcpip_thread. + */ +static err_t +bridgeif_tcpip_input(struct pbuf *p, struct netif *netif) +{ + return tcpip_inpkt(p, netif, bridgeif_input); +} +#endif /* BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT */ + +/** + * @ingroup bridgeif + * Initialization function passed to netif_add(). + * + * ATTENTION: A pointer to a @ref bridgeif_initdata_t must be passed as 'state' + * to @ref netif_add when adding the bridge. I supplies MAC address + * and controls memory allocation (number of ports, FDB size). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialized + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +err_t +bridgeif_init(struct netif *netif) +{ + bridgeif_initdata_t *init_data; + bridgeif_private_t *br; + size_t alloc_len_sizet; + mem_size_t alloc_len; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("bridgeif needs an input callback", (netif->input != NULL)); +#if !BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT + if (netif->input == tcpip_input) { + LWIP_DEBUGF(BRIDGEIF_DEBUG | LWIP_DBG_ON, ("bridgeif does not need tcpip_input, use netif_input/ethernet_input instead")); + } +#endif + + if (bridgeif_netif_client_id == 0xFF) { + bridgeif_netif_client_id = netif_alloc_client_data_id(); + } + + init_data = (bridgeif_initdata_t *)netif->state; + LWIP_ASSERT("init_data != NULL", (init_data != NULL)); + LWIP_ASSERT("init_data->max_ports <= BRIDGEIF_MAX_PORTS", + init_data->max_ports <= BRIDGEIF_MAX_PORTS); + + alloc_len_sizet = sizeof(bridgeif_private_t) + (init_data->max_ports * sizeof(bridgeif_port_t) + (init_data->max_fdb_static_entries * sizeof(bridgeif_fdb_static_entry_t))); + alloc_len = (mem_size_t)alloc_len_sizet; + LWIP_ASSERT("alloc_len == alloc_len_sizet", alloc_len == alloc_len_sizet); + LWIP_DEBUGF(BRIDGEIF_DEBUG, ("bridgeif_init: allocating %d bytes for private data\n", (int)alloc_len)); + br = (bridgeif_private_t *)mem_calloc(1, alloc_len); + if (br == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("bridgeif_init: out of memory\n")); + return ERR_MEM; + } + memcpy(&br->ethaddr, &init_data->ethaddr, sizeof(br->ethaddr)); + br->netif = netif; + + br->max_ports = init_data->max_ports; + br->ports = (bridgeif_port_t *)(br + 1); + + br->max_fdbs_entries = init_data->max_fdb_static_entries; + br->fdbs = (bridgeif_fdb_static_entry_t *)(((u8_t *)(br + 1)) + (init_data->max_ports * sizeof(bridgeif_port_t))); + + br->max_fdbd_entries = init_data->max_fdb_dynamic_entries; + br->fdbd = bridgeif_fdb_init(init_data->max_fdb_dynamic_entries); + if (br->fdbd == NULL) { + LWIP_DEBUGF(NETIF_DEBUG, ("bridgeif_init: out of memory in fdb_init\n")); + mem_free(br); + return ERR_MEM; + } + +#if LWIP_NETIF_HOSTNAME + /* Initialize interface hostname */ + netif->hostname = "lwip"; +#endif /* LWIP_NETIF_HOSTNAME */ + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, 0); + + netif->state = br; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ +#if LWIP_IPV4 + netif->output = etharp_output; +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 + netif->output_ip6 = ethip6_output; +#endif /* LWIP_IPV6 */ + netif->linkoutput = bridgeif_output; + + /* set MAC hardware address length */ + netif->hwaddr_len = ETH_HWADDR_LEN; + + /* set MAC hardware address */ + memcpy(netif->hwaddr, &br->ethaddr, ETH_HWADDR_LEN); + + /* maximum transfer unit */ + netif->mtu = 1500; + + /* device capabilities */ + /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP | NETIF_FLAG_MLD6 | NETIF_FLAG_LINK_UP; + +#if LWIP_IPV6 && LWIP_IPV6_MLD + /* + * For hardware/netifs that implement MAC filtering. + * All-nodes link-local is handled by default, so we must let the hardware know + * to allow multicast packets in. + * Should set mld_mac_filter previously. */ + if (netif->mld_mac_filter != NULL) { + ip6_addr_t ip6_allnodes_ll; + ip6_addr_set_allnodes_linklocal(&ip6_allnodes_ll); + netif->mld_mac_filter(netif, &ip6_allnodes_ll, NETIF_ADD_MAC_FILTER); + } +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + + return ERR_OK; +} + +/** + * @ingroup bridgeif + * Add a port to the bridge + */ +err_t +bridgeif_add_port(struct netif *bridgeif, struct netif *portif) +{ + bridgeif_private_t *br; + bridgeif_port_t *port; + + LWIP_ASSERT("bridgeif != NULL", bridgeif != NULL); + LWIP_ASSERT("bridgeif->state != NULL", bridgeif->state != NULL); + LWIP_ASSERT("portif != NULL", portif != NULL); + + if (!(portif->flags & NETIF_FLAG_ETHARP) || !(portif->flags & NETIF_FLAG_ETHERNET)) { + /* can only add ETHERNET/ETHARP interfaces */ + return ERR_VAL; + } + + br = (bridgeif_private_t *)bridgeif->state; + + if (br->num_ports >= br->max_ports) { + return ERR_VAL; + } + port = &br->ports[br->num_ports]; + port->port_netif = portif; + port->port_num = br->num_ports; + port->bridge = br; + br->num_ports++; + + /* let the port call us on input */ +#if BRIDGEIF_PORT_NETIFS_OUTPUT_DIRECT + portif->input = bridgeif_input; +#else + portif->input = bridgeif_tcpip_input; +#endif + /* store pointer to bridge in netif */ + netif_set_client_data(portif, bridgeif_netif_client_id, port); + /* remove ETHARP flag to prevent sending report events on netif-up */ + netif_clear_flags(portif, NETIF_FLAG_ETHARP); + + return ERR_OK; +} + +#endif /* LWIP_NUM_NETIF_CLIENT_DATA */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c b/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c new file mode 100644 index 0000000..6739fc2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/bridgeif_fdb.c @@ -0,0 +1,212 @@ +/** + * @file + * lwIP netif implementing an FDB for IEEE 802.1D MAC Bridge + */ + +/* + * Copyright (c) 2017 Simon Goldschmidt. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +/** + * @defgroup bridgeif_fdb FDB example code + * @ingroup bridgeif + * This file implements an example for an FDB (Forwarding DataBase) + */ + +#include "netif/bridgeif.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "lwip/timeouts.h" +#include + +#define BRIDGEIF_AGE_TIMER_MS 1000 + +#define BR_FDB_TIMEOUT_SEC (60*5) /* 5 minutes FDB timeout */ + +typedef struct bridgeif_dfdb_entry_s { + u8_t used; + u8_t port; + u32_t ts; + struct eth_addr addr; +} bridgeif_dfdb_entry_t; + +typedef struct bridgeif_dfdb_s { + u16_t max_fdb_entries; + bridgeif_dfdb_entry_t *fdb; +} bridgeif_dfdb_t; + +/** + * @ingroup bridgeif_fdb + * A real simple and slow implementation of an auto-learning forwarding database that + * remembers known src mac addresses to know which port to send frames destined for that + * mac address. + * + * ATTENTION: This is meant as an example only, in real-world use, you should + * provide a better implementation :-) + */ +void +bridgeif_fdb_update_src(void *fdb_ptr, struct eth_addr *src_addr, u8_t port_idx) +{ + int i; + bridgeif_dfdb_t *fdb = (bridgeif_dfdb_t *)fdb_ptr; + BRIDGEIF_DECL_PROTECT(lev); + BRIDGEIF_READ_PROTECT(lev); + for (i = 0; i < fdb->max_fdb_entries; i++) { + bridgeif_dfdb_entry_t *e = &fdb->fdb[i]; + if (e->used && e->ts) { + if (!memcmp(&e->addr, src_addr, sizeof(struct eth_addr))) { + LWIP_DEBUGF(BRIDGEIF_FDB_DEBUG, ("br: update src %02x:%02x:%02x:%02x:%02x:%02x (from %d) @ idx %d\n", + src_addr->addr[0], src_addr->addr[1], src_addr->addr[2], src_addr->addr[3], src_addr->addr[4], src_addr->addr[5], + port_idx, i)); + BRIDGEIF_WRITE_PROTECT(lev); + e->ts = BR_FDB_TIMEOUT_SEC; + e->port = port_idx; + BRIDGEIF_WRITE_UNPROTECT(lev); + BRIDGEIF_READ_UNPROTECT(lev); + return; + } + } + } + /* not found, allocate new entry from free */ + for (i = 0; i < fdb->max_fdb_entries; i++) { + bridgeif_dfdb_entry_t *e = &fdb->fdb[i]; + if (!e->used || !e->ts) { + BRIDGEIF_WRITE_PROTECT(lev); + /* check again when protected */ + if (!e->used || !e->ts) { + LWIP_DEBUGF(BRIDGEIF_FDB_DEBUG, ("br: create src %02x:%02x:%02x:%02x:%02x:%02x (from %d) @ idx %d\n", + src_addr->addr[0], src_addr->addr[1], src_addr->addr[2], src_addr->addr[3], src_addr->addr[4], src_addr->addr[5], + port_idx, i)); + memcpy(&e->addr, src_addr, sizeof(struct eth_addr)); + e->ts = BR_FDB_TIMEOUT_SEC; + e->port = port_idx; + e->used = 1; + BRIDGEIF_WRITE_UNPROTECT(lev); + BRIDGEIF_READ_UNPROTECT(lev); + return; + } + BRIDGEIF_WRITE_UNPROTECT(lev); + } + } + BRIDGEIF_READ_UNPROTECT(lev); + /* not found, no free entry -> flood */ +} + +/** + * @ingroup bridgeif_fdb + * Walk our list of auto-learnt fdb entries and return a port to forward or BR_FLOOD if unknown + */ +bridgeif_portmask_t +bridgeif_fdb_get_dst_ports(void *fdb_ptr, struct eth_addr *dst_addr) +{ + int i; + bridgeif_dfdb_t *fdb = (bridgeif_dfdb_t *)fdb_ptr; + BRIDGEIF_DECL_PROTECT(lev); + BRIDGEIF_READ_PROTECT(lev); + for (i = 0; i < fdb->max_fdb_entries; i++) { + bridgeif_dfdb_entry_t *e = &fdb->fdb[i]; + if (e->used && e->ts) { + if (!memcmp(&e->addr, dst_addr, sizeof(struct eth_addr))) { + bridgeif_portmask_t ret = (bridgeif_portmask_t)(1 << e->port); + BRIDGEIF_READ_UNPROTECT(lev); + return ret; + } + } + } + BRIDGEIF_READ_UNPROTECT(lev); + return BR_FLOOD; +} + +/** + * @ingroup bridgeif_fdb + * Aging implementation of our simple fdb + */ +static void +bridgeif_fdb_age_one_second(void *fdb_ptr) +{ + int i; + bridgeif_dfdb_t *fdb; + BRIDGEIF_DECL_PROTECT(lev); + + fdb = (bridgeif_dfdb_t *)fdb_ptr; + BRIDGEIF_READ_PROTECT(lev); + + for (i = 0; i < fdb->max_fdb_entries; i++) { + bridgeif_dfdb_entry_t *e = &fdb->fdb[i]; + if (e->used && e->ts) { + BRIDGEIF_WRITE_PROTECT(lev); + /* check again when protected */ + if (e->used && e->ts) { + if (--e->ts == 0) { + e->used = 0; + } + } + BRIDGEIF_WRITE_UNPROTECT(lev); + } + } + BRIDGEIF_READ_UNPROTECT(lev); +} + +/** Timer callback for fdb aging, called once per second */ +static void +bridgeif_age_tmr(void *arg) +{ + bridgeif_dfdb_t *fdb = (bridgeif_dfdb_t *)arg; + + LWIP_ASSERT("invalid arg", arg != NULL); + + bridgeif_fdb_age_one_second(fdb); + sys_timeout(BRIDGEIF_AGE_TIMER_MS, bridgeif_age_tmr, arg); +} + +/** + * @ingroup bridgeif_fdb + * Init our simple fdb list + */ +void * +bridgeif_fdb_init(u16_t max_fdb_entries) +{ + bridgeif_dfdb_t *fdb; + size_t alloc_len_sizet = sizeof(bridgeif_dfdb_t) + (max_fdb_entries * sizeof(bridgeif_dfdb_entry_t)); + mem_size_t alloc_len = (mem_size_t)alloc_len_sizet; + LWIP_ASSERT("alloc_len == alloc_len_sizet", alloc_len == alloc_len_sizet); + LWIP_DEBUGF(BRIDGEIF_DEBUG, ("bridgeif_fdb_init: allocating %d bytes for private FDB data\n", (int)alloc_len)); + fdb = (bridgeif_dfdb_t *)mem_calloc(1, alloc_len); + if (fdb == NULL) { + return NULL; + } + fdb->max_fdb_entries = max_fdb_entries; + fdb->fdb = (bridgeif_dfdb_entry_t *)(fdb + 1); + + sys_timeout(BRIDGEIF_AGE_TIMER_MS, bridgeif_age_tmr, fdb); + + return fdb; +} diff --git a/Middlewares/Third_Party/LwIP/src/netif/ethernet.c b/Middlewares/Third_Party/LwIP/src/netif/ethernet.c new file mode 100644 index 0000000..dd171e2 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ethernet.c @@ -0,0 +1,321 @@ +/** + * @file + * Ethernet common functions + * + * @defgroup ethernet Ethernet + * @ingroup callbackstyle_api + */ + +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * Copyright (c) 2003-2004 Leon Woestenberg + * Copyright (c) 2003-2004 Axon Digital Design B.V., The Netherlands. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "lwip/opt.h" + +#if LWIP_ARP || LWIP_ETHERNET + +#include "netif/ethernet.h" +#include "lwip/def.h" +#include "lwip/stats.h" +#include "lwip/etharp.h" +#include "lwip/ip.h" +#include "lwip/snmp.h" + +#include + +#include "netif/ppp/ppp_opts.h" +#if PPPOE_SUPPORT +#include "netif/ppp/pppoe.h" +#endif /* PPPOE_SUPPORT */ + +#ifdef LWIP_HOOK_FILENAME +#include LWIP_HOOK_FILENAME +#endif + +const struct eth_addr ethbroadcast = {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; +const struct eth_addr ethzero = {{0, 0, 0, 0, 0, 0}}; + +/** + * @ingroup lwip_nosys + * Process received ethernet frames. Using this function instead of directly + * calling ip_input and passing ARP frames through etharp in ethernetif_input, + * the ARP cache is protected from concurrent access.\n + * Don't call directly, pass to netif_add() and call netif->input(). + * + * @param p the received packet, p->payload pointing to the ethernet header + * @param netif the network interface on which the packet was received + * + * @see LWIP_HOOK_UNKNOWN_ETH_PROTOCOL + * @see ETHARP_SUPPORT_VLAN + * @see LWIP_HOOK_VLAN_CHECK + */ +err_t +ethernet_input(struct pbuf *p, struct netif *netif) +{ + struct eth_hdr *ethhdr; + u16_t type; +#if LWIP_ARP || ETHARP_SUPPORT_VLAN || LWIP_IPV6 + u16_t next_hdr_offset = SIZEOF_ETH_HDR; +#endif /* LWIP_ARP || ETHARP_SUPPORT_VLAN */ + + LWIP_ASSERT_CORE_LOCKED(); + + if (p->len <= SIZEOF_ETH_HDR) { + /* a packet with only an ethernet header (or less) is not valid for us */ + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + MIB2_STATS_NETIF_INC(netif, ifinerrors); + goto free_and_return; + } + + if (p->if_idx == NETIF_NO_INDEX) { + p->if_idx = netif_get_index(netif); + } + + /* points to packet payload, which starts with an Ethernet header */ + ethhdr = (struct eth_hdr *)p->payload; + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, + ("ethernet_input: dest:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", src:%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F":%"X8_F", type:%"X16_F"\n", + (unsigned char)ethhdr->dest.addr[0], (unsigned char)ethhdr->dest.addr[1], (unsigned char)ethhdr->dest.addr[2], + (unsigned char)ethhdr->dest.addr[3], (unsigned char)ethhdr->dest.addr[4], (unsigned char)ethhdr->dest.addr[5], + (unsigned char)ethhdr->src.addr[0], (unsigned char)ethhdr->src.addr[1], (unsigned char)ethhdr->src.addr[2], + (unsigned char)ethhdr->src.addr[3], (unsigned char)ethhdr->src.addr[4], (unsigned char)ethhdr->src.addr[5], + lwip_htons(ethhdr->type))); + + type = ethhdr->type; +#if ETHARP_SUPPORT_VLAN + if (type == PP_HTONS(ETHTYPE_VLAN)) { + struct eth_vlan_hdr *vlan = (struct eth_vlan_hdr *)(((char *)ethhdr) + SIZEOF_ETH_HDR); + next_hdr_offset = SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR; + if (p->len <= SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) { + /* a packet with only an ethernet/vlan header (or less) is not valid for us */ + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + MIB2_STATS_NETIF_INC(netif, ifinerrors); + goto free_and_return; + } +#if defined(LWIP_HOOK_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK_FN) /* if not, allow all VLANs */ +#ifdef LWIP_HOOK_VLAN_CHECK + if (!LWIP_HOOK_VLAN_CHECK(netif, ethhdr, vlan)) { +#elif defined(ETHARP_VLAN_CHECK_FN) + if (!ETHARP_VLAN_CHECK_FN(ethhdr, vlan)) { +#elif defined(ETHARP_VLAN_CHECK) + if (VLAN_ID(vlan) != ETHARP_VLAN_CHECK) { +#endif + /* silently ignore this packet: not for our VLAN */ + pbuf_free(p); + return ERR_OK; + } +#endif /* defined(LWIP_HOOK_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK) || defined(ETHARP_VLAN_CHECK_FN) */ + type = vlan->tpid; + } +#endif /* ETHARP_SUPPORT_VLAN */ + +#if LWIP_ARP_FILTER_NETIF + netif = LWIP_ARP_FILTER_NETIF_FN(p, netif, lwip_htons(type)); +#endif /* LWIP_ARP_FILTER_NETIF*/ + + if (ethhdr->dest.addr[0] & 1) { + /* this might be a multicast or broadcast packet */ + if (ethhdr->dest.addr[0] == LL_IP4_MULTICAST_ADDR_0) { +#if LWIP_IPV4 + if ((ethhdr->dest.addr[1] == LL_IP4_MULTICAST_ADDR_1) && + (ethhdr->dest.addr[2] == LL_IP4_MULTICAST_ADDR_2)) { + /* mark the pbuf as link-layer multicast */ + p->flags |= PBUF_FLAG_LLMCAST; + } +#endif /* LWIP_IPV4 */ + } +#if LWIP_IPV6 + else if ((ethhdr->dest.addr[0] == LL_IP6_MULTICAST_ADDR_0) && + (ethhdr->dest.addr[1] == LL_IP6_MULTICAST_ADDR_1)) { + /* mark the pbuf as link-layer multicast */ + p->flags |= PBUF_FLAG_LLMCAST; + } +#endif /* LWIP_IPV6 */ + else if (eth_addr_cmp(ðhdr->dest, ðbroadcast)) { + /* mark the pbuf as link-layer broadcast */ + p->flags |= PBUF_FLAG_LLBCAST; + } + } + + switch (type) { +#if LWIP_IPV4 && LWIP_ARP + /* IP packet? */ + case PP_HTONS(ETHTYPE_IP): + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + goto free_and_return; + } + /* skip Ethernet header (min. size checked above) */ + if (pbuf_remove_header(p, next_hdr_offset)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("ethernet_input: IPv4 packet dropped, too short (%"U16_F"/%"U16_F")\n", + p->tot_len, next_hdr_offset)); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("Can't move over header in packet")); + goto free_and_return; + } else { + /* pass to IP layer */ + ip4_input(p, netif); + } + break; + + case PP_HTONS(ETHTYPE_ARP): + if (!(netif->flags & NETIF_FLAG_ETHARP)) { + goto free_and_return; + } + /* skip Ethernet header (min. size checked above) */ + if (pbuf_remove_header(p, next_hdr_offset)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("ethernet_input: ARP response packet dropped, too short (%"U16_F"/%"U16_F")\n", + p->tot_len, next_hdr_offset)); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, ("Can't move over header in packet")); + ETHARP_STATS_INC(etharp.lenerr); + ETHARP_STATS_INC(etharp.drop); + goto free_and_return; + } else { + /* pass p to ARP module */ + etharp_input(p, netif); + } + break; +#endif /* LWIP_IPV4 && LWIP_ARP */ +#if PPPOE_SUPPORT + case PP_HTONS(ETHTYPE_PPPOEDISC): /* PPP Over Ethernet Discovery Stage */ + pppoe_disc_input(netif, p); + break; + + case PP_HTONS(ETHTYPE_PPPOE): /* PPP Over Ethernet Session Stage */ + pppoe_data_input(netif, p); + break; +#endif /* PPPOE_SUPPORT */ + +#if LWIP_IPV6 + case PP_HTONS(ETHTYPE_IPV6): /* IPv6 */ + /* skip Ethernet header */ + if ((p->len < next_hdr_offset) || pbuf_remove_header(p, next_hdr_offset)) { + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_WARNING, + ("ethernet_input: IPv6 packet dropped, too short (%"U16_F"/%"U16_F")\n", + p->tot_len, next_hdr_offset)); + goto free_and_return; + } else { + /* pass to IPv6 layer */ + ip6_input(p, netif); + } + break; +#endif /* LWIP_IPV6 */ + + default: +#ifdef LWIP_HOOK_UNKNOWN_ETH_PROTOCOL + if (LWIP_HOOK_UNKNOWN_ETH_PROTOCOL(p, netif) == ERR_OK) { + break; + } +#endif + ETHARP_STATS_INC(etharp.proterr); + ETHARP_STATS_INC(etharp.drop); + MIB2_STATS_NETIF_INC(netif, ifinunknownprotos); + goto free_and_return; + } + + /* This means the pbuf is freed or consumed, + so the caller doesn't have to free it again */ + return ERR_OK; + +free_and_return: + pbuf_free(p); + return ERR_OK; +} + +/** + * @ingroup ethernet + * Send an ethernet packet on the network using netif->linkoutput(). + * The ethernet header is filled in before sending. + * + * @see LWIP_HOOK_VLAN_SET + * + * @param netif the lwIP network interface on which to send the packet + * @param p the packet to send. pbuf layer must be @ref PBUF_LINK. + * @param src the source MAC address to be copied into the ethernet header + * @param dst the destination MAC address to be copied into the ethernet header + * @param eth_type ethernet type (@ref lwip_ieee_eth_type) + * @return ERR_OK if the packet was sent, any other err_t on failure + */ +err_t +ethernet_output(struct netif * netif, struct pbuf * p, + const struct eth_addr * src, const struct eth_addr * dst, + u16_t eth_type) { + struct eth_hdr *ethhdr; + u16_t eth_type_be = lwip_htons(eth_type); + +#if ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) + s32_t vlan_prio_vid = LWIP_HOOK_VLAN_SET(netif, p, src, dst, eth_type); + if (vlan_prio_vid >= 0) { + struct eth_vlan_hdr *vlanhdr; + + LWIP_ASSERT("prio_vid must be <= 0xFFFF", vlan_prio_vid <= 0xFFFF); + + if (pbuf_add_header(p, SIZEOF_ETH_HDR + SIZEOF_VLAN_HDR) != 0) { + goto pbuf_header_failed; + } + vlanhdr = (struct eth_vlan_hdr *)(((u8_t *)p->payload) + SIZEOF_ETH_HDR); + vlanhdr->tpid = eth_type_be; + vlanhdr->prio_vid = lwip_htons((u16_t)vlan_prio_vid); + + eth_type_be = PP_HTONS(ETHTYPE_VLAN); + } else +#endif /* ETHARP_SUPPORT_VLAN && defined(LWIP_HOOK_VLAN_SET) */ + { + if (pbuf_add_header(p, SIZEOF_ETH_HDR) != 0) { + goto pbuf_header_failed; + } + } + + LWIP_ASSERT_CORE_LOCKED(); + + ethhdr = (struct eth_hdr *)p->payload; + ethhdr->type = eth_type_be; + SMEMCPY(ðhdr->dest, dst, ETH_HWADDR_LEN); + SMEMCPY(ðhdr->src, src, ETH_HWADDR_LEN); + + LWIP_ASSERT("netif->hwaddr_len must be 6 for ethernet_output!", + (netif->hwaddr_len == ETH_HWADDR_LEN)); + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE, + ("ethernet_output: sending packet %p\n", (void *)p)); + + /* send the packet */ + return netif->linkoutput(netif, p); + +pbuf_header_failed: + LWIP_DEBUGF(ETHARP_DEBUG | LWIP_DBG_TRACE | LWIP_DBG_LEVEL_SERIOUS, + ("ethernet_output: could not allocate room for header.\n")); + LINK_STATS_INC(link.lenerr); + return ERR_BUF; +} + +#endif /* LWIP_ARP || LWIP_ETHERNET */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/lowpan6.c b/Middlewares/Third_Party/LwIP/src/netif/lowpan6.c new file mode 100644 index 0000000..7f0d276 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/lowpan6.c @@ -0,0 +1,920 @@ +/** + * @file + * + * 6LowPAN output for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units. + * + * This implementation aims to conform to IEEE 802.15.4(-2015), RFC 4944 and RFC 6282. + * @todo: RFC 6775. + */ + +/* + * Copyright (c) 2015 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +/** + * @defgroup sixlowpan 6LoWPAN (RFC4944) + * @ingroup netifs + * 6LowPAN netif implementation + */ + +#include "netif/lowpan6.h" + +#if LWIP_IPV6 + +#include "lwip/ip.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/nd6.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/tcpip.h" +#include "lwip/snmp.h" +#include "netif/ieee802154.h" + +#include + +#if LWIP_6LOWPAN_802154_HW_CRC +#define LWIP_6LOWPAN_DO_CALC_CRC(buf, len) 0 +#else +#define LWIP_6LOWPAN_DO_CALC_CRC(buf, len) LWIP_6LOWPAN_CALC_CRC(buf, len) +#endif + +/** This is a helper struct for reassembly of fragments + * (IEEE 802.15.4 limits to 127 bytes) + */ +struct lowpan6_reass_helper { + struct lowpan6_reass_helper *next_packet; + struct pbuf *reass; + struct pbuf *frags; + u8_t timer; + struct lowpan6_link_addr sender_addr; + u16_t datagram_size; + u16_t datagram_tag; +}; + +/** This struct keeps track of per-netif state */ +struct lowpan6_ieee802154_data { + /** fragment reassembly list */ + struct lowpan6_reass_helper *reass_list; +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 + /** address context for compression */ + ip6_addr_t lowpan6_context[LWIP_6LOWPAN_NUM_CONTEXTS]; +#endif + /** Datagram Tag for fragmentation */ + u16_t tx_datagram_tag; + /** local PAN ID for IEEE 802.15.4 header */ + u16_t ieee_802154_pan_id; + /** Sequence Number for IEEE 802.15.4 transmission */ + u8_t tx_frame_seq_num; +}; + +/* Maximum frame size is 127 bytes minus CRC size */ +#define LOWPAN6_MAX_PAYLOAD (127 - 2) + +/** Currently, this state is global, since there's only one 6LoWPAN netif */ +static struct lowpan6_ieee802154_data lowpan6_data; + +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 +#define LWIP_6LOWPAN_CONTEXTS(netif) lowpan6_data.lowpan6_context +#else +#define LWIP_6LOWPAN_CONTEXTS(netif) NULL +#endif + +static const struct lowpan6_link_addr ieee_802154_broadcast = {2, {0xff, 0xff}}; + +#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS +static struct lowpan6_link_addr short_mac_addr = {2, {0, 0}}; +#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ + +/* IEEE 802.15.4 specific functions: */ + +/** Write the IEEE 802.15.4 header that encapsulates the 6LoWPAN frame. + * Src and dst PAN IDs are filled with the ID set by @ref lowpan6_set_pan_id. + * + * Since the length is variable: + * @returns the header length + */ +static u8_t +lowpan6_write_iee802154_header(struct ieee_802154_hdr *hdr, const struct lowpan6_link_addr *src, + const struct lowpan6_link_addr *dst) +{ + u8_t ieee_header_len; + u8_t *buffer; + u8_t i; + u16_t fc; + + fc = IEEE_802154_FC_FT_DATA; /* send data packet (2003 frame version) */ + fc |= IEEE_802154_FC_PANID_COMPR; /* set PAN ID compression, for now src and dst PANs are equal */ + if (dst != &ieee_802154_broadcast) { + fc |= IEEE_802154_FC_ACK_REQ; /* data packet, no broadcast: ack required. */ + } + if (dst->addr_len == 2) { + fc |= IEEE_802154_FC_DST_ADDR_MODE_SHORT; + } else { + LWIP_ASSERT("invalid dst address length", dst->addr_len == 8); + fc |= IEEE_802154_FC_DST_ADDR_MODE_EXT; + } + if (src->addr_len == 2) { + fc |= IEEE_802154_FC_SRC_ADDR_MODE_SHORT; + } else { + LWIP_ASSERT("invalid src address length", src->addr_len == 8); + fc |= IEEE_802154_FC_SRC_ADDR_MODE_EXT; + } + hdr->frame_control = fc; + hdr->sequence_number = lowpan6_data.tx_frame_seq_num++; + hdr->destination_pan_id = lowpan6_data.ieee_802154_pan_id; /* pan id */ + + buffer = (u8_t *)hdr; + ieee_header_len = 5; + i = dst->addr_len; + /* reverse memcpy of dst addr */ + while (i-- > 0) { + buffer[ieee_header_len++] = dst->addr[i]; + } + /* Source PAN ID skipped due to PAN ID Compression */ + i = src->addr_len; + /* reverse memcpy of src addr */ + while (i-- > 0) { + buffer[ieee_header_len++] = src->addr[i]; + } + return ieee_header_len; +} + +/** Parse the IEEE 802.15.4 header from a pbuf. + * If successful, the header is hidden from the pbuf. + * + * PAN IDs and seuqence number are not checked + * + * @param p input pbuf, p->payload pointing at the IEEE 802.15.4 header + * @param src pointer to source address filled from the header + * @param dest pointer to destination address filled from the header + * @returns ERR_OK if successful + */ +static err_t +lowpan6_parse_iee802154_header(struct pbuf *p, struct lowpan6_link_addr *src, + struct lowpan6_link_addr *dest) +{ + u8_t *puc; + s8_t i; + u16_t frame_control, addr_mode; + u16_t datagram_offset; + + /* Parse IEEE 802.15.4 header */ + puc = (u8_t *)p->payload; + frame_control = puc[0] | (puc[1] << 8); + datagram_offset = 2; + if (frame_control & IEEE_802154_FC_SEQNO_SUPPR) { + if (IEEE_802154_FC_FRAME_VERSION_GET(frame_control) <= 1) { + /* sequence number suppressed, this is not valid for versions 0/1 */ + return ERR_VAL; + } + } else { + datagram_offset++; + } + datagram_offset += 2; /* Skip destination PAN ID */ + addr_mode = frame_control & IEEE_802154_FC_DST_ADDR_MODE_MASK; + if (addr_mode == IEEE_802154_FC_DST_ADDR_MODE_EXT) { + /* extended address (64 bit) */ + dest->addr_len = 8; + /* reverse memcpy: */ + for (i = 0; i < 8; i++) { + dest->addr[i] = puc[datagram_offset + 7 - i]; + } + datagram_offset += 8; + } else if (addr_mode == IEEE_802154_FC_DST_ADDR_MODE_SHORT) { + /* short address (16 bit) */ + dest->addr_len = 2; + /* reverse memcpy: */ + dest->addr[0] = puc[datagram_offset + 1]; + dest->addr[1] = puc[datagram_offset]; + datagram_offset += 2; + } else { + /* unsupported address mode (do we need "no address"?) */ + return ERR_VAL; + } + + if (!(frame_control & IEEE_802154_FC_PANID_COMPR)) { + /* No PAN ID compression, skip source PAN ID */ + datagram_offset += 2; + } + + addr_mode = frame_control & IEEE_802154_FC_SRC_ADDR_MODE_MASK; + if (addr_mode == IEEE_802154_FC_SRC_ADDR_MODE_EXT) { + /* extended address (64 bit) */ + src->addr_len = 8; + /* reverse memcpy: */ + for (i = 0; i < 8; i++) { + src->addr[i] = puc[datagram_offset + 7 - i]; + } + datagram_offset += 8; + } else if (addr_mode == IEEE_802154_FC_DST_ADDR_MODE_SHORT) { + /* short address (16 bit) */ + src->addr_len = 2; + src->addr[0] = puc[datagram_offset + 1]; + src->addr[1] = puc[datagram_offset]; + datagram_offset += 2; + } else { + /* unsupported address mode (do we need "no address"?) */ + return ERR_VAL; + } + + /* hide IEEE802.15.4 header. */ + if (pbuf_remove_header(p, datagram_offset)) { + return ERR_VAL; + } + return ERR_OK; +} + +/** Calculate the 16-bit CRC as required by IEEE 802.15.4 */ +u16_t +lowpan6_calc_crc(const void* buf, u16_t len) +{ +#define CCITT_POLY_16 0x8408U + u16_t i; + u8_t b; + u16_t crc = 0; + const u8_t* p = (const u8_t*)buf; + + for (i = 0; i < len; i++) { + u8_t data = *p; + for (b = 0U; b < 8U; b++) { + if (((data ^ crc) & 1) != 0) { + crc = (u16_t)((crc >> 1) ^ CCITT_POLY_16); + } else { + crc = (u16_t)(crc >> 1); + } + data = (u8_t)(data >> 1); + } + p++; + } + return crc; +} + +/* Fragmentation specific functions: */ + +static void +free_reass_datagram(struct lowpan6_reass_helper *lrh) +{ + if (lrh->reass) { + pbuf_free(lrh->reass); + } + if (lrh->frags) { + pbuf_free(lrh->frags); + } + mem_free(lrh); +} + +/** + * Removes a datagram from the reassembly queue. + **/ +static void +dequeue_datagram(struct lowpan6_reass_helper *lrh, struct lowpan6_reass_helper *prev) +{ + if (lowpan6_data.reass_list == lrh) { + lowpan6_data.reass_list = lowpan6_data.reass_list->next_packet; + } else { + /* it wasn't the first, so it must have a valid 'prev' */ + LWIP_ASSERT("sanity check linked list", prev != NULL); + prev->next_packet = lrh->next_packet; + } +} + +/** + * Periodic timer for 6LowPAN functions: + * + * - Remove incomplete/old packets + */ +void +lowpan6_tmr(void) +{ + struct lowpan6_reass_helper *lrh, *lrh_next, *lrh_prev = NULL; + + lrh = lowpan6_data.reass_list; + while (lrh != NULL) { + lrh_next = lrh->next_packet; + if ((--lrh->timer) == 0) { + dequeue_datagram(lrh, lrh_prev); + free_reass_datagram(lrh); + } else { + lrh_prev = lrh; + } + lrh = lrh_next; + } +} + +/* + * Encapsulates data into IEEE 802.15.4 frames. + * Fragments an IPv6 datagram into 6LowPAN units, which fit into IEEE 802.15.4 frames. + * If configured, will compress IPv6 and or UDP headers. + * */ +static err_t +lowpan6_frag(struct netif *netif, struct pbuf *p, const struct lowpan6_link_addr *src, const struct lowpan6_link_addr *dst) +{ + struct pbuf *p_frag; + u16_t frag_len, remaining_len, max_data_len; + u8_t *buffer; + u8_t ieee_header_len; + u8_t lowpan6_header_len; + u8_t hidden_header_len; + u16_t crc; + u16_t datagram_offset; + err_t err = ERR_IF; + + LWIP_ASSERT("lowpan6_frag: netif->linkoutput not set", netif->linkoutput != NULL); + + /* We'll use a dedicated pbuf for building 6LowPAN fragments. */ + p_frag = pbuf_alloc(PBUF_RAW, 127, PBUF_RAM); + if (p_frag == NULL) { + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + return ERR_MEM; + } + LWIP_ASSERT("this needs a pbuf in one piece", p_frag->len == p_frag->tot_len); + + /* Write IEEE 802.15.4 header. */ + buffer = (u8_t *)p_frag->payload; + ieee_header_len = lowpan6_write_iee802154_header((struct ieee_802154_hdr *)buffer, src, dst); + LWIP_ASSERT("ieee_header_len < p_frag->len", ieee_header_len < p_frag->len); + +#if LWIP_6LOWPAN_IPHC + /* Perform 6LowPAN IPv6 header compression according to RFC 6282 */ + /* do the header compression (this does NOT copy any non-compressed data) */ + err = lowpan6_compress_headers(netif, (u8_t *)p->payload, p->len, + &buffer[ieee_header_len], p_frag->len - ieee_header_len, &lowpan6_header_len, + &hidden_header_len, LWIP_6LOWPAN_CONTEXTS(netif), src, dst); + if (err != ERR_OK) { + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + pbuf_free(p_frag); + return err; + } + pbuf_remove_header(p, hidden_header_len); + +#else /* LWIP_6LOWPAN_IPHC */ + /* Send uncompressed IPv6 header with appropriate dispatch byte. */ + lowpan6_header_len = 1; + buffer[ieee_header_len] = 0x41; /* IPv6 dispatch */ +#endif /* LWIP_6LOWPAN_IPHC */ + + /* Calculate remaining packet length */ + remaining_len = p->tot_len; + + if (remaining_len > 0x7FF) { + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + /* datagram_size must fit into 11 bit */ + pbuf_free(p_frag); + return ERR_VAL; + } + + /* Fragment, or 1 packet? */ + max_data_len = LOWPAN6_MAX_PAYLOAD - ieee_header_len - lowpan6_header_len; + if (remaining_len > max_data_len) { + u16_t data_len; + /* We must move the 6LowPAN header to make room for the FRAG header. */ + memmove(&buffer[ieee_header_len + 4], &buffer[ieee_header_len], lowpan6_header_len); + + /* Now we need to fragment the packet. FRAG1 header first */ + buffer[ieee_header_len] = 0xc0 | (((p->tot_len + hidden_header_len) >> 8) & 0x7); + buffer[ieee_header_len + 1] = (p->tot_len + hidden_header_len) & 0xff; + + lowpan6_data.tx_datagram_tag++; + buffer[ieee_header_len + 2] = (lowpan6_data.tx_datagram_tag >> 8) & 0xff; + buffer[ieee_header_len + 3] = lowpan6_data.tx_datagram_tag & 0xff; + + /* Fragment follows. */ + data_len = (max_data_len - 4) & 0xf8; + frag_len = data_len + lowpan6_header_len; + + pbuf_copy_partial(p, buffer + ieee_header_len + lowpan6_header_len + 4, frag_len - lowpan6_header_len, 0); + remaining_len -= frag_len - lowpan6_header_len; + /* datagram offset holds the offset before compression */ + datagram_offset = frag_len - lowpan6_header_len + hidden_header_len; + LWIP_ASSERT("datagram offset must be a multiple of 8", (datagram_offset & 7) == 0); + + /* Calculate frame length */ + p_frag->len = p_frag->tot_len = ieee_header_len + 4 + frag_len + 2; /* add 2 bytes for crc*/ + + /* 2 bytes CRC */ + crc = LWIP_6LOWPAN_DO_CALC_CRC(p_frag->payload, p_frag->len - 2); + pbuf_take_at(p_frag, &crc, 2, p_frag->len - 2); + + /* send the packet */ + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len); + LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p)); + err = netif->linkoutput(netif, p_frag); + + while ((remaining_len > 0) && (err == ERR_OK)) { + struct ieee_802154_hdr *hdr = (struct ieee_802154_hdr *)buffer; + /* new frame, new seq num for ACK */ + hdr->sequence_number = lowpan6_data.tx_frame_seq_num++; + + buffer[ieee_header_len] |= 0x20; /* Change FRAG1 to FRAGN */ + + LWIP_ASSERT("datagram offset must be a multiple of 8", (datagram_offset & 7) == 0); + buffer[ieee_header_len + 4] = (u8_t)(datagram_offset >> 3); /* datagram offset in FRAGN header (datagram_offset is max. 11 bit) */ + + frag_len = (127 - ieee_header_len - 5 - 2) & 0xf8; + if (frag_len > remaining_len) { + frag_len = remaining_len; + } + + pbuf_copy_partial(p, buffer + ieee_header_len + 5, frag_len, p->tot_len - remaining_len); + remaining_len -= frag_len; + datagram_offset += frag_len; + + /* Calculate frame length */ + p_frag->len = p_frag->tot_len = frag_len + 5 + ieee_header_len + 2; + + /* 2 bytes CRC */ + crc = LWIP_6LOWPAN_DO_CALC_CRC(p_frag->payload, p_frag->len - 2); + pbuf_take_at(p_frag, &crc, 2, p_frag->len - 2); + + /* send the packet */ + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len); + LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p)); + err = netif->linkoutput(netif, p_frag); + } + } else { + /* It fits in one frame. */ + frag_len = remaining_len; + + /* Copy IPv6 packet */ + pbuf_copy_partial(p, buffer + ieee_header_len + lowpan6_header_len, frag_len, 0); + remaining_len = 0; + + /* Calculate frame length */ + p_frag->len = p_frag->tot_len = frag_len + lowpan6_header_len + ieee_header_len + 2; + LWIP_ASSERT("", p_frag->len <= 127); + + /* 2 bytes CRC */ + crc = LWIP_6LOWPAN_DO_CALC_CRC(p_frag->payload, p_frag->len - 2); + pbuf_take_at(p_frag, &crc, 2, p_frag->len - 2); + + /* send the packet */ + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len); + LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG | LWIP_DBG_TRACE, ("lowpan6_send: sending packet %p\n", (void *)p)); + err = netif->linkoutput(netif, p_frag); + } + + pbuf_free(p_frag); + + return err; +} + +/** + * @ingroup sixlowpan + * Set context + */ +err_t +lowpan6_set_context(u8_t idx, const ip6_addr_t *context) +{ +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 + if (idx >= LWIP_6LOWPAN_NUM_CONTEXTS) { + return ERR_ARG; + } + + IP6_ADDR_ZONECHECK(context); + + ip6_addr_set(&lowpan6_data.lowpan6_context[idx], context); + + return ERR_OK; +#else + LWIP_UNUSED_ARG(idx); + LWIP_UNUSED_ARG(context); + return ERR_ARG; +#endif +} + +#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS +/** + * @ingroup sixlowpan + * Set short address + */ +err_t +lowpan6_set_short_addr(u8_t addr_high, u8_t addr_low) +{ + short_mac_addr.addr[0] = addr_high; + short_mac_addr.addr[1] = addr_low; + + return ERR_OK; +} +#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ + +/* Create IEEE 802.15.4 address from netif address */ +static err_t +lowpan6_hwaddr_to_addr(struct netif *netif, struct lowpan6_link_addr *addr) +{ + addr->addr_len = 8; + if (netif->hwaddr_len == 8) { + LWIP_ERROR("NETIF_MAX_HWADDR_LEN >= 8 required", sizeof(netif->hwaddr) >= 8, return ERR_VAL;); + SMEMCPY(addr->addr, netif->hwaddr, 8); + } else if (netif->hwaddr_len == 6) { + /* Copy from MAC-48 */ + SMEMCPY(addr->addr, netif->hwaddr, 3); + addr->addr[3] = addr->addr[4] = 0xff; + SMEMCPY(&addr->addr[5], &netif->hwaddr[3], 3); + } else { + /* Invalid address length, don't know how to convert this */ + return ERR_VAL; + } + return ERR_OK; +} + +/** + * @ingroup sixlowpan + * Resolve and fill-in IEEE 802.15.4 address header for outgoing IPv6 packet. + * + * Perform Header Compression and fragment if necessary. + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param q The pbuf(s) containing the IP packet to be sent. + * @param ip6addr The IP address of the packet destination. + * + * @return err_t + */ +err_t +lowpan6_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr) +{ + err_t result; + const u8_t *hwaddr; + struct lowpan6_link_addr src, dest; +#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS + ip6_addr_t ip6_src; + struct ip6_hdr *ip6_hdr; +#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ + +#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS + /* Check if we can compress source address (use aligned copy) */ + ip6_hdr = (struct ip6_hdr *)q->payload; + ip6_addr_copy_from_packed(ip6_src, ip6_hdr->src); + ip6_addr_assign_zone(&ip6_src, IP6_UNICAST, netif); + if (lowpan6_get_address_mode(&ip6_src, &short_mac_addr) == 3) { + src.addr_len = 2; + src.addr[0] = short_mac_addr.addr[0]; + src.addr[1] = short_mac_addr.addr[1]; + } else +#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ + { + result = lowpan6_hwaddr_to_addr(netif, &src); + if (result != ERR_OK) { + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + return result; + } + } + + /* multicast destination IP address? */ + if (ip6_addr_ismulticast(ip6addr)) { + MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); + /* We need to send to the broadcast address.*/ + return lowpan6_frag(netif, q, &src, &ieee_802154_broadcast); + } + + /* We have a unicast destination IP address */ + /* @todo anycast? */ + +#if LWIP_6LOWPAN_INFER_SHORT_ADDRESS + if (src.addr_len == 2) { + /* If source address was compressable to short_mac_addr, and dest has same subnet and + * is also compressable to 2-bytes, assume we can infer dest as a short address too. */ + dest.addr_len = 2; + dest.addr[0] = ((u8_t *)q->payload)[38]; + dest.addr[1] = ((u8_t *)q->payload)[39]; + if ((src.addr_len == 2) && (ip6_addr_netcmp_zoneless(&ip6_hdr->src, &ip6_hdr->dest)) && + (lowpan6_get_address_mode(ip6addr, &dest) == 3)) { + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + return lowpan6_frag(netif, q, &src, &dest); + } + } +#endif /* LWIP_6LOWPAN_INFER_SHORT_ADDRESS */ + + /* Ask ND6 what to do with the packet. */ + result = nd6_get_next_hop_addr_or_queue(netif, q, ip6addr, &hwaddr); + if (result != ERR_OK) { + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + return result; + } + + /* If no hardware address is returned, nd6 has queued the packet for later. */ + if (hwaddr == NULL) { + return ERR_OK; + } + + /* Send out the packet using the returned hardware address. */ + dest.addr_len = netif->hwaddr_len; + /* XXX: Inferring the length of the source address from the destination address + * is not correct for IEEE 802.15.4, but currently we don't get this information + * from the neighbor cache */ + SMEMCPY(dest.addr, hwaddr, netif->hwaddr_len); + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + return lowpan6_frag(netif, q, &src, &dest); +} +/** + * @ingroup sixlowpan + * NETIF input function: don't free the input pbuf when returning != ERR_OK! + */ +err_t +lowpan6_input(struct pbuf *p, struct netif *netif) +{ + u8_t *puc, b; + s8_t i; + struct lowpan6_link_addr src, dest; + u16_t datagram_size = 0; + u16_t datagram_offset, datagram_tag; + struct lowpan6_reass_helper *lrh, *lrh_next, *lrh_prev = NULL; + + if (p == NULL) { + return ERR_OK; + } + + MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); + + if (p->len != p->tot_len) { + /* for now, this needs a pbuf in one piece */ + goto lowpan6_input_discard; + } + + if (lowpan6_parse_iee802154_header(p, &src, &dest) != ERR_OK) { + goto lowpan6_input_discard; + } + + /* Check dispatch. */ + puc = (u8_t *)p->payload; + + b = *puc; + if ((b & 0xf8) == 0xc0) { + /* FRAG1 dispatch. add this packet to reassembly list. */ + datagram_size = ((u16_t)(puc[0] & 0x07) << 8) | (u16_t)puc[1]; + datagram_tag = ((u16_t)puc[2] << 8) | (u16_t)puc[3]; + + /* check for duplicate */ + lrh = lowpan6_data.reass_list; + while (lrh != NULL) { + uint8_t discard = 0; + lrh_next = lrh->next_packet; + if ((lrh->sender_addr.addr_len == src.addr_len) && + (memcmp(lrh->sender_addr.addr, src.addr, src.addr_len) == 0)) { + /* address match with packet in reassembly. */ + if ((datagram_tag == lrh->datagram_tag) && (datagram_size == lrh->datagram_size)) { + /* duplicate fragment. */ + goto lowpan6_input_discard; + } else { + /* We are receiving the start of a new datagram. Discard old one (incomplete). */ + discard = 1; + } + } + if (discard) { + dequeue_datagram(lrh, lrh_prev); + free_reass_datagram(lrh); + } else { + lrh_prev = lrh; + } + /* Check next datagram in queue. */ + lrh = lrh_next; + } + + pbuf_remove_header(p, 4); /* hide frag1 dispatch */ + + lrh = (struct lowpan6_reass_helper *) mem_malloc(sizeof(struct lowpan6_reass_helper)); + if (lrh == NULL) { + goto lowpan6_input_discard; + } + + lrh->sender_addr.addr_len = src.addr_len; + for (i = 0; i < src.addr_len; i++) { + lrh->sender_addr.addr[i] = src.addr[i]; + } + lrh->datagram_size = datagram_size; + lrh->datagram_tag = datagram_tag; + lrh->frags = NULL; + if (*(u8_t *)p->payload == 0x41) { + /* This is a complete IPv6 packet, just skip dispatch byte. */ + pbuf_remove_header(p, 1); /* hide dispatch byte. */ + lrh->reass = p; + } else if ((*(u8_t *)p->payload & 0xe0 ) == 0x60) { + lrh->reass = lowpan6_decompress(p, datagram_size, LWIP_6LOWPAN_CONTEXTS(netif), &src, &dest); + if (lrh->reass == NULL) { + /* decompression failed */ + mem_free(lrh); + goto lowpan6_input_discard; + } + } + /* TODO: handle the case where we already have FRAGN received */ + lrh->next_packet = lowpan6_data.reass_list; + lrh->timer = 2; + lowpan6_data.reass_list = lrh; + + return ERR_OK; + } else if ((b & 0xf8) == 0xe0) { + /* FRAGN dispatch, find packet being reassembled. */ + datagram_size = ((u16_t)(puc[0] & 0x07) << 8) | (u16_t)puc[1]; + datagram_tag = ((u16_t)puc[2] << 8) | (u16_t)puc[3]; + datagram_offset = (u16_t)puc[4] << 3; + pbuf_remove_header(p, 4); /* hide frag1 dispatch but keep datagram offset for reassembly */ + + for (lrh = lowpan6_data.reass_list; lrh != NULL; lrh_prev = lrh, lrh = lrh->next_packet) { + if ((lrh->sender_addr.addr_len == src.addr_len) && + (memcmp(lrh->sender_addr.addr, src.addr, src.addr_len) == 0) && + (datagram_tag == lrh->datagram_tag) && + (datagram_size == lrh->datagram_size)) { + break; + } + } + if (lrh == NULL) { + /* rogue fragment */ + goto lowpan6_input_discard; + } + /* Insert new pbuf into list of fragments. Each fragment is a pbuf, + this only works for unchained pbufs. */ + LWIP_ASSERT("p->next == NULL", p->next == NULL); + if (lrh->reass != NULL) { + /* FRAG1 already received, check this offset against first len */ + if (datagram_offset < lrh->reass->len) { + /* fragment overlap, discard old fragments */ + dequeue_datagram(lrh, lrh_prev); + free_reass_datagram(lrh); + goto lowpan6_input_discard; + } + } + if (lrh->frags == NULL) { + /* first FRAGN */ + lrh->frags = p; + } else { + /* find the correct place to insert */ + struct pbuf *q, *last; + u16_t new_frag_len = p->len - 1; /* p->len includes datagram_offset byte */ + for (q = lrh->frags, last = NULL; q != NULL; last = q, q = q->next) { + u16_t q_datagram_offset = ((u8_t *)q->payload)[0] << 3; + u16_t q_frag_len = q->len - 1; + if (datagram_offset < q_datagram_offset) { + if (datagram_offset + new_frag_len > q_datagram_offset) { + /* overlap, discard old fragments */ + dequeue_datagram(lrh, lrh_prev); + free_reass_datagram(lrh); + goto lowpan6_input_discard; + } + /* insert here */ + break; + } else if (datagram_offset == q_datagram_offset) { + if (q_frag_len != new_frag_len) { + /* fragment mismatch, discard old fragments */ + dequeue_datagram(lrh, lrh_prev); + free_reass_datagram(lrh); + goto lowpan6_input_discard; + } + /* duplicate, ignore */ + pbuf_free(p); + return ERR_OK; + } + } + /* insert fragment */ + if (last == NULL) { + lrh->frags = p; + } else { + last->next = p; + p->next = q; + } + } + /* check if all fragments were received */ + if (lrh->reass) { + u16_t offset = lrh->reass->len; + struct pbuf *q; + for (q = lrh->frags; q != NULL; q = q->next) { + u16_t q_datagram_offset = ((u8_t *)q->payload)[0] << 3; + if (q_datagram_offset != offset) { + /* not complete, wait for more fragments */ + return ERR_OK; + } + offset += q->len - 1; + } + if (offset == datagram_size) { + /* all fragments received, combine pbufs */ + u16_t datagram_left = datagram_size - lrh->reass->len; + for (q = lrh->frags; q != NULL; q = q->next) { + /* hide datagram_offset byte now */ + pbuf_remove_header(q, 1); + q->tot_len = datagram_left; + datagram_left -= q->len; + } + LWIP_ASSERT("datagram_left == 0", datagram_left == 0); + q = lrh->reass; + q->tot_len = datagram_size; + q->next = lrh->frags; + lrh->frags = NULL; + lrh->reass = NULL; + dequeue_datagram(lrh, lrh_prev); + mem_free(lrh); + + /* @todo: distinguish unicast/multicast */ + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + return ip6_input(q, netif); + } + } + /* pbuf enqueued, waiting for more fragments */ + return ERR_OK; + } else { + if (b == 0x41) { + /* This is a complete IPv6 packet, just skip dispatch byte. */ + pbuf_remove_header(p, 1); /* hide dispatch byte. */ + } else if ((b & 0xe0 ) == 0x60) { + /* IPv6 headers are compressed using IPHC. */ + p = lowpan6_decompress(p, datagram_size, LWIP_6LOWPAN_CONTEXTS(netif), &src, &dest); + if (p == NULL) { + MIB2_STATS_NETIF_INC(netif, ifindiscards); + return ERR_OK; + } + } else { + goto lowpan6_input_discard; + } + + /* @todo: distinguish unicast/multicast */ + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + + return ip6_input(p, netif); + } +lowpan6_input_discard: + MIB2_STATS_NETIF_INC(netif, ifindiscards); + pbuf_free(p); + /* always return ERR_OK here to prevent the caller freeing the pbuf */ + return ERR_OK; +} + +/** + * @ingroup sixlowpan + */ +err_t +lowpan6_if_init(struct netif *netif) +{ + netif->name[0] = 'L'; + netif->name[1] = '6'; + netif->output_ip6 = lowpan6_output; + + MIB2_INIT_NETIF(netif, snmp_ifType_other, 0); + + /* maximum transfer unit */ + netif->mtu = 1280; + + /* broadcast capability */ + netif->flags = NETIF_FLAG_BROADCAST /* | NETIF_FLAG_LOWPAN6 */; + + return ERR_OK; +} + +/** + * @ingroup sixlowpan + * Set PAN ID + */ +err_t +lowpan6_set_pan_id(u16_t pan_id) +{ + lowpan6_data.ieee_802154_pan_id = pan_id; + + return ERR_OK; +} + +#if !NO_SYS +/** + * @ingroup sixlowpan + * Pass a received packet to tcpip_thread for input processing + * + * @param p the received packet, p->payload pointing to the + * IEEE 802.15.4 header. + * @param inp the network interface on which the packet was received + */ +err_t +tcpip_6lowpan_input(struct pbuf *p, struct netif *inp) +{ + return tcpip_inpkt(p, inp, lowpan6_input); +} +#endif /* !NO_SYS */ + +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c b/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c new file mode 100644 index 0000000..d89816d --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/lowpan6_ble.c @@ -0,0 +1,447 @@ +/** + * @file + * 6LowPAN over BLE output for IPv6 (RFC7668). +*/ + +/* + * Copyright (c) 2017 Benjamin Aigner + * Copyright (c) 2015 Inico Technologies Ltd. , Author: Ivan Delamer + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * Author: Benjamin Aigner + * + * Based on the original 6lowpan implementation of lwIP ( @see 6lowpan.c) + */ + + +/** + * @defgroup rfc7668if 6LoWPAN over BLE (RFC7668) + * @ingroup netifs + * This file implements a RFC7668 implementation for 6LoWPAN over + * Bluetooth Low Energy. The specification is very similar to 6LoWPAN, + * so most of the code is re-used. + * Compared to 6LoWPAN, much functionality is already implemented in + * lower BLE layers (fragmenting, session management,...). + * + * Usage: + * - add this netif + * - don't add IPv4 addresses (no IPv4 support in RFC7668), pass 'NULL','NULL','NULL' + * - use the BLE to EUI64 conversation util to create an IPv6 link-local address from the BLE MAC (@ref ble_addr_to_eui64) + * - input function: @ref rfc7668_input + * - set the link output function, which transmits output data to an established L2CAP channel + * - If data arrives (HCI event "L2CAP_DATA_PACKET"): + * - allocate a @ref PBUF_RAW buffer + * - let the pbuf struct point to the incoming data or copy it to the buffer + * - call netif->input + * + * @todo: + * - further testing + * - support compression contexts + * - support multiple addresses + * - support multicast + * - support neighbor discovery + */ + + +#include "netif/lowpan6_ble.h" + +#if LWIP_IPV6 + +#include "lwip/ip.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/nd6.h" +#include "lwip/mem.h" +#include "lwip/udp.h" +#include "lwip/tcpip.h" +#include "lwip/snmp.h" + +#include + +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 +/** context memory, containing IPv6 addresses */ +static ip6_addr_t rfc7668_context[LWIP_6LOWPAN_NUM_CONTEXTS]; +#else +#define rfc7668_context NULL +#endif + +static struct lowpan6_link_addr rfc7668_local_addr; +static struct lowpan6_link_addr rfc7668_peer_addr; + +/** + * @ingroup rfc7668if + * convert BT address to EUI64 addr + * + * This method converts a Bluetooth MAC address to an EUI64 address, + * which is used within IPv6 communication + * + * @param dst IPv6 destination space + * @param src BLE MAC address source + * @param public_addr If the LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS + * option is set, bit 0x02 will be set if param=0 (no public addr); cleared otherwise + * + * @see LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS + */ +void +ble_addr_to_eui64(uint8_t *dst, const uint8_t *src, int public_addr) +{ + /* according to RFC7668 ch 3.2.2. */ + memcpy(dst, src, 3); + dst[3] = 0xFF; + dst[4] = 0xFE; + memcpy(&dst[5], &src[3], 3); +#if LWIP_RFC7668_LINUX_WORKAROUND_PUBLIC_ADDRESS + if(public_addr) { + dst[0] &= ~0x02; + } else { + dst[0] |= 0x02; + } +#else + LWIP_UNUSED_ARG(public_addr); +#endif +} + +/** + * @ingroup rfc7668if + * convert EUI64 address to Bluetooth MAC addr + * + * This method converts an EUI64 address to a Bluetooth MAC address, + * + * @param dst BLE MAC address destination + * @param src IPv6 source + * + */ +void +eui64_to_ble_addr(uint8_t *dst, const uint8_t *src) +{ + /* according to RFC7668 ch 3.2.2. */ + memcpy(dst,src,3); + memcpy(&dst[3],&src[5],3); +} + +/** Set an address used for stateful compression. + * This expects an address of 6 or 8 bytes. + */ +static err_t +rfc7668_set_addr(struct lowpan6_link_addr *addr, const u8_t *in_addr, size_t in_addr_len, int is_mac_48, int is_public_addr) +{ + if ((in_addr == NULL) || (addr == NULL)) { + return ERR_VAL; + } + if (is_mac_48) { + if (in_addr_len != 6) { + return ERR_VAL; + } + addr->addr_len = 8; + ble_addr_to_eui64(addr->addr, in_addr, is_public_addr); + } else { + if (in_addr_len != 8) { + return ERR_VAL; + } + addr->addr_len = 8; + memcpy(addr->addr, in_addr, 8); + } + return ERR_OK; +} + + +/** Set the local address used for stateful compression. + * This expects an address of 8 bytes. + */ +err_t +rfc7668_set_local_addr_eui64(struct netif *netif, const u8_t *local_addr, size_t local_addr_len) +{ + /* netif not used for now, the address is stored globally... */ + LWIP_UNUSED_ARG(netif); + return rfc7668_set_addr(&rfc7668_local_addr, local_addr, local_addr_len, 0, 0); +} + +/** Set the local address used for stateful compression. + * This expects an address of 6 bytes. + */ +err_t +rfc7668_set_local_addr_mac48(struct netif *netif, const u8_t *local_addr, size_t local_addr_len, int is_public_addr) +{ + /* netif not used for now, the address is stored globally... */ + LWIP_UNUSED_ARG(netif); + return rfc7668_set_addr(&rfc7668_local_addr, local_addr, local_addr_len, 1, is_public_addr); +} + +/** Set the peer address used for stateful compression. + * This expects an address of 8 bytes. + */ +err_t +rfc7668_set_peer_addr_eui64(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len) +{ + /* netif not used for now, the address is stored globally... */ + LWIP_UNUSED_ARG(netif); + return rfc7668_set_addr(&rfc7668_peer_addr, peer_addr, peer_addr_len, 0, 0); +} + +/** Set the peer address used for stateful compression. + * This expects an address of 6 bytes. + */ +err_t +rfc7668_set_peer_addr_mac48(struct netif *netif, const u8_t *peer_addr, size_t peer_addr_len, int is_public_addr) +{ + /* netif not used for now, the address is stored globally... */ + LWIP_UNUSED_ARG(netif); + return rfc7668_set_addr(&rfc7668_peer_addr, peer_addr, peer_addr_len, 1, is_public_addr); +} + +/** Encapsulate IPv6 frames for BLE transmission + * + * This method implements the IPv6 header compression: + * *) According to RFC6282 + * *) See Figure 2, contains base format of bit positions + * *) Fragmentation not necessary (done at L2CAP layer of BLE) + * @note Currently the pbuf allocation uses 256 bytes. If longer packets are used (possible due to MTU=1480Bytes), increase it here! + * + * @param p Pbuf struct, containing the payload data + * @param netif Output network interface. Should be of RFC7668 type + * + * @return Same as netif->output. + */ +static err_t +rfc7668_compress(struct netif *netif, struct pbuf *p) +{ + struct pbuf *p_frag; + u16_t remaining_len; + u8_t *buffer; + u8_t lowpan6_header_len; + u8_t hidden_header_len; + err_t err; + + LWIP_ASSERT("lowpan6_frag: netif->linkoutput not set", netif->linkoutput != NULL); + +#if LWIP_6LOWPAN_IPHC + + /* We'll use a dedicated pbuf for building BLE fragments. + * We'll over-allocate it by the bytes saved for header compression. + */ + p_frag = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if (p_frag == NULL) { + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + return ERR_MEM; + } + LWIP_ASSERT("this needs a pbuf in one piece", p_frag->len == p_frag->tot_len); + + /* Write IP6 header (with IPHC). */ + buffer = (u8_t*)p_frag->payload; + + err = lowpan6_compress_headers(netif, (u8_t *)p->payload, p->len, buffer, p_frag->len, + &lowpan6_header_len, &hidden_header_len, rfc7668_context, &rfc7668_local_addr, &rfc7668_peer_addr); + if (err != ERR_OK) { + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + pbuf_free(p_frag); + return err; + } + pbuf_remove_header(p, hidden_header_len); + + /* Calculate remaining packet length */ + remaining_len = p->tot_len; + + /* Copy IPv6 packet */ + pbuf_copy_partial(p, buffer + lowpan6_header_len, remaining_len, 0); + + /* Calculate frame length */ + p_frag->len = p_frag->tot_len = remaining_len + lowpan6_header_len; + + /* send the packet */ + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p_frag->tot_len); + LWIP_DEBUGF(LWIP_LOWPAN6_DEBUG|LWIP_DBG_TRACE, ("rfc7668_output: sending packet %p\n", (void *)p)); + err = netif->linkoutput(netif, p_frag); + + pbuf_free(p_frag); + + return err; +#else /* LWIP_6LOWPAN_IPHC */ + /* 6LoWPAN over BLE requires IPHC! */ + return ERR_IF; +#endif/* LWIP_6LOWPAN_IPHC */ +} + +/** + * @ingroup rfc7668if + * Set context id IPv6 address + * + * Store one IPv6 address to a given context id. + * + * @param idx Context id + * @param context IPv6 addr for this context + * + * @return ERR_OK (if everything is fine), ERR_ARG (if the context id is out of range), ERR_VAL (if contexts disabled) + */ +err_t +rfc7668_set_context(u8_t idx, const ip6_addr_t *context) +{ +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 + /* check if the ID is possible */ + if (idx >= LWIP_6LOWPAN_NUM_CONTEXTS) { + return ERR_ARG; + } + /* copy IPv6 address to context storage */ + ip6_addr_set(&rfc7668_context[idx], context); + return ERR_OK; +#else + LWIP_UNUSED_ARG(idx); + LWIP_UNUSED_ARG(context); + return ERR_VAL; +#endif +} + +/** + * @ingroup rfc7668if + * Compress outgoing IPv6 packet and pass it on to netif->linkoutput + * + * @param netif The lwIP network interface which the IP packet will be sent on. + * @param q The pbuf(s) containing the IP packet to be sent. + * @param ip6addr The IP address of the packet destination. + * + * @return See rfc7668_compress + */ +err_t +rfc7668_output(struct netif *netif, struct pbuf *q, const ip6_addr_t *ip6addr) +{ + /* dst ip6addr is not used here, we only have one peer */ + LWIP_UNUSED_ARG(ip6addr); + + return rfc7668_compress(netif, q); +} + +/** + * @ingroup rfc7668if + * Process a received raw payload from an L2CAP channel + * + * @param p the received packet, p->payload pointing to the + * IPv6 header (maybe compressed) + * @param netif the network interface on which the packet was received + * + * @return ERR_OK if everything was fine + */ +err_t +rfc7668_input(struct pbuf * p, struct netif *netif) +{ + u8_t * puc; + + MIB2_STATS_NETIF_ADD(netif, ifinoctets, p->tot_len); + + /* Load first header byte */ + puc = (u8_t*)p->payload; + + /* no IP header compression */ + if (*puc == 0x41) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Completed packet, removing dispatch: 0x%2x \n", *puc)); + /* This is a complete IPv6 packet, just skip header byte. */ + pbuf_remove_header(p, 1); + /* IPHC header compression */ + } else if ((*puc & 0xe0 )== 0x60) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Completed packet, decompress dispatch: 0x%2x \n", *puc)); + /* IPv6 headers are compressed using IPHC. */ + p = lowpan6_decompress(p, 0, rfc7668_context, &rfc7668_peer_addr, &rfc7668_local_addr); + /* if no pbuf is returned, handle as discarded packet */ + if (p == NULL) { + MIB2_STATS_NETIF_INC(netif, ifindiscards); + return ERR_OK; + } + /* invalid header byte, discard */ + } else { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Completed packet, discarding: 0x%2x \n", *puc)); + MIB2_STATS_NETIF_INC(netif, ifindiscards); + pbuf_free(p); + return ERR_OK; + } + /* @todo: distinguish unicast/multicast */ + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + +#if LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG + { + u16_t i; + LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("IPv6 payload:\n")); + for (i = 0; i < p->len; i++) { + if ((i%4)==0) { + LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("\n")); + } + LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("%2X ", *((uint8_t *)p->payload+i))); + } + LWIP_DEBUGF(LWIP_RFC7668_IP_UNCOMPRESSED_DEBUG, ("\np->len: %d\n", p->len)); + } +#endif + /* pass data to ip6_input */ + return ip6_input(p, netif); +} + +/** + * @ingroup rfc7668if + * Initialize the netif + * + * No flags are used (broadcast not possible, not ethernet, ...) + * The shortname for this netif is "BT" + * + * @param netif the network interface to be initialized as RFC7668 netif + * + * @return ERR_OK if everything went fine + */ +err_t +rfc7668_if_init(struct netif *netif) +{ + netif->name[0] = 'b'; + netif->name[1] = 't'; + /* local function as IPv6 output */ + netif->output_ip6 = rfc7668_output; + + MIB2_INIT_NETIF(netif, snmp_ifType_other, 0); + + /* maximum transfer unit, set according to RFC7668 ch2.4 */ + netif->mtu = 1280; + + /* no flags set (no broadcast, ethernet,...)*/ + netif->flags = 0; + + /* everything fine */ + return ERR_OK; +} + +#if !NO_SYS +/** + * Pass a received packet to tcpip_thread for input processing + * + * @param p the received packet, p->payload pointing to the + * IEEE 802.15.4 header. + * @param inp the network interface on which the packet was received + * + * @return see @ref tcpip_inpkt, same return values + */ +err_t +tcpip_rfc7668_input(struct pbuf *p, struct netif *inp) +{ + /* send data to upper layer, return the result */ + return tcpip_inpkt(p, inp, rfc7668_input); +} +#endif /* !NO_SYS */ + +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c b/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c new file mode 100644 index 0000000..baea206 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/lowpan6_common.c @@ -0,0 +1,841 @@ +/** + * @file + * + * Common 6LowPAN routines for IPv6. Uses ND tables for link-layer addressing. Fragments packets to 6LowPAN units. + * + * This implementation aims to conform to IEEE 802.15.4(-2015), RFC 4944 and RFC 6282. + * @todo: RFC 6775. + */ + +/* + * Copyright (c) 2015 Inico Technologies Ltd. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Ivan Delamer + * + * + * Please coordinate changes and requests with Ivan Delamer + * + */ + +/** + * @defgroup sixlowpan 6LoWPAN (RFC4944) + * @ingroup netifs + * 6LowPAN netif implementation + */ + +#include "netif/lowpan6_common.h" + +#if LWIP_IPV6 + +#include "lwip/ip.h" +#include "lwip/pbuf.h" +#include "lwip/ip_addr.h" +#include "lwip/netif.h" +#include "lwip/udp.h" + +#include + +/* Determine compression mode for unicast address. */ +s8_t +lowpan6_get_address_mode(const ip6_addr_t *ip6addr, const struct lowpan6_link_addr *mac_addr) +{ + if (mac_addr->addr_len == 2) { + if ((ip6addr->addr[2] == (u32_t)PP_HTONL(0x000000ff)) && + ((ip6addr->addr[3] & PP_HTONL(0xffff0000)) == PP_NTOHL(0xfe000000))) { + if ((ip6addr->addr[3] & PP_HTONL(0x0000ffff)) == lwip_ntohl((mac_addr->addr[0] << 8) | mac_addr->addr[1])) { + return 3; + } + } + } else if (mac_addr->addr_len == 8) { + if ((ip6addr->addr[2] == lwip_ntohl(((mac_addr->addr[0] ^ 2) << 24) | (mac_addr->addr[1] << 16) | mac_addr->addr[2] << 8 | mac_addr->addr[3])) && + (ip6addr->addr[3] == lwip_ntohl((mac_addr->addr[4] << 24) | (mac_addr->addr[5] << 16) | mac_addr->addr[6] << 8 | mac_addr->addr[7]))) { + return 3; + } + } + + if ((ip6addr->addr[2] == PP_HTONL(0x000000ffUL)) && + ((ip6addr->addr[3] & PP_HTONL(0xffff0000)) == PP_NTOHL(0xfe000000UL))) { + return 2; + } + + return 1; +} + +#if LWIP_6LOWPAN_IPHC + +/* Determine compression mode for multicast address. */ +static s8_t +lowpan6_get_address_mode_mc(const ip6_addr_t *ip6addr) +{ + if ((ip6addr->addr[0] == PP_HTONL(0xff020000)) && + (ip6addr->addr[1] == 0) && + (ip6addr->addr[2] == 0) && + ((ip6addr->addr[3] & PP_HTONL(0xffffff00)) == 0)) { + return 3; + } else if (((ip6addr->addr[0] & PP_HTONL(0xff00ffff)) == PP_HTONL(0xff000000)) && + (ip6addr->addr[1] == 0)) { + if ((ip6addr->addr[2] == 0) && + ((ip6addr->addr[3] & PP_HTONL(0xff000000)) == 0)) { + return 2; + } else if ((ip6addr->addr[2] & PP_HTONL(0xffffff00)) == 0) { + return 1; + } + } + + return 0; +} + +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 +static s8_t +lowpan6_context_lookup(const ip6_addr_t *lowpan6_contexts, const ip6_addr_t *ip6addr) +{ + s8_t i; + + for (i = 0; i < LWIP_6LOWPAN_NUM_CONTEXTS; i++) { + if (ip6_addr_netcmp(&lowpan6_contexts[i], ip6addr)) { + return i; + } + } + return -1; +} +#endif /* LWIP_6LOWPAN_NUM_CONTEXTS > 0 */ + +/* + * Compress IPv6 and/or UDP headers. + * */ +err_t +lowpan6_compress_headers(struct netif *netif, u8_t *inbuf, size_t inbuf_size, u8_t *outbuf, size_t outbuf_size, + u8_t *lowpan6_header_len_out, u8_t *hidden_header_len_out, ip6_addr_t *lowpan6_contexts, + const struct lowpan6_link_addr *src, const struct lowpan6_link_addr *dst) +{ + u8_t *buffer, *inptr; + u8_t lowpan6_header_len; + u8_t hidden_header_len = 0; + s8_t i; + struct ip6_hdr *ip6hdr; + ip_addr_t ip6src, ip6dst; + + LWIP_ASSERT("netif != NULL", netif != NULL); + LWIP_ASSERT("inbuf != NULL", inbuf != NULL); + LWIP_ASSERT("outbuf != NULL", outbuf != NULL); + LWIP_ASSERT("lowpan6_header_len_out != NULL", lowpan6_header_len_out != NULL); + LWIP_ASSERT("hidden_header_len_out != NULL", hidden_header_len_out != NULL); + + /* Perform 6LowPAN IPv6 header compression according to RFC 6282 */ + buffer = outbuf; + inptr = inbuf; + + if (inbuf_size < IP6_HLEN) { + /* input buffer too short */ + return ERR_VAL; + } + if (outbuf_size < IP6_HLEN) { + /* output buffer too short for worst case */ + return ERR_MEM; + } + + /* Point to ip6 header and align copies of src/dest addresses. */ + ip6hdr = (struct ip6_hdr *)inptr; + ip_addr_copy_from_ip6_packed(ip6dst, ip6hdr->dest); + ip6_addr_assign_zone(ip_2_ip6(&ip6dst), IP6_UNKNOWN, netif); + ip_addr_copy_from_ip6_packed(ip6src, ip6hdr->src); + ip6_addr_assign_zone(ip_2_ip6(&ip6src), IP6_UNKNOWN, netif); + + /* Basic length of 6LowPAN header, set dispatch and clear fields. */ + lowpan6_header_len = 2; + buffer[0] = 0x60; + buffer[1] = 0; + + /* Determine whether there will be a Context Identifier Extension byte or not. + * If so, set it already. */ +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 + buffer[2] = 0; + + i = lowpan6_context_lookup(lowpan6_contexts, ip_2_ip6(&ip6src)); + if (i >= 0) { + /* Stateful source address compression. */ + buffer[1] |= 0x40; + buffer[2] |= (i & 0x0f) << 4; + } + + i = lowpan6_context_lookup(lowpan6_contexts, ip_2_ip6(&ip6dst)); + if (i >= 0) { + /* Stateful destination address compression. */ + buffer[1] |= 0x04; + buffer[2] |= i & 0x0f; + } + + if (buffer[2] != 0x00) { + /* Context identifier extension byte is appended. */ + buffer[1] |= 0x80; + lowpan6_header_len++; + } +#else /* LWIP_6LOWPAN_NUM_CONTEXTS > 0 */ + LWIP_UNUSED_ARG(lowpan6_contexts); +#endif /* LWIP_6LOWPAN_NUM_CONTEXTS > 0 */ + + /* Determine TF field: Traffic Class, Flow Label */ + if (IP6H_FL(ip6hdr) == 0) { + /* Flow label is elided. */ + buffer[0] |= 0x10; + if (IP6H_TC(ip6hdr) == 0) { + /* Traffic class (ECN+DSCP) elided too. */ + buffer[0] |= 0x08; + } else { + /* Traffic class (ECN+DSCP) appended. */ + buffer[lowpan6_header_len++] = IP6H_TC(ip6hdr); + } + } else { + if (((IP6H_TC(ip6hdr) & 0x3f) == 0)) { + /* DSCP portion of Traffic Class is elided, ECN and FL are appended (3 bytes) */ + buffer[0] |= 0x08; + + buffer[lowpan6_header_len] = IP6H_TC(ip6hdr) & 0xc0; + buffer[lowpan6_header_len++] |= (IP6H_FL(ip6hdr) >> 16) & 0x0f; + buffer[lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 8) & 0xff; + buffer[lowpan6_header_len++] = IP6H_FL(ip6hdr) & 0xff; + } else { + /* Traffic class and flow label are appended (4 bytes) */ + buffer[lowpan6_header_len++] = IP6H_TC(ip6hdr); + buffer[lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 16) & 0x0f; + buffer[lowpan6_header_len++] = (IP6H_FL(ip6hdr) >> 8) & 0xff; + buffer[lowpan6_header_len++] = IP6H_FL(ip6hdr) & 0xff; + } + } + + /* Compress NH? + * Only if UDP for now. @todo support other NH compression. */ + if (IP6H_NEXTH(ip6hdr) == IP6_NEXTH_UDP) { + buffer[0] |= 0x04; + } else { + /* append nexth. */ + buffer[lowpan6_header_len++] = IP6H_NEXTH(ip6hdr); + } + + /* Compress hop limit? */ + if (IP6H_HOPLIM(ip6hdr) == 255) { + buffer[0] |= 0x03; + } else if (IP6H_HOPLIM(ip6hdr) == 64) { + buffer[0] |= 0x02; + } else if (IP6H_HOPLIM(ip6hdr) == 1) { + buffer[0] |= 0x01; + } else { + /* append hop limit */ + buffer[lowpan6_header_len++] = IP6H_HOPLIM(ip6hdr); + } + + /* Compress source address */ + if (((buffer[1] & 0x40) != 0) || + (ip6_addr_islinklocal(ip_2_ip6(&ip6src)))) { + /* Context-based or link-local source address compression. */ + i = lowpan6_get_address_mode(ip_2_ip6(&ip6src), src); + buffer[1] |= (i & 0x03) << 4; + if (i == 1) { + MEMCPY(buffer + lowpan6_header_len, inptr + 16, 8); + lowpan6_header_len += 8; + } else if (i == 2) { + MEMCPY(buffer + lowpan6_header_len, inptr + 22, 2); + lowpan6_header_len += 2; + } + } else if (ip6_addr_isany(ip_2_ip6(&ip6src))) { + /* Special case: mark SAC and leave SAM=0 */ + buffer[1] |= 0x40; + } else { + /* Append full address. */ + MEMCPY(buffer + lowpan6_header_len, inptr + 8, 16); + lowpan6_header_len += 16; + } + + /* Compress destination address */ + if (ip6_addr_ismulticast(ip_2_ip6(&ip6dst))) { + /* @todo support stateful multicast address compression */ + + buffer[1] |= 0x08; + + i = lowpan6_get_address_mode_mc(ip_2_ip6(&ip6dst)); + buffer[1] |= i & 0x03; + if (i == 0) { + MEMCPY(buffer + lowpan6_header_len, inptr + 24, 16); + lowpan6_header_len += 16; + } else if (i == 1) { + buffer[lowpan6_header_len++] = inptr[25]; + MEMCPY(buffer + lowpan6_header_len, inptr + 35, 5); + lowpan6_header_len += 5; + } else if (i == 2) { + buffer[lowpan6_header_len++] = inptr[25]; + MEMCPY(buffer + lowpan6_header_len, inptr + 37, 3); + lowpan6_header_len += 3; + } else if (i == 3) { + buffer[lowpan6_header_len++] = (inptr)[39]; + } + } else if (((buffer[1] & 0x04) != 0) || + (ip6_addr_islinklocal(ip_2_ip6(&ip6dst)))) { + /* Context-based or link-local destination address compression. */ + i = lowpan6_get_address_mode(ip_2_ip6(&ip6dst), dst); + buffer[1] |= i & 0x03; + if (i == 1) { + MEMCPY(buffer + lowpan6_header_len, inptr + 32, 8); + lowpan6_header_len += 8; + } else if (i == 2) { + MEMCPY(buffer + lowpan6_header_len, inptr + 38, 2); + lowpan6_header_len += 2; + } + } else { + /* Append full address. */ + MEMCPY(buffer + lowpan6_header_len, inptr + 24, 16); + lowpan6_header_len += 16; + } + + /* Move to payload. */ + inptr += IP6_HLEN; + hidden_header_len += IP6_HLEN; + +#if LWIP_UDP + /* Compress UDP header? */ + if (IP6H_NEXTH(ip6hdr) == IP6_NEXTH_UDP) { + /* @todo support optional checksum compression */ + + if (inbuf_size < IP6_HLEN + UDP_HLEN) { + /* input buffer too short */ + return ERR_VAL; + } + if (outbuf_size < (size_t)(hidden_header_len + 7)) { + /* output buffer too short for worst case */ + return ERR_MEM; + } + + buffer[lowpan6_header_len] = 0xf0; + + /* determine port compression mode. */ + if ((inptr[0] == 0xf0) && ((inptr[1] & 0xf0) == 0xb0) && + (inptr[2] == 0xf0) && ((inptr[3] & 0xf0) == 0xb0)) { + /* Compress source and dest ports. */ + buffer[lowpan6_header_len++] |= 0x03; + buffer[lowpan6_header_len++] = ((inptr[1] & 0x0f) << 4) | (inptr[3] & 0x0f); + } else if (inptr[0] == 0xf0) { + /* Compress source port. */ + buffer[lowpan6_header_len++] |= 0x02; + buffer[lowpan6_header_len++] = inptr[1]; + buffer[lowpan6_header_len++] = inptr[2]; + buffer[lowpan6_header_len++] = inptr[3]; + } else if (inptr[2] == 0xf0) { + /* Compress dest port. */ + buffer[lowpan6_header_len++] |= 0x01; + buffer[lowpan6_header_len++] = inptr[0]; + buffer[lowpan6_header_len++] = inptr[1]; + buffer[lowpan6_header_len++] = inptr[3]; + } else { + /* append full ports. */ + lowpan6_header_len++; + buffer[lowpan6_header_len++] = inptr[0]; + buffer[lowpan6_header_len++] = inptr[1]; + buffer[lowpan6_header_len++] = inptr[2]; + buffer[lowpan6_header_len++] = inptr[3]; + } + + /* elide length and copy checksum */ + buffer[lowpan6_header_len++] = inptr[6]; + buffer[lowpan6_header_len++] = inptr[7]; + + hidden_header_len += UDP_HLEN; + } +#endif /* LWIP_UDP */ + + *lowpan6_header_len_out = lowpan6_header_len; + *hidden_header_len_out = hidden_header_len; + + return ERR_OK; +} + +/** Decompress IPv6 and UDP headers compressed according to RFC 6282 + * + * @param lowpan6_buffer compressed headers, first byte is the dispatch byte + * @param lowpan6_bufsize size of lowpan6_buffer (may include data after headers) + * @param decomp_buffer buffer where the decompressed headers are stored + * @param decomp_bufsize size of decomp_buffer + * @param hdr_size_comp returns the size of the compressed headers (skip to get to data) + * @param hdr_size_decomp returns the size of the decompressed headers (IPv6 + UDP) + * @param datagram_size datagram size from fragments or 0 if unfragmented + * @param compressed_size compressed datagram size (for unfragmented rx) + * @param lowpan6_contexts context addresses + * @param src source address of the outer layer, used for address compression + * @param dest destination address of the outer layer, used for address compression + * @return ERR_OK if decompression succeeded, an error otherwise + */ +static err_t +lowpan6_decompress_hdr(u8_t *lowpan6_buffer, size_t lowpan6_bufsize, + u8_t *decomp_buffer, size_t decomp_bufsize, + u16_t *hdr_size_comp, u16_t *hdr_size_decomp, + u16_t datagram_size, u16_t compressed_size, + ip6_addr_t *lowpan6_contexts, + struct lowpan6_link_addr *src, struct lowpan6_link_addr *dest) +{ + u16_t lowpan6_offset; + struct ip6_hdr *ip6hdr; + s8_t i; + u32_t header_temp; + u16_t ip6_offset = IP6_HLEN; + + LWIP_ASSERT("lowpan6_buffer != NULL", lowpan6_buffer != NULL); + LWIP_ASSERT("decomp_buffer != NULL", decomp_buffer != NULL); + LWIP_ASSERT("src != NULL", src != NULL); + LWIP_ASSERT("dest != NULL", dest != NULL); + LWIP_ASSERT("hdr_size_comp != NULL", hdr_size_comp != NULL); + LWIP_ASSERT("dehdr_size_decompst != NULL", hdr_size_decomp != NULL); + + ip6hdr = (struct ip6_hdr *)decomp_buffer; + if (decomp_bufsize < IP6_HLEN) { + return ERR_MEM; + } + + /* output the full compressed packet, if set in @see lowpan6_opts.h */ +#if LWIP_LOWPAN6_IP_COMPRESSED_DEBUG + { + u16_t j; + LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("lowpan6_decompress_hdr: IP6 payload (compressed): \n")); + for (j = 0; j < lowpan6_bufsize; j++) { + if ((j % 4) == 0) { + LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("\n")); + } + LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("%2X ", lowpan6_buffer[j])); + } + LWIP_DEBUGF(LWIP_LOWPAN6_IP_COMPRESSED_DEBUG, ("\np->len: %d", lowpan6_bufsize)); + } +#endif + + /* offset for inline IP headers (RFC 6282 ch3)*/ + lowpan6_offset = 2; + /* if CID is set (context identifier), the context byte + * follows immediately after the header, so other IPHC fields are @+3 */ + if (lowpan6_buffer[1] & 0x80) { + lowpan6_offset++; + } + + /* Set IPv6 version, traffic class and flow label. (RFC6282, ch 3.1.1.)*/ + if ((lowpan6_buffer[0] & 0x18) == 0x00) { + header_temp = ((lowpan6_buffer[lowpan6_offset+1] & 0x0f) << 16) | \ + (lowpan6_buffer[lowpan6_offset + 2] << 8) | lowpan6_buffer[lowpan6_offset+3]; + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 00, ECN: 0x%2x, Flowlabel+DSCP: 0x%8X\n", \ + lowpan6_buffer[lowpan6_offset],header_temp)); + IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset], header_temp); + /* increase offset, processed 4 bytes here: + * TF=00: ECN + DSCP + 4-bit Pad + Flow Label (4 bytes)*/ + lowpan6_offset += 4; + } else if ((lowpan6_buffer[0] & 0x18) == 0x08) { + header_temp = ((lowpan6_buffer[lowpan6_offset] & 0x0f) << 16) | (lowpan6_buffer[lowpan6_offset + 1] << 8) | lowpan6_buffer[lowpan6_offset+2]; + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 01, ECN: 0x%2x, Flowlabel: 0x%2X, DSCP ignored\n", \ + lowpan6_buffer[lowpan6_offset] & 0xc0,header_temp)); + IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset] & 0xc0, header_temp); + /* increase offset, processed 3 bytes here: + * TF=01: ECN + 2-bit Pad + Flow Label (3 bytes), DSCP is elided.*/ + lowpan6_offset += 3; + } else if ((lowpan6_buffer[0] & 0x18) == 0x10) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 10, DCSP+ECN: 0x%2x, Flowlabel ignored\n", lowpan6_buffer[lowpan6_offset])); + IP6H_VTCFL_SET(ip6hdr, 6, lowpan6_buffer[lowpan6_offset],0); + /* increase offset, processed 1 byte here: + * ECN + DSCP (1 byte), Flow Label is elided.*/ + lowpan6_offset += 1; + } else if ((lowpan6_buffer[0] & 0x18) == 0x18) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("TF: 11, DCSP/ECN & Flowlabel ignored\n")); + /* don't increase offset, no bytes processed here */ + IP6H_VTCFL_SET(ip6hdr, 6, 0, 0); + } + + /* Set Next Header (NH) */ + if ((lowpan6_buffer[0] & 0x04) == 0x00) { + /* 0: full next header byte carried inline (increase offset)*/ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NH: 0x%2X\n", lowpan6_buffer[lowpan6_offset+1])); + IP6H_NEXTH_SET(ip6hdr, lowpan6_buffer[lowpan6_offset++]); + } else { + /* 1: NH compression, LOWPAN_NHC (RFC6282, ch 4.1) */ + /* We should fill this later with NHC decoding */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NH: skipped, later done with NHC\n")); + IP6H_NEXTH_SET(ip6hdr, 0); + } + + /* Set Hop Limit, either carried inline or 3 different hops (1,64,255) */ + if ((lowpan6_buffer[0] & 0x03) == 0x00) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: full value: %d\n", lowpan6_buffer[lowpan6_offset+1])); + IP6H_HOPLIM_SET(ip6hdr, lowpan6_buffer[lowpan6_offset++]); + } else if ((lowpan6_buffer[0] & 0x03) == 0x01) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: compressed: 1\n")); + IP6H_HOPLIM_SET(ip6hdr, 1); + } else if ((lowpan6_buffer[0] & 0x03) == 0x02) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: compressed: 64\n")); + IP6H_HOPLIM_SET(ip6hdr, 64); + } else if ((lowpan6_buffer[0] & 0x03) == 0x03) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Hops: compressed: 255\n")); + IP6H_HOPLIM_SET(ip6hdr, 255); + } + + /* Source address decoding. */ + if ((lowpan6_buffer[1] & 0x40) == 0x00) { + /* Source address compression (SAC) = 0 -> stateless compression */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAC == 0, no context byte\n")); + /* Stateless compression */ + if ((lowpan6_buffer[1] & 0x30) == 0x00) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 00, no src compression, fetching 128bits inline\n")); + /* copy full address, increase offset by 16 Bytes */ + MEMCPY(&ip6hdr->src.addr[0], lowpan6_buffer + lowpan6_offset, 16); + lowpan6_offset += 16; + } else if ((lowpan6_buffer[1] & 0x30) == 0x10) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 01, src compression, 64bits inline\n")); + /* set 64 bits to link local */ + ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL); + ip6hdr->src.addr[1] = 0; + /* copy 8 Bytes, increase offset */ + MEMCPY(&ip6hdr->src.addr[2], lowpan6_buffer + lowpan6_offset, 8); + lowpan6_offset += 8; + } else if ((lowpan6_buffer[1] & 0x30) == 0x20) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 10, src compression, 16bits inline\n")); + /* set 96 bits to link local */ + ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL); + ip6hdr->src.addr[1] = 0; + ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); + /* extract remaining 16bits from inline bytes, increase offset */ + ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | + lowpan6_buffer[lowpan6_offset + 1]); + lowpan6_offset += 2; + } else if ((lowpan6_buffer[1] & 0x30) == 0x30) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 11, src compression, 0bits inline, using other headers\n")); + /* no information avalaible, using other layers, see RFC6282 ch 3.2.2 */ + ip6hdr->src.addr[0] = PP_HTONL(0xfe800000UL); + ip6hdr->src.addr[1] = 0; + if (src->addr_len == 2) { + ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); + ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (src->addr[0] << 8) | src->addr[1]); + } else if (src->addr_len == 8) { + ip6hdr->src.addr[2] = lwip_htonl(((src->addr[0] ^ 2) << 24) | (src->addr[1] << 16) | + (src->addr[2] << 8) | src->addr[3]); + ip6hdr->src.addr[3] = lwip_htonl((src->addr[4] << 24) | (src->addr[5] << 16) | + (src->addr[6] << 8) | src->addr[7]); + } else { + /* invalid source address length */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Invalid source address length\n")); + return ERR_VAL; + } + } + } else { + /* Source address compression (SAC) = 1 -> stateful/context-based compression */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAC == 1, additional context byte\n")); + if ((lowpan6_buffer[1] & 0x30) == 0x00) { + /* SAM=00, address=> :: (ANY) */ + ip6hdr->src.addr[0] = 0; + ip6hdr->src.addr[1] = 0; + ip6hdr->src.addr[2] = 0; + ip6hdr->src.addr[3] = 0; + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 00, context compression, ANY (::)\n")); + } else { + /* Set prefix from context info */ + if (lowpan6_buffer[1] & 0x80) { + i = (lowpan6_buffer[2] >> 4) & 0x0f; + } else { + i = 0; + } + if (i >= LWIP_6LOWPAN_NUM_CONTEXTS) { + /* Error */ + return ERR_VAL; + } +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 + ip6hdr->src.addr[0] = lowpan6_contexts[i].addr[0]; + ip6hdr->src.addr[1] = lowpan6_contexts[i].addr[1]; + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == xx, context compression found @%d: %8X, %8X\n", (int)i, ip6hdr->src.addr[0], ip6hdr->src.addr[1])); +#else + LWIP_UNUSED_ARG(lowpan6_contexts); +#endif + } + + /* determine further address bits */ + if ((lowpan6_buffer[1] & 0x30) == 0x10) { + /* SAM=01, load additional 64bits */ + MEMCPY(&ip6hdr->src.addr[2], lowpan6_buffer + lowpan6_offset, 8); + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 01, context compression, 64bits inline\n")); + lowpan6_offset += 8; + } else if ((lowpan6_buffer[1] & 0x30) == 0x20) { + /* SAM=01, load additional 16bits */ + ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); + ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | lowpan6_buffer[lowpan6_offset + 1]); + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 10, context compression, 16bits inline\n")); + lowpan6_offset += 2; + } else if ((lowpan6_buffer[1] & 0x30) == 0x30) { + /* SAM=11, address is fully elided, load from other layers */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("SAM == 11, context compression, 0bits inline, using other headers\n")); + if (src->addr_len == 2) { + ip6hdr->src.addr[2] = PP_HTONL(0x000000ffUL); + ip6hdr->src.addr[3] = lwip_htonl(0xfe000000UL | (src->addr[0] << 8) | src->addr[1]); + } else if (src->addr_len == 8) { + ip6hdr->src.addr[2] = lwip_htonl(((src->addr[0] ^ 2) << 24) | (src->addr[1] << 16) | (src->addr[2] << 8) | src->addr[3]); + ip6hdr->src.addr[3] = lwip_htonl((src->addr[4] << 24) | (src->addr[5] << 16) | (src->addr[6] << 8) | src->addr[7]); + } else { + /* invalid source address length */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Invalid source address length\n")); + return ERR_VAL; + } + } + } + + /* Destination address decoding. */ + if (lowpan6_buffer[1] & 0x08) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("M=1: multicast\n")); + /* Multicast destination */ + if (lowpan6_buffer[1] & 0x04) { + LWIP_DEBUGF(LWIP_DBG_ON,("DAC == 1, context multicast: unsupported!!!\n")); + /* @todo support stateful multicast addressing */ + return ERR_VAL; + } + + if ((lowpan6_buffer[1] & 0x03) == 0x00) { + /* DAM = 00, copy full address (128bits) */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 00, no dst compression, fetching 128bits inline\n")); + MEMCPY(&ip6hdr->dest.addr[0], lowpan6_buffer + lowpan6_offset, 16); + lowpan6_offset += 16; + } else if ((lowpan6_buffer[1] & 0x03) == 0x01) { + /* DAM = 01, copy 4 bytes (32bits) */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 01, dst address form (48bits): ffXX::00XX:XXXX:XXXX\n")); + ip6hdr->dest.addr[0] = lwip_htonl(0xff000000UL | (lowpan6_buffer[lowpan6_offset++] << 16)); + ip6hdr->dest.addr[1] = 0; + ip6hdr->dest.addr[2] = lwip_htonl(lowpan6_buffer[lowpan6_offset++]); + ip6hdr->dest.addr[3] = lwip_htonl((lowpan6_buffer[lowpan6_offset] << 24) | (lowpan6_buffer[lowpan6_offset + 1] << 16) | (lowpan6_buffer[lowpan6_offset + 2] << 8) | lowpan6_buffer[lowpan6_offset + 3]); + lowpan6_offset += 4; + } else if ((lowpan6_buffer[1] & 0x03) == 0x02) { + /* DAM = 10, copy 3 bytes (24bits) */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 10, dst address form (32bits): ffXX::00XX:XXXX\n")); + ip6hdr->dest.addr[0] = lwip_htonl(0xff000000UL | (lowpan6_buffer[lowpan6_offset++] << 16)); + ip6hdr->dest.addr[1] = 0; + ip6hdr->dest.addr[2] = 0; + ip6hdr->dest.addr[3] = lwip_htonl((lowpan6_buffer[lowpan6_offset] << 16) | (lowpan6_buffer[lowpan6_offset + 1] << 8) | lowpan6_buffer[lowpan6_offset + 2]); + lowpan6_offset += 3; + } else if ((lowpan6_buffer[1] & 0x03) == 0x03) { + /* DAM = 11, copy 1 byte (8bits) */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 11, dst address form (8bits): ff02::00XX\n")); + ip6hdr->dest.addr[0] = PP_HTONL(0xff020000UL); + ip6hdr->dest.addr[1] = 0; + ip6hdr->dest.addr[2] = 0; + ip6hdr->dest.addr[3] = lwip_htonl(lowpan6_buffer[lowpan6_offset++]); + } + + } else { + /* no Multicast (M=0) */ + if (lowpan6_buffer[1] & 0x04) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAC == 1, stateful compression\n")); + /* Stateful destination compression */ + /* Set prefix from context info */ + if (lowpan6_buffer[1] & 0x80) { + i = lowpan6_buffer[2] & 0x0f; + } else { + i = 0; + } + if (i >= LWIP_6LOWPAN_NUM_CONTEXTS) { + /* Error */ + return ERR_VAL; + } +#if LWIP_6LOWPAN_NUM_CONTEXTS > 0 + ip6hdr->dest.addr[0] = lowpan6_contexts[i].addr[0]; + ip6hdr->dest.addr[1] = lowpan6_contexts[i].addr[1]; +#endif + } else { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAC == 0, stateless compression, setting link local prefix\n")); + /* Link local address compression */ + ip6hdr->dest.addr[0] = PP_HTONL(0xfe800000UL); + ip6hdr->dest.addr[1] = 0; + } + + /* M=0, DAC=0, determining destination address length via DAM=xx */ + if ((lowpan6_buffer[1] & 0x03) == 0x00) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 00, no dst compression, fetching 128bits inline")); + /* DAM=00, copy full address */ + MEMCPY(&ip6hdr->dest.addr[0], lowpan6_buffer + lowpan6_offset, 16); + lowpan6_offset += 16; + } else if ((lowpan6_buffer[1] & 0x03) == 0x01) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 01, dst compression, 64bits inline\n")); + /* DAM=01, copy 64 inline bits, increase offset */ + MEMCPY(&ip6hdr->dest.addr[2], lowpan6_buffer + lowpan6_offset, 8); + lowpan6_offset += 8; + } else if ((lowpan6_buffer[1] & 0x03) == 0x02) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("DAM == 01, dst compression, 16bits inline\n")); + /* DAM=10, copy 16 inline bits, increase offset */ + ip6hdr->dest.addr[2] = PP_HTONL(0x000000ffUL); + ip6hdr->dest.addr[3] = lwip_htonl(0xfe000000UL | (lowpan6_buffer[lowpan6_offset] << 8) | lowpan6_buffer[lowpan6_offset + 1]); + lowpan6_offset += 2; + } else if ((lowpan6_buffer[1] & 0x03) == 0x03) { + /* DAM=11, no bits available, use other headers (not done here) */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG,("DAM == 01, dst compression, 0bits inline, using other headers\n")); + if (dest->addr_len == 2) { + ip6hdr->dest.addr[2] = PP_HTONL(0x000000ffUL); + ip6hdr->dest.addr[3] = lwip_htonl(0xfe000000UL | (dest->addr[0] << 8) | dest->addr[1]); + } else if (dest->addr_len == 8) { + ip6hdr->dest.addr[2] = lwip_htonl(((dest->addr[0] ^ 2) << 24) | (dest->addr[1] << 16) | dest->addr[2] << 8 | dest->addr[3]); + ip6hdr->dest.addr[3] = lwip_htonl((dest->addr[4] << 24) | (dest->addr[5] << 16) | dest->addr[6] << 8 | dest->addr[7]); + } else { + /* invalid destination address length */ + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("Invalid destination address length\n")); + return ERR_VAL; + } + } + } + + + /* Next Header Compression (NHC) decoding? */ + if (lowpan6_buffer[0] & 0x04) { + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NHC decoding\n")); +#if LWIP_UDP + if ((lowpan6_buffer[lowpan6_offset] & 0xf8) == 0xf0) { + /* NHC: UDP */ + struct udp_hdr *udphdr; + LWIP_DEBUGF(LWIP_LOWPAN6_DECOMPRESSION_DEBUG, ("NHC: UDP\n")); + + /* UDP compression */ + IP6H_NEXTH_SET(ip6hdr, IP6_NEXTH_UDP); + udphdr = (struct udp_hdr *)((u8_t *)decomp_buffer + ip6_offset); + if (decomp_bufsize < IP6_HLEN + UDP_HLEN) { + return ERR_MEM; + } + + /* Checksum decompression */ + if (lowpan6_buffer[lowpan6_offset] & 0x04) { + /* @todo support checksum decompress */ + LWIP_DEBUGF(LWIP_DBG_ON, ("NHC: UDP chechsum decompression UNSUPPORTED\n")); + return ERR_VAL; + } + + /* Decompress ports, according to RFC4944 */ + i = lowpan6_buffer[lowpan6_offset++] & 0x03; + if (i == 0) { + udphdr->src = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]); + udphdr->dest = lwip_htons(lowpan6_buffer[lowpan6_offset + 2] << 8 | lowpan6_buffer[lowpan6_offset + 3]); + lowpan6_offset += 4; + } else if (i == 0x01) { + udphdr->src = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]); + udphdr->dest = lwip_htons(0xf000 | lowpan6_buffer[lowpan6_offset + 2]); + lowpan6_offset += 3; + } else if (i == 0x02) { + udphdr->src = lwip_htons(0xf000 | lowpan6_buffer[lowpan6_offset]); + udphdr->dest = lwip_htons(lowpan6_buffer[lowpan6_offset + 1] << 8 | lowpan6_buffer[lowpan6_offset + 2]); + lowpan6_offset += 3; + } else if (i == 0x03) { + udphdr->src = lwip_htons(0xf0b0 | ((lowpan6_buffer[lowpan6_offset] >> 4) & 0x0f)); + udphdr->dest = lwip_htons(0xf0b0 | (lowpan6_buffer[lowpan6_offset] & 0x0f)); + lowpan6_offset += 1; + } + + udphdr->chksum = lwip_htons(lowpan6_buffer[lowpan6_offset] << 8 | lowpan6_buffer[lowpan6_offset + 1]); + lowpan6_offset += 2; + ip6_offset += UDP_HLEN; + if (datagram_size == 0) { + datagram_size = compressed_size - lowpan6_offset + ip6_offset; + } + udphdr->len = lwip_htons(datagram_size - IP6_HLEN); + + } else +#endif /* LWIP_UDP */ + { + LWIP_DEBUGF(LWIP_DBG_ON,("NHC: unsupported protocol!\n")); + /* @todo support NHC other than UDP */ + return ERR_VAL; + } + } + if (datagram_size == 0) { + datagram_size = compressed_size - lowpan6_offset + ip6_offset; + } + /* Infer IPv6 payload length for header */ + IP6H_PLEN_SET(ip6hdr, datagram_size - IP6_HLEN); + + if (lowpan6_offset > lowpan6_bufsize) { + /* input buffer overflow */ + return ERR_VAL; + } + *hdr_size_comp = lowpan6_offset; + *hdr_size_decomp = ip6_offset; + + return ERR_OK; +} + +struct pbuf * +lowpan6_decompress(struct pbuf *p, u16_t datagram_size, ip6_addr_t *lowpan6_contexts, + struct lowpan6_link_addr *src, struct lowpan6_link_addr *dest) +{ + struct pbuf *q; + u16_t lowpan6_offset, ip6_offset; + err_t err; + +#if LWIP_UDP +#define UDP_HLEN_ALLOC UDP_HLEN +#else +#define UDP_HLEN_ALLOC 0 +#endif + + /* Allocate a buffer for decompression. This buffer will be too big and will be + trimmed once the final size is known. */ + q = pbuf_alloc(PBUF_IP, p->len + IP6_HLEN + UDP_HLEN_ALLOC, PBUF_POOL); + if (q == NULL) { + pbuf_free(p); + return NULL; + } + if (q->len < IP6_HLEN + UDP_HLEN_ALLOC) { + /* The headers need to fit into the first pbuf */ + pbuf_free(p); + pbuf_free(q); + return NULL; + } + + /* Decompress the IPv6 (and possibly UDP) header(s) into the new pbuf */ + err = lowpan6_decompress_hdr((u8_t *)p->payload, p->len, (u8_t *)q->payload, q->len, + &lowpan6_offset, &ip6_offset, datagram_size, p->tot_len, lowpan6_contexts, src, dest); + if (err != ERR_OK) { + pbuf_free(p); + pbuf_free(q); + return NULL; + } + + /* Now we copy leftover contents from p to q, so we have all L2 and L3 headers + (and L4?) in a single pbuf: */ + + /* Hide the compressed headers in p */ + pbuf_remove_header(p, lowpan6_offset); + /* Temporarily hide the headers in q... */ + pbuf_remove_header(q, ip6_offset); + /* ... copy the rest of p into q... */ + pbuf_copy(q, p); + /* ... and reveal the headers again... */ + pbuf_add_header_force(q, ip6_offset); + /* ... trim the pbuf to its correct size... */ + pbuf_realloc(q, ip6_offset + p->len); + /* ... and cat possibly remaining (data-only) pbufs */ + if (p->next != NULL) { + pbuf_cat(q, p->next); + } + /* the original (first) pbuf can now be freed */ + p->next = NULL; + pbuf_free(p); + + /* all done */ + return q; +} + +#endif /* LWIP_6LOWPAN_IPHC */ +#endif /* LWIP_IPV6 */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c new file mode 100644 index 0000000..c8673ad --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/auth.c @@ -0,0 +1,2510 @@ +/* + * auth.c - PPP authentication and phase control. + * + * Copyright (c) 1993-2002 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Derived from main.c, which is: + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if 0 /* UNUSED */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(_PATH_LASTLOG) && defined(__linux__) +#include +#endif + +#include +#include +#include + +#ifdef HAS_SHADOW +#include +#ifndef PW_PPP +#define PW_PPP PW_LOGIN +#endif +#endif + +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/lcp.h" +#if CCP_SUPPORT +#include "netif/ppp/ccp.h" +#endif /* CCP_SUPPORT */ +#if ECP_SUPPORT +#include "netif/ppp/ecp.h" +#endif /* ECP_SUPPORT */ +#include "netif/ppp/ipcp.h" +#if PAP_SUPPORT +#include "netif/ppp/upap.h" +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT +#include "netif/ppp/chap-new.h" +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT +#include "netif/ppp/eap.h" +#endif /* EAP_SUPPORT */ +#if CBCP_SUPPORT +#include "netif/ppp/cbcp.h" +#endif + +#if 0 /* UNUSED */ +#include "session.h" +#endif /* UNUSED */ + +#if 0 /* UNUSED */ +/* Bits in scan_authfile return value */ +#define NONWILD_SERVER 1 +#define NONWILD_CLIENT 2 + +#define ISWILD(word) (word[0] == '*' && word[1] == 0) +#endif /* UNUSED */ + +#if 0 /* UNUSED */ +/* List of addresses which the peer may use. */ +static struct permitted_ip *addresses[NUM_PPP]; + +/* Wordlist giving addresses which the peer may use + without authenticating itself. */ +static struct wordlist *noauth_addrs; + +/* Remote telephone number, if available */ +char remote_number[MAXNAMELEN]; + +/* Wordlist giving remote telephone numbers which may connect. */ +static struct wordlist *permitted_numbers; + +/* Extra options to apply, from the secrets file entry for the peer. */ +static struct wordlist *extra_options; +#endif /* UNUSED */ + +#if 0 /* UNUSED */ +/* Set if we require authentication only because we have a default route. */ +static bool default_auth; + +/* Hook to enable a plugin to control the idle time limit */ +int (*idle_time_hook) (struct ppp_idle *) = NULL; + +/* Hook for a plugin to say whether we can possibly authenticate any peer */ +int (*pap_check_hook) (void) = NULL; + +/* Hook for a plugin to check the PAP user and password */ +int (*pap_auth_hook) (char *user, char *passwd, char **msgp, + struct wordlist **paddrs, + struct wordlist **popts) = NULL; + +/* Hook for a plugin to know about the PAP user logout */ +void (*pap_logout_hook) (void) = NULL; + +/* Hook for a plugin to get the PAP password for authenticating us */ +int (*pap_passwd_hook) (char *user, char *passwd) = NULL; + +/* Hook for a plugin to say if we can possibly authenticate a peer using CHAP */ +int (*chap_check_hook) (void) = NULL; + +/* Hook for a plugin to get the CHAP password for authenticating us */ +int (*chap_passwd_hook) (char *user, char *passwd) = NULL; + +/* Hook for a plugin to say whether it is OK if the peer + refuses to authenticate. */ +int (*null_auth_hook) (struct wordlist **paddrs, + struct wordlist **popts) = NULL; + +int (*allowed_address_hook) (u32_t addr) = NULL; +#endif /* UNUSED */ + +#ifdef HAVE_MULTILINK +/* Hook for plugin to hear when an interface joins a multilink bundle */ +void (*multilink_join_hook) (void) = NULL; +#endif + +#if PPP_NOTIFY +/* A notifier for when the peer has authenticated itself, + and we are proceeding to the network phase. */ +struct notifier *auth_up_notifier = NULL; + +/* A notifier for when the link goes down. */ +struct notifier *link_down_notifier = NULL; +#endif /* PPP_NOTIFY */ + +/* + * Option variables. + */ +#if 0 /* MOVED TO ppp_settings */ +bool uselogin = 0; /* Use /etc/passwd for checking PAP */ +bool session_mgmt = 0; /* Do session management (login records) */ +bool cryptpap = 0; /* Passwords in pap-secrets are encrypted */ +bool refuse_pap = 0; /* Don't wanna auth. ourselves with PAP */ +bool refuse_chap = 0; /* Don't wanna auth. ourselves with CHAP */ +bool refuse_eap = 0; /* Don't wanna auth. ourselves with EAP */ +#if MSCHAP_SUPPORT +bool refuse_mschap = 0; /* Don't wanna auth. ourselves with MS-CHAP */ +bool refuse_mschap_v2 = 0; /* Don't wanna auth. ourselves with MS-CHAPv2 */ +#else /* MSCHAP_SUPPORT */ +bool refuse_mschap = 1; /* Don't wanna auth. ourselves with MS-CHAP */ +bool refuse_mschap_v2 = 1; /* Don't wanna auth. ourselves with MS-CHAPv2 */ +#endif /* MSCHAP_SUPPORT */ +bool usehostname = 0; /* Use hostname for our_name */ +bool auth_required = 0; /* Always require authentication from peer */ +bool allow_any_ip = 0; /* Allow peer to use any IP address */ +bool explicit_remote = 0; /* User specified explicit remote name */ +bool explicit_user = 0; /* Set if "user" option supplied */ +bool explicit_passwd = 0; /* Set if "password" option supplied */ +char remote_name[MAXNAMELEN]; /* Peer's name for authentication */ +static char *uafname; /* name of most recent +ua file */ + +extern char *crypt (const char *, const char *); +#endif /* UNUSED */ +/* Prototypes for procedures local to this file. */ + +static void network_phase(ppp_pcb *pcb); +#if PPP_IDLETIMELIMIT +static void check_idle(void *arg); +#endif /* PPP_IDLETIMELIMIT */ +#if PPP_MAXCONNECT +static void connect_time_expired(void *arg); +#endif /* PPP_MAXCONNECT */ +#if 0 /* UNUSED */ +static int null_login (int); +/* static int get_pap_passwd (char *); */ +static int have_pap_secret (int *); +static int have_chap_secret (char *, char *, int, int *); +static int have_srp_secret (char *client, char *server, int need_ip, + int *lacks_ipp); +static int ip_addr_check (u32_t, struct permitted_ip *); +static int scan_authfile (FILE *, char *, char *, char *, + struct wordlist **, struct wordlist **, + char *, int); +static void free_wordlist (struct wordlist *); +static void set_allowed_addrs (int, struct wordlist *, struct wordlist *); +static int some_ip_ok (struct wordlist *); +static int setupapfile (char **); +static int privgroup (char **); +static int set_noauth_addr (char **); +static int set_permitted_number (char **); +static void check_access (FILE *, char *); +static int wordlist_count (struct wordlist *); +#endif /* UNUSED */ + +#ifdef MAXOCTETS +static void check_maxoctets (void *); +#endif + +#if PPP_OPTIONS +/* + * Authentication-related options. + */ +option_t auth_options[] = { + { "auth", o_bool, &auth_required, + "Require authentication from peer", OPT_PRIO | 1 }, + { "noauth", o_bool, &auth_required, + "Don't require peer to authenticate", OPT_PRIOSUB | OPT_PRIV, + &allow_any_ip }, + { "require-pap", o_bool, &lcp_wantoptions[0].neg_upap, + "Require PAP authentication from peer", + OPT_PRIOSUB | 1, &auth_required }, + { "+pap", o_bool, &lcp_wantoptions[0].neg_upap, + "Require PAP authentication from peer", + OPT_ALIAS | OPT_PRIOSUB | 1, &auth_required }, + { "require-chap", o_bool, &auth_required, + "Require CHAP authentication from peer", + OPT_PRIOSUB | OPT_A2OR | MDTYPE_MD5, + &lcp_wantoptions[0].chap_mdtype }, + { "+chap", o_bool, &auth_required, + "Require CHAP authentication from peer", + OPT_ALIAS | OPT_PRIOSUB | OPT_A2OR | MDTYPE_MD5, + &lcp_wantoptions[0].chap_mdtype }, +#if MSCHAP_SUPPORT + { "require-mschap", o_bool, &auth_required, + "Require MS-CHAP authentication from peer", + OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT, + &lcp_wantoptions[0].chap_mdtype }, + { "+mschap", o_bool, &auth_required, + "Require MS-CHAP authentication from peer", + OPT_ALIAS | OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT, + &lcp_wantoptions[0].chap_mdtype }, + { "require-mschap-v2", o_bool, &auth_required, + "Require MS-CHAPv2 authentication from peer", + OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT_V2, + &lcp_wantoptions[0].chap_mdtype }, + { "+mschap-v2", o_bool, &auth_required, + "Require MS-CHAPv2 authentication from peer", + OPT_ALIAS | OPT_PRIOSUB | OPT_A2OR | MDTYPE_MICROSOFT_V2, + &lcp_wantoptions[0].chap_mdtype }, +#endif /* MSCHAP_SUPPORT */ +#if 0 + { "refuse-pap", o_bool, &refuse_pap, + "Don't agree to auth to peer with PAP", 1 }, + { "-pap", o_bool, &refuse_pap, + "Don't allow PAP authentication with peer", OPT_ALIAS | 1 }, + { "refuse-chap", o_bool, &refuse_chap, + "Don't agree to auth to peer with CHAP", + OPT_A2CLRB | MDTYPE_MD5, + &lcp_allowoptions[0].chap_mdtype }, + { "-chap", o_bool, &refuse_chap, + "Don't allow CHAP authentication with peer", + OPT_ALIAS | OPT_A2CLRB | MDTYPE_MD5, + &lcp_allowoptions[0].chap_mdtype }, +#endif +#if MSCHAP_SUPPORT +#if 0 + { "refuse-mschap", o_bool, &refuse_mschap, + "Don't agree to auth to peer with MS-CHAP", + OPT_A2CLRB | MDTYPE_MICROSOFT, + &lcp_allowoptions[0].chap_mdtype }, + { "-mschap", o_bool, &refuse_mschap, + "Don't allow MS-CHAP authentication with peer", + OPT_ALIAS | OPT_A2CLRB | MDTYPE_MICROSOFT, + &lcp_allowoptions[0].chap_mdtype }, + { "refuse-mschap-v2", o_bool, &refuse_mschap_v2, + "Don't agree to auth to peer with MS-CHAPv2", + OPT_A2CLRB | MDTYPE_MICROSOFT_V2, + &lcp_allowoptions[0].chap_mdtype }, + { "-mschap-v2", o_bool, &refuse_mschap_v2, + "Don't allow MS-CHAPv2 authentication with peer", + OPT_ALIAS | OPT_A2CLRB | MDTYPE_MICROSOFT_V2, + &lcp_allowoptions[0].chap_mdtype }, +#endif +#endif /* MSCHAP_SUPPORT*/ +#if EAP_SUPPORT + { "require-eap", o_bool, &lcp_wantoptions[0].neg_eap, + "Require EAP authentication from peer", OPT_PRIOSUB | 1, + &auth_required }, +#if 0 + { "refuse-eap", o_bool, &refuse_eap, + "Don't agree to authenticate to peer with EAP", 1 }, +#endif +#endif /* EAP_SUPPORT */ + { "name", o_string, our_name, + "Set local name for authentication", + OPT_PRIO | OPT_PRIV | OPT_STATIC, NULL, MAXNAMELEN }, + + { "+ua", o_special, (void *)setupapfile, + "Get PAP user and password from file", + OPT_PRIO | OPT_A2STRVAL, &uafname }, + +#if 0 + { "user", o_string, user, + "Set name for auth with peer", OPT_PRIO | OPT_STATIC, + &explicit_user, MAXNAMELEN }, + + { "password", o_string, passwd, + "Password for authenticating us to the peer", + OPT_PRIO | OPT_STATIC | OPT_HIDE, + &explicit_passwd, MAXSECRETLEN }, +#endif + + { "usehostname", o_bool, &usehostname, + "Must use hostname for authentication", 1 }, + + { "remotename", o_string, remote_name, + "Set remote name for authentication", OPT_PRIO | OPT_STATIC, + &explicit_remote, MAXNAMELEN }, + + { "login", o_bool, &uselogin, + "Use system password database for PAP", OPT_A2COPY | 1 , + &session_mgmt }, + { "enable-session", o_bool, &session_mgmt, + "Enable session accounting for remote peers", OPT_PRIV | 1 }, + + { "papcrypt", o_bool, &cryptpap, + "PAP passwords are encrypted", 1 }, + + { "privgroup", o_special, (void *)privgroup, + "Allow group members to use privileged options", OPT_PRIV | OPT_A2LIST }, + + { "allow-ip", o_special, (void *)set_noauth_addr, + "Set IP address(es) which can be used without authentication", + OPT_PRIV | OPT_A2LIST }, + + { "remotenumber", o_string, remote_number, + "Set remote telephone number for authentication", OPT_PRIO | OPT_STATIC, + NULL, MAXNAMELEN }, + + { "allow-number", o_special, (void *)set_permitted_number, + "Set telephone number(s) which are allowed to connect", + OPT_PRIV | OPT_A2LIST }, + + { NULL } +}; +#endif /* PPP_OPTIONS */ + +#if 0 /* UNUSED */ +/* + * setupapfile - specifies UPAP info for authenticating with peer. + */ +static int +setupapfile(argv) + char **argv; +{ + FILE *ufile; + int l; + uid_t euid; + char u[MAXNAMELEN], p[MAXSECRETLEN]; + char *fname; + + lcp_allowoptions[0].neg_upap = 1; + + /* open user info file */ + fname = strdup(*argv); + if (fname == NULL) + novm("+ua file name"); + euid = geteuid(); + if (seteuid(getuid()) == -1) { + option_error("unable to reset uid before opening %s: %m", fname); + return 0; + } + ufile = fopen(fname, "r"); + if (seteuid(euid) == -1) + fatal("unable to regain privileges: %m"); + if (ufile == NULL) { + option_error("unable to open user login data file %s", fname); + return 0; + } + check_access(ufile, fname); + uafname = fname; + + /* get username */ + if (fgets(u, MAXNAMELEN - 1, ufile) == NULL + || fgets(p, MAXSECRETLEN - 1, ufile) == NULL) { + fclose(ufile); + option_error("unable to read user login data file %s", fname); + return 0; + } + fclose(ufile); + + /* get rid of newlines */ + l = strlen(u); + if (l > 0 && u[l-1] == '\n') + u[l-1] = 0; + l = strlen(p); + if (l > 0 && p[l-1] == '\n') + p[l-1] = 0; + + if (override_value("user", option_priority, fname)) { + strlcpy(ppp_settings.user, u, sizeof(ppp_settings.user)); + explicit_user = 1; + } + if (override_value("passwd", option_priority, fname)) { + strlcpy(ppp_settings.passwd, p, sizeof(ppp_settings.passwd)); + explicit_passwd = 1; + } + + return (1); +} + +/* + * privgroup - allow members of the group to have privileged access. + */ +static int +privgroup(argv) + char **argv; +{ + struct group *g; + int i; + + g = getgrnam(*argv); + if (g == 0) { + option_error("group %s is unknown", *argv); + return 0; + } + for (i = 0; i < ngroups; ++i) { + if (groups[i] == g->gr_gid) { + privileged = 1; + break; + } + } + return 1; +} + + +/* + * set_noauth_addr - set address(es) that can be used without authentication. + * Equivalent to specifying an entry like `"" * "" addr' in pap-secrets. + */ +static int +set_noauth_addr(argv) + char **argv; +{ + char *addr = *argv; + int l = strlen(addr) + 1; + struct wordlist *wp; + + wp = (struct wordlist *) malloc(sizeof(struct wordlist) + l); + if (wp == NULL) + novm("allow-ip argument"); + wp->word = (char *) (wp + 1); + wp->next = noauth_addrs; + MEMCPY(wp->word, addr, l); + noauth_addrs = wp; + return 1; +} + + +/* + * set_permitted_number - set remote telephone number(s) that may connect. + */ +static int +set_permitted_number(argv) + char **argv; +{ + char *number = *argv; + int l = strlen(number) + 1; + struct wordlist *wp; + + wp = (struct wordlist *) malloc(sizeof(struct wordlist) + l); + if (wp == NULL) + novm("allow-number argument"); + wp->word = (char *) (wp + 1); + wp->next = permitted_numbers; + MEMCPY(wp->word, number, l); + permitted_numbers = wp; + return 1; +} +#endif + +/* + * An Open on LCP has requested a change from Dead to Establish phase. + */ +void link_required(ppp_pcb *pcb) { + LWIP_UNUSED_ARG(pcb); +} + +#if 0 +/* + * Bring the link up to the point of being able to do ppp. + */ +void start_link(unit) + int unit; +{ + ppp_pcb *pcb = &ppp_pcb_list[unit]; + char *msg; + + status = EXIT_NEGOTIATION_FAILED; + new_phase(pcb, PPP_PHASE_SERIALCONN); + + hungup = 0; + devfd = the_channel->connect(); + msg = "Connect script failed"; + if (devfd < 0) + goto fail; + + /* set up the serial device as a ppp interface */ + /* + * N.B. we used to do tdb_writelock/tdb_writeunlock around this + * (from establish_ppp to set_ifunit). However, we won't be + * doing the set_ifunit in multilink mode, which is the only time + * we need the atomicity that the tdb_writelock/tdb_writeunlock + * gives us. Thus we don't need the tdb_writelock/tdb_writeunlock. + */ + fd_ppp = the_channel->establish_ppp(devfd); + msg = "ppp establishment failed"; + if (fd_ppp < 0) { + status = EXIT_FATAL_ERROR; + goto disconnect; + } + + if (!demand && ifunit >= 0) + set_ifunit(1); + + /* + * Start opening the connection and wait for + * incoming events (reply, timeout, etc.). + */ + if (ifunit >= 0) + ppp_notice("Connect: %s <--> %s", ifname, ppp_devnam); + else + ppp_notice("Starting negotiation on %s", ppp_devnam); + add_fd(fd_ppp); + + new_phase(pcb, PPP_PHASE_ESTABLISH); + + lcp_lowerup(pcb); + return; + + disconnect: + new_phase(pcb, PPP_PHASE_DISCONNECT); + if (the_channel->disconnect) + the_channel->disconnect(); + + fail: + new_phase(pcb, PPP_PHASE_DEAD); + if (the_channel->cleanup) + (*the_channel->cleanup)(); +} +#endif + +/* + * LCP has terminated the link; go to the Dead phase and take the + * physical layer down. + */ +void link_terminated(ppp_pcb *pcb) { + if (pcb->phase == PPP_PHASE_DEAD +#ifdef HAVE_MULTILINK + || pcb->phase == PPP_PHASE_MASTER +#endif /* HAVE_MULTILINK */ + ) + return; + new_phase(pcb, PPP_PHASE_DISCONNECT); + +#if 0 /* UNUSED */ + if (pap_logout_hook) { + pap_logout_hook(); + } + session_end(devnam); +#endif /* UNUSED */ + + if (!doing_multilink) { + ppp_notice("Connection terminated."); +#if PPP_STATS_SUPPORT + print_link_stats(); +#endif /* PPP_STATS_SUPPORT */ + } else + ppp_notice("Link terminated."); + + lcp_lowerdown(pcb); + + ppp_link_terminated(pcb); +#if 0 + /* + * Delete pid files before disestablishing ppp. Otherwise it + * can happen that another pppd gets the same unit and then + * we delete its pid file. + */ + if (!doing_multilink && !demand) + remove_pidfiles(); + + /* + * If we may want to bring the link up again, transfer + * the ppp unit back to the loopback. Set the + * real serial device back to its normal mode of operation. + */ + if (fd_ppp >= 0) { + remove_fd(fd_ppp); + clean_check(); + the_channel->disestablish_ppp(devfd); + if (doing_multilink) + mp_exit_bundle(); + fd_ppp = -1; + } + if (!hungup) + lcp_lowerdown(pcb); + if (!doing_multilink && !demand) + script_unsetenv("IFNAME"); + + /* + * Run disconnector script, if requested. + * XXX we may not be able to do this if the line has hung up! + */ + if (devfd >= 0 && the_channel->disconnect) { + the_channel->disconnect(); + devfd = -1; + } + if (the_channel->cleanup) + (*the_channel->cleanup)(); + + if (doing_multilink && multilink_master) { + if (!bundle_terminating) + new_phase(pcb, PPP_PHASE_MASTER); + else + mp_bundle_terminated(); + } else + new_phase(pcb, PPP_PHASE_DEAD); +#endif +} + +/* + * LCP has gone down; it will either die or try to re-establish. + */ +void link_down(ppp_pcb *pcb) { +#if PPP_NOTIFY + notify(link_down_notifier, 0); +#endif /* PPP_NOTIFY */ + + if (!doing_multilink) { + upper_layers_down(pcb); + if (pcb->phase != PPP_PHASE_DEAD +#ifdef HAVE_MULTILINK + && pcb->phase != PPP_PHASE_MASTER +#endif /* HAVE_MULTILINK */ + ) + new_phase(pcb, PPP_PHASE_ESTABLISH); + } + /* XXX if doing_multilink, should do something to stop + network-layer traffic on the link */ +} + +void upper_layers_down(ppp_pcb *pcb) { + int i; + const struct protent *protp; + + for (i = 0; (protp = protocols[i]) != NULL; ++i) { + if (protp->protocol != PPP_LCP && protp->lowerdown != NULL) + (*protp->lowerdown)(pcb); + if (protp->protocol < 0xC000 && protp->close != NULL) + (*protp->close)(pcb, "LCP down"); + } + pcb->num_np_open = 0; + pcb->num_np_up = 0; +} + +/* + * The link is established. + * Proceed to the Dead, Authenticate or Network phase as appropriate. + */ +void link_established(ppp_pcb *pcb) { +#if PPP_AUTH_SUPPORT + int auth; +#if PPP_SERVER +#if PAP_SUPPORT + lcp_options *wo = &pcb->lcp_wantoptions; +#endif /* PAP_SUPPORT */ + lcp_options *go = &pcb->lcp_gotoptions; +#endif /* PPP_SERVER */ + lcp_options *ho = &pcb->lcp_hisoptions; +#endif /* PPP_AUTH_SUPPORT */ + int i; + const struct protent *protp; + + /* + * Tell higher-level protocols that LCP is up. + */ + if (!doing_multilink) { + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (protp->protocol != PPP_LCP + && protp->lowerup != NULL) + (*protp->lowerup)(pcb); + } + +#if PPP_AUTH_SUPPORT +#if PPP_SERVER +#if PPP_ALLOWED_ADDRS + if (!auth_required && noauth_addrs != NULL) + set_allowed_addrs(unit, NULL, NULL); +#endif /* PPP_ALLOWED_ADDRS */ + + if (pcb->settings.auth_required && !(0 +#if PAP_SUPPORT + || go->neg_upap +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + || go->neg_chap +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + || go->neg_eap +#endif /* EAP_SUPPORT */ + )) { + +#if PPP_ALLOWED_ADDRS + /* + * We wanted the peer to authenticate itself, and it refused: + * if we have some address(es) it can use without auth, fine, + * otherwise treat it as though it authenticated with PAP using + * a username of "" and a password of "". If that's not OK, + * boot it out. + */ + if (noauth_addrs != NULL) { + set_allowed_addrs(unit, NULL, NULL); + } else +#endif /* PPP_ALLOWED_ADDRS */ + if (!pcb->settings.null_login +#if PAP_SUPPORT + || !wo->neg_upap +#endif /* PAP_SUPPORT */ + ) { + ppp_warn("peer refused to authenticate: terminating link"); +#if 0 /* UNUSED */ + status = EXIT_PEER_AUTH_FAILED; +#endif /* UNUSED */ + pcb->err_code = PPPERR_AUTHFAIL; + lcp_close(pcb, "peer refused to authenticate"); + return; + } + } +#endif /* PPP_SERVER */ + + new_phase(pcb, PPP_PHASE_AUTHENTICATE); + auth = 0; +#if PPP_SERVER +#if EAP_SUPPORT + if (go->neg_eap) { + eap_authpeer(pcb, PPP_OUR_NAME); + auth |= EAP_PEER; + } else +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT + if (go->neg_chap) { + chap_auth_peer(pcb, PPP_OUR_NAME, CHAP_DIGEST(go->chap_mdtype)); + auth |= CHAP_PEER; + } else +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + if (go->neg_upap) { + upap_authpeer(pcb); + auth |= PAP_PEER; + } else +#endif /* PAP_SUPPORT */ + {} +#endif /* PPP_SERVER */ + +#if EAP_SUPPORT + if (ho->neg_eap) { + eap_authwithpeer(pcb, pcb->settings.user); + auth |= EAP_WITHPEER; + } else +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT + if (ho->neg_chap) { + chap_auth_with_peer(pcb, pcb->settings.user, CHAP_DIGEST(ho->chap_mdtype)); + auth |= CHAP_WITHPEER; + } else +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + if (ho->neg_upap) { + upap_authwithpeer(pcb, pcb->settings.user, pcb->settings.passwd); + auth |= PAP_WITHPEER; + } else +#endif /* PAP_SUPPORT */ + {} + + pcb->auth_pending = auth; + pcb->auth_done = 0; + + if (!auth) +#endif /* PPP_AUTH_SUPPORT */ + network_phase(pcb); +} + +/* + * Proceed to the network phase. + */ +static void network_phase(ppp_pcb *pcb) { +#if CBCP_SUPPORT + ppp_pcb *pcb = &ppp_pcb_list[unit]; +#endif +#if 0 /* UNUSED */ + lcp_options *go = &lcp_gotoptions[unit]; +#endif /* UNUSED */ + +#if 0 /* UNUSED */ + /* Log calling number. */ + if (*remote_number) + ppp_notice("peer from calling number %q authorized", remote_number); +#endif /* UNUSED */ + +#if PPP_NOTIFY + /* + * If the peer had to authenticate, notify it now. + */ + if (0 +#if CHAP_SUPPORT + || go->neg_chap +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + || go->neg_upap +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + || go->neg_eap +#endif /* EAP_SUPPORT */ + ) { + notify(auth_up_notifier, 0); + } +#endif /* PPP_NOTIFY */ + +#if CBCP_SUPPORT + /* + * If we negotiated callback, do it now. + */ + if (go->neg_cbcp) { + new_phase(pcb, PPP_PHASE_CALLBACK); + (*cbcp_protent.open)(pcb); + return; + } +#endif + +#if PPP_OPTIONS + /* + * Process extra options from the secrets file + */ + if (extra_options) { + options_from_list(extra_options, 1); + free_wordlist(extra_options); + extra_options = 0; + } +#endif /* PPP_OPTIONS */ + start_networks(pcb); +} + +void start_networks(ppp_pcb *pcb) { +#if CCP_SUPPORT || ECP_SUPPORT + int i; + const struct protent *protp; +#endif /* CCP_SUPPORT || ECP_SUPPORT */ + + new_phase(pcb, PPP_PHASE_NETWORK); + +#ifdef HAVE_MULTILINK + if (multilink) { + if (mp_join_bundle()) { + if (multilink_join_hook) + (*multilink_join_hook)(); + if (updetach && !nodetach) + detach(); + return; + } + } +#endif /* HAVE_MULTILINK */ + +#ifdef PPP_FILTER + if (!demand) + set_filters(&pass_filter, &active_filter); +#endif +#if CCP_SUPPORT || ECP_SUPPORT + /* Start CCP and ECP */ + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if ( + (0 +#if ECP_SUPPORT + || protp->protocol == PPP_ECP +#endif /* ECP_SUPPORT */ +#if CCP_SUPPORT + || protp->protocol == PPP_CCP +#endif /* CCP_SUPPORT */ + ) + && protp->open != NULL) + (*protp->open)(pcb); +#endif /* CCP_SUPPORT || ECP_SUPPORT */ + + /* + * Bring up other network protocols iff encryption is not required. + */ + if (1 +#if ECP_SUPPORT + && !ecp_gotoptions[unit].required +#endif /* ECP_SUPPORT */ +#if MPPE_SUPPORT + && !pcb->ccp_gotoptions.mppe +#endif /* MPPE_SUPPORT */ + ) + continue_networks(pcb); +} + +void continue_networks(ppp_pcb *pcb) { + int i; + const struct protent *protp; + + /* + * Start the "real" network protocols. + */ + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (protp->protocol < 0xC000 +#if CCP_SUPPORT + && protp->protocol != PPP_CCP +#endif /* CCP_SUPPORT */ +#if ECP_SUPPORT + && protp->protocol != PPP_ECP +#endif /* ECP_SUPPORT */ + && protp->open != NULL) { + (*protp->open)(pcb); + ++pcb->num_np_open; + } + + if (pcb->num_np_open == 0) + /* nothing to do */ + lcp_close(pcb, "No network protocols running"); +} + +#if PPP_AUTH_SUPPORT +#if PPP_SERVER +/* + * auth_check_passwd - Check the user name and passwd against configuration. + * + * returns: + * 0: Authentication failed. + * 1: Authentication succeeded. + * In either case, msg points to an appropriate message and msglen to the message len. + */ +int auth_check_passwd(ppp_pcb *pcb, char *auser, int userlen, char *apasswd, int passwdlen, const char **msg, int *msglen) { + int secretuserlen; + int secretpasswdlen; + + if (pcb->settings.user && pcb->settings.passwd) { + secretuserlen = (int)strlen(pcb->settings.user); + secretpasswdlen = (int)strlen(pcb->settings.passwd); + if (secretuserlen == userlen + && secretpasswdlen == passwdlen + && !memcmp(auser, pcb->settings.user, userlen) + && !memcmp(apasswd, pcb->settings.passwd, passwdlen) ) { + *msg = "Login ok"; + *msglen = sizeof("Login ok")-1; + return 1; + } + } + + *msg = "Login incorrect"; + *msglen = sizeof("Login incorrect")-1; + return 0; +} + +/* + * The peer has failed to authenticate himself using `protocol'. + */ +void auth_peer_fail(ppp_pcb *pcb, int protocol) { + LWIP_UNUSED_ARG(protocol); + /* + * Authentication failure: take the link down + */ +#if 0 /* UNUSED */ + status = EXIT_PEER_AUTH_FAILED; +#endif /* UNUSED */ + pcb->err_code = PPPERR_AUTHFAIL; + lcp_close(pcb, "Authentication failed"); +} + +/* + * The peer has been successfully authenticated using `protocol'. + */ +void auth_peer_success(ppp_pcb *pcb, int protocol, int prot_flavor, const char *name, int namelen) { + int bit; +#ifndef HAVE_MULTILINK + LWIP_UNUSED_ARG(name); + LWIP_UNUSED_ARG(namelen); +#endif /* HAVE_MULTILINK */ + + switch (protocol) { +#if CHAP_SUPPORT + case PPP_CHAP: + bit = CHAP_PEER; + switch (prot_flavor) { + case CHAP_MD5: + bit |= CHAP_MD5_PEER; + break; +#if MSCHAP_SUPPORT + case CHAP_MICROSOFT: + bit |= CHAP_MS_PEER; + break; + case CHAP_MICROSOFT_V2: + bit |= CHAP_MS2_PEER; + break; +#endif /* MSCHAP_SUPPORT */ + default: + break; + } + break; +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + case PPP_PAP: + bit = PAP_PEER; + break; +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + case PPP_EAP: + bit = EAP_PEER; + break; +#endif /* EAP_SUPPORT */ + default: + ppp_warn("auth_peer_success: unknown protocol %x", protocol); + return; + } + +#ifdef HAVE_MULTILINK + /* + * Save the authenticated name of the peer for later. + */ + if (namelen > (int)sizeof(pcb->peer_authname) - 1) + namelen = (int)sizeof(pcb->peer_authname) - 1; + MEMCPY(pcb->peer_authname, name, namelen); + pcb->peer_authname[namelen] = 0; +#endif /* HAVE_MULTILINK */ +#if 0 /* UNUSED */ + script_setenv("PEERNAME", , 0); +#endif /* UNUSED */ + + /* Save the authentication method for later. */ + pcb->auth_done |= bit; + + /* + * If there is no more authentication still to be done, + * proceed to the network (or callback) phase. + */ + if ((pcb->auth_pending &= ~bit) == 0) + network_phase(pcb); +} +#endif /* PPP_SERVER */ + +/* + * We have failed to authenticate ourselves to the peer using `protocol'. + */ +void auth_withpeer_fail(ppp_pcb *pcb, int protocol) { + LWIP_UNUSED_ARG(protocol); + /* + * We've failed to authenticate ourselves to our peer. + * + * Some servers keep sending CHAP challenges, but there + * is no point in persisting without any way to get updated + * authentication secrets. + * + * He'll probably take the link down, and there's not much + * we can do except wait for that. + */ + pcb->err_code = PPPERR_AUTHFAIL; + lcp_close(pcb, "Failed to authenticate ourselves to peer"); +} + +/* + * We have successfully authenticated ourselves with the peer using `protocol'. + */ +void auth_withpeer_success(ppp_pcb *pcb, int protocol, int prot_flavor) { + int bit; + const char *prot = ""; + + switch (protocol) { +#if CHAP_SUPPORT + case PPP_CHAP: + bit = CHAP_WITHPEER; + prot = "CHAP"; + switch (prot_flavor) { + case CHAP_MD5: + bit |= CHAP_MD5_WITHPEER; + break; +#if MSCHAP_SUPPORT + case CHAP_MICROSOFT: + bit |= CHAP_MS_WITHPEER; + break; + case CHAP_MICROSOFT_V2: + bit |= CHAP_MS2_WITHPEER; + break; +#endif /* MSCHAP_SUPPORT */ + default: + break; + } + break; +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + case PPP_PAP: + bit = PAP_WITHPEER; + prot = "PAP"; + break; +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + case PPP_EAP: + bit = EAP_WITHPEER; + prot = "EAP"; + break; +#endif /* EAP_SUPPORT */ + default: + ppp_warn("auth_withpeer_success: unknown protocol %x", protocol); + bit = 0; + /* no break */ + } + + ppp_notice("%s authentication succeeded", prot); + + /* Save the authentication method for later. */ + pcb->auth_done |= bit; + + /* + * If there is no more authentication still being done, + * proceed to the network (or callback) phase. + */ + if ((pcb->auth_pending &= ~bit) == 0) + network_phase(pcb); +} +#endif /* PPP_AUTH_SUPPORT */ + + +/* + * np_up - a network protocol has come up. + */ +void np_up(ppp_pcb *pcb, int proto) { +#if PPP_IDLETIMELIMIT + int tlim; +#endif /* PPP_IDLETIMELIMIT */ + LWIP_UNUSED_ARG(proto); + + if (pcb->num_np_up == 0) { + /* + * At this point we consider that the link has come up successfully. + */ + new_phase(pcb, PPP_PHASE_RUNNING); + +#if PPP_IDLETIMELIMIT +#if 0 /* UNUSED */ + if (idle_time_hook != 0) + tlim = (*idle_time_hook)(NULL); + else +#endif /* UNUSED */ + tlim = pcb->settings.idle_time_limit; + if (tlim > 0) + TIMEOUT(check_idle, (void*)pcb, tlim); +#endif /* PPP_IDLETIMELIMIT */ + +#if PPP_MAXCONNECT + /* + * Set a timeout to close the connection once the maximum + * connect time has expired. + */ + if (pcb->settings.maxconnect > 0) + TIMEOUT(connect_time_expired, (void*)pcb, pcb->settings.maxconnect); +#endif /* PPP_MAXCONNECT */ + +#ifdef MAXOCTETS + if (maxoctets > 0) + TIMEOUT(check_maxoctets, NULL, maxoctets_timeout); +#endif + +#if 0 /* Unused */ + /* + * Detach now, if the updetach option was given. + */ + if (updetach && !nodetach) + detach(); +#endif /* Unused */ + } + ++pcb->num_np_up; +} + +/* + * np_down - a network protocol has gone down. + */ +void np_down(ppp_pcb *pcb, int proto) { + LWIP_UNUSED_ARG(proto); + if (--pcb->num_np_up == 0) { +#if PPP_IDLETIMELIMIT + UNTIMEOUT(check_idle, (void*)pcb); +#endif /* PPP_IDLETIMELIMIT */ +#if PPP_MAXCONNECT + UNTIMEOUT(connect_time_expired, NULL); +#endif /* PPP_MAXCONNECT */ +#ifdef MAXOCTETS + UNTIMEOUT(check_maxoctets, NULL); +#endif + new_phase(pcb, PPP_PHASE_NETWORK); + } +} + +/* + * np_finished - a network protocol has finished using the link. + */ +void np_finished(ppp_pcb *pcb, int proto) { + LWIP_UNUSED_ARG(proto); + if (--pcb->num_np_open <= 0) { + /* no further use for the link: shut up shop. */ + lcp_close(pcb, "No network protocols running"); + } +} + +#ifdef MAXOCTETS +static void +check_maxoctets(arg) + void *arg; +{ +#if PPP_STATS_SUPPORT + unsigned int used; + + update_link_stats(ifunit); + link_stats_valid=0; + + switch(maxoctets_dir) { + case PPP_OCTETS_DIRECTION_IN: + used = link_stats.bytes_in; + break; + case PPP_OCTETS_DIRECTION_OUT: + used = link_stats.bytes_out; + break; + case PPP_OCTETS_DIRECTION_MAXOVERAL: + case PPP_OCTETS_DIRECTION_MAXSESSION: + used = (link_stats.bytes_in > link_stats.bytes_out) ? link_stats.bytes_in : link_stats.bytes_out; + break; + default: + used = link_stats.bytes_in+link_stats.bytes_out; + break; + } + if (used > maxoctets) { + ppp_notice("Traffic limit reached. Limit: %u Used: %u", maxoctets, used); + status = EXIT_TRAFFIC_LIMIT; + lcp_close(pcb, "Traffic limit"); +#if 0 /* UNUSED */ + need_holdoff = 0; +#endif /* UNUSED */ + } else { + TIMEOUT(check_maxoctets, NULL, maxoctets_timeout); + } +#endif /* PPP_STATS_SUPPORT */ +} +#endif /* MAXOCTETS */ + +#if PPP_IDLETIMELIMIT +/* + * check_idle - check whether the link has been idle for long + * enough that we can shut it down. + */ +static void check_idle(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + struct ppp_idle idle; + time_t itime; + int tlim; + + if (!get_idle_time(pcb, &idle)) + return; +#if 0 /* UNUSED */ + if (idle_time_hook != 0) { + tlim = idle_time_hook(&idle); + } else { +#endif /* UNUSED */ + itime = LWIP_MIN(idle.xmit_idle, idle.recv_idle); + tlim = pcb->settings.idle_time_limit - itime; +#if 0 /* UNUSED */ + } +#endif /* UNUSED */ + if (tlim <= 0) { + /* link is idle: shut it down. */ + ppp_notice("Terminating connection due to lack of activity."); + pcb->err_code = PPPERR_IDLETIMEOUT; + lcp_close(pcb, "Link inactive"); +#if 0 /* UNUSED */ + need_holdoff = 0; +#endif /* UNUSED */ + } else { + TIMEOUT(check_idle, (void*)pcb, tlim); + } +} +#endif /* PPP_IDLETIMELIMIT */ + +#if PPP_MAXCONNECT +/* + * connect_time_expired - log a message and close the connection. + */ +static void connect_time_expired(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + ppp_info("Connect time expired"); + pcb->err_code = PPPERR_CONNECTTIME; + lcp_close(pcb, "Connect time expired"); /* Close connection */ +} +#endif /* PPP_MAXCONNECT */ + +#if PPP_OPTIONS +/* + * auth_check_options - called to check authentication options. + */ +void +auth_check_options() +{ + lcp_options *wo = &lcp_wantoptions[0]; + int can_auth; + int lacks_ip; + + /* Default our_name to hostname, and user to our_name */ + if (our_name[0] == 0 || usehostname) + strlcpy(our_name, hostname, sizeof(our_name)); + /* If a blank username was explicitly given as an option, trust + the user and don't use our_name */ + if (ppp_settings.user[0] == 0 && !explicit_user) + strlcpy(ppp_settings.user, our_name, sizeof(ppp_settings.user)); + + /* + * If we have a default route, require the peer to authenticate + * unless the noauth option was given or the real user is root. + */ + if (!auth_required && !allow_any_ip && have_route_to(0) && !privileged) { + auth_required = 1; + default_auth = 1; + } + +#if CHAP_SUPPORT + /* If we selected any CHAP flavors, we should probably negotiate it. :-) */ + if (wo->chap_mdtype) + wo->neg_chap = 1; +#endif /* CHAP_SUPPORT */ + + /* If authentication is required, ask peer for CHAP, PAP, or EAP. */ + if (auth_required) { + allow_any_ip = 0; + if (1 +#if CHAP_SUPPORT + && !wo->neg_chap +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + && !wo->neg_upap +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + && !wo->neg_eap +#endif /* EAP_SUPPORT */ + ) { +#if CHAP_SUPPORT + wo->neg_chap = CHAP_MDTYPE_SUPPORTED != MDTYPE_NONE; + wo->chap_mdtype = CHAP_MDTYPE_SUPPORTED; +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + wo->neg_upap = 1; +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + wo->neg_eap = 1; +#endif /* EAP_SUPPORT */ + } + } else { +#if CHAP_SUPPORT + wo->neg_chap = 0; + wo->chap_mdtype = MDTYPE_NONE; +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + wo->neg_upap = 0; +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + wo->neg_eap = 0; +#endif /* EAP_SUPPORT */ + } + + /* + * Check whether we have appropriate secrets to use + * to authenticate the peer. Note that EAP can authenticate by way + * of a CHAP-like exchanges as well as SRP. + */ + lacks_ip = 0; +#if PAP_SUPPORT + can_auth = wo->neg_upap && (uselogin || have_pap_secret(&lacks_ip)); +#else + can_auth = 0; +#endif /* PAP_SUPPORT */ + if (!can_auth && (0 +#if CHAP_SUPPORT + || wo->neg_chap +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + || wo->neg_eap +#endif /* EAP_SUPPORT */ + )) { +#if CHAP_SUPPORT + can_auth = have_chap_secret((explicit_remote? remote_name: NULL), + our_name, 1, &lacks_ip); +#else + can_auth = 0; +#endif + } + if (!can_auth +#if EAP_SUPPORT + && wo->neg_eap +#endif /* EAP_SUPPORT */ + ) { + can_auth = have_srp_secret((explicit_remote? remote_name: NULL), + our_name, 1, &lacks_ip); + } + + if (auth_required && !can_auth && noauth_addrs == NULL) { + if (default_auth) { + option_error( +"By default the remote system is required to authenticate itself"); + option_error( +"(because this system has a default route to the internet)"); + } else if (explicit_remote) + option_error( +"The remote system (%s) is required to authenticate itself", + remote_name); + else + option_error( +"The remote system is required to authenticate itself"); + option_error( +"but I couldn't find any suitable secret (password) for it to use to do so."); + if (lacks_ip) + option_error( +"(None of the available passwords would let it use an IP address.)"); + + exit(1); + } + + /* + * Early check for remote number authorization. + */ + if (!auth_number()) { + ppp_warn("calling number %q is not authorized", remote_number); + exit(EXIT_CNID_AUTH_FAILED); + } +} +#endif /* PPP_OPTIONS */ + +#if 0 /* UNUSED */ +/* + * auth_reset - called when LCP is starting negotiations to recheck + * authentication options, i.e. whether we have appropriate secrets + * to use for authenticating ourselves and/or the peer. + */ +void +auth_reset(unit) + int unit; +{ + lcp_options *go = &lcp_gotoptions[unit]; + lcp_options *ao = &lcp_allowoptions[unit]; + int hadchap; + + hadchap = -1; + ao->neg_upap = !refuse_pap && (passwd[0] != 0 || get_pap_passwd(NULL)); + ao->neg_chap = (!refuse_chap || !refuse_mschap || !refuse_mschap_v2) + && (passwd[0] != 0 || + (hadchap = have_chap_secret(user, (explicit_remote? remote_name: + NULL), 0, NULL))); + ao->neg_eap = !refuse_eap && ( + passwd[0] != 0 || + (hadchap == 1 || (hadchap == -1 && have_chap_secret(user, + (explicit_remote? remote_name: NULL), 0, NULL))) || + have_srp_secret(user, (explicit_remote? remote_name: NULL), 0, NULL)); + + hadchap = -1; + if (go->neg_upap && !uselogin && !have_pap_secret(NULL)) + go->neg_upap = 0; + if (go->neg_chap) { + if (!(hadchap = have_chap_secret((explicit_remote? remote_name: NULL), + our_name, 1, NULL))) + go->neg_chap = 0; + } + if (go->neg_eap && + (hadchap == 0 || (hadchap == -1 && + !have_chap_secret((explicit_remote? remote_name: NULL), our_name, + 1, NULL))) && + !have_srp_secret((explicit_remote? remote_name: NULL), our_name, 1, + NULL)) + go->neg_eap = 0; +} + +/* + * check_passwd - Check the user name and passwd against the PAP secrets + * file. If requested, also check against the system password database, + * and login the user if OK. + * + * returns: + * UPAP_AUTHNAK: Authentication failed. + * UPAP_AUTHACK: Authentication succeeded. + * In either case, msg points to an appropriate message. + */ +int +check_passwd(unit, auser, userlen, apasswd, passwdlen, msg) + int unit; + char *auser; + int userlen; + char *apasswd; + int passwdlen; + char **msg; +{ + return UPAP_AUTHNAK; + int ret; + char *filename; + FILE *f; + struct wordlist *addrs = NULL, *opts = NULL; + char passwd[256], user[256]; + char secret[MAXWORDLEN]; + static int attempts = 0; + + /* + * Make copies of apasswd and auser, then null-terminate them. + * If there are unprintable characters in the password, make + * them visible. + */ + slprintf(ppp_settings.passwd, sizeof(ppp_settings.passwd), "%.*v", passwdlen, apasswd); + slprintf(ppp_settings.user, sizeof(ppp_settings.user), "%.*v", userlen, auser); + *msg = ""; + + /* + * Check if a plugin wants to handle this. + */ + if (pap_auth_hook) { + ret = (*pap_auth_hook)(ppp_settings.user, ppp_settings.passwd, msg, &addrs, &opts); + if (ret >= 0) { + /* note: set_allowed_addrs() saves opts (but not addrs): + don't free it! */ + if (ret) + set_allowed_addrs(unit, addrs, opts); + else if (opts != 0) + free_wordlist(opts); + if (addrs != 0) + free_wordlist(addrs); + BZERO(ppp_settings.passwd, sizeof(ppp_settings.passwd)); + return ret? UPAP_AUTHACK: UPAP_AUTHNAK; + } + } + + /* + * Open the file of pap secrets and scan for a suitable secret + * for authenticating this user. + */ + filename = _PATH_UPAPFILE; + addrs = opts = NULL; + ret = UPAP_AUTHNAK; + f = fopen(filename, "r"); + if (f == NULL) { + ppp_error("Can't open PAP password file %s: %m", filename); + + } else { + check_access(f, filename); + if (scan_authfile(f, ppp_settings.user, our_name, secret, &addrs, &opts, filename, 0) < 0) { + ppp_warn("no PAP secret found for %s", user); + } else { + /* + * If the secret is "@login", it means to check + * the password against the login database. + */ + int login_secret = strcmp(secret, "@login") == 0; + ret = UPAP_AUTHACK; + if (uselogin || login_secret) { + /* login option or secret is @login */ + if (session_full(ppp_settings.user, ppp_settings.passwd, devnam, msg) == 0) { + ret = UPAP_AUTHNAK; + } + } else if (session_mgmt) { + if (session_check(ppp_settings.user, NULL, devnam, NULL) == 0) { + ppp_warn("Peer %q failed PAP Session verification", user); + ret = UPAP_AUTHNAK; + } + } + if (secret[0] != 0 && !login_secret) { + /* password given in pap-secrets - must match */ + if ((cryptpap || strcmp(ppp_settings.passwd, secret) != 0) + && strcmp(crypt(ppp_settings.passwd, secret), secret) != 0) + ret = UPAP_AUTHNAK; + } + } + fclose(f); + } + + if (ret == UPAP_AUTHNAK) { + if (**msg == 0) + *msg = "Login incorrect"; + /* + * XXX can we ever get here more than once?? + * Frustrate passwd stealer programs. + * Allow 10 tries, but start backing off after 3 (stolen from login). + * On 10'th, drop the connection. + */ + if (attempts++ >= 10) { + ppp_warn("%d LOGIN FAILURES ON %s, %s", attempts, devnam, user); + lcp_close(pcb, "login failed"); + } + if (attempts > 3) + sleep((u_int) (attempts - 3) * 5); + if (opts != NULL) + free_wordlist(opts); + + } else { + attempts = 0; /* Reset count */ + if (**msg == 0) + *msg = "Login ok"; + set_allowed_addrs(unit, addrs, opts); + } + + if (addrs != NULL) + free_wordlist(addrs); + BZERO(ppp_settings.passwd, sizeof(ppp_settings.passwd)); + BZERO(secret, sizeof(secret)); + + return ret; +} + +/* + * null_login - Check if a username of "" and a password of "" are + * acceptable, and iff so, set the list of acceptable IP addresses + * and return 1. + */ +static int +null_login(unit) + int unit; +{ + char *filename; + FILE *f; + int i, ret; + struct wordlist *addrs, *opts; + char secret[MAXWORDLEN]; + + /* + * Check if a plugin wants to handle this. + */ + ret = -1; + if (null_auth_hook) + ret = (*null_auth_hook)(&addrs, &opts); + + /* + * Open the file of pap secrets and scan for a suitable secret. + */ + if (ret <= 0) { + filename = _PATH_UPAPFILE; + addrs = NULL; + f = fopen(filename, "r"); + if (f == NULL) + return 0; + check_access(f, filename); + + i = scan_authfile(f, "", our_name, secret, &addrs, &opts, filename, 0); + ret = i >= 0 && secret[0] == 0; + BZERO(secret, sizeof(secret)); + fclose(f); + } + + if (ret) + set_allowed_addrs(unit, addrs, opts); + else if (opts != 0) + free_wordlist(opts); + if (addrs != 0) + free_wordlist(addrs); + + return ret; +} + +/* + * get_pap_passwd - get a password for authenticating ourselves with + * our peer using PAP. Returns 1 on success, 0 if no suitable password + * could be found. + * Assumes passwd points to MAXSECRETLEN bytes of space (if non-null). + */ +static int +get_pap_passwd(passwd) + char *passwd; +{ + char *filename; + FILE *f; + int ret; + char secret[MAXWORDLEN]; + + /* + * Check whether a plugin wants to supply this. + */ + if (pap_passwd_hook) { + ret = (*pap_passwd_hook)(ppp_settings,user, ppp_settings.passwd); + if (ret >= 0) + return ret; + } + + filename = _PATH_UPAPFILE; + f = fopen(filename, "r"); + if (f == NULL) + return 0; + check_access(f, filename); + ret = scan_authfile(f, user, + (remote_name[0]? remote_name: NULL), + secret, NULL, NULL, filename, 0); + fclose(f); + if (ret < 0) + return 0; + if (passwd != NULL) + strlcpy(passwd, secret, MAXSECRETLEN); + BZERO(secret, sizeof(secret)); + return 1; +} + +/* + * have_pap_secret - check whether we have a PAP file with any + * secrets that we could possibly use for authenticating the peer. + */ +static int +have_pap_secret(lacks_ipp) + int *lacks_ipp; +{ + FILE *f; + int ret; + char *filename; + struct wordlist *addrs; + + /* let the plugin decide, if there is one */ + if (pap_check_hook) { + ret = (*pap_check_hook)(); + if (ret >= 0) + return ret; + } + + filename = _PATH_UPAPFILE; + f = fopen(filename, "r"); + if (f == NULL) + return 0; + + ret = scan_authfile(f, (explicit_remote? remote_name: NULL), our_name, + NULL, &addrs, NULL, filename, 0); + fclose(f); + if (ret >= 0 && !some_ip_ok(addrs)) { + if (lacks_ipp != 0) + *lacks_ipp = 1; + ret = -1; + } + if (addrs != 0) + free_wordlist(addrs); + + return ret >= 0; +} + +/* + * have_chap_secret - check whether we have a CHAP file with a + * secret that we could possibly use for authenticating `client' + * on `server'. Either can be the null string, meaning we don't + * know the identity yet. + */ +static int +have_chap_secret(client, server, need_ip, lacks_ipp) + char *client; + char *server; + int need_ip; + int *lacks_ipp; +{ + FILE *f; + int ret; + char *filename; + struct wordlist *addrs; + + if (chap_check_hook) { + ret = (*chap_check_hook)(); + if (ret >= 0) { + return ret; + } + } + + filename = _PATH_CHAPFILE; + f = fopen(filename, "r"); + if (f == NULL) + return 0; + + if (client != NULL && client[0] == 0) + client = NULL; + else if (server != NULL && server[0] == 0) + server = NULL; + + ret = scan_authfile(f, client, server, NULL, &addrs, NULL, filename, 0); + fclose(f); + if (ret >= 0 && need_ip && !some_ip_ok(addrs)) { + if (lacks_ipp != 0) + *lacks_ipp = 1; + ret = -1; + } + if (addrs != 0) + free_wordlist(addrs); + + return ret >= 0; +} + +/* + * have_srp_secret - check whether we have a SRP file with a + * secret that we could possibly use for authenticating `client' + * on `server'. Either can be the null string, meaning we don't + * know the identity yet. + */ +static int +have_srp_secret(client, server, need_ip, lacks_ipp) + char *client; + char *server; + int need_ip; + int *lacks_ipp; +{ + FILE *f; + int ret; + char *filename; + struct wordlist *addrs; + + filename = _PATH_SRPFILE; + f = fopen(filename, "r"); + if (f == NULL) + return 0; + + if (client != NULL && client[0] == 0) + client = NULL; + else if (server != NULL && server[0] == 0) + server = NULL; + + ret = scan_authfile(f, client, server, NULL, &addrs, NULL, filename, 0); + fclose(f); + if (ret >= 0 && need_ip && !some_ip_ok(addrs)) { + if (lacks_ipp != 0) + *lacks_ipp = 1; + ret = -1; + } + if (addrs != 0) + free_wordlist(addrs); + + return ret >= 0; +} +#endif /* UNUSED */ + +#if PPP_AUTH_SUPPORT +/* + * get_secret - open the CHAP secret file and return the secret + * for authenticating the given client on the given server. + * (We could be either client or server). + */ +int get_secret(ppp_pcb *pcb, const char *client, const char *server, char *secret, int *secret_len, int am_server) { + int len; + LWIP_UNUSED_ARG(server); + LWIP_UNUSED_ARG(am_server); + + if (!client || !client[0] || !pcb->settings.user || !pcb->settings.passwd || strcmp(client, pcb->settings.user)) { + return 0; + } + + len = (int)strlen(pcb->settings.passwd); + if (len > MAXSECRETLEN) { + ppp_error("Secret for %s on %s is too long", client, server); + len = MAXSECRETLEN; + } + + MEMCPY(secret, pcb->settings.passwd, len); + *secret_len = len; + return 1; + +#if 0 /* UNUSED */ + FILE *f; + int ret, len; + char *filename; + struct wordlist *addrs, *opts; + char secbuf[MAXWORDLEN]; + struct wordlist *addrs; + addrs = NULL; + + if (!am_server && ppp_settings.passwd[0] != 0) { + strlcpy(secbuf, ppp_settings.passwd, sizeof(secbuf)); + } else if (!am_server && chap_passwd_hook) { + if ( (*chap_passwd_hook)(client, secbuf) < 0) { + ppp_error("Unable to obtain CHAP password for %s on %s from plugin", + client, server); + return 0; + } + } else { + filename = _PATH_CHAPFILE; + addrs = NULL; + secbuf[0] = 0; + + f = fopen(filename, "r"); + if (f == NULL) { + ppp_error("Can't open chap secret file %s: %m", filename); + return 0; + } + check_access(f, filename); + + ret = scan_authfile(f, client, server, secbuf, &addrs, &opts, filename, 0); + fclose(f); + if (ret < 0) + return 0; + + if (am_server) + set_allowed_addrs(unit, addrs, opts); + else if (opts != 0) + free_wordlist(opts); + if (addrs != 0) + free_wordlist(addrs); + } + + len = strlen(secbuf); + if (len > MAXSECRETLEN) { + ppp_error("Secret for %s on %s is too long", client, server); + len = MAXSECRETLEN; + } + MEMCPY(secret, secbuf, len); + BZERO(secbuf, sizeof(secbuf)); + *secret_len = len; + + return 1; +#endif /* UNUSED */ +} +#endif /* PPP_AUTH_SUPPORT */ + + +#if 0 /* UNUSED */ +/* + * get_srp_secret - open the SRP secret file and return the secret + * for authenticating the given client on the given server. + * (We could be either client or server). + */ +int +get_srp_secret(unit, client, server, secret, am_server) + int unit; + char *client; + char *server; + char *secret; + int am_server; +{ + FILE *fp; + int ret; + char *filename; + struct wordlist *addrs, *opts; + + if (!am_server && ppp_settings.passwd[0] != '\0') { + strlcpy(secret, ppp_settings.passwd, MAXWORDLEN); + } else { + filename = _PATH_SRPFILE; + addrs = NULL; + + fp = fopen(filename, "r"); + if (fp == NULL) { + ppp_error("Can't open srp secret file %s: %m", filename); + return 0; + } + check_access(fp, filename); + + secret[0] = '\0'; + ret = scan_authfile(fp, client, server, secret, &addrs, &opts, + filename, am_server); + fclose(fp); + if (ret < 0) + return 0; + + if (am_server) + set_allowed_addrs(unit, addrs, opts); + else if (opts != NULL) + free_wordlist(opts); + if (addrs != NULL) + free_wordlist(addrs); + } + + return 1; +} + +/* + * set_allowed_addrs() - set the list of allowed addresses. + * Also looks for `--' indicating options to apply for this peer + * and leaves the following words in extra_options. + */ +static void +set_allowed_addrs(unit, addrs, opts) + int unit; + struct wordlist *addrs; + struct wordlist *opts; +{ + int n; + struct wordlist *ap, **plink; + struct permitted_ip *ip; + char *ptr_word, *ptr_mask; + struct hostent *hp; + struct netent *np; + u32_t a, mask, ah, offset; + struct ipcp_options *wo = &ipcp_wantoptions[unit]; + u32_t suggested_ip = 0; + + if (addresses[unit] != NULL) + free(addresses[unit]); + addresses[unit] = NULL; + if (extra_options != NULL) + free_wordlist(extra_options); + extra_options = opts; + + /* + * Count the number of IP addresses given. + */ + n = wordlist_count(addrs) + wordlist_count(noauth_addrs); + if (n == 0) + return; + ip = (struct permitted_ip *) malloc((n + 1) * sizeof(struct permitted_ip)); + if (ip == 0) + return; + + /* temporarily append the noauth_addrs list to addrs */ + for (plink = &addrs; *plink != NULL; plink = &(*plink)->next) + ; + *plink = noauth_addrs; + + n = 0; + for (ap = addrs; ap != NULL; ap = ap->next) { + /* "-" means no addresses authorized, "*" means any address allowed */ + ptr_word = ap->word; + if (strcmp(ptr_word, "-") == 0) + break; + if (strcmp(ptr_word, "*") == 0) { + ip[n].permit = 1; + ip[n].base = ip[n].mask = 0; + ++n; + break; + } + + ip[n].permit = 1; + if (*ptr_word == '!') { + ip[n].permit = 0; + ++ptr_word; + } + + mask = ~ (u32_t) 0; + offset = 0; + ptr_mask = strchr (ptr_word, '/'); + if (ptr_mask != NULL) { + int bit_count; + char *endp; + + bit_count = (int) strtol (ptr_mask+1, &endp, 10); + if (bit_count <= 0 || bit_count > 32) { + ppp_warn("invalid address length %v in auth. address list", + ptr_mask+1); + continue; + } + bit_count = 32 - bit_count; /* # bits in host part */ + if (*endp == '+') { + offset = ifunit + 1; + ++endp; + } + if (*endp != 0) { + ppp_warn("invalid address length syntax: %v", ptr_mask+1); + continue; + } + *ptr_mask = '\0'; + mask <<= bit_count; + } + + hp = gethostbyname(ptr_word); + if (hp != NULL && hp->h_addrtype == AF_INET) { + a = *(u32_t *)hp->h_addr; + } else { + np = getnetbyname (ptr_word); + if (np != NULL && np->n_addrtype == AF_INET) { + a = lwip_htonl ((u32_t)np->n_net); + if (ptr_mask == NULL) { + /* calculate appropriate mask for net */ + ah = lwip_ntohl(a); + if (IN_CLASSA(ah)) + mask = IN_CLASSA_NET; + else if (IN_CLASSB(ah)) + mask = IN_CLASSB_NET; + else if (IN_CLASSC(ah)) + mask = IN_CLASSC_NET; + } + } else { + a = inet_addr (ptr_word); + } + } + + if (ptr_mask != NULL) + *ptr_mask = '/'; + + if (a == (u32_t)-1L) { + ppp_warn("unknown host %s in auth. address list", ap->word); + continue; + } + if (offset != 0) { + if (offset >= ~mask) { + ppp_warn("interface unit %d too large for subnet %v", + ifunit, ptr_word); + continue; + } + a = lwip_htonl((lwip_ntohl(a) & mask) + offset); + mask = ~(u32_t)0; + } + ip[n].mask = lwip_htonl(mask); + ip[n].base = a & ip[n].mask; + ++n; + if (~mask == 0 && suggested_ip == 0) + suggested_ip = a; + } + *plink = NULL; + + ip[n].permit = 0; /* make the last entry forbid all addresses */ + ip[n].base = 0; /* to terminate the list */ + ip[n].mask = 0; + + addresses[unit] = ip; + + /* + * If the address given for the peer isn't authorized, or if + * the user hasn't given one, AND there is an authorized address + * which is a single host, then use that if we find one. + */ + if (suggested_ip != 0 + && (wo->hisaddr == 0 || !auth_ip_addr(unit, wo->hisaddr))) { + wo->hisaddr = suggested_ip; + /* + * Do we insist on this address? No, if there are other + * addresses authorized than the suggested one. + */ + if (n > 1) + wo->accept_remote = 1; + } +} + +/* + * auth_ip_addr - check whether the peer is authorized to use + * a given IP address. Returns 1 if authorized, 0 otherwise. + */ +int +auth_ip_addr(unit, addr) + int unit; + u32_t addr; +{ + int ok; + + /* don't allow loopback or multicast address */ + if (bad_ip_adrs(addr)) + return 0; + + if (allowed_address_hook) { + ok = allowed_address_hook(addr); + if (ok >= 0) return ok; + } + + if (addresses[unit] != NULL) { + ok = ip_addr_check(addr, addresses[unit]); + if (ok >= 0) + return ok; + } + + if (auth_required) + return 0; /* no addresses authorized */ + return allow_any_ip || privileged || !have_route_to(addr); +} + +static int +ip_addr_check(addr, addrs) + u32_t addr; + struct permitted_ip *addrs; +{ + for (; ; ++addrs) + if ((addr & addrs->mask) == addrs->base) + return addrs->permit; +} + +/* + * bad_ip_adrs - return 1 if the IP address is one we don't want + * to use, such as an address in the loopback net or a multicast address. + * addr is in network byte order. + */ +int +bad_ip_adrs(addr) + u32_t addr; +{ + addr = lwip_ntohl(addr); + return (addr >> IN_CLASSA_NSHIFT) == IN_LOOPBACKNET + || IN_MULTICAST(addr) || IN_BADCLASS(addr); +} + +/* + * some_ip_ok - check a wordlist to see if it authorizes any + * IP address(es). + */ +static int +some_ip_ok(addrs) + struct wordlist *addrs; +{ + for (; addrs != 0; addrs = addrs->next) { + if (addrs->word[0] == '-') + break; + if (addrs->word[0] != '!') + return 1; /* some IP address is allowed */ + } + return 0; +} + +/* + * auth_number - check whether the remote number is allowed to connect. + * Returns 1 if authorized, 0 otherwise. + */ +int +auth_number() +{ + struct wordlist *wp = permitted_numbers; + int l; + + /* Allow all if no authorization list. */ + if (!wp) + return 1; + + /* Allow if we have a match in the authorization list. */ + while (wp) { + /* trailing '*' wildcard */ + l = strlen(wp->word); + if ((wp->word)[l - 1] == '*') + l--; + if (!strncasecmp(wp->word, remote_number, l)) + return 1; + wp = wp->next; + } + + return 0; +} + +/* + * check_access - complain if a secret file has too-liberal permissions. + */ +static void +check_access(f, filename) + FILE *f; + char *filename; +{ + struct stat sbuf; + + if (fstat(fileno(f), &sbuf) < 0) { + ppp_warn("cannot stat secret file %s: %m", filename); + } else if ((sbuf.st_mode & (S_IRWXG | S_IRWXO)) != 0) { + ppp_warn("Warning - secret file %s has world and/or group access", + filename); + } +} + +/* + * scan_authfile - Scan an authorization file for a secret suitable + * for authenticating `client' on `server'. The return value is -1 + * if no secret is found, otherwise >= 0. The return value has + * NONWILD_CLIENT set if the secret didn't have "*" for the client, and + * NONWILD_SERVER set if the secret didn't have "*" for the server. + * Any following words on the line up to a "--" (i.e. address authorization + * info) are placed in a wordlist and returned in *addrs. Any + * following words (extra options) are placed in a wordlist and + * returned in *opts. + * We assume secret is NULL or points to MAXWORDLEN bytes of space. + * Flags are non-zero if we need two colons in the secret in order to + * match. + */ +static int +scan_authfile(f, client, server, secret, addrs, opts, filename, flags) + FILE *f; + char *client; + char *server; + char *secret; + struct wordlist **addrs; + struct wordlist **opts; + char *filename; + int flags; +{ + int newline, xxx; + int got_flag, best_flag; + FILE *sf; + struct wordlist *ap, *addr_list, *alist, **app; + char word[MAXWORDLEN]; + char atfile[MAXWORDLEN]; + char lsecret[MAXWORDLEN]; + char *cp; + + if (addrs != NULL) + *addrs = NULL; + if (opts != NULL) + *opts = NULL; + addr_list = NULL; + if (!getword(f, word, &newline, filename)) + return -1; /* file is empty??? */ + newline = 1; + best_flag = -1; + for (;;) { + /* + * Skip until we find a word at the start of a line. + */ + while (!newline && getword(f, word, &newline, filename)) + ; + if (!newline) + break; /* got to end of file */ + + /* + * Got a client - check if it's a match or a wildcard. + */ + got_flag = 0; + if (client != NULL && strcmp(word, client) != 0 && !ISWILD(word)) { + newline = 0; + continue; + } + if (!ISWILD(word)) + got_flag = NONWILD_CLIENT; + + /* + * Now get a server and check if it matches. + */ + if (!getword(f, word, &newline, filename)) + break; + if (newline) + continue; + if (!ISWILD(word)) { + if (server != NULL && strcmp(word, server) != 0) + continue; + got_flag |= NONWILD_SERVER; + } + + /* + * Got some sort of a match - see if it's better than what + * we have already. + */ + if (got_flag <= best_flag) + continue; + + /* + * Get the secret. + */ + if (!getword(f, word, &newline, filename)) + break; + if (newline) + continue; + + /* + * SRP-SHA1 authenticator should never be reading secrets from + * a file. (Authenticatee may, though.) + */ + if (flags && ((cp = strchr(word, ':')) == NULL || + strchr(cp + 1, ':') == NULL)) + continue; + + if (secret != NULL) { + /* + * Special syntax: @/pathname means read secret from file. + */ + if (word[0] == '@' && word[1] == '/') { + strlcpy(atfile, word+1, sizeof(atfile)); + if ((sf = fopen(atfile, "r")) == NULL) { + ppp_warn("can't open indirect secret file %s", atfile); + continue; + } + check_access(sf, atfile); + if (!getword(sf, word, &xxx, atfile)) { + ppp_warn("no secret in indirect secret file %s", atfile); + fclose(sf); + continue; + } + fclose(sf); + } + strlcpy(lsecret, word, sizeof(lsecret)); + } + + /* + * Now read address authorization info and make a wordlist. + */ + app = &alist; + for (;;) { + if (!getword(f, word, &newline, filename) || newline) + break; + ap = (struct wordlist *) + malloc(sizeof(struct wordlist) + strlen(word) + 1); + if (ap == NULL) + novm("authorized addresses"); + ap->word = (char *) (ap + 1); + strcpy(ap->word, word); + *app = ap; + app = &ap->next; + } + *app = NULL; + + /* + * This is the best so far; remember it. + */ + best_flag = got_flag; + if (addr_list) + free_wordlist(addr_list); + addr_list = alist; + if (secret != NULL) + strlcpy(secret, lsecret, MAXWORDLEN); + + if (!newline) + break; + } + + /* scan for a -- word indicating the start of options */ + for (app = &addr_list; (ap = *app) != NULL; app = &ap->next) + if (strcmp(ap->word, "--") == 0) + break; + /* ap = start of options */ + if (ap != NULL) { + ap = ap->next; /* first option */ + free(*app); /* free the "--" word */ + *app = NULL; /* terminate addr list */ + } + if (opts != NULL) + *opts = ap; + else if (ap != NULL) + free_wordlist(ap); + if (addrs != NULL) + *addrs = addr_list; + else if (addr_list != NULL) + free_wordlist(addr_list); + + return best_flag; +} + +/* + * wordlist_count - return the number of items in a wordlist + */ +static int +wordlist_count(wp) + struct wordlist *wp; +{ + int n; + + for (n = 0; wp != NULL; wp = wp->next) + ++n; + return n; +} + +/* + * free_wordlist - release memory allocated for a wordlist. + */ +static void +free_wordlist(wp) + struct wordlist *wp; +{ + struct wordlist *next; + + while (wp != NULL) { + next = wp->next; + free(wp); + wp = next; + } +} +#endif /* UNUSED */ + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c new file mode 100644 index 0000000..f8519eb --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/ccp.c @@ -0,0 +1,1740 @@ +/* + * ccp.c - PPP Compression Control Protocol. + * + * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && CCP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include +#include + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/ccp.h" + +#if MPPE_SUPPORT +#include "netif/ppp/lcp.h" /* lcp_close(), lcp_fsm */ +#include "netif/ppp/mppe.h" /* mppe_init() */ +#endif /* MPPE_SUPPORT */ + +/* + * Unfortunately there is a bug in zlib which means that using a + * size of 8 (window size = 256) for Deflate compression will cause + * buffer overruns and kernel crashes in the deflate module. + * Until this is fixed we only accept sizes in the range 9 .. 15. + * Thanks to James Carlson for pointing this out. + */ +#define DEFLATE_MIN_WORKS 9 + +/* + * Command-line options. + */ +#if PPP_OPTIONS +static int setbsdcomp (char **); +static int setdeflate (char **); +static char bsd_value[8]; +static char deflate_value[8]; + +/* + * Option variables. + */ +#if MPPE_SUPPORT +bool refuse_mppe_stateful = 1; /* Allow stateful mode? */ +#endif /* MPPE_SUPPORT */ + +static option_t ccp_option_list[] = { + { "noccp", o_bool, &ccp_protent.enabled_flag, + "Disable CCP negotiation" }, + { "-ccp", o_bool, &ccp_protent.enabled_flag, + "Disable CCP negotiation", OPT_ALIAS }, + + { "bsdcomp", o_special, (void *)setbsdcomp, + "Request BSD-Compress packet compression", + OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, bsd_value }, + { "nobsdcomp", o_bool, &ccp_wantoptions[0].bsd_compress, + "don't allow BSD-Compress", OPT_PRIOSUB | OPT_A2CLR, + &ccp_allowoptions[0].bsd_compress }, + { "-bsdcomp", o_bool, &ccp_wantoptions[0].bsd_compress, + "don't allow BSD-Compress", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR, + &ccp_allowoptions[0].bsd_compress }, + + { "deflate", o_special, (void *)setdeflate, + "request Deflate compression", + OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, deflate_value }, + { "nodeflate", o_bool, &ccp_wantoptions[0].deflate, + "don't allow Deflate compression", OPT_PRIOSUB | OPT_A2CLR, + &ccp_allowoptions[0].deflate }, + { "-deflate", o_bool, &ccp_wantoptions[0].deflate, + "don't allow Deflate compression", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR, + &ccp_allowoptions[0].deflate }, + + { "nodeflatedraft", o_bool, &ccp_wantoptions[0].deflate_draft, + "don't use draft deflate #", OPT_A2COPY, + &ccp_allowoptions[0].deflate_draft }, + + { "predictor1", o_bool, &ccp_wantoptions[0].predictor_1, + "request Predictor-1", OPT_PRIO | 1 }, + { "nopredictor1", o_bool, &ccp_wantoptions[0].predictor_1, + "don't allow Predictor-1", OPT_PRIOSUB | OPT_A2CLR, + &ccp_allowoptions[0].predictor_1 }, + { "-predictor1", o_bool, &ccp_wantoptions[0].predictor_1, + "don't allow Predictor-1", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR, + &ccp_allowoptions[0].predictor_1 }, + +#if MPPE_SUPPORT + /* MPPE options are symmetrical ... we only set wantoptions here */ + { "require-mppe", o_bool, &ccp_wantoptions[0].mppe, + "require MPPE encryption", + OPT_PRIO | MPPE_OPT_40 | MPPE_OPT_128 }, + { "+mppe", o_bool, &ccp_wantoptions[0].mppe, + "require MPPE encryption", + OPT_ALIAS | OPT_PRIO | MPPE_OPT_40 | MPPE_OPT_128 }, + { "nomppe", o_bool, &ccp_wantoptions[0].mppe, + "don't allow MPPE encryption", OPT_PRIO }, + { "-mppe", o_bool, &ccp_wantoptions[0].mppe, + "don't allow MPPE encryption", OPT_ALIAS | OPT_PRIO }, + + /* We use ccp_allowoptions[0].mppe as a junk var ... it is reset later */ + { "require-mppe-40", o_bool, &ccp_allowoptions[0].mppe, + "require MPPE 40-bit encryption", OPT_PRIO | OPT_A2OR | MPPE_OPT_40, + &ccp_wantoptions[0].mppe }, + { "+mppe-40", o_bool, &ccp_allowoptions[0].mppe, + "require MPPE 40-bit encryption", OPT_PRIO | OPT_A2OR | MPPE_OPT_40, + &ccp_wantoptions[0].mppe }, + { "nomppe-40", o_bool, &ccp_allowoptions[0].mppe, + "don't allow MPPE 40-bit encryption", + OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_40, &ccp_wantoptions[0].mppe }, + { "-mppe-40", o_bool, &ccp_allowoptions[0].mppe, + "don't allow MPPE 40-bit encryption", + OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_40, + &ccp_wantoptions[0].mppe }, + + { "require-mppe-128", o_bool, &ccp_allowoptions[0].mppe, + "require MPPE 128-bit encryption", OPT_PRIO | OPT_A2OR | MPPE_OPT_128, + &ccp_wantoptions[0].mppe }, + { "+mppe-128", o_bool, &ccp_allowoptions[0].mppe, + "require MPPE 128-bit encryption", + OPT_ALIAS | OPT_PRIO | OPT_A2OR | MPPE_OPT_128, + &ccp_wantoptions[0].mppe }, + { "nomppe-128", o_bool, &ccp_allowoptions[0].mppe, + "don't allow MPPE 128-bit encryption", + OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_128, &ccp_wantoptions[0].mppe }, + { "-mppe-128", o_bool, &ccp_allowoptions[0].mppe, + "don't allow MPPE 128-bit encryption", + OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_128, + &ccp_wantoptions[0].mppe }, + + /* strange one; we always request stateless, but will we allow stateful? */ + { "mppe-stateful", o_bool, &refuse_mppe_stateful, + "allow MPPE stateful mode", OPT_PRIO }, + { "nomppe-stateful", o_bool, &refuse_mppe_stateful, + "disallow MPPE stateful mode", OPT_PRIO | 1 }, +#endif /* MPPE_SUPPORT */ + + { NULL } +}; +#endif /* PPP_OPTIONS */ + +/* + * Protocol entry points from main code. + */ +static void ccp_init(ppp_pcb *pcb); +static void ccp_open(ppp_pcb *pcb); +static void ccp_close(ppp_pcb *pcb, const char *reason); +static void ccp_lowerup(ppp_pcb *pcb); +static void ccp_lowerdown(ppp_pcb *pcb); +static void ccp_input(ppp_pcb *pcb, u_char *pkt, int len); +static void ccp_protrej(ppp_pcb *pcb); +#if PRINTPKT_SUPPORT +static int ccp_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg); +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT +static void ccp_datainput(ppp_pcb *pcb, u_char *pkt, int len); +#endif /* PPP_DATAINPUT */ + +const struct protent ccp_protent = { + PPP_CCP, + ccp_init, + ccp_input, + ccp_protrej, + ccp_lowerup, + ccp_lowerdown, + ccp_open, + ccp_close, +#if PRINTPKT_SUPPORT + ccp_printpkt, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + ccp_datainput, +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "CCP", + "Compressed", +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + ccp_option_list, + NULL, +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + NULL, + NULL +#endif /* DEMAND_SUPPORT */ +}; + +/* + * Callbacks for fsm code. + */ +static void ccp_resetci (fsm *); +static int ccp_cilen (fsm *); +static void ccp_addci (fsm *, u_char *, int *); +static int ccp_ackci (fsm *, u_char *, int); +static int ccp_nakci (fsm *, u_char *, int, int); +static int ccp_rejci (fsm *, u_char *, int); +static int ccp_reqci (fsm *, u_char *, int *, int); +static void ccp_up (fsm *); +static void ccp_down (fsm *); +static int ccp_extcode (fsm *, int, int, u_char *, int); +static void ccp_rack_timeout (void *); +static const char *method_name (ccp_options *, ccp_options *); + +static const fsm_callbacks ccp_callbacks = { + ccp_resetci, + ccp_cilen, + ccp_addci, + ccp_ackci, + ccp_nakci, + ccp_rejci, + ccp_reqci, + ccp_up, + ccp_down, + NULL, + NULL, + NULL, + NULL, + ccp_extcode, + "CCP" +}; + +/* + * Do we want / did we get any compression? + */ +static int ccp_anycompress(ccp_options *opt) { + return (0 +#if DEFLATE_SUPPORT + || (opt)->deflate +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + || (opt)->bsd_compress +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + || (opt)->predictor_1 || (opt)->predictor_2 +#endif /* PREDICTOR_SUPPORT */ +#if MPPE_SUPPORT + || (opt)->mppe +#endif /* MPPE_SUPPORT */ + ); +} + +/* + * Local state (mainly for handling reset-reqs and reset-acks). + */ +#define RACK_PENDING 1 /* waiting for reset-ack */ +#define RREQ_REPEAT 2 /* send another reset-req if no reset-ack */ + +#define RACKTIMEOUT 1 /* second */ + +#if PPP_OPTIONS +/* + * Option parsing + */ +static int +setbsdcomp(argv) + char **argv; +{ + int rbits, abits; + char *str, *endp; + + str = *argv; + abits = rbits = strtol(str, &endp, 0); + if (endp != str && *endp == ',') { + str = endp + 1; + abits = strtol(str, &endp, 0); + } + if (*endp != 0 || endp == str) { + option_error("invalid parameter '%s' for bsdcomp option", *argv); + return 0; + } + if ((rbits != 0 && (rbits < BSD_MIN_BITS || rbits > BSD_MAX_BITS)) + || (abits != 0 && (abits < BSD_MIN_BITS || abits > BSD_MAX_BITS))) { + option_error("bsdcomp option values must be 0 or %d .. %d", + BSD_MIN_BITS, BSD_MAX_BITS); + return 0; + } + if (rbits > 0) { + ccp_wantoptions[0].bsd_compress = 1; + ccp_wantoptions[0].bsd_bits = rbits; + } else + ccp_wantoptions[0].bsd_compress = 0; + if (abits > 0) { + ccp_allowoptions[0].bsd_compress = 1; + ccp_allowoptions[0].bsd_bits = abits; + } else + ccp_allowoptions[0].bsd_compress = 0; + ppp_slprintf(bsd_value, sizeof(bsd_value), + rbits == abits? "%d": "%d,%d", rbits, abits); + + return 1; +} + +static int +setdeflate(argv) + char **argv; +{ + int rbits, abits; + char *str, *endp; + + str = *argv; + abits = rbits = strtol(str, &endp, 0); + if (endp != str && *endp == ',') { + str = endp + 1; + abits = strtol(str, &endp, 0); + } + if (*endp != 0 || endp == str) { + option_error("invalid parameter '%s' for deflate option", *argv); + return 0; + } + if ((rbits != 0 && (rbits < DEFLATE_MIN_SIZE || rbits > DEFLATE_MAX_SIZE)) + || (abits != 0 && (abits < DEFLATE_MIN_SIZE + || abits > DEFLATE_MAX_SIZE))) { + option_error("deflate option values must be 0 or %d .. %d", + DEFLATE_MIN_SIZE, DEFLATE_MAX_SIZE); + return 0; + } + if (rbits == DEFLATE_MIN_SIZE || abits == DEFLATE_MIN_SIZE) { + if (rbits == DEFLATE_MIN_SIZE) + rbits = DEFLATE_MIN_WORKS; + if (abits == DEFLATE_MIN_SIZE) + abits = DEFLATE_MIN_WORKS; + warn("deflate option value of %d changed to %d to avoid zlib bug", + DEFLATE_MIN_SIZE, DEFLATE_MIN_WORKS); + } + if (rbits > 0) { + ccp_wantoptions[0].deflate = 1; + ccp_wantoptions[0].deflate_size = rbits; + } else + ccp_wantoptions[0].deflate = 0; + if (abits > 0) { + ccp_allowoptions[0].deflate = 1; + ccp_allowoptions[0].deflate_size = abits; + } else + ccp_allowoptions[0].deflate = 0; + ppp_slprintf(deflate_value, sizeof(deflate_value), + rbits == abits? "%d": "%d,%d", rbits, abits); + + return 1; +} +#endif /* PPP_OPTIONS */ + +/* + * ccp_init - initialize CCP. + */ +static void ccp_init(ppp_pcb *pcb) { + fsm *f = &pcb->ccp_fsm; + + f->pcb = pcb; + f->protocol = PPP_CCP; + f->callbacks = &ccp_callbacks; + fsm_init(f); + +#if 0 /* Not necessary, everything is cleared in ppp_new() */ + memset(wo, 0, sizeof(*wo)); + memset(go, 0, sizeof(*go)); + memset(ao, 0, sizeof(*ao)); + memset(ho, 0, sizeof(*ho)); +#endif /* 0 */ + +#if DEFLATE_SUPPORT + wo->deflate = 1; + wo->deflate_size = DEFLATE_MAX_SIZE; + wo->deflate_correct = 1; + wo->deflate_draft = 1; + ao->deflate = 1; + ao->deflate_size = DEFLATE_MAX_SIZE; + ao->deflate_correct = 1; + ao->deflate_draft = 1; +#endif /* DEFLATE_SUPPORT */ + +#if BSDCOMPRESS_SUPPORT + wo->bsd_compress = 1; + wo->bsd_bits = BSD_MAX_BITS; + ao->bsd_compress = 1; + ao->bsd_bits = BSD_MAX_BITS; +#endif /* BSDCOMPRESS_SUPPORT */ + +#if PREDICTOR_SUPPORT + ao->predictor_1 = 1; +#endif /* PREDICTOR_SUPPORT */ +} + +/* + * ccp_open - CCP is allowed to come up. + */ +static void ccp_open(ppp_pcb *pcb) { + fsm *f = &pcb->ccp_fsm; + ccp_options *go = &pcb->ccp_gotoptions; + + if (f->state != PPP_FSM_OPENED) + ccp_set(pcb, 1, 0, 0, 0); + + /* + * Find out which compressors the kernel supports before + * deciding whether to open in silent mode. + */ + ccp_resetci(f); + if (!ccp_anycompress(go)) + f->flags |= OPT_SILENT; + + fsm_open(f); +} + +/* + * ccp_close - Terminate CCP. + */ +static void ccp_close(ppp_pcb *pcb, const char *reason) { + fsm *f = &pcb->ccp_fsm; + ccp_set(pcb, 0, 0, 0, 0); + fsm_close(f, reason); +} + +/* + * ccp_lowerup - we may now transmit CCP packets. + */ +static void ccp_lowerup(ppp_pcb *pcb) { + fsm *f = &pcb->ccp_fsm; + fsm_lowerup(f); +} + +/* + * ccp_lowerdown - we may not transmit CCP packets. + */ +static void ccp_lowerdown(ppp_pcb *pcb) { + fsm *f = &pcb->ccp_fsm; + fsm_lowerdown(f); +} + +/* + * ccp_input - process a received CCP packet. + */ +static void ccp_input(ppp_pcb *pcb, u_char *p, int len) { + fsm *f = &pcb->ccp_fsm; + ccp_options *go = &pcb->ccp_gotoptions; + int oldstate; + + /* + * Check for a terminate-request so we can print a message. + */ + oldstate = f->state; + fsm_input(f, p, len); + if (oldstate == PPP_FSM_OPENED && p[0] == TERMREQ && f->state != PPP_FSM_OPENED) { + ppp_notice("Compression disabled by peer."); +#if MPPE_SUPPORT + if (go->mppe) { + ppp_error("MPPE disabled, closing LCP"); + lcp_close(pcb, "MPPE disabled by peer"); + } +#endif /* MPPE_SUPPORT */ + } + + /* + * If we get a terminate-ack and we're not asking for compression, + * close CCP. + */ + if (oldstate == PPP_FSM_REQSENT && p[0] == TERMACK + && !ccp_anycompress(go)) + ccp_close(pcb, "No compression negotiated"); +} + +/* + * Handle a CCP-specific code. + */ +static int ccp_extcode(fsm *f, int code, int id, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(len); + + switch (code) { + case CCP_RESETREQ: + if (f->state != PPP_FSM_OPENED) + break; + ccp_reset_comp(pcb); + /* send a reset-ack, which the transmitter will see and + reset its compression state. */ + fsm_sdata(f, CCP_RESETACK, id, NULL, 0); + break; + + case CCP_RESETACK: + if ((pcb->ccp_localstate & RACK_PENDING) && id == f->reqid) { + pcb->ccp_localstate &= ~(RACK_PENDING | RREQ_REPEAT); + UNTIMEOUT(ccp_rack_timeout, f); + ccp_reset_decomp(pcb); + } + break; + + default: + return 0; + } + + return 1; +} + +/* + * ccp_protrej - peer doesn't talk CCP. + */ +static void ccp_protrej(ppp_pcb *pcb) { + fsm *f = &pcb->ccp_fsm; +#if MPPE_SUPPORT + ccp_options *go = &pcb->ccp_gotoptions; +#endif /* MPPE_SUPPORT */ + + ccp_set(pcb, 0, 0, 0, 0); + fsm_lowerdown(f); + +#if MPPE_SUPPORT + if (go->mppe) { + ppp_error("MPPE required but peer negotiation failed"); + lcp_close(pcb, "MPPE required but peer negotiation failed"); + } +#endif /* MPPE_SUPPORT */ + +} + +/* + * ccp_resetci - initialize at start of negotiation. + */ +static void ccp_resetci(fsm *f) { + ppp_pcb *pcb = f->pcb; + ccp_options *go = &pcb->ccp_gotoptions; + ccp_options *wo = &pcb->ccp_wantoptions; +#if MPPE_SUPPORT + ccp_options *ao = &pcb->ccp_allowoptions; +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT + u_char opt_buf[CCP_MAX_OPTION_LENGTH]; +#endif /* DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT */ +#if DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT + int res; +#endif /* DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT */ + +#if MPPE_SUPPORT + if (pcb->settings.require_mppe) { + wo->mppe = ao->mppe = + (pcb->settings.refuse_mppe_40 ? 0 : MPPE_OPT_40) + | (pcb->settings.refuse_mppe_128 ? 0 : MPPE_OPT_128); + } +#endif /* MPPE_SUPPORT */ + + *go = *wo; + pcb->ccp_all_rejected = 0; + +#if MPPE_SUPPORT + if (go->mppe) { + int auth_mschap_bits = pcb->auth_done; + int numbits; + + /* + * Start with a basic sanity check: mschap[v2] auth must be in + * exactly one direction. RFC 3079 says that the keys are + * 'derived from the credentials of the peer that initiated the call', + * however the PPP protocol doesn't have such a concept, and pppd + * cannot get this info externally. Instead we do the best we can. + * NB: If MPPE is required, all other compression opts are invalid. + * So, we return right away if we can't do it. + */ + + /* Leave only the mschap auth bits set */ + auth_mschap_bits &= (CHAP_MS_WITHPEER | CHAP_MS_PEER | + CHAP_MS2_WITHPEER | CHAP_MS2_PEER); + /* Count the mschap auths */ + auth_mschap_bits >>= CHAP_MS_SHIFT; + numbits = 0; + do { + numbits += auth_mschap_bits & 1; + auth_mschap_bits >>= 1; + } while (auth_mschap_bits); + if (numbits > 1) { + ppp_error("MPPE required, but auth done in both directions."); + lcp_close(pcb, "MPPE required but not available"); + return; + } + if (!numbits) { + ppp_error("MPPE required, but MS-CHAP[v2] auth not performed."); + lcp_close(pcb, "MPPE required but not available"); + return; + } + + /* A plugin (eg radius) may not have obtained key material. */ + if (!pcb->mppe_keys_set) { + ppp_error("MPPE required, but keys are not available. " + "Possible plugin problem?"); + lcp_close(pcb, "MPPE required but not available"); + return; + } + + /* LM auth not supported for MPPE */ + if (pcb->auth_done & (CHAP_MS_WITHPEER | CHAP_MS_PEER)) { + /* This might be noise */ + if (go->mppe & MPPE_OPT_40) { + ppp_notice("Disabling 40-bit MPPE; MS-CHAP LM not supported"); + go->mppe &= ~MPPE_OPT_40; + wo->mppe &= ~MPPE_OPT_40; + } + } + + /* Last check: can we actually negotiate something? */ + if (!(go->mppe & (MPPE_OPT_40 | MPPE_OPT_128))) { + /* Could be misconfig, could be 40-bit disabled above. */ + ppp_error("MPPE required, but both 40-bit and 128-bit disabled."); + lcp_close(pcb, "MPPE required but not available"); + return; + } + + /* sync options */ + ao->mppe = go->mppe; + /* MPPE is not compatible with other compression types */ +#if BSDCOMPRESS_SUPPORT + ao->bsd_compress = go->bsd_compress = 0; +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + ao->predictor_1 = go->predictor_1 = 0; + ao->predictor_2 = go->predictor_2 = 0; +#endif /* PREDICTOR_SUPPORT */ +#if DEFLATE_SUPPORT + ao->deflate = go->deflate = 0; +#endif /* DEFLATE_SUPPORT */ + } +#endif /* MPPE_SUPPORT */ + + /* + * Check whether the kernel knows about the various + * compression methods we might request. + */ +#if BSDCOMPRESS_SUPPORT + /* FIXME: we don't need to test if BSD compress is available + * if BSDCOMPRESS_SUPPORT is set, it is. + */ + if (go->bsd_compress) { + opt_buf[0] = CI_BSD_COMPRESS; + opt_buf[1] = CILEN_BSD_COMPRESS; + for (;;) { + if (go->bsd_bits < BSD_MIN_BITS) { + go->bsd_compress = 0; + break; + } + opt_buf[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits); + res = ccp_test(pcb, opt_buf, CILEN_BSD_COMPRESS, 0); + if (res > 0) { + break; + } else if (res < 0) { + go->bsd_compress = 0; + break; + } + go->bsd_bits--; + } + } +#endif /* BSDCOMPRESS_SUPPORT */ +#if DEFLATE_SUPPORT + /* FIXME: we don't need to test if deflate is available + * if DEFLATE_SUPPORT is set, it is. + */ + if (go->deflate) { + if (go->deflate_correct) { + opt_buf[0] = CI_DEFLATE; + opt_buf[1] = CILEN_DEFLATE; + opt_buf[3] = DEFLATE_CHK_SEQUENCE; + for (;;) { + if (go->deflate_size < DEFLATE_MIN_WORKS) { + go->deflate_correct = 0; + break; + } + opt_buf[2] = DEFLATE_MAKE_OPT(go->deflate_size); + res = ccp_test(pcb, opt_buf, CILEN_DEFLATE, 0); + if (res > 0) { + break; + } else if (res < 0) { + go->deflate_correct = 0; + break; + } + go->deflate_size--; + } + } + if (go->deflate_draft) { + opt_buf[0] = CI_DEFLATE_DRAFT; + opt_buf[1] = CILEN_DEFLATE; + opt_buf[3] = DEFLATE_CHK_SEQUENCE; + for (;;) { + if (go->deflate_size < DEFLATE_MIN_WORKS) { + go->deflate_draft = 0; + break; + } + opt_buf[2] = DEFLATE_MAKE_OPT(go->deflate_size); + res = ccp_test(pcb, opt_buf, CILEN_DEFLATE, 0); + if (res > 0) { + break; + } else if (res < 0) { + go->deflate_draft = 0; + break; + } + go->deflate_size--; + } + } + if (!go->deflate_correct && !go->deflate_draft) + go->deflate = 0; + } +#endif /* DEFLATE_SUPPORT */ +#if PREDICTOR_SUPPORT + /* FIXME: we don't need to test if predictor is available, + * if PREDICTOR_SUPPORT is set, it is. + */ + if (go->predictor_1) { + opt_buf[0] = CI_PREDICTOR_1; + opt_buf[1] = CILEN_PREDICTOR_1; + if (ccp_test(pcb, opt_buf, CILEN_PREDICTOR_1, 0) <= 0) + go->predictor_1 = 0; + } + if (go->predictor_2) { + opt_buf[0] = CI_PREDICTOR_2; + opt_buf[1] = CILEN_PREDICTOR_2; + if (ccp_test(pcb, opt_buf, CILEN_PREDICTOR_2, 0) <= 0) + go->predictor_2 = 0; + } +#endif /* PREDICTOR_SUPPORT */ +} + +/* + * ccp_cilen - Return total length of our configuration info. + */ +static int ccp_cilen(fsm *f) { + ppp_pcb *pcb = f->pcb; + ccp_options *go = &pcb->ccp_gotoptions; + + return 0 +#if BSDCOMPRESS_SUPPORT + + (go->bsd_compress? CILEN_BSD_COMPRESS: 0) +#endif /* BSDCOMPRESS_SUPPORT */ +#if DEFLATE_SUPPORT + + (go->deflate && go->deflate_correct? CILEN_DEFLATE: 0) + + (go->deflate && go->deflate_draft? CILEN_DEFLATE: 0) +#endif /* DEFLATE_SUPPORT */ +#if PREDICTOR_SUPPORT + + (go->predictor_1? CILEN_PREDICTOR_1: 0) + + (go->predictor_2? CILEN_PREDICTOR_2: 0) +#endif /* PREDICTOR_SUPPORT */ +#if MPPE_SUPPORT + + (go->mppe? CILEN_MPPE: 0) +#endif /* MPPE_SUPPORT */ + ; +} + +/* + * ccp_addci - put our requests in a packet. + */ +static void ccp_addci(fsm *f, u_char *p, int *lenp) { + ppp_pcb *pcb = f->pcb; + ccp_options *go = &pcb->ccp_gotoptions; + u_char *p0 = p; + + /* + * Add the compression types that we can receive, in decreasing + * preference order. + */ +#if MPPE_SUPPORT + if (go->mppe) { + p[0] = CI_MPPE; + p[1] = CILEN_MPPE; + MPPE_OPTS_TO_CI(go->mppe, &p[2]); + mppe_init(pcb, &pcb->mppe_decomp, go->mppe); + p += CILEN_MPPE; + } +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT + if (go->deflate) { + if (go->deflate_correct) { + p[0] = CI_DEFLATE; + p[1] = CILEN_DEFLATE; + p[2] = DEFLATE_MAKE_OPT(go->deflate_size); + p[3] = DEFLATE_CHK_SEQUENCE; + p += CILEN_DEFLATE; + } + if (go->deflate_draft) { + p[0] = CI_DEFLATE_DRAFT; + p[1] = CILEN_DEFLATE; + p[2] = p[2 - CILEN_DEFLATE]; + p[3] = DEFLATE_CHK_SEQUENCE; + p += CILEN_DEFLATE; + } + } +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + if (go->bsd_compress) { + p[0] = CI_BSD_COMPRESS; + p[1] = CILEN_BSD_COMPRESS; + p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits); + p += CILEN_BSD_COMPRESS; + } +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + /* XXX Should Predictor 2 be preferable to Predictor 1? */ + if (go->predictor_1) { + p[0] = CI_PREDICTOR_1; + p[1] = CILEN_PREDICTOR_1; + p += CILEN_PREDICTOR_1; + } + if (go->predictor_2) { + p[0] = CI_PREDICTOR_2; + p[1] = CILEN_PREDICTOR_2; + p += CILEN_PREDICTOR_2; + } +#endif /* PREDICTOR_SUPPORT */ + + go->method = (p > p0)? p0[0]: 0; + + *lenp = p - p0; +} + +/* + * ccp_ackci - process a received configure-ack, and return + * 1 iff the packet was OK. + */ +static int ccp_ackci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + ccp_options *go = &pcb->ccp_gotoptions; +#if BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT + u_char *p0 = p; +#endif /* BSDCOMPRESS_SUPPORT || PREDICTOR_SUPPORT */ + +#if MPPE_SUPPORT + if (go->mppe) { + u_char opt_buf[CILEN_MPPE]; + + opt_buf[0] = CI_MPPE; + opt_buf[1] = CILEN_MPPE; + MPPE_OPTS_TO_CI(go->mppe, &opt_buf[2]); + if (len < CILEN_MPPE || memcmp(opt_buf, p, CILEN_MPPE)) + return 0; + p += CILEN_MPPE; + len -= CILEN_MPPE; + /* XXX Cope with first/fast ack */ + if (len == 0) + return 1; + } +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT + if (go->deflate) { + if (len < CILEN_DEFLATE + || p[0] != (go->deflate_correct? CI_DEFLATE: CI_DEFLATE_DRAFT) + || p[1] != CILEN_DEFLATE + || p[2] != DEFLATE_MAKE_OPT(go->deflate_size) + || p[3] != DEFLATE_CHK_SEQUENCE) + return 0; + p += CILEN_DEFLATE; + len -= CILEN_DEFLATE; + /* XXX Cope with first/fast ack */ + if (len == 0) + return 1; + if (go->deflate_correct && go->deflate_draft) { + if (len < CILEN_DEFLATE + || p[0] != CI_DEFLATE_DRAFT + || p[1] != CILEN_DEFLATE + || p[2] != DEFLATE_MAKE_OPT(go->deflate_size) + || p[3] != DEFLATE_CHK_SEQUENCE) + return 0; + p += CILEN_DEFLATE; + len -= CILEN_DEFLATE; + } + } +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + if (go->bsd_compress) { + if (len < CILEN_BSD_COMPRESS + || p[0] != CI_BSD_COMPRESS || p[1] != CILEN_BSD_COMPRESS + || p[2] != BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits)) + return 0; + p += CILEN_BSD_COMPRESS; + len -= CILEN_BSD_COMPRESS; + /* XXX Cope with first/fast ack */ + if (p == p0 && len == 0) + return 1; + } +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + if (go->predictor_1) { + if (len < CILEN_PREDICTOR_1 + || p[0] != CI_PREDICTOR_1 || p[1] != CILEN_PREDICTOR_1) + return 0; + p += CILEN_PREDICTOR_1; + len -= CILEN_PREDICTOR_1; + /* XXX Cope with first/fast ack */ + if (p == p0 && len == 0) + return 1; + } + if (go->predictor_2) { + if (len < CILEN_PREDICTOR_2 + || p[0] != CI_PREDICTOR_2 || p[1] != CILEN_PREDICTOR_2) + return 0; + p += CILEN_PREDICTOR_2; + len -= CILEN_PREDICTOR_2; + /* XXX Cope with first/fast ack */ + if (p == p0 && len == 0) + return 1; + } +#endif /* PREDICTOR_SUPPORT */ + + if (len != 0) + return 0; + return 1; +} + +/* + * ccp_nakci - process received configure-nak. + * Returns 1 iff the nak was OK. + */ +static int ccp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) { + ppp_pcb *pcb = f->pcb; + ccp_options *go = &pcb->ccp_gotoptions; + ccp_options no; /* options we've seen already */ + ccp_options try_; /* options to ask for next time */ + LWIP_UNUSED_ARG(treat_as_reject); +#if !MPPE_SUPPORT && !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT + LWIP_UNUSED_ARG(p); + LWIP_UNUSED_ARG(len); +#endif /* !MPPE_SUPPORT && !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT */ + + memset(&no, 0, sizeof(no)); + try_ = *go; + +#if MPPE_SUPPORT + if (go->mppe && len >= CILEN_MPPE + && p[0] == CI_MPPE && p[1] == CILEN_MPPE) { + no.mppe = 1; + /* + * Peer wants us to use a different strength or other setting. + * Fail if we aren't willing to use his suggestion. + */ + MPPE_CI_TO_OPTS(&p[2], try_.mppe); + if ((try_.mppe & MPPE_OPT_STATEFUL) && pcb->settings.refuse_mppe_stateful) { + ppp_error("Refusing MPPE stateful mode offered by peer"); + try_.mppe = 0; + } else if (((go->mppe | MPPE_OPT_STATEFUL) & try_.mppe) != try_.mppe) { + /* Peer must have set options we didn't request (suggest) */ + try_.mppe = 0; + } + + if (!try_.mppe) { + ppp_error("MPPE required but peer negotiation failed"); + lcp_close(pcb, "MPPE required but peer negotiation failed"); + } + } +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT + if (go->deflate && len >= CILEN_DEFLATE + && p[0] == (go->deflate_correct? CI_DEFLATE: CI_DEFLATE_DRAFT) + && p[1] == CILEN_DEFLATE) { + no.deflate = 1; + /* + * Peer wants us to use a different code size or something. + * Stop asking for Deflate if we don't understand his suggestion. + */ + if (DEFLATE_METHOD(p[2]) != DEFLATE_METHOD_VAL + || DEFLATE_SIZE(p[2]) < DEFLATE_MIN_WORKS + || p[3] != DEFLATE_CHK_SEQUENCE) + try_.deflate = 0; + else if (DEFLATE_SIZE(p[2]) < go->deflate_size) + try_.deflate_size = DEFLATE_SIZE(p[2]); + p += CILEN_DEFLATE; + len -= CILEN_DEFLATE; + if (go->deflate_correct && go->deflate_draft + && len >= CILEN_DEFLATE && p[0] == CI_DEFLATE_DRAFT + && p[1] == CILEN_DEFLATE) { + p += CILEN_DEFLATE; + len -= CILEN_DEFLATE; + } + } +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + if (go->bsd_compress && len >= CILEN_BSD_COMPRESS + && p[0] == CI_BSD_COMPRESS && p[1] == CILEN_BSD_COMPRESS) { + no.bsd_compress = 1; + /* + * Peer wants us to use a different number of bits + * or a different version. + */ + if (BSD_VERSION(p[2]) != BSD_CURRENT_VERSION) + try_.bsd_compress = 0; + else if (BSD_NBITS(p[2]) < go->bsd_bits) + try_.bsd_bits = BSD_NBITS(p[2]); + p += CILEN_BSD_COMPRESS; + len -= CILEN_BSD_COMPRESS; + } +#endif /* BSDCOMPRESS_SUPPORT */ + + /* + * Predictor-1 and 2 have no options, so they can't be Naked. + * + * There may be remaining options but we ignore them. + */ + + if (f->state != PPP_FSM_OPENED) + *go = try_; + return 1; +} + +/* + * ccp_rejci - reject some of our suggested compression methods. + */ +static int ccp_rejci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + ccp_options *go = &pcb->ccp_gotoptions; + ccp_options try_; /* options to request next time */ + + try_ = *go; + + /* + * Cope with empty configure-rejects by ceasing to send + * configure-requests. + */ + if (len == 0 && pcb->ccp_all_rejected) + return -1; + +#if MPPE_SUPPORT + if (go->mppe && len >= CILEN_MPPE + && p[0] == CI_MPPE && p[1] == CILEN_MPPE) { + ppp_error("MPPE required but peer refused"); + lcp_close(pcb, "MPPE required but peer refused"); + p += CILEN_MPPE; + len -= CILEN_MPPE; + } +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT + if (go->deflate_correct && len >= CILEN_DEFLATE + && p[0] == CI_DEFLATE && p[1] == CILEN_DEFLATE) { + if (p[2] != DEFLATE_MAKE_OPT(go->deflate_size) + || p[3] != DEFLATE_CHK_SEQUENCE) + return 0; /* Rej is bad */ + try_.deflate_correct = 0; + p += CILEN_DEFLATE; + len -= CILEN_DEFLATE; + } + if (go->deflate_draft && len >= CILEN_DEFLATE + && p[0] == CI_DEFLATE_DRAFT && p[1] == CILEN_DEFLATE) { + if (p[2] != DEFLATE_MAKE_OPT(go->deflate_size) + || p[3] != DEFLATE_CHK_SEQUENCE) + return 0; /* Rej is bad */ + try_.deflate_draft = 0; + p += CILEN_DEFLATE; + len -= CILEN_DEFLATE; + } + if (!try_.deflate_correct && !try_.deflate_draft) + try_.deflate = 0; +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + if (go->bsd_compress && len >= CILEN_BSD_COMPRESS + && p[0] == CI_BSD_COMPRESS && p[1] == CILEN_BSD_COMPRESS) { + if (p[2] != BSD_MAKE_OPT(BSD_CURRENT_VERSION, go->bsd_bits)) + return 0; + try_.bsd_compress = 0; + p += CILEN_BSD_COMPRESS; + len -= CILEN_BSD_COMPRESS; + } +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + if (go->predictor_1 && len >= CILEN_PREDICTOR_1 + && p[0] == CI_PREDICTOR_1 && p[1] == CILEN_PREDICTOR_1) { + try_.predictor_1 = 0; + p += CILEN_PREDICTOR_1; + len -= CILEN_PREDICTOR_1; + } + if (go->predictor_2 && len >= CILEN_PREDICTOR_2 + && p[0] == CI_PREDICTOR_2 && p[1] == CILEN_PREDICTOR_2) { + try_.predictor_2 = 0; + p += CILEN_PREDICTOR_2; + len -= CILEN_PREDICTOR_2; + } +#endif /* PREDICTOR_SUPPORT */ + + if (len != 0) + return 0; + + if (f->state != PPP_FSM_OPENED) + *go = try_; + + return 1; +} + +/* + * ccp_reqci - processed a received configure-request. + * Returns CONFACK, CONFNAK or CONFREJ and the packet modified + * appropriately. + */ +static int ccp_reqci(fsm *f, u_char *p, int *lenp, int dont_nak) { + ppp_pcb *pcb = f->pcb; + ccp_options *ho = &pcb->ccp_hisoptions; + ccp_options *ao = &pcb->ccp_allowoptions; + int ret, newret; +#if DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT + int res; + int nb; +#endif /* DEFLATE_SUPPORT || BSDCOMPRESS_SUPPORT */ + u_char *p0, *retp; + int len, clen, type; +#if MPPE_SUPPORT + u8_t rej_for_ci_mppe = 1; /* Are we rejecting based on a bad/missing */ + /* CI_MPPE, or due to other options? */ +#endif /* MPPE_SUPPORT */ + + ret = CONFACK; + retp = p0 = p; + len = *lenp; + + memset(ho, 0, sizeof(ccp_options)); + ho->method = (len > 0)? p[0]: 0; + + while (len > 0) { + newret = CONFACK; + if (len < 2 || p[1] < 2 || p[1] > len) { + /* length is bad */ + clen = len; + newret = CONFREJ; + + } else { + type = p[0]; + clen = p[1]; + + switch (type) { +#if MPPE_SUPPORT + case CI_MPPE: + if (!ao->mppe || clen != CILEN_MPPE) { + newret = CONFREJ; + break; + } + MPPE_CI_TO_OPTS(&p[2], ho->mppe); + + /* Nak if anything unsupported or unknown are set. */ + if (ho->mppe & MPPE_OPT_UNSUPPORTED) { + newret = CONFNAK; + ho->mppe &= ~MPPE_OPT_UNSUPPORTED; + } + if (ho->mppe & MPPE_OPT_UNKNOWN) { + newret = CONFNAK; + ho->mppe &= ~MPPE_OPT_UNKNOWN; + } + + /* Check state opt */ + if (ho->mppe & MPPE_OPT_STATEFUL) { + /* + * We can Nak and request stateless, but it's a + * lot easier to just assume the peer will request + * it if he can do it; stateful mode is bad over + * the Internet -- which is where we expect MPPE. + */ + if (pcb->settings.refuse_mppe_stateful) { + ppp_error("Refusing MPPE stateful mode offered by peer"); + newret = CONFREJ; + break; + } + } + + /* Find out which of {S,L} are set. */ + if ((ho->mppe & MPPE_OPT_128) + && (ho->mppe & MPPE_OPT_40)) { + /* Both are set, negotiate the strongest. */ + newret = CONFNAK; + if (ao->mppe & MPPE_OPT_128) + ho->mppe &= ~MPPE_OPT_40; + else if (ao->mppe & MPPE_OPT_40) + ho->mppe &= ~MPPE_OPT_128; + else { + newret = CONFREJ; + break; + } + } else if (ho->mppe & MPPE_OPT_128) { + if (!(ao->mppe & MPPE_OPT_128)) { + newret = CONFREJ; + break; + } + } else if (ho->mppe & MPPE_OPT_40) { + if (!(ao->mppe & MPPE_OPT_40)) { + newret = CONFREJ; + break; + } + } else { + /* Neither are set. */ + /* We cannot accept this. */ + newret = CONFNAK; + /* Give the peer our idea of what can be used, + so it can choose and confirm */ + ho->mppe = ao->mppe; + } + + /* rebuild the opts */ + MPPE_OPTS_TO_CI(ho->mppe, &p[2]); + if (newret == CONFACK) { + int mtu; + + mppe_init(pcb, &pcb->mppe_comp, ho->mppe); + /* + * We need to decrease the interface MTU by MPPE_PAD + * because MPPE frames **grow**. The kernel [must] + * allocate MPPE_PAD extra bytes in xmit buffers. + */ + mtu = netif_get_mtu(pcb); + if (mtu) + netif_set_mtu(pcb, mtu - MPPE_PAD); + else + newret = CONFREJ; + } + + /* + * We have accepted MPPE or are willing to negotiate + * MPPE parameters. A CONFREJ is due to subsequent + * (non-MPPE) processing. + */ + rej_for_ci_mppe = 0; + break; +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT + case CI_DEFLATE: + case CI_DEFLATE_DRAFT: + if (!ao->deflate || clen != CILEN_DEFLATE + || (!ao->deflate_correct && type == CI_DEFLATE) + || (!ao->deflate_draft && type == CI_DEFLATE_DRAFT)) { + newret = CONFREJ; + break; + } + + ho->deflate = 1; + ho->deflate_size = nb = DEFLATE_SIZE(p[2]); + if (DEFLATE_METHOD(p[2]) != DEFLATE_METHOD_VAL + || p[3] != DEFLATE_CHK_SEQUENCE + || nb > ao->deflate_size || nb < DEFLATE_MIN_WORKS) { + newret = CONFNAK; + if (!dont_nak) { + p[2] = DEFLATE_MAKE_OPT(ao->deflate_size); + p[3] = DEFLATE_CHK_SEQUENCE; + /* fall through to test this #bits below */ + } else + break; + } + + /* + * Check whether we can do Deflate with the window + * size they want. If the window is too big, reduce + * it until the kernel can cope and nak with that. + * We only check this for the first option. + */ + if (p == p0) { + for (;;) { + res = ccp_test(pcb, p, CILEN_DEFLATE, 1); + if (res > 0) + break; /* it's OK now */ + if (res < 0 || nb == DEFLATE_MIN_WORKS || dont_nak) { + newret = CONFREJ; + p[2] = DEFLATE_MAKE_OPT(ho->deflate_size); + break; + } + newret = CONFNAK; + --nb; + p[2] = DEFLATE_MAKE_OPT(nb); + } + } + break; +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + case CI_BSD_COMPRESS: + if (!ao->bsd_compress || clen != CILEN_BSD_COMPRESS) { + newret = CONFREJ; + break; + } + + ho->bsd_compress = 1; + ho->bsd_bits = nb = BSD_NBITS(p[2]); + if (BSD_VERSION(p[2]) != BSD_CURRENT_VERSION + || nb > ao->bsd_bits || nb < BSD_MIN_BITS) { + newret = CONFNAK; + if (!dont_nak) { + p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, ao->bsd_bits); + /* fall through to test this #bits below */ + } else + break; + } + + /* + * Check whether we can do BSD-Compress with the code + * size they want. If the code size is too big, reduce + * it until the kernel can cope and nak with that. + * We only check this for the first option. + */ + if (p == p0) { + for (;;) { + res = ccp_test(pcb, p, CILEN_BSD_COMPRESS, 1); + if (res > 0) + break; + if (res < 0 || nb == BSD_MIN_BITS || dont_nak) { + newret = CONFREJ; + p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, + ho->bsd_bits); + break; + } + newret = CONFNAK; + --nb; + p[2] = BSD_MAKE_OPT(BSD_CURRENT_VERSION, nb); + } + } + break; +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + case CI_PREDICTOR_1: + if (!ao->predictor_1 || clen != CILEN_PREDICTOR_1) { + newret = CONFREJ; + break; + } + + ho->predictor_1 = 1; + if (p == p0 + && ccp_test(pcb, p, CILEN_PREDICTOR_1, 1) <= 0) { + newret = CONFREJ; + } + break; + + case CI_PREDICTOR_2: + if (!ao->predictor_2 || clen != CILEN_PREDICTOR_2) { + newret = CONFREJ; + break; + } + + ho->predictor_2 = 1; + if (p == p0 + && ccp_test(pcb, p, CILEN_PREDICTOR_2, 1) <= 0) { + newret = CONFREJ; + } + break; +#endif /* PREDICTOR_SUPPORT */ + + default: + newret = CONFREJ; + } + } + + if (newret == CONFNAK && dont_nak) + newret = CONFREJ; + if (!(newret == CONFACK || (newret == CONFNAK && ret == CONFREJ))) { + /* we're returning this option */ + if (newret == CONFREJ && ret == CONFNAK) + retp = p0; + ret = newret; + if (p != retp) + MEMCPY(retp, p, clen); + retp += clen; + } + + p += clen; + len -= clen; + } + + if (ret != CONFACK) { + if (ret == CONFREJ && *lenp == retp - p0) + pcb->ccp_all_rejected = 1; + else + *lenp = retp - p0; + } +#if MPPE_SUPPORT + if (ret == CONFREJ && ao->mppe && rej_for_ci_mppe) { + ppp_error("MPPE required but peer negotiation failed"); + lcp_close(pcb, "MPPE required but peer negotiation failed"); + } +#endif /* MPPE_SUPPORT */ + return ret; +} + +/* + * Make a string name for a compression method (or 2). + */ +static const char *method_name(ccp_options *opt, ccp_options *opt2) { + static char result[64]; +#if !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT + LWIP_UNUSED_ARG(opt2); +#endif /* !DEFLATE_SUPPORT && !BSDCOMPRESS_SUPPORT */ + + if (!ccp_anycompress(opt)) + return "(none)"; + switch (opt->method) { +#if MPPE_SUPPORT + case CI_MPPE: + { + char *p = result; + char *q = result + sizeof(result); /* 1 past result */ + + ppp_slprintf(p, q - p, "MPPE "); + p += 5; + if (opt->mppe & MPPE_OPT_128) { + ppp_slprintf(p, q - p, "128-bit "); + p += 8; + } + if (opt->mppe & MPPE_OPT_40) { + ppp_slprintf(p, q - p, "40-bit "); + p += 7; + } + if (opt->mppe & MPPE_OPT_STATEFUL) + ppp_slprintf(p, q - p, "stateful"); + else + ppp_slprintf(p, q - p, "stateless"); + + break; + } +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT + case CI_DEFLATE: + case CI_DEFLATE_DRAFT: + if (opt2 != NULL && opt2->deflate_size != opt->deflate_size) + ppp_slprintf(result, sizeof(result), "Deflate%s (%d/%d)", + (opt->method == CI_DEFLATE_DRAFT? "(old#)": ""), + opt->deflate_size, opt2->deflate_size); + else + ppp_slprintf(result, sizeof(result), "Deflate%s (%d)", + (opt->method == CI_DEFLATE_DRAFT? "(old#)": ""), + opt->deflate_size); + break; +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + case CI_BSD_COMPRESS: + if (opt2 != NULL && opt2->bsd_bits != opt->bsd_bits) + ppp_slprintf(result, sizeof(result), "BSD-Compress (%d/%d)", + opt->bsd_bits, opt2->bsd_bits); + else + ppp_slprintf(result, sizeof(result), "BSD-Compress (%d)", + opt->bsd_bits); + break; +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + case CI_PREDICTOR_1: + return "Predictor 1"; + case CI_PREDICTOR_2: + return "Predictor 2"; +#endif /* PREDICTOR_SUPPORT */ + default: + ppp_slprintf(result, sizeof(result), "Method %d", opt->method); + } + return result; +} + +/* + * CCP has come up - inform the kernel driver and log a message. + */ +static void ccp_up(fsm *f) { + ppp_pcb *pcb = f->pcb; + ccp_options *go = &pcb->ccp_gotoptions; + ccp_options *ho = &pcb->ccp_hisoptions; + char method1[64]; + + ccp_set(pcb, 1, 1, go->method, ho->method); + if (ccp_anycompress(go)) { + if (ccp_anycompress(ho)) { + if (go->method == ho->method) { + ppp_notice("%s compression enabled", method_name(go, ho)); + } else { + ppp_strlcpy(method1, method_name(go, NULL), sizeof(method1)); + ppp_notice("%s / %s compression enabled", + method1, method_name(ho, NULL)); + } + } else + ppp_notice("%s receive compression enabled", method_name(go, NULL)); + } else if (ccp_anycompress(ho)) + ppp_notice("%s transmit compression enabled", method_name(ho, NULL)); +#if MPPE_SUPPORT + if (go->mppe) { + continue_networks(pcb); /* Bring up IP et al */ + } +#endif /* MPPE_SUPPORT */ +} + +/* + * CCP has gone down - inform the kernel driver. + */ +static void ccp_down(fsm *f) { + ppp_pcb *pcb = f->pcb; +#if MPPE_SUPPORT + ccp_options *go = &pcb->ccp_gotoptions; +#endif /* MPPE_SUPPORT */ + + if (pcb->ccp_localstate & RACK_PENDING) + UNTIMEOUT(ccp_rack_timeout, f); + pcb->ccp_localstate = 0; + ccp_set(pcb, 1, 0, 0, 0); +#if MPPE_SUPPORT + if (go->mppe) { + go->mppe = 0; + if (pcb->lcp_fsm.state == PPP_FSM_OPENED) { + /* If LCP is not already going down, make sure it does. */ + ppp_error("MPPE disabled"); + lcp_close(pcb, "MPPE disabled"); + } + } +#endif /* MPPE_SUPPORT */ +} + +#if PRINTPKT_SUPPORT +/* + * Print the contents of a CCP packet. + */ +static const char* const ccp_codenames[] = { + "ConfReq", "ConfAck", "ConfNak", "ConfRej", + "TermReq", "TermAck", "CodeRej", + NULL, NULL, NULL, NULL, NULL, NULL, + "ResetReq", "ResetAck", +}; + +static int ccp_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg) { + const u_char *p0, *optend; + int code, id, len; + int optlen; + + p0 = p; + if (plen < HEADERLEN) + return 0; + code = p[0]; + id = p[1]; + len = (p[2] << 8) + p[3]; + if (len < HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(ccp_codenames) && ccp_codenames[code-1] != NULL) + printer(arg, " %s", ccp_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= HEADERLEN; + p += HEADERLEN; + + switch (code) { + case CONFREQ: + case CONFACK: + case CONFNAK: + case CONFREJ: + /* print list of possible compression methods */ + while (len >= 2) { + code = p[0]; + optlen = p[1]; + if (optlen < 2 || optlen > len) + break; + printer(arg, " <"); + len -= optlen; + optend = p + optlen; + switch (code) { +#if MPPE_SUPPORT + case CI_MPPE: + if (optlen >= CILEN_MPPE) { + u_char mppe_opts; + + MPPE_CI_TO_OPTS(&p[2], mppe_opts); + printer(arg, "mppe %s %s %s %s %s %s%s", + (p[2] & MPPE_H_BIT)? "+H": "-H", + (p[5] & MPPE_M_BIT)? "+M": "-M", + (p[5] & MPPE_S_BIT)? "+S": "-S", + (p[5] & MPPE_L_BIT)? "+L": "-L", + (p[5] & MPPE_D_BIT)? "+D": "-D", + (p[5] & MPPE_C_BIT)? "+C": "-C", + (mppe_opts & MPPE_OPT_UNKNOWN)? " +U": ""); + if (mppe_opts & MPPE_OPT_UNKNOWN) + printer(arg, " (%.2x %.2x %.2x %.2x)", + p[2], p[3], p[4], p[5]); + p += CILEN_MPPE; + } + break; +#endif /* MPPE_SUPPORT */ +#if DEFLATE_SUPPORT + case CI_DEFLATE: + case CI_DEFLATE_DRAFT: + if (optlen >= CILEN_DEFLATE) { + printer(arg, "deflate%s %d", + (code == CI_DEFLATE_DRAFT? "(old#)": ""), + DEFLATE_SIZE(p[2])); + if (DEFLATE_METHOD(p[2]) != DEFLATE_METHOD_VAL) + printer(arg, " method %d", DEFLATE_METHOD(p[2])); + if (p[3] != DEFLATE_CHK_SEQUENCE) + printer(arg, " check %d", p[3]); + p += CILEN_DEFLATE; + } + break; +#endif /* DEFLATE_SUPPORT */ +#if BSDCOMPRESS_SUPPORT + case CI_BSD_COMPRESS: + if (optlen >= CILEN_BSD_COMPRESS) { + printer(arg, "bsd v%d %d", BSD_VERSION(p[2]), + BSD_NBITS(p[2])); + p += CILEN_BSD_COMPRESS; + } + break; +#endif /* BSDCOMPRESS_SUPPORT */ +#if PREDICTOR_SUPPORT + case CI_PREDICTOR_1: + if (optlen >= CILEN_PREDICTOR_1) { + printer(arg, "predictor 1"); + p += CILEN_PREDICTOR_1; + } + break; + case CI_PREDICTOR_2: + if (optlen >= CILEN_PREDICTOR_2) { + printer(arg, "predictor 2"); + p += CILEN_PREDICTOR_2; + } + break; +#endif /* PREDICTOR_SUPPORT */ + default: + break; + } + while (p < optend) + printer(arg, " %.2x", *p++); + printer(arg, ">"); + } + break; + + case TERMACK: + case TERMREQ: + if (len > 0 && *p >= ' ' && *p < 0x7f) { + ppp_print_string(p, len, printer, arg); + p += len; + len = 0; + } + break; + default: + break; + } + + /* dump out the rest of the packet in hex */ + while (--len >= 0) + printer(arg, " %.2x", *p++); + + return p - p0; +} +#endif /* PRINTPKT_SUPPORT */ + +#if PPP_DATAINPUT +/* + * We have received a packet that the decompressor failed to + * decompress. Here we would expect to issue a reset-request, but + * Motorola has a patent on resetting the compressor as a result of + * detecting an error in the decompressed data after decompression. + * (See US patent 5,130,993; international patent publication number + * WO 91/10289; Australian patent 73296/91.) + * + * So we ask the kernel whether the error was detected after + * decompression; if it was, we take CCP down, thus disabling + * compression :-(, otherwise we issue the reset-request. + */ +static void ccp_datainput(ppp_pcb *pcb, u_char *pkt, int len) { + fsm *f; +#if MPPE_SUPPORT + ccp_options *go = &pcb->ccp_gotoptions; +#endif /* MPPE_SUPPORT */ + LWIP_UNUSED_ARG(pkt); + LWIP_UNUSED_ARG(len); + + f = &pcb->ccp_fsm; + if (f->state == PPP_FSM_OPENED) { + if (ccp_fatal_error(pcb)) { + /* + * Disable compression by taking CCP down. + */ + ppp_error("Lost compression sync: disabling compression"); + ccp_close(pcb, "Lost compression sync"); +#if MPPE_SUPPORT + /* + * If we were doing MPPE, we must also take the link down. + */ + if (go->mppe) { + ppp_error("Too many MPPE errors, closing LCP"); + lcp_close(pcb, "Too many MPPE errors"); + } +#endif /* MPPE_SUPPORT */ + } else { + /* + * Send a reset-request to reset the peer's compressor. + * We don't do that if we are still waiting for an + * acknowledgement to a previous reset-request. + */ + if (!(pcb->ccp_localstate & RACK_PENDING)) { + fsm_sdata(f, CCP_RESETREQ, f->reqid = ++f->id, NULL, 0); + TIMEOUT(ccp_rack_timeout, f, RACKTIMEOUT); + pcb->ccp_localstate |= RACK_PENDING; + } else + pcb->ccp_localstate |= RREQ_REPEAT; + } + } +} +#endif /* PPP_DATAINPUT */ + +/* + * We have received a packet that the decompressor failed to + * decompress. Issue a reset-request. + */ +void ccp_resetrequest(ppp_pcb *pcb) { + fsm *f = &pcb->ccp_fsm; + + if (f->state != PPP_FSM_OPENED) + return; + + /* + * Send a reset-request to reset the peer's compressor. + * We don't do that if we are still waiting for an + * acknowledgement to a previous reset-request. + */ + if (!(pcb->ccp_localstate & RACK_PENDING)) { + fsm_sdata(f, CCP_RESETREQ, f->reqid = ++f->id, NULL, 0); + TIMEOUT(ccp_rack_timeout, f, RACKTIMEOUT); + pcb->ccp_localstate |= RACK_PENDING; + } else + pcb->ccp_localstate |= RREQ_REPEAT; +} + +/* + * Timeout waiting for reset-ack. + */ +static void ccp_rack_timeout(void *arg) { + fsm *f = (fsm*)arg; + ppp_pcb *pcb = f->pcb; + + if (f->state == PPP_FSM_OPENED && (pcb->ccp_localstate & RREQ_REPEAT)) { + fsm_sdata(f, CCP_RESETREQ, f->reqid, NULL, 0); + TIMEOUT(ccp_rack_timeout, f, RACKTIMEOUT); + pcb->ccp_localstate &= ~RREQ_REPEAT; + } else + pcb->ccp_localstate &= ~RACK_PENDING; +} + +#endif /* PPP_SUPPORT && CCP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c new file mode 100644 index 0000000..88f069f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-md5.c @@ -0,0 +1,126 @@ +/* + * chap-md5.c - New CHAP/MD5 implementation. + * + * Copyright (c) 2003 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if 0 /* UNUSED */ +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/chap-new.h" +#include "netif/ppp/chap-md5.h" +#include "netif/ppp/magic.h" +#include "netif/ppp/pppcrypt.h" + +#define MD5_HASH_SIZE 16 +#define MD5_MIN_CHALLENGE 17 +#define MD5_MAX_CHALLENGE 24 +#define MD5_MIN_MAX_POWER_OF_TWO_CHALLENGE 3 /* 2^3-1 = 7, 17+7 = 24 */ + +#if PPP_SERVER +static void chap_md5_generate_challenge(ppp_pcb *pcb, unsigned char *cp) { + int clen; + LWIP_UNUSED_ARG(pcb); + + clen = MD5_MIN_CHALLENGE + magic_pow(MD5_MIN_MAX_POWER_OF_TWO_CHALLENGE); + *cp++ = clen; + magic_random_bytes(cp, clen); +} + +static int chap_md5_verify_response(ppp_pcb *pcb, int id, const char *name, + const unsigned char *secret, int secret_len, + const unsigned char *challenge, const unsigned char *response, + char *message, int message_space) { + lwip_md5_context ctx; + unsigned char idbyte = id; + unsigned char hash[MD5_HASH_SIZE]; + int challenge_len, response_len; + LWIP_UNUSED_ARG(name); + LWIP_UNUSED_ARG(pcb); + + challenge_len = *challenge++; + response_len = *response++; + if (response_len == MD5_HASH_SIZE) { + /* Generate hash of ID, secret, challenge */ + lwip_md5_init(&ctx); + lwip_md5_starts(&ctx); + lwip_md5_update(&ctx, &idbyte, 1); + lwip_md5_update(&ctx, secret, secret_len); + lwip_md5_update(&ctx, challenge, challenge_len); + lwip_md5_finish(&ctx, hash); + lwip_md5_free(&ctx); + + /* Test if our hash matches the peer's response */ + if (memcmp(hash, response, MD5_HASH_SIZE) == 0) { + ppp_slprintf(message, message_space, "Access granted"); + return 1; + } + } + ppp_slprintf(message, message_space, "Access denied"); + return 0; +} +#endif /* PPP_SERVER */ + +static void chap_md5_make_response(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name, + const unsigned char *challenge, const char *secret, int secret_len, + unsigned char *private_) { + lwip_md5_context ctx; + unsigned char idbyte = id; + int challenge_len = *challenge++; + LWIP_UNUSED_ARG(our_name); + LWIP_UNUSED_ARG(private_); + LWIP_UNUSED_ARG(pcb); + + lwip_md5_init(&ctx); + lwip_md5_starts(&ctx); + lwip_md5_update(&ctx, &idbyte, 1); + lwip_md5_update(&ctx, (const u_char *)secret, secret_len); + lwip_md5_update(&ctx, challenge, challenge_len); + lwip_md5_finish(&ctx, &response[1]); + lwip_md5_free(&ctx); + response[0] = MD5_HASH_SIZE; +} + +const struct chap_digest_type md5_digest = { + CHAP_MD5, /* code */ +#if PPP_SERVER + chap_md5_generate_challenge, + chap_md5_verify_response, +#endif /* PPP_SERVER */ + chap_md5_make_response, + NULL, /* check_success */ + NULL, /* handle_failure */ +}; + +#endif /* PPP_SUPPORT && CHAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c new file mode 100644 index 0000000..485122d --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/chap-new.c @@ -0,0 +1,677 @@ +/* + * chap-new.c - New CHAP implementation. + * + * Copyright (c) 2003 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && CHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if 0 /* UNUSED */ +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#if 0 /* UNUSED */ +#include "session.h" +#endif /* UNUSED */ + +#include "netif/ppp/chap-new.h" +#include "netif/ppp/chap-md5.h" +#if MSCHAP_SUPPORT +#include "netif/ppp/chap_ms.h" +#endif +#include "netif/ppp/magic.h" + +#if 0 /* UNUSED */ +/* Hook for a plugin to validate CHAP challenge */ +int (*chap_verify_hook)(const char *name, const char *ourname, int id, + const struct chap_digest_type *digest, + const unsigned char *challenge, const unsigned char *response, + char *message, int message_space) = NULL; +#endif /* UNUSED */ + +#if PPP_OPTIONS +/* + * Command-line options. + */ +static option_t chap_option_list[] = { + { "chap-restart", o_int, &chap_timeout_time, + "Set timeout for CHAP", OPT_PRIO }, + { "chap-max-challenge", o_int, &pcb->settings.chap_max_transmits, + "Set max #xmits for challenge", OPT_PRIO }, + { "chap-interval", o_int, &pcb->settings.chap_rechallenge_time, + "Set interval for rechallenge", OPT_PRIO }, + { NULL } +}; +#endif /* PPP_OPTIONS */ + + +/* Values for flags in chap_client_state and chap_server_state */ +#define LOWERUP 1 +#define AUTH_STARTED 2 +#define AUTH_DONE 4 +#define AUTH_FAILED 8 +#define TIMEOUT_PENDING 0x10 +#define CHALLENGE_VALID 0x20 + +/* + * Prototypes. + */ +static void chap_init(ppp_pcb *pcb); +static void chap_lowerup(ppp_pcb *pcb); +static void chap_lowerdown(ppp_pcb *pcb); +#if PPP_SERVER +static void chap_timeout(void *arg); +static void chap_generate_challenge(ppp_pcb *pcb); +static void chap_handle_response(ppp_pcb *pcb, int code, + unsigned char *pkt, int len); +static int chap_verify_response(ppp_pcb *pcb, const char *name, const char *ourname, int id, + const struct chap_digest_type *digest, + const unsigned char *challenge, const unsigned char *response, + char *message, int message_space); +#endif /* PPP_SERVER */ +static void chap_respond(ppp_pcb *pcb, int id, + unsigned char *pkt, int len); +static void chap_handle_status(ppp_pcb *pcb, int code, int id, + unsigned char *pkt, int len); +static void chap_protrej(ppp_pcb *pcb); +static void chap_input(ppp_pcb *pcb, unsigned char *pkt, int pktlen); +#if PRINTPKT_SUPPORT +static int chap_print_pkt(const unsigned char *p, int plen, + void (*printer) (void *, const char *, ...), void *arg); +#endif /* PRINTPKT_SUPPORT */ + +/* List of digest types that we know about */ +static const struct chap_digest_type* const chap_digests[] = { + &md5_digest, +#if MSCHAP_SUPPORT + &chapms_digest, + &chapms2_digest, +#endif /* MSCHAP_SUPPORT */ + NULL +}; + +/* + * chap_init - reset to initial state. + */ +static void chap_init(ppp_pcb *pcb) { + LWIP_UNUSED_ARG(pcb); + +#if 0 /* Not necessary, everything is cleared in ppp_new() */ + memset(&pcb->chap_client, 0, sizeof(chap_client_state)); +#if PPP_SERVER + memset(&pcb->chap_server, 0, sizeof(chap_server_state)); +#endif /* PPP_SERVER */ +#endif /* 0 */ +} + +/* + * chap_lowerup - we can start doing stuff now. + */ +static void chap_lowerup(ppp_pcb *pcb) { + + pcb->chap_client.flags |= LOWERUP; +#if PPP_SERVER + pcb->chap_server.flags |= LOWERUP; + if (pcb->chap_server.flags & AUTH_STARTED) + chap_timeout(pcb); +#endif /* PPP_SERVER */ +} + +static void chap_lowerdown(ppp_pcb *pcb) { + + pcb->chap_client.flags = 0; +#if PPP_SERVER + if (pcb->chap_server.flags & TIMEOUT_PENDING) + UNTIMEOUT(chap_timeout, pcb); + pcb->chap_server.flags = 0; +#endif /* PPP_SERVER */ +} + +#if PPP_SERVER +/* + * chap_auth_peer - Start authenticating the peer. + * If the lower layer is already up, we start sending challenges, + * otherwise we wait for the lower layer to come up. + */ +void chap_auth_peer(ppp_pcb *pcb, const char *our_name, int digest_code) { + const struct chap_digest_type *dp; + int i; + + if (pcb->chap_server.flags & AUTH_STARTED) { + ppp_error("CHAP: peer authentication already started!"); + return; + } + for (i = 0; (dp = chap_digests[i]) != NULL; ++i) + if (dp->code == digest_code) + break; + if (dp == NULL) + ppp_fatal("CHAP digest 0x%x requested but not available", + digest_code); + + pcb->chap_server.digest = dp; + pcb->chap_server.name = our_name; + /* Start with a random ID value */ + pcb->chap_server.id = magic(); + pcb->chap_server.flags |= AUTH_STARTED; + if (pcb->chap_server.flags & LOWERUP) + chap_timeout(pcb); +} +#endif /* PPP_SERVER */ + +/* + * chap_auth_with_peer - Prepare to authenticate ourselves to the peer. + * There isn't much to do until we receive a challenge. + */ +void chap_auth_with_peer(ppp_pcb *pcb, const char *our_name, int digest_code) { + const struct chap_digest_type *dp; + int i; + + if(NULL == our_name) + return; + + if (pcb->chap_client.flags & AUTH_STARTED) { + ppp_error("CHAP: authentication with peer already started!"); + return; + } + for (i = 0; (dp = chap_digests[i]) != NULL; ++i) + if (dp->code == digest_code) + break; + + if (dp == NULL) + ppp_fatal("CHAP digest 0x%x requested but not available", + digest_code); + + pcb->chap_client.digest = dp; + pcb->chap_client.name = our_name; + pcb->chap_client.flags |= AUTH_STARTED; +} + +#if PPP_SERVER +/* + * chap_timeout - It's time to send another challenge to the peer. + * This could be either a retransmission of a previous challenge, + * or a new challenge to start re-authentication. + */ +static void chap_timeout(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + struct pbuf *p; + + pcb->chap_server.flags &= ~TIMEOUT_PENDING; + if ((pcb->chap_server.flags & CHALLENGE_VALID) == 0) { + pcb->chap_server.challenge_xmits = 0; + chap_generate_challenge(pcb); + pcb->chap_server.flags |= CHALLENGE_VALID; + } else if (pcb->chap_server.challenge_xmits >= pcb->settings.chap_max_transmits) { + pcb->chap_server.flags &= ~CHALLENGE_VALID; + pcb->chap_server.flags |= AUTH_DONE | AUTH_FAILED; + auth_peer_fail(pcb, PPP_CHAP); + return; + } + + p = pbuf_alloc(PBUF_RAW, (u16_t)(pcb->chap_server.challenge_pktlen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + MEMCPY(p->payload, pcb->chap_server.challenge, pcb->chap_server.challenge_pktlen); + ppp_write(pcb, p); + ++pcb->chap_server.challenge_xmits; + pcb->chap_server.flags |= TIMEOUT_PENDING; + TIMEOUT(chap_timeout, arg, pcb->settings.chap_timeout_time); +} + +/* + * chap_generate_challenge - generate a challenge string and format + * the challenge packet in pcb->chap_server.challenge_pkt. + */ +static void chap_generate_challenge(ppp_pcb *pcb) { + int clen = 1, nlen, len; + unsigned char *p; + + p = pcb->chap_server.challenge; + MAKEHEADER(p, PPP_CHAP); + p += CHAP_HDRLEN; + pcb->chap_server.digest->generate_challenge(pcb, p); + clen = *p; + nlen = strlen(pcb->chap_server.name); + memcpy(p + 1 + clen, pcb->chap_server.name, nlen); + + len = CHAP_HDRLEN + 1 + clen + nlen; + pcb->chap_server.challenge_pktlen = PPP_HDRLEN + len; + + p = pcb->chap_server.challenge + PPP_HDRLEN; + p[0] = CHAP_CHALLENGE; + p[1] = ++pcb->chap_server.id; + p[2] = len >> 8; + p[3] = len; +} + +/* + * chap_handle_response - check the response to our challenge. + */ +static void chap_handle_response(ppp_pcb *pcb, int id, + unsigned char *pkt, int len) { + int response_len, ok, mlen; + const unsigned char *response; + unsigned char *outp; + struct pbuf *p; + const char *name = NULL; /* initialized to shut gcc up */ +#if 0 /* UNUSED */ + int (*verifier)(const char *, const char *, int, const struct chap_digest_type *, + const unsigned char *, const unsigned char *, char *, int); +#endif /* UNUSED */ + char rname[MAXNAMELEN+1]; + char message[256]; + + if ((pcb->chap_server.flags & LOWERUP) == 0) + return; + if (id != pcb->chap_server.challenge[PPP_HDRLEN+1] || len < 2) + return; + if (pcb->chap_server.flags & CHALLENGE_VALID) { + response = pkt; + GETCHAR(response_len, pkt); + len -= response_len + 1; /* length of name */ + name = (char *)pkt + response_len; + if (len < 0) + return; + + if (pcb->chap_server.flags & TIMEOUT_PENDING) { + pcb->chap_server.flags &= ~TIMEOUT_PENDING; + UNTIMEOUT(chap_timeout, pcb); + } +#if PPP_REMOTENAME + if (pcb->settings.explicit_remote) { + name = pcb->remote_name; + } else +#endif /* PPP_REMOTENAME */ + { + /* Null terminate and clean remote name. */ + ppp_slprintf(rname, sizeof(rname), "%.*v", len, name); + name = rname; + } + +#if 0 /* UNUSED */ + if (chap_verify_hook) + verifier = chap_verify_hook; + else + verifier = chap_verify_response; + ok = (*verifier)(name, pcb->chap_server.name, id, pcb->chap_server.digest, + pcb->chap_server.challenge + PPP_HDRLEN + CHAP_HDRLEN, + response, pcb->chap_server.message, sizeof(pcb->chap_server.message)); +#endif /* UNUSED */ + ok = chap_verify_response(pcb, name, pcb->chap_server.name, id, pcb->chap_server.digest, + pcb->chap_server.challenge + PPP_HDRLEN + CHAP_HDRLEN, + response, message, sizeof(message)); +#if 0 /* UNUSED */ + if (!ok || !auth_number()) { +#endif /* UNUSED */ + if (!ok) { + pcb->chap_server.flags |= AUTH_FAILED; + ppp_warn("Peer %q failed CHAP authentication", name); + } + } else if ((pcb->chap_server.flags & AUTH_DONE) == 0) + return; + + /* send the response */ + mlen = strlen(message); + len = CHAP_HDRLEN + mlen; + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN +len), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (unsigned char *)p->payload; + MAKEHEADER(outp, PPP_CHAP); + + outp[0] = (pcb->chap_server.flags & AUTH_FAILED)? CHAP_FAILURE: CHAP_SUCCESS; + outp[1] = id; + outp[2] = len >> 8; + outp[3] = len; + if (mlen > 0) + memcpy(outp + CHAP_HDRLEN, message, mlen); + ppp_write(pcb, p); + + if (pcb->chap_server.flags & CHALLENGE_VALID) { + pcb->chap_server.flags &= ~CHALLENGE_VALID; + if (!(pcb->chap_server.flags & AUTH_DONE) && !(pcb->chap_server.flags & AUTH_FAILED)) { + +#if 0 /* UNUSED */ + /* + * Auth is OK, so now we need to check session restrictions + * to ensure everything is OK, but only if we used a + * plugin, and only if we're configured to check. This + * allows us to do PAM checks on PPP servers that + * authenticate against ActiveDirectory, and use AD for + * account info (like when using Winbind integrated with + * PAM). + */ + if (session_mgmt && + session_check(name, NULL, devnam, NULL) == 0) { + pcb->chap_server.flags |= AUTH_FAILED; + ppp_warn("Peer %q failed CHAP Session verification", name); + } +#endif /* UNUSED */ + + } + if (pcb->chap_server.flags & AUTH_FAILED) { + auth_peer_fail(pcb, PPP_CHAP); + } else { + if ((pcb->chap_server.flags & AUTH_DONE) == 0) + auth_peer_success(pcb, PPP_CHAP, + pcb->chap_server.digest->code, + name, strlen(name)); + if (pcb->settings.chap_rechallenge_time) { + pcb->chap_server.flags |= TIMEOUT_PENDING; + TIMEOUT(chap_timeout, pcb, + pcb->settings.chap_rechallenge_time); + } + } + pcb->chap_server.flags |= AUTH_DONE; + } +} + +/* + * chap_verify_response - check whether the peer's response matches + * what we think it should be. Returns 1 if it does (authentication + * succeeded), or 0 if it doesn't. + */ +static int chap_verify_response(ppp_pcb *pcb, const char *name, const char *ourname, int id, + const struct chap_digest_type *digest, + const unsigned char *challenge, const unsigned char *response, + char *message, int message_space) { + int ok; + unsigned char secret[MAXSECRETLEN]; + int secret_len; + + /* Get the secret that the peer is supposed to know */ + if (!get_secret(pcb, name, ourname, (char *)secret, &secret_len, 1)) { + ppp_error("No CHAP secret found for authenticating %q", name); + return 0; + } + ok = digest->verify_response(pcb, id, name, secret, secret_len, challenge, + response, message, message_space); + memset(secret, 0, sizeof(secret)); + + return ok; +} +#endif /* PPP_SERVER */ + +/* + * chap_respond - Generate and send a response to a challenge. + */ +static void chap_respond(ppp_pcb *pcb, int id, + unsigned char *pkt, int len) { + int clen, nlen; + int secret_len; + struct pbuf *p; + u_char *outp; + char rname[MAXNAMELEN+1]; + char secret[MAXSECRETLEN+1]; + + p = pbuf_alloc(PBUF_RAW, (u16_t)(RESP_MAX_PKTLEN), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + if ((pcb->chap_client.flags & (LOWERUP | AUTH_STARTED)) != (LOWERUP | AUTH_STARTED)) + return; /* not ready */ + if (len < 2 || len < pkt[0] + 1) + return; /* too short */ + clen = pkt[0]; + nlen = len - (clen + 1); + + /* Null terminate and clean remote name. */ + ppp_slprintf(rname, sizeof(rname), "%.*v", nlen, pkt + clen + 1); + +#if PPP_REMOTENAME + /* Microsoft doesn't send their name back in the PPP packet */ + if (pcb->settings.explicit_remote || (pcb->settings.remote_name[0] != 0 && rname[0] == 0)) + strlcpy(rname, pcb->settings.remote_name, sizeof(rname)); +#endif /* PPP_REMOTENAME */ + + /* get secret for authenticating ourselves with the specified host */ + if (!get_secret(pcb, pcb->chap_client.name, rname, secret, &secret_len, 0)) { + secret_len = 0; /* assume null secret if can't find one */ + ppp_warn("No CHAP secret found for authenticating us to %q", rname); + } + + outp = (u_char*)p->payload; + MAKEHEADER(outp, PPP_CHAP); + outp += CHAP_HDRLEN; + + pcb->chap_client.digest->make_response(pcb, outp, id, pcb->chap_client.name, pkt, + secret, secret_len, pcb->chap_client.priv); + memset(secret, 0, secret_len); + + clen = *outp; + nlen = strlen(pcb->chap_client.name); + memcpy(outp + clen + 1, pcb->chap_client.name, nlen); + + outp = (u_char*)p->payload + PPP_HDRLEN; + len = CHAP_HDRLEN + clen + 1 + nlen; + outp[0] = CHAP_RESPONSE; + outp[1] = id; + outp[2] = len >> 8; + outp[3] = len; + + pbuf_realloc(p, PPP_HDRLEN + len); + ppp_write(pcb, p); +} + +static void chap_handle_status(ppp_pcb *pcb, int code, int id, + unsigned char *pkt, int len) { + const char *msg = NULL; + LWIP_UNUSED_ARG(id); + + if ((pcb->chap_client.flags & (AUTH_DONE|AUTH_STARTED|LOWERUP)) + != (AUTH_STARTED|LOWERUP)) + return; + pcb->chap_client.flags |= AUTH_DONE; + + if (code == CHAP_SUCCESS) { + /* used for MS-CHAP v2 mutual auth, yuck */ + if (pcb->chap_client.digest->check_success != NULL) { + if (!(*pcb->chap_client.digest->check_success)(pcb, pkt, len, pcb->chap_client.priv)) + code = CHAP_FAILURE; + } else + msg = "CHAP authentication succeeded"; + } else { + if (pcb->chap_client.digest->handle_failure != NULL) + (*pcb->chap_client.digest->handle_failure)(pcb, pkt, len); + else + msg = "CHAP authentication failed"; + } + if (msg) { + if (len > 0) + ppp_info("%s: %.*v", msg, len, pkt); + else + ppp_info("%s", msg); + } + if (code == CHAP_SUCCESS) + auth_withpeer_success(pcb, PPP_CHAP, pcb->chap_client.digest->code); + else { + pcb->chap_client.flags |= AUTH_FAILED; + ppp_error("CHAP authentication failed"); + auth_withpeer_fail(pcb, PPP_CHAP); + } +} + +static void chap_input(ppp_pcb *pcb, unsigned char *pkt, int pktlen) { + unsigned char code, id; + int len; + + if (pktlen < CHAP_HDRLEN) + return; + GETCHAR(code, pkt); + GETCHAR(id, pkt); + GETSHORT(len, pkt); + if (len < CHAP_HDRLEN || len > pktlen) + return; + len -= CHAP_HDRLEN; + + switch (code) { + case CHAP_CHALLENGE: + chap_respond(pcb, id, pkt, len); + break; +#if PPP_SERVER + case CHAP_RESPONSE: + chap_handle_response(pcb, id, pkt, len); + break; +#endif /* PPP_SERVER */ + case CHAP_FAILURE: + case CHAP_SUCCESS: + chap_handle_status(pcb, code, id, pkt, len); + break; + default: + break; + } +} + +static void chap_protrej(ppp_pcb *pcb) { + +#if PPP_SERVER + if (pcb->chap_server.flags & TIMEOUT_PENDING) { + pcb->chap_server.flags &= ~TIMEOUT_PENDING; + UNTIMEOUT(chap_timeout, pcb); + } + if (pcb->chap_server.flags & AUTH_STARTED) { + pcb->chap_server.flags = 0; + auth_peer_fail(pcb, PPP_CHAP); + } +#endif /* PPP_SERVER */ + if ((pcb->chap_client.flags & (AUTH_STARTED|AUTH_DONE)) == AUTH_STARTED) { + pcb->chap_client.flags &= ~AUTH_STARTED; + ppp_error("CHAP authentication failed due to protocol-reject"); + auth_withpeer_fail(pcb, PPP_CHAP); + } +} + +#if PRINTPKT_SUPPORT +/* + * chap_print_pkt - print the contents of a CHAP packet. + */ +static const char* const chap_code_names[] = { + "Challenge", "Response", "Success", "Failure" +}; + +static int chap_print_pkt(const unsigned char *p, int plen, + void (*printer) (void *, const char *, ...), void *arg) { + int code, id, len; + int clen, nlen; + unsigned char x; + + if (plen < CHAP_HDRLEN) + return 0; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < CHAP_HDRLEN || len > plen) + return 0; + + if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(chap_code_names)) + printer(arg, " %s", chap_code_names[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= CHAP_HDRLEN; + switch (code) { + case CHAP_CHALLENGE: + case CHAP_RESPONSE: + if (len < 1) + break; + clen = p[0]; + if (len < clen + 1) + break; + ++p; + nlen = len - clen - 1; + printer(arg, " <"); + for (; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, "%.2x", x); + } + printer(arg, ">, name = "); + ppp_print_string(p, nlen, printer, arg); + break; + case CHAP_FAILURE: + case CHAP_SUCCESS: + printer(arg, " "); + ppp_print_string(p, len, printer, arg); + break; + default: + for (clen = len; clen > 0; --clen) { + GETCHAR(x, p); + printer(arg, " %.2x", x); + } + /* no break */ + } + + return len + CHAP_HDRLEN; +} +#endif /* PRINTPKT_SUPPORT */ + +const struct protent chap_protent = { + PPP_CHAP, + chap_init, + chap_input, + chap_protrej, + chap_lowerup, + chap_lowerdown, + NULL, /* open */ + NULL, /* close */ +#if PRINTPKT_SUPPORT + chap_print_pkt, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + NULL, /* datainput */ +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "CHAP", /* name */ + NULL, /* data_name */ +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + chap_option_list, + NULL, /* check_options */ +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + NULL, + NULL +#endif /* DEMAND_SUPPORT */ +}; + +#endif /* PPP_SUPPORT && CHAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c new file mode 100644 index 0000000..5a989c9 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/chap_ms.c @@ -0,0 +1,962 @@ +/* + * chap_ms.c - Microsoft MS-CHAP compatible implementation. + * + * Copyright (c) 1995 Eric Rosenquist. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* + * Modifications by Lauri Pesonen / lpesonen@clinet.fi, april 1997 + * + * Implemented LANManager type password response to MS-CHAP challenges. + * Now pppd provides both NT style and LANMan style blocks, and the + * prefered is set by option "ms-lanman". Default is to use NT. + * The hash text (StdText) was taken from Win95 RASAPI32.DLL. + * + * You should also use DOMAIN\\USERNAME as described in README.MSCHAP80 + */ + +/* + * Modifications by Frank Cusack, frank@google.com, March 2002. + * + * Implemented MS-CHAPv2 functionality, heavily based on sample + * implementation in RFC 2759. Implemented MPPE functionality, + * heavily based on sample implementation in RFC 3079. + * + * Copyright (c) 2002 Google, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && MSCHAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if 0 /* UNUSED */ +#include +#include +#include +#include +#include +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/chap-new.h" +#include "netif/ppp/chap_ms.h" +#include "netif/ppp/pppcrypt.h" +#include "netif/ppp/magic.h" +#if MPPE_SUPPORT +#include "netif/ppp/mppe.h" /* For mppe_sha1_pad*, mppe_set_key() */ +#endif /* MPPE_SUPPORT */ + +#define SHA1_SIGNATURE_SIZE 20 +#define MD4_SIGNATURE_SIZE 16 /* 16 bytes in a MD4 message digest */ +#define MAX_NT_PASSWORD 256 /* Max (Unicode) chars in an NT pass */ + +#define MS_CHAP_RESPONSE_LEN 49 /* Response length for MS-CHAP */ +#define MS_CHAP2_RESPONSE_LEN 49 /* Response length for MS-CHAPv2 */ +#define MS_AUTH_RESPONSE_LENGTH 40 /* MS-CHAPv2 authenticator response, */ + /* as ASCII */ + +/* Error codes for MS-CHAP failure messages. */ +#define MS_CHAP_ERROR_RESTRICTED_LOGON_HOURS 646 +#define MS_CHAP_ERROR_ACCT_DISABLED 647 +#define MS_CHAP_ERROR_PASSWD_EXPIRED 648 +#define MS_CHAP_ERROR_NO_DIALIN_PERMISSION 649 +#define MS_CHAP_ERROR_AUTHENTICATION_FAILURE 691 +#define MS_CHAP_ERROR_CHANGING_PASSWORD 709 + +/* + * Offsets within the response field for MS-CHAP + */ +#define MS_CHAP_LANMANRESP 0 +#define MS_CHAP_LANMANRESP_LEN 24 +#define MS_CHAP_NTRESP 24 +#define MS_CHAP_NTRESP_LEN 24 +#define MS_CHAP_USENT 48 + +/* + * Offsets within the response field for MS-CHAP2 + */ +#define MS_CHAP2_PEER_CHALLENGE 0 +#define MS_CHAP2_PEER_CHAL_LEN 16 +#define MS_CHAP2_RESERVED_LEN 8 +#define MS_CHAP2_NTRESP 24 +#define MS_CHAP2_NTRESP_LEN 24 +#define MS_CHAP2_FLAGS 48 + +#if MPPE_SUPPORT +#if 0 /* UNUSED */ +/* These values are the RADIUS attribute values--see RFC 2548. */ +#define MPPE_ENC_POL_ENC_ALLOWED 1 +#define MPPE_ENC_POL_ENC_REQUIRED 2 +#define MPPE_ENC_TYPES_RC4_40 2 +#define MPPE_ENC_TYPES_RC4_128 4 + +/* used by plugins (using above values) */ +extern void set_mppe_enc_types(int, int); +#endif /* UNUSED */ +#endif /* MPPE_SUPPORT */ + +/* Are we the authenticator or authenticatee? For MS-CHAPv2 key derivation. */ +#define MS_CHAP2_AUTHENTICATEE 0 +#define MS_CHAP2_AUTHENTICATOR 1 + +static void ascii2unicode (const char[], int, u_char[]); +static void NTPasswordHash (u_char *, int, u_char[MD4_SIGNATURE_SIZE]); +static void ChallengeResponse (const u_char *, const u_char *, u_char[24]); +static void ChallengeHash (const u_char[16], const u_char *, const char *, u_char[8]); +static void ChapMS_NT (const u_char *, const char *, int, u_char[24]); +static void ChapMS2_NT (const u_char *, const u_char[16], const char *, const char *, int, + u_char[24]); +static void GenerateAuthenticatorResponsePlain + (const char*, int, u_char[24], const u_char[16], const u_char *, + const char *, u_char[41]); +#ifdef MSLANMAN +static void ChapMS_LANMan (u_char *, char *, int, u_char *); +#endif + +static void GenerateAuthenticatorResponse(const u_char PasswordHashHash[MD4_SIGNATURE_SIZE], + u_char NTResponse[24], const u_char PeerChallenge[16], + const u_char *rchallenge, const char *username, + u_char authResponse[MS_AUTH_RESPONSE_LENGTH+1]); + +#if MPPE_SUPPORT +static void Set_Start_Key (ppp_pcb *pcb, const u_char *, const char *, int); +static void SetMasterKeys (ppp_pcb *pcb, const char *, int, u_char[24], int); +#endif /* MPPE_SUPPORT */ + +static void ChapMS (ppp_pcb *pcb, const u_char *, const char *, int, u_char *); +static void ChapMS2 (ppp_pcb *pcb, const u_char *, const u_char *, const char *, const char *, int, + u_char *, u_char[MS_AUTH_RESPONSE_LENGTH+1], int); + +#ifdef MSLANMAN +bool ms_lanman = 0; /* Use LanMan password instead of NT */ + /* Has meaning only with MS-CHAP challenges */ +#endif + +#if MPPE_SUPPORT +#ifdef DEBUGMPPEKEY +/* For MPPE debug */ +/* Use "[]|}{?/><,`!2&&(" (sans quotes) for RFC 3079 MS-CHAPv2 test value */ +static char *mschap_challenge = NULL; +/* Use "!@\#$%^&*()_+:3|~" (sans quotes, backslash is to escape #) for ... */ +static char *mschap2_peer_challenge = NULL; +#endif + +#include "netif/ppp/fsm.h" /* Need to poke MPPE options */ +#include "netif/ppp/ccp.h" +#endif /* MPPE_SUPPORT */ + +#if PPP_OPTIONS +/* + * Command-line options. + */ +static option_t chapms_option_list[] = { +#ifdef MSLANMAN + { "ms-lanman", o_bool, &ms_lanman, + "Use LanMan passwd when using MS-CHAP", 1 }, +#endif +#ifdef DEBUGMPPEKEY + { "mschap-challenge", o_string, &mschap_challenge, + "specify CHAP challenge" }, + { "mschap2-peer-challenge", o_string, &mschap2_peer_challenge, + "specify CHAP peer challenge" }, +#endif + { NULL } +}; +#endif /* PPP_OPTIONS */ + +#if PPP_SERVER +/* + * chapms_generate_challenge - generate a challenge for MS-CHAP. + * For MS-CHAP the challenge length is fixed at 8 bytes. + * The length goes in challenge[0] and the actual challenge starts + * at challenge[1]. + */ +static void chapms_generate_challenge(ppp_pcb *pcb, unsigned char *challenge) { + LWIP_UNUSED_ARG(pcb); + + *challenge++ = 8; +#ifdef DEBUGMPPEKEY + if (mschap_challenge && strlen(mschap_challenge) == 8) + memcpy(challenge, mschap_challenge, 8); + else +#endif + magic_random_bytes(challenge, 8); +} + +static void chapms2_generate_challenge(ppp_pcb *pcb, unsigned char *challenge) { + LWIP_UNUSED_ARG(pcb); + + *challenge++ = 16; +#ifdef DEBUGMPPEKEY + if (mschap_challenge && strlen(mschap_challenge) == 16) + memcpy(challenge, mschap_challenge, 16); + else +#endif + magic_random_bytes(challenge, 16); +} + +static int chapms_verify_response(ppp_pcb *pcb, int id, const char *name, + const unsigned char *secret, int secret_len, + const unsigned char *challenge, const unsigned char *response, + char *message, int message_space) { + unsigned char md[MS_CHAP_RESPONSE_LEN]; + int diff; + int challenge_len, response_len; + LWIP_UNUSED_ARG(id); + LWIP_UNUSED_ARG(name); + + challenge_len = *challenge++; /* skip length, is 8 */ + response_len = *response++; + if (response_len != MS_CHAP_RESPONSE_LEN) + goto bad; + +#ifndef MSLANMAN + if (!response[MS_CHAP_USENT]) { + /* Should really propagate this into the error packet. */ + ppp_notice("Peer request for LANMAN auth not supported"); + goto bad; + } +#endif + + /* Generate the expected response. */ + ChapMS(pcb, (const u_char *)challenge, (const char *)secret, secret_len, md); + +#ifdef MSLANMAN + /* Determine which part of response to verify against */ + if (!response[MS_CHAP_USENT]) + diff = memcmp(&response[MS_CHAP_LANMANRESP], + &md[MS_CHAP_LANMANRESP], MS_CHAP_LANMANRESP_LEN); + else +#endif + diff = memcmp(&response[MS_CHAP_NTRESP], &md[MS_CHAP_NTRESP], + MS_CHAP_NTRESP_LEN); + + if (diff == 0) { + ppp_slprintf(message, message_space, "Access granted"); + return 1; + } + + bad: + /* See comments below for MS-CHAP V2 */ + ppp_slprintf(message, message_space, "E=691 R=1 C=%0.*B V=0", + challenge_len, challenge); + return 0; +} + +static int chapms2_verify_response(ppp_pcb *pcb, int id, const char *name, + const unsigned char *secret, int secret_len, + const unsigned char *challenge, const unsigned char *response, + char *message, int message_space) { + unsigned char md[MS_CHAP2_RESPONSE_LEN]; + char saresponse[MS_AUTH_RESPONSE_LENGTH+1]; + int challenge_len, response_len; + LWIP_UNUSED_ARG(id); + + challenge_len = *challenge++; /* skip length, is 16 */ + response_len = *response++; + if (response_len != MS_CHAP2_RESPONSE_LEN) + goto bad; /* not even the right length */ + + /* Generate the expected response and our mutual auth. */ + ChapMS2(pcb, (const u_char*)challenge, (const u_char*)&response[MS_CHAP2_PEER_CHALLENGE], name, + (const char *)secret, secret_len, md, + (unsigned char *)saresponse, MS_CHAP2_AUTHENTICATOR); + + /* compare MDs and send the appropriate status */ + /* + * Per RFC 2759, success message must be formatted as + * "S= M=" + * where + * is the Authenticator Response (mutual auth) + * is a text message + * + * However, some versions of Windows (win98 tested) do not know + * about the M= part (required per RFC 2759) and flag + * it as an error (reported incorrectly as an encryption error + * to the user). Since the RFC requires it, and it can be + * useful information, we supply it if the peer is a conforming + * system. Luckily (?), win98 sets the Flags field to 0x04 + * (contrary to RFC requirements) so we can use that to + * distinguish between conforming and non-conforming systems. + * + * Special thanks to Alex Swiridov for + * help debugging this. + */ + if (memcmp(&md[MS_CHAP2_NTRESP], &response[MS_CHAP2_NTRESP], + MS_CHAP2_NTRESP_LEN) == 0) { + if (response[MS_CHAP2_FLAGS]) + ppp_slprintf(message, message_space, "S=%s", saresponse); + else + ppp_slprintf(message, message_space, "S=%s M=%s", + saresponse, "Access granted"); + return 1; + } + + bad: + /* + * Failure message must be formatted as + * "E=e R=r C=c V=v M=m" + * where + * e = error code (we use 691, ERROR_AUTHENTICATION_FAILURE) + * r = retry (we use 1, ok to retry) + * c = challenge to use for next response, we reuse previous + * v = Change Password version supported, we use 0 + * m = text message + * + * The M=m part is only for MS-CHAPv2. Neither win2k nor + * win98 (others untested) display the message to the user anyway. + * They also both ignore the E=e code. + * + * Note that it's safe to reuse the same challenge as we don't + * actually accept another response based on the error message + * (and no clients try to resend a response anyway). + * + * Basically, this whole bit is useless code, even the small + * implementation here is only because of overspecification. + */ + ppp_slprintf(message, message_space, "E=691 R=1 C=%0.*B V=0 M=%s", + challenge_len, challenge, "Access denied"); + return 0; +} +#endif /* PPP_SERVER */ + +static void chapms_make_response(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name, + const unsigned char *challenge, const char *secret, int secret_len, + unsigned char *private_) { + LWIP_UNUSED_ARG(id); + LWIP_UNUSED_ARG(our_name); + LWIP_UNUSED_ARG(private_); + challenge++; /* skip length, should be 8 */ + *response++ = MS_CHAP_RESPONSE_LEN; + ChapMS(pcb, challenge, secret, secret_len, response); +} + +static void chapms2_make_response(ppp_pcb *pcb, unsigned char *response, int id, const char *our_name, + const unsigned char *challenge, const char *secret, int secret_len, + unsigned char *private_) { + LWIP_UNUSED_ARG(id); + challenge++; /* skip length, should be 16 */ + *response++ = MS_CHAP2_RESPONSE_LEN; + ChapMS2(pcb, challenge, +#ifdef DEBUGMPPEKEY + mschap2_peer_challenge, +#else + NULL, +#endif + our_name, secret, secret_len, response, private_, + MS_CHAP2_AUTHENTICATEE); +} + +static int chapms2_check_success(ppp_pcb *pcb, unsigned char *msg, int len, unsigned char *private_) { + LWIP_UNUSED_ARG(pcb); + + if ((len < MS_AUTH_RESPONSE_LENGTH + 2) || + strncmp((char *)msg, "S=", 2) != 0) { + /* Packet does not start with "S=" */ + ppp_error("MS-CHAPv2 Success packet is badly formed."); + return 0; + } + msg += 2; + len -= 2; + if (len < MS_AUTH_RESPONSE_LENGTH + || memcmp(msg, private_, MS_AUTH_RESPONSE_LENGTH)) { + /* Authenticator Response did not match expected. */ + ppp_error("MS-CHAPv2 mutual authentication failed."); + return 0; + } + /* Authenticator Response matches. */ + msg += MS_AUTH_RESPONSE_LENGTH; /* Eat it */ + len -= MS_AUTH_RESPONSE_LENGTH; + if ((len >= 3) && !strncmp((char *)msg, " M=", 3)) { + msg += 3; /* Eat the delimiter */ + } else if (len) { + /* Packet has extra text which does not begin " M=" */ + ppp_error("MS-CHAPv2 Success packet is badly formed."); + return 0; + } + return 1; +} + +static void chapms_handle_failure(ppp_pcb *pcb, unsigned char *inp, int len) { + int err; + const char *p; + char msg[64]; + LWIP_UNUSED_ARG(pcb); + + /* We want a null-terminated string for strxxx(). */ + len = LWIP_MIN(len, 63); + MEMCPY(msg, inp, len); + msg[len] = 0; + p = msg; + + /* + * Deal with MS-CHAP formatted failure messages; just print the + * M= part (if any). For MS-CHAP we're not really supposed + * to use M=, but it shouldn't hurt. See + * chapms[2]_verify_response. + */ + if (!strncmp(p, "E=", 2)) + err = strtol(p+2, NULL, 10); /* Remember the error code. */ + else + goto print_msg; /* Message is badly formatted. */ + + if (len && ((p = strstr(p, " M=")) != NULL)) { + /* M= field found. */ + p += 3; + } else { + /* No M=; use the error code. */ + switch (err) { + case MS_CHAP_ERROR_RESTRICTED_LOGON_HOURS: + p = "E=646 Restricted logon hours"; + break; + + case MS_CHAP_ERROR_ACCT_DISABLED: + p = "E=647 Account disabled"; + break; + + case MS_CHAP_ERROR_PASSWD_EXPIRED: + p = "E=648 Password expired"; + break; + + case MS_CHAP_ERROR_NO_DIALIN_PERMISSION: + p = "E=649 No dialin permission"; + break; + + case MS_CHAP_ERROR_AUTHENTICATION_FAILURE: + p = "E=691 Authentication failure"; + break; + + case MS_CHAP_ERROR_CHANGING_PASSWORD: + /* Should never see this, we don't support Change Password. */ + p = "E=709 Error changing password"; + break; + + default: + ppp_error("Unknown MS-CHAP authentication failure: %.*v", + len, inp); + return; + } + } +print_msg: + if (p != NULL) + ppp_error("MS-CHAP authentication failed: %v", p); +} + +static void ChallengeResponse(const u_char *challenge, + const u_char PasswordHash[MD4_SIGNATURE_SIZE], + u_char response[24]) { + u_char ZPasswordHash[21]; + lwip_des_context des; + u_char des_key[8]; + + BZERO(ZPasswordHash, sizeof(ZPasswordHash)); + MEMCPY(ZPasswordHash, PasswordHash, MD4_SIGNATURE_SIZE); + +#if 0 + dbglog("ChallengeResponse - ZPasswordHash %.*B", + sizeof(ZPasswordHash), ZPasswordHash); +#endif + + pppcrypt_56_to_64_bit_key(ZPasswordHash + 0, des_key); + lwip_des_init(&des); + lwip_des_setkey_enc(&des, des_key); + lwip_des_crypt_ecb(&des, challenge, response +0); + lwip_des_free(&des); + + pppcrypt_56_to_64_bit_key(ZPasswordHash + 7, des_key); + lwip_des_init(&des); + lwip_des_setkey_enc(&des, des_key); + lwip_des_crypt_ecb(&des, challenge, response +8); + lwip_des_free(&des); + + pppcrypt_56_to_64_bit_key(ZPasswordHash + 14, des_key); + lwip_des_init(&des); + lwip_des_setkey_enc(&des, des_key); + lwip_des_crypt_ecb(&des, challenge, response +16); + lwip_des_free(&des); + +#if 0 + dbglog("ChallengeResponse - response %.24B", response); +#endif +} + +static void ChallengeHash(const u_char PeerChallenge[16], const u_char *rchallenge, + const char *username, u_char Challenge[8]) { + lwip_sha1_context sha1Context; + u_char sha1Hash[SHA1_SIGNATURE_SIZE]; + const char *user; + + /* remove domain from "domain\username" */ + if ((user = strrchr(username, '\\')) != NULL) + ++user; + else + user = username; + + lwip_sha1_init(&sha1Context); + lwip_sha1_starts(&sha1Context); + lwip_sha1_update(&sha1Context, PeerChallenge, 16); + lwip_sha1_update(&sha1Context, rchallenge, 16); + lwip_sha1_update(&sha1Context, (const unsigned char*)user, strlen(user)); + lwip_sha1_finish(&sha1Context, sha1Hash); + lwip_sha1_free(&sha1Context); + + MEMCPY(Challenge, sha1Hash, 8); +} + +/* + * Convert the ASCII version of the password to Unicode. + * This implicitly supports 8-bit ISO8859/1 characters. + * This gives us the little-endian representation, which + * is assumed by all M$ CHAP RFCs. (Unicode byte ordering + * is machine-dependent.) + */ +static void ascii2unicode(const char ascii[], int ascii_len, u_char unicode[]) { + int i; + + BZERO(unicode, ascii_len * 2); + for (i = 0; i < ascii_len; i++) + unicode[i * 2] = (u_char) ascii[i]; +} + +static void NTPasswordHash(u_char *secret, int secret_len, u_char hash[MD4_SIGNATURE_SIZE]) { + lwip_md4_context md4Context; + + lwip_md4_init(&md4Context); + lwip_md4_starts(&md4Context); + lwip_md4_update(&md4Context, secret, secret_len); + lwip_md4_finish(&md4Context, hash); + lwip_md4_free(&md4Context); +} + +static void ChapMS_NT(const u_char *rchallenge, const char *secret, int secret_len, + u_char NTResponse[24]) { + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + u_char PasswordHash[MD4_SIGNATURE_SIZE]; + + /* Hash the Unicode version of the secret (== password). */ + ascii2unicode(secret, secret_len, unicodePassword); + NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash); + + ChallengeResponse(rchallenge, PasswordHash, NTResponse); +} + +static void ChapMS2_NT(const u_char *rchallenge, const u_char PeerChallenge[16], const char *username, + const char *secret, int secret_len, u_char NTResponse[24]) { + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + u_char PasswordHash[MD4_SIGNATURE_SIZE]; + u_char Challenge[8]; + + ChallengeHash(PeerChallenge, rchallenge, username, Challenge); + + /* Hash the Unicode version of the secret (== password). */ + ascii2unicode(secret, secret_len, unicodePassword); + NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash); + + ChallengeResponse(Challenge, PasswordHash, NTResponse); +} + +#ifdef MSLANMAN +static u_char *StdText = (u_char *)"KGS!@#$%"; /* key from rasapi32.dll */ + +static void ChapMS_LANMan(u_char *rchallenge, char *secret, int secret_len, + unsigned char *response) { + int i; + u_char UcasePassword[MAX_NT_PASSWORD]; /* max is actually 14 */ + u_char PasswordHash[MD4_SIGNATURE_SIZE]; + lwip_des_context des; + u_char des_key[8]; + + /* LANMan password is case insensitive */ + BZERO(UcasePassword, sizeof(UcasePassword)); + for (i = 0; i < secret_len; i++) + UcasePassword[i] = (u_char)toupper(secret[i]); + + pppcrypt_56_to_64_bit_key(UcasePassword +0, des_key); + lwip_des_init(&des); + lwip_des_setkey_enc(&des, des_key); + lwip_des_crypt_ecb(&des, StdText, PasswordHash +0); + lwip_des_free(&des); + + pppcrypt_56_to_64_bit_key(UcasePassword +7, des_key); + lwip_des_init(&des); + lwip_des_setkey_enc(&des, des_key); + lwip_des_crypt_ecb(&des, StdText, PasswordHash +8); + lwip_des_free(&des); + + ChallengeResponse(rchallenge, PasswordHash, &response[MS_CHAP_LANMANRESP]); +} +#endif + + +static void GenerateAuthenticatorResponse(const u_char PasswordHashHash[MD4_SIGNATURE_SIZE], + u_char NTResponse[24], const u_char PeerChallenge[16], + const u_char *rchallenge, const char *username, + u_char authResponse[MS_AUTH_RESPONSE_LENGTH+1]) { + /* + * "Magic" constants used in response generation, from RFC 2759. + */ + static const u_char Magic1[39] = /* "Magic server to client signing constant" */ + { 0x4D, 0x61, 0x67, 0x69, 0x63, 0x20, 0x73, 0x65, 0x72, 0x76, + 0x65, 0x72, 0x20, 0x74, 0x6F, 0x20, 0x63, 0x6C, 0x69, 0x65, + 0x6E, 0x74, 0x20, 0x73, 0x69, 0x67, 0x6E, 0x69, 0x6E, 0x67, + 0x20, 0x63, 0x6F, 0x6E, 0x73, 0x74, 0x61, 0x6E, 0x74 }; + static const u_char Magic2[41] = /* "Pad to make it do more than one iteration" */ + { 0x50, 0x61, 0x64, 0x20, 0x74, 0x6F, 0x20, 0x6D, 0x61, 0x6B, + 0x65, 0x20, 0x69, 0x74, 0x20, 0x64, 0x6F, 0x20, 0x6D, 0x6F, + 0x72, 0x65, 0x20, 0x74, 0x68, 0x61, 0x6E, 0x20, 0x6F, 0x6E, + 0x65, 0x20, 0x69, 0x74, 0x65, 0x72, 0x61, 0x74, 0x69, 0x6F, + 0x6E }; + + int i; + lwip_sha1_context sha1Context; + u_char Digest[SHA1_SIGNATURE_SIZE]; + u_char Challenge[8]; + + lwip_sha1_init(&sha1Context); + lwip_sha1_starts(&sha1Context); + lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE); + lwip_sha1_update(&sha1Context, NTResponse, 24); + lwip_sha1_update(&sha1Context, Magic1, sizeof(Magic1)); + lwip_sha1_finish(&sha1Context, Digest); + lwip_sha1_free(&sha1Context); + + ChallengeHash(PeerChallenge, rchallenge, username, Challenge); + + lwip_sha1_init(&sha1Context); + lwip_sha1_starts(&sha1Context); + lwip_sha1_update(&sha1Context, Digest, sizeof(Digest)); + lwip_sha1_update(&sha1Context, Challenge, sizeof(Challenge)); + lwip_sha1_update(&sha1Context, Magic2, sizeof(Magic2)); + lwip_sha1_finish(&sha1Context, Digest); + lwip_sha1_free(&sha1Context); + + /* Convert to ASCII hex string. */ + for (i = 0; i < LWIP_MAX((MS_AUTH_RESPONSE_LENGTH / 2), (int)sizeof(Digest)); i++) + sprintf((char *)&authResponse[i * 2], "%02X", Digest[i]); +} + + +static void GenerateAuthenticatorResponsePlain( + const char *secret, int secret_len, + u_char NTResponse[24], const u_char PeerChallenge[16], + const u_char *rchallenge, const char *username, + u_char authResponse[MS_AUTH_RESPONSE_LENGTH+1]) { + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + u_char PasswordHash[MD4_SIGNATURE_SIZE]; + u_char PasswordHashHash[MD4_SIGNATURE_SIZE]; + + /* Hash (x2) the Unicode version of the secret (== password). */ + ascii2unicode(secret, secret_len, unicodePassword); + NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash); + NTPasswordHash(PasswordHash, sizeof(PasswordHash), + PasswordHashHash); + + GenerateAuthenticatorResponse(PasswordHashHash, NTResponse, PeerChallenge, + rchallenge, username, authResponse); +} + + +#if MPPE_SUPPORT +/* + * Set mppe_xxxx_key from MS-CHAP credentials. (see RFC 3079) + */ +static void Set_Start_Key(ppp_pcb *pcb, const u_char *rchallenge, const char *secret, int secret_len) { + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + u_char PasswordHash[MD4_SIGNATURE_SIZE]; + u_char PasswordHashHash[MD4_SIGNATURE_SIZE]; + lwip_sha1_context sha1Context; + u_char Digest[SHA1_SIGNATURE_SIZE]; /* >= MPPE_MAX_KEY_LEN */ + + /* Hash (x2) the Unicode version of the secret (== password). */ + ascii2unicode(secret, secret_len, unicodePassword); + NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash); + NTPasswordHash(PasswordHash, sizeof(PasswordHash), PasswordHashHash); + + lwip_sha1_init(&sha1Context); + lwip_sha1_starts(&sha1Context); + lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE); + lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE); + lwip_sha1_update(&sha1Context, rchallenge, 8); + lwip_sha1_finish(&sha1Context, Digest); + lwip_sha1_free(&sha1Context); + + /* Same key in both directions. */ + mppe_set_key(pcb, &pcb->mppe_comp, Digest); + mppe_set_key(pcb, &pcb->mppe_decomp, Digest); + + pcb->mppe_keys_set = 1; +} + +/* + * Set mppe_xxxx_key from MS-CHAPv2 credentials. (see RFC 3079) + */ +static void SetMasterKeys(ppp_pcb *pcb, const char *secret, int secret_len, u_char NTResponse[24], int IsServer) { + u_char unicodePassword[MAX_NT_PASSWORD * 2]; + u_char PasswordHash[MD4_SIGNATURE_SIZE]; + u_char PasswordHashHash[MD4_SIGNATURE_SIZE]; + lwip_sha1_context sha1Context; + u_char MasterKey[SHA1_SIGNATURE_SIZE]; /* >= MPPE_MAX_KEY_LEN */ + u_char Digest[SHA1_SIGNATURE_SIZE]; /* >= MPPE_MAX_KEY_LEN */ + const u_char *s; + + /* "This is the MPPE Master Key" */ + static const u_char Magic1[27] = + { 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x74, + 0x68, 0x65, 0x20, 0x4d, 0x50, 0x50, 0x45, 0x20, 0x4d, + 0x61, 0x73, 0x74, 0x65, 0x72, 0x20, 0x4b, 0x65, 0x79 }; + /* "On the client side, this is the send key; " + "on the server side, it is the receive key." */ + static const u_char Magic2[84] = + { 0x4f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x6c, 0x69, + 0x65, 0x6e, 0x74, 0x20, 0x73, 0x69, 0x64, 0x65, 0x2c, 0x20, + 0x74, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x74, 0x68, + 0x65, 0x20, 0x73, 0x65, 0x6e, 0x64, 0x20, 0x6b, 0x65, 0x79, + 0x3b, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x73, + 0x65, 0x72, 0x76, 0x65, 0x72, 0x20, 0x73, 0x69, 0x64, 0x65, + 0x2c, 0x20, 0x69, 0x74, 0x20, 0x69, 0x73, 0x20, 0x74, 0x68, + 0x65, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x20, + 0x6b, 0x65, 0x79, 0x2e }; + /* "On the client side, this is the receive key; " + "on the server side, it is the send key." */ + static const u_char Magic3[84] = + { 0x4f, 0x6e, 0x20, 0x74, 0x68, 0x65, 0x20, 0x63, 0x6c, 0x69, + 0x65, 0x6e, 0x74, 0x20, 0x73, 0x69, 0x64, 0x65, 0x2c, 0x20, + 0x74, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, 0x74, 0x68, + 0x65, 0x20, 0x72, 0x65, 0x63, 0x65, 0x69, 0x76, 0x65, 0x20, + 0x6b, 0x65, 0x79, 0x3b, 0x20, 0x6f, 0x6e, 0x20, 0x74, 0x68, + 0x65, 0x20, 0x73, 0x65, 0x72, 0x76, 0x65, 0x72, 0x20, 0x73, + 0x69, 0x64, 0x65, 0x2c, 0x20, 0x69, 0x74, 0x20, 0x69, 0x73, + 0x20, 0x74, 0x68, 0x65, 0x20, 0x73, 0x65, 0x6e, 0x64, 0x20, + 0x6b, 0x65, 0x79, 0x2e }; + + /* Hash (x2) the Unicode version of the secret (== password). */ + ascii2unicode(secret, secret_len, unicodePassword); + NTPasswordHash(unicodePassword, secret_len * 2, PasswordHash); + NTPasswordHash(PasswordHash, sizeof(PasswordHash), PasswordHashHash); + + lwip_sha1_init(&sha1Context); + lwip_sha1_starts(&sha1Context); + lwip_sha1_update(&sha1Context, PasswordHashHash, MD4_SIGNATURE_SIZE); + lwip_sha1_update(&sha1Context, NTResponse, 24); + lwip_sha1_update(&sha1Context, Magic1, sizeof(Magic1)); + lwip_sha1_finish(&sha1Context, MasterKey); + lwip_sha1_free(&sha1Context); + + /* + * generate send key + */ + if (IsServer) + s = Magic3; + else + s = Magic2; + lwip_sha1_init(&sha1Context); + lwip_sha1_starts(&sha1Context); + lwip_sha1_update(&sha1Context, MasterKey, 16); + lwip_sha1_update(&sha1Context, mppe_sha1_pad1, SHA1_PAD_SIZE); + lwip_sha1_update(&sha1Context, s, 84); + lwip_sha1_update(&sha1Context, mppe_sha1_pad2, SHA1_PAD_SIZE); + lwip_sha1_finish(&sha1Context, Digest); + lwip_sha1_free(&sha1Context); + + mppe_set_key(pcb, &pcb->mppe_comp, Digest); + + /* + * generate recv key + */ + if (IsServer) + s = Magic2; + else + s = Magic3; + lwip_sha1_init(&sha1Context); + lwip_sha1_starts(&sha1Context); + lwip_sha1_update(&sha1Context, MasterKey, 16); + lwip_sha1_update(&sha1Context, mppe_sha1_pad1, SHA1_PAD_SIZE); + lwip_sha1_update(&sha1Context, s, 84); + lwip_sha1_update(&sha1Context, mppe_sha1_pad2, SHA1_PAD_SIZE); + lwip_sha1_finish(&sha1Context, Digest); + lwip_sha1_free(&sha1Context); + + mppe_set_key(pcb, &pcb->mppe_decomp, Digest); + + pcb->mppe_keys_set = 1; +} + +#endif /* MPPE_SUPPORT */ + + +static void ChapMS(ppp_pcb *pcb, const u_char *rchallenge, const char *secret, int secret_len, + unsigned char *response) { +#if !MPPE_SUPPORT + LWIP_UNUSED_ARG(pcb); +#endif /* !MPPE_SUPPORT */ + BZERO(response, MS_CHAP_RESPONSE_LEN); + + ChapMS_NT(rchallenge, secret, secret_len, &response[MS_CHAP_NTRESP]); + +#ifdef MSLANMAN + ChapMS_LANMan(rchallenge, secret, secret_len, + &response[MS_CHAP_LANMANRESP]); + + /* preferred method is set by option */ + response[MS_CHAP_USENT] = !ms_lanman; +#else + response[MS_CHAP_USENT] = 1; +#endif + +#if MPPE_SUPPORT + Set_Start_Key(pcb, rchallenge, secret, secret_len); +#endif /* MPPE_SUPPORT */ +} + + +/* + * If PeerChallenge is NULL, one is generated and the PeerChallenge + * field of response is filled in. Call this way when generating a response. + * If PeerChallenge is supplied, it is copied into the PeerChallenge field. + * Call this way when verifying a response (or debugging). + * Do not call with PeerChallenge = response. + * + * The PeerChallenge field of response is then used for calculation of the + * Authenticator Response. + */ +static void ChapMS2(ppp_pcb *pcb, const u_char *rchallenge, const u_char *PeerChallenge, + const char *user, const char *secret, int secret_len, unsigned char *response, + u_char authResponse[], int authenticator) { + /* ARGSUSED */ + LWIP_UNUSED_ARG(authenticator); +#if !MPPE_SUPPORT + LWIP_UNUSED_ARG(pcb); +#endif /* !MPPE_SUPPORT */ + + BZERO(response, MS_CHAP2_RESPONSE_LEN); + + /* Generate the Peer-Challenge if requested, or copy it if supplied. */ + if (!PeerChallenge) + magic_random_bytes(&response[MS_CHAP2_PEER_CHALLENGE], MS_CHAP2_PEER_CHAL_LEN); + else + MEMCPY(&response[MS_CHAP2_PEER_CHALLENGE], PeerChallenge, + MS_CHAP2_PEER_CHAL_LEN); + + /* Generate the NT-Response */ + ChapMS2_NT(rchallenge, &response[MS_CHAP2_PEER_CHALLENGE], user, + secret, secret_len, &response[MS_CHAP2_NTRESP]); + + /* Generate the Authenticator Response. */ + GenerateAuthenticatorResponsePlain(secret, secret_len, + &response[MS_CHAP2_NTRESP], + &response[MS_CHAP2_PEER_CHALLENGE], + rchallenge, user, authResponse); + +#if MPPE_SUPPORT + SetMasterKeys(pcb, secret, secret_len, + &response[MS_CHAP2_NTRESP], authenticator); +#endif /* MPPE_SUPPORT */ +} + +#if 0 /* UNUSED */ +#if MPPE_SUPPORT +/* + * Set MPPE options from plugins. + */ +void set_mppe_enc_types(int policy, int types) { + /* Early exit for unknown policies. */ + if (policy != MPPE_ENC_POL_ENC_ALLOWED || + policy != MPPE_ENC_POL_ENC_REQUIRED) + return; + + /* Don't modify MPPE if it's optional and wasn't already configured. */ + if (policy == MPPE_ENC_POL_ENC_ALLOWED && !ccp_wantoptions[0].mppe) + return; + + /* + * Disable undesirable encryption types. Note that we don't ENABLE + * any encryption types, to avoid overriding manual configuration. + */ + switch(types) { + case MPPE_ENC_TYPES_RC4_40: + ccp_wantoptions[0].mppe &= ~MPPE_OPT_128; /* disable 128-bit */ + break; + case MPPE_ENC_TYPES_RC4_128: + ccp_wantoptions[0].mppe &= ~MPPE_OPT_40; /* disable 40-bit */ + break; + default: + break; + } +} +#endif /* MPPE_SUPPORT */ +#endif /* UNUSED */ + +const struct chap_digest_type chapms_digest = { + CHAP_MICROSOFT, /* code */ +#if PPP_SERVER + chapms_generate_challenge, + chapms_verify_response, +#endif /* PPP_SERVER */ + chapms_make_response, + NULL, /* check_success */ + chapms_handle_failure, +}; + +const struct chap_digest_type chapms2_digest = { + CHAP_MICROSOFT_V2, /* code */ +#if PPP_SERVER + chapms2_generate_challenge, + chapms2_verify_response, +#endif /* PPP_SERVER */ + chapms2_make_response, + chapms2_check_success, + chapms_handle_failure, +}; + +#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c new file mode 100644 index 0000000..26c6c30 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/demand.c @@ -0,0 +1,465 @@ +/* + * demand.c - Support routines for demand-dialling. + * + * Copyright (c) 1996-2002 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && DEMAND_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef PPP_FILTER +#include +#endif + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/ipcp.h" +#include "netif/ppp/lcp.h" + +char *frame; +int framelen; +int framemax; +int escape_flag; +int flush_flag; +int fcs; + +struct packet { + int length; + struct packet *next; + unsigned char data[1]; +}; + +struct packet *pend_q; +struct packet *pend_qtail; + +static int active_packet (unsigned char *, int); + +/* + * demand_conf - configure the interface for doing dial-on-demand. + */ +void +demand_conf() +{ + int i; + const struct protent *protp; + +/* framemax = lcp_allowoptions[0].mru; + if (framemax < PPP_MRU) */ + framemax = PPP_MRU; + framemax += PPP_HDRLEN + PPP_FCSLEN; + frame = malloc(framemax); + if (frame == NULL) + novm("demand frame"); + framelen = 0; + pend_q = NULL; + escape_flag = 0; + flush_flag = 0; + fcs = PPP_INITFCS; + + netif_set_mtu(pcb, LWIP_MIN(lcp_allowoptions[0].mru, PPP_MRU)); + if (ppp_send_config(pcb, PPP_MRU, (u32_t) 0, 0, 0) < 0 + || ppp_recv_config(pcb, PPP_MRU, (u32_t) 0, 0, 0) < 0) + fatal("Couldn't set up demand-dialled PPP interface: %m"); + +#ifdef PPP_FILTER + set_filters(&pass_filter, &active_filter); +#endif + + /* + * Call the demand_conf procedure for each protocol that's got one. + */ + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (protp->demand_conf != NULL) + ((*protp->demand_conf)(pcb)); +/* FIXME: find a way to die() here */ +#if 0 + if (!((*protp->demand_conf)(pcb))) + die(1); +#endif +} + + +/* + * demand_block - set each network protocol to block further packets. + */ +void +demand_block() +{ + int i; + const struct protent *protp; + + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (protp->demand_conf != NULL) + sifnpmode(pcb, protp->protocol & ~0x8000, NPMODE_QUEUE); + get_loop_output(); +} + +/* + * demand_discard - set each network protocol to discard packets + * with an error. + */ +void +demand_discard() +{ + struct packet *pkt, *nextpkt; + int i; + const struct protent *protp; + + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (protp->demand_conf != NULL) + sifnpmode(pcb, protp->protocol & ~0x8000, NPMODE_ERROR); + get_loop_output(); + + /* discard all saved packets */ + for (pkt = pend_q; pkt != NULL; pkt = nextpkt) { + nextpkt = pkt->next; + free(pkt); + } + pend_q = NULL; + framelen = 0; + flush_flag = 0; + escape_flag = 0; + fcs = PPP_INITFCS; +} + +/* + * demand_unblock - set each enabled network protocol to pass packets. + */ +void +demand_unblock() +{ + int i; + const struct protent *protp; + + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (protp->demand_conf != NULL) + sifnpmode(pcb, protp->protocol & ~0x8000, NPMODE_PASS); +} + +/* + * FCS lookup table as calculated by genfcstab. + */ +static u_short fcstab[256] = { + 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, + 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, + 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, + 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, + 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, + 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, + 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, + 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, + 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, + 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, + 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, + 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, + 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, + 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, + 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, + 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, + 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, + 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, + 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, + 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, + 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, + 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, + 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, + 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, + 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, + 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, + 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, + 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, + 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, + 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, + 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, + 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 +}; + +/* + * loop_chars - process characters received from the loopback. + * Calls loop_frame when a complete frame has been accumulated. + * Return value is 1 if we need to bring up the link, 0 otherwise. + */ +int +loop_chars(p, n) + unsigned char *p; + int n; +{ + int c, rv; + + rv = 0; + +/* check for synchronous connection... */ + + if ( (p[0] == 0xFF) && (p[1] == 0x03) ) { + rv = loop_frame(p,n); + return rv; + } + + for (; n > 0; --n) { + c = *p++; + if (c == PPP_FLAG) { + if (!escape_flag && !flush_flag + && framelen > 2 && fcs == PPP_GOODFCS) { + framelen -= 2; + if (loop_frame((unsigned char *)frame, framelen)) + rv = 1; + } + framelen = 0; + flush_flag = 0; + escape_flag = 0; + fcs = PPP_INITFCS; + continue; + } + if (flush_flag) + continue; + if (escape_flag) { + c ^= PPP_TRANS; + escape_flag = 0; + } else if (c == PPP_ESCAPE) { + escape_flag = 1; + continue; + } + if (framelen >= framemax) { + flush_flag = 1; + continue; + } + frame[framelen++] = c; + fcs = PPP_FCS(fcs, c); + } + return rv; +} + +/* + * loop_frame - given a frame obtained from the loopback, + * decide whether to bring up the link or not, and, if we want + * to transmit this frame later, put it on the pending queue. + * Return value is 1 if we need to bring up the link, 0 otherwise. + * We assume that the kernel driver has already applied the + * pass_filter, so we won't get packets it rejected. + * We apply the active_filter to see if we want this packet to + * bring up the link. + */ +int +loop_frame(frame, len) + unsigned char *frame; + int len; +{ + struct packet *pkt; + + /* dbglog("from loop: %P", frame, len); */ + if (len < PPP_HDRLEN) + return 0; + if ((PPP_PROTOCOL(frame) & 0x8000) != 0) + return 0; /* shouldn't get any of these anyway */ + if (!active_packet(frame, len)) + return 0; + + pkt = (struct packet *) malloc(sizeof(struct packet) + len); + if (pkt != NULL) { + pkt->length = len; + pkt->next = NULL; + memcpy(pkt->data, frame, len); + if (pend_q == NULL) + pend_q = pkt; + else + pend_qtail->next = pkt; + pend_qtail = pkt; + } + return 1; +} + +/* + * demand_rexmit - Resend all those frames which we got via the + * loopback, now that the real serial link is up. + */ +void +demand_rexmit(proto, newip) + int proto; + u32_t newip; +{ + struct packet *pkt, *prev, *nextpkt; + unsigned short checksum; + unsigned short pkt_checksum = 0; + unsigned iphdr; + struct timeval tv; + char cv = 0; + char ipstr[16]; + + prev = NULL; + pkt = pend_q; + pend_q = NULL; + tv.tv_sec = 1; + tv.tv_usec = 0; + select(0,NULL,NULL,NULL,&tv); /* Sleep for 1 Seconds */ + for (; pkt != NULL; pkt = nextpkt) { + nextpkt = pkt->next; + if (PPP_PROTOCOL(pkt->data) == proto) { + if ( (proto == PPP_IP) && newip ) { + /* Get old checksum */ + + iphdr = (pkt->data[4] & 15) << 2; + checksum = *((unsigned short *) (pkt->data+14)); + if (checksum == 0xFFFF) { + checksum = 0; + } + + + if (pkt->data[13] == 17) { + pkt_checksum = *((unsigned short *) (pkt->data+10+iphdr)); + if (pkt_checksum) { + cv = 1; + if (pkt_checksum == 0xFFFF) { + pkt_checksum = 0; + } + } + else { + cv = 0; + } + } + + if (pkt->data[13] == 6) { + pkt_checksum = *((unsigned short *) (pkt->data+20+iphdr)); + cv = 1; + if (pkt_checksum == 0xFFFF) { + pkt_checksum = 0; + } + } + + /* Delete old Source-IP-Address */ + checksum -= *((unsigned short *) (pkt->data+16)) ^ 0xFFFF; + checksum -= *((unsigned short *) (pkt->data+18)) ^ 0xFFFF; + + pkt_checksum -= *((unsigned short *) (pkt->data+16)) ^ 0xFFFF; + pkt_checksum -= *((unsigned short *) (pkt->data+18)) ^ 0xFFFF; + + /* Change Source-IP-Address */ + * ((u32_t *) (pkt->data + 16)) = newip; + + /* Add new Source-IP-Address */ + checksum += *((unsigned short *) (pkt->data+16)) ^ 0xFFFF; + checksum += *((unsigned short *) (pkt->data+18)) ^ 0xFFFF; + + pkt_checksum += *((unsigned short *) (pkt->data+16)) ^ 0xFFFF; + pkt_checksum += *((unsigned short *) (pkt->data+18)) ^ 0xFFFF; + + /* Write new checksum */ + if (!checksum) { + checksum = 0xFFFF; + } + *((unsigned short *) (pkt->data+14)) = checksum; + if (pkt->data[13] == 6) { + *((unsigned short *) (pkt->data+20+iphdr)) = pkt_checksum; + } + if (cv && (pkt->data[13] == 17) ) { + *((unsigned short *) (pkt->data+10+iphdr)) = pkt_checksum; + } + + /* Log Packet */ + strcpy(ipstr,inet_ntoa(*( (struct in_addr *) (pkt->data+16)))); + if (pkt->data[13] == 1) { + syslog(LOG_INFO,"Open ICMP %s -> %s\n", + ipstr, + inet_ntoa(*( (struct in_addr *) (pkt->data+20)))); + } else { + syslog(LOG_INFO,"Open %s %s:%d -> %s:%d\n", + pkt->data[13] == 6 ? "TCP" : "UDP", + ipstr, + ntohs(*( (short *) (pkt->data+iphdr+4))), + inet_ntoa(*( (struct in_addr *) (pkt->data+20))), + ntohs(*( (short *) (pkt->data+iphdr+6)))); + } + } + output(pcb, pkt->data, pkt->length); + free(pkt); + } else { + if (prev == NULL) + pend_q = pkt; + else + prev->next = pkt; + prev = pkt; + } + } + pend_qtail = prev; + if (prev != NULL) + prev->next = NULL; +} + +/* + * Scan a packet to decide whether it is an "active" packet, + * that is, whether it is worth bringing up the link for. + */ +static int +active_packet(p, len) + unsigned char *p; + int len; +{ + int proto, i; + const struct protent *protp; + + if (len < PPP_HDRLEN) + return 0; + proto = PPP_PROTOCOL(p); +#ifdef PPP_FILTER + p[0] = 1; /* outbound packet indicator */ + if ((pass_filter.bf_len != 0 + && bpf_filter(pass_filter.bf_insns, p, len, len) == 0) + || (active_filter.bf_len != 0 + && bpf_filter(active_filter.bf_insns, p, len, len) == 0)) { + p[0] = 0xff; + return 0; + } + p[0] = 0xff; +#endif + for (i = 0; (protp = protocols[i]) != NULL; ++i) { + if (protp->protocol < 0xC000 && (protp->protocol & ~0x8000) == proto) { + if (protp->active_pkt == NULL) + return 1; + return (*protp->active_pkt)(p, len); + } + } + return 0; /* not a supported protocol !!?? */ +} + +#endif /* PPP_SUPPORT && DEMAND_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c new file mode 100644 index 0000000..8fb5636 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/eap.c @@ -0,0 +1,2423 @@ +/* + * eap.c - Extensible Authentication Protocol for PPP (RFC 2284) + * + * Copyright (c) 2001 by Sun Microsystems, Inc. + * All rights reserved. + * + * Non-exclusive rights to redistribute, modify, translate, and use + * this software in source and binary forms, in whole or in part, is + * hereby granted, provided that the above copyright notice is + * duplicated in any source form, and that neither the name of the + * copyright holder nor the author is used to endorse or promote + * products derived from this software. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Original version by James Carlson + * + * This implementation of EAP supports MD5-Challenge and SRP-SHA1 + * authentication styles. Note that support of MD5-Challenge is a + * requirement of RFC 2284, and that it's essentially just a + * reimplementation of regular RFC 1994 CHAP using EAP messages. + * + * As an authenticator ("server"), there are multiple phases for each + * style. In the first phase of each style, the unauthenticated peer + * name is queried using the EAP Identity request type. If the + * "remotename" option is used, then this phase is skipped, because + * the peer's name is presumed to be known. + * + * For MD5-Challenge, there are two phases, and the second phase + * consists of sending the challenge itself and handling the + * associated response. + * + * For SRP-SHA1, there are four phases. The second sends 's', 'N', + * and 'g'. The reply contains 'A'. The third sends 'B', and the + * reply contains 'M1'. The forth sends the 'M2' value. + * + * As an authenticatee ("client"), there's just a single phase -- + * responding to the queries generated by the peer. EAP is an + * authenticator-driven protocol. + * + * Based on draft-ietf-pppext-eap-srp-03.txt. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && EAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/eap.h" +#include "netif/ppp/magic.h" +#include "netif/ppp/pppcrypt.h" + +#ifdef USE_SRP +#include +#include +#include +#endif /* USE_SRP */ + +#ifndef SHA_DIGESTSIZE +#define SHA_DIGESTSIZE 20 +#endif + +#ifdef USE_SRP +static char *pn_secret = NULL; /* Pseudonym generating secret */ +#endif + +#if PPP_OPTIONS +/* + * Command-line options. + */ +static option_t eap_option_list[] = { + { "eap-restart", o_int, &eap_states[0].es_server.ea_timeout, + "Set retransmit timeout for EAP Requests (server)" }, + { "eap-max-sreq", o_int, &eap_states[0].es_server.ea_maxrequests, + "Set max number of EAP Requests sent (server)" }, + { "eap-timeout", o_int, &eap_states[0].es_client.ea_timeout, + "Set time limit for peer EAP authentication" }, + { "eap-max-rreq", o_int, &eap_states[0].es_client.ea_maxrequests, + "Set max number of EAP Requests allows (client)" }, + { "eap-interval", o_int, &eap_states[0].es_rechallenge, + "Set interval for EAP rechallenge" }, +#ifdef USE_SRP + { "srp-interval", o_int, &eap_states[0].es_lwrechallenge, + "Set interval for SRP lightweight rechallenge" }, + { "srp-pn-secret", o_string, &pn_secret, + "Long term pseudonym generation secret" }, + { "srp-use-pseudonym", o_bool, &eap_states[0].es_usepseudo, + "Use pseudonym if offered one by server", 1 }, +#endif + { NULL } +}; +#endif /* PPP_OPTIONS */ + +/* + * Protocol entry points. + */ +static void eap_init(ppp_pcb *pcb); +static void eap_input(ppp_pcb *pcb, u_char *inp, int inlen); +static void eap_protrej(ppp_pcb *pcb); +static void eap_lowerup(ppp_pcb *pcb); +static void eap_lowerdown(ppp_pcb *pcb); +#if PRINTPKT_SUPPORT +static int eap_printpkt(const u_char *inp, int inlen, + void (*)(void *arg, const char *fmt, ...), void *arg); +#endif /* PRINTPKT_SUPPORT */ + +const struct protent eap_protent = { + PPP_EAP, /* protocol number */ + eap_init, /* initialization procedure */ + eap_input, /* process a received packet */ + eap_protrej, /* process a received protocol-reject */ + eap_lowerup, /* lower layer has gone up */ + eap_lowerdown, /* lower layer has gone down */ + NULL, /* open the protocol */ + NULL, /* close the protocol */ +#if PRINTPKT_SUPPORT + eap_printpkt, /* print a packet in readable form */ +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + NULL, /* process a received data packet */ +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "EAP", /* text name of protocol */ + NULL, /* text name of corresponding data protocol */ +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + eap_option_list, /* list of command-line options */ + NULL, /* check requested options; assign defaults */ +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + NULL, /* configure interface for demand-dial */ + NULL /* say whether to bring up link for this pkt */ +#endif /* DEMAND_SUPPORT */ +}; + +#ifdef USE_SRP +/* + * A well-known 2048 bit modulus. + */ +static const u_char wkmodulus[] = { + 0xAC, 0x6B, 0xDB, 0x41, 0x32, 0x4A, 0x9A, 0x9B, + 0xF1, 0x66, 0xDE, 0x5E, 0x13, 0x89, 0x58, 0x2F, + 0xAF, 0x72, 0xB6, 0x65, 0x19, 0x87, 0xEE, 0x07, + 0xFC, 0x31, 0x92, 0x94, 0x3D, 0xB5, 0x60, 0x50, + 0xA3, 0x73, 0x29, 0xCB, 0xB4, 0xA0, 0x99, 0xED, + 0x81, 0x93, 0xE0, 0x75, 0x77, 0x67, 0xA1, 0x3D, + 0xD5, 0x23, 0x12, 0xAB, 0x4B, 0x03, 0x31, 0x0D, + 0xCD, 0x7F, 0x48, 0xA9, 0xDA, 0x04, 0xFD, 0x50, + 0xE8, 0x08, 0x39, 0x69, 0xED, 0xB7, 0x67, 0xB0, + 0xCF, 0x60, 0x95, 0x17, 0x9A, 0x16, 0x3A, 0xB3, + 0x66, 0x1A, 0x05, 0xFB, 0xD5, 0xFA, 0xAA, 0xE8, + 0x29, 0x18, 0xA9, 0x96, 0x2F, 0x0B, 0x93, 0xB8, + 0x55, 0xF9, 0x79, 0x93, 0xEC, 0x97, 0x5E, 0xEA, + 0xA8, 0x0D, 0x74, 0x0A, 0xDB, 0xF4, 0xFF, 0x74, + 0x73, 0x59, 0xD0, 0x41, 0xD5, 0xC3, 0x3E, 0xA7, + 0x1D, 0x28, 0x1E, 0x44, 0x6B, 0x14, 0x77, 0x3B, + 0xCA, 0x97, 0xB4, 0x3A, 0x23, 0xFB, 0x80, 0x16, + 0x76, 0xBD, 0x20, 0x7A, 0x43, 0x6C, 0x64, 0x81, + 0xF1, 0xD2, 0xB9, 0x07, 0x87, 0x17, 0x46, 0x1A, + 0x5B, 0x9D, 0x32, 0xE6, 0x88, 0xF8, 0x77, 0x48, + 0x54, 0x45, 0x23, 0xB5, 0x24, 0xB0, 0xD5, 0x7D, + 0x5E, 0xA7, 0x7A, 0x27, 0x75, 0xD2, 0xEC, 0xFA, + 0x03, 0x2C, 0xFB, 0xDB, 0xF5, 0x2F, 0xB3, 0x78, + 0x61, 0x60, 0x27, 0x90, 0x04, 0xE5, 0x7A, 0xE6, + 0xAF, 0x87, 0x4E, 0x73, 0x03, 0xCE, 0x53, 0x29, + 0x9C, 0xCC, 0x04, 0x1C, 0x7B, 0xC3, 0x08, 0xD8, + 0x2A, 0x56, 0x98, 0xF3, 0xA8, 0xD0, 0xC3, 0x82, + 0x71, 0xAE, 0x35, 0xF8, 0xE9, 0xDB, 0xFB, 0xB6, + 0x94, 0xB5, 0xC8, 0x03, 0xD8, 0x9F, 0x7A, 0xE4, + 0x35, 0xDE, 0x23, 0x6D, 0x52, 0x5F, 0x54, 0x75, + 0x9B, 0x65, 0xE3, 0x72, 0xFC, 0xD6, 0x8E, 0xF2, + 0x0F, 0xA7, 0x11, 0x1F, 0x9E, 0x4A, 0xFF, 0x73 +}; +#endif + +#if PPP_SERVER +/* Local forward declarations. */ +static void eap_server_timeout(void *arg); +#endif /* PPP_SERVER */ + +/* + * Convert EAP state code to printable string for debug. + */ +static const char * eap_state_name(enum eap_state_code esc) +{ + static const char *state_names[] = { EAP_STATES }; + + return (state_names[(int)esc]); +} + +/* + * eap_init - Initialize state for an EAP user. This is currently + * called once by main() during start-up. + */ +static void eap_init(ppp_pcb *pcb) { + + BZERO(&pcb->eap, sizeof(eap_state)); +#if PPP_SERVER + pcb->eap.es_server.ea_id = magic(); +#endif /* PPP_SERVER */ +} + +/* + * eap_client_timeout - Give up waiting for the peer to send any + * Request messages. + */ +static void eap_client_timeout(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + + if (!eap_client_active(pcb)) + return; + + ppp_error("EAP: timeout waiting for Request from peer"); + auth_withpeer_fail(pcb, PPP_EAP); + pcb->eap.es_client.ea_state = eapBadAuth; +} + +/* + * eap_authwithpeer - Authenticate to our peer (behave as client). + * + * Start client state and wait for requests. This is called only + * after eap_lowerup. + */ +void eap_authwithpeer(ppp_pcb *pcb, const char *localname) { + + if(NULL == localname) + return; + + /* Save the peer name we're given */ + pcb->eap.es_client.ea_name = localname; + pcb->eap.es_client.ea_namelen = strlen(localname); + + pcb->eap.es_client.ea_state = eapListen; + + /* + * Start a timer so that if the other end just goes + * silent, we don't sit here waiting forever. + */ + if (pcb->settings.eap_req_time > 0) + TIMEOUT(eap_client_timeout, pcb, + pcb->settings.eap_req_time); +} + +#if PPP_SERVER +/* + * Format a standard EAP Failure message and send it to the peer. + * (Server operation) + */ +static void eap_send_failure(ppp_pcb *pcb) { + struct pbuf *p; + u_char *outp; + + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + EAP_HEADERLEN), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_FAILURE, outp); + pcb->eap.es_server.ea_id++; + PUTCHAR(pcb->eap.es_server.ea_id, outp); + PUTSHORT(EAP_HEADERLEN, outp); + + ppp_write(pcb, p); + + pcb->eap.es_server.ea_state = eapBadAuth; + auth_peer_fail(pcb, PPP_EAP); +} + +/* + * Format a standard EAP Success message and send it to the peer. + * (Server operation) + */ +static void eap_send_success(ppp_pcb *pcb) { + struct pbuf *p; + u_char *outp; + + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + EAP_HEADERLEN), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_SUCCESS, outp); + pcb->eap.es_server.ea_id++; + PUTCHAR(pcb->eap.es_server.ea_id, outp); + PUTSHORT(EAP_HEADERLEN, outp); + + ppp_write(pcb, p); + + auth_peer_success(pcb, PPP_EAP, 0, + pcb->eap.es_server.ea_peer, pcb->eap.es_server.ea_peerlen); +} +#endif /* PPP_SERVER */ + +#ifdef USE_SRP +/* + * Set DES key according to pseudonym-generating secret and current + * date. + */ +static bool +pncrypt_setkey(int timeoffs) +{ + struct tm *tp; + char tbuf[9]; + SHA1_CTX ctxt; + u_char dig[SHA_DIGESTSIZE]; + time_t reftime; + + if (pn_secret == NULL) + return (0); + reftime = time(NULL) + timeoffs; + tp = localtime(&reftime); + SHA1Init(&ctxt); + SHA1Update(&ctxt, pn_secret, strlen(pn_secret)); + strftime(tbuf, sizeof (tbuf), "%Y%m%d", tp); + SHA1Update(&ctxt, tbuf, strlen(tbuf)); + SHA1Final(dig, &ctxt); + /* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */ + return (DesSetkey(dig)); +} + +static char base64[] = +"ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + +struct b64state { + u32_t bs_bits; + int bs_offs; +}; + +static int +b64enc(bs, inp, inlen, outp) +struct b64state *bs; +u_char *inp; +int inlen; +u_char *outp; +{ + int outlen = 0; + + while (inlen > 0) { + bs->bs_bits = (bs->bs_bits << 8) | *inp++; + inlen--; + bs->bs_offs += 8; + if (bs->bs_offs >= 24) { + *outp++ = base64[(bs->bs_bits >> 18) & 0x3F]; + *outp++ = base64[(bs->bs_bits >> 12) & 0x3F]; + *outp++ = base64[(bs->bs_bits >> 6) & 0x3F]; + *outp++ = base64[bs->bs_bits & 0x3F]; + outlen += 4; + bs->bs_offs = 0; + bs->bs_bits = 0; + } + } + return (outlen); +} + +static int +b64flush(bs, outp) +struct b64state *bs; +u_char *outp; +{ + int outlen = 0; + + if (bs->bs_offs == 8) { + *outp++ = base64[(bs->bs_bits >> 2) & 0x3F]; + *outp++ = base64[(bs->bs_bits << 4) & 0x3F]; + outlen = 2; + } else if (bs->bs_offs == 16) { + *outp++ = base64[(bs->bs_bits >> 10) & 0x3F]; + *outp++ = base64[(bs->bs_bits >> 4) & 0x3F]; + *outp++ = base64[(bs->bs_bits << 2) & 0x3F]; + outlen = 3; + } + bs->bs_offs = 0; + bs->bs_bits = 0; + return (outlen); +} + +static int +b64dec(bs, inp, inlen, outp) +struct b64state *bs; +u_char *inp; +int inlen; +u_char *outp; +{ + int outlen = 0; + char *cp; + + while (inlen > 0) { + if ((cp = strchr(base64, *inp++)) == NULL) + break; + bs->bs_bits = (bs->bs_bits << 6) | (cp - base64); + inlen--; + bs->bs_offs += 6; + if (bs->bs_offs >= 8) { + *outp++ = bs->bs_bits >> (bs->bs_offs - 8); + outlen++; + bs->bs_offs -= 8; + } + } + return (outlen); +} +#endif /* USE_SRP */ + +#if PPP_SERVER +/* + * Assume that current waiting server state is complete and figure + * next state to use based on available authentication data. 'status' + * indicates if there was an error in handling the last query. It is + * 0 for success and non-zero for failure. + */ +static void eap_figure_next_state(ppp_pcb *pcb, int status) { +#ifdef USE_SRP + unsigned char secbuf[MAXSECRETLEN], clear[8], *sp, *dp; + struct t_pw tpw; + struct t_confent *tce, mytce; + char *cp, *cp2; + struct t_server *ts; + int id, i, plen, toffs; + u_char vals[2]; + struct b64state bs; +#endif /* USE_SRP */ + + pcb->settings.eap_timeout_time = pcb->eap.es_savedtime; + switch (pcb->eap.es_server.ea_state) { + case eapBadAuth: + return; + + case eapIdentify: +#ifdef USE_SRP + /* Discard any previous session. */ + ts = (struct t_server *)pcb->eap.es_server.ea_session; + if (ts != NULL) { + t_serverclose(ts); + pcb->eap.es_server.ea_session = NULL; + pcb->eap.es_server.ea_skey = NULL; + } +#endif /* USE_SRP */ + if (status != 0) { + pcb->eap.es_server.ea_state = eapBadAuth; + break; + } +#ifdef USE_SRP + /* If we've got a pseudonym, try to decode to real name. */ + if (pcb->eap.es_server.ea_peerlen > SRP_PSEUDO_LEN && + strncmp(pcb->eap.es_server.ea_peer, SRP_PSEUDO_ID, + SRP_PSEUDO_LEN) == 0 && + (pcb->eap.es_server.ea_peerlen - SRP_PSEUDO_LEN) * 3 / 4 < + sizeof (secbuf)) { + BZERO(&bs, sizeof (bs)); + plen = b64dec(&bs, + pcb->eap.es_server.ea_peer + SRP_PSEUDO_LEN, + pcb->eap.es_server.ea_peerlen - SRP_PSEUDO_LEN, + secbuf); + toffs = 0; + for (i = 0; i < 5; i++) { + pncrypt_setkey(toffs); + toffs -= 86400; + /* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */ + if (!DesDecrypt(secbuf, clear)) { + ppp_dbglog("no DES here; cannot decode " + "pseudonym"); + return; + } + id = *(unsigned char *)clear; + if (id + 1 <= plen && id + 9 > plen) + break; + } + if (plen % 8 == 0 && i < 5) { + /* + * Note that this is always shorter than the + * original stored string, so there's no need + * to realloc. + */ + if ((i = plen = *(unsigned char *)clear) > 7) + i = 7; + pcb->eap.es_server.ea_peerlen = plen; + dp = (unsigned char *)pcb->eap.es_server.ea_peer; + MEMCPY(dp, clear + 1, i); + plen -= i; + dp += i; + sp = secbuf + 8; + while (plen > 0) { + /* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */ + (void) DesDecrypt(sp, dp); + sp += 8; + dp += 8; + plen -= 8; + } + pcb->eap.es_server.ea_peer[ + pcb->eap.es_server.ea_peerlen] = '\0'; + ppp_dbglog("decoded pseudonym to \"%.*q\"", + pcb->eap.es_server.ea_peerlen, + pcb->eap.es_server.ea_peer); + } else { + ppp_dbglog("failed to decode real name"); + /* Stay in eapIdentfy state; requery */ + break; + } + } + /* Look up user in secrets database. */ + if (get_srp_secret(pcb->eap.es_unit, pcb->eap.es_server.ea_peer, + pcb->eap.es_server.ea_name, (char *)secbuf, 1) != 0) { + /* Set up default in case SRP entry is bad */ + pcb->eap.es_server.ea_state = eapMD5Chall; + /* Get t_confent based on index in srp-secrets */ + id = strtol((char *)secbuf, &cp, 10); + if (*cp++ != ':' || id < 0) + break; + if (id == 0) { + mytce.index = 0; + mytce.modulus.data = (u_char *)wkmodulus; + mytce.modulus.len = sizeof (wkmodulus); + mytce.generator.data = (u_char *)"\002"; + mytce.generator.len = 1; + tce = &mytce; + } else if ((tce = gettcid(id)) != NULL) { + /* + * Client will have to verify this modulus/ + * generator combination, and that will take + * a while. Lengthen the timeout here. + */ + if (pcb->settings.eap_timeout_time > 0 && + pcb->settings.eap_timeout_time < 30) + pcb->settings.eap_timeout_time = 30; + } else { + break; + } + if ((cp2 = strchr(cp, ':')) == NULL) + break; + *cp2++ = '\0'; + tpw.pebuf.name = pcb->eap.es_server.ea_peer; + tpw.pebuf.password.len = t_fromb64((char *)tpw.pwbuf, + cp); + tpw.pebuf.password.data = tpw.pwbuf; + tpw.pebuf.salt.len = t_fromb64((char *)tpw.saltbuf, + cp2); + tpw.pebuf.salt.data = tpw.saltbuf; + if ((ts = t_serveropenraw(&tpw.pebuf, tce)) == NULL) + break; + pcb->eap.es_server.ea_session = (void *)ts; + pcb->eap.es_server.ea_state = eapSRP1; + vals[0] = pcb->eap.es_server.ea_id + 1; + vals[1] = EAPT_SRP; + t_serveraddexdata(ts, vals, 2); + /* Generate B; must call before t_servergetkey() */ + t_servergenexp(ts); + break; + } +#endif /* USE_SRP */ + pcb->eap.es_server.ea_state = eapMD5Chall; + break; + + case eapSRP1: +#ifdef USE_SRP + ts = (struct t_server *)pcb->eap.es_server.ea_session; + if (ts != NULL && status != 0) { + t_serverclose(ts); + pcb->eap.es_server.ea_session = NULL; + pcb->eap.es_server.ea_skey = NULL; + } +#endif /* USE_SRP */ + if (status == 1) { + pcb->eap.es_server.ea_state = eapMD5Chall; + } else if (status != 0 || pcb->eap.es_server.ea_session == NULL) { + pcb->eap.es_server.ea_state = eapBadAuth; + } else { + pcb->eap.es_server.ea_state = eapSRP2; + } + break; + + case eapSRP2: +#ifdef USE_SRP + ts = (struct t_server *)pcb->eap.es_server.ea_session; + if (ts != NULL && status != 0) { + t_serverclose(ts); + pcb->eap.es_server.ea_session = NULL; + pcb->eap.es_server.ea_skey = NULL; + } +#endif /* USE_SRP */ + if (status != 0 || pcb->eap.es_server.ea_session == NULL) { + pcb->eap.es_server.ea_state = eapBadAuth; + } else { + pcb->eap.es_server.ea_state = eapSRP3; + } + break; + + case eapSRP3: + case eapSRP4: +#ifdef USE_SRP + ts = (struct t_server *)pcb->eap.es_server.ea_session; + if (ts != NULL && status != 0) { + t_serverclose(ts); + pcb->eap.es_server.ea_session = NULL; + pcb->eap.es_server.ea_skey = NULL; + } +#endif /* USE_SRP */ + if (status != 0 || pcb->eap.es_server.ea_session == NULL) { + pcb->eap.es_server.ea_state = eapBadAuth; + } else { + pcb->eap.es_server.ea_state = eapOpen; + } + break; + + case eapMD5Chall: + if (status != 0) { + pcb->eap.es_server.ea_state = eapBadAuth; + } else { + pcb->eap.es_server.ea_state = eapOpen; + } + break; + + default: + pcb->eap.es_server.ea_state = eapBadAuth; + break; + } + if (pcb->eap.es_server.ea_state == eapBadAuth) + eap_send_failure(pcb); +} + +/* + * Format an EAP Request message and send it to the peer. Message + * type depends on current state. (Server operation) + */ +static void eap_send_request(ppp_pcb *pcb) { + struct pbuf *p; + u_char *outp; + u_char *lenloc; + int outlen; + int len; + const char *str; +#ifdef USE_SRP + struct t_server *ts; + u_char clear[8], cipher[8], dig[SHA_DIGESTSIZE], *optr, *cp; + int i, j; + struct b64state b64; + SHA1_CTX ctxt; +#endif /* USE_SRP */ + + /* Handle both initial auth and restart */ + if (pcb->eap.es_server.ea_state < eapIdentify && + pcb->eap.es_server.ea_state != eapInitial) { + pcb->eap.es_server.ea_state = eapIdentify; +#if PPP_REMOTENAME + if (pcb->settings.explicit_remote && pcb->remote_name) { + /* + * If we already know the peer's + * unauthenticated name, then there's no + * reason to ask. Go to next state instead. + */ + int len = (int)strlen(pcb->remote_name); + if (len > MAXNAMELEN) { + len = MAXNAMELEN; + } + MEMCPY(pcb->eap.es_server.ea_peer, pcb->remote_name, len); + pcb->eap.es_server.ea_peer[len] = '\0'; + pcb->eap.es_server.ea_peerlen = len; + eap_figure_next_state(pcb, 0); + } +#endif /* PPP_REMOTENAME */ + } + + if (pcb->settings.eap_max_transmits > 0 && + pcb->eap.es_server.ea_requests >= pcb->settings.eap_max_transmits) { + if (pcb->eap.es_server.ea_responses > 0) + ppp_error("EAP: too many Requests sent"); + else + ppp_error("EAP: no response to Requests"); + eap_send_failure(pcb); + return; + } + + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_CTRL_PBUF_MAX_SIZE), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_REQUEST, outp); + PUTCHAR(pcb->eap.es_server.ea_id, outp); + lenloc = outp; + INCPTR(2, outp); + + switch (pcb->eap.es_server.ea_state) { + case eapIdentify: + PUTCHAR(EAPT_IDENTITY, outp); + str = "Name"; + len = strlen(str); + MEMCPY(outp, str, len); + INCPTR(len, outp); + break; + + case eapMD5Chall: + PUTCHAR(EAPT_MD5CHAP, outp); + /* + * pick a random challenge length between + * EAP_MIN_CHALLENGE_LENGTH and EAP_MAX_CHALLENGE_LENGTH + */ + pcb->eap.es_challen = EAP_MIN_CHALLENGE_LENGTH + + magic_pow(EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH); + PUTCHAR(pcb->eap.es_challen, outp); + magic_random_bytes(pcb->eap.es_challenge, pcb->eap.es_challen); + MEMCPY(outp, pcb->eap.es_challenge, pcb->eap.es_challen); + INCPTR(pcb->eap.es_challen, outp); + MEMCPY(outp, pcb->eap.es_server.ea_name, pcb->eap.es_server.ea_namelen); + INCPTR(pcb->eap.es_server.ea_namelen, outp); + break; + +#ifdef USE_SRP + case eapSRP1: + PUTCHAR(EAPT_SRP, outp); + PUTCHAR(EAPSRP_CHALLENGE, outp); + + PUTCHAR(pcb->eap.es_server.ea_namelen, outp); + MEMCPY(outp, pcb->eap.es_server.ea_name, pcb->eap.es_server.ea_namelen); + INCPTR(pcb->eap.es_server.ea_namelen, outp); + + ts = (struct t_server *)pcb->eap.es_server.ea_session; + assert(ts != NULL); + PUTCHAR(ts->s.len, outp); + MEMCPY(outp, ts->s.data, ts->s.len); + INCPTR(ts->s.len, outp); + + if (ts->g.len == 1 && ts->g.data[0] == 2) { + PUTCHAR(0, outp); + } else { + PUTCHAR(ts->g.len, outp); + MEMCPY(outp, ts->g.data, ts->g.len); + INCPTR(ts->g.len, outp); + } + + if (ts->n.len != sizeof (wkmodulus) || + BCMP(ts->n.data, wkmodulus, sizeof (wkmodulus)) != 0) { + MEMCPY(outp, ts->n.data, ts->n.len); + INCPTR(ts->n.len, outp); + } + break; + + case eapSRP2: + PUTCHAR(EAPT_SRP, outp); + PUTCHAR(EAPSRP_SKEY, outp); + + ts = (struct t_server *)pcb->eap.es_server.ea_session; + assert(ts != NULL); + MEMCPY(outp, ts->B.data, ts->B.len); + INCPTR(ts->B.len, outp); + break; + + case eapSRP3: + PUTCHAR(EAPT_SRP, outp); + PUTCHAR(EAPSRP_SVALIDATOR, outp); + PUTLONG(SRPVAL_EBIT, outp); + ts = (struct t_server *)pcb->eap.es_server.ea_session; + assert(ts != NULL); + MEMCPY(outp, t_serverresponse(ts), SHA_DIGESTSIZE); + INCPTR(SHA_DIGESTSIZE, outp); + + if (pncrypt_setkey(0)) { + /* Generate pseudonym */ + optr = outp; + cp = (unsigned char *)pcb->eap.es_server.ea_peer; + if ((j = i = pcb->eap.es_server.ea_peerlen) > 7) + j = 7; + clear[0] = i; + MEMCPY(clear + 1, cp, j); + i -= j; + cp += j; + /* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */ + if (!DesEncrypt(clear, cipher)) { + ppp_dbglog("no DES here; not generating pseudonym"); + break; + } + BZERO(&b64, sizeof (b64)); + outp++; /* space for pseudonym length */ + outp += b64enc(&b64, cipher, 8, outp); + while (i >= 8) { + /* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */ + (void) DesEncrypt(cp, cipher); + outp += b64enc(&b64, cipher, 8, outp); + cp += 8; + i -= 8; + } + if (i > 0) { + MEMCPY(clear, cp, i); + cp += i; + magic_random_bytes(cp, 8-i); + /* FIXME: if we want to do SRP, we need to find a way to pass the PolarSSL des_context instead of using static memory */ + (void) DesEncrypt(clear, cipher); + outp += b64enc(&b64, cipher, 8, outp); + } + outp += b64flush(&b64, outp); + + /* Set length and pad out to next 20 octet boundary */ + i = outp - optr - 1; + *optr = i; + i %= SHA_DIGESTSIZE; + if (i != 0) { + magic_random_bytes(outp, SHA_DIGESTSIZE-i); + INCPTR(SHA_DIGESTSIZE-i, outp); + } + + /* Obscure the pseudonym with SHA1 hash */ + SHA1Init(&ctxt); + SHA1Update(&ctxt, &pcb->eap.es_server.ea_id, 1); + SHA1Update(&ctxt, pcb->eap.es_server.ea_skey, + SESSION_KEY_LEN); + SHA1Update(&ctxt, pcb->eap.es_server.ea_peer, + pcb->eap.es_server.ea_peerlen); + while (optr < outp) { + SHA1Final(dig, &ctxt); + cp = dig; + while (cp < dig + SHA_DIGESTSIZE) + *optr++ ^= *cp++; + SHA1Init(&ctxt); + SHA1Update(&ctxt, &pcb->eap.es_server.ea_id, 1); + SHA1Update(&ctxt, pcb->eap.es_server.ea_skey, + SESSION_KEY_LEN); + SHA1Update(&ctxt, optr - SHA_DIGESTSIZE, + SHA_DIGESTSIZE); + } + } + break; + + case eapSRP4: + PUTCHAR(EAPT_SRP, outp); + PUTCHAR(EAPSRP_LWRECHALLENGE, outp); + pcb->eap.es_challen = EAP_MIN_CHALLENGE_LENGTH + + magic_pow(EAP_MIN_MAX_POWER_OF_TWO_CHALLENGE_LENGTH); + magic_random_bytes(pcb->eap.es_challenge, pcb->eap.es_challen); + MEMCPY(outp, pcb->eap.es_challenge, pcb->eap.es_challen); + INCPTR(pcb->eap.es_challen, outp); + break; +#endif /* USE_SRP */ + + default: + return; + } + + outlen = (outp - (unsigned char*)p->payload) - PPP_HDRLEN; + PUTSHORT(outlen, lenloc); + + pbuf_realloc(p, outlen + PPP_HDRLEN); + ppp_write(pcb, p); + + pcb->eap.es_server.ea_requests++; + + if (pcb->settings.eap_timeout_time > 0) + TIMEOUT(eap_server_timeout, pcb, pcb->settings.eap_timeout_time); +} + +/* + * eap_authpeer - Authenticate our peer (behave as server). + * + * Start server state and send first request. This is called only + * after eap_lowerup. + */ +void eap_authpeer(ppp_pcb *pcb, const char *localname) { + + /* Save the name we're given. */ + pcb->eap.es_server.ea_name = localname; + pcb->eap.es_server.ea_namelen = strlen(localname); + + pcb->eap.es_savedtime = pcb->settings.eap_timeout_time; + + /* Lower layer up yet? */ + if (pcb->eap.es_server.ea_state == eapInitial || + pcb->eap.es_server.ea_state == eapPending) { + pcb->eap.es_server.ea_state = eapPending; + return; + } + + pcb->eap.es_server.ea_state = eapPending; + + /* ID number not updated here intentionally; hashed into M1 */ + eap_send_request(pcb); +} + +/* + * eap_server_timeout - Retransmission timer for sending Requests + * expired. + */ +static void eap_server_timeout(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + + if (!eap_server_active(pcb)) + return; + + /* EAP ID number must not change on timeout. */ + eap_send_request(pcb); +} + +/* + * When it's time to send rechallenge the peer, this timeout is + * called. Once the rechallenge is successful, the response handler + * will restart the timer. If it fails, then the link is dropped. + */ +static void eap_rechallenge(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + + if (pcb->eap.es_server.ea_state != eapOpen && + pcb->eap.es_server.ea_state != eapSRP4) + return; + + pcb->eap.es_server.ea_requests = 0; + pcb->eap.es_server.ea_state = eapIdentify; + eap_figure_next_state(pcb, 0); + pcb->eap.es_server.ea_id++; + eap_send_request(pcb); +} + +static void srp_lwrechallenge(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + + if (pcb->eap.es_server.ea_state != eapOpen || + pcb->eap.es_server.ea_type != EAPT_SRP) + return; + + pcb->eap.es_server.ea_requests = 0; + pcb->eap.es_server.ea_state = eapSRP4; + pcb->eap.es_server.ea_id++; + eap_send_request(pcb); +} +#endif /* PPP_SERVER */ + +/* + * eap_lowerup - The lower layer is now up. + * + * This is called before either eap_authpeer or eap_authwithpeer. See + * link_established() in auth.c. All that's necessary here is to + * return to closed state so that those two routines will do the right + * thing. + */ +static void eap_lowerup(ppp_pcb *pcb) { + pcb->eap.es_client.ea_state = eapClosed; +#if PPP_SERVER + pcb->eap.es_server.ea_state = eapClosed; +#endif /* PPP_SERVER */ +} + +/* + * eap_lowerdown - The lower layer is now down. + * + * Cancel all timeouts and return to initial state. + */ +static void eap_lowerdown(ppp_pcb *pcb) { + + if (eap_client_active(pcb) && pcb->settings.eap_req_time > 0) { + UNTIMEOUT(eap_client_timeout, pcb); + } +#if PPP_SERVER + if (eap_server_active(pcb)) { + if (pcb->settings.eap_timeout_time > 0) { + UNTIMEOUT(eap_server_timeout, pcb); + } + } else { + if ((pcb->eap.es_server.ea_state == eapOpen || + pcb->eap.es_server.ea_state == eapSRP4) && + pcb->eap.es_rechallenge > 0) { + UNTIMEOUT(eap_rechallenge, (void *)pcb); + } + if (pcb->eap.es_server.ea_state == eapOpen && + pcb->eap.es_lwrechallenge > 0) { + UNTIMEOUT(srp_lwrechallenge, (void *)pcb); + } + } + + pcb->eap.es_client.ea_state = pcb->eap.es_server.ea_state = eapInitial; + pcb->eap.es_client.ea_requests = pcb->eap.es_server.ea_requests = 0; +#endif /* PPP_SERVER */ +} + +/* + * eap_protrej - Peer doesn't speak this protocol. + * + * This shouldn't happen. If it does, it represents authentication + * failure. + */ +static void eap_protrej(ppp_pcb *pcb) { + + if (eap_client_active(pcb)) { + ppp_error("EAP authentication failed due to Protocol-Reject"); + auth_withpeer_fail(pcb, PPP_EAP); + } +#if PPP_SERVER + if (eap_server_active(pcb)) { + ppp_error("EAP authentication of peer failed on Protocol-Reject"); + auth_peer_fail(pcb, PPP_EAP); + } +#endif /* PPP_SERVER */ + eap_lowerdown(pcb); +} + +/* + * Format and send a regular EAP Response message. + */ +static void eap_send_response(ppp_pcb *pcb, u_char id, u_char typenum, const u_char *str, int lenstr) { + struct pbuf *p; + u_char *outp; + int msglen; + + msglen = EAP_HEADERLEN + sizeof (u_char) + lenstr; + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_RESPONSE, outp); + PUTCHAR(id, outp); + pcb->eap.es_client.ea_id = id; + PUTSHORT(msglen, outp); + PUTCHAR(typenum, outp); + if (lenstr > 0) { + MEMCPY(outp, str, lenstr); + } + + ppp_write(pcb, p); +} + +/* + * Format and send an MD5-Challenge EAP Response message. + */ +static void eap_chap_response(ppp_pcb *pcb, u_char id, u_char *hash, const char *name, int namelen) { + struct pbuf *p; + u_char *outp; + int msglen; + + msglen = EAP_HEADERLEN + 2 * sizeof (u_char) + MD5_SIGNATURE_SIZE + + namelen; + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_RESPONSE, outp); + PUTCHAR(id, outp); + pcb->eap.es_client.ea_id = id; + PUTSHORT(msglen, outp); + PUTCHAR(EAPT_MD5CHAP, outp); + PUTCHAR(MD5_SIGNATURE_SIZE, outp); + MEMCPY(outp, hash, MD5_SIGNATURE_SIZE); + INCPTR(MD5_SIGNATURE_SIZE, outp); + if (namelen > 0) { + MEMCPY(outp, name, namelen); + } + + ppp_write(pcb, p); +} + +#ifdef USE_SRP +/* + * Format and send a SRP EAP Response message. + */ +static void +eap_srp_response(esp, id, subtypenum, str, lenstr) +eap_state *esp; +u_char id; +u_char subtypenum; +u_char *str; +int lenstr; +{ + ppp_pcb *pcb = &ppp_pcb_list[pcb->eap.es_unit]; + struct pbuf *p; + u_char *outp; + int msglen; + + msglen = EAP_HEADERLEN + 2 * sizeof (u_char) + lenstr; + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_RESPONSE, outp); + PUTCHAR(id, outp); + pcb->eap.es_client.ea_id = id; + PUTSHORT(msglen, outp); + PUTCHAR(EAPT_SRP, outp); + PUTCHAR(subtypenum, outp); + if (lenstr > 0) { + MEMCPY(outp, str, lenstr); + } + + ppp_write(pcb, p); +} + +/* + * Format and send a SRP EAP Client Validator Response message. + */ +static void +eap_srpval_response(esp, id, flags, str) +eap_state *esp; +u_char id; +u32_t flags; +u_char *str; +{ + ppp_pcb *pcb = &ppp_pcb_list[pcb->eap.es_unit]; + struct pbuf *p; + u_char *outp; + int msglen; + + msglen = EAP_HEADERLEN + 2 * sizeof (u_char) + sizeof (u32_t) + + SHA_DIGESTSIZE; + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_RESPONSE, outp); + PUTCHAR(id, outp); + pcb->eap.es_client.ea_id = id; + PUTSHORT(msglen, outp); + PUTCHAR(EAPT_SRP, outp); + PUTCHAR(EAPSRP_CVALIDATOR, outp); + PUTLONG(flags, outp); + MEMCPY(outp, str, SHA_DIGESTSIZE); + + ppp_write(pcb, p); +} +#endif /* USE_SRP */ + +static void eap_send_nak(ppp_pcb *pcb, u_char id, u_char type) { + struct pbuf *p; + u_char *outp; + int msglen; + + msglen = EAP_HEADERLEN + 2 * sizeof (u_char); + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN + msglen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + + MAKEHEADER(outp, PPP_EAP); + + PUTCHAR(EAP_RESPONSE, outp); + PUTCHAR(id, outp); + pcb->eap.es_client.ea_id = id; + PUTSHORT(msglen, outp); + PUTCHAR(EAPT_NAK, outp); + PUTCHAR(type, outp); + + ppp_write(pcb, p); +} + +#ifdef USE_SRP +static char * +name_of_pn_file() +{ + char *user, *path, *file; + struct passwd *pw; + size_t pl; + static bool pnlogged = 0; + + pw = getpwuid(getuid()); + if (pw == NULL || (user = pw->pw_dir) == NULL || user[0] == 0) { + errno = EINVAL; + return (NULL); + } + file = _PATH_PSEUDONYM; + pl = strlen(user) + strlen(file) + 2; + path = malloc(pl); + if (path == NULL) + return (NULL); + (void) slprintf(path, pl, "%s/%s", user, file); + if (!pnlogged) { + ppp_dbglog("pseudonym file: %s", path); + pnlogged = 1; + } + return (path); +} + +static int +open_pn_file(modebits) +mode_t modebits; +{ + char *path; + int fd, err; + + if ((path = name_of_pn_file()) == NULL) + return (-1); + fd = open(path, modebits, S_IRUSR | S_IWUSR); + err = errno; + free(path); + errno = err; + return (fd); +} + +static void +remove_pn_file() +{ + char *path; + + if ((path = name_of_pn_file()) != NULL) { + (void) unlink(path); + (void) free(path); + } +} + +static void +write_pseudonym(esp, inp, len, id) +eap_state *esp; +u_char *inp; +int len, id; +{ + u_char val; + u_char *datp, *digp; + SHA1_CTX ctxt; + u_char dig[SHA_DIGESTSIZE]; + int dsize, fd, olen = len; + + /* + * Do the decoding by working backwards. This eliminates the need + * to save the decoded output in a separate buffer. + */ + val = id; + while (len > 0) { + if ((dsize = len % SHA_DIGESTSIZE) == 0) + dsize = SHA_DIGESTSIZE; + len -= dsize; + datp = inp + len; + SHA1Init(&ctxt); + SHA1Update(&ctxt, &val, 1); + SHA1Update(&ctxt, pcb->eap.es_client.ea_skey, SESSION_KEY_LEN); + if (len > 0) { + SHA1Update(&ctxt, datp, SHA_DIGESTSIZE); + } else { + SHA1Update(&ctxt, pcb->eap.es_client.ea_name, + pcb->eap.es_client.ea_namelen); + } + SHA1Final(dig, &ctxt); + for (digp = dig; digp < dig + SHA_DIGESTSIZE; digp++) + *datp++ ^= *digp; + } + + /* Now check that the result is sane */ + if (olen <= 0 || *inp + 1 > olen) { + ppp_dbglog("EAP: decoded pseudonym is unusable <%.*B>", olen, inp); + return; + } + + /* Save it away */ + fd = open_pn_file(O_WRONLY | O_CREAT | O_TRUNC); + if (fd < 0) { + ppp_dbglog("EAP: error saving pseudonym: %m"); + return; + } + len = write(fd, inp + 1, *inp); + if (close(fd) != -1 && len == *inp) { + ppp_dbglog("EAP: saved pseudonym"); + pcb->eap.es_usedpseudo = 0; + } else { + ppp_dbglog("EAP: failed to save pseudonym"); + remove_pn_file(); + } +} +#endif /* USE_SRP */ + +/* + * eap_request - Receive EAP Request message (client mode). + */ +static void eap_request(ppp_pcb *pcb, u_char *inp, int id, int len) { + u_char typenum; + u_char vallen; + int secret_len; + char secret[MAXSECRETLEN]; + char rhostname[MAXNAMELEN]; + lwip_md5_context mdContext; + u_char hash[MD5_SIGNATURE_SIZE]; +#ifdef USE_SRP + struct t_client *tc; + struct t_num sval, gval, Nval, *Ap, Bval; + u_char vals[2]; + SHA1_CTX ctxt; + u_char dig[SHA_DIGESTSIZE]; + int fd; +#endif /* USE_SRP */ + + /* + * Note: we update es_client.ea_id *only if* a Response + * message is being generated. Otherwise, we leave it the + * same for duplicate detection purposes. + */ + + pcb->eap.es_client.ea_requests++; + if (pcb->settings.eap_allow_req != 0 && + pcb->eap.es_client.ea_requests > pcb->settings.eap_allow_req) { + ppp_info("EAP: received too many Request messages"); + if (pcb->settings.eap_req_time > 0) { + UNTIMEOUT(eap_client_timeout, pcb); + } + auth_withpeer_fail(pcb, PPP_EAP); + return; + } + + if (len <= 0) { + ppp_error("EAP: empty Request message discarded"); + return; + } + + GETCHAR(typenum, inp); + len--; + + switch (typenum) { + case EAPT_IDENTITY: + if (len > 0) + ppp_info("EAP: Identity prompt \"%.*q\"", len, inp); +#ifdef USE_SRP + if (pcb->eap.es_usepseudo && + (pcb->eap.es_usedpseudo == 0 || + (pcb->eap.es_usedpseudo == 1 && + id == pcb->eap.es_client.ea_id))) { + pcb->eap.es_usedpseudo = 1; + /* Try to get a pseudonym */ + if ((fd = open_pn_file(O_RDONLY)) >= 0) { + strcpy(rhostname, SRP_PSEUDO_ID); + len = read(fd, rhostname + SRP_PSEUDO_LEN, + sizeof (rhostname) - SRP_PSEUDO_LEN); + /* XXX NAI unsupported */ + if (len > 0) { + eap_send_response(pcb, id, typenum, + rhostname, len + SRP_PSEUDO_LEN); + } + (void) close(fd); + if (len > 0) + break; + } + } + /* Stop using pseudonym now. */ + if (pcb->eap.es_usepseudo && pcb->eap.es_usedpseudo != 2) { + remove_pn_file(); + pcb->eap.es_usedpseudo = 2; + } +#endif /* USE_SRP */ + eap_send_response(pcb, id, typenum, (const u_char*)pcb->eap.es_client.ea_name, + pcb->eap.es_client.ea_namelen); + break; + + case EAPT_NOTIFICATION: + if (len > 0) + ppp_info("EAP: Notification \"%.*q\"", len, inp); + eap_send_response(pcb, id, typenum, NULL, 0); + break; + + case EAPT_NAK: + /* + * Avoid the temptation to send Response Nak in reply + * to Request Nak here. It can only lead to trouble. + */ + ppp_warn("EAP: unexpected Nak in Request; ignored"); + /* Return because we're waiting for something real. */ + return; + + case EAPT_MD5CHAP: + if (len < 1) { + ppp_error("EAP: received MD5-Challenge with no data"); + /* Bogus request; wait for something real. */ + return; + } + GETCHAR(vallen, inp); + len--; + if (vallen < 8 || vallen > len) { + ppp_error("EAP: MD5-Challenge with bad length %d (8..%d)", + vallen, len); + /* Try something better. */ + eap_send_nak(pcb, id, EAPT_SRP); + break; + } + + /* Not so likely to happen. */ + if (vallen >= len + sizeof (rhostname)) { + ppp_dbglog("EAP: trimming really long peer name down"); + MEMCPY(rhostname, inp + vallen, sizeof (rhostname) - 1); + rhostname[sizeof (rhostname) - 1] = '\0'; + } else { + MEMCPY(rhostname, inp + vallen, len - vallen); + rhostname[len - vallen] = '\0'; + } + +#if PPP_REMOTENAME + /* In case the remote doesn't give us his name. */ + if (pcb->settings.explicit_remote || + (pcb->settings.remote_name[0] != '\0' && vallen == len)) + strlcpy(rhostname, pcb->settings.remote_name, sizeof (rhostname)); +#endif /* PPP_REMOTENAME */ + + /* + * Get the secret for authenticating ourselves with + * the specified host. + */ + if (!get_secret(pcb, pcb->eap.es_client.ea_name, + rhostname, secret, &secret_len, 0)) { + ppp_dbglog("EAP: no MD5 secret for auth to %q", rhostname); + eap_send_nak(pcb, id, EAPT_SRP); + break; + } + lwip_md5_init(&mdContext); + lwip_md5_starts(&mdContext); + typenum = id; + lwip_md5_update(&mdContext, &typenum, 1); + lwip_md5_update(&mdContext, (u_char *)secret, secret_len); + BZERO(secret, sizeof (secret)); + lwip_md5_update(&mdContext, inp, vallen); + lwip_md5_finish(&mdContext, hash); + lwip_md5_free(&mdContext); + eap_chap_response(pcb, id, hash, pcb->eap.es_client.ea_name, + pcb->eap.es_client.ea_namelen); + break; + +#ifdef USE_SRP + case EAPT_SRP: + if (len < 1) { + ppp_error("EAP: received empty SRP Request"); + /* Bogus request; wait for something real. */ + return; + } + + /* Get subtype */ + GETCHAR(vallen, inp); + len--; + switch (vallen) { + case EAPSRP_CHALLENGE: + tc = NULL; + if (pcb->eap.es_client.ea_session != NULL) { + tc = (struct t_client *)pcb->eap.es_client. + ea_session; + /* + * If this is a new challenge, then start + * over with a new client session context. + * Otherwise, just resend last response. + */ + if (id != pcb->eap.es_client.ea_id) { + t_clientclose(tc); + pcb->eap.es_client.ea_session = NULL; + tc = NULL; + } + } + /* No session key just yet */ + pcb->eap.es_client.ea_skey = NULL; + if (tc == NULL) { + int rhostnamelen; + + GETCHAR(vallen, inp); + len--; + if (vallen >= len) { + ppp_error("EAP: badly-formed SRP Challenge" + " (name)"); + /* Ignore badly-formed messages */ + return; + } + MEMCPY(rhostname, inp, vallen); + rhostname[vallen] = '\0'; + INCPTR(vallen, inp); + len -= vallen; + + /* + * In case the remote doesn't give us his name, + * use configured name. + */ + if (explicit_remote || + (remote_name[0] != '\0' && vallen == 0)) { + strlcpy(rhostname, remote_name, + sizeof (rhostname)); + } + + rhostnamelen = (int)strlen(rhostname); + if (rhostnamelen > MAXNAMELEN) { + rhostnamelen = MAXNAMELEN; + } + MEMCPY(pcb->eap.es_client.ea_peer, rhostname, rhostnamelen); + pcb->eap.es_client.ea_peer[rhostnamelen] = '\0'; + pcb->eap.es_client.ea_peerlen = rhostnamelen; + + GETCHAR(vallen, inp); + len--; + if (vallen >= len) { + ppp_error("EAP: badly-formed SRP Challenge" + " (s)"); + /* Ignore badly-formed messages */ + return; + } + sval.data = inp; + sval.len = vallen; + INCPTR(vallen, inp); + len -= vallen; + + GETCHAR(vallen, inp); + len--; + if (vallen > len) { + ppp_error("EAP: badly-formed SRP Challenge" + " (g)"); + /* Ignore badly-formed messages */ + return; + } + /* If no generator present, then use value 2 */ + if (vallen == 0) { + gval.data = (u_char *)"\002"; + gval.len = 1; + } else { + gval.data = inp; + gval.len = vallen; + } + INCPTR(vallen, inp); + len -= vallen; + + /* + * If no modulus present, then use well-known + * value. + */ + if (len == 0) { + Nval.data = (u_char *)wkmodulus; + Nval.len = sizeof (wkmodulus); + } else { + Nval.data = inp; + Nval.len = len; + } + tc = t_clientopen(pcb->eap.es_client.ea_name, + &Nval, &gval, &sval); + if (tc == NULL) { + eap_send_nak(pcb, id, EAPT_MD5CHAP); + break; + } + pcb->eap.es_client.ea_session = (void *)tc; + + /* Add Challenge ID & type to verifier */ + vals[0] = id; + vals[1] = EAPT_SRP; + t_clientaddexdata(tc, vals, 2); + } + Ap = t_clientgenexp(tc); + eap_srp_response(esp, id, EAPSRP_CKEY, Ap->data, + Ap->len); + break; + + case EAPSRP_SKEY: + tc = (struct t_client *)pcb->eap.es_client.ea_session; + if (tc == NULL) { + ppp_warn("EAP: peer sent Subtype 2 without 1"); + eap_send_nak(pcb, id, EAPT_MD5CHAP); + break; + } + if (pcb->eap.es_client.ea_skey != NULL) { + /* + * ID number should not change here. Warn + * if it does (but otherwise ignore). + */ + if (id != pcb->eap.es_client.ea_id) { + ppp_warn("EAP: ID changed from %d to %d " + "in SRP Subtype 2 rexmit", + pcb->eap.es_client.ea_id, id); + } + } else { + if (get_srp_secret(pcb->eap.es_unit, + pcb->eap.es_client.ea_name, + pcb->eap.es_client.ea_peer, secret, 0) == 0) { + /* + * Can't work with this peer because + * the secret is missing. Just give + * up. + */ + eap_send_nak(pcb, id, EAPT_MD5CHAP); + break; + } + Bval.data = inp; + Bval.len = len; + t_clientpasswd(tc, secret); + BZERO(secret, sizeof (secret)); + pcb->eap.es_client.ea_skey = + t_clientgetkey(tc, &Bval); + if (pcb->eap.es_client.ea_skey == NULL) { + /* Server is rogue; stop now */ + ppp_error("EAP: SRP server is rogue"); + goto client_failure; + } + } + eap_srpval_response(esp, id, SRPVAL_EBIT, + t_clientresponse(tc)); + break; + + case EAPSRP_SVALIDATOR: + tc = (struct t_client *)pcb->eap.es_client.ea_session; + if (tc == NULL || pcb->eap.es_client.ea_skey == NULL) { + ppp_warn("EAP: peer sent Subtype 3 without 1/2"); + eap_send_nak(pcb, id, EAPT_MD5CHAP); + break; + } + /* + * If we're already open, then this ought to be a + * duplicate. Otherwise, check that the server is + * who we think it is. + */ + if (pcb->eap.es_client.ea_state == eapOpen) { + if (id != pcb->eap.es_client.ea_id) { + ppp_warn("EAP: ID changed from %d to %d " + "in SRP Subtype 3 rexmit", + pcb->eap.es_client.ea_id, id); + } + } else { + len -= sizeof (u32_t) + SHA_DIGESTSIZE; + if (len < 0 || t_clientverify(tc, inp + + sizeof (u32_t)) != 0) { + ppp_error("EAP: SRP server verification " + "failed"); + goto client_failure; + } + GETLONG(pcb->eap.es_client.ea_keyflags, inp); + /* Save pseudonym if user wants it. */ + if (len > 0 && pcb->eap.es_usepseudo) { + INCPTR(SHA_DIGESTSIZE, inp); + write_pseudonym(esp, inp, len, id); + } + } + /* + * We've verified our peer. We're now mostly done, + * except for waiting on the regular EAP Success + * message. + */ + eap_srp_response(esp, id, EAPSRP_ACK, NULL, 0); + break; + + case EAPSRP_LWRECHALLENGE: + if (len < 4) { + ppp_warn("EAP: malformed Lightweight rechallenge"); + return; + } + SHA1Init(&ctxt); + vals[0] = id; + SHA1Update(&ctxt, vals, 1); + SHA1Update(&ctxt, pcb->eap.es_client.ea_skey, + SESSION_KEY_LEN); + SHA1Update(&ctxt, inp, len); + SHA1Update(&ctxt, pcb->eap.es_client.ea_name, + pcb->eap.es_client.ea_namelen); + SHA1Final(dig, &ctxt); + eap_srp_response(esp, id, EAPSRP_LWRECHALLENGE, dig, + SHA_DIGESTSIZE); + break; + + default: + ppp_error("EAP: unknown SRP Subtype %d", vallen); + eap_send_nak(pcb, id, EAPT_MD5CHAP); + break; + } + break; +#endif /* USE_SRP */ + + default: + ppp_info("EAP: unknown authentication type %d; Naking", typenum); + eap_send_nak(pcb, id, EAPT_SRP); + break; + } + + if (pcb->settings.eap_req_time > 0) { + UNTIMEOUT(eap_client_timeout, pcb); + TIMEOUT(eap_client_timeout, pcb, + pcb->settings.eap_req_time); + } + return; + +#ifdef USE_SRP +client_failure: + pcb->eap.es_client.ea_state = eapBadAuth; + if (pcb->settings.eap_req_time > 0) { + UNTIMEOUT(eap_client_timeout, (void *)esp); + } + pcb->eap.es_client.ea_session = NULL; + t_clientclose(tc); + auth_withpeer_fail(pcb, PPP_EAP); +#endif /* USE_SRP */ +} + +#if PPP_SERVER +/* + * eap_response - Receive EAP Response message (server mode). + */ +static void eap_response(ppp_pcb *pcb, u_char *inp, int id, int len) { + u_char typenum; + u_char vallen; + int secret_len; + char secret[MAXSECRETLEN]; + char rhostname[MAXNAMELEN]; + lwip_md5_context mdContext; + u_char hash[MD5_SIGNATURE_SIZE]; +#ifdef USE_SRP + struct t_server *ts; + struct t_num A; + SHA1_CTX ctxt; + u_char dig[SHA_DIGESTSIZE]; +#endif /* USE_SRP */ + + if (pcb->eap.es_server.ea_id != id) { + ppp_dbglog("EAP: discarding Response %d; expected ID %d", id, + pcb->eap.es_server.ea_id); + return; + } + + pcb->eap.es_server.ea_responses++; + + if (len <= 0) { + ppp_error("EAP: empty Response message discarded"); + return; + } + + GETCHAR(typenum, inp); + len--; + + switch (typenum) { + case EAPT_IDENTITY: + if (pcb->eap.es_server.ea_state != eapIdentify) { + ppp_dbglog("EAP discarding unwanted Identify \"%.q\"", len, + inp); + break; + } + ppp_info("EAP: unauthenticated peer name \"%.*q\"", len, inp); + if (len > MAXNAMELEN) { + len = MAXNAMELEN; + } + MEMCPY(pcb->eap.es_server.ea_peer, inp, len); + pcb->eap.es_server.ea_peer[len] = '\0'; + pcb->eap.es_server.ea_peerlen = len; + eap_figure_next_state(pcb, 0); + break; + + case EAPT_NOTIFICATION: + ppp_dbglog("EAP unexpected Notification; response discarded"); + break; + + case EAPT_NAK: + if (len < 1) { + ppp_info("EAP: Nak Response with no suggested protocol"); + eap_figure_next_state(pcb, 1); + break; + } + + GETCHAR(vallen, inp); + len--; + + if ( +#if PPP_REMOTENAME + !pcb->explicit_remote && +#endif /* PPP_REMOTENAME */ + pcb->eap.es_server.ea_state == eapIdentify){ + /* Peer cannot Nak Identify Request */ + eap_figure_next_state(pcb, 1); + break; + } + + switch (vallen) { + case EAPT_SRP: + /* Run through SRP validator selection again. */ + pcb->eap.es_server.ea_state = eapIdentify; + eap_figure_next_state(pcb, 0); + break; + + case EAPT_MD5CHAP: + pcb->eap.es_server.ea_state = eapMD5Chall; + break; + + default: + ppp_dbglog("EAP: peer requesting unknown Type %d", vallen); + switch (pcb->eap.es_server.ea_state) { + case eapSRP1: + case eapSRP2: + case eapSRP3: + pcb->eap.es_server.ea_state = eapMD5Chall; + break; + case eapMD5Chall: + case eapSRP4: + pcb->eap.es_server.ea_state = eapIdentify; + eap_figure_next_state(pcb, 0); + break; + default: + break; + } + break; + } + break; + + case EAPT_MD5CHAP: + if (pcb->eap.es_server.ea_state != eapMD5Chall) { + ppp_error("EAP: unexpected MD5-Response"); + eap_figure_next_state(pcb, 1); + break; + } + if (len < 1) { + ppp_error("EAP: received MD5-Response with no data"); + eap_figure_next_state(pcb, 1); + break; + } + GETCHAR(vallen, inp); + len--; + if (vallen != 16 || vallen > len) { + ppp_error("EAP: MD5-Response with bad length %d", vallen); + eap_figure_next_state(pcb, 1); + break; + } + + /* Not so likely to happen. */ + if (vallen >= len + sizeof (rhostname)) { + ppp_dbglog("EAP: trimming really long peer name down"); + MEMCPY(rhostname, inp + vallen, sizeof (rhostname) - 1); + rhostname[sizeof (rhostname) - 1] = '\0'; + } else { + MEMCPY(rhostname, inp + vallen, len - vallen); + rhostname[len - vallen] = '\0'; + } + +#if PPP_REMOTENAME + /* In case the remote doesn't give us his name. */ + if (explicit_remote || + (remote_name[0] != '\0' && vallen == len)) + strlcpy(rhostname, remote_name, sizeof (rhostname)); +#endif /* PPP_REMOTENAME */ + + /* + * Get the secret for authenticating the specified + * host. + */ + if (!get_secret(pcb, rhostname, + pcb->eap.es_server.ea_name, secret, &secret_len, 1)) { + ppp_dbglog("EAP: no MD5 secret for auth of %q", rhostname); + eap_send_failure(pcb); + break; + } + lwip_md5_init(&mdContext); + lwip_md5_starts(&mdContext); + lwip_md5_update(&mdContext, &pcb->eap.es_server.ea_id, 1); + lwip_md5_update(&mdContext, (u_char *)secret, secret_len); + BZERO(secret, sizeof (secret)); + lwip_md5_update(&mdContext, pcb->eap.es_challenge, pcb->eap.es_challen); + lwip_md5_finish(&mdContext, hash); + lwip_md5_free(&mdContext); + if (BCMP(hash, inp, MD5_SIGNATURE_SIZE) != 0) { + eap_send_failure(pcb); + break; + } + pcb->eap.es_server.ea_type = EAPT_MD5CHAP; + eap_send_success(pcb); + eap_figure_next_state(pcb, 0); + if (pcb->eap.es_rechallenge != 0) + TIMEOUT(eap_rechallenge, pcb, pcb->eap.es_rechallenge); + break; + +#ifdef USE_SRP + case EAPT_SRP: + if (len < 1) { + ppp_error("EAP: empty SRP Response"); + eap_figure_next_state(pcb, 1); + break; + } + GETCHAR(typenum, inp); + len--; + switch (typenum) { + case EAPSRP_CKEY: + if (pcb->eap.es_server.ea_state != eapSRP1) { + ppp_error("EAP: unexpected SRP Subtype 1 Response"); + eap_figure_next_state(pcb, 1); + break; + } + A.data = inp; + A.len = len; + ts = (struct t_server *)pcb->eap.es_server.ea_session; + assert(ts != NULL); + pcb->eap.es_server.ea_skey = t_servergetkey(ts, &A); + if (pcb->eap.es_server.ea_skey == NULL) { + /* Client's A value is bogus; terminate now */ + ppp_error("EAP: bogus A value from client"); + eap_send_failure(pcb); + } else { + eap_figure_next_state(pcb, 0); + } + break; + + case EAPSRP_CVALIDATOR: + if (pcb->eap.es_server.ea_state != eapSRP2) { + ppp_error("EAP: unexpected SRP Subtype 2 Response"); + eap_figure_next_state(pcb, 1); + break; + } + if (len < sizeof (u32_t) + SHA_DIGESTSIZE) { + ppp_error("EAP: M1 length %d < %d", len, + sizeof (u32_t) + SHA_DIGESTSIZE); + eap_figure_next_state(pcb, 1); + break; + } + GETLONG(pcb->eap.es_server.ea_keyflags, inp); + ts = (struct t_server *)pcb->eap.es_server.ea_session; + assert(ts != NULL); + if (t_serververify(ts, inp)) { + ppp_info("EAP: unable to validate client identity"); + eap_send_failure(pcb); + break; + } + eap_figure_next_state(pcb, 0); + break; + + case EAPSRP_ACK: + if (pcb->eap.es_server.ea_state != eapSRP3) { + ppp_error("EAP: unexpected SRP Subtype 3 Response"); + eap_send_failure(esp); + break; + } + pcb->eap.es_server.ea_type = EAPT_SRP; + eap_send_success(pcb, esp); + eap_figure_next_state(pcb, 0); + if (pcb->eap.es_rechallenge != 0) + TIMEOUT(eap_rechallenge, pcb, + pcb->eap.es_rechallenge); + if (pcb->eap.es_lwrechallenge != 0) + TIMEOUT(srp_lwrechallenge, pcb, + pcb->eap.es_lwrechallenge); + break; + + case EAPSRP_LWRECHALLENGE: + if (pcb->eap.es_server.ea_state != eapSRP4) { + ppp_info("EAP: unexpected SRP Subtype 4 Response"); + return; + } + if (len != SHA_DIGESTSIZE) { + ppp_error("EAP: bad Lightweight rechallenge " + "response"); + return; + } + SHA1Init(&ctxt); + vallen = id; + SHA1Update(&ctxt, &vallen, 1); + SHA1Update(&ctxt, pcb->eap.es_server.ea_skey, + SESSION_KEY_LEN); + SHA1Update(&ctxt, pcb->eap.es_challenge, pcb->eap.es_challen); + SHA1Update(&ctxt, pcb->eap.es_server.ea_peer, + pcb->eap.es_server.ea_peerlen); + SHA1Final(dig, &ctxt); + if (BCMP(dig, inp, SHA_DIGESTSIZE) != 0) { + ppp_error("EAP: failed Lightweight rechallenge"); + eap_send_failure(pcb); + break; + } + pcb->eap.es_server.ea_state = eapOpen; + if (pcb->eap.es_lwrechallenge != 0) + TIMEOUT(srp_lwrechallenge, esp, + pcb->eap.es_lwrechallenge); + break; + } + break; +#endif /* USE_SRP */ + + default: + /* This can't happen. */ + ppp_error("EAP: unknown Response type %d; ignored", typenum); + return; + } + + if (pcb->settings.eap_timeout_time > 0) { + UNTIMEOUT(eap_server_timeout, pcb); + } + + if (pcb->eap.es_server.ea_state != eapBadAuth && + pcb->eap.es_server.ea_state != eapOpen) { + pcb->eap.es_server.ea_id++; + eap_send_request(pcb); + } +} +#endif /* PPP_SERVER */ + +/* + * eap_success - Receive EAP Success message (client mode). + */ +static void eap_success(ppp_pcb *pcb, u_char *inp, int id, int len) { + LWIP_UNUSED_ARG(id); + + if (pcb->eap.es_client.ea_state != eapOpen && !eap_client_active(pcb)) { + ppp_dbglog("EAP unexpected success message in state %s (%d)", + eap_state_name(pcb->eap.es_client.ea_state), + pcb->eap.es_client.ea_state); + return; + } + + if (pcb->settings.eap_req_time > 0) { + UNTIMEOUT(eap_client_timeout, pcb); + } + + if (len > 0) { + /* This is odd. The spec doesn't allow for this. */ + PRINTMSG(inp, len); + } + + pcb->eap.es_client.ea_state = eapOpen; + auth_withpeer_success(pcb, PPP_EAP, 0); +} + +/* + * eap_failure - Receive EAP Failure message (client mode). + */ +static void eap_failure(ppp_pcb *pcb, u_char *inp, int id, int len) { + LWIP_UNUSED_ARG(id); + + if (!eap_client_active(pcb)) { + ppp_dbglog("EAP unexpected failure message in state %s (%d)", + eap_state_name(pcb->eap.es_client.ea_state), + pcb->eap.es_client.ea_state); + } + + if (pcb->settings.eap_req_time > 0) { + UNTIMEOUT(eap_client_timeout, pcb); + } + + if (len > 0) { + /* This is odd. The spec doesn't allow for this. */ + PRINTMSG(inp, len); + } + + pcb->eap.es_client.ea_state = eapBadAuth; + + ppp_error("EAP: peer reports authentication failure"); + auth_withpeer_fail(pcb, PPP_EAP); +} + +/* + * eap_input - Handle received EAP message. + */ +static void eap_input(ppp_pcb *pcb, u_char *inp, int inlen) { + u_char code, id; + int len; + + /* + * Parse header (code, id and length). If packet too short, + * drop it. + */ + if (inlen < EAP_HEADERLEN) { + ppp_error("EAP: packet too short: %d < %d", inlen, EAP_HEADERLEN); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < EAP_HEADERLEN || len > inlen) { + ppp_error("EAP: packet has illegal length field %d (%d..%d)", len, + EAP_HEADERLEN, inlen); + return; + } + len -= EAP_HEADERLEN; + + /* Dispatch based on message code */ + switch (code) { + case EAP_REQUEST: + eap_request(pcb, inp, id, len); + break; + +#if PPP_SERVER + case EAP_RESPONSE: + eap_response(pcb, inp, id, len); + break; +#endif /* PPP_SERVER */ + + case EAP_SUCCESS: + eap_success(pcb, inp, id, len); + break; + + case EAP_FAILURE: + eap_failure(pcb, inp, id, len); + break; + + default: /* XXX Need code reject */ + /* Note: it's not legal to send EAP Nak here. */ + ppp_warn("EAP: unknown code %d received", code); + break; + } +} + +#if PRINTPKT_SUPPORT +/* + * eap_printpkt - print the contents of an EAP packet. + */ +static const char* const eap_codenames[] = { + "Request", "Response", "Success", "Failure" +}; + +static const char* const eap_typenames[] = { + "Identity", "Notification", "Nak", "MD5-Challenge", + "OTP", "Generic-Token", NULL, NULL, + "RSA", "DSS", "KEA", "KEA-Validate", + "TLS", "Defender", "Windows 2000", "Arcot", + "Cisco", "Nokia", "SRP" +}; + +static int eap_printpkt(const u_char *inp, int inlen, void (*printer) (void *, const char *, ...), void *arg) { + int code, id, len, rtype, vallen; + const u_char *pstart; + u32_t uval; + + if (inlen < EAP_HEADERLEN) + return (0); + pstart = inp; + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < EAP_HEADERLEN || len > inlen) + return (0); + + if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(eap_codenames)) + printer(arg, " %s", eap_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= EAP_HEADERLEN; + switch (code) { + case EAP_REQUEST: + if (len < 1) { + printer(arg, " "); + break; + } + GETCHAR(rtype, inp); + len--; + if (rtype >= 1 && rtype <= (int)LWIP_ARRAYSIZE(eap_typenames)) + printer(arg, " %s", eap_typenames[rtype-1]); + else + printer(arg, " type=0x%x", rtype); + switch (rtype) { + case EAPT_IDENTITY: + case EAPT_NOTIFICATION: + if (len > 0) { + printer(arg, " "); + INCPTR(len, inp); + len = 0; + } else { + printer(arg, " "); + } + break; + + case EAPT_MD5CHAP: + if (len <= 0) + break; + GETCHAR(vallen, inp); + len--; + if (vallen > len) + goto truncated; + printer(arg, " ", vallen, inp); + INCPTR(vallen, inp); + len -= vallen; + if (len > 0) { + printer(arg, " "); + INCPTR(len, inp); + len = 0; + } else { + printer(arg, " "); + } + break; + + case EAPT_SRP: + if (len < 3) + goto truncated; + GETCHAR(vallen, inp); + len--; + printer(arg, "-%d", vallen); + switch (vallen) { + case EAPSRP_CHALLENGE: + GETCHAR(vallen, inp); + len--; + if (vallen >= len) + goto truncated; + if (vallen > 0) { + printer(arg, " "); + } else { + printer(arg, " "); + } + INCPTR(vallen, inp); + len -= vallen; + GETCHAR(vallen, inp); + len--; + if (vallen >= len) + goto truncated; + printer(arg, " ", vallen, inp); + INCPTR(vallen, inp); + len -= vallen; + GETCHAR(vallen, inp); + len--; + if (vallen > len) + goto truncated; + if (vallen == 0) { + printer(arg, " "); + } else { + printer(arg, " ", vallen, inp); + } + INCPTR(vallen, inp); + len -= vallen; + if (len == 0) { + printer(arg, " "); + } else { + printer(arg, " ", len, inp); + INCPTR(len, inp); + len = 0; + } + break; + + case EAPSRP_SKEY: + printer(arg, " ", len, inp); + INCPTR(len, inp); + len = 0; + break; + + case EAPSRP_SVALIDATOR: + if (len < (int)sizeof (u32_t)) + break; + GETLONG(uval, inp); + len -= sizeof (u32_t); + if (uval & SRPVAL_EBIT) { + printer(arg, " E"); + uval &= ~SRPVAL_EBIT; + } + if (uval != 0) { + printer(arg, " f<%X>", uval); + } + if ((vallen = len) > SHA_DIGESTSIZE) + vallen = SHA_DIGESTSIZE; + printer(arg, " ", len, inp, + len < SHA_DIGESTSIZE ? "?" : ""); + INCPTR(vallen, inp); + len -= vallen; + if (len > 0) { + printer(arg, " ", len, inp); + INCPTR(len, inp); + len = 0; + } + break; + + case EAPSRP_LWRECHALLENGE: + printer(arg, " ", len, inp); + INCPTR(len, inp); + len = 0; + break; + default: + break; + } + break; + default: + break; + } + break; + + case EAP_RESPONSE: + if (len < 1) + break; + GETCHAR(rtype, inp); + len--; + if (rtype >= 1 && rtype <= (int)LWIP_ARRAYSIZE(eap_typenames)) + printer(arg, " %s", eap_typenames[rtype-1]); + else + printer(arg, " type=0x%x", rtype); + switch (rtype) { + case EAPT_IDENTITY: + if (len > 0) { + printer(arg, " "); + INCPTR(len, inp); + len = 0; + } + break; + + case EAPT_NAK: + if (len <= 0) { + printer(arg, " "); + break; + } + GETCHAR(rtype, inp); + len--; + printer(arg, " = 1 && rtype < (int)LWIP_ARRAYSIZE(eap_typenames)) + printer(arg, " (%s)", eap_typenames[rtype-1]); + printer(arg, ">"); + break; + + case EAPT_MD5CHAP: + if (len <= 0) { + printer(arg, " "); + break; + } + GETCHAR(vallen, inp); + len--; + if (vallen > len) + goto truncated; + printer(arg, " ", vallen, inp); + INCPTR(vallen, inp); + len -= vallen; + if (len > 0) { + printer(arg, " "); + INCPTR(len, inp); + len = 0; + } else { + printer(arg, " "); + } + break; + + case EAPT_SRP: + if (len < 1) + goto truncated; + GETCHAR(vallen, inp); + len--; + printer(arg, "-%d", vallen); + switch (vallen) { + case EAPSRP_CKEY: + printer(arg, " ", len, inp); + INCPTR(len, inp); + len = 0; + break; + + case EAPSRP_CVALIDATOR: + if (len < (int)sizeof (u32_t)) + break; + GETLONG(uval, inp); + len -= sizeof (u32_t); + if (uval & SRPVAL_EBIT) { + printer(arg, " E"); + uval &= ~SRPVAL_EBIT; + } + if (uval != 0) { + printer(arg, " f<%X>", uval); + } + printer(arg, " ", len, inp, + len == SHA_DIGESTSIZE ? "" : "?"); + INCPTR(len, inp); + len = 0; + break; + + case EAPSRP_ACK: + break; + + case EAPSRP_LWRECHALLENGE: + printer(arg, " ", len, inp, + len == SHA_DIGESTSIZE ? "" : "?"); + if ((vallen = len) > SHA_DIGESTSIZE) + vallen = SHA_DIGESTSIZE; + INCPTR(vallen, inp); + len -= vallen; + break; + default: + break; + } + break; + default: + break; + } + break; + + case EAP_SUCCESS: /* No payload expected for these! */ + case EAP_FAILURE: + default: + break; + + truncated: + printer(arg, " "); + break; + } + + if (len > 8) + printer(arg, "%8B...", inp); + else if (len > 0) + printer(arg, "%.*B", len, inp); + INCPTR(len, inp); + + return (inp - pstart); +} +#endif /* PRINTPKT_SUPPORT */ + +#endif /* PPP_SUPPORT && EAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c new file mode 100644 index 0000000..4d84f60 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/ecp.c @@ -0,0 +1,191 @@ +/* + * ecp.c - PPP Encryption Control Protocol. + * + * Copyright (c) 2002 Google, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * Derived from ccp.c, which is: + * + * Copyright (c) 1994-2002 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && ECP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/ecp.h" + +#if PPP_OPTIONS +static option_t ecp_option_list[] = { + { "noecp", o_bool, &ecp_protent.enabled_flag, + "Disable ECP negotiation" }, + { "-ecp", o_bool, &ecp_protent.enabled_flag, + "Disable ECP negotiation", OPT_ALIAS }, + + { NULL } +}; +#endif /* PPP_OPTIONS */ + +/* + * Protocol entry points from main code. + */ +static void ecp_init (int unit); +/* +static void ecp_open (int unit); +static void ecp_close (int unit, char *); +static void ecp_lowerup (int unit); +static void ecp_lowerdown (int); +static void ecp_input (int unit, u_char *pkt, int len); +static void ecp_protrej (int unit); +*/ +#if PRINTPKT_SUPPORT +static int ecp_printpkt (const u_char *pkt, int len, + void (*printer) (void *, char *, ...), + void *arg); +#endif /* PRINTPKT_SUPPORT */ +/* +static void ecp_datainput (int unit, u_char *pkt, int len); +*/ + +const struct protent ecp_protent = { + PPP_ECP, + ecp_init, + NULL, /* ecp_input, */ + NULL, /* ecp_protrej, */ + NULL, /* ecp_lowerup, */ + NULL, /* ecp_lowerdown, */ + NULL, /* ecp_open, */ + NULL, /* ecp_close, */ +#if PRINTPKT_SUPPORT + ecp_printpkt, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + NULL, /* ecp_datainput, */ +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "ECP", + "Encrypted", +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + ecp_option_list, + NULL, +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + NULL, + NULL +#endif /* DEMAND_SUPPORT */ +}; + +fsm ecp_fsm[NUM_PPP]; +ecp_options ecp_wantoptions[NUM_PPP]; /* what to request the peer to use */ +ecp_options ecp_gotoptions[NUM_PPP]; /* what the peer agreed to do */ +ecp_options ecp_allowoptions[NUM_PPP]; /* what we'll agree to do */ +ecp_options ecp_hisoptions[NUM_PPP]; /* what we agreed to do */ + +static const fsm_callbacks ecp_callbacks = { + NULL, /* ecp_resetci, */ + NULL, /* ecp_cilen, */ + NULL, /* ecp_addci, */ + NULL, /* ecp_ackci, */ + NULL, /* ecp_nakci, */ + NULL, /* ecp_rejci, */ + NULL, /* ecp_reqci, */ + NULL, /* ecp_up, */ + NULL, /* ecp_down, */ + NULL, + NULL, + NULL, + NULL, + NULL, /* ecp_extcode, */ + "ECP" +}; + +/* + * ecp_init - initialize ECP. + */ +static void +ecp_init(unit) + int unit; +{ + fsm *f = &ecp_fsm[unit]; + + f->unit = unit; + f->protocol = PPP_ECP; + f->callbacks = &ecp_callbacks; + fsm_init(f); + +#if 0 /* Not necessary, everything is cleared in ppp_new() */ + memset(&ecp_wantoptions[unit], 0, sizeof(ecp_options)); + memset(&ecp_gotoptions[unit], 0, sizeof(ecp_options)); + memset(&ecp_allowoptions[unit], 0, sizeof(ecp_options)); + memset(&ecp_hisoptions[unit], 0, sizeof(ecp_options)); +#endif /* 0 */ + +} + + +#if PRINTPKT_SUPPORT +static int +ecp_printpkt(p, plen, printer, arg) + const u_char *p; + int plen; + void (*printer) (void *, char *, ...); + void *arg; +{ + return 0; +} +#endif /* PRINTPKT_SUPPORT */ + +#endif /* PPP_SUPPORT && ECP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c new file mode 100644 index 0000000..01493bc --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/eui64.c @@ -0,0 +1,56 @@ +/* + * eui64.c - EUI64 routines for IPv6CP. + * + * Copyright (c) 1999 Tommi Komulainen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Tommi Komulainen + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: eui64.c,v 1.6 2002/12/04 23:03:32 paulus Exp $ + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPP_IPV6_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/eui64.h" + +/* + * eui64_ntoa - Make an ascii representation of an interface identifier + */ +char *eui64_ntoa(eui64_t e) { + static char buf[20]; + + sprintf(buf, "%02x%02x:%02x%02x:%02x%02x:%02x%02x", + e.e8[0], e.e8[1], e.e8[2], e.e8[3], + e.e8[4], e.e8[5], e.e8[6], e.e8[7]); + return buf; +} + +#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c new file mode 100644 index 0000000..b1f08af --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/fsm.c @@ -0,0 +1,799 @@ +/* + * fsm.c - {Link, IP} Control Protocol Finite State Machine. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +/* + * @todo: + * Randomize fsm id on link/init. + * Deal with variable outgoing MTU. + */ + +#if 0 /* UNUSED */ +#include +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" + +static void fsm_timeout (void *); +static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len); +static void fsm_rconfack(fsm *f, int id, u_char *inp, int len); +static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len); +static void fsm_rtermreq(fsm *f, int id, u_char *p, int len); +static void fsm_rtermack(fsm *f); +static void fsm_rcoderej(fsm *f, u_char *inp, int len); +static void fsm_sconfreq(fsm *f, int retransmit); + +#define PROTO_NAME(f) ((f)->callbacks->proto_name) + +/* + * fsm_init - Initialize fsm. + * + * Initialize fsm state. + */ +void fsm_init(fsm *f) { + ppp_pcb *pcb = f->pcb; + f->state = PPP_FSM_INITIAL; + f->flags = 0; + f->id = 0; /* XXX Start with random id? */ + f->maxnakloops = pcb->settings.fsm_max_nak_loops; + f->term_reason_len = 0; +} + + +/* + * fsm_lowerup - The lower layer is up. + */ +void fsm_lowerup(fsm *f) { + switch( f->state ){ + case PPP_FSM_INITIAL: + f->state = PPP_FSM_CLOSED; + break; + + case PPP_FSM_STARTING: + if( f->flags & OPT_SILENT ) + f->state = PPP_FSM_STOPPED; + else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = PPP_FSM_REQSENT; + } + break; + + default: + FSMDEBUG(("%s: Up event in state %d!", PROTO_NAME(f), f->state)); + /* no break */ + } +} + + +/* + * fsm_lowerdown - The lower layer is down. + * + * Cancel all timeouts and inform upper layers. + */ +void fsm_lowerdown(fsm *f) { + switch( f->state ){ + case PPP_FSM_CLOSED: + f->state = PPP_FSM_INITIAL; + break; + + case PPP_FSM_STOPPED: + f->state = PPP_FSM_STARTING; + if( f->callbacks->starting ) + (*f->callbacks->starting)(f); + break; + + case PPP_FSM_CLOSING: + f->state = PPP_FSM_INITIAL; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case PPP_FSM_STOPPING: + case PPP_FSM_REQSENT: + case PPP_FSM_ACKRCVD: + case PPP_FSM_ACKSENT: + f->state = PPP_FSM_STARTING; + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + break; + + case PPP_FSM_OPENED: + if( f->callbacks->down ) + (*f->callbacks->down)(f); + f->state = PPP_FSM_STARTING; + break; + + default: + FSMDEBUG(("%s: Down event in state %d!", PROTO_NAME(f), f->state)); + /* no break */ + } +} + + +/* + * fsm_open - Link is allowed to come up. + */ +void fsm_open(fsm *f) { + switch( f->state ){ + case PPP_FSM_INITIAL: + f->state = PPP_FSM_STARTING; + if( f->callbacks->starting ) + (*f->callbacks->starting)(f); + break; + + case PPP_FSM_CLOSED: + if( f->flags & OPT_SILENT ) + f->state = PPP_FSM_STOPPED; + else { + /* Send an initial configure-request */ + fsm_sconfreq(f, 0); + f->state = PPP_FSM_REQSENT; + } + break; + + case PPP_FSM_CLOSING: + f->state = PPP_FSM_STOPPING; + /* fall through */ + /* no break */ + case PPP_FSM_STOPPED: + case PPP_FSM_OPENED: + if( f->flags & OPT_RESTART ){ + fsm_lowerdown(f); + fsm_lowerup(f); + } + break; + default: + break; + } +} + +/* + * terminate_layer - Start process of shutting down the FSM + * + * Cancel any timeout running, notify upper layers we're done, and + * send a terminate-request message as configured. + */ +static void terminate_layer(fsm *f, int nextstate) { + ppp_pcb *pcb = f->pcb; + + if( f->state != PPP_FSM_OPENED ) + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + else if( f->callbacks->down ) + (*f->callbacks->down)(f); /* Inform upper layers we're down */ + + /* Init restart counter and send Terminate-Request */ + f->retransmits = pcb->settings.fsm_max_term_transmits; + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (const u_char *) f->term_reason, f->term_reason_len); + + if (f->retransmits == 0) { + /* + * User asked for no terminate requests at all; just close it. + * We've already fired off one Terminate-Request just to be nice + * to the peer, but we're not going to wait for a reply. + */ + f->state = nextstate == PPP_FSM_CLOSING ? PPP_FSM_CLOSED : PPP_FSM_STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + return; + } + + TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time); + --f->retransmits; + + f->state = nextstate; +} + +/* + * fsm_close - Start closing connection. + * + * Cancel timeouts and either initiate close or possibly go directly to + * the PPP_FSM_CLOSED state. + */ +void fsm_close(fsm *f, const char *reason) { + f->term_reason = reason; + f->term_reason_len = (reason == NULL? 0: (u8_t)LWIP_MIN(strlen(reason), 0xFF) ); + switch( f->state ){ + case PPP_FSM_STARTING: + f->state = PPP_FSM_INITIAL; + break; + case PPP_FSM_STOPPED: + f->state = PPP_FSM_CLOSED; + break; + case PPP_FSM_STOPPING: + f->state = PPP_FSM_CLOSING; + break; + + case PPP_FSM_REQSENT: + case PPP_FSM_ACKRCVD: + case PPP_FSM_ACKSENT: + case PPP_FSM_OPENED: + terminate_layer(f, PPP_FSM_CLOSING); + break; + default: + break; + } +} + + +/* + * fsm_timeout - Timeout expired. + */ +static void fsm_timeout(void *arg) { + fsm *f = (fsm *) arg; + ppp_pcb *pcb = f->pcb; + + switch (f->state) { + case PPP_FSM_CLOSING: + case PPP_FSM_STOPPING: + if( f->retransmits <= 0 ){ + /* + * We've waited for an ack long enough. Peer probably heard us. + */ + f->state = (f->state == PPP_FSM_CLOSING)? PPP_FSM_CLOSED: PPP_FSM_STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + } else { + /* Send Terminate-Request */ + fsm_sdata(f, TERMREQ, f->reqid = ++f->id, + (const u_char *) f->term_reason, f->term_reason_len); + TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time); + --f->retransmits; + } + break; + + case PPP_FSM_REQSENT: + case PPP_FSM_ACKRCVD: + case PPP_FSM_ACKSENT: + if (f->retransmits <= 0) { + ppp_warn("%s: timeout sending Config-Requests", PROTO_NAME(f)); + f->state = PPP_FSM_STOPPED; + if( (f->flags & OPT_PASSIVE) == 0 && f->callbacks->finished ) + (*f->callbacks->finished)(f); + + } else { + /* Retransmit the configure-request */ + if (f->callbacks->retransmit) + (*f->callbacks->retransmit)(f); + fsm_sconfreq(f, 1); /* Re-send Configure-Request */ + if( f->state == PPP_FSM_ACKRCVD ) + f->state = PPP_FSM_REQSENT; + } + break; + + default: + FSMDEBUG(("%s: Timeout event in state %d!", PROTO_NAME(f), f->state)); + /* no break */ + } +} + + +/* + * fsm_input - Input packet. + */ +void fsm_input(fsm *f, u_char *inpacket, int l) { + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (l < HEADERLEN) { + FSMDEBUG(("fsm_input(%x): Rcvd short header.", f->protocol)); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < HEADERLEN) { + FSMDEBUG(("fsm_input(%x): Rcvd illegal length.", f->protocol)); + return; + } + if (len > l) { + FSMDEBUG(("fsm_input(%x): Rcvd short packet.", f->protocol)); + return; + } + len -= HEADERLEN; /* subtract header length */ + + if( f->state == PPP_FSM_INITIAL || f->state == PPP_FSM_STARTING ){ + FSMDEBUG(("fsm_input(%x): Rcvd packet in state %d.", + f->protocol, f->state)); + return; + } + + /* + * Action depends on code. + */ + switch (code) { + case CONFREQ: + fsm_rconfreq(f, id, inp, len); + break; + + case CONFACK: + fsm_rconfack(f, id, inp, len); + break; + + case CONFNAK: + case CONFREJ: + fsm_rconfnakrej(f, code, id, inp, len); + break; + + case TERMREQ: + fsm_rtermreq(f, id, inp, len); + break; + + case TERMACK: + fsm_rtermack(f); + break; + + case CODEREJ: + fsm_rcoderej(f, inp, len); + break; + + default: + if( !f->callbacks->extcode + || !(*f->callbacks->extcode)(f, code, id, inp, len) ) + fsm_sdata(f, CODEREJ, ++f->id, inpacket, len + HEADERLEN); + break; + } +} + + +/* + * fsm_rconfreq - Receive Configure-Request. + */ +static void fsm_rconfreq(fsm *f, u_char id, u_char *inp, int len) { + int code, reject_if_disagree; + + switch( f->state ){ + case PPP_FSM_CLOSED: + /* Go away, we're closed */ + fsm_sdata(f, TERMACK, id, NULL, 0); + return; + case PPP_FSM_CLOSING: + case PPP_FSM_STOPPING: + return; + + case PPP_FSM_OPENED: + /* Go down and restart negotiation */ + if( f->callbacks->down ) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = PPP_FSM_REQSENT; + break; + + case PPP_FSM_STOPPED: + /* Negotiation started by our peer */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = PPP_FSM_REQSENT; + break; + default: + break; + } + + /* + * Pass the requested configuration options + * to protocol-specific code for checking. + */ + if (f->callbacks->reqci){ /* Check CI */ + reject_if_disagree = (f->nakloops >= f->maxnakloops); + code = (*f->callbacks->reqci)(f, inp, &len, reject_if_disagree); + } else if (len) + code = CONFREJ; /* Reject all CI */ + else + code = CONFACK; + + /* send the Ack, Nak or Rej to the peer */ + fsm_sdata(f, code, id, inp, len); + + if (code == CONFACK) { + if (f->state == PPP_FSM_ACKRCVD) { + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = PPP_FSM_OPENED; + if (f->callbacks->up) + (*f->callbacks->up)(f); /* Inform upper layers */ + } else + f->state = PPP_FSM_ACKSENT; + f->nakloops = 0; + + } else { + /* we sent CONFACK or CONFREJ */ + if (f->state != PPP_FSM_ACKRCVD) + f->state = PPP_FSM_REQSENT; + if( code == CONFNAK ) + ++f->nakloops; + } +} + + +/* + * fsm_rconfack - Receive Configure-Ack. + */ +static void fsm_rconfack(fsm *f, int id, u_char *inp, int len) { + ppp_pcb *pcb = f->pcb; + + if (id != f->reqid || f->seen_ack) /* Expected id? */ + return; /* Nope, toss... */ + if( !(f->callbacks->ackci? (*f->callbacks->ackci)(f, inp, len): + (len == 0)) ){ + /* Ack is bad - ignore it */ + ppp_error("Received bad configure-ack: %P", inp, len); + return; + } + f->seen_ack = 1; + f->rnakloops = 0; + + switch (f->state) { + case PPP_FSM_CLOSED: + case PPP_FSM_STOPPED: + fsm_sdata(f, TERMACK, id, NULL, 0); + break; + + case PPP_FSM_REQSENT: + f->state = PPP_FSM_ACKRCVD; + f->retransmits = pcb->settings.fsm_max_conf_req_transmits; + break; + + case PPP_FSM_ACKRCVD: + /* Huh? an extra valid Ack? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = PPP_FSM_REQSENT; + break; + + case PPP_FSM_ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + f->state = PPP_FSM_OPENED; + f->retransmits = pcb->settings.fsm_max_conf_req_transmits; + if (f->callbacks->up) + (*f->callbacks->up)(f); /* Inform upper layers */ + break; + + case PPP_FSM_OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = PPP_FSM_REQSENT; + break; + default: + break; + } +} + + +/* + * fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. + */ +static void fsm_rconfnakrej(fsm *f, int code, int id, u_char *inp, int len) { + int ret; + int treat_as_reject; + + if (id != f->reqid || f->seen_ack) /* Expected id? */ + return; /* Nope, toss... */ + + if (code == CONFNAK) { + ++f->rnakloops; + treat_as_reject = (f->rnakloops >= f->maxnakloops); + if (f->callbacks->nakci == NULL + || !(ret = f->callbacks->nakci(f, inp, len, treat_as_reject))) { + ppp_error("Received bad configure-nak: %P", inp, len); + return; + } + } else { + f->rnakloops = 0; + if (f->callbacks->rejci == NULL + || !(ret = f->callbacks->rejci(f, inp, len))) { + ppp_error("Received bad configure-rej: %P", inp, len); + return; + } + } + + f->seen_ack = 1; + + switch (f->state) { + case PPP_FSM_CLOSED: + case PPP_FSM_STOPPED: + fsm_sdata(f, TERMACK, id, NULL, 0); + break; + + case PPP_FSM_REQSENT: + case PPP_FSM_ACKSENT: + /* They didn't agree to what we wanted - try another request */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + if (ret < 0) + f->state = PPP_FSM_STOPPED; /* kludge for stopping CCP */ + else + fsm_sconfreq(f, 0); /* Send Configure-Request */ + break; + + case PPP_FSM_ACKRCVD: + /* Got a Nak/reject when we had already had an Ack?? oh well... */ + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + fsm_sconfreq(f, 0); + f->state = PPP_FSM_REQSENT; + break; + + case PPP_FSM_OPENED: + /* Go down and restart negotiation */ + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); /* Send initial Configure-Request */ + f->state = PPP_FSM_REQSENT; + break; + default: + break; + } +} + + +/* + * fsm_rtermreq - Receive Terminate-Req. + */ +static void fsm_rtermreq(fsm *f, int id, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + + switch (f->state) { + case PPP_FSM_ACKRCVD: + case PPP_FSM_ACKSENT: + f->state = PPP_FSM_REQSENT; /* Start over but keep trying */ + break; + + case PPP_FSM_OPENED: + if (len > 0) { + ppp_info("%s terminated by peer (%0.*v)", PROTO_NAME(f), len, p); + } else + ppp_info("%s terminated by peer", PROTO_NAME(f)); + f->retransmits = 0; + f->state = PPP_FSM_STOPPING; + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time); + break; + default: + break; + } + + fsm_sdata(f, TERMACK, id, NULL, 0); +} + + +/* + * fsm_rtermack - Receive Terminate-Ack. + */ +static void fsm_rtermack(fsm *f) { + switch (f->state) { + case PPP_FSM_CLOSING: + UNTIMEOUT(fsm_timeout, f); + f->state = PPP_FSM_CLOSED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + case PPP_FSM_STOPPING: + UNTIMEOUT(fsm_timeout, f); + f->state = PPP_FSM_STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case PPP_FSM_ACKRCVD: + f->state = PPP_FSM_REQSENT; + break; + + case PPP_FSM_OPENED: + if (f->callbacks->down) + (*f->callbacks->down)(f); /* Inform upper layers */ + fsm_sconfreq(f, 0); + f->state = PPP_FSM_REQSENT; + break; + default: + break; + } +} + + +/* + * fsm_rcoderej - Receive an Code-Reject. + */ +static void fsm_rcoderej(fsm *f, u_char *inp, int len) { + u_char code, id; + + if (len < HEADERLEN) { + FSMDEBUG(("fsm_rcoderej: Rcvd short Code-Reject packet!")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + ppp_warn("%s: Rcvd Code-Reject for code %d, id %d", PROTO_NAME(f), code, id); + + if( f->state == PPP_FSM_ACKRCVD ) + f->state = PPP_FSM_REQSENT; +} + + +/* + * fsm_protreject - Peer doesn't speak this protocol. + * + * Treat this as a catastrophic error (RXJ-). + */ +void fsm_protreject(fsm *f) { + switch( f->state ){ + case PPP_FSM_CLOSING: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + /* no break */ + case PPP_FSM_CLOSED: + f->state = PPP_FSM_CLOSED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case PPP_FSM_STOPPING: + case PPP_FSM_REQSENT: + case PPP_FSM_ACKRCVD: + case PPP_FSM_ACKSENT: + UNTIMEOUT(fsm_timeout, f); /* Cancel timeout */ + /* fall through */ + /* no break */ + case PPP_FSM_STOPPED: + f->state = PPP_FSM_STOPPED; + if( f->callbacks->finished ) + (*f->callbacks->finished)(f); + break; + + case PPP_FSM_OPENED: + terminate_layer(f, PPP_FSM_STOPPING); + break; + + default: + FSMDEBUG(("%s: Protocol-reject event in state %d!", + PROTO_NAME(f), f->state)); + /* no break */ + } +} + + +/* + * fsm_sconfreq - Send a Configure-Request. + */ +static void fsm_sconfreq(fsm *f, int retransmit) { + ppp_pcb *pcb = f->pcb; + struct pbuf *p; + u_char *outp; + int cilen; + + if( f->state != PPP_FSM_REQSENT && f->state != PPP_FSM_ACKRCVD && f->state != PPP_FSM_ACKSENT ){ + /* Not currently negotiating - reset options */ + if( f->callbacks->resetci ) + (*f->callbacks->resetci)(f); + f->nakloops = 0; + f->rnakloops = 0; + } + + if( !retransmit ){ + /* New request - reset retransmission counter, use new ID */ + f->retransmits = pcb->settings.fsm_max_conf_req_transmits; + f->reqid = ++f->id; + } + + f->seen_ack = 0; + + /* + * Make up the request packet + */ + if( f->callbacks->cilen && f->callbacks->addci ){ + cilen = (*f->callbacks->cilen)(f); + if( cilen > pcb->peer_mru - HEADERLEN ) + cilen = pcb->peer_mru - HEADERLEN; + } else + cilen = 0; + + p = pbuf_alloc(PBUF_RAW, (u16_t)(cilen + HEADERLEN + PPP_HDRLEN), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + /* send the request to our peer */ + outp = (u_char*)p->payload; + MAKEHEADER(outp, f->protocol); + PUTCHAR(CONFREQ, outp); + PUTCHAR(f->reqid, outp); + PUTSHORT(cilen + HEADERLEN, outp); + if (cilen != 0) { + (*f->callbacks->addci)(f, outp, &cilen); + LWIP_ASSERT("cilen == p->len - HEADERLEN - PPP_HDRLEN", cilen == p->len - HEADERLEN - PPP_HDRLEN); + } + + ppp_write(pcb, p); + + /* start the retransmit timer */ + --f->retransmits; + TIMEOUT(fsm_timeout, f, pcb->settings.fsm_timeout_time); +} + + +/* + * fsm_sdata - Send some data. + * + * Used for all packets sent to our peer by this module. + */ +void fsm_sdata(fsm *f, u_char code, u_char id, const u_char *data, int datalen) { + ppp_pcb *pcb = f->pcb; + struct pbuf *p; + u_char *outp; + int outlen; + + /* Adjust length to be smaller than MTU */ + if (datalen > pcb->peer_mru - HEADERLEN) + datalen = pcb->peer_mru - HEADERLEN; + outlen = datalen + HEADERLEN; + + p = pbuf_alloc(PBUF_RAW, (u16_t)(outlen + PPP_HDRLEN), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + if (datalen) /* && data != outp + PPP_HDRLEN + HEADERLEN) -- was only for fsm_sconfreq() */ + MEMCPY(outp + PPP_HDRLEN + HEADERLEN, data, datalen); + MAKEHEADER(outp, f->protocol); + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + ppp_write(pcb, p); +} + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c new file mode 100644 index 0000000..b7c766e --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/ipcp.c @@ -0,0 +1,2418 @@ +/* + * ipcp.c - PPP IP Control Protocol. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPP_IPV4_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +/* + * @todo: + */ + +#if 0 /* UNUSED */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/ipcp.h" + +#if 0 /* UNUSED */ +/* global vars */ +u32_t netmask = 0; /* IP netmask to set on interface */ +#endif /* UNUSED */ + +#if 0 /* UNUSED */ +bool disable_defaultip = 0; /* Don't use hostname for default IP adrs */ +#endif /* UNUSED */ + +#if 0 /* moved to ppp_settings */ +bool noremoteip = 0; /* Let him have no IP address */ +#endif /* moved to ppp_setting */ + +#if 0 /* UNUSED */ +/* Hook for a plugin to know when IP protocol has come up */ +void (*ip_up_hook) (void) = NULL; + +/* Hook for a plugin to know when IP protocol has come down */ +void (*ip_down_hook) (void) = NULL; + +/* Hook for a plugin to choose the remote IP address */ +void (*ip_choose_hook) (u32_t *) = NULL; +#endif /* UNUSED */ + +#if PPP_NOTIFY +/* Notifiers for when IPCP goes up and down */ +struct notifier *ip_up_notifier = NULL; +struct notifier *ip_down_notifier = NULL; +#endif /* PPP_NOTIFY */ + +/* local vars */ +#if 0 /* moved to ppp_pcb */ +static int default_route_set[NUM_PPP]; /* Have set up a default route */ +static int proxy_arp_set[NUM_PPP]; /* Have created proxy arp entry */ +static int ipcp_is_up; /* have called np_up() */ +static int ipcp_is_open; /* haven't called np_finished() */ +static bool ask_for_local; /* request our address from peer */ +#endif /* moved to ppp_pcb */ +#if 0 /* UNUSED */ +static char vj_value[8]; /* string form of vj option value */ +static char netmask_str[20]; /* string form of netmask value */ +#endif /* UNUSED */ + +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void ipcp_resetci(fsm *f); /* Reset our CI */ +static int ipcp_cilen(fsm *f); /* Return length of our CI */ +static void ipcp_addci(fsm *f, u_char *ucp, int *lenp); /* Add our CI */ +static int ipcp_ackci(fsm *f, u_char *p, int len); /* Peer ack'd our CI */ +static int ipcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject);/* Peer nak'd our CI */ +static int ipcp_rejci(fsm *f, u_char *p, int len); /* Peer rej'd our CI */ +static int ipcp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree); /* Rcv CI */ +static void ipcp_up(fsm *f); /* We're UP */ +static void ipcp_down(fsm *f); /* We're DOWN */ +static void ipcp_finished(fsm *f); /* Don't need lower layer */ + +static const fsm_callbacks ipcp_callbacks = { /* IPCP callback routines */ + ipcp_resetci, /* Reset our Configuration Information */ + ipcp_cilen, /* Length of our Configuration Information */ + ipcp_addci, /* Add our Configuration Information */ + ipcp_ackci, /* ACK our Configuration Information */ + ipcp_nakci, /* NAK our Configuration Information */ + ipcp_rejci, /* Reject our Configuration Information */ + ipcp_reqci, /* Request peer's Configuration Information */ + ipcp_up, /* Called when fsm reaches OPENED state */ + ipcp_down, /* Called when fsm leaves OPENED state */ + NULL, /* Called when we want the lower layer up */ + ipcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + NULL, /* Called to handle protocol-specific codes */ + "IPCP" /* String name of protocol */ +}; + +/* + * Command-line options. + */ +#if PPP_OPTIONS +static int setvjslots (char **); +static int setdnsaddr (char **); +static int setwinsaddr (char **); +static int setnetmask (char **); +int setipaddr (char *, char **, int); + +static void printipaddr (option_t *, void (*)(void *, char *,...),void *); + +static option_t ipcp_option_list[] = { + { "noip", o_bool, &ipcp_protent.enabled_flag, + "Disable IP and IPCP" }, + { "-ip", o_bool, &ipcp_protent.enabled_flag, + "Disable IP and IPCP", OPT_ALIAS }, + + { "novj", o_bool, &ipcp_wantoptions[0].neg_vj, + "Disable VJ compression", OPT_A2CLR, &ipcp_allowoptions[0].neg_vj }, + { "-vj", o_bool, &ipcp_wantoptions[0].neg_vj, + "Disable VJ compression", OPT_ALIAS | OPT_A2CLR, + &ipcp_allowoptions[0].neg_vj }, + + { "novjccomp", o_bool, &ipcp_wantoptions[0].cflag, + "Disable VJ connection-ID compression", OPT_A2CLR, + &ipcp_allowoptions[0].cflag }, + { "-vjccomp", o_bool, &ipcp_wantoptions[0].cflag, + "Disable VJ connection-ID compression", OPT_ALIAS | OPT_A2CLR, + &ipcp_allowoptions[0].cflag }, + + { "vj-max-slots", o_special, (void *)setvjslots, + "Set maximum VJ header slots", + OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, vj_value }, + + { "ipcp-accept-local", o_bool, &ipcp_wantoptions[0].accept_local, + "Accept peer's address for us", 1 }, + { "ipcp-accept-remote", o_bool, &ipcp_wantoptions[0].accept_remote, + "Accept peer's address for it", 1 }, + + { "ipparam", o_string, &ipparam, + "Set ip script parameter", OPT_PRIO }, + + { "noipdefault", o_bool, &disable_defaultip, + "Don't use name for default IP adrs", 1 }, + + { "ms-dns", 1, (void *)setdnsaddr, + "DNS address for the peer's use" }, + { "ms-wins", 1, (void *)setwinsaddr, + "Nameserver for SMB over TCP/IP for peer" }, + + { "ipcp-restart", o_int, &ipcp_fsm[0].timeouttime, + "Set timeout for IPCP", OPT_PRIO }, + { "ipcp-max-terminate", o_int, &ipcp_fsm[0].maxtermtransmits, + "Set max #xmits for term-reqs", OPT_PRIO }, + { "ipcp-max-configure", o_int, &ipcp_fsm[0].maxconfreqtransmits, + "Set max #xmits for conf-reqs", OPT_PRIO }, + { "ipcp-max-failure", o_int, &ipcp_fsm[0].maxnakloops, + "Set max #conf-naks for IPCP", OPT_PRIO }, + + { "defaultroute", o_bool, &ipcp_wantoptions[0].default_route, + "Add default route", OPT_ENABLE|1, &ipcp_allowoptions[0].default_route }, + { "nodefaultroute", o_bool, &ipcp_allowoptions[0].default_route, + "disable defaultroute option", OPT_A2CLR, + &ipcp_wantoptions[0].default_route }, + { "-defaultroute", o_bool, &ipcp_allowoptions[0].default_route, + "disable defaultroute option", OPT_ALIAS | OPT_A2CLR, + &ipcp_wantoptions[0].default_route }, + + { "replacedefaultroute", o_bool, + &ipcp_wantoptions[0].replace_default_route, + "Replace default route", 1 + }, + { "noreplacedefaultroute", o_bool, + &ipcp_allowoptions[0].replace_default_route, + "Never replace default route", OPT_A2COPY, + &ipcp_wantoptions[0].replace_default_route }, + { "proxyarp", o_bool, &ipcp_wantoptions[0].proxy_arp, + "Add proxy ARP entry", OPT_ENABLE|1, &ipcp_allowoptions[0].proxy_arp }, + { "noproxyarp", o_bool, &ipcp_allowoptions[0].proxy_arp, + "disable proxyarp option", OPT_A2CLR, + &ipcp_wantoptions[0].proxy_arp }, + { "-proxyarp", o_bool, &ipcp_allowoptions[0].proxy_arp, + "disable proxyarp option", OPT_ALIAS | OPT_A2CLR, + &ipcp_wantoptions[0].proxy_arp }, + + { "usepeerdns", o_bool, &usepeerdns, + "Ask peer for DNS address(es)", 1 }, + + { "netmask", o_special, (void *)setnetmask, + "set netmask", OPT_PRIO | OPT_A2STRVAL | OPT_STATIC, netmask_str }, + + { "ipcp-no-addresses", o_bool, &ipcp_wantoptions[0].old_addrs, + "Disable old-style IP-Addresses usage", OPT_A2CLR, + &ipcp_allowoptions[0].old_addrs }, + { "ipcp-no-address", o_bool, &ipcp_wantoptions[0].neg_addr, + "Disable IP-Address usage", OPT_A2CLR, + &ipcp_allowoptions[0].neg_addr }, + + { "noremoteip", o_bool, &noremoteip, + "Allow peer to have no IP address", 1 }, + + { "nosendip", o_bool, &ipcp_wantoptions[0].neg_addr, + "Don't send our IP address to peer", OPT_A2CLR, + &ipcp_wantoptions[0].old_addrs}, + + { "IP addresses", o_wild, (void *) &setipaddr, + "set local and remote IP addresses", + OPT_NOARG | OPT_A2PRINTER, (void *) &printipaddr }, + + { NULL } +}; +#endif /* PPP_OPTIONS */ + +/* + * Protocol entry points from main code. + */ +static void ipcp_init(ppp_pcb *pcb); +static void ipcp_open(ppp_pcb *pcb); +static void ipcp_close(ppp_pcb *pcb, const char *reason); +static void ipcp_lowerup(ppp_pcb *pcb); +static void ipcp_lowerdown(ppp_pcb *pcb); +static void ipcp_input(ppp_pcb *pcb, u_char *p, int len); +static void ipcp_protrej(ppp_pcb *pcb); +#if PRINTPKT_SUPPORT +static int ipcp_printpkt(const u_char *p, int plen, + void (*printer) (void *, const char *, ...), void *arg); +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS +static void ip_check_options (void); +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT +static int ip_demand_conf (int); +static int ip_active_pkt (u_char *, int); +#endif /* DEMAND_SUPPORT */ +#if 0 /* UNUSED */ +static void create_resolv (u32_t, u32_t); +#endif /* UNUSED */ + +const struct protent ipcp_protent = { + PPP_IPCP, + ipcp_init, + ipcp_input, + ipcp_protrej, + ipcp_lowerup, + ipcp_lowerdown, + ipcp_open, + ipcp_close, +#if PRINTPKT_SUPPORT + ipcp_printpkt, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + NULL, +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "IPCP", + "IP", +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + ipcp_option_list, + ip_check_options, +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + ip_demand_conf, + ip_active_pkt +#endif /* DEMAND_SUPPORT */ +}; + +static void ipcp_clear_addrs(ppp_pcb *pcb, u32_t ouraddr, u32_t hisaddr, u8_t replacedefaultroute); + +/* + * Lengths of configuration options. + */ +#define CILEN_VOID 2 +#define CILEN_COMPRESS 4 /* min length for compression protocol opt. */ +#define CILEN_VJ 6 /* length for RFC1332 Van-Jacobson opt. */ +#define CILEN_ADDR 6 /* new-style single address option */ +#define CILEN_ADDRS 10 /* old-style dual address option */ + + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + +#if 0 /* UNUSED, already defined by lwIP */ +/* + * Make a string representation of a network IP address. + */ +char * +ip_ntoa(ipaddr) +u32_t ipaddr; +{ + static char b[64]; + + slprintf(b, sizeof(b), "%I", ipaddr); + return b; +} +#endif /* UNUSED, already defined by lwIP */ + +/* + * Option parsing. + */ +#if PPP_OPTIONS +/* + * setvjslots - set maximum number of connection slots for VJ compression + */ +static int +setvjslots(argv) + char **argv; +{ + int value; + + if (!int_option(*argv, &value)) + return 0; + + if (value < 2 || value > 16) { + option_error("vj-max-slots value must be between 2 and 16"); + return 0; + } + ipcp_wantoptions [0].maxslotindex = + ipcp_allowoptions[0].maxslotindex = value - 1; + slprintf(vj_value, sizeof(vj_value), "%d", value); + return 1; +} + +/* + * setdnsaddr - set the dns address(es) + */ +static int +setdnsaddr(argv) + char **argv; +{ + u32_t dns; + struct hostent *hp; + + dns = inet_addr(*argv); + if (dns == (u32_t) -1) { + if ((hp = gethostbyname(*argv)) == NULL) { + option_error("invalid address parameter '%s' for ms-dns option", + *argv); + return 0; + } + dns = *(u32_t *)hp->h_addr; + } + + /* We take the last 2 values given, the 2nd-last as the primary + and the last as the secondary. If only one is given it + becomes both primary and secondary. */ + if (ipcp_allowoptions[0].dnsaddr[1] == 0) + ipcp_allowoptions[0].dnsaddr[0] = dns; + else + ipcp_allowoptions[0].dnsaddr[0] = ipcp_allowoptions[0].dnsaddr[1]; + + /* always set the secondary address value. */ + ipcp_allowoptions[0].dnsaddr[1] = dns; + + return (1); +} + +/* + * setwinsaddr - set the wins address(es) + * This is primrarly used with the Samba package under UNIX or for pointing + * the caller to the existing WINS server on a Windows NT platform. + */ +static int +setwinsaddr(argv) + char **argv; +{ + u32_t wins; + struct hostent *hp; + + wins = inet_addr(*argv); + if (wins == (u32_t) -1) { + if ((hp = gethostbyname(*argv)) == NULL) { + option_error("invalid address parameter '%s' for ms-wins option", + *argv); + return 0; + } + wins = *(u32_t *)hp->h_addr; + } + + /* We take the last 2 values given, the 2nd-last as the primary + and the last as the secondary. If only one is given it + becomes both primary and secondary. */ + if (ipcp_allowoptions[0].winsaddr[1] == 0) + ipcp_allowoptions[0].winsaddr[0] = wins; + else + ipcp_allowoptions[0].winsaddr[0] = ipcp_allowoptions[0].winsaddr[1]; + + /* always set the secondary address value. */ + ipcp_allowoptions[0].winsaddr[1] = wins; + + return (1); +} + +/* + * setipaddr - Set the IP address + * If doit is 0, the call is to check whether this option is + * potentially an IP address specification. + * Not static so that plugins can call it to set the addresses + */ +int +setipaddr(arg, argv, doit) + char *arg; + char **argv; + int doit; +{ + struct hostent *hp; + char *colon; + u32_t local, remote; + ipcp_options *wo = &ipcp_wantoptions[0]; + static int prio_local = 0, prio_remote = 0; + + /* + * IP address pair separated by ":". + */ + if ((colon = strchr(arg, ':')) == NULL) + return 0; + if (!doit) + return 1; + + /* + * If colon first character, then no local addr. + */ + if (colon != arg && option_priority >= prio_local) { + *colon = '\0'; + if ((local = inet_addr(arg)) == (u32_t) -1) { + if ((hp = gethostbyname(arg)) == NULL) { + option_error("unknown host: %s", arg); + return 0; + } + local = *(u32_t *)hp->h_addr; + } + if (bad_ip_adrs(local)) { + option_error("bad local IP address %s", ip_ntoa(local)); + return 0; + } + if (local != 0) + wo->ouraddr = local; + *colon = ':'; + prio_local = option_priority; + } + + /* + * If colon last character, then no remote addr. + */ + if (*++colon != '\0' && option_priority >= prio_remote) { + if ((remote = inet_addr(colon)) == (u32_t) -1) { + if ((hp = gethostbyname(colon)) == NULL) { + option_error("unknown host: %s", colon); + return 0; + } + remote = *(u32_t *)hp->h_addr; + if (remote_name[0] == 0) + strlcpy(remote_name, colon, sizeof(remote_name)); + } + if (bad_ip_adrs(remote)) { + option_error("bad remote IP address %s", ip_ntoa(remote)); + return 0; + } + if (remote != 0) + wo->hisaddr = remote; + prio_remote = option_priority; + } + + return 1; +} + +static void +printipaddr(opt, printer, arg) + option_t *opt; + void (*printer) (void *, char *, ...); + void *arg; +{ + ipcp_options *wo = &ipcp_wantoptions[0]; + + if (wo->ouraddr != 0) + printer(arg, "%I", wo->ouraddr); + printer(arg, ":"); + if (wo->hisaddr != 0) + printer(arg, "%I", wo->hisaddr); +} + +/* + * setnetmask - set the netmask to be used on the interface. + */ +static int +setnetmask(argv) + char **argv; +{ + u32_t mask; + int n; + char *p; + + /* + * Unfortunately, if we use inet_addr, we can't tell whether + * a result of all 1s is an error or a valid 255.255.255.255. + */ + p = *argv; + n = parse_dotted_ip(p, &mask); + + mask = lwip_htonl(mask); + + if (n == 0 || p[n] != 0 || (netmask & ~mask) != 0) { + option_error("invalid netmask value '%s'", *argv); + return 0; + } + + netmask = mask; + slprintf(netmask_str, sizeof(netmask_str), "%I", mask); + + return (1); +} + +int +parse_dotted_ip(p, vp) + char *p; + u32_t *vp; +{ + int n; + u32_t v, b; + char *endp, *p0 = p; + + v = 0; + for (n = 3;; --n) { + b = strtoul(p, &endp, 0); + if (endp == p) + return 0; + if (b > 255) { + if (n < 3) + return 0; + /* accept e.g. 0xffffff00 */ + *vp = b; + return endp - p0; + } + v |= b << (n * 8); + p = endp; + if (n == 0) + break; + if (*p != '.') + return 0; + ++p; + } + *vp = v; + return p - p0; +} +#endif /* PPP_OPTIONS */ + +/* + * ipcp_init - Initialize IPCP. + */ +static void ipcp_init(ppp_pcb *pcb) { + fsm *f = &pcb->ipcp_fsm; + + ipcp_options *wo = &pcb->ipcp_wantoptions; + ipcp_options *ao = &pcb->ipcp_allowoptions; + + f->pcb = pcb; + f->protocol = PPP_IPCP; + f->callbacks = &ipcp_callbacks; + fsm_init(f); + + /* + * Some 3G modems use repeated IPCP NAKs as a way of stalling + * until they can contact a server on the network, so we increase + * the default number of NAKs we accept before we start treating + * them as rejects. + */ + f->maxnakloops = 100; + +#if 0 /* Not necessary, everything is cleared in ppp_new() */ + memset(wo, 0, sizeof(*wo)); + memset(ao, 0, sizeof(*ao)); +#endif /* 0 */ + + wo->neg_addr = wo->old_addrs = 1; +#if VJ_SUPPORT + wo->neg_vj = 1; + wo->vj_protocol = IPCP_VJ_COMP; + wo->maxslotindex = MAX_STATES - 1; /* really max index */ + wo->cflag = 1; +#endif /* VJ_SUPPORT */ + +#if 0 /* UNUSED */ + /* wanting default route by default */ + wo->default_route = 1; +#endif /* UNUSED */ + + ao->neg_addr = ao->old_addrs = 1; +#if VJ_SUPPORT + /* max slots and slot-id compression are currently hardwired in */ + /* ppp_if.c to 16 and 1, this needs to be changed (among other */ + /* things) gmc */ + + ao->neg_vj = 1; + ao->maxslotindex = MAX_STATES - 1; + ao->cflag = 1; +#endif /* #if VJ_SUPPORT */ + +#if 0 /* UNUSED */ + /* + * XXX These control whether the user may use the proxyarp + * and defaultroute options. + */ + ao->proxy_arp = 1; + ao->default_route = 1; +#endif /* UNUSED */ +} + + +/* + * ipcp_open - IPCP is allowed to come up. + */ +static void ipcp_open(ppp_pcb *pcb) { + fsm *f = &pcb->ipcp_fsm; + fsm_open(f); + pcb->ipcp_is_open = 1; +} + + +/* + * ipcp_close - Take IPCP down. + */ +static void ipcp_close(ppp_pcb *pcb, const char *reason) { + fsm *f = &pcb->ipcp_fsm; + fsm_close(f, reason); +} + + +/* + * ipcp_lowerup - The lower layer is up. + */ +static void ipcp_lowerup(ppp_pcb *pcb) { + fsm *f = &pcb->ipcp_fsm; + fsm_lowerup(f); +} + + +/* + * ipcp_lowerdown - The lower layer is down. + */ +static void ipcp_lowerdown(ppp_pcb *pcb) { + fsm *f = &pcb->ipcp_fsm; + fsm_lowerdown(f); +} + + +/* + * ipcp_input - Input IPCP packet. + */ +static void ipcp_input(ppp_pcb *pcb, u_char *p, int len) { + fsm *f = &pcb->ipcp_fsm; + fsm_input(f, p, len); +} + + +/* + * ipcp_protrej - A Protocol-Reject was received for IPCP. + * + * Pretend the lower layer went down, so we shut up. + */ +static void ipcp_protrej(ppp_pcb *pcb) { + fsm *f = &pcb->ipcp_fsm; + fsm_lowerdown(f); +} + + +/* + * ipcp_resetci - Reset our CI. + * Called by fsm_sconfreq, Send Configure Request. + */ +static void ipcp_resetci(fsm *f) { + ppp_pcb *pcb = f->pcb; + ipcp_options *wo = &pcb->ipcp_wantoptions; + ipcp_options *go = &pcb->ipcp_gotoptions; + ipcp_options *ao = &pcb->ipcp_allowoptions; + + wo->req_addr = (wo->neg_addr || wo->old_addrs) && + (ao->neg_addr || ao->old_addrs); + if (wo->ouraddr == 0) + wo->accept_local = 1; + if (wo->hisaddr == 0) + wo->accept_remote = 1; +#if LWIP_DNS + wo->req_dns1 = wo->req_dns2 = pcb->settings.usepeerdns; /* Request DNS addresses from the peer */ +#endif /* LWIP_DNS */ + *go = *wo; + if (!pcb->ask_for_local) + go->ouraddr = 0; +#if 0 /* UNUSED */ + if (ip_choose_hook) { + ip_choose_hook(&wo->hisaddr); + if (wo->hisaddr) { + wo->accept_remote = 0; + } + } +#endif /* UNUSED */ + BZERO(&pcb->ipcp_hisoptions, sizeof(ipcp_options)); +} + + +/* + * ipcp_cilen - Return length of our CI. + * Called by fsm_sconfreq, Send Configure Request. + */ +static int ipcp_cilen(fsm *f) { + ppp_pcb *pcb = f->pcb; + ipcp_options *go = &pcb->ipcp_gotoptions; +#if VJ_SUPPORT + ipcp_options *wo = &pcb->ipcp_wantoptions; +#endif /* VJ_SUPPORT */ + ipcp_options *ho = &pcb->ipcp_hisoptions; + +#define LENCIADDRS(neg) (neg ? CILEN_ADDRS : 0) +#if VJ_SUPPORT +#define LENCIVJ(neg, old) (neg ? (old? CILEN_COMPRESS : CILEN_VJ) : 0) +#endif /* VJ_SUPPORT */ +#define LENCIADDR(neg) (neg ? CILEN_ADDR : 0) +#if LWIP_DNS +#define LENCIDNS(neg) LENCIADDR(neg) +#endif /* LWIP_DNS */ +#if 0 /* UNUSED - WINS */ +#define LENCIWINS(neg) LENCIADDR(neg) +#endif /* UNUSED - WINS */ + + /* + * First see if we want to change our options to the old + * forms because we have received old forms from the peer. + */ + if (go->neg_addr && go->old_addrs && !ho->neg_addr && ho->old_addrs) + go->neg_addr = 0; + +#if VJ_SUPPORT + if (wo->neg_vj && !go->neg_vj && !go->old_vj) { + /* try an older style of VJ negotiation */ + /* use the old style only if the peer did */ + if (ho->neg_vj && ho->old_vj) { + go->neg_vj = 1; + go->old_vj = 1; + go->vj_protocol = ho->vj_protocol; + } + } +#endif /* VJ_SUPPORT */ + + return (LENCIADDRS(!go->neg_addr && go->old_addrs) + +#if VJ_SUPPORT + LENCIVJ(go->neg_vj, go->old_vj) + +#endif /* VJ_SUPPORT */ + LENCIADDR(go->neg_addr) + +#if LWIP_DNS + LENCIDNS(go->req_dns1) + + LENCIDNS(go->req_dns2) + +#endif /* LWIP_DNS */ +#if 0 /* UNUSED - WINS */ + LENCIWINS(go->winsaddr[0]) + + LENCIWINS(go->winsaddr[1]) + +#endif /* UNUSED - WINS */ + 0); +} + + +/* + * ipcp_addci - Add our desired CIs to a packet. + * Called by fsm_sconfreq, Send Configure Request. + */ +static void ipcp_addci(fsm *f, u_char *ucp, int *lenp) { + ppp_pcb *pcb = f->pcb; + ipcp_options *go = &pcb->ipcp_gotoptions; + int len = *lenp; + +#define ADDCIADDRS(opt, neg, val1, val2) \ + if (neg) { \ + if (len >= CILEN_ADDRS) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_ADDRS, ucp); \ + l = lwip_ntohl(val1); \ + PUTLONG(l, ucp); \ + l = lwip_ntohl(val2); \ + PUTLONG(l, ucp); \ + len -= CILEN_ADDRS; \ + } else \ + go->old_addrs = 0; \ + } + +#if VJ_SUPPORT +#define ADDCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if (len >= vjlen) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(vjlen, ucp); \ + PUTSHORT(val, ucp); \ + if (!old) { \ + PUTCHAR(maxslotindex, ucp); \ + PUTCHAR(cflag, ucp); \ + } \ + len -= vjlen; \ + } else \ + neg = 0; \ + } +#endif /* VJ_SUPPORT */ + +#define ADDCIADDR(opt, neg, val) \ + if (neg) { \ + if (len >= CILEN_ADDR) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_ADDR, ucp); \ + l = lwip_ntohl(val); \ + PUTLONG(l, ucp); \ + len -= CILEN_ADDR; \ + } else \ + neg = 0; \ + } + +#if LWIP_DNS +#define ADDCIDNS(opt, neg, addr) \ + if (neg) { \ + if (len >= CILEN_ADDR) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_ADDR, ucp); \ + l = lwip_ntohl(addr); \ + PUTLONG(l, ucp); \ + len -= CILEN_ADDR; \ + } else \ + neg = 0; \ + } +#endif /* LWIP_DNS */ + +#if 0 /* UNUSED - WINS */ +#define ADDCIWINS(opt, addr) \ + if (addr) { \ + if (len >= CILEN_ADDR) { \ + u32_t l; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_ADDR, ucp); \ + l = lwip_ntohl(addr); \ + PUTLONG(l, ucp); \ + len -= CILEN_ADDR; \ + } else \ + addr = 0; \ + } +#endif /* UNUSED - WINS */ + + ADDCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs, go->ouraddr, + go->hisaddr); + +#if VJ_SUPPORT + ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); +#endif /* VJ_SUPPORT */ + + ADDCIADDR(CI_ADDR, go->neg_addr, go->ouraddr); + +#if LWIP_DNS + ADDCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ADDCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); +#endif /* LWIP_DNS */ + +#if 0 /* UNUSED - WINS */ + ADDCIWINS(CI_MS_WINS1, go->winsaddr[0]); + + ADDCIWINS(CI_MS_WINS2, go->winsaddr[1]); +#endif /* UNUSED - WINS */ + + *lenp -= len; +} + + +/* + * ipcp_ackci - Ack our CIs. + * Called by fsm_rconfack, Receive Configure ACK. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int ipcp_ackci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + ipcp_options *go = &pcb->ipcp_gotoptions; + u_short cilen, citype; + u32_t cilong; +#if VJ_SUPPORT + u_short cishort; + u_char cimaxslotindex, cicflag; +#endif /* VJ_SUPPORT */ + + /* + * CIs must be in exactly the same order that we sent... + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ + +#define ACKCIADDRS(opt, neg, val1, val2) \ + if (neg) { \ + u32_t l; \ + if ((len -= CILEN_ADDRS) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_ADDRS || \ + citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + if (val1 != cilong) \ + goto bad; \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + if (val2 != cilong) \ + goto bad; \ + } + +#if VJ_SUPPORT +#define ACKCIVJ(opt, neg, val, old, maxslotindex, cflag) \ + if (neg) { \ + int vjlen = old? CILEN_COMPRESS : CILEN_VJ; \ + if ((len -= vjlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != vjlen || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslotindex) \ + goto bad; \ + GETCHAR(cicflag, p); \ + if (cicflag != cflag) \ + goto bad; \ + } \ + } +#endif /* VJ_SUPPORT */ + +#define ACKCIADDR(opt, neg, val) \ + if (neg) { \ + u32_t l; \ + if ((len -= CILEN_ADDR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_ADDR || \ + citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + if (val != cilong) \ + goto bad; \ + } + +#if LWIP_DNS +#define ACKCIDNS(opt, neg, addr) \ + if (neg) { \ + u32_t l; \ + if ((len -= CILEN_ADDR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_ADDR || citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + if (addr != cilong) \ + goto bad; \ + } +#endif /* LWIP_DNS */ + +#if 0 /* UNUSED - WINS */ +#define ACKCIWINS(opt, addr) \ + if (addr) { \ + u32_t l; \ + if ((len -= CILEN_ADDR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_ADDR || citype != opt) \ + goto bad; \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + if (addr != cilong) \ + goto bad; \ + } +#endif /* UNUSED - WINS */ + + ACKCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs, go->ouraddr, + go->hisaddr); + +#if VJ_SUPPORT + ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); +#endif /* VJ_SUPPORT */ + + ACKCIADDR(CI_ADDR, go->neg_addr, go->ouraddr); + +#if LWIP_DNS + ACKCIDNS(CI_MS_DNS1, go->req_dns1, go->dnsaddr[0]); + + ACKCIDNS(CI_MS_DNS2, go->req_dns2, go->dnsaddr[1]); +#endif /* LWIP_DNS */ + +#if 0 /* UNUSED - WINS */ + ACKCIWINS(CI_MS_WINS1, go->winsaddr[0]); + + ACKCIWINS(CI_MS_WINS2, go->winsaddr[1]); +#endif /* UNUSED - WINS */ + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + return (1); + +bad: + IPCPDEBUG(("ipcp_ackci: received bad Ack!")); + return (0); +} + +/* + * ipcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if IPCP is in the OPENED state. + * Calback from fsm_rconfnakrej - Receive Configure-Nak or Configure-Reject. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int ipcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) { + ppp_pcb *pcb = f->pcb; + ipcp_options *go = &pcb->ipcp_gotoptions; + u_char citype, cilen, *next; +#if VJ_SUPPORT + u_char cimaxslotindex, cicflag; + u_short cishort; +#endif /* VJ_SUPPORT */ + u32_t ciaddr1, ciaddr2, l; +#if LWIP_DNS + u32_t cidnsaddr; +#endif /* LWIP_DNS */ + ipcp_options no; /* options we've seen Naks for */ + ipcp_options try_; /* options to request next time */ + + BZERO(&no, sizeof(no)); + try_ = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIADDRS(opt, neg, code) \ + if ((neg) && \ + (cilen = p[1]) == CILEN_ADDRS && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + ciaddr1 = lwip_htonl(l); \ + GETLONG(l, p); \ + ciaddr2 = lwip_htonl(l); \ + no.old_addrs = 1; \ + code \ + } + +#if VJ_SUPPORT +#define NAKCIVJ(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_COMPRESS || cilen == CILEN_VJ) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } +#endif /* VJ_SUPPORT */ + +#define NAKCIADDR(opt, neg, code) \ + if (go->neg && \ + (cilen = p[1]) == CILEN_ADDR && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + ciaddr1 = lwip_htonl(l); \ + no.neg = 1; \ + code \ + } + +#if LWIP_DNS +#define NAKCIDNS(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cidnsaddr = lwip_htonl(l); \ + no.neg = 1; \ + code \ + } +#endif /* LWIP_DNS */ + + /* + * Accept the peer's idea of {our,his} address, if different + * from our idea, only if the accept_{local,remote} flag is set. + */ + NAKCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs, + if (treat_as_reject) { + try_.old_addrs = 0; + } else { + if (go->accept_local && ciaddr1) { + /* take his idea of our address */ + try_.ouraddr = ciaddr1; + } + if (go->accept_remote && ciaddr2) { + /* take his idea of his address */ + try_.hisaddr = ciaddr2; + } + } + ); + +#if VJ_SUPPORT + /* + * Accept the peer's value of maxslotindex provided that it + * is less than what we asked for. Turn off slot-ID compression + * if the peer wants. Send old-style compress-type option if + * the peer wants. + */ + NAKCIVJ(CI_COMPRESSTYPE, neg_vj, + if (treat_as_reject) { + try_.neg_vj = 0; + } else if (cilen == CILEN_VJ) { + GETCHAR(cimaxslotindex, p); + GETCHAR(cicflag, p); + if (cishort == IPCP_VJ_COMP) { + try_.old_vj = 0; + if (cimaxslotindex < go->maxslotindex) + try_.maxslotindex = cimaxslotindex; + if (!cicflag) + try_.cflag = 0; + } else { + try_.neg_vj = 0; + } + } else { + if (cishort == IPCP_VJ_COMP || cishort == IPCP_VJ_COMP_OLD) { + try_.old_vj = 1; + try_.vj_protocol = cishort; + } else { + try_.neg_vj = 0; + } + } + ); +#endif /* VJ_SUPPORT */ + + NAKCIADDR(CI_ADDR, neg_addr, + if (treat_as_reject) { + try_.neg_addr = 0; + try_.old_addrs = 0; + } else if (go->accept_local && ciaddr1) { + /* take his idea of our address */ + try_.ouraddr = ciaddr1; + } + ); + +#if LWIP_DNS + NAKCIDNS(CI_MS_DNS1, req_dns1, + if (treat_as_reject) { + try_.req_dns1 = 0; + } else { + try_.dnsaddr[0] = cidnsaddr; + } + ); + + NAKCIDNS(CI_MS_DNS2, req_dns2, + if (treat_as_reject) { + try_.req_dns2 = 0; + } else { + try_.dnsaddr[1] = cidnsaddr; + } + ); +#endif /* #if LWIP_DNS */ + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If they want to negotiate about IP addresses, we comply. + * If they want us to ask for compression, we refuse. + * If they want us to ask for ms-dns, we do that, since some + * peers get huffy if we don't. + */ + while (len >= CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if ( cilen < CILEN_VOID || (len -= cilen) < 0 ) + goto bad; + next = p + cilen - 2; + + switch (citype) { +#if VJ_SUPPORT + case CI_COMPRESSTYPE: + if (go->neg_vj || no.neg_vj || + (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) + goto bad; + no.neg_vj = 1; + break; +#endif /* VJ_SUPPORT */ + case CI_ADDRS: + if ((!go->neg_addr && go->old_addrs) || no.old_addrs + || cilen != CILEN_ADDRS) + goto bad; + try_.neg_addr = 0; + GETLONG(l, p); + ciaddr1 = lwip_htonl(l); + if (ciaddr1 && go->accept_local) + try_.ouraddr = ciaddr1; + GETLONG(l, p); + ciaddr2 = lwip_htonl(l); + if (ciaddr2 && go->accept_remote) + try_.hisaddr = ciaddr2; + no.old_addrs = 1; + break; + case CI_ADDR: + if (go->neg_addr || no.neg_addr || cilen != CILEN_ADDR) + goto bad; + try_.old_addrs = 0; + GETLONG(l, p); + ciaddr1 = lwip_htonl(l); + if (ciaddr1 && go->accept_local) + try_.ouraddr = ciaddr1; + if (try_.ouraddr != 0) + try_.neg_addr = 1; + no.neg_addr = 1; + break; +#if LWIP_DNS + case CI_MS_DNS1: + if (go->req_dns1 || no.req_dns1 || cilen != CILEN_ADDR) + goto bad; + GETLONG(l, p); + try_.dnsaddr[0] = lwip_htonl(l); + try_.req_dns1 = 1; + no.req_dns1 = 1; + break; + case CI_MS_DNS2: + if (go->req_dns2 || no.req_dns2 || cilen != CILEN_ADDR) + goto bad; + GETLONG(l, p); + try_.dnsaddr[1] = lwip_htonl(l); + try_.req_dns2 = 1; + no.req_dns2 = 1; + break; +#endif /* LWIP_DNS */ +#if 0 /* UNUSED - WINS */ + case CI_MS_WINS1: + case CI_MS_WINS2: + if (cilen != CILEN_ADDR) + goto bad; + GETLONG(l, p); + ciaddr1 = lwip_htonl(l); + if (ciaddr1) + try_.winsaddr[citype == CI_MS_WINS2] = ciaddr1; + break; +#endif /* UNUSED - WINS */ + default: + break; + } + p = next; + } + + /* + * OK, the Nak is good. Now we can update state. + * If there are any remaining options, we ignore them. + */ + if (f->state != PPP_FSM_OPENED) + *go = try_; + + return 1; + +bad: + IPCPDEBUG(("ipcp_nakci: received bad Nak!")); + return 0; +} + + +/* + * ipcp_rejci - Reject some of our CIs. + * Callback from fsm_rconfnakrej. + */ +static int ipcp_rejci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + ipcp_options *go = &pcb->ipcp_gotoptions; + u_char cilen; +#if VJ_SUPPORT + u_char cimaxslotindex, ciflag; + u_short cishort; +#endif /* VJ_SUPPORT */ + u32_t cilong; + ipcp_options try_; /* options to request next time */ + + try_ = *go; + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIADDRS(opt, neg, val1, val2) \ + if ((neg) && \ + (cilen = p[1]) == CILEN_ADDRS && \ + len >= cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val1) \ + goto bad; \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val2) \ + goto bad; \ + try_.old_addrs = 0; \ + } + +#if VJ_SUPPORT +#define REJCIVJ(opt, neg, val, old, maxslot, cflag) \ + if (go->neg && \ + p[1] == (old? CILEN_COMPRESS : CILEN_VJ) && \ + len >= p[1] && \ + p[0] == opt) { \ + len -= p[1]; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) \ + goto bad; \ + if (!old) { \ + GETCHAR(cimaxslotindex, p); \ + if (cimaxslotindex != maxslot) \ + goto bad; \ + GETCHAR(ciflag, p); \ + if (ciflag != cflag) \ + goto bad; \ + } \ + try_.neg = 0; \ + } +#endif /* VJ_SUPPORT */ + +#define REJCIADDR(opt, neg, val) \ + if (go->neg && \ + (cilen = p[1]) == CILEN_ADDR && \ + len >= cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + /* Check rejected value. */ \ + if (cilong != val) \ + goto bad; \ + try_.neg = 0; \ + } + +#if LWIP_DNS +#define REJCIDNS(opt, neg, dnsaddr) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + /* Check rejected value. */ \ + if (cilong != dnsaddr) \ + goto bad; \ + try_.neg = 0; \ + } +#endif /* LWIP_DNS */ + +#if 0 /* UNUSED - WINS */ +#define REJCIWINS(opt, addr) \ + if (addr && \ + ((cilen = p[1]) == CILEN_ADDR) && \ + len >= cilen && \ + p[0] == opt) { \ + u32_t l; \ + len -= cilen; \ + INCPTR(2, p); \ + GETLONG(l, p); \ + cilong = lwip_htonl(l); \ + /* Check rejected value. */ \ + if (cilong != addr) \ + goto bad; \ + try_.winsaddr[opt == CI_MS_WINS2] = 0; \ + } +#endif /* UNUSED - WINS */ + + REJCIADDRS(CI_ADDRS, !go->neg_addr && go->old_addrs, + go->ouraddr, go->hisaddr); + +#if VJ_SUPPORT + REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol, go->old_vj, + go->maxslotindex, go->cflag); +#endif /* VJ_SUPPORT */ + + REJCIADDR(CI_ADDR, neg_addr, go->ouraddr); + +#if LWIP_DNS + REJCIDNS(CI_MS_DNS1, req_dns1, go->dnsaddr[0]); + + REJCIDNS(CI_MS_DNS2, req_dns2, go->dnsaddr[1]); +#endif /* LWIP_DNS */ + +#if 0 /* UNUSED - WINS */ + REJCIWINS(CI_MS_WINS1, go->winsaddr[0]); + + REJCIWINS(CI_MS_WINS2, go->winsaddr[1]); +#endif /* UNUSED - WINS */ + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + /* + * Now we can update state. + */ + if (f->state != PPP_FSM_OPENED) + *go = try_; + return 1; + +bad: + IPCPDEBUG(("ipcp_rejci: received bad Reject!")); + return 0; +} + + +/* + * ipcp_reqci - Check the peer's requested CIs and send appropriate response. + * Callback from fsm_rconfreq, Receive Configure Request + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + * + * inp = Requested CIs + * len = Length of requested CIs + */ +static int ipcp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree) { + ppp_pcb *pcb = f->pcb; + ipcp_options *wo = &pcb->ipcp_wantoptions; + ipcp_options *ho = &pcb->ipcp_hisoptions; + ipcp_options *ao = &pcb->ipcp_allowoptions; + u_char *cip, *next; /* Pointer to current and next CIs */ + u_short cilen, citype; /* Parsed len, type */ +#if VJ_SUPPORT + u_short cishort; /* Parsed short value */ +#endif /* VJ_SUPPORT */ + u32_t tl, ciaddr1, ciaddr2;/* Parsed address values */ + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *ucp = inp; /* Pointer to current output char */ + int l = *len; /* Length left */ +#if VJ_SUPPORT + u_char maxslotindex, cflag; +#endif /* VJ_SUPPORT */ +#if LWIP_DNS + int d; +#endif /* LWIP_DNS */ + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + IPCPDEBUG(("ipcp_reqci: bad CI length!")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ + case CI_ADDRS: + if (!ao->old_addrs || ho->neg_addr || + cilen != CILEN_ADDRS) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = lwip_htonl(tl); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = lwip_ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * If neither we nor he knows his address, reject the option. + */ + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + /* + * If he doesn't know our address, or if we both have our address + * but disagree about it, then NAK it with our idea. + */ + GETLONG(tl, p); /* Parse desination address (ours) */ + ciaddr2 = lwip_htonl(tl); + if (ciaddr2 != wo->ouraddr) { + if (ciaddr2 == 0 || !wo->accept_local) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = lwip_ntohl(wo->ouraddr); + PUTLONG(tl, p); + } + } else { + wo->ouraddr = ciaddr2; /* accept peer's idea */ + } + } + + ho->old_addrs = 1; + ho->hisaddr = ciaddr1; + ho->ouraddr = ciaddr2; + break; + + case CI_ADDR: + if (!ao->neg_addr || ho->old_addrs || + cilen != CILEN_ADDR) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no address, or if we both have his address but + * disagree about it, then NAK it with our idea. + * In particular, if we don't know his address, but he does, + * then accept it. + */ + GETLONG(tl, p); /* Parse source address (his) */ + ciaddr1 = lwip_htonl(tl); + if (ciaddr1 != wo->hisaddr + && (ciaddr1 == 0 || !wo->accept_remote)) { + orc = CONFNAK; + if (!reject_if_disagree) { + DECPTR(sizeof(u32_t), p); + tl = lwip_ntohl(wo->hisaddr); + PUTLONG(tl, p); + } + } else if (ciaddr1 == 0 && wo->hisaddr == 0) { + /* + * Don't ACK an address of 0.0.0.0 - reject it instead. + */ + orc = CONFREJ; + wo->req_addr = 0; /* don't NAK with 0.0.0.0 later */ + break; + } + + ho->neg_addr = 1; + ho->hisaddr = ciaddr1; + break; + +#if LWIP_DNS + case CI_MS_DNS1: + case CI_MS_DNS2: + /* Microsoft primary or secondary DNS request */ + d = citype == CI_MS_DNS2; + + /* If we do not have a DNS address then we cannot send it */ + if (ao->dnsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (lwip_htonl(tl) != ao->dnsaddr[d]) { + DECPTR(sizeof(u32_t), p); + tl = lwip_ntohl(ao->dnsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + break; +#endif /* LWIP_DNS */ + +#if 0 /* UNUSED - WINS */ + case CI_MS_WINS1: + case CI_MS_WINS2: + /* Microsoft primary or secondary WINS request */ + d = citype == CI_MS_WINS2; + + /* If we do not have a DNS address then we cannot send it */ + if (ao->winsaddr[d] == 0 || + cilen != CILEN_ADDR) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + GETLONG(tl, p); + if (lwip_htonl(tl) != ao->winsaddr[d]) { + DECPTR(sizeof(u32_t), p); + tl = lwip_ntohl(ao->winsaddr[d]); + PUTLONG(tl, p); + orc = CONFNAK; + } + break; +#endif /* UNUSED - WINS */ + +#if VJ_SUPPORT + case CI_COMPRESSTYPE: + if (!ao->neg_vj || + (cilen != CILEN_VJ && cilen != CILEN_COMPRESS)) { + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + if (!(cishort == IPCP_VJ_COMP || + (cishort == IPCP_VJ_COMP_OLD && cilen == CILEN_COMPRESS))) { + orc = CONFREJ; + break; + } + + ho->neg_vj = 1; + ho->vj_protocol = cishort; + if (cilen == CILEN_VJ) { + GETCHAR(maxslotindex, p); + if (maxslotindex > ao->maxslotindex) { + orc = CONFNAK; + if (!reject_if_disagree){ + DECPTR(1, p); + PUTCHAR(ao->maxslotindex, p); + } + } + GETCHAR(cflag, p); + if (cflag && !ao->cflag) { + orc = CONFNAK; + if (!reject_if_disagree){ + DECPTR(1, p); + PUTCHAR(wo->cflag, p); + } + } + ho->maxslotindex = maxslotindex; + ho->cflag = cflag; + } else { + ho->old_vj = 1; + ho->maxslotindex = MAX_STATES - 1; + ho->cflag = 1; + } + break; +#endif /* VJ_SUPPORT */ + + default: + orc = CONFREJ; + break; + } +endswitch: + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) /* but prior CI wasnt? */ + continue; /* Don't send this one */ + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree) /* Getting fed up with sending NAKs? */ + orc = CONFREJ; /* Get tough if so */ + else { + if (rc == CONFREJ) /* Rejecting prior CI? */ + continue; /* Don't send this one */ + if (rc == CONFACK) { /* Ack'd all prior CIs? */ + rc = CONFNAK; /* Not anymore... */ + ucp = inp; /* Backup */ + } + } + } + + if (orc == CONFREJ && /* Reject this CI */ + rc != CONFREJ) { /* but no prior ones? */ + rc = CONFREJ; + ucp = inp; /* Backup */ + } + + /* Need to move CI? */ + if (ucp != cip) + MEMCPY(ucp, cip, cilen); /* Move it */ + + /* Update output pointer */ + INCPTR(cilen, ucp); + } + + /* + * If we aren't rejecting this packet, and we want to negotiate + * their address, and they didn't send their address, then we + * send a NAK with a CI_ADDR option appended. We assume the + * input buffer is long enough that we can append the extra + * option safely. + */ + if (rc != CONFREJ && !ho->neg_addr && !ho->old_addrs && + wo->req_addr && !reject_if_disagree && !pcb->settings.noremoteip) { + if (rc == CONFACK) { + rc = CONFNAK; + ucp = inp; /* reset pointer */ + wo->req_addr = 0; /* don't ask again */ + } + PUTCHAR(CI_ADDR, ucp); + PUTCHAR(CILEN_ADDR, ucp); + tl = lwip_ntohl(wo->hisaddr); + PUTLONG(tl, ucp); + } + + *len = ucp - inp; /* Compute output length */ + IPCPDEBUG(("ipcp: returning Configure-%s", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +#if 0 /* UNUSED */ +/* + * ip_check_options - check that any IP-related options are OK, + * and assign appropriate defaults. + */ +static void +ip_check_options() +{ + struct hostent *hp; + u32_t local; + ipcp_options *wo = &ipcp_wantoptions[0]; + + /* + * Default our local IP address based on our hostname. + * If local IP address already given, don't bother. + */ + if (wo->ouraddr == 0 && !disable_defaultip) { + /* + * Look up our hostname (possibly with domain name appended) + * and take the first IP address as our local IP address. + * If there isn't an IP address for our hostname, too bad. + */ + wo->accept_local = 1; /* don't insist on this default value */ + if ((hp = gethostbyname(hostname)) != NULL) { + local = *(u32_t *)hp->h_addr; + if (local != 0 && !bad_ip_adrs(local)) + wo->ouraddr = local; + } + } + ask_for_local = wo->ouraddr != 0 || !disable_defaultip; +} +#endif /* UNUSED */ + +#if DEMAND_SUPPORT +/* + * ip_demand_conf - configure the interface as though + * IPCP were up, for use with dial-on-demand. + */ +static int +ip_demand_conf(u) + int u; +{ + ppp_pcb *pcb = &ppp_pcb_list[u]; + ipcp_options *wo = &ipcp_wantoptions[u]; + + if (wo->hisaddr == 0 && !pcb->settings.noremoteip) { + /* make up an arbitrary address for the peer */ + wo->hisaddr = lwip_htonl(0x0a707070 + ifunit); + wo->accept_remote = 1; + } + if (wo->ouraddr == 0) { + /* make up an arbitrary address for us */ + wo->ouraddr = lwip_htonl(0x0a404040 + ifunit); + wo->accept_local = 1; + ask_for_local = 0; /* don't tell the peer this address */ + } + if (!sifaddr(pcb, wo->ouraddr, wo->hisaddr, get_mask(wo->ouraddr))) + return 0; + if (!sifup(pcb)) + return 0; + if (!sifnpmode(pcb, PPP_IP, NPMODE_QUEUE)) + return 0; +#if 0 /* UNUSED */ + if (wo->default_route) + if (sifdefaultroute(pcb, wo->ouraddr, wo->hisaddr, + wo->replace_default_route)) + default_route_set[u] = 1; +#endif /* UNUSED */ +#if 0 /* UNUSED - PROXY ARP */ + if (wo->proxy_arp) + if (sifproxyarp(pcb, wo->hisaddr)) + proxy_arp_set[u] = 1; +#endif /* UNUSED - PROXY ARP */ + + ppp_notice("local IP address %I", wo->ouraddr); + if (wo->hisaddr) + ppp_notice("remote IP address %I", wo->hisaddr); + + return 1; +} +#endif /* DEMAND_SUPPORT */ + +/* + * ipcp_up - IPCP has come UP. + * + * Configure the IP network interface appropriately and bring it up. + */ +static void ipcp_up(fsm *f) { + ppp_pcb *pcb = f->pcb; + u32_t mask; + ipcp_options *ho = &pcb->ipcp_hisoptions; + ipcp_options *go = &pcb->ipcp_gotoptions; + ipcp_options *wo = &pcb->ipcp_wantoptions; + + IPCPDEBUG(("ipcp: up")); + + /* + * We must have a non-zero IP address for both ends of the link. + */ + if (!ho->neg_addr && !ho->old_addrs) + ho->hisaddr = wo->hisaddr; + + if (!(go->neg_addr || go->old_addrs) && (wo->neg_addr || wo->old_addrs) + && wo->ouraddr != 0) { + ppp_error("Peer refused to agree to our IP address"); + ipcp_close(f->pcb, "Refused our IP address"); + return; + } + if (go->ouraddr == 0) { + ppp_error("Could not determine local IP address"); + ipcp_close(f->pcb, "Could not determine local IP address"); + return; + } + if (ho->hisaddr == 0 && !pcb->settings.noremoteip) { + ho->hisaddr = lwip_htonl(0x0a404040); + ppp_warn("Could not determine remote IP address: defaulting to %I", + ho->hisaddr); + } +#if 0 /* UNUSED */ + script_setenv("IPLOCAL", ip_ntoa(go->ouraddr), 0); + if (ho->hisaddr != 0) + script_setenv("IPREMOTE", ip_ntoa(ho->hisaddr), 1); +#endif /* UNUSED */ + +#if LWIP_DNS + if (!go->req_dns1) + go->dnsaddr[0] = 0; + if (!go->req_dns2) + go->dnsaddr[1] = 0; +#if 0 /* UNUSED */ + if (go->dnsaddr[0]) + script_setenv("DNS1", ip_ntoa(go->dnsaddr[0]), 0); + if (go->dnsaddr[1]) + script_setenv("DNS2", ip_ntoa(go->dnsaddr[1]), 0); +#endif /* UNUSED */ + if (pcb->settings.usepeerdns && (go->dnsaddr[0] || go->dnsaddr[1])) { + sdns(pcb, go->dnsaddr[0], go->dnsaddr[1]); +#if 0 /* UNUSED */ + script_setenv("USEPEERDNS", "1", 0); + create_resolv(go->dnsaddr[0], go->dnsaddr[1]); +#endif /* UNUSED */ + } +#endif /* LWIP_DNS */ + + /* + * Check that the peer is allowed to use the IP address it wants. + */ + if (ho->hisaddr != 0) { + u32_t addr = lwip_ntohl(ho->hisaddr); + if ((addr >> IP_CLASSA_NSHIFT) == IP_LOOPBACKNET + || IP_MULTICAST(addr) || IP_BADCLASS(addr) + /* + * For now, consider that PPP in server mode with peer required + * to authenticate must provide the peer IP address, reject any + * IP address wanted by peer different than the one we wanted. + */ +#if PPP_SERVER && PPP_AUTH_SUPPORT + || (pcb->settings.auth_required && wo->hisaddr != ho->hisaddr) +#endif /* PPP_SERVER && PPP_AUTH_SUPPORT */ + ) { + ppp_error("Peer is not authorized to use remote address %I", ho->hisaddr); + ipcp_close(pcb, "Unauthorized remote IP address"); + return; + } + } +#if 0 /* Unused */ + /* Upstream checking code */ + if (ho->hisaddr != 0 && !auth_ip_addr(f->unit, ho->hisaddr)) { + ppp_error("Peer is not authorized to use remote address %I", ho->hisaddr); + ipcp_close(f->unit, "Unauthorized remote IP address"); + return; + } +#endif /* Unused */ + +#if VJ_SUPPORT + /* set tcp compression */ + sifvjcomp(pcb, ho->neg_vj, ho->cflag, ho->maxslotindex); +#endif /* VJ_SUPPORT */ + +#if DEMAND_SUPPORT + /* + * If we are doing dial-on-demand, the interface is already + * configured, so we put out any saved-up packets, then set the + * interface to pass IP packets. + */ + if (demand) { + if (go->ouraddr != wo->ouraddr || ho->hisaddr != wo->hisaddr) { + ipcp_clear_addrs(f->unit, wo->ouraddr, wo->hisaddr, + wo->replace_default_route); + if (go->ouraddr != wo->ouraddr) { + ppp_warn("Local IP address changed to %I", go->ouraddr); + script_setenv("OLDIPLOCAL", ip_ntoa(wo->ouraddr), 0); + wo->ouraddr = go->ouraddr; + } else + script_unsetenv("OLDIPLOCAL"); + if (ho->hisaddr != wo->hisaddr && wo->hisaddr != 0) { + ppp_warn("Remote IP address changed to %I", ho->hisaddr); + script_setenv("OLDIPREMOTE", ip_ntoa(wo->hisaddr), 0); + wo->hisaddr = ho->hisaddr; + } else + script_unsetenv("OLDIPREMOTE"); + + /* Set the interface to the new addresses */ + mask = get_mask(go->ouraddr); + if (!sifaddr(pcb, go->ouraddr, ho->hisaddr, mask)) { +#if PPP_DEBUG + ppp_warn("Interface configuration failed"); +#endif /* PPP_DEBUG */ + ipcp_close(f->unit, "Interface configuration failed"); + return; + } + + /* assign a default route through the interface if required */ + if (ipcp_wantoptions[f->unit].default_route) + if (sifdefaultroute(pcb, go->ouraddr, ho->hisaddr, + wo->replace_default_route)) + default_route_set[f->unit] = 1; + +#if 0 /* UNUSED - PROXY ARP */ + /* Make a proxy ARP entry if requested. */ + if (ho->hisaddr != 0 && ipcp_wantoptions[f->unit].proxy_arp) + if (sifproxyarp(pcb, ho->hisaddr)) + proxy_arp_set[f->unit] = 1; +#endif /* UNUSED - PROXY ARP */ + + } + demand_rexmit(PPP_IP,go->ouraddr); + sifnpmode(pcb, PPP_IP, NPMODE_PASS); + + } else +#endif /* DEMAND_SUPPORT */ + { + /* + * Set IP addresses and (if specified) netmask. + */ + mask = get_mask(go->ouraddr); + +#if !(defined(SVR4) && (defined(SNI) || defined(__USLC__))) + if (!sifaddr(pcb, go->ouraddr, ho->hisaddr, mask)) { +#if PPP_DEBUG + ppp_warn("Interface configuration failed"); +#endif /* PPP_DEBUG */ + ipcp_close(f->pcb, "Interface configuration failed"); + return; + } +#endif + + /* bring the interface up for IP */ + if (!sifup(pcb)) { +#if PPP_DEBUG + ppp_warn("Interface failed to come up"); +#endif /* PPP_DEBUG */ + ipcp_close(f->pcb, "Interface configuration failed"); + return; + } + +#if (defined(SVR4) && (defined(SNI) || defined(__USLC__))) + if (!sifaddr(pcb, go->ouraddr, ho->hisaddr, mask)) { +#if PPP_DEBUG + ppp_warn("Interface configuration failed"); +#endif /* PPP_DEBUG */ + ipcp_close(f->unit, "Interface configuration failed"); + return; + } +#endif +#if DEMAND_SUPPORT + sifnpmode(pcb, PPP_IP, NPMODE_PASS); +#endif /* DEMAND_SUPPORT */ + +#if 0 /* UNUSED */ + /* assign a default route through the interface if required */ + if (wo->default_route) + if (sifdefaultroute(pcb, go->ouraddr, ho->hisaddr, + wo->replace_default_route)) + pcb->default_route_set = 1; +#endif /* UNUSED */ + +#if 0 /* UNUSED - PROXY ARP */ + /* Make a proxy ARP entry if requested. */ + if (ho->hisaddr != 0 && wo->proxy_arp) + if (sifproxyarp(pcb, ho->hisaddr)) + pcb->proxy_arp_set = 1; +#endif /* UNUSED - PROXY ARP */ + + wo->ouraddr = go->ouraddr; + + ppp_notice("local IP address %I", go->ouraddr); + if (ho->hisaddr != 0) + ppp_notice("remote IP address %I", ho->hisaddr); +#if LWIP_DNS + if (go->dnsaddr[0]) + ppp_notice("primary DNS address %I", go->dnsaddr[0]); + if (go->dnsaddr[1]) + ppp_notice("secondary DNS address %I", go->dnsaddr[1]); +#endif /* LWIP_DNS */ + } + +#if PPP_STATS_SUPPORT + reset_link_stats(f->unit); +#endif /* PPP_STATS_SUPPORT */ + + np_up(pcb, PPP_IP); + pcb->ipcp_is_up = 1; + +#if PPP_NOTIFY + notify(ip_up_notifier, 0); +#endif /* PPP_NOTIFY */ +#if 0 /* UNUSED */ + if (ip_up_hook) + ip_up_hook(); +#endif /* UNUSED */ +} + + +/* + * ipcp_down - IPCP has gone DOWN. + * + * Take the IP network interface down, clear its addresses + * and delete routes through it. + */ +static void ipcp_down(fsm *f) { + ppp_pcb *pcb = f->pcb; + ipcp_options *ho = &pcb->ipcp_hisoptions; + ipcp_options *go = &pcb->ipcp_gotoptions; + + IPCPDEBUG(("ipcp: down")); +#if PPP_STATS_SUPPORT + /* XXX a bit IPv4-centric here, we only need to get the stats + * before the interface is marked down. */ + /* XXX more correct: we must get the stats before running the notifiers, + * at least for the radius plugin */ + update_link_stats(f->unit); +#endif /* PPP_STATS_SUPPORT */ +#if PPP_NOTIFY + notify(ip_down_notifier, 0); +#endif /* PPP_NOTIFY */ +#if 0 /* UNUSED */ + if (ip_down_hook) + ip_down_hook(); +#endif /* UNUSED */ + if (pcb->ipcp_is_up) { + pcb->ipcp_is_up = 0; + np_down(pcb, PPP_IP); + } +#if VJ_SUPPORT + sifvjcomp(pcb, 0, 0, 0); +#endif /* VJ_SUPPORT */ + +#if PPP_STATS_SUPPORT + print_link_stats(); /* _after_ running the notifiers and ip_down_hook(), + * because print_link_stats() sets link_stats_valid + * to 0 (zero) */ +#endif /* PPP_STATS_SUPPORT */ + +#if DEMAND_SUPPORT + /* + * If we are doing dial-on-demand, set the interface + * to queue up outgoing packets (for now). + */ + if (demand) { + sifnpmode(pcb, PPP_IP, NPMODE_QUEUE); + } else +#endif /* DEMAND_SUPPORT */ + { +#if DEMAND_SUPPORT + sifnpmode(pcb, PPP_IP, NPMODE_DROP); +#endif /* DEMAND_SUPPORT */ + sifdown(pcb); + ipcp_clear_addrs(pcb, go->ouraddr, + ho->hisaddr, 0); +#if LWIP_DNS + cdns(pcb, go->dnsaddr[0], go->dnsaddr[1]); +#endif /* LWIP_DNS */ + } +} + + +/* + * ipcp_clear_addrs() - clear the interface addresses, routes, + * proxy arp entries, etc. + */ +static void ipcp_clear_addrs(ppp_pcb *pcb, u32_t ouraddr, u32_t hisaddr, u8_t replacedefaultroute) { + LWIP_UNUSED_ARG(replacedefaultroute); + +#if 0 /* UNUSED - PROXY ARP */ + if (pcb->proxy_arp_set) { + cifproxyarp(pcb, hisaddr); + pcb->proxy_arp_set = 0; + } +#endif /* UNUSED - PROXY ARP */ +#if 0 /* UNUSED */ + /* If replacedefaultroute, sifdefaultroute will be called soon + * with replacedefaultroute set and that will overwrite the current + * default route. This is the case only when doing demand, otherwise + * during demand, this cifdefaultroute would restore the old default + * route which is not what we want in this case. In the non-demand + * case, we'll delete the default route and restore the old if there + * is one saved by an sifdefaultroute with replacedefaultroute. + */ + if (!replacedefaultroute && pcb->default_route_set) { + cifdefaultroute(pcb, ouraddr, hisaddr); + pcb->default_route_set = 0; + } +#endif /* UNUSED */ + cifaddr(pcb, ouraddr, hisaddr); +} + + +/* + * ipcp_finished - possibly shut down the lower layers. + */ +static void ipcp_finished(fsm *f) { + ppp_pcb *pcb = f->pcb; + if (pcb->ipcp_is_open) { + pcb->ipcp_is_open = 0; + np_finished(pcb, PPP_IP); + } +} + + +#if 0 /* UNUSED */ +/* + * create_resolv - create the replacement resolv.conf file + */ +static void +create_resolv(peerdns1, peerdns2) + u32_t peerdns1, peerdns2; +{ + +} +#endif /* UNUSED */ + +#if PRINTPKT_SUPPORT +/* + * ipcp_printpkt - print the contents of an IPCP packet. + */ +static const char* const ipcp_codenames[] = { + "ConfReq", "ConfAck", "ConfNak", "ConfRej", + "TermReq", "TermAck", "CodeRej" +}; + +static int ipcp_printpkt(const u_char *p, int plen, + void (*printer) (void *, const char *, ...), void *arg) { + int code, id, len, olen; + const u_char *pstart, *optend; +#if VJ_SUPPORT + u_short cishort; +#endif /* VJ_SUPPORT */ + u32_t cilong; + + if (plen < HEADERLEN) + return 0; + pstart = p; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(ipcp_codenames)) + printer(arg, " %s", ipcp_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= HEADERLEN; + switch (code) { + case CONFREQ: + case CONFACK: + case CONFNAK: + case CONFREJ: + /* print option list */ + while (len >= 2) { + GETCHAR(code, p); + GETCHAR(olen, p); + p -= 2; + if (olen < 2 || olen > len) { + break; + } + printer(arg, " <"); + len -= olen; + optend = p + olen; + switch (code) { + case CI_ADDRS: + if (olen == CILEN_ADDRS) { + p += 2; + GETLONG(cilong, p); + printer(arg, "addrs %I", lwip_htonl(cilong)); + GETLONG(cilong, p); + printer(arg, " %I", lwip_htonl(cilong)); + } + break; +#if VJ_SUPPORT + case CI_COMPRESSTYPE: + if (olen >= CILEN_COMPRESS) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "compress "); + switch (cishort) { + case IPCP_VJ_COMP: + printer(arg, "VJ"); + break; + case IPCP_VJ_COMP_OLD: + printer(arg, "old-VJ"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; +#endif /* VJ_SUPPORT */ + case CI_ADDR: + if (olen == CILEN_ADDR) { + p += 2; + GETLONG(cilong, p); + printer(arg, "addr %I", lwip_htonl(cilong)); + } + break; +#if LWIP_DNS + case CI_MS_DNS1: + case CI_MS_DNS2: + p += 2; + GETLONG(cilong, p); + printer(arg, "ms-dns%d %I", (code == CI_MS_DNS1? 1: 2), + htonl(cilong)); + break; +#endif /* LWIP_DNS */ +#if 0 /* UNUSED - WINS */ + case CI_MS_WINS1: + case CI_MS_WINS2: + p += 2; + GETLONG(cilong, p); + printer(arg, "ms-wins %I", lwip_htonl(cilong)); + break; +#endif /* UNUSED - WINS */ + default: + break; + } + while (p < optend) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + printer(arg, ">"); + } + break; + + case TERMACK: + case TERMREQ: + if (len > 0 && *p >= ' ' && *p < 0x7f) { + printer(arg, " "); + ppp_print_string(p, len, printer, arg); + p += len; + len = 0; + } + break; + default: + break; + } + + /* print the rest of the bytes in the packet */ + for (; len > 0; --len) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + + return p - pstart; +} +#endif /* PRINTPKT_SUPPORT */ + +#if DEMAND_SUPPORT +/* + * ip_active_pkt - see if this IP packet is worth bringing the link up for. + * We don't bring the link up for IP fragments or for TCP FIN packets + * with no data. + */ +#define IP_HDRLEN 20 /* bytes */ +#define IP_OFFMASK 0x1fff +#ifndef IPPROTO_TCP +#define IPPROTO_TCP 6 +#endif +#define TCP_HDRLEN 20 +#define TH_FIN 0x01 + +/* + * We use these macros because the IP header may be at an odd address, + * and some compilers might use word loads to get th_off or ip_hl. + */ + +#define net_short(x) (((x)[0] << 8) + (x)[1]) +#define get_iphl(x) (((unsigned char *)(x))[0] & 0xF) +#define get_ipoff(x) net_short((unsigned char *)(x) + 6) +#define get_ipproto(x) (((unsigned char *)(x))[9]) +#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) +#define get_tcpflags(x) (((unsigned char *)(x))[13]) + +static int +ip_active_pkt(pkt, len) + u_char *pkt; + int len; +{ + u_char *tcp; + int hlen; + + len -= PPP_HDRLEN; + pkt += PPP_HDRLEN; + if (len < IP_HDRLEN) + return 0; + if ((get_ipoff(pkt) & IP_OFFMASK) != 0) + return 0; + if (get_ipproto(pkt) != IPPROTO_TCP) + return 1; + hlen = get_iphl(pkt) * 4; + if (len < hlen + TCP_HDRLEN) + return 0; + tcp = pkt + hlen; + if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == hlen + get_tcpoff(tcp) * 4) + return 0; + return 1; +} +#endif /* DEMAND_SUPPORT */ + +#endif /* PPP_SUPPORT && PPP_IPV4_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c new file mode 100644 index 0000000..11c18df --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/ipv6cp.c @@ -0,0 +1,1533 @@ +/* + * ipv6cp.c - PPP IPV6 Control Protocol. + * + * Copyright (c) 1999 Tommi Komulainen. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Tommi Komulainen + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* Original version, based on RFC2023 : + + Copyright (c) 1995, 1996, 1997 Francis.Dupont@inria.fr, INRIA Rocquencourt, + Alain.Durand@imag.fr, IMAG, + Jean-Luc.Richier@imag.fr, IMAG-LSR. + + Copyright (c) 1998, 1999 Francis.Dupont@inria.fr, GIE DYADE, + Alain.Durand@imag.fr, IMAG, + Jean-Luc.Richier@imag.fr, IMAG-LSR. + + Ce travail a été fait au sein du GIE DYADE (Groupement d'Intérêt + Économique ayant pour membres BULL S.A. et l'INRIA). + + Ce logiciel informatique est disponible aux conditions + usuelles dans la recherche, c'est-à-dire qu'il peut + être utilisé, copié, modifié, distribué à l'unique + condition que ce texte soit conservé afin que + l'origine de ce logiciel soit reconnue. + + Le nom de l'Institut National de Recherche en Informatique + et en Automatique (INRIA), de l'IMAG, ou d'une personne morale + ou physique ayant participé à l'élaboration de ce logiciel ne peut + être utilisé sans son accord préalable explicite. + + Ce logiciel est fourni tel quel sans aucune garantie, + support ou responsabilité d'aucune sorte. + Ce logiciel est dérivé de sources d'origine + "University of California at Berkeley" et + "Digital Equipment Corporation" couvertes par des copyrights. + + L'Institut d'Informatique et de Mathématiques Appliquées de Grenoble (IMAG) + est une fédération d'unités mixtes de recherche du CNRS, de l'Institut National + Polytechnique de Grenoble et de l'Université Joseph Fourier regroupant + sept laboratoires dont le laboratoire Logiciels, Systèmes, Réseaux (LSR). + + This work has been done in the context of GIE DYADE (joint R & D venture + between BULL S.A. and INRIA). + + This software is available with usual "research" terms + with the aim of retain credits of the software. + Permission to use, copy, modify and distribute this software for any + purpose and without fee is hereby granted, provided that the above + copyright notice and this permission notice appear in all copies, + and the name of INRIA, IMAG, or any contributor not be used in advertising + or publicity pertaining to this material without the prior explicit + permission. The software is provided "as is" without any + warranties, support or liabilities of any kind. + This software is derived from source code from + "University of California at Berkeley" and + "Digital Equipment Corporation" protected by copyrights. + + Grenoble's Institute of Computer Science and Applied Mathematics (IMAG) + is a federation of seven research units funded by the CNRS, National + Polytechnic Institute of Grenoble and University Joseph Fourier. + The research unit in Software, Systems, Networks (LSR) is member of IMAG. +*/ + +/* + * Derived from : + * + * + * ipcp.c - PPP IP Control Protocol. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: ipv6cp.c,v 1.21 2005/08/25 23:59:34 paulus Exp $ + */ + +/* + * @todo: + * + * Proxy Neighbour Discovery. + * + * Better defines for selecting the ordering of + * interface up / set address. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPP_IPV6_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if 0 /* UNUSED */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/fsm.h" +#include "netif/ppp/ipcp.h" +#include "netif/ppp/ipv6cp.h" +#include "netif/ppp/magic.h" + +/* global vars */ +#if 0 /* UNUSED */ +int no_ifaceid_neg = 0; +#endif /* UNUSED */ + +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void ipv6cp_resetci(fsm *f); /* Reset our CI */ +static int ipv6cp_cilen(fsm *f); /* Return length of our CI */ +static void ipv6cp_addci(fsm *f, u_char *ucp, int *lenp); /* Add our CI */ +static int ipv6cp_ackci(fsm *f, u_char *p, int len); /* Peer ack'd our CI */ +static int ipv6cp_nakci(fsm *f, u_char *p, int len, int treat_as_reject); /* Peer nak'd our CI */ +static int ipv6cp_rejci(fsm *f, u_char *p, int len); /* Peer rej'd our CI */ +static int ipv6cp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree); /* Rcv CI */ +static void ipv6cp_up(fsm *f); /* We're UP */ +static void ipv6cp_down(fsm *f); /* We're DOWN */ +static void ipv6cp_finished(fsm *f); /* Don't need lower layer */ + +static const fsm_callbacks ipv6cp_callbacks = { /* IPV6CP callback routines */ + ipv6cp_resetci, /* Reset our Configuration Information */ + ipv6cp_cilen, /* Length of our Configuration Information */ + ipv6cp_addci, /* Add our Configuration Information */ + ipv6cp_ackci, /* ACK our Configuration Information */ + ipv6cp_nakci, /* NAK our Configuration Information */ + ipv6cp_rejci, /* Reject our Configuration Information */ + ipv6cp_reqci, /* Request peer's Configuration Information */ + ipv6cp_up, /* Called when fsm reaches OPENED state */ + ipv6cp_down, /* Called when fsm leaves OPENED state */ + NULL, /* Called when we want the lower layer up */ + ipv6cp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + NULL, /* Called to handle protocol-specific codes */ + "IPV6CP" /* String name of protocol */ +}; + +#if PPP_OPTIONS +/* + * Command-line options. + */ +static int setifaceid(char **arg)); +static void printifaceid(option_t *, + void (*)(void *, char *, ...), void *)); + +static option_t ipv6cp_option_list[] = { + { "ipv6", o_special, (void *)setifaceid, + "Set interface identifiers for IPV6", + OPT_A2PRINTER, (void *)printifaceid }, + + { "+ipv6", o_bool, &ipv6cp_protent.enabled_flag, + "Enable IPv6 and IPv6CP", OPT_PRIO | 1 }, + { "noipv6", o_bool, &ipv6cp_protent.enabled_flag, + "Disable IPv6 and IPv6CP", OPT_PRIOSUB }, + { "-ipv6", o_bool, &ipv6cp_protent.enabled_flag, + "Disable IPv6 and IPv6CP", OPT_PRIOSUB | OPT_ALIAS }, + + { "ipv6cp-accept-local", o_bool, &ipv6cp_allowoptions[0].accept_local, + "Accept peer's interface identifier for us", 1 }, + + { "ipv6cp-use-ipaddr", o_bool, &ipv6cp_allowoptions[0].use_ip, + "Use (default) IPv4 address as interface identifier", 1 }, + + { "ipv6cp-use-persistent", o_bool, &ipv6cp_wantoptions[0].use_persistent, + "Use uniquely-available persistent value for link local address", 1 }, + + { "ipv6cp-restart", o_int, &ipv6cp_fsm[0].timeouttime, + "Set timeout for IPv6CP", OPT_PRIO }, + { "ipv6cp-max-terminate", o_int, &ipv6cp_fsm[0].maxtermtransmits, + "Set max #xmits for term-reqs", OPT_PRIO }, + { "ipv6cp-max-configure", o_int, &ipv6cp_fsm[0].maxconfreqtransmits, + "Set max #xmits for conf-reqs", OPT_PRIO }, + { "ipv6cp-max-failure", o_int, &ipv6cp_fsm[0].maxnakloops, + "Set max #conf-naks for IPv6CP", OPT_PRIO }, + + { NULL } +}; +#endif /* PPP_OPTIONS */ + +/* + * Protocol entry points from main code. + */ +static void ipv6cp_init(ppp_pcb *pcb); +static void ipv6cp_open(ppp_pcb *pcb); +static void ipv6cp_close(ppp_pcb *pcb, const char *reason); +static void ipv6cp_lowerup(ppp_pcb *pcb); +static void ipv6cp_lowerdown(ppp_pcb *pcb); +static void ipv6cp_input(ppp_pcb *pcb, u_char *p, int len); +static void ipv6cp_protrej(ppp_pcb *pcb); +#if PPP_OPTIONS +static void ipv6_check_options(void); +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT +static int ipv6_demand_conf(int u); +#endif /* DEMAND_SUPPORT */ +#if PRINTPKT_SUPPORT +static int ipv6cp_printpkt(const u_char *p, int plen, + void (*printer)(void *, const char *, ...), void *arg); +#endif /* PRINTPKT_SUPPORT */ +#if DEMAND_SUPPORT +static int ipv6_active_pkt(u_char *pkt, int len); +#endif /* DEMAND_SUPPORT */ + +const struct protent ipv6cp_protent = { + PPP_IPV6CP, + ipv6cp_init, + ipv6cp_input, + ipv6cp_protrej, + ipv6cp_lowerup, + ipv6cp_lowerdown, + ipv6cp_open, + ipv6cp_close, +#if PRINTPKT_SUPPORT + ipv6cp_printpkt, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + NULL, +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "IPV6CP", + "IPV6", +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + ipv6cp_option_list, + ipv6_check_options, +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + ipv6_demand_conf, + ipv6_active_pkt +#endif /* DEMAND_SUPPORT */ +}; + +static void ipv6cp_clear_addrs(ppp_pcb *pcb, eui64_t ourid, eui64_t hisid); +#if 0 /* UNUSED */ +static void ipv6cp_script(char *)); +static void ipv6cp_script_done(void *)); +#endif /* UNUSED */ + +/* + * Lengths of configuration options. + */ +#define CILEN_VOID 2 +#define CILEN_COMPRESS 4 /* length for RFC2023 compress opt. */ +#define CILEN_IFACEID 10 /* RFC2472, interface identifier */ + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + +#if 0 /* UNUSED */ +/* + * This state variable is used to ensure that we don't + * run an ipcp-up/down script while one is already running. + */ +static enum script_state { + s_down, + s_up, +} ipv6cp_script_state; +static pid_t ipv6cp_script_pid; +#endif /* UNUSED */ + +static char *llv6_ntoa(eui64_t ifaceid); + +#if PPP_OPTIONS +/* + * setifaceid - set the interface identifiers manually + */ +static int +setifaceid(argv) + char **argv; +{ + char *comma, *arg, c; + ipv6cp_options *wo = &ipv6cp_wantoptions[0]; + struct in6_addr addr; + static int prio_local, prio_remote; + +#define VALIDID(a) ( (((a).s6_addr32[0] == 0) && ((a).s6_addr32[1] == 0)) && \ + (((a).s6_addr32[2] != 0) || ((a).s6_addr32[3] != 0)) ) + + arg = *argv; + if ((comma = strchr(arg, ',')) == NULL) + comma = arg + strlen(arg); + + /* + * If comma first character, then no local identifier + */ + if (comma != arg) { + c = *comma; + *comma = '\0'; + + if (inet_pton(AF_INET6, arg, &addr) == 0 || !VALIDID(addr)) { + option_error("Illegal interface identifier (local): %s", arg); + return 0; + } + + if (option_priority >= prio_local) { + eui64_copy(addr.s6_addr32[2], wo->ourid); + wo->opt_local = 1; + prio_local = option_priority; + } + *comma = c; + } + + /* + * If comma last character, the no remote identifier + */ + if (*comma != 0 && *++comma != '\0') { + if (inet_pton(AF_INET6, comma, &addr) == 0 || !VALIDID(addr)) { + option_error("Illegal interface identifier (remote): %s", comma); + return 0; + } + if (option_priority >= prio_remote) { + eui64_copy(addr.s6_addr32[2], wo->hisid); + wo->opt_remote = 1; + prio_remote = option_priority; + } + } + + if (override_value("+ipv6", option_priority, option_source)) + ipv6cp_protent.enabled_flag = 1; + return 1; +} + +static void +printifaceid(opt, printer, arg) + option_t *opt; + void (*printer)(void *, char *, ...)); + void *arg; +{ + ipv6cp_options *wo = &ipv6cp_wantoptions[0]; + + if (wo->opt_local) + printer(arg, "%s", llv6_ntoa(wo->ourid)); + printer(arg, ","); + if (wo->opt_remote) + printer(arg, "%s", llv6_ntoa(wo->hisid)); +} +#endif /* PPP_OPTIONS */ + +/* + * Make a string representation of a network address. + */ +static char * +llv6_ntoa(eui64_t ifaceid) +{ + static char b[26]; + + sprintf(b, "fe80::%02x%02x:%02x%02x:%02x%02x:%02x%02x", + ifaceid.e8[0], ifaceid.e8[1], ifaceid.e8[2], ifaceid.e8[3], + ifaceid.e8[4], ifaceid.e8[5], ifaceid.e8[6], ifaceid.e8[7]); + + return b; +} + + +/* + * ipv6cp_init - Initialize IPV6CP. + */ +static void ipv6cp_init(ppp_pcb *pcb) { + fsm *f = &pcb->ipv6cp_fsm; + ipv6cp_options *wo = &pcb->ipv6cp_wantoptions; + ipv6cp_options *ao = &pcb->ipv6cp_allowoptions; + + f->pcb = pcb; + f->protocol = PPP_IPV6CP; + f->callbacks = &ipv6cp_callbacks; + fsm_init(f); + +#if 0 /* Not necessary, everything is cleared in ppp_new() */ + memset(wo, 0, sizeof(*wo)); + memset(ao, 0, sizeof(*ao)); +#endif /* 0 */ + + wo->accept_local = 1; + wo->neg_ifaceid = 1; + ao->neg_ifaceid = 1; + +#ifdef IPV6CP_COMP + wo->neg_vj = 1; + ao->neg_vj = 1; + wo->vj_protocol = IPV6CP_COMP; +#endif + +} + + +/* + * ipv6cp_open - IPV6CP is allowed to come up. + */ +static void ipv6cp_open(ppp_pcb *pcb) { + fsm_open(&pcb->ipv6cp_fsm); +} + + +/* + * ipv6cp_close - Take IPV6CP down. + */ +static void ipv6cp_close(ppp_pcb *pcb, const char *reason) { + fsm_close(&pcb->ipv6cp_fsm, reason); +} + + +/* + * ipv6cp_lowerup - The lower layer is up. + */ +static void ipv6cp_lowerup(ppp_pcb *pcb) { + fsm_lowerup(&pcb->ipv6cp_fsm); +} + + +/* + * ipv6cp_lowerdown - The lower layer is down. + */ +static void ipv6cp_lowerdown(ppp_pcb *pcb) { + fsm_lowerdown(&pcb->ipv6cp_fsm); +} + + +/* + * ipv6cp_input - Input IPV6CP packet. + */ +static void ipv6cp_input(ppp_pcb *pcb, u_char *p, int len) { + fsm_input(&pcb->ipv6cp_fsm, p, len); +} + + +/* + * ipv6cp_protrej - A Protocol-Reject was received for IPV6CP. + * + * Pretend the lower layer went down, so we shut up. + */ +static void ipv6cp_protrej(ppp_pcb *pcb) { + fsm_lowerdown(&pcb->ipv6cp_fsm); +} + + +/* + * ipv6cp_resetci - Reset our CI. + */ +static void ipv6cp_resetci(fsm *f) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *wo = &pcb->ipv6cp_wantoptions; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + ipv6cp_options *ao = &pcb->ipv6cp_allowoptions; + + wo->req_ifaceid = wo->neg_ifaceid && ao->neg_ifaceid; + + if (!wo->opt_local) { + eui64_magic_nz(wo->ourid); + } + + *go = *wo; + eui64_zero(go->hisid); /* last proposed interface identifier */ +} + + +/* + * ipv6cp_cilen - Return length of our CI. + */ +static int ipv6cp_cilen(fsm *f) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + +#ifdef IPV6CP_COMP +#define LENCIVJ(neg) (neg ? CILEN_COMPRESS : 0) +#endif /* IPV6CP_COMP */ +#define LENCIIFACEID(neg) (neg ? CILEN_IFACEID : 0) + + return (LENCIIFACEID(go->neg_ifaceid) + +#ifdef IPV6CP_COMP + LENCIVJ(go->neg_vj) + +#endif /* IPV6CP_COMP */ + 0); +} + + +/* + * ipv6cp_addci - Add our desired CIs to a packet. + */ +static void ipv6cp_addci(fsm *f, u_char *ucp, int *lenp) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + int len = *lenp; + +#ifdef IPV6CP_COMP +#define ADDCIVJ(opt, neg, val) \ + if (neg) { \ + int vjlen = CILEN_COMPRESS; \ + if (len >= vjlen) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(vjlen, ucp); \ + PUTSHORT(val, ucp); \ + len -= vjlen; \ + } else \ + neg = 0; \ + } +#endif /* IPV6CP_COMP */ + +#define ADDCIIFACEID(opt, neg, val1) \ + if (neg) { \ + int idlen = CILEN_IFACEID; \ + if (len >= idlen) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(idlen, ucp); \ + eui64_put(val1, ucp); \ + len -= idlen; \ + } else \ + neg = 0; \ + } + + ADDCIIFACEID(CI_IFACEID, go->neg_ifaceid, go->ourid); + +#ifdef IPV6CP_COMP + ADDCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol); +#endif /* IPV6CP_COMP */ + + *lenp -= len; +} + + +/* + * ipv6cp_ackci - Ack our CIs. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int ipv6cp_ackci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + u_short cilen, citype; +#ifdef IPV6CP_COMP + u_short cishort; +#endif /* IPV6CP_COMP */ + eui64_t ifaceid; + + /* + * CIs must be in exactly the same order that we sent... + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ + +#ifdef IPV6CP_COMP +#define ACKCIVJ(opt, neg, val) \ + if (neg) { \ + int vjlen = CILEN_COMPRESS; \ + if ((len -= vjlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != vjlen || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + } +#endif /* IPV6CP_COMP */ + +#define ACKCIIFACEID(opt, neg, val1) \ + if (neg) { \ + int idlen = CILEN_IFACEID; \ + if ((len -= idlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != idlen || \ + citype != opt) \ + goto bad; \ + eui64_get(ifaceid, p); \ + if (! eui64_equals(val1, ifaceid)) \ + goto bad; \ + } + + ACKCIIFACEID(CI_IFACEID, go->neg_ifaceid, go->ourid); + +#ifdef IPV6CP_COMP + ACKCIVJ(CI_COMPRESSTYPE, go->neg_vj, go->vj_protocol); +#endif /* IPV6CP_COMP */ + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + return (1); + +bad: + IPV6CPDEBUG(("ipv6cp_ackci: received bad Ack!")); + return (0); +} + +/* + * ipv6cp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if IPV6CP is in the OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int ipv6cp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + u_char citype, cilen, *next; +#ifdef IPV6CP_COMP + u_short cishort; +#endif /* IPV6CP_COMP */ + eui64_t ifaceid; + ipv6cp_options no; /* options we've seen Naks for */ + ipv6cp_options try_; /* options to request next time */ + + BZERO(&no, sizeof(no)); + try_ = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIIFACEID(opt, neg, code) \ + if (go->neg && \ + len >= (cilen = CILEN_IFACEID) && \ + p[1] == cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + eui64_get(ifaceid, p); \ + no.neg = 1; \ + code \ + } + +#ifdef IPV6CP_COMP +#define NAKCIVJ(opt, neg, code) \ + if (go->neg && \ + ((cilen = p[1]) == CILEN_COMPRESS) && \ + len >= cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } +#endif /* IPV6CP_COMP */ + + /* + * Accept the peer's idea of {our,his} interface identifier, if different + * from our idea, only if the accept_{local,remote} flag is set. + */ + NAKCIIFACEID(CI_IFACEID, neg_ifaceid, + if (treat_as_reject) { + try_.neg_ifaceid = 0; + } else if (go->accept_local) { + while (eui64_iszero(ifaceid) || + eui64_equals(ifaceid, go->hisid)) /* bad luck */ + eui64_magic(ifaceid); + try_.ourid = ifaceid; + IPV6CPDEBUG(("local LL address %s", llv6_ntoa(ifaceid))); + } + ); + +#ifdef IPV6CP_COMP + NAKCIVJ(CI_COMPRESSTYPE, neg_vj, + { + if (cishort == IPV6CP_COMP && !treat_as_reject) { + try_.vj_protocol = cishort; + } else { + try_.neg_vj = 0; + } + } + ); +#endif /* IPV6CP_COMP */ + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If they want to negotiate about interface identifier, we comply. + * If they want us to ask for compression, we refuse. + */ + while (len >= CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if ( cilen < CILEN_VOID || (len -= cilen) < 0 ) + goto bad; + next = p + cilen - 2; + + switch (citype) { +#ifdef IPV6CP_COMP + case CI_COMPRESSTYPE: + if (go->neg_vj || no.neg_vj || + (cilen != CILEN_COMPRESS)) + goto bad; + no.neg_vj = 1; + break; +#endif /* IPV6CP_COMP */ + case CI_IFACEID: + if (go->neg_ifaceid || no.neg_ifaceid || cilen != CILEN_IFACEID) + goto bad; + try_.neg_ifaceid = 1; + eui64_get(ifaceid, p); + if (go->accept_local) { + while (eui64_iszero(ifaceid) || + eui64_equals(ifaceid, go->hisid)) /* bad luck */ + eui64_magic(ifaceid); + try_.ourid = ifaceid; + } + no.neg_ifaceid = 1; + break; + default: + break; + } + p = next; + } + + /* If there is still anything left, this packet is bad. */ + if (len != 0) + goto bad; + + /* + * OK, the Nak is good. Now we can update state. + */ + if (f->state != PPP_FSM_OPENED) + *go = try_; + + return 1; + +bad: + IPV6CPDEBUG(("ipv6cp_nakci: received bad Nak!")); + return 0; +} + + +/* + * ipv6cp_rejci - Reject some of our CIs. + */ +static int ipv6cp_rejci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + u_char cilen; +#ifdef IPV6CP_COMP + u_short cishort; +#endif /* IPV6CP_COMP */ + eui64_t ifaceid; + ipv6cp_options try_; /* options to request next time */ + + try_ = *go; + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIIFACEID(opt, neg, val1) \ + if (go->neg && \ + len >= (cilen = CILEN_IFACEID) && \ + p[1] == cilen && \ + p[0] == opt) { \ + len -= cilen; \ + INCPTR(2, p); \ + eui64_get(ifaceid, p); \ + /* Check rejected value. */ \ + if (! eui64_equals(ifaceid, val1)) \ + goto bad; \ + try_.neg = 0; \ + } + +#ifdef IPV6CP_COMP +#define REJCIVJ(opt, neg, val) \ + if (go->neg && \ + p[1] == CILEN_COMPRESS && \ + len >= p[1] && \ + p[0] == opt) { \ + len -= p[1]; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) \ + goto bad; \ + try_.neg = 0; \ + } +#endif /* IPV6CP_COMP */ + + REJCIIFACEID(CI_IFACEID, neg_ifaceid, go->ourid); + +#ifdef IPV6CP_COMP + REJCIVJ(CI_COMPRESSTYPE, neg_vj, go->vj_protocol); +#endif /* IPV6CP_COMP */ + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + /* + * Now we can update state. + */ + if (f->state != PPP_FSM_OPENED) + *go = try_; + return 1; + +bad: + IPV6CPDEBUG(("ipv6cp_rejci: received bad Reject!")); + return 0; +} + + +/* + * ipv6cp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + * + * inp = Requested CIs + * len = Length of requested CIs + * + */ +static int ipv6cp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *wo = &pcb->ipv6cp_wantoptions; + ipv6cp_options *ho = &pcb->ipv6cp_hisoptions; + ipv6cp_options *ao = &pcb->ipv6cp_allowoptions; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + u_char *cip, *next; /* Pointer to current and next CIs */ + u_short cilen, citype; /* Parsed len, type */ +#ifdef IPV6CP_COMP + u_short cishort; /* Parsed short value */ +#endif /* IPV6CP_COMP */ + eui64_t ifaceid; /* Parsed interface identifier */ + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *ucp = inp; /* Pointer to current output char */ + int l = *len; /* Length left */ + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + IPV6CPDEBUG(("ipv6cp_reqci: bad CI length!")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ + case CI_IFACEID: + IPV6CPDEBUG(("ipv6cp: received interface identifier ")); + + if (!ao->neg_ifaceid || + cilen != CILEN_IFACEID) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + + /* + * If he has no interface identifier, or if we both have same + * identifier then NAK it with new idea. + * In particular, if we don't know his identifier, but he does, + * then accept it. + */ + eui64_get(ifaceid, p); + IPV6CPDEBUG(("(%s)", llv6_ntoa(ifaceid))); + if (eui64_iszero(ifaceid) && eui64_iszero(go->ourid)) { + orc = CONFREJ; /* Reject CI */ + break; + } + if (!eui64_iszero(wo->hisid) && + !eui64_equals(ifaceid, wo->hisid) && + eui64_iszero(go->hisid)) { + + orc = CONFNAK; + ifaceid = wo->hisid; + go->hisid = ifaceid; + DECPTR(sizeof(ifaceid), p); + eui64_put(ifaceid, p); + } else + if (eui64_iszero(ifaceid) || eui64_equals(ifaceid, go->ourid)) { + orc = CONFNAK; + if (eui64_iszero(go->hisid)) /* first time, try option */ + ifaceid = wo->hisid; + while (eui64_iszero(ifaceid) || + eui64_equals(ifaceid, go->ourid)) /* bad luck */ + eui64_magic(ifaceid); + go->hisid = ifaceid; + DECPTR(sizeof(ifaceid), p); + eui64_put(ifaceid, p); + } + + ho->neg_ifaceid = 1; + ho->hisid = ifaceid; + break; + +#ifdef IPV6CP_COMP + case CI_COMPRESSTYPE: + IPV6CPDEBUG(("ipv6cp: received COMPRESSTYPE ")); + if (!ao->neg_vj || + (cilen != CILEN_COMPRESS)) { + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + IPV6CPDEBUG(("(%d)", cishort)); + + if (!(cishort == IPV6CP_COMP)) { + orc = CONFREJ; + break; + } + + ho->neg_vj = 1; + ho->vj_protocol = cishort; + break; +#endif /* IPV6CP_COMP */ + + default: + orc = CONFREJ; + break; + } + +endswitch: + IPV6CPDEBUG((" (%s)\n", CODENAME(orc))); + + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) /* but prior CI wasnt? */ + continue; /* Don't send this one */ + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree) /* Getting fed up with sending NAKs? */ + orc = CONFREJ; /* Get tough if so */ + else { + if (rc == CONFREJ) /* Rejecting prior CI? */ + continue; /* Don't send this one */ + if (rc == CONFACK) { /* Ack'd all prior CIs? */ + rc = CONFNAK; /* Not anymore... */ + ucp = inp; /* Backup */ + } + } + } + + if (orc == CONFREJ && /* Reject this CI */ + rc != CONFREJ) { /* but no prior ones? */ + rc = CONFREJ; + ucp = inp; /* Backup */ + } + + /* Need to move CI? */ + if (ucp != cip) + MEMCPY(ucp, cip, cilen); /* Move it */ + + /* Update output pointer */ + INCPTR(cilen, ucp); + } + + /* + * If we aren't rejecting this packet, and we want to negotiate + * their identifier and they didn't send their identifier, then we + * send a NAK with a CI_IFACEID option appended. We assume the + * input buffer is long enough that we can append the extra + * option safely. + */ + if (rc != CONFREJ && !ho->neg_ifaceid && + wo->req_ifaceid && !reject_if_disagree) { + if (rc == CONFACK) { + rc = CONFNAK; + ucp = inp; /* reset pointer */ + wo->req_ifaceid = 0; /* don't ask again */ + } + PUTCHAR(CI_IFACEID, ucp); + PUTCHAR(CILEN_IFACEID, ucp); + eui64_put(wo->hisid, ucp); + } + + *len = ucp - inp; /* Compute output length */ + IPV6CPDEBUG(("ipv6cp: returning Configure-%s", CODENAME(rc))); + return (rc); /* Return final code */ +} + +#if PPP_OPTIONS +/* + * ipv6_check_options - check that any IP-related options are OK, + * and assign appropriate defaults. + */ +static void ipv6_check_options() { + ipv6cp_options *wo = &ipv6cp_wantoptions[0]; + + if (!ipv6cp_protent.enabled_flag) + return; + + /* + * Persistent link-local id is only used when user has not explicitly + * configure/hard-code the id + */ + if ((wo->use_persistent) && (!wo->opt_local) && (!wo->opt_remote)) { + + /* + * On systems where there are no Ethernet interfaces used, there + * may be other ways to obtain a persistent id. Right now, it + * will fall back to using magic [see eui64_magic] below when + * an EUI-48 from MAC address can't be obtained. Other possibilities + * include obtaining EEPROM serial numbers, or some other unique + * yet persistent number. On Sparc platforms, this is possible, + * but too bad there's no standards yet for x86 machines. + */ + if (ether_to_eui64(&wo->ourid)) { + wo->opt_local = 1; + } + } + + if (!wo->opt_local) { /* init interface identifier */ + if (wo->use_ip && eui64_iszero(wo->ourid)) { + eui64_setlo32(wo->ourid, lwip_ntohl(ipcp_wantoptions[0].ouraddr)); + if (!eui64_iszero(wo->ourid)) + wo->opt_local = 1; + } + + while (eui64_iszero(wo->ourid)) + eui64_magic(wo->ourid); + } + + if (!wo->opt_remote) { + if (wo->use_ip && eui64_iszero(wo->hisid)) { + eui64_setlo32(wo->hisid, lwip_ntohl(ipcp_wantoptions[0].hisaddr)); + if (!eui64_iszero(wo->hisid)) + wo->opt_remote = 1; + } + } + + if (demand && (eui64_iszero(wo->ourid) || eui64_iszero(wo->hisid))) { + option_error("local/remote LL address required for demand-dialling\n"); + exit(1); + } +} +#endif /* PPP_OPTIONS */ + +#if DEMAND_SUPPORT +/* + * ipv6_demand_conf - configure the interface as though + * IPV6CP were up, for use with dial-on-demand. + */ +static int ipv6_demand_conf(int u) { + ipv6cp_options *wo = &ipv6cp_wantoptions[u]; + + if (!sif6up(u)) + return 0; + + if (!sif6addr(u, wo->ourid, wo->hisid)) + return 0; + + if (!sifnpmode(u, PPP_IPV6, NPMODE_QUEUE)) + return 0; + + ppp_notice("ipv6_demand_conf"); + ppp_notice("local LL address %s", llv6_ntoa(wo->ourid)); + ppp_notice("remote LL address %s", llv6_ntoa(wo->hisid)); + + return 1; +} +#endif /* DEMAND_SUPPORT */ + + +/* + * ipv6cp_up - IPV6CP has come UP. + * + * Configure the IPv6 network interface appropriately and bring it up. + */ +static void ipv6cp_up(fsm *f) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *wo = &pcb->ipv6cp_wantoptions; + ipv6cp_options *ho = &pcb->ipv6cp_hisoptions; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + + IPV6CPDEBUG(("ipv6cp: up")); + + /* + * We must have a non-zero LL address for both ends of the link. + */ + if (!ho->neg_ifaceid) + ho->hisid = wo->hisid; + +#if 0 /* UNUSED */ + if(!no_ifaceid_neg) { +#endif /* UNUSED */ + if (eui64_iszero(ho->hisid)) { + ppp_error("Could not determine remote LL address"); + ipv6cp_close(f->pcb, "Could not determine remote LL address"); + return; + } + if (eui64_iszero(go->ourid)) { + ppp_error("Could not determine local LL address"); + ipv6cp_close(f->pcb, "Could not determine local LL address"); + return; + } + if (eui64_equals(go->ourid, ho->hisid)) { + ppp_error("local and remote LL addresses are equal"); + ipv6cp_close(f->pcb, "local and remote LL addresses are equal"); + return; + } +#if 0 /* UNUSED */ + } +#endif /* UNUSED */ +#if 0 /* UNUSED */ + script_setenv("LLLOCAL", llv6_ntoa(go->ourid), 0); + script_setenv("LLREMOTE", llv6_ntoa(ho->hisid), 0); +#endif /* UNUSED */ + +#ifdef IPV6CP_COMP + /* set tcp compression */ + sif6comp(f->unit, ho->neg_vj); +#endif + +#if DEMAND_SUPPORT + /* + * If we are doing dial-on-demand, the interface is already + * configured, so we put out any saved-up packets, then set the + * interface to pass IPv6 packets. + */ + if (demand) { + if (! eui64_equals(go->ourid, wo->ourid) || + ! eui64_equals(ho->hisid, wo->hisid)) { + if (! eui64_equals(go->ourid, wo->ourid)) + warn("Local LL address changed to %s", + llv6_ntoa(go->ourid)); + if (! eui64_equals(ho->hisid, wo->hisid)) + warn("Remote LL address changed to %s", + llv6_ntoa(ho->hisid)); + ipv6cp_clear_addrs(f->pcb, go->ourid, ho->hisid); + + /* Set the interface to the new addresses */ + if (!sif6addr(f->pcb, go->ourid, ho->hisid)) { + if (debug) + warn("sif6addr failed"); + ipv6cp_close(f->unit, "Interface configuration failed"); + return; + } + + } + demand_rexmit(PPP_IPV6); + sifnpmode(f->unit, PPP_IPV6, NPMODE_PASS); + + } else +#endif /* DEMAND_SUPPORT */ + { + /* + * Set LL addresses + */ + if (!sif6addr(f->pcb, go->ourid, ho->hisid)) { + PPPDEBUG(LOG_DEBUG, ("sif6addr failed")); + ipv6cp_close(f->pcb, "Interface configuration failed"); + return; + } + + /* bring the interface up for IPv6 */ + if (!sif6up(f->pcb)) { + PPPDEBUG(LOG_DEBUG, ("sif6up failed (IPV6)")); + ipv6cp_close(f->pcb, "Interface configuration failed"); + return; + } +#if DEMAND_SUPPORT + sifnpmode(f->pcb, PPP_IPV6, NPMODE_PASS); +#endif /* DEMAND_SUPPORT */ + + ppp_notice("local LL address %s", llv6_ntoa(go->ourid)); + ppp_notice("remote LL address %s", llv6_ntoa(ho->hisid)); + } + + np_up(f->pcb, PPP_IPV6); + pcb->ipv6cp_is_up = 1; + +#if 0 /* UNUSED */ + /* + * Execute the ipv6-up script, like this: + * /etc/ppp/ipv6-up interface tty speed local-LL remote-LL + */ + if (ipv6cp_script_state == s_down && ipv6cp_script_pid == 0) { + ipv6cp_script_state = s_up; + ipv6cp_script(_PATH_IPV6UP); + } +#endif /* UNUSED */ +} + + +/* + * ipv6cp_down - IPV6CP has gone DOWN. + * + * Take the IPv6 network interface down, clear its addresses + * and delete routes through it. + */ +static void ipv6cp_down(fsm *f) { + ppp_pcb *pcb = f->pcb; + ipv6cp_options *go = &pcb->ipv6cp_gotoptions; + ipv6cp_options *ho = &pcb->ipv6cp_hisoptions; + + IPV6CPDEBUG(("ipv6cp: down")); +#if PPP_STATS_SUPPORT + update_link_stats(f->unit); +#endif /* PPP_STATS_SUPPORT */ + if (pcb->ipv6cp_is_up) { + pcb->ipv6cp_is_up = 0; + np_down(f->pcb, PPP_IPV6); + } +#ifdef IPV6CP_COMP + sif6comp(f->unit, 0); +#endif + +#if DEMAND_SUPPORT + /* + * If we are doing dial-on-demand, set the interface + * to queue up outgoing packets (for now). + */ + if (demand) { + sifnpmode(f->pcb, PPP_IPV6, NPMODE_QUEUE); + } else +#endif /* DEMAND_SUPPORT */ + { +#if DEMAND_SUPPORT + sifnpmode(f->pcb, PPP_IPV6, NPMODE_DROP); +#endif /* DEMAND_SUPPORT */ + ipv6cp_clear_addrs(f->pcb, + go->ourid, + ho->hisid); + sif6down(f->pcb); + } + +#if 0 /* UNUSED */ + /* Execute the ipv6-down script */ + if (ipv6cp_script_state == s_up && ipv6cp_script_pid == 0) { + ipv6cp_script_state = s_down; + ipv6cp_script(_PATH_IPV6DOWN); + } +#endif /* UNUSED */ +} + + +/* + * ipv6cp_clear_addrs() - clear the interface addresses, routes, + * proxy neighbour discovery entries, etc. + */ +static void ipv6cp_clear_addrs(ppp_pcb *pcb, eui64_t ourid, eui64_t hisid) { + cif6addr(pcb, ourid, hisid); +} + + +/* + * ipv6cp_finished - possibly shut down the lower layers. + */ +static void ipv6cp_finished(fsm *f) { + np_finished(f->pcb, PPP_IPV6); +} + + +#if 0 /* UNUSED */ +/* + * ipv6cp_script_done - called when the ipv6-up or ipv6-down script + * has finished. + */ +static void +ipv6cp_script_done(arg) + void *arg; +{ + ipv6cp_script_pid = 0; + switch (ipv6cp_script_state) { + case s_up: + if (ipv6cp_fsm[0].state != PPP_FSM_OPENED) { + ipv6cp_script_state = s_down; + ipv6cp_script(_PATH_IPV6DOWN); + } + break; + case s_down: + if (ipv6cp_fsm[0].state == PPP_FSM_OPENED) { + ipv6cp_script_state = s_up; + ipv6cp_script(_PATH_IPV6UP); + } + break; + } +} + + +/* + * ipv6cp_script - Execute a script with arguments + * interface-name tty-name speed local-LL remote-LL. + */ +static void +ipv6cp_script(script) + char *script; +{ + char strspeed[32], strlocal[32], strremote[32]; + char *argv[8]; + + sprintf(strspeed, "%d", baud_rate); + strcpy(strlocal, llv6_ntoa(ipv6cp_gotoptions[0].ourid)); + strcpy(strremote, llv6_ntoa(ipv6cp_hisoptions[0].hisid)); + + argv[0] = script; + argv[1] = ifname; + argv[2] = devnam; + argv[3] = strspeed; + argv[4] = strlocal; + argv[5] = strremote; + argv[6] = ipparam; + argv[7] = NULL; + + ipv6cp_script_pid = run_program(script, argv, 0, ipv6cp_script_done, + NULL, 0); +} +#endif /* UNUSED */ + +#if PRINTPKT_SUPPORT +/* + * ipv6cp_printpkt - print the contents of an IPV6CP packet. + */ +static const char* const ipv6cp_codenames[] = { + "ConfReq", "ConfAck", "ConfNak", "ConfRej", + "TermReq", "TermAck", "CodeRej" +}; + +static int ipv6cp_printpkt(const u_char *p, int plen, + void (*printer)(void *, const char *, ...), void *arg) { + int code, id, len, olen; + const u_char *pstart, *optend; +#ifdef IPV6CP_COMP + u_short cishort; +#endif /* IPV6CP_COMP */ + eui64_t ifaceid; + + if (plen < HEADERLEN) + return 0; + pstart = p; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(ipv6cp_codenames)) + printer(arg, " %s", ipv6cp_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= HEADERLEN; + switch (code) { + case CONFREQ: + case CONFACK: + case CONFNAK: + case CONFREJ: + /* print option list */ + while (len >= 2) { + GETCHAR(code, p); + GETCHAR(olen, p); + p -= 2; + if (olen < 2 || olen > len) { + break; + } + printer(arg, " <"); + len -= olen; + optend = p + olen; + switch (code) { +#ifdef IPV6CP_COMP + case CI_COMPRESSTYPE: + if (olen >= CILEN_COMPRESS) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "compress "); + printer(arg, "0x%x", cishort); + } + break; +#endif /* IPV6CP_COMP */ + case CI_IFACEID: + if (olen == CILEN_IFACEID) { + p += 2; + eui64_get(ifaceid, p); + printer(arg, "addr %s", llv6_ntoa(ifaceid)); + } + break; + default: + break; + } + while (p < optend) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + printer(arg, ">"); + } + break; + + case TERMACK: + case TERMREQ: + if (len > 0 && *p >= ' ' && *p < 0x7f) { + printer(arg, " "); + ppp_print_string(p, len, printer, arg); + p += len; + len = 0; + } + break; + default: + break; + } + + /* print the rest of the bytes in the packet */ + for (; len > 0; --len) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + + return p - pstart; +} +#endif /* PRINTPKT_SUPPORT */ + +#if DEMAND_SUPPORT +/* + * ipv6_active_pkt - see if this IP packet is worth bringing the link up for. + * We don't bring the link up for IP fragments or for TCP FIN packets + * with no data. + */ +#define IP6_HDRLEN 40 /* bytes */ +#define IP6_NHDR_FRAG 44 /* fragment IPv6 header */ +#define TCP_HDRLEN 20 +#define TH_FIN 0x01 + +/* + * We use these macros because the IP header may be at an odd address, + * and some compilers might use word loads to get th_off or ip_hl. + */ + +#define get_ip6nh(x) (((unsigned char *)(x))[6]) +#define get_tcpoff(x) (((unsigned char *)(x))[12] >> 4) +#define get_tcpflags(x) (((unsigned char *)(x))[13]) + +static int ipv6_active_pkt(u_char *pkt, int len) { + u_char *tcp; + + len -= PPP_HDRLEN; + pkt += PPP_HDRLEN; + if (len < IP6_HDRLEN) + return 0; + if (get_ip6nh(pkt) == IP6_NHDR_FRAG) + return 0; + if (get_ip6nh(pkt) != IPPROTO_TCP) + return 1; + if (len < IP6_HDRLEN + TCP_HDRLEN) + return 0; + tcp = pkt + IP6_HDRLEN; + if ((get_tcpflags(tcp) & TH_FIN) != 0 && len == IP6_HDRLEN + get_tcpoff(tcp) * 4) + return 0; + return 1; +} +#endif /* DEMAND_SUPPORT */ + +#endif /* PPP_SUPPORT && PPP_IPV6_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c new file mode 100644 index 0000000..90ed183 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/lcp.c @@ -0,0 +1,2790 @@ +/* + * lcp.c - PPP Link Control Protocol. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +/* + * @todo: + */ + +#if 0 /* UNUSED */ +#include +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/lcp.h" +#if CHAP_SUPPORT +#include "netif/ppp/chap-new.h" +#endif /* CHAP_SUPPORT */ +#include "netif/ppp/magic.h" + +/* + * When the link comes up we want to be able to wait for a short while, + * or until seeing some input from the peer, before starting to send + * configure-requests. We do this by delaying the fsm_lowerup call. + */ +/* steal a bit in fsm flags word */ +#define DELAYED_UP 0x80 + +static void lcp_delayed_up(void *arg); + +/* + * LCP-related command-line options. + */ +#if 0 /* UNUSED */ +int lcp_echo_interval = 0; /* Interval between LCP echo-requests */ +int lcp_echo_fails = 0; /* Tolerance to unanswered echo-requests */ +#endif /* UNUSED */ + +#if 0 /* UNUSED */ +/* options */ +static u_int lcp_echo_interval = LCP_ECHOINTERVAL; /* Interval between LCP echo-requests */ +static u_int lcp_echo_fails = LCP_MAXECHOFAILS; /* Tolerance to unanswered echo-requests */ +#endif /* UNUSED */ + +#if 0 /* UNUSED */ +#if PPP_LCP_ADAPTIVE +bool lcp_echo_adaptive = 0; /* request echo only if the link was idle */ +#endif +bool lax_recv = 0; /* accept control chars in asyncmap */ +bool noendpoint = 0; /* don't send/accept endpoint discriminator */ +#endif /* UNUSED */ + +#if PPP_OPTIONS +static int noopt (char **); +#endif /* PPP_OPTIONS */ + +#ifdef HAVE_MULTILINK +static int setendpoint (char **); +static void printendpoint (option_t *, void (*)(void *, char *, ...), + void *); +#endif /* HAVE_MULTILINK */ + +#if PPP_OPTIONS +static option_t lcp_option_list[] = { + /* LCP options */ + { "-all", o_special_noarg, (void *)noopt, + "Don't request/allow any LCP options" }, + + { "noaccomp", o_bool, &lcp_wantoptions[0].neg_accompression, + "Disable address/control compression", + OPT_A2CLR, &lcp_allowoptions[0].neg_accompression }, + { "-ac", o_bool, &lcp_wantoptions[0].neg_accompression, + "Disable address/control compression", + OPT_ALIAS | OPT_A2CLR, &lcp_allowoptions[0].neg_accompression }, + + { "asyncmap", o_uint32, &lcp_wantoptions[0].asyncmap, + "Set asyncmap (for received packets)", + OPT_OR, &lcp_wantoptions[0].neg_asyncmap }, + { "-as", o_uint32, &lcp_wantoptions[0].asyncmap, + "Set asyncmap (for received packets)", + OPT_ALIAS | OPT_OR, &lcp_wantoptions[0].neg_asyncmap }, + { "default-asyncmap", o_uint32, &lcp_wantoptions[0].asyncmap, + "Disable asyncmap negotiation", + OPT_OR | OPT_NOARG | OPT_VAL(~0U) | OPT_A2CLR, + &lcp_allowoptions[0].neg_asyncmap }, + { "-am", o_uint32, &lcp_wantoptions[0].asyncmap, + "Disable asyncmap negotiation", + OPT_ALIAS | OPT_OR | OPT_NOARG | OPT_VAL(~0U) | OPT_A2CLR, + &lcp_allowoptions[0].neg_asyncmap }, + + { "nomagic", o_bool, &lcp_wantoptions[0].neg_magicnumber, + "Disable magic number negotiation (looped-back line detection)", + OPT_A2CLR, &lcp_allowoptions[0].neg_magicnumber }, + { "-mn", o_bool, &lcp_wantoptions[0].neg_magicnumber, + "Disable magic number negotiation (looped-back line detection)", + OPT_ALIAS | OPT_A2CLR, &lcp_allowoptions[0].neg_magicnumber }, + + { "mru", o_int, &lcp_wantoptions[0].mru, + "Set MRU (maximum received packet size) for negotiation", + OPT_PRIO, &lcp_wantoptions[0].neg_mru }, + { "default-mru", o_bool, &lcp_wantoptions[0].neg_mru, + "Disable MRU negotiation (use default 1500)", + OPT_PRIOSUB | OPT_A2CLR, &lcp_allowoptions[0].neg_mru }, + { "-mru", o_bool, &lcp_wantoptions[0].neg_mru, + "Disable MRU negotiation (use default 1500)", + OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR, &lcp_allowoptions[0].neg_mru }, + + { "mtu", o_int, &lcp_allowoptions[0].mru, + "Set our MTU", OPT_LIMITS, NULL, MAXMRU, MINMRU }, + + { "nopcomp", o_bool, &lcp_wantoptions[0].neg_pcompression, + "Disable protocol field compression", + OPT_A2CLR, &lcp_allowoptions[0].neg_pcompression }, + { "-pc", o_bool, &lcp_wantoptions[0].neg_pcompression, + "Disable protocol field compression", + OPT_ALIAS | OPT_A2CLR, &lcp_allowoptions[0].neg_pcompression }, + + { "passive", o_bool, &lcp_wantoptions[0].passive, + "Set passive mode", 1 }, + { "-p", o_bool, &lcp_wantoptions[0].passive, + "Set passive mode", OPT_ALIAS | 1 }, + + { "silent", o_bool, &lcp_wantoptions[0].silent, + "Set silent mode", 1 }, + + { "lcp-echo-failure", o_int, &lcp_echo_fails, + "Set number of consecutive echo failures to indicate link failure", + OPT_PRIO }, + { "lcp-echo-interval", o_int, &lcp_echo_interval, + "Set time in seconds between LCP echo requests", OPT_PRIO }, +#if PPP_LCP_ADAPTIVE + { "lcp-echo-adaptive", o_bool, &lcp_echo_adaptive, + "Suppress LCP echo requests if traffic was received", 1 }, +#endif + { "lcp-restart", o_int, &lcp_fsm[0].timeouttime, + "Set time in seconds between LCP retransmissions", OPT_PRIO }, + { "lcp-max-terminate", o_int, &lcp_fsm[0].maxtermtransmits, + "Set maximum number of LCP terminate-request transmissions", OPT_PRIO }, + { "lcp-max-configure", o_int, &lcp_fsm[0].maxconfreqtransmits, + "Set maximum number of LCP configure-request transmissions", OPT_PRIO }, + { "lcp-max-failure", o_int, &lcp_fsm[0].maxnakloops, + "Set limit on number of LCP configure-naks", OPT_PRIO }, + + { "receive-all", o_bool, &lax_recv, + "Accept all received control characters", 1 }, + +#ifdef HAVE_MULTILINK + { "mrru", o_int, &lcp_wantoptions[0].mrru, + "Maximum received packet size for multilink bundle", + OPT_PRIO, &lcp_wantoptions[0].neg_mrru }, + + { "mpshortseq", o_bool, &lcp_wantoptions[0].neg_ssnhf, + "Use short sequence numbers in multilink headers", + OPT_PRIO | 1, &lcp_allowoptions[0].neg_ssnhf }, + { "nompshortseq", o_bool, &lcp_wantoptions[0].neg_ssnhf, + "Don't use short sequence numbers in multilink headers", + OPT_PRIOSUB | OPT_A2CLR, &lcp_allowoptions[0].neg_ssnhf }, + + { "endpoint", o_special, (void *) setendpoint, + "Endpoint discriminator for multilink", + OPT_PRIO | OPT_A2PRINTER, (void *) printendpoint }, +#endif /* HAVE_MULTILINK */ + + { "noendpoint", o_bool, &noendpoint, + "Don't send or accept multilink endpoint discriminator", 1 }, + + {NULL} +}; +#endif /* PPP_OPTIONS */ + +/* + * Callbacks for fsm code. (CI = Configuration Information) + */ +static void lcp_resetci(fsm *f); /* Reset our CI */ +static int lcp_cilen(fsm *f); /* Return length of our CI */ +static void lcp_addci(fsm *f, u_char *ucp, int *lenp); /* Add our CI to pkt */ +static int lcp_ackci(fsm *f, u_char *p, int len); /* Peer ack'd our CI */ +static int lcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject); /* Peer nak'd our CI */ +static int lcp_rejci(fsm *f, u_char *p, int len); /* Peer rej'd our CI */ +static int lcp_reqci(fsm *f, u_char *inp, int *lenp, int reject_if_disagree); /* Rcv peer CI */ +static void lcp_up(fsm *f); /* We're UP */ +static void lcp_down(fsm *f); /* We're DOWN */ +static void lcp_starting (fsm *); /* We need lower layer up */ +static void lcp_finished (fsm *); /* We need lower layer down */ +static int lcp_extcode(fsm *f, int code, int id, u_char *inp, int len); +static void lcp_rprotrej(fsm *f, u_char *inp, int len); + +/* + * routines to send LCP echos to peer + */ + +static void lcp_echo_lowerup(ppp_pcb *pcb); +static void lcp_echo_lowerdown(ppp_pcb *pcb); +static void LcpEchoTimeout(void *arg); +static void lcp_received_echo_reply(fsm *f, int id, u_char *inp, int len); +static void LcpSendEchoRequest(fsm *f); +static void LcpLinkFailure(fsm *f); +static void LcpEchoCheck(fsm *f); + +static const fsm_callbacks lcp_callbacks = { /* LCP callback routines */ + lcp_resetci, /* Reset our Configuration Information */ + lcp_cilen, /* Length of our Configuration Information */ + lcp_addci, /* Add our Configuration Information */ + lcp_ackci, /* ACK our Configuration Information */ + lcp_nakci, /* NAK our Configuration Information */ + lcp_rejci, /* Reject our Configuration Information */ + lcp_reqci, /* Request peer's Configuration Information */ + lcp_up, /* Called when fsm reaches OPENED state */ + lcp_down, /* Called when fsm leaves OPENED state */ + lcp_starting, /* Called when we want the lower layer up */ + lcp_finished, /* Called when we want the lower layer down */ + NULL, /* Called when Protocol-Reject received */ + NULL, /* Retransmission is necessary */ + lcp_extcode, /* Called to handle LCP-specific codes */ + "LCP" /* String name of protocol */ +}; + +/* + * Protocol entry points. + * Some of these are called directly. + */ + +static void lcp_init(ppp_pcb *pcb); +static void lcp_input(ppp_pcb *pcb, u_char *p, int len); +static void lcp_protrej(ppp_pcb *pcb); +#if PRINTPKT_SUPPORT +static int lcp_printpkt(const u_char *p, int plen, + void (*printer) (void *, const char *, ...), void *arg); +#endif /* PRINTPKT_SUPPORT */ + +const struct protent lcp_protent = { + PPP_LCP, + lcp_init, + lcp_input, + lcp_protrej, + lcp_lowerup, + lcp_lowerdown, + lcp_open, + lcp_close, +#if PRINTPKT_SUPPORT + lcp_printpkt, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + NULL, +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "LCP", + NULL, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + lcp_option_list, + NULL, +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + NULL, + NULL +#endif /* DEMAND_SUPPORT */ +}; + +/* + * Length of each type of configuration option (in octets) + */ +#define CILEN_VOID 2 +#define CILEN_CHAR 3 +#define CILEN_SHORT 4 /* CILEN_VOID + 2 */ +#if CHAP_SUPPORT +#define CILEN_CHAP 5 /* CILEN_VOID + 2 + 1 */ +#endif /* CHAP_SUPPORT */ +#define CILEN_LONG 6 /* CILEN_VOID + 4 */ +#if LQR_SUPPORT +#define CILEN_LQR 8 /* CILEN_VOID + 2 + 4 */ +#endif /* LQR_SUPPORT */ +#define CILEN_CBCP 3 + +#define CODENAME(x) ((x) == CONFACK ? "ACK" : \ + (x) == CONFNAK ? "NAK" : "REJ") + +#if PPP_OPTIONS +/* + * noopt - Disable all options (why?). + */ +static int +noopt(argv) + char **argv; +{ + BZERO((char *) &lcp_wantoptions[0], sizeof (struct lcp_options)); + BZERO((char *) &lcp_allowoptions[0], sizeof (struct lcp_options)); + + return (1); +} +#endif /* PPP_OPTIONS */ + +#ifdef HAVE_MULTILINK +static int +setendpoint(argv) + char **argv; +{ + if (str_to_epdisc(&lcp_wantoptions[0].endpoint, *argv)) { + lcp_wantoptions[0].neg_endpoint = 1; + return 1; + } + option_error("Can't parse '%s' as an endpoint discriminator", *argv); + return 0; +} + +static void +printendpoint(opt, printer, arg) + option_t *opt; + void (*printer) (void *, char *, ...); + void *arg; +{ + printer(arg, "%s", epdisc_to_str(&lcp_wantoptions[0].endpoint)); +} +#endif /* HAVE_MULTILINK */ + +/* + * lcp_init - Initialize LCP. + */ +static void lcp_init(ppp_pcb *pcb) { + fsm *f = &pcb->lcp_fsm; + lcp_options *wo = &pcb->lcp_wantoptions; + lcp_options *ao = &pcb->lcp_allowoptions; + + f->pcb = pcb; + f->protocol = PPP_LCP; + f->callbacks = &lcp_callbacks; + + fsm_init(f); + + BZERO(wo, sizeof(*wo)); + wo->neg_mru = 1; + wo->mru = PPP_DEFMRU; + wo->neg_asyncmap = 1; + wo->neg_magicnumber = 1; + wo->neg_pcompression = 1; + wo->neg_accompression = 1; + + BZERO(ao, sizeof(*ao)); + ao->neg_mru = 1; + ao->mru = PPP_MAXMRU; + ao->neg_asyncmap = 1; +#if CHAP_SUPPORT + ao->neg_chap = 1; + ao->chap_mdtype = CHAP_MDTYPE_SUPPORTED; +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + ao->neg_upap = 1; +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + ao->neg_eap = 1; +#endif /* EAP_SUPPORT */ + ao->neg_magicnumber = 1; + ao->neg_pcompression = 1; + ao->neg_accompression = 1; + ao->neg_endpoint = 1; +} + + +/* + * lcp_open - LCP is allowed to come up. + */ +void lcp_open(ppp_pcb *pcb) { + fsm *f = &pcb->lcp_fsm; + lcp_options *wo = &pcb->lcp_wantoptions; + + f->flags &= ~(OPT_PASSIVE | OPT_SILENT); + if (wo->passive) + f->flags |= OPT_PASSIVE; + if (wo->silent) + f->flags |= OPT_SILENT; + fsm_open(f); +} + + +/* + * lcp_close - Take LCP down. + */ +void lcp_close(ppp_pcb *pcb, const char *reason) { + fsm *f = &pcb->lcp_fsm; + int oldstate; + + if (pcb->phase != PPP_PHASE_DEAD +#ifdef HAVE_MULTILINK + && pcb->phase != PPP_PHASE_MASTER +#endif /* HAVE_MULTILINK */ + ) + new_phase(pcb, PPP_PHASE_TERMINATE); + + if (f->flags & DELAYED_UP) { + UNTIMEOUT(lcp_delayed_up, f); + f->state = PPP_FSM_STOPPED; + } + oldstate = f->state; + + fsm_close(f, reason); + if (oldstate == PPP_FSM_STOPPED && (f->flags & (OPT_PASSIVE|OPT_SILENT|DELAYED_UP))) { + /* + * This action is not strictly according to the FSM in RFC1548, + * but it does mean that the program terminates if you do a + * lcp_close() when a connection hasn't been established + * because we are in passive/silent mode or because we have + * delayed the fsm_lowerup() call and it hasn't happened yet. + */ + f->flags &= ~DELAYED_UP; + lcp_finished(f); + } +} + + +/* + * lcp_lowerup - The lower layer is up. + */ +void lcp_lowerup(ppp_pcb *pcb) { + lcp_options *wo = &pcb->lcp_wantoptions; + fsm *f = &pcb->lcp_fsm; + /* + * Don't use A/C or protocol compression on transmission, + * but accept A/C and protocol compressed packets + * if we are going to ask for A/C and protocol compression. + */ + if (ppp_send_config(pcb, PPP_MRU, 0xffffffff, 0, 0) < 0 + || ppp_recv_config(pcb, PPP_MRU, (pcb->settings.lax_recv? 0: 0xffffffff), + wo->neg_pcompression, wo->neg_accompression) < 0) + return; + pcb->peer_mru = PPP_MRU; + + if (pcb->settings.listen_time != 0) { + f->flags |= DELAYED_UP; + TIMEOUTMS(lcp_delayed_up, f, pcb->settings.listen_time); + } else + fsm_lowerup(f); +} + + +/* + * lcp_lowerdown - The lower layer is down. + */ +void lcp_lowerdown(ppp_pcb *pcb) { + fsm *f = &pcb->lcp_fsm; + + if (f->flags & DELAYED_UP) { + f->flags &= ~DELAYED_UP; + UNTIMEOUT(lcp_delayed_up, f); + } else + fsm_lowerdown(f); +} + + +/* + * lcp_delayed_up - Bring the lower layer up now. + */ +static void lcp_delayed_up(void *arg) { + fsm *f = (fsm*)arg; + + if (f->flags & DELAYED_UP) { + f->flags &= ~DELAYED_UP; + fsm_lowerup(f); + } +} + + +/* + * lcp_input - Input LCP packet. + */ +static void lcp_input(ppp_pcb *pcb, u_char *p, int len) { + fsm *f = &pcb->lcp_fsm; + + if (f->flags & DELAYED_UP) { + f->flags &= ~DELAYED_UP; + UNTIMEOUT(lcp_delayed_up, f); + fsm_lowerup(f); + } + fsm_input(f, p, len); +} + +/* + * lcp_extcode - Handle a LCP-specific code. + */ +static int lcp_extcode(fsm *f, int code, int id, u_char *inp, int len) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + u_char *magp; + + switch( code ){ + case PROTREJ: + lcp_rprotrej(f, inp, len); + break; + + case ECHOREQ: + if (f->state != PPP_FSM_OPENED) + break; + magp = inp; + PUTLONG(go->magicnumber, magp); + fsm_sdata(f, ECHOREP, id, inp, len); + break; + + case ECHOREP: + lcp_received_echo_reply(f, id, inp, len); + break; + + case DISCREQ: + case IDENTIF: + case TIMEREM: + break; + + default: + return 0; + } + return 1; +} + + +/* + * lcp_rprotrej - Receive an Protocol-Reject. + * + * Figure out which protocol is rejected and inform it. + */ +static void lcp_rprotrej(fsm *f, u_char *inp, int len) { + int i; + const struct protent *protp; + u_short prot; +#if PPP_PROTOCOLNAME + const char *pname; +#endif /* PPP_PROTOCOLNAME */ + + if (len < 2) { + LCPDEBUG(("lcp_rprotrej: Rcvd short Protocol-Reject packet!")); + return; + } + + GETSHORT(prot, inp); + + /* + * Protocol-Reject packets received in any state other than the LCP + * OPENED state SHOULD be silently discarded. + */ + if( f->state != PPP_FSM_OPENED ){ + LCPDEBUG(("Protocol-Reject discarded: LCP in state %d", f->state)); + return; + } + +#if PPP_PROTOCOLNAME + pname = protocol_name(prot); +#endif /* PPP_PROTOCOLNAME */ + + /* + * Upcall the proper Protocol-Reject routine. + */ + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (protp->protocol == prot) { +#if PPP_PROTOCOLNAME + if (pname != NULL) + ppp_dbglog("Protocol-Reject for '%s' (0x%x) received", pname, + prot); + else +#endif /* PPP_PROTOCOLNAME */ + ppp_dbglog("Protocol-Reject for 0x%x received", prot); + (*protp->protrej)(f->pcb); + return; + } + +#if PPP_PROTOCOLNAME + if (pname != NULL) + ppp_warn("Protocol-Reject for unsupported protocol '%s' (0x%x)", pname, + prot); + else +#endif /* #if PPP_PROTOCOLNAME */ + ppp_warn("Protocol-Reject for unsupported protocol 0x%x", prot); +} + + +/* + * lcp_protrej - A Protocol-Reject was received. + */ +/*ARGSUSED*/ +static void lcp_protrej(ppp_pcb *pcb) { + /* + * Can't reject LCP! + */ + ppp_error("Received Protocol-Reject for LCP!"); + fsm_protreject(&pcb->lcp_fsm); +} + + +/* + * lcp_sprotrej - Send a Protocol-Reject for some protocol. + */ +void lcp_sprotrej(ppp_pcb *pcb, u_char *p, int len) { + fsm *f = &pcb->lcp_fsm; + /* + * Send back the protocol and the information field of the + * rejected packet. We only get here if LCP is in the OPENED state. + */ +#if 0 + p += 2; + len -= 2; +#endif + + fsm_sdata(f, PROTREJ, ++f->id, + p, len); +} + + +/* + * lcp_resetci - Reset our CI. + */ +static void lcp_resetci(fsm *f) { + ppp_pcb *pcb = f->pcb; + lcp_options *wo = &pcb->lcp_wantoptions; + lcp_options *go = &pcb->lcp_gotoptions; + lcp_options *ao = &pcb->lcp_allowoptions; + +#if PPP_AUTH_SUPPORT + + /* note: default value is true for allow options */ + if (pcb->settings.user && pcb->settings.passwd) { +#if PAP_SUPPORT + if (pcb->settings.refuse_pap) { + ao->neg_upap = 0; + } +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + if (pcb->settings.refuse_chap) { + ao->chap_mdtype &= ~MDTYPE_MD5; + } +#if MSCHAP_SUPPORT + if (pcb->settings.refuse_mschap) { + ao->chap_mdtype &= ~MDTYPE_MICROSOFT; + } + if (pcb->settings.refuse_mschap_v2) { + ao->chap_mdtype &= ~MDTYPE_MICROSOFT_V2; + } +#endif /* MSCHAP_SUPPORT */ + ao->neg_chap = (ao->chap_mdtype != MDTYPE_NONE); +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + if (pcb->settings.refuse_eap) { + ao->neg_eap = 0; + } +#endif /* EAP_SUPPORT */ + +#if PPP_SERVER + /* note: default value is false for wanted options */ + if (pcb->settings.auth_required) { +#if PAP_SUPPORT + if (!pcb->settings.refuse_pap) { + wo->neg_upap = 1; + } +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + if (!pcb->settings.refuse_chap) { + wo->chap_mdtype |= MDTYPE_MD5; + } +#if MSCHAP_SUPPORT + if (!pcb->settings.refuse_mschap) { + wo->chap_mdtype |= MDTYPE_MICROSOFT; + } + if (!pcb->settings.refuse_mschap_v2) { + wo->chap_mdtype |= MDTYPE_MICROSOFT_V2; + } +#endif /* MSCHAP_SUPPORT */ + wo->neg_chap = (wo->chap_mdtype != MDTYPE_NONE); +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + if (!pcb->settings.refuse_eap) { + wo->neg_eap = 1; + } +#endif /* EAP_SUPPORT */ + } +#endif /* PPP_SERVER */ + + } else { +#if PAP_SUPPORT + ao->neg_upap = 0; +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + ao->neg_chap = 0; + ao->chap_mdtype = MDTYPE_NONE; +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + ao->neg_eap = 0; +#endif /* EAP_SUPPORT */ + } + + PPPDEBUG(LOG_DEBUG, ("ppp: auth protocols:")); +#if PAP_SUPPORT + PPPDEBUG(LOG_DEBUG, (" PAP=%d", ao->neg_upap)); +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + PPPDEBUG(LOG_DEBUG, (" CHAP=%d CHAP_MD5=%d", ao->neg_chap, !!(ao->chap_mdtype&MDTYPE_MD5))); +#if MSCHAP_SUPPORT + PPPDEBUG(LOG_DEBUG, (" CHAP_MS=%d CHAP_MS2=%d", !!(ao->chap_mdtype&MDTYPE_MICROSOFT), !!(ao->chap_mdtype&MDTYPE_MICROSOFT_V2))); +#endif /* MSCHAP_SUPPORT */ +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + PPPDEBUG(LOG_DEBUG, (" EAP=%d", ao->neg_eap)); +#endif /* EAP_SUPPORT */ + PPPDEBUG(LOG_DEBUG, ("\n")); + +#endif /* PPP_AUTH_SUPPORT */ + + wo->magicnumber = magic(); + wo->numloops = 0; + *go = *wo; +#ifdef HAVE_MULTILINK + if (!multilink) { + go->neg_mrru = 0; +#endif /* HAVE_MULTILINK */ + go->neg_ssnhf = 0; + go->neg_endpoint = 0; +#ifdef HAVE_MULTILINK + } +#endif /* HAVE_MULTILINK */ + if (pcb->settings.noendpoint) + ao->neg_endpoint = 0; + pcb->peer_mru = PPP_MRU; +#if 0 /* UNUSED */ + auth_reset(pcb); +#endif /* UNUSED */ +} + + +/* + * lcp_cilen - Return length of our CI. + */ +static int lcp_cilen(fsm *f) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + +#define LENCIVOID(neg) ((neg) ? CILEN_VOID : 0) +#if CHAP_SUPPORT +#define LENCICHAP(neg) ((neg) ? CILEN_CHAP : 0) +#endif /* CHAP_SUPPORT */ +#define LENCISHORT(neg) ((neg) ? CILEN_SHORT : 0) +#define LENCILONG(neg) ((neg) ? CILEN_LONG : 0) +#if LQR_SUPPORT +#define LENCILQR(neg) ((neg) ? CILEN_LQR: 0) +#endif /* LQR_SUPPORT */ +#define LENCICBCP(neg) ((neg) ? CILEN_CBCP: 0) + /* + * NB: we only ask for one of CHAP, UPAP, or EAP, even if we will + * accept more than one. We prefer EAP first, then CHAP, then + * PAP. + */ + return (LENCISHORT(go->neg_mru && go->mru != PPP_DEFMRU) + + LENCILONG(go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF) + +#if EAP_SUPPORT + LENCISHORT(go->neg_eap) + +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */ +#if EAP_SUPPORT + LENCICHAP(!go->neg_eap && go->neg_chap) + +#endif /* EAP_SUPPORT */ +#if !EAP_SUPPORT + LENCICHAP(go->neg_chap) + +#endif /* !EAP_SUPPORT */ +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */ +#if EAP_SUPPORT && CHAP_SUPPORT + LENCISHORT(!go->neg_eap && !go->neg_chap && go->neg_upap) + +#endif /* EAP_SUPPORT && CHAP_SUPPORT */ +#if EAP_SUPPORT && !CHAP_SUPPORT + LENCISHORT(!go->neg_eap && go->neg_upap) + +#endif /* EAP_SUPPORT && !CHAP_SUPPORT */ +#if !EAP_SUPPORT && CHAP_SUPPORT + LENCISHORT(!go->neg_chap && go->neg_upap) + +#endif /* !EAP_SUPPORT && CHAP_SUPPORT */ +#if !EAP_SUPPORT && !CHAP_SUPPORT + LENCISHORT(go->neg_upap) + +#endif /* !EAP_SUPPORT && !CHAP_SUPPORT */ +#endif /* PAP_SUPPORT */ +#if LQR_SUPPORT + LENCILQR(go->neg_lqr) + +#endif /* LQR_SUPPORT */ + LENCICBCP(go->neg_cbcp) + + LENCILONG(go->neg_magicnumber) + + LENCIVOID(go->neg_pcompression) + + LENCIVOID(go->neg_accompression) + +#ifdef HAVE_MULTILINK + LENCISHORT(go->neg_mrru) + +#endif /* HAVE_MULTILINK */ + LENCIVOID(go->neg_ssnhf) + + (go->neg_endpoint? CILEN_CHAR + go->endpoint.length: 0)); +} + + +/* + * lcp_addci - Add our desired CIs to a packet. + */ +static void lcp_addci(fsm *f, u_char *ucp, int *lenp) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + u_char *start_ucp = ucp; + +#define ADDCIVOID(opt, neg) \ + if (neg) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_VOID, ucp); \ + } +#define ADDCISHORT(opt, neg, val) \ + if (neg) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_SHORT, ucp); \ + PUTSHORT(val, ucp); \ + } +#if CHAP_SUPPORT +#define ADDCICHAP(opt, neg, val) \ + if (neg) { \ + PUTCHAR((opt), ucp); \ + PUTCHAR(CILEN_CHAP, ucp); \ + PUTSHORT(PPP_CHAP, ucp); \ + PUTCHAR((CHAP_DIGEST(val)), ucp); \ + } +#endif /* CHAP_SUPPORT */ +#define ADDCILONG(opt, neg, val) \ + if (neg) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LONG, ucp); \ + PUTLONG(val, ucp); \ + } +#if LQR_SUPPORT +#define ADDCILQR(opt, neg, val) \ + if (neg) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_LQR, ucp); \ + PUTSHORT(PPP_LQR, ucp); \ + PUTLONG(val, ucp); \ + } +#endif /* LQR_SUPPORT */ +#define ADDCICHAR(opt, neg, val) \ + if (neg) { \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAR, ucp); \ + PUTCHAR(val, ucp); \ + } +#define ADDCIENDP(opt, neg, class, val, len) \ + if (neg) { \ + int i; \ + PUTCHAR(opt, ucp); \ + PUTCHAR(CILEN_CHAR + len, ucp); \ + PUTCHAR(class, ucp); \ + for (i = 0; i < len; ++i) \ + PUTCHAR(val[i], ucp); \ + } + + ADDCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ADDCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF, + go->asyncmap); +#if EAP_SUPPORT + ADDCISHORT(CI_AUTHTYPE, go->neg_eap, PPP_EAP); +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */ +#if EAP_SUPPORT + ADDCICHAP(CI_AUTHTYPE, !go->neg_eap && go->neg_chap, go->chap_mdtype); +#endif /* EAP_SUPPORT */ +#if !EAP_SUPPORT + ADDCICHAP(CI_AUTHTYPE, go->neg_chap, go->chap_mdtype); +#endif /* !EAP_SUPPORT */ +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */ +#if EAP_SUPPORT && CHAP_SUPPORT + ADDCISHORT(CI_AUTHTYPE, !go->neg_eap && !go->neg_chap && go->neg_upap, PPP_PAP); +#endif /* EAP_SUPPORT && CHAP_SUPPORT */ +#if EAP_SUPPORT && !CHAP_SUPPORT + ADDCISHORT(CI_AUTHTYPE, !go->neg_eap && go->neg_upap, PPP_PAP); +#endif /* EAP_SUPPORT && !CHAP_SUPPORT */ +#if !EAP_SUPPORT && CHAP_SUPPORT + ADDCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); +#endif /* !EAP_SUPPORT && CHAP_SUPPORT */ +#if !EAP_SUPPORT && !CHAP_SUPPORT + ADDCISHORT(CI_AUTHTYPE, go->neg_upap, PPP_PAP); +#endif /* !EAP_SUPPORT && !CHAP_SUPPORT */ +#endif /* PAP_SUPPORT */ +#if LQR_SUPPORT + ADDCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); +#endif /* LQR_SUPPORT */ + ADDCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ADDCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ADDCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ADDCIVOID(CI_ACCOMPRESSION, go->neg_accompression); +#ifdef HAVE_MULTILINK + ADDCISHORT(CI_MRRU, go->neg_mrru, go->mrru); +#endif + ADDCIVOID(CI_SSNHF, go->neg_ssnhf); + ADDCIENDP(CI_EPDISC, go->neg_endpoint, go->endpoint.class_, + go->endpoint.value, go->endpoint.length); + + if (ucp - start_ucp != *lenp) { + /* this should never happen, because peer_mtu should be 1500 */ + ppp_error("Bug in lcp_addci: wrong length"); + } +} + + +/* + * lcp_ackci - Ack our CIs. + * This should not modify any state if the Ack is bad. + * + * Returns: + * 0 - Ack was bad. + * 1 - Ack was good. + */ +static int lcp_ackci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + u_char cilen, citype, cichar; + u_short cishort; + u32_t cilong; + + /* + * CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define ACKCIVOID(opt, neg) \ + if (neg) { \ + if ((len -= CILEN_VOID) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_VOID || \ + citype != opt) \ + goto bad; \ + } +#define ACKCISHORT(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_SHORT) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_SHORT || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != val) \ + goto bad; \ + } +#define ACKCICHAR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_CHAR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAR || \ + citype != opt) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != val) \ + goto bad; \ + } +#if CHAP_SUPPORT +#define ACKCICHAP(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_CHAP) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAP || \ + citype != (opt)) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != PPP_CHAP) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != (CHAP_DIGEST(val))) \ + goto bad; \ + } +#endif /* CHAP_SUPPORT */ +#define ACKCILONG(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LONG) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LONG || \ + citype != opt) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } +#if LQR_SUPPORT +#define ACKCILQR(opt, neg, val) \ + if (neg) { \ + if ((len -= CILEN_LQR) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_LQR || \ + citype != opt) \ + goto bad; \ + GETSHORT(cishort, p); \ + if (cishort != PPP_LQR) \ + goto bad; \ + GETLONG(cilong, p); \ + if (cilong != val) \ + goto bad; \ + } +#endif /* LQR_SUPPORT */ +#define ACKCIENDP(opt, neg, class, val, vlen) \ + if (neg) { \ + int i; \ + if ((len -= CILEN_CHAR + vlen) < 0) \ + goto bad; \ + GETCHAR(citype, p); \ + GETCHAR(cilen, p); \ + if (cilen != CILEN_CHAR + vlen || \ + citype != opt) \ + goto bad; \ + GETCHAR(cichar, p); \ + if (cichar != class) \ + goto bad; \ + for (i = 0; i < vlen; ++i) { \ + GETCHAR(cichar, p); \ + if (cichar != val[i]) \ + goto bad; \ + } \ + } + + ACKCISHORT(CI_MRU, go->neg_mru && go->mru != PPP_DEFMRU, go->mru); + ACKCILONG(CI_ASYNCMAP, go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF, + go->asyncmap); +#if EAP_SUPPORT + ACKCISHORT(CI_AUTHTYPE, go->neg_eap, PPP_EAP); +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */ +#if EAP_SUPPORT + ACKCICHAP(CI_AUTHTYPE, !go->neg_eap && go->neg_chap, go->chap_mdtype); +#endif /* EAP_SUPPORT */ +#if !EAP_SUPPORT + ACKCICHAP(CI_AUTHTYPE, go->neg_chap, go->chap_mdtype); +#endif /* !EAP_SUPPORT */ +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT /* cannot be improved, embedding a directive within macro arguments is not portable */ +#if EAP_SUPPORT && CHAP_SUPPORT + ACKCISHORT(CI_AUTHTYPE, !go->neg_eap && !go->neg_chap && go->neg_upap, PPP_PAP); +#endif /* EAP_SUPPORT && CHAP_SUPPORT */ +#if EAP_SUPPORT && !CHAP_SUPPORT + ACKCISHORT(CI_AUTHTYPE, !go->neg_eap && go->neg_upap, PPP_PAP); +#endif /* EAP_SUPPORT && !CHAP_SUPPORT */ +#if !EAP_SUPPORT && CHAP_SUPPORT + ACKCISHORT(CI_AUTHTYPE, !go->neg_chap && go->neg_upap, PPP_PAP); +#endif /* !EAP_SUPPORT && CHAP_SUPPORT */ +#if !EAP_SUPPORT && !CHAP_SUPPORT + ACKCISHORT(CI_AUTHTYPE, go->neg_upap, PPP_PAP); +#endif /* !EAP_SUPPORT && !CHAP_SUPPORT */ +#endif /* PAP_SUPPORT */ +#if LQR_SUPPORT + ACKCILQR(CI_QUALITY, go->neg_lqr, go->lqr_period); +#endif /* LQR_SUPPORT */ + ACKCICHAR(CI_CALLBACK, go->neg_cbcp, CBCP_OPT); + ACKCILONG(CI_MAGICNUMBER, go->neg_magicnumber, go->magicnumber); + ACKCIVOID(CI_PCOMPRESSION, go->neg_pcompression); + ACKCIVOID(CI_ACCOMPRESSION, go->neg_accompression); +#ifdef HAVE_MULTILINK + ACKCISHORT(CI_MRRU, go->neg_mrru, go->mrru); +#endif /* HAVE_MULTILINK */ + ACKCIVOID(CI_SSNHF, go->neg_ssnhf); + ACKCIENDP(CI_EPDISC, go->neg_endpoint, go->endpoint.class_, + go->endpoint.value, go->endpoint.length); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + return (1); +bad: + LCPDEBUG(("lcp_acki: received bad Ack!")); + return (0); +} + + +/* + * lcp_nakci - Peer has sent a NAK for some of our CIs. + * This should not modify any state if the Nak is bad + * or if LCP is in the OPENED state. + * + * Returns: + * 0 - Nak was bad. + * 1 - Nak was good. + */ +static int lcp_nakci(fsm *f, u_char *p, int len, int treat_as_reject) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + lcp_options *wo = &pcb->lcp_wantoptions; + u_char citype, cichar, *next; + u_short cishort; + u32_t cilong; + lcp_options no; /* options we've seen Naks for */ + lcp_options try_; /* options to request next time */ + int looped_back = 0; + int cilen; + + BZERO(&no, sizeof(no)); + try_ = *go; + + /* + * Any Nak'd CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define NAKCIVOID(opt, neg) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + no.neg = 1; \ + try_.neg = 0; \ + } +#if CHAP_SUPPORT +#define NAKCICHAP(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#endif /* CHAP_SUPPORT */ +#define NAKCICHAR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_CHAR && \ + p[1] == CILEN_CHAR && \ + p[0] == opt) { \ + len -= CILEN_CHAR; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + no.neg = 1; \ + code \ + } +#define NAKCISHORT(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + no.neg = 1; \ + code \ + } +#define NAKCILONG(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } +#if LQR_SUPPORT +#define NAKCILQR(opt, neg, code) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + no.neg = 1; \ + code \ + } +#endif /* LQR_SUPPORT */ +#define NAKCIENDP(opt, neg) \ + if (go->neg && \ + len >= CILEN_CHAR && \ + p[0] == opt && \ + p[1] >= CILEN_CHAR && \ + p[1] <= len) { \ + len -= p[1]; \ + INCPTR(p[1], p); \ + no.neg = 1; \ + try_.neg = 0; \ + } + + /* + * NOTE! There must be no assignments to individual fields of *go in + * the code below. Any such assignment is a BUG! + */ + /* + * We don't care if they want to send us smaller packets than + * we want. Therefore, accept any MRU less than what we asked for, + * but then ignore the new value when setting the MRU in the kernel. + * If they send us a bigger MRU than what we asked, accept it, up to + * the limit of the default MRU we'd get if we didn't negotiate. + */ + if (go->neg_mru && go->mru != PPP_DEFMRU) { + NAKCISHORT(CI_MRU, neg_mru, + if (cishort <= wo->mru || cishort <= PPP_DEFMRU) + try_.mru = cishort; + ); + } + + /* + * Add any characters they want to our (receive-side) asyncmap. + */ + if (go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF) { + NAKCILONG(CI_ASYNCMAP, neg_asyncmap, + try_.asyncmap = go->asyncmap | cilong; + ); + } + + /* + * If they've nak'd our authentication-protocol, check whether + * they are proposing a different protocol, or a different + * hash algorithm for CHAP. + */ + if ((0 +#if CHAP_SUPPORT + || go->neg_chap +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + || go->neg_upap +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + || go->neg_eap +#endif /* EAP_SUPPORT */ + ) + && len >= CILEN_SHORT + && p[0] == CI_AUTHTYPE && p[1] >= CILEN_SHORT && p[1] <= len) { + cilen = p[1]; + len -= cilen; +#if CHAP_SUPPORT + no.neg_chap = go->neg_chap; +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + no.neg_upap = go->neg_upap; +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + no.neg_eap = go->neg_eap; +#endif /* EAP_SUPPORT */ + INCPTR(2, p); + GETSHORT(cishort, p); + +#if PAP_SUPPORT + if (cishort == PPP_PAP && cilen == CILEN_SHORT) { +#if EAP_SUPPORT + /* If we were asking for EAP, then we need to stop that. */ + if (go->neg_eap) + try_.neg_eap = 0; + else +#endif /* EAP_SUPPORT */ + +#if CHAP_SUPPORT + /* If we were asking for CHAP, then we need to stop that. */ + if (go->neg_chap) + try_.neg_chap = 0; + else +#endif /* CHAP_SUPPORT */ + + /* + * If we weren't asking for CHAP or EAP, then we were asking for + * PAP, in which case this Nak is bad. + */ + goto bad; + } else +#endif /* PAP_SUPPORT */ + +#if CHAP_SUPPORT + if (cishort == PPP_CHAP && cilen == CILEN_CHAP) { + GETCHAR(cichar, p); +#if EAP_SUPPORT + /* Stop asking for EAP, if we were. */ + if (go->neg_eap) { + try_.neg_eap = 0; + /* Try to set up to use their suggestion, if possible */ + if (CHAP_CANDIGEST(go->chap_mdtype, cichar)) + try_.chap_mdtype = CHAP_MDTYPE_D(cichar); + } else +#endif /* EAP_SUPPORT */ + if (go->neg_chap) { + /* + * We were asking for our preferred algorithm, they must + * want something different. + */ + if (cichar != CHAP_DIGEST(go->chap_mdtype)) { + if (CHAP_CANDIGEST(go->chap_mdtype, cichar)) { + /* Use their suggestion if we support it ... */ + try_.chap_mdtype = CHAP_MDTYPE_D(cichar); + } else { + /* ... otherwise, try our next-preferred algorithm. */ + try_.chap_mdtype &= ~(CHAP_MDTYPE(try_.chap_mdtype)); + if (try_.chap_mdtype == MDTYPE_NONE) /* out of algos */ + try_.neg_chap = 0; + } + } else { + /* + * Whoops, they Nak'd our algorithm of choice + * but then suggested it back to us. + */ + goto bad; + } + } else { + /* + * Stop asking for PAP if we were asking for it. + */ +#if PAP_SUPPORT + try_.neg_upap = 0; +#endif /* PAP_SUPPORT */ + } + + } else +#endif /* CHAP_SUPPORT */ + { + +#if EAP_SUPPORT + /* + * If we were asking for EAP, and they're Conf-Naking EAP, + * well, that's just strange. Nobody should do that. + */ + if (cishort == PPP_EAP && cilen == CILEN_SHORT && go->neg_eap) + ppp_dbglog("Unexpected Conf-Nak for EAP"); + + /* + * We don't recognize what they're suggesting. + * Stop asking for what we were asking for. + */ + if (go->neg_eap) + try_.neg_eap = 0; + else +#endif /* EAP_SUPPORT */ + +#if CHAP_SUPPORT + if (go->neg_chap) + try_.neg_chap = 0; + else +#endif /* CHAP_SUPPORT */ + +#if PAP_SUPPORT + if(1) + try_.neg_upap = 0; + else +#endif /* PAP_SUPPORT */ + {} + + p += cilen - CILEN_SHORT; + } + } + +#if LQR_SUPPORT + /* + * If they can't cope with our link quality protocol, we'll have + * to stop asking for LQR. We haven't got any other protocol. + * If they Nak the reporting period, take their value XXX ? + */ + NAKCILQR(CI_QUALITY, neg_lqr, + if (cishort != PPP_LQR) + try_.neg_lqr = 0; + else + try_.lqr_period = cilong; + ); +#endif /* LQR_SUPPORT */ + + /* + * Only implementing CBCP...not the rest of the callback options + */ + NAKCICHAR(CI_CALLBACK, neg_cbcp, + try_.neg_cbcp = 0; + (void)cichar; /* if CHAP support is not compiled, cichar is set but not used, which makes some compilers complaining */ + ); + + /* + * Check for a looped-back line. + */ + NAKCILONG(CI_MAGICNUMBER, neg_magicnumber, + try_.magicnumber = magic(); + looped_back = 1; + ); + + /* + * Peer shouldn't send Nak for protocol compression or + * address/control compression requests; they should send + * a Reject instead. If they send a Nak, treat it as a Reject. + */ + NAKCIVOID(CI_PCOMPRESSION, neg_pcompression); + NAKCIVOID(CI_ACCOMPRESSION, neg_accompression); + +#ifdef HAVE_MULTILINK + /* + * Nak for MRRU option - accept their value if it is smaller + * than the one we want. + */ + if (go->neg_mrru) { + NAKCISHORT(CI_MRRU, neg_mrru, + if (treat_as_reject) + try_.neg_mrru = 0; + else if (cishort <= wo->mrru) + try_.mrru = cishort; + ); + } +#else /* HAVE_MULTILINK */ + LWIP_UNUSED_ARG(treat_as_reject); +#endif /* HAVE_MULTILINK */ + + /* + * Nak for short sequence numbers shouldn't be sent, treat it + * like a reject. + */ + NAKCIVOID(CI_SSNHF, neg_ssnhf); + + /* + * Nak of the endpoint discriminator option is not permitted, + * treat it like a reject. + */ + NAKCIENDP(CI_EPDISC, neg_endpoint); + + /* + * There may be remaining CIs, if the peer is requesting negotiation + * on an option that we didn't include in our request packet. + * If we see an option that we requested, or one we've already seen + * in this packet, then this packet is bad. + * If we wanted to respond by starting to negotiate on the requested + * option(s), we could, but we don't, because except for the + * authentication type and quality protocol, if we are not negotiating + * an option, it is because we were told not to. + * For the authentication type, the Nak from the peer means + * `let me authenticate myself with you' which is a bit pointless. + * For the quality protocol, the Nak means `ask me to send you quality + * reports', but if we didn't ask for them, we don't want them. + * An option we don't recognize represents the peer asking to + * negotiate some option we don't support, so ignore it. + */ + while (len >= CILEN_VOID) { + GETCHAR(citype, p); + GETCHAR(cilen, p); + if (cilen < CILEN_VOID || (len -= cilen) < 0) + goto bad; + next = p + cilen - 2; + + switch (citype) { + case CI_MRU: + if ((go->neg_mru && go->mru != PPP_DEFMRU) + || no.neg_mru || cilen != CILEN_SHORT) + goto bad; + GETSHORT(cishort, p); + if (cishort < PPP_DEFMRU) { + try_.neg_mru = 1; + try_.mru = cishort; + } + break; + case CI_ASYNCMAP: + if ((go->neg_asyncmap && go->asyncmap != 0xFFFFFFFF) + || no.neg_asyncmap || cilen != CILEN_LONG) + goto bad; + break; + case CI_AUTHTYPE: + if (0 +#if CHAP_SUPPORT + || go->neg_chap || no.neg_chap +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + || go->neg_upap || no.neg_upap +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + || go->neg_eap || no.neg_eap +#endif /* EAP_SUPPORT */ + ) + goto bad; + break; + case CI_MAGICNUMBER: + if (go->neg_magicnumber || no.neg_magicnumber || + cilen != CILEN_LONG) + goto bad; + break; + case CI_PCOMPRESSION: + if (go->neg_pcompression || no.neg_pcompression + || cilen != CILEN_VOID) + goto bad; + break; + case CI_ACCOMPRESSION: + if (go->neg_accompression || no.neg_accompression + || cilen != CILEN_VOID) + goto bad; + break; +#if LQR_SUPPORT + case CI_QUALITY: + if (go->neg_lqr || no.neg_lqr || cilen != CILEN_LQR) + goto bad; + break; +#endif /* LQR_SUPPORT */ +#ifdef HAVE_MULTILINK + case CI_MRRU: + if (go->neg_mrru || no.neg_mrru || cilen != CILEN_SHORT) + goto bad; + break; +#endif /* HAVE_MULTILINK */ + case CI_SSNHF: + if (go->neg_ssnhf || no.neg_ssnhf || cilen != CILEN_VOID) + goto bad; + try_.neg_ssnhf = 1; + break; + case CI_EPDISC: + if (go->neg_endpoint || no.neg_endpoint || cilen < CILEN_CHAR) + goto bad; + break; + default: + break; + } + p = next; + } + + /* + * OK, the Nak is good. Now we can update state. + * If there are any options left we ignore them. + */ + if (f->state != PPP_FSM_OPENED) { + if (looped_back) { + if (++try_.numloops >= pcb->settings.lcp_loopbackfail) { + ppp_notice("Serial line is looped back."); + pcb->err_code = PPPERR_LOOPBACK; + lcp_close(f->pcb, "Loopback detected"); + } + } else + try_.numloops = 0; + *go = try_; + } + + return 1; + +bad: + LCPDEBUG(("lcp_nakci: received bad Nak!")); + return 0; +} + + +/* + * lcp_rejci - Peer has Rejected some of our CIs. + * This should not modify any state if the Reject is bad + * or if LCP is in the OPENED state. + * + * Returns: + * 0 - Reject was bad. + * 1 - Reject was good. + */ +static int lcp_rejci(fsm *f, u_char *p, int len) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + u_char cichar; + u_short cishort; + u32_t cilong; + lcp_options try_; /* options to request next time */ + + try_ = *go; + + /* + * Any Rejected CIs must be in exactly the same order that we sent. + * Check packet length and CI length at each step. + * If we find any deviations, then this packet is bad. + */ +#define REJCIVOID(opt, neg) \ + if (go->neg && \ + len >= CILEN_VOID && \ + p[1] == CILEN_VOID && \ + p[0] == opt) { \ + len -= CILEN_VOID; \ + INCPTR(CILEN_VOID, p); \ + try_.neg = 0; \ + } +#define REJCISHORT(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_SHORT && \ + p[1] == CILEN_SHORT && \ + p[0] == opt) { \ + len -= CILEN_SHORT; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + /* Check rejected value. */ \ + if (cishort != val) \ + goto bad; \ + try_.neg = 0; \ + } + +#if CHAP_SUPPORT && EAP_SUPPORT && PAP_SUPPORT +#define REJCICHAP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \ + goto bad; \ + try_.neg = 0; \ + try_.neg_eap = try_.neg_upap = 0; \ + } +#endif /* CHAP_SUPPORT && EAP_SUPPORT && PAP_SUPPORT */ + +#if CHAP_SUPPORT && !EAP_SUPPORT && PAP_SUPPORT +#define REJCICHAP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \ + goto bad; \ + try_.neg = 0; \ + try_.neg_upap = 0; \ + } +#endif /* CHAP_SUPPORT && !EAP_SUPPORT && PAP_SUPPORT */ + +#if CHAP_SUPPORT && EAP_SUPPORT && !PAP_SUPPORT +#define REJCICHAP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \ + goto bad; \ + try_.neg = 0; \ + try_.neg_eap = 0; \ + } +#endif /* CHAP_SUPPORT && EAP_SUPPORT && !PAP_SUPPORT */ + +#if CHAP_SUPPORT && !EAP_SUPPORT && !PAP_SUPPORT +#define REJCICHAP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CHAP && \ + p[1] == CILEN_CHAP && \ + p[0] == opt) { \ + len -= CILEN_CHAP; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if ((cishort != PPP_CHAP) || (cichar != (CHAP_DIGEST(val)))) \ + goto bad; \ + try_.neg = 0; \ + } +#endif /* CHAP_SUPPORT && !EAP_SUPPORT && !PAP_SUPPORT */ + +#define REJCILONG(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LONG && \ + p[1] == CILEN_LONG && \ + p[0] == opt) { \ + len -= CILEN_LONG; \ + INCPTR(2, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cilong != val) \ + goto bad; \ + try_.neg = 0; \ + } +#if LQR_SUPPORT +#define REJCILQR(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_LQR && \ + p[1] == CILEN_LQR && \ + p[0] == opt) { \ + len -= CILEN_LQR; \ + INCPTR(2, p); \ + GETSHORT(cishort, p); \ + GETLONG(cilong, p); \ + /* Check rejected value. */ \ + if (cishort != PPP_LQR || cilong != val) \ + goto bad; \ + try_.neg = 0; \ + } +#endif /* LQR_SUPPORT */ +#define REJCICBCP(opt, neg, val) \ + if (go->neg && \ + len >= CILEN_CBCP && \ + p[1] == CILEN_CBCP && \ + p[0] == opt) { \ + len -= CILEN_CBCP; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + /* Check rejected value. */ \ + if (cichar != val) \ + goto bad; \ + try_.neg = 0; \ + } +#define REJCIENDP(opt, neg, class, val, vlen) \ + if (go->neg && \ + len >= CILEN_CHAR + vlen && \ + p[0] == opt && \ + p[1] == CILEN_CHAR + vlen) { \ + int i; \ + len -= CILEN_CHAR + vlen; \ + INCPTR(2, p); \ + GETCHAR(cichar, p); \ + if (cichar != class) \ + goto bad; \ + for (i = 0; i < vlen; ++i) { \ + GETCHAR(cichar, p); \ + if (cichar != val[i]) \ + goto bad; \ + } \ + try_.neg = 0; \ + } + + REJCISHORT(CI_MRU, neg_mru, go->mru); + REJCILONG(CI_ASYNCMAP, neg_asyncmap, go->asyncmap); +#if EAP_SUPPORT + REJCISHORT(CI_AUTHTYPE, neg_eap, PPP_EAP); + if (!go->neg_eap) { +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT + REJCICHAP(CI_AUTHTYPE, neg_chap, go->chap_mdtype); + if (!go->neg_chap) { +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + REJCISHORT(CI_AUTHTYPE, neg_upap, PPP_PAP); +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + } +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + } +#endif /* EAP_SUPPORT */ +#if LQR_SUPPORT + REJCILQR(CI_QUALITY, neg_lqr, go->lqr_period); +#endif /* LQR_SUPPORT */ + REJCICBCP(CI_CALLBACK, neg_cbcp, CBCP_OPT); + REJCILONG(CI_MAGICNUMBER, neg_magicnumber, go->magicnumber); + REJCIVOID(CI_PCOMPRESSION, neg_pcompression); + REJCIVOID(CI_ACCOMPRESSION, neg_accompression); +#ifdef HAVE_MULTILINK + REJCISHORT(CI_MRRU, neg_mrru, go->mrru); +#endif /* HAVE_MULTILINK */ + REJCIVOID(CI_SSNHF, neg_ssnhf); + REJCIENDP(CI_EPDISC, neg_endpoint, go->endpoint.class_, + go->endpoint.value, go->endpoint.length); + + /* + * If there are any remaining CIs, then this packet is bad. + */ + if (len != 0) + goto bad; + /* + * Now we can update state. + */ + if (f->state != PPP_FSM_OPENED) + *go = try_; + return 1; + +bad: + LCPDEBUG(("lcp_rejci: received bad Reject!")); + return 0; +} + + +/* + * lcp_reqci - Check the peer's requested CIs and send appropriate response. + * + * Returns: CONFACK, CONFNAK or CONFREJ and input packet modified + * appropriately. If reject_if_disagree is non-zero, doesn't return + * CONFNAK; returns CONFREJ if it can't return CONFACK. + * + * inp = Requested CIs + * lenp = Length of requested CIs + */ +static int lcp_reqci(fsm *f, u_char *inp, int *lenp, int reject_if_disagree) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + lcp_options *ho = &pcb->lcp_hisoptions; + lcp_options *ao = &pcb->lcp_allowoptions; + u_char *cip, *next; /* Pointer to current and next CIs */ + int cilen, citype, cichar; /* Parsed len, type, char value */ + u_short cishort; /* Parsed short value */ + u32_t cilong; /* Parse long value */ + int rc = CONFACK; /* Final packet return code */ + int orc; /* Individual option return code */ + u_char *p; /* Pointer to next char to parse */ + u_char *rejp; /* Pointer to next char in reject frame */ + struct pbuf *nakp; /* Nak buffer */ + u_char *nakoutp; /* Pointer to next char in Nak frame */ + int l = *lenp; /* Length left */ + + /* + * Reset all his options. + */ + BZERO(ho, sizeof(*ho)); + + /* + * Process all his options. + */ + next = inp; + nakp = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_CTRL_PBUF_MAX_SIZE), PPP_CTRL_PBUF_TYPE); + if(NULL == nakp) + return 0; + if(nakp->tot_len != nakp->len) { + pbuf_free(nakp); + return 0; + } + + nakoutp = (u_char*)nakp->payload; + rejp = inp; + while (l) { + orc = CONFACK; /* Assume success */ + cip = p = next; /* Remember begining of CI */ + if (l < 2 || /* Not enough data for CI header or */ + p[1] < 2 || /* CI length too small or */ + p[1] > l) { /* CI length too big? */ + LCPDEBUG(("lcp_reqci: bad CI length!")); + orc = CONFREJ; /* Reject bad CI */ + cilen = l; /* Reject till end of packet */ + l = 0; /* Don't loop again */ + citype = 0; + goto endswitch; + } + GETCHAR(citype, p); /* Parse CI type */ + GETCHAR(cilen, p); /* Parse CI length */ + l -= cilen; /* Adjust remaining length */ + next += cilen; /* Step to next CI */ + + switch (citype) { /* Check CI type */ + case CI_MRU: + if (!ao->neg_mru || /* Allow option? */ + cilen != CILEN_SHORT) { /* Check CI length */ + orc = CONFREJ; /* Reject CI */ + break; + } + GETSHORT(cishort, p); /* Parse MRU */ + + /* + * He must be able to receive at least our minimum. + * No need to check a maximum. If he sends a large number, + * we'll just ignore it. + */ + if (cishort < PPP_MINMRU) { + orc = CONFNAK; /* Nak CI */ + PUTCHAR(CI_MRU, nakoutp); + PUTCHAR(CILEN_SHORT, nakoutp); + PUTSHORT(PPP_MINMRU, nakoutp); /* Give him a hint */ + break; + } + ho->neg_mru = 1; /* Remember he sent MRU */ + ho->mru = cishort; /* And remember value */ + break; + + case CI_ASYNCMAP: + if (!ao->neg_asyncmap || + cilen != CILEN_LONG) { + orc = CONFREJ; + break; + } + GETLONG(cilong, p); + + /* + * Asyncmap must have set at least the bits + * which are set in lcp_allowoptions[unit].asyncmap. + */ + if ((ao->asyncmap & ~cilong) != 0) { + orc = CONFNAK; + PUTCHAR(CI_ASYNCMAP, nakoutp); + PUTCHAR(CILEN_LONG, nakoutp); + PUTLONG(ao->asyncmap | cilong, nakoutp); + break; + } + ho->neg_asyncmap = 1; + ho->asyncmap = cilong; + break; + + case CI_AUTHTYPE: + if (cilen < CILEN_SHORT || + !(0 +#if PAP_SUPPORT + || ao->neg_upap +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + || ao->neg_chap +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + || ao->neg_eap +#endif /* EAP_SUPPORT */ + )) { + /* + * Reject the option if we're not willing to authenticate. + */ + ppp_dbglog("No auth is possible"); + orc = CONFREJ; + break; + } + GETSHORT(cishort, p); + + /* + * Authtype must be PAP, CHAP, or EAP. + * + * Note: if more than one of ao->neg_upap, ao->neg_chap, and + * ao->neg_eap are set, and the peer sends a Configure-Request + * with two or more authenticate-protocol requests, then we will + * reject the second request. + * Whether we end up doing CHAP, UPAP, or EAP depends then on + * the ordering of the CIs in the peer's Configure-Request. + */ + +#if PAP_SUPPORT + if (cishort == PPP_PAP) { + /* we've already accepted CHAP or EAP */ + if (0 +#if CHAP_SUPPORT + || ho->neg_chap +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + || ho->neg_eap +#endif /* EAP_SUPPORT */ + || cilen != CILEN_SHORT) { + LCPDEBUG(("lcp_reqci: rcvd AUTHTYPE PAP, rejecting...")); + orc = CONFREJ; + break; + } + if (!ao->neg_upap) { /* we don't want to do PAP */ + orc = CONFNAK; /* NAK it and suggest CHAP or EAP */ + PUTCHAR(CI_AUTHTYPE, nakoutp); +#if EAP_SUPPORT + if (ao->neg_eap) { + PUTCHAR(CILEN_SHORT, nakoutp); + PUTSHORT(PPP_EAP, nakoutp); + } else { +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT + PUTCHAR(CILEN_CHAP, nakoutp); + PUTSHORT(PPP_CHAP, nakoutp); + PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp); +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + } +#endif /* EAP_SUPPORT */ + break; + } + ho->neg_upap = 1; + break; + } +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + if (cishort == PPP_CHAP) { + /* we've already accepted PAP or EAP */ + if ( +#if PAP_SUPPORT + ho->neg_upap || +#endif /* PAP_SUPPORT */ +#if EAP_SUPPORT + ho->neg_eap || +#endif /* EAP_SUPPORT */ + cilen != CILEN_CHAP) { + LCPDEBUG(("lcp_reqci: rcvd AUTHTYPE CHAP, rejecting...")); + orc = CONFREJ; + break; + } + if (!ao->neg_chap) { /* we don't want to do CHAP */ + orc = CONFNAK; /* NAK it and suggest EAP or PAP */ + PUTCHAR(CI_AUTHTYPE, nakoutp); + PUTCHAR(CILEN_SHORT, nakoutp); +#if EAP_SUPPORT + if (ao->neg_eap) { + PUTSHORT(PPP_EAP, nakoutp); + } else +#endif /* EAP_SUPPORT */ +#if PAP_SUPPORT + if(1) { + PUTSHORT(PPP_PAP, nakoutp); + } + else +#endif /* PAP_SUPPORT */ + {} + break; + } + GETCHAR(cichar, p); /* get digest type */ + if (!(CHAP_CANDIGEST(ao->chap_mdtype, cichar))) { + /* + * We can't/won't do the requested type, + * suggest something else. + */ + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakoutp); + PUTCHAR(CILEN_CHAP, nakoutp); + PUTSHORT(PPP_CHAP, nakoutp); + PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp); + break; + } + ho->chap_mdtype = CHAP_MDTYPE_D(cichar); /* save md type */ + ho->neg_chap = 1; + break; + } +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + if (cishort == PPP_EAP) { + /* we've already accepted CHAP or PAP */ + if ( +#if CHAP_SUPPORT + ho->neg_chap || +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + ho->neg_upap || +#endif /* PAP_SUPPORT */ + cilen != CILEN_SHORT) { + LCPDEBUG(("lcp_reqci: rcvd AUTHTYPE EAP, rejecting...")); + orc = CONFREJ; + break; + } + if (!ao->neg_eap) { /* we don't want to do EAP */ + orc = CONFNAK; /* NAK it and suggest CHAP or PAP */ + PUTCHAR(CI_AUTHTYPE, nakoutp); +#if CHAP_SUPPORT + if (ao->neg_chap) { + PUTCHAR(CILEN_CHAP, nakoutp); + PUTSHORT(PPP_CHAP, nakoutp); + PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp); + } else +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + if(1) { + PUTCHAR(CILEN_SHORT, nakoutp); + PUTSHORT(PPP_PAP, nakoutp); + } else +#endif /* PAP_SUPPORT */ + {} + break; + } + ho->neg_eap = 1; + break; + } +#endif /* EAP_SUPPORT */ + + /* + * We don't recognize the protocol they're asking for. + * Nak it with something we're willing to do. + * (At this point we know ao->neg_upap || ao->neg_chap || + * ao->neg_eap.) + */ + orc = CONFNAK; + PUTCHAR(CI_AUTHTYPE, nakoutp); + +#if EAP_SUPPORT + if (ao->neg_eap) { + PUTCHAR(CILEN_SHORT, nakoutp); + PUTSHORT(PPP_EAP, nakoutp); + } else +#endif /* EAP_SUPPORT */ +#if CHAP_SUPPORT + if (ao->neg_chap) { + PUTCHAR(CILEN_CHAP, nakoutp); + PUTSHORT(PPP_CHAP, nakoutp); + PUTCHAR(CHAP_DIGEST(ao->chap_mdtype), nakoutp); + } else +#endif /* CHAP_SUPPORT */ +#if PAP_SUPPORT + if(1) { + PUTCHAR(CILEN_SHORT, nakoutp); + PUTSHORT(PPP_PAP, nakoutp); + } else +#endif /* PAP_SUPPORT */ + {} + break; + +#if LQR_SUPPORT + case CI_QUALITY: + if (!ao->neg_lqr || + cilen != CILEN_LQR) { + orc = CONFREJ; + break; + } + + GETSHORT(cishort, p); + GETLONG(cilong, p); + + /* + * Check the protocol and the reporting period. + * XXX When should we Nak this, and what with? + */ + if (cishort != PPP_LQR) { + orc = CONFNAK; + PUTCHAR(CI_QUALITY, nakoutp); + PUTCHAR(CILEN_LQR, nakoutp); + PUTSHORT(PPP_LQR, nakoutp); + PUTLONG(ao->lqr_period, nakoutp); + break; + } + break; +#endif /* LQR_SUPPORT */ + + case CI_MAGICNUMBER: + if (!(ao->neg_magicnumber || go->neg_magicnumber) || + cilen != CILEN_LONG) { + orc = CONFREJ; + break; + } + GETLONG(cilong, p); + + /* + * He must have a different magic number. + */ + if (go->neg_magicnumber && + cilong == go->magicnumber) { + cilong = magic(); /* Don't put magic() inside macro! */ + orc = CONFNAK; + PUTCHAR(CI_MAGICNUMBER, nakoutp); + PUTCHAR(CILEN_LONG, nakoutp); + PUTLONG(cilong, nakoutp); + break; + } + ho->neg_magicnumber = 1; + ho->magicnumber = cilong; + break; + + + case CI_PCOMPRESSION: + if (!ao->neg_pcompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_pcompression = 1; + break; + + case CI_ACCOMPRESSION: + if (!ao->neg_accompression || + cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_accompression = 1; + break; + +#ifdef HAVE_MULTILINK + case CI_MRRU: + if (!ao->neg_mrru + || !multilink + || cilen != CILEN_SHORT) { + orc = CONFREJ; + break; + } + + GETSHORT(cishort, p); + /* possibly should insist on a minimum/maximum MRRU here */ + ho->neg_mrru = 1; + ho->mrru = cishort; + break; +#endif /* HAVE_MULTILINK */ + + case CI_SSNHF: + if (!ao->neg_ssnhf +#ifdef HAVE_MULTILINK + || !multilink +#endif /* HAVE_MULTILINK */ + || cilen != CILEN_VOID) { + orc = CONFREJ; + break; + } + ho->neg_ssnhf = 1; + break; + + case CI_EPDISC: + if (!ao->neg_endpoint || + cilen < CILEN_CHAR || + cilen > CILEN_CHAR + MAX_ENDP_LEN) { + orc = CONFREJ; + break; + } + GETCHAR(cichar, p); + cilen -= CILEN_CHAR; + ho->neg_endpoint = 1; + ho->endpoint.class_ = cichar; + ho->endpoint.length = cilen; + MEMCPY(ho->endpoint.value, p, cilen); + INCPTR(cilen, p); + break; + + default: + LCPDEBUG(("lcp_reqci: rcvd unknown option %d", citype)); + orc = CONFREJ; + break; + } + +endswitch: + if (orc == CONFACK && /* Good CI */ + rc != CONFACK) /* but prior CI wasnt? */ + continue; /* Don't send this one */ + + if (orc == CONFNAK) { /* Nak this CI? */ + if (reject_if_disagree /* Getting fed up with sending NAKs? */ + && citype != CI_MAGICNUMBER) { + orc = CONFREJ; /* Get tough if so */ + } else { + if (rc == CONFREJ) /* Rejecting prior CI? */ + continue; /* Don't send this one */ + rc = CONFNAK; + } + } + if (orc == CONFREJ) { /* Reject this CI */ + rc = CONFREJ; + if (cip != rejp) /* Need to move rejected CI? */ + MEMCPY(rejp, cip, cilen); /* Move it */ + INCPTR(cilen, rejp); /* Update output pointer */ + } + } + + /* + * If we wanted to send additional NAKs (for unsent CIs), the + * code would go here. The extra NAKs would go at *nakoutp. + * At present there are no cases where we want to ask the + * peer to negotiate an option. + */ + + switch (rc) { + case CONFACK: + *lenp = next - inp; + break; + case CONFNAK: + /* + * Copy the Nak'd options from the nak buffer to the caller's buffer. + */ + *lenp = nakoutp - (u_char*)nakp->payload; + MEMCPY(inp, nakp->payload, *lenp); + break; + case CONFREJ: + *lenp = rejp - inp; + break; + default: + break; + } + + pbuf_free(nakp); + LCPDEBUG(("lcp_reqci: returning CONF%s.", CODENAME(rc))); + return (rc); /* Return final code */ +} + + +/* + * lcp_up - LCP has come UP. + */ +static void lcp_up(fsm *f) { + ppp_pcb *pcb = f->pcb; + lcp_options *wo = &pcb->lcp_wantoptions; + lcp_options *ho = &pcb->lcp_hisoptions; + lcp_options *go = &pcb->lcp_gotoptions; + lcp_options *ao = &pcb->lcp_allowoptions; + int mtu, mru; + + if (!go->neg_magicnumber) + go->magicnumber = 0; + if (!ho->neg_magicnumber) + ho->magicnumber = 0; + + /* + * Set our MTU to the smaller of the MTU we wanted and + * the MRU our peer wanted. If we negotiated an MRU, + * set our MRU to the larger of value we wanted and + * the value we got in the negotiation. + * Note on the MTU: the link MTU can be the MRU the peer wanted, + * the interface MTU is set to the lowest of that, the + * MTU we want to use, and our link MRU. + */ + mtu = ho->neg_mru? ho->mru: PPP_MRU; + mru = go->neg_mru? LWIP_MAX(wo->mru, go->mru): PPP_MRU; +#ifdef HAVE_MULTILINK + if (!(multilink && go->neg_mrru && ho->neg_mrru)) +#endif /* HAVE_MULTILINK */ + netif_set_mtu(pcb, LWIP_MIN(LWIP_MIN(mtu, mru), ao->mru)); + ppp_send_config(pcb, mtu, + (ho->neg_asyncmap? ho->asyncmap: 0xffffffff), + ho->neg_pcompression, ho->neg_accompression); + ppp_recv_config(pcb, mru, + (pcb->settings.lax_recv? 0: go->neg_asyncmap? go->asyncmap: 0xffffffff), + go->neg_pcompression, go->neg_accompression); + + if (ho->neg_mru) + pcb->peer_mru = ho->mru; + + lcp_echo_lowerup(f->pcb); /* Enable echo messages */ + + link_established(pcb); +} + + +/* + * lcp_down - LCP has gone DOWN. + * + * Alert other protocols. + */ +static void lcp_down(fsm *f) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + + lcp_echo_lowerdown(f->pcb); + + link_down(pcb); + + ppp_send_config(pcb, PPP_MRU, 0xffffffff, 0, 0); + ppp_recv_config(pcb, PPP_MRU, + (go->neg_asyncmap? go->asyncmap: 0xffffffff), + go->neg_pcompression, go->neg_accompression); + pcb->peer_mru = PPP_MRU; +} + + +/* + * lcp_starting - LCP needs the lower layer up. + */ +static void lcp_starting(fsm *f) { + ppp_pcb *pcb = f->pcb; + link_required(pcb); +} + + +/* + * lcp_finished - LCP has finished with the lower layer. + */ +static void lcp_finished(fsm *f) { + ppp_pcb *pcb = f->pcb; + link_terminated(pcb); +} + + +#if PRINTPKT_SUPPORT +/* + * lcp_printpkt - print the contents of an LCP packet. + */ +static const char* const lcp_codenames[] = { + "ConfReq", "ConfAck", "ConfNak", "ConfRej", + "TermReq", "TermAck", "CodeRej", "ProtRej", + "EchoReq", "EchoRep", "DiscReq", "Ident", + "TimeRem" +}; + +static int lcp_printpkt(const u_char *p, int plen, + void (*printer) (void *, const char *, ...), void *arg) { + int code, id, len, olen, i; + const u_char *pstart, *optend; + u_short cishort; + u32_t cilong; + + if (plen < HEADERLEN) + return 0; + pstart = p; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(lcp_codenames)) + printer(arg, " %s", lcp_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= HEADERLEN; + switch (code) { + case CONFREQ: + case CONFACK: + case CONFNAK: + case CONFREJ: + /* print option list */ + while (len >= 2) { + GETCHAR(code, p); + GETCHAR(olen, p); + p -= 2; + if (olen < 2 || olen > len) { + break; + } + printer(arg, " <"); + len -= olen; + optend = p + olen; + switch (code) { + case CI_MRU: + if (olen == CILEN_SHORT) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "mru %d", cishort); + } + break; + case CI_ASYNCMAP: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "asyncmap 0x%x", cilong); + } + break; + case CI_AUTHTYPE: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "auth "); + GETSHORT(cishort, p); + switch (cishort) { +#if PAP_SUPPORT + case PPP_PAP: + printer(arg, "pap"); + break; +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + case PPP_CHAP: + printer(arg, "chap"); + if (p < optend) { + switch (*p) { + case CHAP_MD5: + printer(arg, " MD5"); + ++p; + break; +#if MSCHAP_SUPPORT + case CHAP_MICROSOFT: + printer(arg, " MS"); + ++p; + break; + + case CHAP_MICROSOFT_V2: + printer(arg, " MS-v2"); + ++p; + break; +#endif /* MSCHAP_SUPPORT */ + default: + break; + } + } + break; +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + case PPP_EAP: + printer(arg, "eap"); + break; +#endif /* EAP_SUPPORT */ + default: + printer(arg, "0x%x", cishort); + } + } + break; +#if LQR_SUPPORT + case CI_QUALITY: + if (olen >= CILEN_SHORT) { + p += 2; + printer(arg, "quality "); + GETSHORT(cishort, p); + switch (cishort) { + case PPP_LQR: + printer(arg, "lqr"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; +#endif /* LQR_SUPPORT */ + case CI_CALLBACK: + if (olen >= CILEN_CHAR) { + p += 2; + printer(arg, "callback "); + GETCHAR(cishort, p); + switch (cishort) { + case CBCP_OPT: + printer(arg, "CBCP"); + break; + default: + printer(arg, "0x%x", cishort); + } + } + break; + case CI_MAGICNUMBER: + if (olen == CILEN_LONG) { + p += 2; + GETLONG(cilong, p); + printer(arg, "magic 0x%x", cilong); + } + break; + case CI_PCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "pcomp"); + } + break; + case CI_ACCOMPRESSION: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "accomp"); + } + break; + case CI_MRRU: + if (olen == CILEN_SHORT) { + p += 2; + GETSHORT(cishort, p); + printer(arg, "mrru %d", cishort); + } + break; + case CI_SSNHF: + if (olen == CILEN_VOID) { + p += 2; + printer(arg, "ssnhf"); + } + break; + case CI_EPDISC: +#ifdef HAVE_MULTILINK + if (olen >= CILEN_CHAR) { + struct epdisc epd; + p += 2; + GETCHAR(epd.class, p); + epd.length = olen - CILEN_CHAR; + if (epd.length > MAX_ENDP_LEN) + epd.length = MAX_ENDP_LEN; + if (epd.length > 0) { + MEMCPY(epd.value, p, epd.length); + p += epd.length; + } + printer(arg, "endpoint [%s]", epdisc_to_str(&epd)); + } +#else + printer(arg, "endpoint"); +#endif + break; + default: + break; + } + while (p < optend) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + printer(arg, ">"); + } + break; + + case TERMACK: + case TERMREQ: + if (len > 0 && *p >= ' ' && *p < 0x7f) { + printer(arg, " "); + ppp_print_string(p, len, printer, arg); + p += len; + len = 0; + } + break; + + case ECHOREQ: + case ECHOREP: + case DISCREQ: + if (len >= 4) { + GETLONG(cilong, p); + printer(arg, " magic=0x%x", cilong); + len -= 4; + } + break; + + case IDENTIF: + case TIMEREM: + if (len >= 4) { + GETLONG(cilong, p); + printer(arg, " magic=0x%x", cilong); + len -= 4; + } + if (code == TIMEREM) { + if (len < 4) + break; + GETLONG(cilong, p); + printer(arg, " seconds=%u", cilong); + len -= 4; + } + if (len > 0) { + printer(arg, " "); + ppp_print_string(p, len, printer, arg); + p += len; + len = 0; + } + break; + default: + break; + } + + /* print the rest of the bytes in the packet */ + for (i = 0; i < len && i < 32; ++i) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + if (i < len) { + printer(arg, " ..."); + p += len - i; + } + + return p - pstart; +} +#endif /* PRINTPKT_SUPPORT */ + +/* + * Time to shut down the link because there is nothing out there. + */ + +static void LcpLinkFailure(fsm *f) { + ppp_pcb *pcb = f->pcb; + if (f->state == PPP_FSM_OPENED) { + ppp_info("No response to %d echo-requests", pcb->lcp_echos_pending); + ppp_notice("Serial link appears to be disconnected."); + pcb->err_code = PPPERR_PEERDEAD; + lcp_close(pcb, "Peer not responding"); + } +} + +/* + * Timer expired for the LCP echo requests from this process. + */ + +static void LcpEchoCheck(fsm *f) { + ppp_pcb *pcb = f->pcb; + + LcpSendEchoRequest (f); + if (f->state != PPP_FSM_OPENED) + return; + + /* + * Start the timer for the next interval. + */ + if (pcb->lcp_echo_timer_running) + ppp_warn("assertion lcp_echo_timer_running==0 failed"); + TIMEOUT (LcpEchoTimeout, f, pcb->settings.lcp_echo_interval); + pcb->lcp_echo_timer_running = 1; +} + +/* + * LcpEchoTimeout - Timer expired on the LCP echo + */ + +static void LcpEchoTimeout(void *arg) { + fsm *f = (fsm*)arg; + ppp_pcb *pcb = f->pcb; + if (pcb->lcp_echo_timer_running != 0) { + pcb->lcp_echo_timer_running = 0; + LcpEchoCheck ((fsm *) arg); + } +} + +/* + * LcpEchoReply - LCP has received a reply to the echo + */ + +static void lcp_received_echo_reply(fsm *f, int id, u_char *inp, int len) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + u32_t magic_val; + LWIP_UNUSED_ARG(id); + + /* Check the magic number - don't count replies from ourselves. */ + if (len < 4) { + ppp_dbglog("lcp: received short Echo-Reply, length %d", len); + return; + } + GETLONG(magic_val, inp); + if (go->neg_magicnumber + && magic_val == go->magicnumber) { + ppp_warn("appear to have received our own echo-reply!"); + return; + } + + /* Reset the number of outstanding echo frames */ + pcb->lcp_echos_pending = 0; +} + +/* + * LcpSendEchoRequest - Send an echo request frame to the peer + */ + +static void LcpSendEchoRequest(fsm *f) { + ppp_pcb *pcb = f->pcb; + lcp_options *go = &pcb->lcp_gotoptions; + u32_t lcp_magic; + u_char pkt[4], *pktp; + + /* + * Detect the failure of the peer at this point. + */ + if (pcb->settings.lcp_echo_fails != 0) { + if (pcb->lcp_echos_pending >= pcb->settings.lcp_echo_fails) { + LcpLinkFailure(f); + pcb->lcp_echos_pending = 0; + } + } + +#if PPP_LCP_ADAPTIVE + /* + * If adaptive echos have been enabled, only send the echo request if + * no traffic was received since the last one. + */ + if (pcb->settings.lcp_echo_adaptive) { + static unsigned int last_pkts_in = 0; + +#if PPP_STATS_SUPPORT + update_link_stats(f->unit); + link_stats_valid = 0; +#endif /* PPP_STATS_SUPPORT */ + + if (link_stats.pkts_in != last_pkts_in) { + last_pkts_in = link_stats.pkts_in; + return; + } + } +#endif + + /* + * Make and send the echo request frame. + */ + if (f->state == PPP_FSM_OPENED) { + lcp_magic = go->magicnumber; + pktp = pkt; + PUTLONG(lcp_magic, pktp); + fsm_sdata(f, ECHOREQ, pcb->lcp_echo_number++, pkt, pktp - pkt); + ++pcb->lcp_echos_pending; + } +} + +/* + * lcp_echo_lowerup - Start the timer for the LCP frame + */ + +static void lcp_echo_lowerup(ppp_pcb *pcb) { + fsm *f = &pcb->lcp_fsm; + + /* Clear the parameters for generating echo frames */ + pcb->lcp_echos_pending = 0; + pcb->lcp_echo_number = 0; + pcb->lcp_echo_timer_running = 0; + + /* If a timeout interval is specified then start the timer */ + if (pcb->settings.lcp_echo_interval != 0) + LcpEchoCheck (f); +} + +/* + * lcp_echo_lowerdown - Stop the timer for the LCP frame + */ + +static void lcp_echo_lowerdown(ppp_pcb *pcb) { + fsm *f = &pcb->lcp_fsm; + + if (pcb->lcp_echo_timer_running != 0) { + UNTIMEOUT (LcpEchoTimeout, f); + pcb->lcp_echo_timer_running = 0; + } +} + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c new file mode 100644 index 0000000..d0d87c5 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/magic.c @@ -0,0 +1,294 @@ +/* + * magic.c - PPP Magic Number routines. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +/***************************************************************************** +* randm.c - Random number generator program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* Copyright (c) 1998 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 98-06-03 Guy Lancaster , Global Election Systems Inc. +* Extracted from avos. +*****************************************************************************/ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/magic.h" + +#if PPP_MD5_RANDM /* Using MD5 for better randomness if enabled */ + +#include "netif/ppp/pppcrypt.h" + +#define MD5_HASH_SIZE 16 +static char magic_randpool[MD5_HASH_SIZE]; /* Pool of randomness. */ +static long magic_randcount; /* Pseudo-random incrementer */ +static u32_t magic_randomseed; /* Seed used for random number generation. */ + +/* + * Churn the randomness pool on a random event. Call this early and often + * on random and semi-random system events to build randomness in time for + * usage. For randomly timed events, pass a null pointer and a zero length + * and this will use the system timer and other sources to add randomness. + * If new random data is available, pass a pointer to that and it will be + * included. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + */ +static void magic_churnrand(char *rand_data, u32_t rand_len) { + lwip_md5_context md5_ctx; + + /* LWIP_DEBUGF(LOG_INFO, ("magic_churnrand: %u@%P\n", rand_len, rand_data)); */ + lwip_md5_init(&md5_ctx); + lwip_md5_starts(&md5_ctx); + lwip_md5_update(&md5_ctx, (u_char *)magic_randpool, sizeof(magic_randpool)); + if (rand_data) { + lwip_md5_update(&md5_ctx, (u_char *)rand_data, rand_len); + } else { + struct { + /* INCLUDE fields for any system sources of randomness */ + u32_t jiffies; +#ifdef LWIP_RAND + u32_t rand; +#endif /* LWIP_RAND */ + } sys_data; + magic_randomseed += sys_jiffies(); + sys_data.jiffies = magic_randomseed; +#ifdef LWIP_RAND + sys_data.rand = LWIP_RAND(); +#endif /* LWIP_RAND */ + /* Load sys_data fields here. */ + lwip_md5_update(&md5_ctx, (u_char *)&sys_data, sizeof(sys_data)); + } + lwip_md5_finish(&md5_ctx, (u_char *)magic_randpool); + lwip_md5_free(&md5_ctx); +/* LWIP_DEBUGF(LOG_INFO, ("magic_churnrand: -> 0\n")); */ +} + +/* + * Initialize the random number generator. + */ +void magic_init(void) { + magic_churnrand(NULL, 0); +} + +/* + * Randomize our random seed value. + */ +void magic_randomize(void) { + magic_churnrand(NULL, 0); +} + +/* + * magic_random_bytes - Fill a buffer with random bytes. + * + * Use the random pool to generate random data. This degrades to pseudo + * random when used faster than randomness is supplied using magic_churnrand(). + * Note: It's important that there be sufficient randomness in magic_randpool + * before this is called for otherwise the range of the result may be + * narrow enough to make a search feasible. + * + * Ref: Applied Cryptography 2nd Ed. by Bruce Schneier p. 427 + * + * XXX Why does he not just call magic_churnrand() for each block? Probably + * so that you don't ever publish the seed which could possibly help + * predict future values. + * XXX Why don't we preserve md5 between blocks and just update it with + * magic_randcount each time? Probably there is a weakness but I wish that + * it was documented. + */ +void magic_random_bytes(unsigned char *buf, u32_t buf_len) { + lwip_md5_context md5_ctx; + u_char tmp[MD5_HASH_SIZE]; + u32_t n; + + while (buf_len > 0) { + lwip_md5_init(&md5_ctx); + lwip_md5_starts(&md5_ctx); + lwip_md5_update(&md5_ctx, (u_char *)magic_randpool, sizeof(magic_randpool)); + lwip_md5_update(&md5_ctx, (u_char *)&magic_randcount, sizeof(magic_randcount)); + lwip_md5_finish(&md5_ctx, tmp); + lwip_md5_free(&md5_ctx); + magic_randcount++; + n = LWIP_MIN(buf_len, MD5_HASH_SIZE); + MEMCPY(buf, tmp, n); + buf += n; + buf_len -= n; + } +} + +/* + * Return a new random number. + */ +u32_t magic(void) { + u32_t new_rand; + + magic_random_bytes((unsigned char *)&new_rand, sizeof(new_rand)); + + return new_rand; +} + +#else /* PPP_MD5_RANDM */ + +/*****************************/ +/*** LOCAL DATA STRUCTURES ***/ +/*****************************/ +#ifndef LWIP_RAND +static int magic_randomized; /* Set when truely randomized. */ +#endif /* LWIP_RAND */ +static u32_t magic_randomseed; /* Seed used for random number generation. */ + + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ + +/* + * Initialize the random number generator. + * + * Here we attempt to compute a random number seed but even if + * it isn't random, we'll randomize it later. + * + * The current method uses the fields from the real time clock, + * the idle process counter, the millisecond counter, and the + * hardware timer tick counter. When this is invoked + * in startup(), then the idle counter and timer values may + * repeat after each boot and the real time clock may not be + * operational. Thus we call it again on the first random + * event. + */ +void magic_init(void) { + magic_randomseed += sys_jiffies(); +#ifndef LWIP_RAND + /* Initialize the Borland random number generator. */ + srand((unsigned)magic_randomseed); +#endif /* LWIP_RAND */ +} + +/* + * magic_init - Initialize the magic number generator. + * + * Randomize our random seed value. Here we use the fact that + * this function is called at *truely random* times by the polling + * and network functions. Here we only get 16 bits of new random + * value but we use the previous value to randomize the other 16 + * bits. + */ +void magic_randomize(void) { +#ifndef LWIP_RAND + if (!magic_randomized) { + magic_randomized = !0; + magic_init(); + /* The initialization function also updates the seed. */ + } else { +#endif /* LWIP_RAND */ + magic_randomseed += sys_jiffies(); +#ifndef LWIP_RAND + } +#endif /* LWIP_RAND */ +} + +/* + * Return a new random number. + * + * Here we use the Borland rand() function to supply a pseudo random + * number which we make truely random by combining it with our own + * seed which is randomized by truely random events. + * Thus the numbers will be truely random unless there have been no + * operator or network events in which case it will be pseudo random + * seeded by the real time clock. + */ +u32_t magic(void) { +#ifdef LWIP_RAND + return LWIP_RAND() + magic_randomseed; +#else /* LWIP_RAND */ + return ((u32_t)rand() << 16) + (u32_t)rand() + magic_randomseed; +#endif /* LWIP_RAND */ +} + +/* + * magic_random_bytes - Fill a buffer with random bytes. + */ +void magic_random_bytes(unsigned char *buf, u32_t buf_len) { + u32_t new_rand, n; + + while (buf_len > 0) { + new_rand = magic(); + n = LWIP_MIN(buf_len, sizeof(new_rand)); + MEMCPY(buf, &new_rand, n); + buf += n; + buf_len -= n; + } +} +#endif /* PPP_MD5_RANDM */ + +/* + * Return a new random number between 0 and (2^pow)-1 included. + */ +u32_t magic_pow(u8_t pow) { + return magic() & ~(~0UL<. + * Copyright (c) 2002,2003,2004 Google, Inc. + * All rights reserved. + * + * License: + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. + * + * Changelog: + * 08/12/05 - Matt Domsch + * Only need extra skb padding on transmit, not receive. + * 06/18/04 - Matt Domsch , Oleg Makarenko + * Use Linux kernel 2.6 arc4 and sha1 routines rather than + * providing our own. + * 2/15/04 - TS: added #include and testing for Kernel + * version before using + * MOD_DEC_USAGE_COUNT/MOD_INC_USAGE_COUNT which are + * deprecated in 2.6 + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && MPPE_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include + +#include "lwip/err.h" + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/ccp.h" +#include "netif/ppp/mppe.h" +#include "netif/ppp/pppdebug.h" +#include "netif/ppp/pppcrypt.h" + +#define SHA1_SIGNATURE_SIZE 20 + +/* ppp_mppe_state.bits definitions */ +#define MPPE_BIT_A 0x80 /* Encryption table were (re)inititalized */ +#define MPPE_BIT_B 0x40 /* MPPC only (not implemented) */ +#define MPPE_BIT_C 0x20 /* MPPC only (not implemented) */ +#define MPPE_BIT_D 0x10 /* This is an encrypted frame */ + +#define MPPE_BIT_FLUSHED MPPE_BIT_A +#define MPPE_BIT_ENCRYPTED MPPE_BIT_D + +#define MPPE_BITS(p) ((p)[0] & 0xf0) +#define MPPE_CCOUNT(p) ((((p)[0] & 0x0f) << 8) + (p)[1]) +#define MPPE_CCOUNT_SPACE 0x1000 /* The size of the ccount space */ + +#define MPPE_OVHD 2 /* MPPE overhead/packet */ +#define SANITY_MAX 1600 /* Max bogon factor we will tolerate */ + +/* + * Perform the MPPE rekey algorithm, from RFC 3078, sec. 7.3. + * Well, not what's written there, but rather what they meant. + */ +static void mppe_rekey(ppp_mppe_state * state, int initial_key) +{ + lwip_sha1_context sha1_ctx; + u8_t sha1_digest[SHA1_SIGNATURE_SIZE]; + + /* + * Key Derivation, from RFC 3078, RFC 3079. + * Equivalent to Get_Key() for MS-CHAP as described in RFC 3079. + */ + lwip_sha1_init(&sha1_ctx); + lwip_sha1_starts(&sha1_ctx); + lwip_sha1_update(&sha1_ctx, state->master_key, state->keylen); + lwip_sha1_update(&sha1_ctx, mppe_sha1_pad1, SHA1_PAD_SIZE); + lwip_sha1_update(&sha1_ctx, state->session_key, state->keylen); + lwip_sha1_update(&sha1_ctx, mppe_sha1_pad2, SHA1_PAD_SIZE); + lwip_sha1_finish(&sha1_ctx, sha1_digest); + lwip_sha1_free(&sha1_ctx); + MEMCPY(state->session_key, sha1_digest, state->keylen); + + if (!initial_key) { + lwip_arc4_init(&state->arc4); + lwip_arc4_setup(&state->arc4, sha1_digest, state->keylen); + lwip_arc4_crypt(&state->arc4, state->session_key, state->keylen); + lwip_arc4_free(&state->arc4); + } + if (state->keylen == 8) { + /* See RFC 3078 */ + state->session_key[0] = 0xd1; + state->session_key[1] = 0x26; + state->session_key[2] = 0x9e; + } + lwip_arc4_init(&state->arc4); + lwip_arc4_setup(&state->arc4, state->session_key, state->keylen); +} + +/* + * Set key, used by MSCHAP before mppe_init() is actually called by CCP so we + * don't have to keep multiple copies of keys. + */ +void mppe_set_key(ppp_pcb *pcb, ppp_mppe_state *state, u8_t *key) { + LWIP_UNUSED_ARG(pcb); + MEMCPY(state->master_key, key, MPPE_MAX_KEY_LEN); +} + +/* + * Initialize (de)compressor state. + */ +void +mppe_init(ppp_pcb *pcb, ppp_mppe_state *state, u8_t options) +{ +#if PPP_DEBUG + const u8_t *debugstr = (const u8_t*)"mppe_comp_init"; + if (&pcb->mppe_decomp == state) { + debugstr = (const u8_t*)"mppe_decomp_init"; + } +#endif /* PPP_DEBUG */ + + /* Save keys. */ + MEMCPY(state->session_key, state->master_key, sizeof(state->master_key)); + + if (options & MPPE_OPT_128) + state->keylen = 16; + else if (options & MPPE_OPT_40) + state->keylen = 8; + else { + PPPDEBUG(LOG_DEBUG, ("%s[%d]: unknown key length\n", debugstr, + pcb->netif->num)); + lcp_close(pcb, "MPPE required but peer negotiation failed"); + return; + } + if (options & MPPE_OPT_STATEFUL) + state->stateful = 1; + + /* Generate the initial session key. */ + mppe_rekey(state, 1); + +#if PPP_DEBUG + { + int i; + char mkey[sizeof(state->master_key) * 2 + 1]; + char skey[sizeof(state->session_key) * 2 + 1]; + + PPPDEBUG(LOG_DEBUG, ("%s[%d]: initialized with %d-bit %s mode\n", + debugstr, pcb->netif->num, (state->keylen == 16) ? 128 : 40, + (state->stateful) ? "stateful" : "stateless")); + + for (i = 0; i < (int)sizeof(state->master_key); i++) + sprintf(mkey + i * 2, "%02x", state->master_key[i]); + for (i = 0; i < (int)sizeof(state->session_key); i++) + sprintf(skey + i * 2, "%02x", state->session_key[i]); + PPPDEBUG(LOG_DEBUG, + ("%s[%d]: keys: master: %s initial session: %s\n", + debugstr, pcb->netif->num, mkey, skey)); + } +#endif /* PPP_DEBUG */ + + /* + * Initialize the coherency count. The initial value is not specified + * in RFC 3078, but we can make a reasonable assumption that it will + * start at 0. Setting it to the max here makes the comp/decomp code + * do the right thing (determined through experiment). + */ + state->ccount = MPPE_CCOUNT_SPACE - 1; + + /* + * Note that even though we have initialized the key table, we don't + * set the FLUSHED bit. This is contrary to RFC 3078, sec. 3.1. + */ + state->bits = MPPE_BIT_ENCRYPTED; +} + +/* + * We received a CCP Reset-Request (actually, we are sending a Reset-Ack), + * tell the compressor to rekey. Note that we MUST NOT rekey for + * every CCP Reset-Request; we only rekey on the next xmit packet. + * We might get multiple CCP Reset-Requests if our CCP Reset-Ack is lost. + * So, rekeying for every CCP Reset-Request is broken as the peer will not + * know how many times we've rekeyed. (If we rekey and THEN get another + * CCP Reset-Request, we must rekey again.) + */ +void mppe_comp_reset(ppp_pcb *pcb, ppp_mppe_state *state) +{ + LWIP_UNUSED_ARG(pcb); + state->bits |= MPPE_BIT_FLUSHED; +} + +/* + * Compress (encrypt) a packet. + * It's strange to call this a compressor, since the output is always + * MPPE_OVHD + 2 bytes larger than the input. + */ +err_t +mppe_compress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb, u16_t protocol) +{ + struct pbuf *n, *np; + u8_t *pl; + err_t err; + + LWIP_UNUSED_ARG(pcb); + + /* TCP stack requires that we don't change the packet payload, therefore we copy + * the whole packet before encryption. + */ + np = pbuf_alloc(PBUF_RAW, MPPE_OVHD + sizeof(protocol) + (*pb)->tot_len, PBUF_RAM); + if (!np) { + return ERR_MEM; + } + + /* Hide MPPE header + protocol */ + pbuf_remove_header(np, MPPE_OVHD + sizeof(protocol)); + + if ((err = pbuf_copy(np, *pb)) != ERR_OK) { + pbuf_free(np); + return err; + } + + /* Reveal MPPE header + protocol */ + pbuf_add_header(np, MPPE_OVHD + sizeof(protocol)); + + *pb = np; + pl = (u8_t*)np->payload; + + state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE; + PPPDEBUG(LOG_DEBUG, ("mppe_compress[%d]: ccount %d\n", pcb->netif->num, state->ccount)); + /* FIXME: use PUT* macros */ + pl[0] = state->ccount>>8; + pl[1] = state->ccount; + + if (!state->stateful || /* stateless mode */ + ((state->ccount & 0xff) == 0xff) || /* "flag" packet */ + (state->bits & MPPE_BIT_FLUSHED)) { /* CCP Reset-Request */ + /* We must rekey */ + if (state->stateful) { + PPPDEBUG(LOG_DEBUG, ("mppe_compress[%d]: rekeying\n", pcb->netif->num)); + } + mppe_rekey(state, 0); + state->bits |= MPPE_BIT_FLUSHED; + } + pl[0] |= state->bits; + state->bits &= ~MPPE_BIT_FLUSHED; /* reset for next xmit */ + pl += MPPE_OVHD; + + /* Add protocol */ + /* FIXME: add PFC support */ + pl[0] = protocol >> 8; + pl[1] = protocol; + + /* Hide MPPE header */ + pbuf_remove_header(np, MPPE_OVHD); + + /* Encrypt packet */ + for (n = np; n != NULL; n = n->next) { + lwip_arc4_crypt(&state->arc4, (u8_t*)n->payload, n->len); + if (n->tot_len == n->len) { + break; + } + } + + /* Reveal MPPE header */ + pbuf_add_header(np, MPPE_OVHD); + + return ERR_OK; +} + +/* + * We received a CCP Reset-Ack. Just ignore it. + */ +void mppe_decomp_reset(ppp_pcb *pcb, ppp_mppe_state *state) +{ + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(state); + return; +} + +/* + * Decompress (decrypt) an MPPE packet. + */ +err_t +mppe_decompress(ppp_pcb *pcb, ppp_mppe_state *state, struct pbuf **pb) +{ + struct pbuf *n0 = *pb, *n; + u8_t *pl; + u16_t ccount; + u8_t flushed; + + /* MPPE Header */ + if (n0->len < MPPE_OVHD) { + PPPDEBUG(LOG_DEBUG, + ("mppe_decompress[%d]: short pkt (%d)\n", + pcb->netif->num, n0->len)); + state->sanity_errors += 100; + goto sanity_error; + } + + pl = (u8_t*)n0->payload; + flushed = MPPE_BITS(pl) & MPPE_BIT_FLUSHED; + ccount = MPPE_CCOUNT(pl); + PPPDEBUG(LOG_DEBUG, ("mppe_decompress[%d]: ccount %d\n", + pcb->netif->num, ccount)); + + /* sanity checks -- terminate with extreme prejudice */ + if (!(MPPE_BITS(pl) & MPPE_BIT_ENCRYPTED)) { + PPPDEBUG(LOG_DEBUG, + ("mppe_decompress[%d]: ENCRYPTED bit not set!\n", + pcb->netif->num)); + state->sanity_errors += 100; + goto sanity_error; + } + if (!state->stateful && !flushed) { + PPPDEBUG(LOG_DEBUG, ("mppe_decompress[%d]: FLUSHED bit not set in " + "stateless mode!\n", pcb->netif->num)); + state->sanity_errors += 100; + goto sanity_error; + } + if (state->stateful && ((ccount & 0xff) == 0xff) && !flushed) { + PPPDEBUG(LOG_DEBUG, ("mppe_decompress[%d]: FLUSHED bit not set on " + "flag packet!\n", pcb->netif->num)); + state->sanity_errors += 100; + goto sanity_error; + } + + /* + * Check the coherency count. + */ + + if (!state->stateful) { + /* Discard late packet */ + if ((ccount - state->ccount) % MPPE_CCOUNT_SPACE > MPPE_CCOUNT_SPACE / 2) { + state->sanity_errors++; + goto sanity_error; + } + + /* RFC 3078, sec 8.1. Rekey for every packet. */ + while (state->ccount != ccount) { + mppe_rekey(state, 0); + state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE; + } + } else { + /* RFC 3078, sec 8.2. */ + if (!state->discard) { + /* normal state */ + state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE; + if (ccount != state->ccount) { + /* + * (ccount > state->ccount) + * Packet loss detected, enter the discard state. + * Signal the peer to rekey (by sending a CCP Reset-Request). + */ + state->discard = 1; + ccp_resetrequest(pcb); + return ERR_BUF; + } + } else { + /* discard state */ + if (!flushed) { + /* ccp.c will be silent (no additional CCP Reset-Requests). */ + return ERR_BUF; + } else { + /* Rekey for every missed "flag" packet. */ + while ((ccount & ~0xff) != + (state->ccount & ~0xff)) { + mppe_rekey(state, 0); + state->ccount = + (state->ccount + + 256) % MPPE_CCOUNT_SPACE; + } + + /* reset */ + state->discard = 0; + state->ccount = ccount; + /* + * Another problem with RFC 3078 here. It implies that the + * peer need not send a Reset-Ack packet. But RFC 1962 + * requires it. Hopefully, M$ does send a Reset-Ack; even + * though it isn't required for MPPE synchronization, it is + * required to reset CCP state. + */ + } + } + if (flushed) + mppe_rekey(state, 0); + } + + /* Hide MPPE header */ + pbuf_remove_header(n0, MPPE_OVHD); + + /* Decrypt the packet. */ + for (n = n0; n != NULL; n = n->next) { + lwip_arc4_crypt(&state->arc4, (u8_t*)n->payload, n->len); + if (n->tot_len == n->len) { + break; + } + } + + /* good packet credit */ + state->sanity_errors >>= 1; + + return ERR_OK; + +sanity_error: + if (state->sanity_errors >= SANITY_MAX) { + /* + * Take LCP down if the peer is sending too many bogons. + * We don't want to do this for a single or just a few + * instances since it could just be due to packet corruption. + */ + lcp_close(pcb, "Too many MPPE errors"); + } + return ERR_BUF; +} + +#endif /* PPP_SUPPORT && MPPE_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c new file mode 100644 index 0000000..62014e8 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/multilink.c @@ -0,0 +1,609 @@ +/* + * multilink.c - support routines for multilink. + * + * Copyright (c) 2000-2002 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && defined(HAVE_MULTILINK) /* don't build if not configured for use in lwipopts.h */ + +/* Multilink support + * + * Multilink uses Samba TDB (Trivial Database Library), which + * we cannot port, because it needs a filesystem. + * + * We have to choose between doing a memory-shared TDB-clone, + * or dropping multilink support at all. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/lcp.h" +#include "netif/ppp/tdb.h" + +bool endpoint_specified; /* user gave explicit endpoint discriminator */ +char *bundle_id; /* identifier for our bundle */ +char *blinks_id; /* key for the list of links */ +bool doing_multilink; /* multilink was enabled and agreed to */ +bool multilink_master; /* we own the multilink bundle */ + +extern TDB_CONTEXT *pppdb; +extern char db_key[]; + +static void make_bundle_links (int append); +static void remove_bundle_link (void); +static void iterate_bundle_links (void (*func) (char *)); + +static int get_default_epdisc (struct epdisc *); +static int parse_num (char *str, const char *key, int *valp); +static int owns_unit (TDB_DATA pid, int unit); + +#define set_ip_epdisc(ep, addr) do { \ + ep->length = 4; \ + ep->value[0] = addr >> 24; \ + ep->value[1] = addr >> 16; \ + ep->value[2] = addr >> 8; \ + ep->value[3] = addr; \ +} while (0) + +#define LOCAL_IP_ADDR(addr) \ + (((addr) & 0xff000000) == 0x0a000000 /* 10.x.x.x */ \ + || ((addr) & 0xfff00000) == 0xac100000 /* 172.16.x.x */ \ + || ((addr) & 0xffff0000) == 0xc0a80000) /* 192.168.x.x */ + +#define process_exists(n) (kill((n), 0) == 0 || errno != ESRCH) + +void +mp_check_options() +{ + lcp_options *wo = &lcp_wantoptions[0]; + lcp_options *ao = &lcp_allowoptions[0]; + + doing_multilink = 0; + if (!multilink) + return; + /* if we're doing multilink, we have to negotiate MRRU */ + if (!wo->neg_mrru) { + /* mrru not specified, default to mru */ + wo->mrru = wo->mru; + wo->neg_mrru = 1; + } + ao->mrru = ao->mru; + ao->neg_mrru = 1; + + if (!wo->neg_endpoint && !noendpoint) { + /* get a default endpoint value */ + wo->neg_endpoint = get_default_epdisc(&wo->endpoint); + } +} + +/* + * Make a new bundle or join us to an existing bundle + * if we are doing multilink. + */ +int +mp_join_bundle() +{ + lcp_options *go = &lcp_gotoptions[0]; + lcp_options *ho = &lcp_hisoptions[0]; + lcp_options *ao = &lcp_allowoptions[0]; + int unit, pppd_pid; + int l, mtu; + char *p; + TDB_DATA key, pid, rec; + + if (doing_multilink) { + /* have previously joined a bundle */ + if (!go->neg_mrru || !ho->neg_mrru) { + notice("oops, didn't get multilink on renegotiation"); + lcp_close(pcb, "multilink required"); + return 0; + } + /* XXX should check the peer_authname and ho->endpoint + are the same as previously */ + return 0; + } + + if (!go->neg_mrru || !ho->neg_mrru) { + /* not doing multilink */ + if (go->neg_mrru) + notice("oops, multilink negotiated only for receive"); + mtu = ho->neg_mru? ho->mru: PPP_MRU; + if (mtu > ao->mru) + mtu = ao->mru; + if (demand) { + /* already have a bundle */ + cfg_bundle(0, 0, 0, 0); + netif_set_mtu(pcb, mtu); + return 0; + } + make_new_bundle(0, 0, 0, 0); + set_ifunit(1); + netif_set_mtu(pcb, mtu); + return 0; + } + + doing_multilink = 1; + + /* + * Find the appropriate bundle or join a new one. + * First we make up a name for the bundle. + * The length estimate is worst-case assuming every + * character has to be quoted. + */ + l = 4 * strlen(peer_authname) + 10; + if (ho->neg_endpoint) + l += 3 * ho->endpoint.length + 8; + if (bundle_name) + l += 3 * strlen(bundle_name) + 2; + bundle_id = malloc(l); + if (bundle_id == 0) + novm("bundle identifier"); + + p = bundle_id; + p += slprintf(p, l-1, "BUNDLE=\"%q\"", peer_authname); + if (ho->neg_endpoint || bundle_name) + *p++ = '/'; + if (ho->neg_endpoint) + p += slprintf(p, bundle_id+l-p, "%s", + epdisc_to_str(&ho->endpoint)); + if (bundle_name) + p += slprintf(p, bundle_id+l-p, "/%v", bundle_name); + + /* Make the key for the list of links belonging to the bundle */ + l = p - bundle_id; + blinks_id = malloc(l + 7); + if (blinks_id == NULL) + novm("bundle links key"); + slprintf(blinks_id, l + 7, "BUNDLE_LINKS=%s", bundle_id + 7); + + /* + * For demand mode, we only need to configure the bundle + * and attach the link. + */ + mtu = LWIP_MIN(ho->mrru, ao->mru); + if (demand) { + cfg_bundle(go->mrru, ho->mrru, go->neg_ssnhf, ho->neg_ssnhf); + netif_set_mtu(pcb, mtu); + script_setenv("BUNDLE", bundle_id + 7, 1); + return 0; + } + + /* + * Check if the bundle ID is already in the database. + */ + unit = -1; + lock_db(); + key.dptr = bundle_id; + key.dsize = p - bundle_id; + pid = tdb_fetch(pppdb, key); + if (pid.dptr != NULL) { + /* bundle ID exists, see if the pppd record exists */ + rec = tdb_fetch(pppdb, pid); + if (rec.dptr != NULL && rec.dsize > 0) { + /* make sure the string is null-terminated */ + rec.dptr[rec.dsize-1] = 0; + /* parse the interface number */ + parse_num(rec.dptr, "IFNAME=ppp", &unit); + /* check the pid value */ + if (!parse_num(rec.dptr, "PPPD_PID=", &pppd_pid) + || !process_exists(pppd_pid) + || !owns_unit(pid, unit)) + unit = -1; + free(rec.dptr); + } + free(pid.dptr); + } + + if (unit >= 0) { + /* attach to existing unit */ + if (bundle_attach(unit)) { + set_ifunit(0); + script_setenv("BUNDLE", bundle_id + 7, 0); + make_bundle_links(1); + unlock_db(); + info("Link attached to %s", ifname); + return 1; + } + /* attach failed because bundle doesn't exist */ + } + + /* we have to make a new bundle */ + make_new_bundle(go->mrru, ho->mrru, go->neg_ssnhf, ho->neg_ssnhf); + set_ifunit(1); + netif_set_mtu(pcb, mtu); + script_setenv("BUNDLE", bundle_id + 7, 1); + make_bundle_links(pcb); + unlock_db(); + info("New bundle %s created", ifname); + multilink_master = 1; + return 0; +} + +void mp_exit_bundle() +{ + lock_db(); + remove_bundle_link(); + unlock_db(); +} + +static void sendhup(char *str) +{ + int pid; + + if (parse_num(str, "PPPD_PID=", &pid) && pid != getpid()) { + if (debug) + dbglog("sending SIGHUP to process %d", pid); + kill(pid, SIGHUP); + } +} + +void mp_bundle_terminated() +{ + TDB_DATA key; + + bundle_terminating = 1; + upper_layers_down(pcb); + notice("Connection terminated."); +#if PPP_STATS_SUPPORT + print_link_stats(); +#endif /* PPP_STATS_SUPPORT */ + if (!demand) { + remove_pidfiles(); + script_unsetenv("IFNAME"); + } + + lock_db(); + destroy_bundle(); + iterate_bundle_links(sendhup); + key.dptr = blinks_id; + key.dsize = strlen(blinks_id); + tdb_delete(pppdb, key); + unlock_db(); + + new_phase(PPP_PHASE_DEAD); + + doing_multilink = 0; + multilink_master = 0; +} + +static void make_bundle_links(int append) +{ + TDB_DATA key, rec; + char *p; + char entry[32]; + int l; + + key.dptr = blinks_id; + key.dsize = strlen(blinks_id); + slprintf(entry, sizeof(entry), "%s;", db_key); + p = entry; + if (append) { + rec = tdb_fetch(pppdb, key); + if (rec.dptr != NULL && rec.dsize > 0) { + rec.dptr[rec.dsize-1] = 0; + if (strstr(rec.dptr, db_key) != NULL) { + /* already in there? strange */ + warn("link entry already exists in tdb"); + return; + } + l = rec.dsize + strlen(entry); + p = malloc(l); + if (p == NULL) + novm("bundle link list"); + slprintf(p, l, "%s%s", rec.dptr, entry); + } else { + warn("bundle link list not found"); + } + if (rec.dptr != NULL) + free(rec.dptr); + } + rec.dptr = p; + rec.dsize = strlen(p) + 1; + if (tdb_store(pppdb, key, rec, TDB_REPLACE)) + error("couldn't %s bundle link list", + append? "update": "create"); + if (p != entry) + free(p); +} + +static void remove_bundle_link() +{ + TDB_DATA key, rec; + char entry[32]; + char *p, *q; + int l; + + key.dptr = blinks_id; + key.dsize = strlen(blinks_id); + slprintf(entry, sizeof(entry), "%s;", db_key); + + rec = tdb_fetch(pppdb, key); + if (rec.dptr == NULL || rec.dsize <= 0) { + if (rec.dptr != NULL) + free(rec.dptr); + return; + } + rec.dptr[rec.dsize-1] = 0; + p = strstr(rec.dptr, entry); + if (p != NULL) { + q = p + strlen(entry); + l = strlen(q) + 1; + memmove(p, q, l); + rec.dsize = p - rec.dptr + l; + if (tdb_store(pppdb, key, rec, TDB_REPLACE)) + error("couldn't update bundle link list (removal)"); + } + free(rec.dptr); +} + +static void iterate_bundle_links(void (*func)(char *)) +{ + TDB_DATA key, rec, pp; + char *p, *q; + + key.dptr = blinks_id; + key.dsize = strlen(blinks_id); + rec = tdb_fetch(pppdb, key); + if (rec.dptr == NULL || rec.dsize <= 0) { + error("bundle link list not found (iterating list)"); + if (rec.dptr != NULL) + free(rec.dptr); + return; + } + p = rec.dptr; + p[rec.dsize-1] = 0; + while ((q = strchr(p, ';')) != NULL) { + *q = 0; + key.dptr = p; + key.dsize = q - p; + pp = tdb_fetch(pppdb, key); + if (pp.dptr != NULL && pp.dsize > 0) { + pp.dptr[pp.dsize-1] = 0; + func(pp.dptr); + } + if (pp.dptr != NULL) + free(pp.dptr); + p = q + 1; + } + free(rec.dptr); +} + +static int +parse_num(str, key, valp) + char *str; + const char *key; + int *valp; +{ + char *p, *endp; + int i; + + p = strstr(str, key); + if (p != 0) { + p += strlen(key); + i = strtol(p, &endp, 10); + if (endp != p && (*endp == 0 || *endp == ';')) { + *valp = i; + return 1; + } + } + return 0; +} + +/* + * Check whether the pppd identified by `key' still owns ppp unit `unit'. + */ +static int +owns_unit(key, unit) + TDB_DATA key; + int unit; +{ + char ifkey[32]; + TDB_DATA kd, vd; + int ret = 0; + + slprintf(ifkey, sizeof(ifkey), "IFNAME=ppp%d", unit); + kd.dptr = ifkey; + kd.dsize = strlen(ifkey); + vd = tdb_fetch(pppdb, kd); + if (vd.dptr != NULL) { + ret = vd.dsize == key.dsize + && memcmp(vd.dptr, key.dptr, vd.dsize) == 0; + free(vd.dptr); + } + return ret; +} + +static int +get_default_epdisc(ep) + struct epdisc *ep; +{ + char *p; + struct hostent *hp; + u32_t addr; + + /* First try for an ethernet MAC address */ + p = get_first_ethernet(); + if (p != 0 && get_if_hwaddr(ep->value, p) >= 0) { + ep->class = EPD_MAC; + ep->length = 6; + return 1; + } + + /* see if our hostname corresponds to a reasonable IP address */ + hp = gethostbyname(hostname); + if (hp != NULL) { + addr = *(u32_t *)hp->h_addr; + if (!bad_ip_adrs(addr)) { + addr = lwip_ntohl(addr); + if (!LOCAL_IP_ADDR(addr)) { + ep->class = EPD_IP; + set_ip_epdisc(ep, addr); + return 1; + } + } + } + + return 0; +} + +/* + * epdisc_to_str - make a printable string from an endpoint discriminator. + */ + +static char *endp_class_names[] = { + "null", "local", "IP", "MAC", "magic", "phone" +}; + +char * +epdisc_to_str(ep) + struct epdisc *ep; +{ + static char str[MAX_ENDP_LEN*3+8]; + u_char *p = ep->value; + int i, mask = 0; + char *q, c, c2; + + if (ep->class == EPD_NULL && ep->length == 0) + return "null"; + if (ep->class == EPD_IP && ep->length == 4) { + u32_t addr; + + GETLONG(addr, p); + slprintf(str, sizeof(str), "IP:%I", lwip_htonl(addr)); + return str; + } + + c = ':'; + c2 = '.'; + if (ep->class == EPD_MAC && ep->length == 6) + c2 = ':'; + else if (ep->class == EPD_MAGIC && (ep->length % 4) == 0) + mask = 3; + q = str; + if (ep->class <= EPD_PHONENUM) + q += slprintf(q, sizeof(str)-1, "%s", + endp_class_names[ep->class]); + else + q += slprintf(q, sizeof(str)-1, "%d", ep->class); + c = ':'; + for (i = 0; i < ep->length && i < MAX_ENDP_LEN; ++i) { + if ((i & mask) == 0) { + *q++ = c; + c = c2; + } + q += slprintf(q, str + sizeof(str) - q, "%.2x", ep->value[i]); + } + return str; +} + +static int hexc_val(int c) +{ + if (c >= 'a') + return c - 'a' + 10; + if (c >= 'A') + return c - 'A' + 10; + return c - '0'; +} + +int +str_to_epdisc(ep, str) + struct epdisc *ep; + char *str; +{ + int i, l; + char *p, *endp; + + for (i = EPD_NULL; i <= EPD_PHONENUM; ++i) { + int sl = strlen(endp_class_names[i]); + if (strncasecmp(str, endp_class_names[i], sl) == 0) { + str += sl; + break; + } + } + if (i > EPD_PHONENUM) { + /* not a class name, try a decimal class number */ + i = strtol(str, &endp, 10); + if (endp == str) + return 0; /* can't parse class number */ + str = endp; + } + ep->class = i; + if (*str == 0) { + ep->length = 0; + return 1; + } + if (*str != ':' && *str != '.') + return 0; + ++str; + + if (i == EPD_IP) { + u32_t addr; + i = parse_dotted_ip(str, &addr); + if (i == 0 || str[i] != 0) + return 0; + set_ip_epdisc(ep, addr); + return 1; + } + if (i == EPD_MAC && get_if_hwaddr(ep->value, str) >= 0) { + ep->length = 6; + return 1; + } + + p = str; + for (l = 0; l < MAX_ENDP_LEN; ++l) { + if (*str == 0) + break; + if (p <= str) + for (p = str; isxdigit(*p); ++p) + ; + i = p - str; + if (i == 0) + return 0; + ep->value[l] = hexc_val(*str++); + if ((i & 1) == 0) + ep->value[l] = (ep->value[l] << 4) + hexc_val(*str++); + if (*str == ':' || *str == '.') + ++str; + } + if (*str != 0 || (ep->class == EPD_MAC && l != 6)) + return 0; + ep->length = l; + return 1; +} + +#endif /* PPP_SUPPORT && HAVE_MULTILINK */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c new file mode 100644 index 0000000..a9c18e3 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/ppp.c @@ -0,0 +1,1628 @@ +/***************************************************************************** +* ppp.c - Network Point to Point Protocol program file. +* +* Copyright (c) 2003 by Marc Boucher, Services Informatiques (MBSI) inc. +* portions Copyright (c) 1997 by Global Election Systems Inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 03-01-01 Marc Boucher +* Ported to lwIP. +* 97-11-05 Guy Lancaster , Global Election Systems Inc. +* Original. +*****************************************************************************/ + +/* + * ppp_defs.h - PPP definitions. + * + * if_pppvar.h - private structures and declarations for PPP. + * + * Copyright (c) 1994 The Australian National University. + * All rights reserved. + * + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, provided that the above copyright + * notice appears in all copies. This software is provided without any + * warranty, express or implied. The Australian National University + * makes no representations about the suitability of this software for + * any purpose. + * + * IN NO EVENT SHALL THE AUSTRALIAN NATIONAL UNIVERSITY BE LIABLE TO ANY + * PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES + * ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF + * THE AUSTRALIAN NATIONAL UNIVERSITY HAVE BEEN ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * THE AUSTRALIAN NATIONAL UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS + * ON AN "AS IS" BASIS, AND THE AUSTRALIAN NATIONAL UNIVERSITY HAS NO + * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, + * OR MODIFICATIONS. + */ + +/* + * if_ppp.h - Point-to-Point Protocol definitions. + * + * Copyright (c) 1989 Carnegie Mellon University. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by Carnegie Mellon University. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +/** + * @defgroup ppp PPP + * @ingroup netifs + * @verbinclude "ppp.txt" + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/sys.h" +#include "lwip/tcpip.h" +#include "lwip/api.h" +#include "lwip/snmp.h" +#include "lwip/ip4.h" /* for ip4_input() */ +#if PPP_IPV6_SUPPORT +#include "lwip/ip6.h" /* for ip6_input() */ +#endif /* PPP_IPV6_SUPPORT */ +#include "lwip/dns.h" + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/pppos.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/lcp.h" +#include "netif/ppp/magic.h" + +#if PAP_SUPPORT +#include "netif/ppp/upap.h" +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT +#include "netif/ppp/chap-new.h" +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT +#include "netif/ppp/eap.h" +#endif /* EAP_SUPPORT */ +#if CCP_SUPPORT +#include "netif/ppp/ccp.h" +#endif /* CCP_SUPPORT */ +#if MPPE_SUPPORT +#include "netif/ppp/mppe.h" +#endif /* MPPE_SUPPORT */ +#if ECP_SUPPORT +#include "netif/ppp/ecp.h" +#endif /* EAP_SUPPORT */ +#if VJ_SUPPORT +#include "netif/ppp/vj.h" +#endif /* VJ_SUPPORT */ +#if PPP_IPV4_SUPPORT +#include "netif/ppp/ipcp.h" +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT +#include "netif/ppp/ipv6cp.h" +#endif /* PPP_IPV6_SUPPORT */ + +/*************************/ +/*** LOCAL DEFINITIONS ***/ +/*************************/ + +/* Memory pools */ +#if PPPOS_SUPPORT +LWIP_MEMPOOL_PROTOTYPE(PPPOS_PCB); +#endif +#if PPPOE_SUPPORT +LWIP_MEMPOOL_PROTOTYPE(PPPOE_IF); +#endif +#if PPPOL2TP_SUPPORT +LWIP_MEMPOOL_PROTOTYPE(PPPOL2TP_PCB); +#endif +#if LWIP_PPP_API && LWIP_MPU_COMPATIBLE +LWIP_MEMPOOL_PROTOTYPE(PPPAPI_MSG); +#endif +LWIP_MEMPOOL_DECLARE(PPP_PCB, MEMP_NUM_PPP_PCB, sizeof(ppp_pcb), "PPP_PCB") + +/* FIXME: add stats per PPP session */ +#if PPP_STATS_SUPPORT +static struct timeval start_time; /* Time when link was started. */ +static struct pppd_stats old_link_stats; +struct pppd_stats link_stats; +unsigned link_connect_time; +int link_stats_valid; +#endif /* PPP_STATS_SUPPORT */ + +/* + * PPP Data Link Layer "protocol" table. + * One entry per supported protocol. + * The last entry must be NULL. + */ +const struct protent* const protocols[] = { + &lcp_protent, +#if PAP_SUPPORT + &pap_protent, +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + &chap_protent, +#endif /* CHAP_SUPPORT */ +#if CBCP_SUPPORT + &cbcp_protent, +#endif /* CBCP_SUPPORT */ +#if PPP_IPV4_SUPPORT + &ipcp_protent, +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT + &ipv6cp_protent, +#endif /* PPP_IPV6_SUPPORT */ +#if CCP_SUPPORT + &ccp_protent, +#endif /* CCP_SUPPORT */ +#if ECP_SUPPORT + &ecp_protent, +#endif /* ECP_SUPPORT */ +#ifdef AT_CHANGE + &atcp_protent, +#endif /* AT_CHANGE */ +#if EAP_SUPPORT + &eap_protent, +#endif /* EAP_SUPPORT */ + NULL +}; + +/* Prototypes for procedures local to this file. */ +static void ppp_do_connect(void *arg); +static err_t ppp_netif_init_cb(struct netif *netif); +#if PPP_IPV4_SUPPORT +static err_t ppp_netif_output_ip4(struct netif *netif, struct pbuf *pb, const ip4_addr_t *ipaddr); +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT +static err_t ppp_netif_output_ip6(struct netif *netif, struct pbuf *pb, const ip6_addr_t *ipaddr); +#endif /* PPP_IPV6_SUPPORT */ +static err_t ppp_netif_output(struct netif *netif, struct pbuf *pb, u16_t protocol); + +/***********************************/ +/*** PUBLIC FUNCTION DEFINITIONS ***/ +/***********************************/ +#if PPP_AUTH_SUPPORT +void ppp_set_auth(ppp_pcb *pcb, u8_t authtype, const char *user, const char *passwd) { + LWIP_ASSERT_CORE_LOCKED(); +#if PAP_SUPPORT + pcb->settings.refuse_pap = !(authtype & PPPAUTHTYPE_PAP); +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + pcb->settings.refuse_chap = !(authtype & PPPAUTHTYPE_CHAP); +#if MSCHAP_SUPPORT + pcb->settings.refuse_mschap = !(authtype & PPPAUTHTYPE_MSCHAP); + pcb->settings.refuse_mschap_v2 = !(authtype & PPPAUTHTYPE_MSCHAP_V2); +#endif /* MSCHAP_SUPPORT */ +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + pcb->settings.refuse_eap = !(authtype & PPPAUTHTYPE_EAP); +#endif /* EAP_SUPPORT */ + pcb->settings.user = user; + pcb->settings.passwd = passwd; +} +#endif /* PPP_AUTH_SUPPORT */ + +#if MPPE_SUPPORT +/* Set MPPE configuration */ +void ppp_set_mppe(ppp_pcb *pcb, u8_t flags) { + if (flags == PPP_MPPE_DISABLE) { + pcb->settings.require_mppe = 0; + return; + } + + pcb->settings.require_mppe = 1; + pcb->settings.refuse_mppe_stateful = !(flags & PPP_MPPE_ALLOW_STATEFUL); + pcb->settings.refuse_mppe_40 = !!(flags & PPP_MPPE_REFUSE_40); + pcb->settings.refuse_mppe_128 = !!(flags & PPP_MPPE_REFUSE_128); +} +#endif /* MPPE_SUPPORT */ + +#if PPP_NOTIFY_PHASE +void ppp_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb) { + pcb->notify_phase_cb = notify_phase_cb; + notify_phase_cb(pcb, pcb->phase, pcb->ctx_cb); +} +#endif /* PPP_NOTIFY_PHASE */ + +/* + * Initiate a PPP connection. + * + * This can only be called if PPP is in the dead phase. + * + * Holdoff is the time to wait (in seconds) before initiating + * the connection. + * + * If this port connects to a modem, the modem connection must be + * established before calling this. + */ +err_t ppp_connect(ppp_pcb *pcb, u16_t holdoff) { + LWIP_ASSERT_CORE_LOCKED(); + if (pcb->phase != PPP_PHASE_DEAD) { + return ERR_ALREADY; + } + + PPPDEBUG(LOG_DEBUG, ("ppp_connect[%d]: holdoff=%d\n", pcb->netif->num, holdoff)); + + magic_randomize(); + + if (holdoff == 0) { + ppp_do_connect(pcb); + return ERR_OK; + } + + new_phase(pcb, PPP_PHASE_HOLDOFF); + sys_timeout((u32_t)(holdoff*1000), ppp_do_connect, pcb); + return ERR_OK; +} + +#if PPP_SERVER +/* + * Listen for an incoming PPP connection. + * + * This can only be called if PPP is in the dead phase. + * + * If this port connects to a modem, the modem connection must be + * established before calling this. + */ +err_t ppp_listen(ppp_pcb *pcb) { + LWIP_ASSERT_CORE_LOCKED(); + if (pcb->phase != PPP_PHASE_DEAD) { + return ERR_ALREADY; + } + + PPPDEBUG(LOG_DEBUG, ("ppp_listen[%d]\n", pcb->netif->num)); + + magic_randomize(); + + if (pcb->link_cb->listen) { + new_phase(pcb, PPP_PHASE_INITIALIZE); + pcb->link_cb->listen(pcb, pcb->link_ctx_cb); + return ERR_OK; + } + return ERR_IF; +} +#endif /* PPP_SERVER */ + +/* + * Initiate the end of a PPP connection. + * Any outstanding packets in the queues are dropped. + * + * Setting nocarrier to 1 close the PPP connection without initiating the + * shutdown procedure. Always using nocarrier = 0 is still recommended, + * this is going to take a little longer time if your link is down, but + * is a safer choice for the PPP state machine. + * + * Return 0 on success, an error code on failure. + */ +err_t +ppp_close(ppp_pcb *pcb, u8_t nocarrier) +{ + LWIP_ASSERT_CORE_LOCKED(); + + pcb->err_code = PPPERR_USER; + + /* holdoff phase, cancel the reconnection */ + if (pcb->phase == PPP_PHASE_HOLDOFF) { + sys_untimeout(ppp_do_connect, pcb); + new_phase(pcb, PPP_PHASE_DEAD); + } + + /* dead phase, nothing to do, call the status callback to be consistent */ + if (pcb->phase == PPP_PHASE_DEAD) { + pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb); + return ERR_OK; + } + + /* Already terminating, nothing to do */ + if (pcb->phase >= PPP_PHASE_TERMINATE) { + return ERR_INPROGRESS; + } + + /* LCP not open, close link protocol */ + if (pcb->phase < PPP_PHASE_ESTABLISH) { + new_phase(pcb, PPP_PHASE_DISCONNECT); + ppp_link_terminated(pcb); + return ERR_OK; + } + + /* + * Only accept carrier lost signal on the stable running phase in order + * to prevent changing the PPP phase FSM in transition phases. + * + * Always using nocarrier = 0 is still recommended, this is going to + * take a little longer time, but is a safer choice from FSM point of view. + */ + if (nocarrier && pcb->phase == PPP_PHASE_RUNNING) { + PPPDEBUG(LOG_DEBUG, ("ppp_close[%d]: carrier lost -> lcp_lowerdown\n", pcb->netif->num)); + lcp_lowerdown(pcb); + /* forced link termination, this will force link protocol to disconnect. */ + link_terminated(pcb); + return ERR_OK; + } + + /* Disconnect */ + PPPDEBUG(LOG_DEBUG, ("ppp_close[%d]: kill_link -> lcp_close\n", pcb->netif->num)); + /* LCP soft close request. */ + lcp_close(pcb, "User request"); + return ERR_OK; +} + +/* + * Release the control block. + * + * This can only be called if PPP is in the dead phase. + * + * You must use ppp_close() before if you wish to terminate + * an established PPP session. + * + * Return 0 on success, an error code on failure. + */ +err_t ppp_free(ppp_pcb *pcb) { + err_t err; + LWIP_ASSERT_CORE_LOCKED(); + if (pcb->phase != PPP_PHASE_DEAD) { + return ERR_CONN; + } + + PPPDEBUG(LOG_DEBUG, ("ppp_free[%d]\n", pcb->netif->num)); + + netif_remove(pcb->netif); + + err = pcb->link_cb->free(pcb, pcb->link_ctx_cb); + + LWIP_MEMPOOL_FREE(PPP_PCB, pcb); + return err; +} + +/* Get and set parameters for the given connection. + * Return 0 on success, an error code on failure. */ +err_t +ppp_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg) +{ + LWIP_ASSERT_CORE_LOCKED(); + if (pcb == NULL) { + return ERR_VAL; + } + + switch(cmd) { + case PPPCTLG_UPSTATUS: /* Get the PPP up status. */ + if (!arg) { + goto fail; + } + *(int *)arg = (int)(0 +#if PPP_IPV4_SUPPORT + || pcb->if4_up +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT + || pcb->if6_up +#endif /* PPP_IPV6_SUPPORT */ + ); + return ERR_OK; + + case PPPCTLG_ERRCODE: /* Get the PPP error code. */ + if (!arg) { + goto fail; + } + *(int *)arg = (int)(pcb->err_code); + return ERR_OK; + + default: + goto fail; + } + +fail: + return ERR_VAL; +} + + +/**********************************/ +/*** LOCAL FUNCTION DEFINITIONS ***/ +/**********************************/ + +static void ppp_do_connect(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + + LWIP_ASSERT("pcb->phase == PPP_PHASE_DEAD || pcb->phase == PPP_PHASE_HOLDOFF", pcb->phase == PPP_PHASE_DEAD || pcb->phase == PPP_PHASE_HOLDOFF); + + new_phase(pcb, PPP_PHASE_INITIALIZE); + pcb->link_cb->connect(pcb, pcb->link_ctx_cb); +} + +/* + * ppp_netif_init_cb - netif init callback + */ +static err_t ppp_netif_init_cb(struct netif *netif) { + netif->name[0] = 'p'; + netif->name[1] = 'p'; +#if PPP_IPV4_SUPPORT + netif->output = ppp_netif_output_ip4; +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT + netif->output_ip6 = ppp_netif_output_ip6; +#endif /* PPP_IPV6_SUPPORT */ + netif->flags = NETIF_FLAG_UP; +#if LWIP_NETIF_HOSTNAME + /* @todo: Initialize interface hostname */ + /* netif_set_hostname(netif, "lwip"); */ +#endif /* LWIP_NETIF_HOSTNAME */ + return ERR_OK; +} + +#if PPP_IPV4_SUPPORT +/* + * Send an IPv4 packet on the given connection. + */ +static err_t ppp_netif_output_ip4(struct netif *netif, struct pbuf *pb, const ip4_addr_t *ipaddr) { + LWIP_UNUSED_ARG(ipaddr); + return ppp_netif_output(netif, pb, PPP_IP); +} +#endif /* PPP_IPV4_SUPPORT */ + +#if PPP_IPV6_SUPPORT +/* + * Send an IPv6 packet on the given connection. + */ +static err_t ppp_netif_output_ip6(struct netif *netif, struct pbuf *pb, const ip6_addr_t *ipaddr) { + LWIP_UNUSED_ARG(ipaddr); + return ppp_netif_output(netif, pb, PPP_IPV6); +} +#endif /* PPP_IPV6_SUPPORT */ + +static err_t ppp_netif_output(struct netif *netif, struct pbuf *pb, u16_t protocol) { + ppp_pcb *pcb = (ppp_pcb*)netif->state; + err_t err; + struct pbuf *fpb = NULL; + + /* Check that the link is up. */ + if (0 +#if PPP_IPV4_SUPPORT + || (protocol == PPP_IP && !pcb->if4_up) +#endif /* PPP_IPV4_SUPPORT */ +#if PPP_IPV6_SUPPORT + || (protocol == PPP_IPV6 && !pcb->if6_up) +#endif /* PPP_IPV6_SUPPORT */ + ) { + PPPDEBUG(LOG_ERR, ("ppp_netif_output[%d]: link not up\n", pcb->netif->num)); + goto err_rte_drop; + } + +#if MPPE_SUPPORT + /* If MPPE is required, refuse any IP packet until we are able to crypt them. */ + if (pcb->settings.require_mppe && pcb->ccp_transmit_method != CI_MPPE) { + PPPDEBUG(LOG_ERR, ("ppp_netif_output[%d]: MPPE required, not up\n", pcb->netif->num)); + goto err_rte_drop; + } +#endif /* MPPE_SUPPORT */ + +#if VJ_SUPPORT + /* + * Attempt Van Jacobson header compression if VJ is configured and + * this is an IP packet. + */ + if (protocol == PPP_IP && pcb->vj_enabled) { + switch (vj_compress_tcp(&pcb->vj_comp, &pb)) { + case TYPE_IP: + /* No change... + protocol = PPP_IP; */ + break; + case TYPE_COMPRESSED_TCP: + /* vj_compress_tcp() returns a new allocated pbuf, indicate we should free + * our duplicated pbuf later */ + fpb = pb; + protocol = PPP_VJC_COMP; + break; + case TYPE_UNCOMPRESSED_TCP: + /* vj_compress_tcp() returns a new allocated pbuf, indicate we should free + * our duplicated pbuf later */ + fpb = pb; + protocol = PPP_VJC_UNCOMP; + break; + default: + PPPDEBUG(LOG_WARNING, ("ppp_netif_output[%d]: bad IP packet\n", pcb->netif->num)); + LINK_STATS_INC(link.proterr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(pcb->netif, ifoutdiscards); + return ERR_VAL; + } + } +#endif /* VJ_SUPPORT */ + +#if CCP_SUPPORT + switch (pcb->ccp_transmit_method) { + case 0: + break; /* Don't compress */ +#if MPPE_SUPPORT + case CI_MPPE: + if ((err = mppe_compress(pcb, &pcb->mppe_comp, &pb, protocol)) != ERR_OK) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); + goto err; + } + /* if VJ compressor returned a new allocated pbuf, free it */ + if (fpb) { + pbuf_free(fpb); + } + /* mppe_compress() returns a new allocated pbuf, indicate we should free + * our duplicated pbuf later */ + fpb = pb; + protocol = PPP_COMP; + break; +#endif /* MPPE_SUPPORT */ + default: + PPPDEBUG(LOG_ERR, ("ppp_netif_output[%d]: bad CCP transmit method\n", pcb->netif->num)); + goto err_rte_drop; /* Cannot really happen, we only negotiate what we are able to do */ + } +#endif /* CCP_SUPPORT */ + + err = pcb->link_cb->netif_output(pcb, pcb->link_ctx_cb, pb, protocol); + goto err; + +err_rte_drop: + err = ERR_RTE; + LINK_STATS_INC(link.rterr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(netif, ifoutdiscards); +err: + if (fpb) { + pbuf_free(fpb); + } + return err; +} + +/************************************/ +/*** PRIVATE FUNCTION DEFINITIONS ***/ +/************************************/ + +/* Initialize the PPP subsystem. */ +int ppp_init(void) +{ +#if PPPOS_SUPPORT + LWIP_MEMPOOL_INIT(PPPOS_PCB); +#endif +#if PPPOE_SUPPORT + LWIP_MEMPOOL_INIT(PPPOE_IF); +#endif +#if PPPOL2TP_SUPPORT + LWIP_MEMPOOL_INIT(PPPOL2TP_PCB); +#endif +#if LWIP_PPP_API && LWIP_MPU_COMPATIBLE + LWIP_MEMPOOL_INIT(PPPAPI_MSG); +#endif + + LWIP_MEMPOOL_INIT(PPP_PCB); + + /* + * Initialize magic number generator now so that protocols may + * use magic numbers in initialization. + */ + magic_init(); + + return 0; +} + +/* + * Create a new PPP control block. + * + * This initializes the PPP control block but does not + * attempt to negotiate the LCP session. + * + * Return a new PPP connection control block pointer + * on success or a null pointer on failure. + */ +ppp_pcb *ppp_new(struct netif *pppif, const struct link_callbacks *callbacks, void *link_ctx_cb, ppp_link_status_cb_fn link_status_cb, void *ctx_cb) { + ppp_pcb *pcb; + const struct protent *protp; + int i; + + /* PPP is single-threaded: without a callback, + * there is no way to know when the link is up. */ + if (link_status_cb == NULL) { + return NULL; + } + + pcb = (ppp_pcb*)LWIP_MEMPOOL_ALLOC(PPP_PCB); + if (pcb == NULL) { + return NULL; + } + + memset(pcb, 0, sizeof(ppp_pcb)); + + /* default configuration */ +#if PAP_SUPPORT + pcb->settings.pap_timeout_time = UPAP_DEFTIMEOUT; + pcb->settings.pap_max_transmits = UPAP_DEFTRANSMITS; +#if PPP_SERVER + pcb->settings.pap_req_timeout = UPAP_DEFREQTIME; +#endif /* PPP_SERVER */ +#endif /* PAP_SUPPORT */ + +#if CHAP_SUPPORT + pcb->settings.chap_timeout_time = CHAP_DEFTIMEOUT; + pcb->settings.chap_max_transmits = CHAP_DEFTRANSMITS; +#if PPP_SERVER + pcb->settings.chap_rechallenge_time = CHAP_DEFRECHALLENGETIME; +#endif /* PPP_SERVER */ +#endif /* CHAP_SUPPPORT */ + +#if EAP_SUPPORT + pcb->settings.eap_req_time = EAP_DEFREQTIME; + pcb->settings.eap_allow_req = EAP_DEFALLOWREQ; +#if PPP_SERVER + pcb->settings.eap_timeout_time = EAP_DEFTIMEOUT; + pcb->settings.eap_max_transmits = EAP_DEFTRANSMITS; +#endif /* PPP_SERVER */ +#endif /* EAP_SUPPORT */ + + pcb->settings.lcp_loopbackfail = LCP_DEFLOOPBACKFAIL; + pcb->settings.lcp_echo_interval = LCP_ECHOINTERVAL; + pcb->settings.lcp_echo_fails = LCP_MAXECHOFAILS; + + pcb->settings.fsm_timeout_time = FSM_DEFTIMEOUT; + pcb->settings.fsm_max_conf_req_transmits = FSM_DEFMAXCONFREQS; + pcb->settings.fsm_max_term_transmits = FSM_DEFMAXTERMREQS; + pcb->settings.fsm_max_nak_loops = FSM_DEFMAXNAKLOOPS; + + pcb->netif = pppif; + MIB2_INIT_NETIF(pppif, snmp_ifType_ppp, 0); + if (!netif_add(pcb->netif, +#if LWIP_IPV4 + IP4_ADDR_ANY4, IP4_ADDR_BROADCAST, IP4_ADDR_ANY4, +#endif /* LWIP_IPV4 */ + (void *)pcb, ppp_netif_init_cb, NULL)) { + LWIP_MEMPOOL_FREE(PPP_PCB, pcb); + PPPDEBUG(LOG_ERR, ("ppp_new: netif_add failed\n")); + return NULL; + } + + pcb->link_cb = callbacks; + pcb->link_ctx_cb = link_ctx_cb; + pcb->link_status_cb = link_status_cb; + pcb->ctx_cb = ctx_cb; + + /* + * Initialize each protocol. + */ + for (i = 0; (protp = protocols[i]) != NULL; ++i) { + (*protp->init)(pcb); + } + + new_phase(pcb, PPP_PHASE_DEAD); + return pcb; +} + +/** Initiate LCP open request */ +void ppp_start(ppp_pcb *pcb) { + PPPDEBUG(LOG_DEBUG, ("ppp_start[%d]\n", pcb->netif->num)); + + /* Clean data not taken care by anything else, mostly shared data. */ +#if PPP_STATS_SUPPORT + link_stats_valid = 0; +#endif /* PPP_STATS_SUPPORT */ +#if MPPE_SUPPORT + pcb->mppe_keys_set = 0; + memset(&pcb->mppe_comp, 0, sizeof(pcb->mppe_comp)); + memset(&pcb->mppe_decomp, 0, sizeof(pcb->mppe_decomp)); +#endif /* MPPE_SUPPORT */ +#if VJ_SUPPORT + vj_compress_init(&pcb->vj_comp); +#endif /* VJ_SUPPORT */ + + /* Start protocol */ + new_phase(pcb, PPP_PHASE_ESTABLISH); + lcp_open(pcb); + lcp_lowerup(pcb); + PPPDEBUG(LOG_DEBUG, ("ppp_start[%d]: finished\n", pcb->netif->num)); +} + +/** Called when link failed to setup */ +void ppp_link_failed(ppp_pcb *pcb) { + PPPDEBUG(LOG_DEBUG, ("ppp_link_failed[%d]\n", pcb->netif->num)); + new_phase(pcb, PPP_PHASE_DEAD); + pcb->err_code = PPPERR_OPEN; + pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb); +} + +/** Called when link is normally down (i.e. it was asked to end) */ +void ppp_link_end(ppp_pcb *pcb) { + PPPDEBUG(LOG_DEBUG, ("ppp_link_end[%d]\n", pcb->netif->num)); + new_phase(pcb, PPP_PHASE_DEAD); + if (pcb->err_code == PPPERR_NONE) { + pcb->err_code = PPPERR_CONNECT; + } + pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb); +} + +/* + * Pass the processed input packet to the appropriate handler. + * This function and all handlers run in the context of the tcpip_thread + */ +void ppp_input(ppp_pcb *pcb, struct pbuf *pb) { + u16_t protocol; +#if PPP_DEBUG && PPP_PROTOCOLNAME + const char *pname; +#endif /* PPP_DEBUG && PPP_PROTOCOLNAME */ + + magic_randomize(); + + if (pb->len < 2) { + PPPDEBUG(LOG_ERR, ("ppp_input[%d]: packet too short\n", pcb->netif->num)); + goto drop; + } + protocol = (((u8_t *)pb->payload)[0] << 8) | ((u8_t*)pb->payload)[1]; + +#if PRINTPKT_SUPPORT + ppp_dump_packet(pcb, "rcvd", (unsigned char *)pb->payload, pb->len); +#endif /* PRINTPKT_SUPPORT */ + + pbuf_remove_header(pb, sizeof(protocol)); + + LINK_STATS_INC(link.recv); + MIB2_STATS_NETIF_INC(pcb->netif, ifinucastpkts); + MIB2_STATS_NETIF_ADD(pcb->netif, ifinoctets, pb->tot_len); + + /* + * Toss all non-LCP packets unless LCP is OPEN. + */ + if (protocol != PPP_LCP && pcb->lcp_fsm.state != PPP_FSM_OPENED) { + ppp_dbglog("Discarded non-LCP packet when LCP not open"); + goto drop; + } + + /* + * Until we get past the authentication phase, toss all packets + * except LCP, LQR and authentication packets. + */ + if (pcb->phase <= PPP_PHASE_AUTHENTICATE + && !(protocol == PPP_LCP +#if LQR_SUPPORT + || protocol == PPP_LQR +#endif /* LQR_SUPPORT */ +#if PAP_SUPPORT + || protocol == PPP_PAP +#endif /* PAP_SUPPORT */ +#if CHAP_SUPPORT + || protocol == PPP_CHAP +#endif /* CHAP_SUPPORT */ +#if EAP_SUPPORT + || protocol == PPP_EAP +#endif /* EAP_SUPPORT */ + )) { + ppp_dbglog("discarding proto 0x%x in phase %d", protocol, pcb->phase); + goto drop; + } + +#if CCP_SUPPORT +#if MPPE_SUPPORT + /* + * MPPE is required and unencrypted data has arrived (this + * should never happen!). We should probably drop the link if + * the protocol is in the range of what should be encrypted. + * At the least, we drop this packet. + */ + if (pcb->settings.require_mppe && protocol != PPP_COMP && protocol < 0x8000) { + PPPDEBUG(LOG_ERR, ("ppp_input[%d]: MPPE required, received unencrypted data!\n", pcb->netif->num)); + goto drop; + } +#endif /* MPPE_SUPPORT */ + + if (protocol == PPP_COMP) { + u8_t *pl; + + switch (pcb->ccp_receive_method) { +#if MPPE_SUPPORT + case CI_MPPE: + if (mppe_decompress(pcb, &pcb->mppe_decomp, &pb) != ERR_OK) { + goto drop; + } + break; +#endif /* MPPE_SUPPORT */ + default: + PPPDEBUG(LOG_ERR, ("ppp_input[%d]: bad CCP receive method\n", pcb->netif->num)); + goto drop; /* Cannot really happen, we only negotiate what we are able to do */ + } + + /* Assume no PFC */ + if (pb->len < 2) { + goto drop; + } + + /* Extract and hide protocol (do PFC decompression if necessary) */ + pl = (u8_t*)pb->payload; + if (pl[0] & 0x01) { + protocol = pl[0]; + pbuf_remove_header(pb, 1); + } else { + protocol = (pl[0] << 8) | pl[1]; + pbuf_remove_header(pb, 2); + } + } +#endif /* CCP_SUPPORT */ + + switch(protocol) { + +#if PPP_IPV4_SUPPORT + case PPP_IP: /* Internet Protocol */ + PPPDEBUG(LOG_INFO, ("ppp_input[%d]: ip in pbuf len=%d\n", pcb->netif->num, pb->tot_len)); + ip4_input(pb, pcb->netif); + return; +#endif /* PPP_IPV4_SUPPORT */ + +#if PPP_IPV6_SUPPORT + case PPP_IPV6: /* Internet Protocol Version 6 */ + PPPDEBUG(LOG_INFO, ("ppp_input[%d]: ip6 in pbuf len=%d\n", pcb->netif->num, pb->tot_len)); + ip6_input(pb, pcb->netif); + return; +#endif /* PPP_IPV6_SUPPORT */ + +#if VJ_SUPPORT + case PPP_VJC_COMP: /* VJ compressed TCP */ + /* + * Clip off the VJ header and prepend the rebuilt TCP/IP header and + * pass the result to IP. + */ + PPPDEBUG(LOG_INFO, ("ppp_input[%d]: vj_comp in pbuf len=%d\n", pcb->netif->num, pb->tot_len)); + if (pcb->vj_enabled && vj_uncompress_tcp(&pb, &pcb->vj_comp) >= 0) { + ip4_input(pb, pcb->netif); + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG(LOG_WARNING, ("ppp_input[%d]: Dropping VJ compressed\n", pcb->netif->num)); + break; + + case PPP_VJC_UNCOMP: /* VJ uncompressed TCP */ + /* + * Process the TCP/IP header for VJ header compression and then pass + * the packet to IP. + */ + PPPDEBUG(LOG_INFO, ("ppp_input[%d]: vj_un in pbuf len=%d\n", pcb->netif->num, pb->tot_len)); + if (pcb->vj_enabled && vj_uncompress_uncomp(pb, &pcb->vj_comp) >= 0) { + ip4_input(pb, pcb->netif); + return; + } + /* Something's wrong so drop it. */ + PPPDEBUG(LOG_WARNING, ("ppp_input[%d]: Dropping VJ uncompressed\n", pcb->netif->num)); + break; +#endif /* VJ_SUPPORT */ + + default: { + int i; + const struct protent *protp; + + /* + * Upcall the proper protocol input routine. + */ + for (i = 0; (protp = protocols[i]) != NULL; ++i) { + if (protp->protocol == protocol) { + pb = pbuf_coalesce(pb, PBUF_RAW); + (*protp->input)(pcb, (u8_t*)pb->payload, pb->len); + goto out; + } +#if 0 /* UNUSED + * + * This is actually a (hacked?) way for the Linux kernel to pass a data + * packet to pppd. pppd in normal condition only do signaling + * (LCP, PAP, CHAP, IPCP, ...) and does not handle any data packet at all. + * + * We don't even need this interface, which is only there because of PPP + * interface limitation between Linux kernel and pppd. For MPPE, which uses + * CCP to negotiate although it is not really a (de)compressor, we added + * ccp_resetrequest() in CCP and MPPE input data flow is calling either + * ccp_resetrequest() or lcp_close() if the issue is, respectively, non-fatal + * or fatal, this is what ccp_datainput() really do. + */ + if (protocol == (protp->protocol & ~0x8000) + && protp->datainput != NULL) { + (*protp->datainput)(pcb, pb->payload, pb->len); + goto out; + } +#endif /* UNUSED */ + } + +#if PPP_DEBUG +#if PPP_PROTOCOLNAME + pname = protocol_name(protocol); + if (pname != NULL) { + ppp_warn("Unsupported protocol '%s' (0x%x) received", pname, protocol); + } else +#endif /* PPP_PROTOCOLNAME */ + ppp_warn("Unsupported protocol 0x%x received", protocol); +#endif /* PPP_DEBUG */ + if (pbuf_add_header(pb, sizeof(protocol))) { + PPPDEBUG(LOG_WARNING, ("ppp_input[%d]: Dropping (pbuf_add_header failed)\n", pcb->netif->num)); + goto drop; + } + lcp_sprotrej(pcb, (u8_t*)pb->payload, pb->len); + } + break; + } + +drop: + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(pcb->netif, ifindiscards); + +out: + pbuf_free(pb); +} + +/* + * Write a pbuf to a ppp link, only used from PPP functions + * to send PPP packets. + * + * IPv4 and IPv6 packets from lwIP are sent, respectively, + * with ppp_netif_output_ip4() and ppp_netif_output_ip6() + * functions (which are callbacks of the netif PPP interface). + */ +err_t ppp_write(ppp_pcb *pcb, struct pbuf *p) { +#if PRINTPKT_SUPPORT + ppp_dump_packet(pcb, "sent", (unsigned char *)p->payload+2, p->len-2); +#endif /* PRINTPKT_SUPPORT */ + return pcb->link_cb->write(pcb, pcb->link_ctx_cb, p); +} + +void ppp_link_terminated(ppp_pcb *pcb) { + PPPDEBUG(LOG_DEBUG, ("ppp_link_terminated[%d]\n", pcb->netif->num)); + pcb->link_cb->disconnect(pcb, pcb->link_ctx_cb); + PPPDEBUG(LOG_DEBUG, ("ppp_link_terminated[%d]: finished.\n", pcb->netif->num)); +} + + +/************************************************************************ + * Functions called by various PPP subsystems to configure + * the PPP interface or change the PPP phase. + */ + +/* + * new_phase - signal the start of a new phase of pppd's operation. + */ +void new_phase(ppp_pcb *pcb, int p) { + pcb->phase = p; + PPPDEBUG(LOG_DEBUG, ("ppp phase changed[%d]: phase=%d\n", pcb->netif->num, pcb->phase)); +#if PPP_NOTIFY_PHASE + if (pcb->notify_phase_cb != NULL) { + pcb->notify_phase_cb(pcb, p, pcb->ctx_cb); + } +#endif /* PPP_NOTIFY_PHASE */ +} + +/* + * ppp_send_config - configure the transmit-side characteristics of + * the ppp interface. + */ +int ppp_send_config(ppp_pcb *pcb, int mtu, u32_t accm, int pcomp, int accomp) { + LWIP_UNUSED_ARG(mtu); + /* pcb->mtu = mtu; -- set correctly with netif_set_mtu */ + + if (pcb->link_cb->send_config) { + pcb->link_cb->send_config(pcb, pcb->link_ctx_cb, accm, pcomp, accomp); + } + + PPPDEBUG(LOG_INFO, ("ppp_send_config[%d]\n", pcb->netif->num) ); + return 0; +} + +/* + * ppp_recv_config - configure the receive-side characteristics of + * the ppp interface. + */ +int ppp_recv_config(ppp_pcb *pcb, int mru, u32_t accm, int pcomp, int accomp) { + LWIP_UNUSED_ARG(mru); + + if (pcb->link_cb->recv_config) { + pcb->link_cb->recv_config(pcb, pcb->link_ctx_cb, accm, pcomp, accomp); + } + + PPPDEBUG(LOG_INFO, ("ppp_recv_config[%d]\n", pcb->netif->num)); + return 0; +} + +#if PPP_IPV4_SUPPORT +/* + * sifaddr - Config the interface IP addresses and netmask. + */ +int sifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr, u32_t netmask) { + ip4_addr_t ip, nm, gw; + + ip4_addr_set_u32(&ip, our_adr); + ip4_addr_set_u32(&nm, netmask); + ip4_addr_set_u32(&gw, his_adr); + netif_set_addr(pcb->netif, &ip, &nm, &gw); + return 1; +} + +/******************************************************************** + * + * cifaddr - Clear the interface IP addresses, and delete routes + * through the interface if possible. + */ +int cifaddr(ppp_pcb *pcb, u32_t our_adr, u32_t his_adr) { + LWIP_UNUSED_ARG(our_adr); + LWIP_UNUSED_ARG(his_adr); + + netif_set_addr(pcb->netif, IP4_ADDR_ANY4, IP4_ADDR_BROADCAST, IP4_ADDR_ANY4); + return 1; +} + +#if 0 /* UNUSED - PROXY ARP */ +/******************************************************************** + * + * sifproxyarp - Make a proxy ARP entry for the peer. + */ + +int sifproxyarp(ppp_pcb *pcb, u32_t his_adr) { + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(his_adr); + return 0; +} + +/******************************************************************** + * + * cifproxyarp - Delete the proxy ARP entry for the peer. + */ + +int cifproxyarp(ppp_pcb *pcb, u32_t his_adr) { + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(his_adr); + return 0; +} +#endif /* UNUSED - PROXY ARP */ + +#if LWIP_DNS +/* + * sdns - Config the DNS servers + */ +int sdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2) { + ip_addr_t ns; + LWIP_UNUSED_ARG(pcb); + + ip_addr_set_ip4_u32_val(ns, ns1); + dns_setserver(0, &ns); + ip_addr_set_ip4_u32_val(ns, ns2); + dns_setserver(1, &ns); + return 1; +} + +/******************************************************************** + * + * cdns - Clear the DNS servers + */ +int cdns(ppp_pcb *pcb, u32_t ns1, u32_t ns2) { + const ip_addr_t *nsa; + ip_addr_t nsb; + LWIP_UNUSED_ARG(pcb); + + nsa = dns_getserver(0); + ip_addr_set_ip4_u32_val(nsb, ns1); + if (ip_addr_cmp(nsa, &nsb)) { + dns_setserver(0, IP_ADDR_ANY); + } + nsa = dns_getserver(1); + ip_addr_set_ip4_u32_val(nsb, ns2); + if (ip_addr_cmp(nsa, &nsb)) { + dns_setserver(1, IP_ADDR_ANY); + } + return 1; +} +#endif /* LWIP_DNS */ + +#if VJ_SUPPORT +/******************************************************************** + * + * sifvjcomp - config tcp header compression + */ +int sifvjcomp(ppp_pcb *pcb, int vjcomp, int cidcomp, int maxcid) { + pcb->vj_enabled = vjcomp; + pcb->vj_comp.compressSlot = cidcomp; + pcb->vj_comp.maxSlotIndex = maxcid; + PPPDEBUG(LOG_INFO, ("sifvjcomp[%d]: VJ compress enable=%d slot=%d max slot=%d\n", + pcb->netif->num, vjcomp, cidcomp, maxcid)); + return 0; +} +#endif /* VJ_SUPPORT */ + +/* + * sifup - Config the interface up and enable IP packets to pass. + */ +int sifup(ppp_pcb *pcb) { + pcb->if4_up = 1; + pcb->err_code = PPPERR_NONE; + netif_set_link_up(pcb->netif); + + PPPDEBUG(LOG_DEBUG, ("sifup[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code)); + pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb); + return 1; +} + +/******************************************************************** + * + * sifdown - Disable the indicated protocol and config the interface + * down if there are no remaining protocols. + */ +int sifdown(ppp_pcb *pcb) { + + pcb->if4_up = 0; + + if (1 +#if PPP_IPV6_SUPPORT + /* set the interface down if IPv6 is down as well */ + && !pcb->if6_up +#endif /* PPP_IPV6_SUPPORT */ + ) { + /* make sure the netif link callback is called */ + netif_set_link_down(pcb->netif); + } + PPPDEBUG(LOG_DEBUG, ("sifdown[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code)); + return 1; +} + +/******************************************************************** + * + * Return user specified netmask, modified by any mask we might determine + * for address `addr' (in network byte order). + * Here we scan through the system's list of interfaces, looking for + * any non-point-to-point interfaces which might appear to be on the same + * network as `addr'. If we find any, we OR in their netmask to the + * user-specified netmask. + */ +u32_t get_mask(u32_t addr) { +#if 0 + u32_t mask, nmask; + + addr = lwip_htonl(addr); + if (IP_CLASSA(addr)) { /* determine network mask for address class */ + nmask = IP_CLASSA_NET; + } else if (IP_CLASSB(addr)) { + nmask = IP_CLASSB_NET; + } else { + nmask = IP_CLASSC_NET; + } + + /* class D nets are disallowed by bad_ip_adrs */ + mask = PP_HTONL(0xffffff00UL) | lwip_htonl(nmask); + + /* XXX + * Scan through the system's network interfaces. + * Get each netmask and OR them into our mask. + */ + /* return mask; */ + return mask; +#endif /* 0 */ + LWIP_UNUSED_ARG(addr); + return IPADDR_BROADCAST; +} +#endif /* PPP_IPV4_SUPPORT */ + +#if PPP_IPV6_SUPPORT +#define IN6_LLADDR_FROM_EUI64(ip6, eui64) do { \ + ip6.addr[0] = PP_HTONL(0xfe800000); \ + ip6.addr[1] = 0; \ + eui64_copy(eui64, ip6.addr[2]); \ + } while (0) + +/******************************************************************** + * + * sif6addr - Config the interface with an IPv6 link-local address + */ +int sif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64) { + ip6_addr_t ip6; + LWIP_UNUSED_ARG(his_eui64); + + IN6_LLADDR_FROM_EUI64(ip6, our_eui64); + netif_ip6_addr_set(pcb->netif, 0, &ip6); + netif_ip6_addr_set_state(pcb->netif, 0, IP6_ADDR_PREFERRED); + /* FIXME: should we add an IPv6 static neighbor using his_eui64 ? */ + return 1; +} + +/******************************************************************** + * + * cif6addr - Remove IPv6 address from interface + */ +int cif6addr(ppp_pcb *pcb, eui64_t our_eui64, eui64_t his_eui64) { + LWIP_UNUSED_ARG(our_eui64); + LWIP_UNUSED_ARG(his_eui64); + + netif_ip6_addr_set_state(pcb->netif, 0, IP6_ADDR_INVALID); + netif_ip6_addr_set(pcb->netif, 0, IP6_ADDR_ANY6); + return 1; +} + +/* + * sif6up - Config the interface up and enable IPv6 packets to pass. + */ +int sif6up(ppp_pcb *pcb) { + + pcb->if6_up = 1; + pcb->err_code = PPPERR_NONE; + netif_set_link_up(pcb->netif); + + PPPDEBUG(LOG_DEBUG, ("sif6up[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code)); + pcb->link_status_cb(pcb, pcb->err_code, pcb->ctx_cb); + return 1; +} + +/******************************************************************** + * + * sif6down - Disable the indicated protocol and config the interface + * down if there are no remaining protocols. + */ +int sif6down(ppp_pcb *pcb) { + + pcb->if6_up = 0; + + if (1 +#if PPP_IPV4_SUPPORT + /* set the interface down if IPv4 is down as well */ + && !pcb->if4_up +#endif /* PPP_IPV4_SUPPORT */ + ) { + /* make sure the netif link callback is called */ + netif_set_link_down(pcb->netif); + } + PPPDEBUG(LOG_DEBUG, ("sif6down[%d]: err_code=%d\n", pcb->netif->num, pcb->err_code)); + return 1; +} +#endif /* PPP_IPV6_SUPPORT */ + +#if DEMAND_SUPPORT +/* + * sifnpmode - Set the mode for handling packets for a given NP. + */ +int sifnpmode(ppp_pcb *pcb, int proto, enum NPmode mode) { + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(proto); + LWIP_UNUSED_ARG(mode); + return 0; +} +#endif /* DEMAND_SUPPORT */ + +/* + * netif_set_mtu - set the MTU on the PPP network interface. + */ +void netif_set_mtu(ppp_pcb *pcb, int mtu) { + + pcb->netif->mtu = mtu; + PPPDEBUG(LOG_INFO, ("netif_set_mtu[%d]: mtu=%d\n", pcb->netif->num, mtu)); +} + +/* + * netif_get_mtu - get PPP interface MTU + */ +int netif_get_mtu(ppp_pcb *pcb) { + + return pcb->netif->mtu; +} + +#if CCP_SUPPORT +#if 0 /* unused */ +/* + * ccp_test - whether a given compression method is acceptable for use. + */ +int +ccp_test(ppp_pcb *pcb, u_char *opt_ptr, int opt_len, int for_transmit) +{ + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(opt_ptr); + LWIP_UNUSED_ARG(opt_len); + LWIP_UNUSED_ARG(for_transmit); + return -1; +} +#endif /* unused */ + +/* + * ccp_set - inform about the current state of CCP. + */ +void +ccp_set(ppp_pcb *pcb, u8_t isopen, u8_t isup, u8_t receive_method, u8_t transmit_method) +{ + LWIP_UNUSED_ARG(isopen); + LWIP_UNUSED_ARG(isup); + pcb->ccp_receive_method = receive_method; + pcb->ccp_transmit_method = transmit_method; + PPPDEBUG(LOG_DEBUG, ("ccp_set[%d]: is_open=%d, is_up=%d, receive_method=%u, transmit_method=%u\n", + pcb->netif->num, isopen, isup, receive_method, transmit_method)); +} + +void +ccp_reset_comp(ppp_pcb *pcb) +{ + switch (pcb->ccp_transmit_method) { +#if MPPE_SUPPORT + case CI_MPPE: + mppe_comp_reset(pcb, &pcb->mppe_comp); + break; +#endif /* MPPE_SUPPORT */ + default: + break; + } +} + +void +ccp_reset_decomp(ppp_pcb *pcb) +{ + switch (pcb->ccp_receive_method) { +#if MPPE_SUPPORT + case CI_MPPE: + mppe_decomp_reset(pcb, &pcb->mppe_decomp); + break; +#endif /* MPPE_SUPPORT */ + default: + break; + } +} + +#if 0 /* unused */ +/* + * ccp_fatal_error - returns 1 if decompression was disabled as a + * result of an error detected after decompression of a packet, + * 0 otherwise. This is necessary because of patent nonsense. + */ +int +ccp_fatal_error(ppp_pcb *pcb) +{ + LWIP_UNUSED_ARG(pcb); + return 1; +} +#endif /* unused */ +#endif /* CCP_SUPPORT */ + +#if PPP_IDLETIMELIMIT +/******************************************************************** + * + * get_idle_time - return how long the link has been idle. + */ +int get_idle_time(ppp_pcb *pcb, struct ppp_idle *ip) { + /* FIXME: add idle time support and make it optional */ + LWIP_UNUSED_ARG(pcb); + LWIP_UNUSED_ARG(ip); + return 1; +} +#endif /* PPP_IDLETIMELIMIT */ + +#if DEMAND_SUPPORT +/******************************************************************** + * + * get_loop_output - get outgoing packets from the ppp device, + * and detect when we want to bring the real link up. + * Return value is 1 if we need to bring up the link, 0 otherwise. + */ +int get_loop_output(void) { + return 0; +} +#endif /* DEMAND_SUPPORT */ + +#if PPP_PROTOCOLNAME +/* List of protocol names, to make our messages a little more informative. */ +struct protocol_list { + u_short proto; + const char *name; +} const protocol_list[] = { + { 0x21, "IP" }, + { 0x23, "OSI Network Layer" }, + { 0x25, "Xerox NS IDP" }, + { 0x27, "DECnet Phase IV" }, + { 0x29, "Appletalk" }, + { 0x2b, "Novell IPX" }, + { 0x2d, "VJ compressed TCP/IP" }, + { 0x2f, "VJ uncompressed TCP/IP" }, + { 0x31, "Bridging PDU" }, + { 0x33, "Stream Protocol ST-II" }, + { 0x35, "Banyan Vines" }, + { 0x39, "AppleTalk EDDP" }, + { 0x3b, "AppleTalk SmartBuffered" }, + { 0x3d, "Multi-Link" }, + { 0x3f, "NETBIOS Framing" }, + { 0x41, "Cisco Systems" }, + { 0x43, "Ascom Timeplex" }, + { 0x45, "Fujitsu Link Backup and Load Balancing (LBLB)" }, + { 0x47, "DCA Remote Lan" }, + { 0x49, "Serial Data Transport Protocol (PPP-SDTP)" }, + { 0x4b, "SNA over 802.2" }, + { 0x4d, "SNA" }, + { 0x4f, "IP6 Header Compression" }, + { 0x51, "KNX Bridging Data" }, + { 0x53, "Encryption" }, + { 0x55, "Individual Link Encryption" }, + { 0x57, "IPv6" }, + { 0x59, "PPP Muxing" }, + { 0x5b, "Vendor-Specific Network Protocol" }, + { 0x61, "RTP IPHC Full Header" }, + { 0x63, "RTP IPHC Compressed TCP" }, + { 0x65, "RTP IPHC Compressed non-TCP" }, + { 0x67, "RTP IPHC Compressed UDP 8" }, + { 0x69, "RTP IPHC Compressed RTP 8" }, + { 0x6f, "Stampede Bridging" }, + { 0x73, "MP+" }, + { 0xc1, "NTCITS IPI" }, + { 0xfb, "single-link compression" }, + { 0xfd, "Compressed Datagram" }, + { 0x0201, "802.1d Hello Packets" }, + { 0x0203, "IBM Source Routing BPDU" }, + { 0x0205, "DEC LANBridge100 Spanning Tree" }, + { 0x0207, "Cisco Discovery Protocol" }, + { 0x0209, "Netcs Twin Routing" }, + { 0x020b, "STP - Scheduled Transfer Protocol" }, + { 0x020d, "EDP - Extreme Discovery Protocol" }, + { 0x0211, "Optical Supervisory Channel Protocol" }, + { 0x0213, "Optical Supervisory Channel Protocol" }, + { 0x0231, "Luxcom" }, + { 0x0233, "Sigma Network Systems" }, + { 0x0235, "Apple Client Server Protocol" }, + { 0x0281, "MPLS Unicast" }, + { 0x0283, "MPLS Multicast" }, + { 0x0285, "IEEE p1284.4 standard - data packets" }, + { 0x0287, "ETSI TETRA Network Protocol Type 1" }, + { 0x0289, "Multichannel Flow Treatment Protocol" }, + { 0x2063, "RTP IPHC Compressed TCP No Delta" }, + { 0x2065, "RTP IPHC Context State" }, + { 0x2067, "RTP IPHC Compressed UDP 16" }, + { 0x2069, "RTP IPHC Compressed RTP 16" }, + { 0x4001, "Cray Communications Control Protocol" }, + { 0x4003, "CDPD Mobile Network Registration Protocol" }, + { 0x4005, "Expand accelerator protocol" }, + { 0x4007, "ODSICP NCP" }, + { 0x4009, "DOCSIS DLL" }, + { 0x400B, "Cetacean Network Detection Protocol" }, + { 0x4021, "Stacker LZS" }, + { 0x4023, "RefTek Protocol" }, + { 0x4025, "Fibre Channel" }, + { 0x4027, "EMIT Protocols" }, + { 0x405b, "Vendor-Specific Protocol (VSP)" }, + { 0x8021, "Internet Protocol Control Protocol" }, + { 0x8023, "OSI Network Layer Control Protocol" }, + { 0x8025, "Xerox NS IDP Control Protocol" }, + { 0x8027, "DECnet Phase IV Control Protocol" }, + { 0x8029, "Appletalk Control Protocol" }, + { 0x802b, "Novell IPX Control Protocol" }, + { 0x8031, "Bridging NCP" }, + { 0x8033, "Stream Protocol Control Protocol" }, + { 0x8035, "Banyan Vines Control Protocol" }, + { 0x803d, "Multi-Link Control Protocol" }, + { 0x803f, "NETBIOS Framing Control Protocol" }, + { 0x8041, "Cisco Systems Control Protocol" }, + { 0x8043, "Ascom Timeplex" }, + { 0x8045, "Fujitsu LBLB Control Protocol" }, + { 0x8047, "DCA Remote Lan Network Control Protocol (RLNCP)" }, + { 0x8049, "Serial Data Control Protocol (PPP-SDCP)" }, + { 0x804b, "SNA over 802.2 Control Protocol" }, + { 0x804d, "SNA Control Protocol" }, + { 0x804f, "IP6 Header Compression Control Protocol" }, + { 0x8051, "KNX Bridging Control Protocol" }, + { 0x8053, "Encryption Control Protocol" }, + { 0x8055, "Individual Link Encryption Control Protocol" }, + { 0x8057, "IPv6 Control Protocol" }, + { 0x8059, "PPP Muxing Control Protocol" }, + { 0x805b, "Vendor-Specific Network Control Protocol (VSNCP)" }, + { 0x806f, "Stampede Bridging Control Protocol" }, + { 0x8073, "MP+ Control Protocol" }, + { 0x80c1, "NTCITS IPI Control Protocol" }, + { 0x80fb, "Single Link Compression Control Protocol" }, + { 0x80fd, "Compression Control Protocol" }, + { 0x8207, "Cisco Discovery Protocol Control" }, + { 0x8209, "Netcs Twin Routing" }, + { 0x820b, "STP - Control Protocol" }, + { 0x820d, "EDPCP - Extreme Discovery Protocol Ctrl Prtcl" }, + { 0x8235, "Apple Client Server Protocol Control" }, + { 0x8281, "MPLSCP" }, + { 0x8285, "IEEE p1284.4 standard - Protocol Control" }, + { 0x8287, "ETSI TETRA TNP1 Control Protocol" }, + { 0x8289, "Multichannel Flow Treatment Protocol" }, + { 0xc021, "Link Control Protocol" }, + { 0xc023, "Password Authentication Protocol" }, + { 0xc025, "Link Quality Report" }, + { 0xc027, "Shiva Password Authentication Protocol" }, + { 0xc029, "CallBack Control Protocol (CBCP)" }, + { 0xc02b, "BACP Bandwidth Allocation Control Protocol" }, + { 0xc02d, "BAP" }, + { 0xc05b, "Vendor-Specific Authentication Protocol (VSAP)" }, + { 0xc081, "Container Control Protocol" }, + { 0xc223, "Challenge Handshake Authentication Protocol" }, + { 0xc225, "RSA Authentication Protocol" }, + { 0xc227, "Extensible Authentication Protocol" }, + { 0xc229, "Mitsubishi Security Info Exch Ptcl (SIEP)" }, + { 0xc26f, "Stampede Bridging Authorization Protocol" }, + { 0xc281, "Proprietary Authentication Protocol" }, + { 0xc283, "Proprietary Authentication Protocol" }, + { 0xc481, "Proprietary Node ID Authentication Protocol" }, + { 0, NULL }, +}; + +/* + * protocol_name - find a name for a PPP protocol. + */ +const char * protocol_name(int proto) { + const struct protocol_list *lp; + + for (lp = protocol_list; lp->proto != 0; ++lp) { + if (proto == lp->proto) { + return lp->name; + } + } + return NULL; +} +#endif /* PPP_PROTOCOLNAME */ + +#if PPP_STATS_SUPPORT + +/* ---- Note on PPP Stats support ---- + * + * The one willing link stats support should add the get_ppp_stats() + * to fetch statistics from lwIP. + */ + +/* + * reset_link_stats - "reset" stats when link goes up. + */ +void reset_link_stats(int u) { + if (!get_ppp_stats(u, &old_link_stats)) { + return; + } + gettimeofday(&start_time, NULL); +} + +/* + * update_link_stats - get stats at link termination. + */ +void update_link_stats(int u) { + struct timeval now; + char numbuf[32]; + + if (!get_ppp_stats(u, &link_stats) || gettimeofday(&now, NULL) < 0) { + return; + } + link_connect_time = now.tv_sec - start_time.tv_sec; + link_stats_valid = 1; + + link_stats.bytes_in -= old_link_stats.bytes_in; + link_stats.bytes_out -= old_link_stats.bytes_out; + link_stats.pkts_in -= old_link_stats.pkts_in; + link_stats.pkts_out -= old_link_stats.pkts_out; +} + +void print_link_stats() { + /* + * Print connect time and statistics. + */ + if (link_stats_valid) { + int t = (link_connect_time + 5) / 6; /* 1/10ths of minutes */ + info("Connect time %d.%d minutes.", t/10, t%10); + info("Sent %u bytes, received %u bytes.", link_stats.bytes_out, link_stats.bytes_in); + link_stats_valid = 0; + } +} +#endif /* PPP_STATS_SUPPORT */ + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c new file mode 100644 index 0000000..947f7ba --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppapi.c @@ -0,0 +1,427 @@ +/** + * @file + * Point To Point Protocol Sequential API module + * + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "netif/ppp/ppp_opts.h" + +#if LWIP_PPP_API /* don't build if not configured for use in lwipopts.h */ + +#include "netif/ppp/pppapi.h" +#include "lwip/priv/tcpip_priv.h" +#include "netif/ppp/pppoe.h" +#include "netif/ppp/pppol2tp.h" +#include "netif/ppp/pppos.h" + +#if LWIP_MPU_COMPATIBLE +LWIP_MEMPOOL_DECLARE(PPPAPI_MSG, MEMP_NUM_PPP_API_MSG, sizeof(struct pppapi_msg), "PPPAPI_MSG") +#endif + +#define PPPAPI_VAR_REF(name) API_VAR_REF(name) +#define PPPAPI_VAR_DECLARE(name) API_VAR_DECLARE(struct pppapi_msg, name) +#define PPPAPI_VAR_ALLOC(name) API_VAR_ALLOC_POOL(struct pppapi_msg, PPPAPI_MSG, name, ERR_MEM) +#define PPPAPI_VAR_ALLOC_RETURN_NULL(name) API_VAR_ALLOC_POOL(struct pppapi_msg, PPPAPI_MSG, name, NULL) +#define PPPAPI_VAR_FREE(name) API_VAR_FREE_POOL(PPPAPI_MSG, name) + +/** + * Call ppp_set_default() inside the tcpip_thread context. + */ +static err_t +pppapi_do_ppp_set_default(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + ppp_set_default(msg->msg.ppp); + return ERR_OK; +} + +/** + * Call ppp_set_default() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +err_t +pppapi_set_default(ppp_pcb *pcb) +{ + err_t err; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = pcb; + err = tcpip_api_call(pppapi_do_ppp_set_default, &PPPAPI_VAR_REF(msg).call); + PPPAPI_VAR_FREE(msg); + return err; +} + + +#if PPP_NOTIFY_PHASE +/** + * Call ppp_set_notify_phase_callback() inside the tcpip_thread context. + */ +static err_t +pppapi_do_ppp_set_notify_phase_callback(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + ppp_set_notify_phase_callback(msg->msg.ppp, msg->msg.msg.setnotifyphasecb.notify_phase_cb); + return ERR_OK; +} + +/** + * Call ppp_set_notify_phase_callback() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +err_t +pppapi_set_notify_phase_callback(ppp_pcb *pcb, ppp_notify_phase_cb_fn notify_phase_cb) +{ + err_t err; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = pcb; + PPPAPI_VAR_REF(msg).msg.msg.setnotifyphasecb.notify_phase_cb = notify_phase_cb; + err = tcpip_api_call(pppapi_do_ppp_set_notify_phase_callback, &PPPAPI_VAR_REF(msg).call); + PPPAPI_VAR_FREE(msg); + return err; +} +#endif /* PPP_NOTIFY_PHASE */ + + +#if PPPOS_SUPPORT +/** + * Call pppos_create() inside the tcpip_thread context. + */ +static err_t +pppapi_do_pppos_create(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + msg->msg.ppp = pppos_create(msg->msg.msg.serialcreate.pppif, msg->msg.msg.serialcreate.output_cb, + msg->msg.msg.serialcreate.link_status_cb, msg->msg.msg.serialcreate.ctx_cb); + return ERR_OK; +} + +/** + * Call pppos_create() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +ppp_pcb* +pppapi_pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb) +{ + ppp_pcb* result; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC_RETURN_NULL(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = NULL; + PPPAPI_VAR_REF(msg).msg.msg.serialcreate.pppif = pppif; + PPPAPI_VAR_REF(msg).msg.msg.serialcreate.output_cb = output_cb; + PPPAPI_VAR_REF(msg).msg.msg.serialcreate.link_status_cb = link_status_cb; + PPPAPI_VAR_REF(msg).msg.msg.serialcreate.ctx_cb = ctx_cb; + tcpip_api_call(pppapi_do_pppos_create, &PPPAPI_VAR_REF(msg).call); + result = PPPAPI_VAR_REF(msg).msg.ppp; + PPPAPI_VAR_FREE(msg); + return result; +} +#endif /* PPPOS_SUPPORT */ + + +#if PPPOE_SUPPORT +/** + * Call pppoe_create() inside the tcpip_thread context. + */ +static err_t +pppapi_do_pppoe_create(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + msg->msg.ppp = pppoe_create(msg->msg.msg.ethernetcreate.pppif, msg->msg.msg.ethernetcreate.ethif, + msg->msg.msg.ethernetcreate.service_name, msg->msg.msg.ethernetcreate.concentrator_name, + msg->msg.msg.ethernetcreate.link_status_cb, msg->msg.msg.ethernetcreate.ctx_cb); + return ERR_OK; +} + +/** + * Call pppoe_create() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +ppp_pcb* +pppapi_pppoe_create(struct netif *pppif, struct netif *ethif, const char *service_name, + const char *concentrator_name, ppp_link_status_cb_fn link_status_cb, + void *ctx_cb) +{ + ppp_pcb* result; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC_RETURN_NULL(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = NULL; + PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.pppif = pppif; + PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.ethif = ethif; + PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.service_name = service_name; + PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.concentrator_name = concentrator_name; + PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.link_status_cb = link_status_cb; + PPPAPI_VAR_REF(msg).msg.msg.ethernetcreate.ctx_cb = ctx_cb; + tcpip_api_call(pppapi_do_pppoe_create, &PPPAPI_VAR_REF(msg).call); + result = PPPAPI_VAR_REF(msg).msg.ppp; + PPPAPI_VAR_FREE(msg); + return result; +} +#endif /* PPPOE_SUPPORT */ + + +#if PPPOL2TP_SUPPORT +/** + * Call pppol2tp_create() inside the tcpip_thread context. + */ +static err_t +pppapi_do_pppol2tp_create(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + msg->msg.ppp = pppol2tp_create(msg->msg.msg.l2tpcreate.pppif, + msg->msg.msg.l2tpcreate.netif, API_EXPR_REF(msg->msg.msg.l2tpcreate.ipaddr), msg->msg.msg.l2tpcreate.port, +#if PPPOL2TP_AUTH_SUPPORT + msg->msg.msg.l2tpcreate.secret, + msg->msg.msg.l2tpcreate.secret_len, +#else /* PPPOL2TP_AUTH_SUPPORT */ + NULL, + 0, +#endif /* PPPOL2TP_AUTH_SUPPORT */ + msg->msg.msg.l2tpcreate.link_status_cb, msg->msg.msg.l2tpcreate.ctx_cb); + return ERR_OK; +} + +/** + * Call pppol2tp_create() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +ppp_pcb* +pppapi_pppol2tp_create(struct netif *pppif, struct netif *netif, ip_addr_t *ipaddr, u16_t port, + const u8_t *secret, u8_t secret_len, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb) +{ + ppp_pcb* result; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC_RETURN_NULL(msg); +#if !PPPOL2TP_AUTH_SUPPORT + LWIP_UNUSED_ARG(secret); + LWIP_UNUSED_ARG(secret_len); +#endif /* !PPPOL2TP_AUTH_SUPPORT */ + + PPPAPI_VAR_REF(msg).msg.ppp = NULL; + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.pppif = pppif; + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.netif = netif; + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.ipaddr = PPPAPI_VAR_REF(ipaddr); + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.port = port; +#if PPPOL2TP_AUTH_SUPPORT + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.secret = secret; + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.secret_len = secret_len; +#endif /* PPPOL2TP_AUTH_SUPPORT */ + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.link_status_cb = link_status_cb; + PPPAPI_VAR_REF(msg).msg.msg.l2tpcreate.ctx_cb = ctx_cb; + tcpip_api_call(pppapi_do_pppol2tp_create, &PPPAPI_VAR_REF(msg).call); + result = PPPAPI_VAR_REF(msg).msg.ppp; + PPPAPI_VAR_FREE(msg); + return result; +} +#endif /* PPPOL2TP_SUPPORT */ + + +/** + * Call ppp_connect() inside the tcpip_thread context. + */ +static err_t +pppapi_do_ppp_connect(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + return ppp_connect(msg->msg.ppp, msg->msg.msg.connect.holdoff); +} + +/** + * Call ppp_connect() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +err_t +pppapi_connect(ppp_pcb *pcb, u16_t holdoff) +{ + err_t err; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = pcb; + PPPAPI_VAR_REF(msg).msg.msg.connect.holdoff = holdoff; + err = tcpip_api_call(pppapi_do_ppp_connect, &PPPAPI_VAR_REF(msg).call); + PPPAPI_VAR_FREE(msg); + return err; +} + + +#if PPP_SERVER +/** + * Call ppp_listen() inside the tcpip_thread context. + */ +static err_t +pppapi_do_ppp_listen(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + return ppp_listen(msg->msg.ppp); +} + +/** + * Call ppp_listen() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +err_t +pppapi_listen(ppp_pcb *pcb) +{ + err_t err; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = pcb; + err = tcpip_api_call(pppapi_do_ppp_listen, &PPPAPI_VAR_REF(msg).call); + PPPAPI_VAR_FREE(msg); + return err; +} +#endif /* PPP_SERVER */ + + +/** + * Call ppp_close() inside the tcpip_thread context. + */ +static err_t +pppapi_do_ppp_close(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + return ppp_close(msg->msg.ppp, msg->msg.msg.close.nocarrier); +} + +/** + * Call ppp_close() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +err_t +pppapi_close(ppp_pcb *pcb, u8_t nocarrier) +{ + err_t err; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = pcb; + PPPAPI_VAR_REF(msg).msg.msg.close.nocarrier = nocarrier; + err = tcpip_api_call(pppapi_do_ppp_close, &PPPAPI_VAR_REF(msg).call); + PPPAPI_VAR_FREE(msg); + return err; +} + + +/** + * Call ppp_free() inside the tcpip_thread context. + */ +static err_t +pppapi_do_ppp_free(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + return ppp_free(msg->msg.ppp); +} + +/** + * Call ppp_free() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +err_t +pppapi_free(ppp_pcb *pcb) +{ + err_t err; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = pcb; + err = tcpip_api_call(pppapi_do_ppp_free, &PPPAPI_VAR_REF(msg).call); + PPPAPI_VAR_FREE(msg); + return err; +} + + +/** + * Call ppp_ioctl() inside the tcpip_thread context. + */ +static err_t +pppapi_do_ppp_ioctl(struct tcpip_api_call_data *m) +{ + /* cast through void* to silence alignment warnings. + * We know it works because the structs have been instantiated as struct pppapi_msg */ + struct pppapi_msg *msg = (struct pppapi_msg *)(void*)m; + + return ppp_ioctl(msg->msg.ppp, msg->msg.msg.ioctl.cmd, msg->msg.msg.ioctl.arg); +} + +/** + * Call ppp_ioctl() in a thread-safe way by running that function inside the + * tcpip_thread context. + */ +err_t +pppapi_ioctl(ppp_pcb *pcb, u8_t cmd, void *arg) +{ + err_t err; + PPPAPI_VAR_DECLARE(msg); + PPPAPI_VAR_ALLOC(msg); + + PPPAPI_VAR_REF(msg).msg.ppp = pcb; + PPPAPI_VAR_REF(msg).msg.msg.ioctl.cmd = cmd; + PPPAPI_VAR_REF(msg).msg.msg.ioctl.arg = arg; + err = tcpip_api_call(pppapi_do_ppp_ioctl, &PPPAPI_VAR_REF(msg).call); + PPPAPI_VAR_FREE(msg); + return err; +} + +#endif /* LWIP_PPP_API */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c new file mode 100644 index 0000000..82d78c1 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppcrypt.c @@ -0,0 +1,66 @@ +/* + * pppcrypt.c - PPP/DES linkage for MS-CHAP and EAP SRP-SHA1 + * + * Extracted from chap_ms.c by James Carlson. + * + * Copyright (c) 1995 Eric Rosenquist. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && MSCHAP_SUPPORT /* don't build if not necessary */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/pppcrypt.h" + + +static u_char pppcrypt_get_7bits(u_char *input, int startBit) { + unsigned int word; + + word = (unsigned)input[startBit / 8] << 8; + word |= (unsigned)input[startBit / 8 + 1]; + + word >>= 15 - (startBit % 8 + 7); + + return word & 0xFE; +} + +/* IN 56 bit DES key missing parity bits + * OUT 64 bit DES key with parity bits added + */ +void pppcrypt_56_to_64_bit_key(u_char *key, u_char * des_key) { + des_key[0] = pppcrypt_get_7bits(key, 0); + des_key[1] = pppcrypt_get_7bits(key, 7); + des_key[2] = pppcrypt_get_7bits(key, 14); + des_key[3] = pppcrypt_get_7bits(key, 21); + des_key[4] = pppcrypt_get_7bits(key, 28); + des_key[5] = pppcrypt_get_7bits(key, 35); + des_key[6] = pppcrypt_get_7bits(key, 42); + des_key[7] = pppcrypt_get_7bits(key, 49); +} + +#endif /* PPP_SUPPORT && MSCHAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c new file mode 100644 index 0000000..8ed2d63 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppoe.c @@ -0,0 +1,1201 @@ +/***************************************************************************** +* pppoe.c - PPP Over Ethernet implementation for lwIP. +* +* Copyright (c) 2006 by Marc Boucher, Services Informatiques (MBSI) inc. +* +* The authors hereby grant permission to use, copy, modify, distribute, +* and license this software and its documentation for any purpose, provided +* that existing copyright notices are retained in all copies and that this +* notice and the following disclaimer are included verbatim in any +* distributions. No written agreement, license, or royalty fee is required +* for any of the authorized uses. +* +* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS *AS IS* AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +****************************************************************************** +* REVISION HISTORY +* +* 06-01-01 Marc Boucher +* Ported to lwIP. +*****************************************************************************/ + + + +/* based on NetBSD: if_pppoe.c,v 1.64 2006/01/31 23:50:15 martin Exp */ + +/*- + * Copyright (c) 2002 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Martin Husemann . + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPPOE_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if 0 /* UNUSED */ +#include +#include +#endif /* UNUSED */ + +#include "lwip/timeouts.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" + +#include "netif/ethernet.h" +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/lcp.h" +#include "netif/ppp/ipcp.h" +#include "netif/ppp/pppoe.h" + +/* Memory pool */ +LWIP_MEMPOOL_DECLARE(PPPOE_IF, MEMP_NUM_PPPOE_INTERFACES, sizeof(struct pppoe_softc), "PPPOE_IF") + +/* Add a 16 bit unsigned value to a buffer pointed to by PTR */ +#define PPPOE_ADD_16(PTR, VAL) \ + *(PTR)++ = (u8_t)((VAL) / 256); \ + *(PTR)++ = (u8_t)((VAL) % 256) + +/* Add a complete PPPoE header to the buffer pointed to by PTR */ +#define PPPOE_ADD_HEADER(PTR, CODE, SESS, LEN) \ + *(PTR)++ = PPPOE_VERTYPE; \ + *(PTR)++ = (CODE); \ + PPPOE_ADD_16(PTR, SESS); \ + PPPOE_ADD_16(PTR, LEN) + +#define PPPOE_DISC_TIMEOUT (5*1000) /* base for quick timeout calculation */ +#define PPPOE_SLOW_RETRY (60*1000) /* persistent retry interval */ +#define PPPOE_DISC_MAXPADI 4 /* retry PADI four times (quickly) */ +#define PPPOE_DISC_MAXPADR 2 /* retry PADR twice */ + +#ifdef PPPOE_SERVER +#error "PPPOE_SERVER is not yet supported under lwIP!" +/* from if_spppsubr.c */ +#define IFF_PASSIVE IFF_LINK0 /* wait passively for connection */ +#endif + +#define PPPOE_ERRORSTRING_LEN 64 + + +/* callbacks called from PPP core */ +static err_t pppoe_write(ppp_pcb *ppp, void *ctx, struct pbuf *p); +static err_t pppoe_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol); +static void pppoe_connect(ppp_pcb *ppp, void *ctx); +static void pppoe_disconnect(ppp_pcb *ppp, void *ctx); +static err_t pppoe_destroy(ppp_pcb *ppp, void *ctx); + +/* management routines */ +static void pppoe_abort_connect(struct pppoe_softc *); +#if 0 /* UNUSED */ +static void pppoe_clear_softc(struct pppoe_softc *, const char *); +#endif /* UNUSED */ + +/* internal timeout handling */ +static void pppoe_timeout(void *); + +/* sending actual protocol controll packets */ +static err_t pppoe_send_padi(struct pppoe_softc *); +static err_t pppoe_send_padr(struct pppoe_softc *); +#ifdef PPPOE_SERVER +static err_t pppoe_send_pado(struct pppoe_softc *); +static err_t pppoe_send_pads(struct pppoe_softc *); +#endif +static err_t pppoe_send_padt(struct netif *, u_int, const u8_t *); + +/* internal helper functions */ +static err_t pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb); +static struct pppoe_softc* pppoe_find_softc_by_session(u_int session, struct netif *rcvif); +static struct pppoe_softc* pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif); + +/** linked list of created pppoe interfaces */ +static struct pppoe_softc *pppoe_softc_list; + +/* Callbacks structure for PPP core */ +static const struct link_callbacks pppoe_callbacks = { + pppoe_connect, +#if PPP_SERVER + NULL, +#endif /* PPP_SERVER */ + pppoe_disconnect, + pppoe_destroy, + pppoe_write, + pppoe_netif_output, + NULL, + NULL +}; + +/* + * Create a new PPP Over Ethernet (PPPoE) connection. + * + * Return 0 on success, an error code on failure. + */ +ppp_pcb *pppoe_create(struct netif *pppif, + struct netif *ethif, + const char *service_name, const char *concentrator_name, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb) +{ + ppp_pcb *ppp; + struct pppoe_softc *sc; + LWIP_UNUSED_ARG(service_name); + LWIP_UNUSED_ARG(concentrator_name); + LWIP_ASSERT_CORE_LOCKED(); + + sc = (struct pppoe_softc *)LWIP_MEMPOOL_ALLOC(PPPOE_IF); + if (sc == NULL) { + return NULL; + } + + ppp = ppp_new(pppif, &pppoe_callbacks, sc, link_status_cb, ctx_cb); + if (ppp == NULL) { + LWIP_MEMPOOL_FREE(PPPOE_IF, sc); + return NULL; + } + + memset(sc, 0, sizeof(struct pppoe_softc)); + sc->pcb = ppp; + sc->sc_ethif = ethif; + /* put the new interface at the head of the list */ + sc->next = pppoe_softc_list; + pppoe_softc_list = sc; + return ppp; +} + +/* Called by PPP core */ +static err_t pppoe_write(ppp_pcb *ppp, void *ctx, struct pbuf *p) { + struct pppoe_softc *sc = (struct pppoe_softc *)ctx; + struct pbuf *ph; /* Ethernet + PPPoE header */ + err_t ret; +#if MIB2_STATS + u16_t tot_len; +#else /* MIB2_STATS */ + LWIP_UNUSED_ARG(ppp); +#endif /* MIB2_STATS */ + + /* skip address & flags */ + pbuf_remove_header(p, 2); + + ph = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN), PBUF_RAM); + if(!ph) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + pbuf_free(p); + return ERR_MEM; + } + + pbuf_remove_header(ph, PPPOE_HEADERLEN); /* hide PPPoE header */ + pbuf_cat(ph, p); +#if MIB2_STATS + tot_len = ph->tot_len; +#endif /* MIB2_STATS */ + + ret = pppoe_xmit(sc, ph); + if (ret != ERR_OK) { + LINK_STATS_INC(link.err); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + return ret; + } + + MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, (u16_t)tot_len); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts); + LINK_STATS_INC(link.xmit); + return ERR_OK; +} + +/* Called by PPP core */ +static err_t pppoe_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol) { + struct pppoe_softc *sc = (struct pppoe_softc *)ctx; + struct pbuf *pb; + u8_t *pl; + err_t err; +#if MIB2_STATS + u16_t tot_len; +#else /* MIB2_STATS */ + LWIP_UNUSED_ARG(ppp); +#endif /* MIB2_STATS */ + + /* @todo: try to use pbuf_header() here! */ + pb = pbuf_alloc(PBUF_LINK, PPPOE_HEADERLEN + sizeof(protocol), PBUF_RAM); + if(!pb) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + return ERR_MEM; + } + + pbuf_remove_header(pb, PPPOE_HEADERLEN); + + pl = (u8_t*)pb->payload; + PUTSHORT(protocol, pl); + + pbuf_chain(pb, p); +#if MIB2_STATS + tot_len = pb->tot_len; +#endif /* MIB2_STATS */ + + if( (err = pppoe_xmit(sc, pb)) != ERR_OK) { + LINK_STATS_INC(link.err); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + return err; + } + + MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, tot_len); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts); + LINK_STATS_INC(link.xmit); + return ERR_OK; +} + +static err_t +pppoe_destroy(ppp_pcb *ppp, void *ctx) +{ + struct pppoe_softc *sc = (struct pppoe_softc *)ctx; + struct pppoe_softc **copp, *freep; + LWIP_UNUSED_ARG(ppp); + + sys_untimeout(pppoe_timeout, sc); + + /* remove interface from list */ + for (copp = &pppoe_softc_list; (freep = *copp); copp = &freep->next) { + if (freep == sc) { + *copp = freep->next; + break; + } + } + +#ifdef PPPOE_TODO + if (sc->sc_concentrator_name) { + mem_free(sc->sc_concentrator_name); + } + if (sc->sc_service_name) { + mem_free(sc->sc_service_name); + } +#endif /* PPPOE_TODO */ + LWIP_MEMPOOL_FREE(PPPOE_IF, sc); + + return ERR_OK; +} + +/* + * Find the interface handling the specified session. + * Note: O(number of sessions open), this is a client-side only, mean + * and lean implementation, so number of open sessions typically should + * be 1. + */ +static struct pppoe_softc* pppoe_find_softc_by_session(u_int session, struct netif *rcvif) { + struct pppoe_softc *sc; + + for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) { + if (sc->sc_state == PPPOE_STATE_SESSION + && sc->sc_session == session + && sc->sc_ethif == rcvif) { + return sc; + } + } + return NULL; +} + +/* Check host unique token passed and return appropriate softc pointer, + * or NULL if token is bogus. */ +static struct pppoe_softc* pppoe_find_softc_by_hunique(u8_t *token, size_t len, struct netif *rcvif) { + struct pppoe_softc *sc, *t; + + if (len != sizeof sc) { + return NULL; + } + MEMCPY(&t, token, len); + + for (sc = pppoe_softc_list; sc != NULL; sc = sc->next) { + if (sc == t) { + break; + } + } + + if (sc == NULL) { + PPPDEBUG(LOG_DEBUG, ("pppoe: alien host unique tag, no session found\n")); + return NULL; + } + + /* should be safe to access *sc now */ + if (sc->sc_state < PPPOE_STATE_PADI_SENT || sc->sc_state >= PPPOE_STATE_SESSION) { + PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": host unique tag found, but it belongs to a connection in state %d\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_state)); + return NULL; + } + if (sc->sc_ethif != rcvif) { + PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": wrong interface, not accepting host unique\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + return NULL; + } + return sc; +} + +/* analyze and handle a single received packet while not in session state */ +void +pppoe_disc_input(struct netif *netif, struct pbuf *pb) +{ + u16_t tag, len, off; + u16_t session, plen; + struct pppoe_softc *sc; +#if PPP_DEBUG + const char *err_msg = NULL; +#endif /* PPP_DEBUG */ + u8_t *ac_cookie; + u16_t ac_cookie_len; +#ifdef PPPOE_SERVER + u8_t *hunique; + size_t hunique_len; +#endif + struct pppoehdr *ph; + struct pppoetag pt; + int err; + struct eth_hdr *ethhdr; + + /* don't do anything if there is not a single PPPoE instance */ + if (pppoe_softc_list == NULL) { + pbuf_free(pb); + return; + } + + pb = pbuf_coalesce(pb, PBUF_RAW); + + ethhdr = (struct eth_hdr *)pb->payload; + + ac_cookie = NULL; + ac_cookie_len = 0; +#ifdef PPPOE_SERVER + hunique = NULL; + hunique_len = 0; +#endif + session = 0; + off = sizeof(struct eth_hdr) + sizeof(struct pppoehdr); + if (pb->len < off) { + PPPDEBUG(LOG_DEBUG, ("pppoe: packet too short: %d\n", pb->len)); + goto done; + } + + ph = (struct pppoehdr *) (ethhdr + 1); + if (ph->vertype != PPPOE_VERTYPE) { + PPPDEBUG(LOG_DEBUG, ("pppoe: unknown version/type packet: 0x%x\n", ph->vertype)); + goto done; + } + session = lwip_ntohs(ph->session); + plen = lwip_ntohs(ph->plen); + + if (plen > (pb->len - off)) { + PPPDEBUG(LOG_DEBUG, ("pppoe: packet content does not fit: data available = %d, packet size = %u\n", + pb->len - off, plen)); + goto done; + } + if(pb->tot_len == pb->len) { + u16_t framelen = off + plen; + if (framelen < pb->len) { + /* ignore trailing garbage */ + pb->tot_len = pb->len = framelen; + } + } + tag = 0; + len = 0; + sc = NULL; + while (off + sizeof(pt) <= pb->len) { + MEMCPY(&pt, (u8_t*)pb->payload + off, sizeof(pt)); + tag = lwip_ntohs(pt.tag); + len = lwip_ntohs(pt.len); + if (off + sizeof(pt) + len > pb->len) { + PPPDEBUG(LOG_DEBUG, ("pppoe: tag 0x%x len 0x%x is too long\n", tag, len)); + goto done; + } + switch (tag) { + case PPPOE_TAG_EOL: + goto breakbreak; + case PPPOE_TAG_SNAME: + break; /* ignored */ + case PPPOE_TAG_ACNAME: + break; /* ignored */ + case PPPOE_TAG_HUNIQUE: + if (sc != NULL) { + break; + } +#ifdef PPPOE_SERVER + hunique = (u8_t*)pb->payload + off + sizeof(pt); + hunique_len = len; +#endif + sc = pppoe_find_softc_by_hunique((u8_t*)pb->payload + off + sizeof(pt), len, netif); + break; + case PPPOE_TAG_ACCOOKIE: + if (ac_cookie == NULL) { + if (len > PPPOE_MAX_AC_COOKIE_LEN) { + PPPDEBUG(LOG_DEBUG, ("pppoe: AC cookie is too long: len = %d, max = %d\n", len, PPPOE_MAX_AC_COOKIE_LEN)); + goto done; + } + ac_cookie = (u8_t*)pb->payload + off + sizeof(pt); + ac_cookie_len = len; + } + break; +#if PPP_DEBUG + case PPPOE_TAG_SNAME_ERR: + err_msg = "SERVICE NAME ERROR"; + break; + case PPPOE_TAG_ACSYS_ERR: + err_msg = "AC SYSTEM ERROR"; + break; + case PPPOE_TAG_GENERIC_ERR: + err_msg = "GENERIC ERROR"; + break; +#endif /* PPP_DEBUG */ + default: + break; + } +#if PPP_DEBUG + if (err_msg != NULL) { + char error_tmp[PPPOE_ERRORSTRING_LEN]; + u16_t error_len = LWIP_MIN(len, sizeof(error_tmp)-1); + strncpy(error_tmp, (char*)pb->payload + off + sizeof(pt), error_len); + error_tmp[error_len] = '\0'; + if (sc) { + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": %s: %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err_msg, error_tmp)); + } else { + PPPDEBUG(LOG_DEBUG, ("pppoe: %s: %s\n", err_msg, error_tmp)); + } + } +#endif /* PPP_DEBUG */ + off += sizeof(pt) + len; + } + +breakbreak:; + switch (ph->code) { + case PPPOE_CODE_PADI: +#ifdef PPPOE_SERVER + /* + * got service name, concentrator name, and/or host unique. + * ignore if we have no interfaces with IFF_PASSIVE|IFF_UP. + */ + if (LIST_EMPTY(&pppoe_softc_list)) { + goto done; + } + LIST_FOREACH(sc, &pppoe_softc_list, sc_list) { + if (!(sc->sc_sppp.pp_if.if_flags & IFF_UP)) { + continue; + } + if (!(sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) { + continue; + } + if (sc->sc_state == PPPOE_STATE_INITIAL) { + break; + } + } + if (sc == NULL) { + /* PPPDEBUG(LOG_DEBUG, ("pppoe: free passive interface is not found\n")); */ + goto done; + } + if (hunique) { + if (sc->sc_hunique) { + mem_free(sc->sc_hunique); + } + sc->sc_hunique = mem_malloc(hunique_len); + if (sc->sc_hunique == NULL) { + goto done; + } + sc->sc_hunique_len = hunique_len; + MEMCPY(sc->sc_hunique, hunique, hunique_len); + } + MEMCPY(&sc->sc_dest, eh->ether_shost, sizeof sc->sc_dest); + sc->sc_state = PPPOE_STATE_PADO_SENT; + pppoe_send_pado(sc); + break; +#endif /* PPPOE_SERVER */ + case PPPOE_CODE_PADR: +#ifdef PPPOE_SERVER + /* + * get sc from ac_cookie if IFF_PASSIVE + */ + if (ac_cookie == NULL) { + /* be quiet if there is not a single pppoe instance */ + PPPDEBUG(LOG_DEBUG, ("pppoe: received PADR but not includes ac_cookie\n")); + goto done; + } + sc = pppoe_find_softc_by_hunique(ac_cookie, ac_cookie_len, netif); + if (sc == NULL) { + /* be quiet if there is not a single pppoe instance */ + if (!LIST_EMPTY(&pppoe_softc_list)) { + PPPDEBUG(LOG_DEBUG, ("pppoe: received PADR but could not find request for it\n")); + } + goto done; + } + if (sc->sc_state != PPPOE_STATE_PADO_SENT) { + PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": received unexpected PADR\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + goto done; + } + if (hunique) { + if (sc->sc_hunique) { + mem_free(sc->sc_hunique); + } + sc->sc_hunique = mem_malloc(hunique_len); + if (sc->sc_hunique == NULL) { + goto done; + } + sc->sc_hunique_len = hunique_len; + MEMCPY(sc->sc_hunique, hunique, hunique_len); + } + pppoe_send_pads(sc); + sc->sc_state = PPPOE_STATE_SESSION; + ppp_start(sc->pcb); /* notify upper layers */ + break; +#else + /* ignore, we are no access concentrator */ + goto done; +#endif /* PPPOE_SERVER */ + case PPPOE_CODE_PADO: + if (sc == NULL) { + /* be quiet if there is not a single pppoe instance */ + if (pppoe_softc_list != NULL) { + PPPDEBUG(LOG_DEBUG, ("pppoe: received PADO but could not find request for it\n")); + } + goto done; + } + if (sc->sc_state != PPPOE_STATE_PADI_SENT) { + PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": received unexpected PADO\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + goto done; + } + if (ac_cookie) { + sc->sc_ac_cookie_len = ac_cookie_len; + MEMCPY(sc->sc_ac_cookie, ac_cookie, ac_cookie_len); + } + MEMCPY(&sc->sc_dest, ethhdr->src.addr, sizeof(sc->sc_dest.addr)); + sys_untimeout(pppoe_timeout, sc); + sc->sc_padr_retried = 0; + sc->sc_state = PPPOE_STATE_PADR_SENT; + if ((err = pppoe_send_padr(sc)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc); + break; + case PPPOE_CODE_PADS: + if (sc == NULL) { + goto done; + } + sc->sc_session = session; + sys_untimeout(pppoe_timeout, sc); + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x connected\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, session)); + sc->sc_state = PPPOE_STATE_SESSION; + ppp_start(sc->pcb); /* notify upper layers */ + break; + case PPPOE_CODE_PADT: + /* Don't disconnect here, we let the LCP Echo/Reply find the fact + * that PPP session is down. Asking the PPP stack to end the session + * require strict checking about the PPP phase to prevent endless + * disconnection loops. + */ +#if 0 /* UNUSED */ + if (sc == NULL) { /* PADT frames are rarely sent with a hunique tag, this is actually almost always true */ + goto done; + } + pppoe_clear_softc(sc, "received PADT"); +#endif /* UNUSED */ + break; + default: + if(sc) { + PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": unknown code (0x%"X16_F") session = 0x%"X16_F"\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, + (u16_t)ph->code, session)); + } else { + PPPDEBUG(LOG_DEBUG, ("pppoe: unknown code (0x%"X16_F") session = 0x%"X16_F"\n", (u16_t)ph->code, session)); + } + break; + } + +done: + pbuf_free(pb); + return; +} + +void +pppoe_data_input(struct netif *netif, struct pbuf *pb) +{ + u16_t session, plen; + struct pppoe_softc *sc; + struct pppoehdr *ph; +#ifdef PPPOE_TERM_UNKNOWN_SESSIONS + u8_t shost[ETHER_ADDR_LEN]; +#endif + +#ifdef PPPOE_TERM_UNKNOWN_SESSIONS + MEMCPY(shost, ((struct eth_hdr *)pb->payload)->src.addr, sizeof(shost)); +#endif + if (pbuf_remove_header(pb, sizeof(struct eth_hdr)) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_remove_header failed\n")); + LINK_STATS_INC(link.lenerr); + goto drop; + } + + if (pb->len < sizeof(*ph)) { + PPPDEBUG(LOG_DEBUG, ("pppoe_data_input: could not get PPPoE header\n")); + goto drop; + } + ph = (struct pppoehdr *)pb->payload; + + if (ph->vertype != PPPOE_VERTYPE) { + PPPDEBUG(LOG_DEBUG, ("pppoe (data): unknown version/type packet: 0x%x\n", ph->vertype)); + goto drop; + } + if (ph->code != 0) { + goto drop; + } + + session = lwip_ntohs(ph->session); + sc = pppoe_find_softc_by_session(session, netif); + if (sc == NULL) { +#ifdef PPPOE_TERM_UNKNOWN_SESSIONS + PPPDEBUG(LOG_DEBUG, ("pppoe: input for unknown session 0x%x, sending PADT\n", session)); + pppoe_send_padt(netif, session, shost); +#endif + goto drop; + } + + plen = lwip_ntohs(ph->plen); + + if (pbuf_remove_header(pb, PPPOE_HEADERLEN) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppoe_data_input: pbuf_remove_header PPPOE_HEADERLEN failed\n")); + LINK_STATS_INC(link.lenerr); + goto drop; + } + + PPPDEBUG(LOG_DEBUG, ("pppoe_data_input: %c%c%"U16_F": pkthdr.len=%d, pppoe.len=%d\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, + pb->len, plen)); + + if (pb->tot_len < plen) { + goto drop; + } + + /* Dispatch the packet thereby consuming it. */ + ppp_input(sc->pcb, pb); + return; + +drop: + pbuf_free(pb); +} + +static err_t +pppoe_output(struct pppoe_softc *sc, struct pbuf *pb) +{ + struct eth_hdr *ethhdr; + u16_t etype; + err_t res; + + /* make room for Ethernet header - should not fail */ + if (pbuf_add_header(pb, sizeof(struct eth_hdr)) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppoe: %c%c%"U16_F": pppoe_output: could not allocate room for Ethernet header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + LINK_STATS_INC(link.lenerr); + pbuf_free(pb); + return ERR_BUF; + } + ethhdr = (struct eth_hdr *)pb->payload; + etype = sc->sc_state == PPPOE_STATE_SESSION ? ETHTYPE_PPPOE : ETHTYPE_PPPOEDISC; + ethhdr->type = lwip_htons(etype); + MEMCPY(ðhdr->dest.addr, &sc->sc_dest.addr, sizeof(ethhdr->dest.addr)); + MEMCPY(ðhdr->src.addr, &sc->sc_ethif->hwaddr, sizeof(ethhdr->src.addr)); + + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F" (%x) state=%d, session=0x%x output -> %02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F":%02"X16_F", len=%d\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, etype, + sc->sc_state, sc->sc_session, + sc->sc_dest.addr[0], sc->sc_dest.addr[1], sc->sc_dest.addr[2], sc->sc_dest.addr[3], sc->sc_dest.addr[4], sc->sc_dest.addr[5], + pb->tot_len)); + + res = sc->sc_ethif->linkoutput(sc->sc_ethif, pb); + + pbuf_free(pb); + + return res; +} + +static err_t +pppoe_send_padi(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + int len; +#ifdef PPPOE_TODO + int l1 = 0, l2 = 0; /* XXX: gcc */ +#endif /* PPPOE_TODO */ + + /* calculate length of frame (excluding ethernet header + pppoe header) */ + len = 2 + 2 + 2 + 2 + sizeof sc; /* service name tag is required, host unique is send too */ +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { + l1 = (int)strlen(sc->sc_service_name); + len += l1; + } + if (sc->sc_concentrator_name != NULL) { + l2 = (int)strlen(sc->sc_concentrator_name); + len += 2 + 2 + l2; + } +#endif /* PPPOE_TODO */ + LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff", + sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff); + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload; + /* fill in pkt */ + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADI, 0, (u16_t)len); + PPPOE_ADD_16(p, PPPOE_TAG_SNAME); +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { + PPPOE_ADD_16(p, l1); + MEMCPY(p, sc->sc_service_name, l1); + p += l1; + } else +#endif /* PPPOE_TODO */ + { + PPPOE_ADD_16(p, 0); + } +#ifdef PPPOE_TODO + if (sc->sc_concentrator_name != NULL) { + PPPOE_ADD_16(p, PPPOE_TAG_ACNAME); + PPPOE_ADD_16(p, l2); + MEMCPY(p, sc->sc_concentrator_name, l2); + p += l2; + } +#endif /* PPPOE_TODO */ + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sizeof(sc)); + MEMCPY(p, &sc, sizeof sc); + + /* send pkt */ + return pppoe_output(sc, pb); +} + +static void +pppoe_timeout(void *arg) +{ + u32_t retry_wait; + int err; + struct pppoe_softc *sc = (struct pppoe_softc*)arg; + + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": timeout\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + + switch (sc->sc_state) { + case PPPOE_STATE_PADI_SENT: + /* + * We have two basic ways of retrying: + * - Quick retry mode: try a few times in short sequence + * - Slow retry mode: we already had a connection successfully + * established and will try infinitely (without user + * intervention) + * We only enter slow retry mode if IFF_LINK1 (aka autodial) + * is not set. + */ + if (sc->sc_padi_retried < 0xff) { + sc->sc_padi_retried++; + } + if (!sc->pcb->settings.persist && sc->sc_padi_retried >= PPPOE_DISC_MAXPADI) { +#if 0 + if ((sc->sc_sppp.pp_if.if_flags & IFF_LINK1) == 0) { + /* slow retry mode */ + retry_wait = PPPOE_SLOW_RETRY; + } else +#endif + { + pppoe_abort_connect(sc); + return; + } + } + /* initialize for quick retry mode */ + retry_wait = LWIP_MIN(PPPOE_DISC_TIMEOUT * sc->sc_padi_retried, PPPOE_SLOW_RETRY); + if ((err = pppoe_send_padi(sc)) != 0) { + sc->sc_padi_retried--; + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to transmit PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_timeout(retry_wait, pppoe_timeout, sc); + break; + + case PPPOE_STATE_PADR_SENT: + sc->sc_padr_retried++; + if (sc->sc_padr_retried >= PPPOE_DISC_MAXPADR) { + MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest)); + sc->sc_state = PPPOE_STATE_PADI_SENT; + sc->sc_padr_retried = 0; + if ((err = pppoe_send_padi(sc)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padi_retried), pppoe_timeout, sc); + return; + } + if ((err = pppoe_send_padr(sc)) != 0) { + sc->sc_padr_retried--; + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADR, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_timeout(PPPOE_DISC_TIMEOUT * (1 + sc->sc_padr_retried), pppoe_timeout, sc); + break; + default: + return; /* all done, work in peace */ + } +} + +/* Start a connection (i.e. initiate discovery phase) */ +static void +pppoe_connect(ppp_pcb *ppp, void *ctx) +{ + err_t err; + struct pppoe_softc *sc = (struct pppoe_softc *)ctx; + lcp_options *lcp_wo; + lcp_options *lcp_ao; +#if PPP_IPV4_SUPPORT && VJ_SUPPORT + ipcp_options *ipcp_wo; + ipcp_options *ipcp_ao; +#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */ + + sc->sc_session = 0; + sc->sc_ac_cookie_len = 0; + sc->sc_padi_retried = 0; + sc->sc_padr_retried = 0; + /* changed to real address later */ + MEMCPY(&sc->sc_dest, ethbroadcast.addr, sizeof(sc->sc_dest)); +#ifdef PPPOE_SERVER + /* wait PADI if IFF_PASSIVE */ + if ((sc->sc_sppp.pp_if.if_flags & IFF_PASSIVE)) { + return 0; + } +#endif + + lcp_wo = &ppp->lcp_wantoptions; + lcp_wo->mru = sc->sc_ethif->mtu-PPPOE_HEADERLEN-2; /* two byte PPP protocol discriminator, then IP data */ + lcp_wo->neg_asyncmap = 0; + lcp_wo->neg_pcompression = 0; + lcp_wo->neg_accompression = 0; + lcp_wo->passive = 0; + lcp_wo->silent = 0; + + lcp_ao = &ppp->lcp_allowoptions; + lcp_ao->mru = sc->sc_ethif->mtu-PPPOE_HEADERLEN-2; /* two byte PPP protocol discriminator, then IP data */ + lcp_ao->neg_asyncmap = 0; + lcp_ao->neg_pcompression = 0; + lcp_ao->neg_accompression = 0; + +#if PPP_IPV4_SUPPORT && VJ_SUPPORT + ipcp_wo = &ppp->ipcp_wantoptions; + ipcp_wo->neg_vj = 0; + ipcp_wo->old_vj = 0; + + ipcp_ao = &ppp->ipcp_allowoptions; + ipcp_ao->neg_vj = 0; + ipcp_ao->old_vj = 0; +#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */ + + /* save state, in case we fail to send PADI */ + sc->sc_state = PPPOE_STATE_PADI_SENT; + if ((err = pppoe_send_padi(sc)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": failed to send PADI, error=%d\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, err)); + } + sys_timeout(PPPOE_DISC_TIMEOUT, pppoe_timeout, sc); +} + +/* disconnect */ +static void +pppoe_disconnect(ppp_pcb *ppp, void *ctx) +{ + struct pppoe_softc *sc = (struct pppoe_softc *)ctx; + + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": disconnecting\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + if (sc->sc_state == PPPOE_STATE_SESSION) { + pppoe_send_padt(sc->sc_ethif, sc->sc_session, (const u8_t *)&sc->sc_dest); + } + + /* stop any timer, disconnect can be called while initiating is in progress */ + sys_untimeout(pppoe_timeout, sc); + sc->sc_state = PPPOE_STATE_INITIAL; +#ifdef PPPOE_SERVER + if (sc->sc_hunique) { + mem_free(sc->sc_hunique); + sc->sc_hunique = NULL; /* probably not necessary, if state is initial we shouldn't have to access hunique anyway */ + } + sc->sc_hunique_len = 0; /* probably not necessary, if state is initial we shouldn't have to access hunique anyway */ +#endif + ppp_link_end(ppp); /* notify upper layers */ + return; +} + +/* Connection attempt aborted */ +static void +pppoe_abort_connect(struct pppoe_softc *sc) +{ + PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": could not establish connection\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + sc->sc_state = PPPOE_STATE_INITIAL; + ppp_link_failed(sc->pcb); /* notify upper layers */ +} + +/* Send a PADR packet */ +static err_t +pppoe_send_padr(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + size_t len; +#ifdef PPPOE_TODO + size_t l1 = 0; /* XXX: gcc */ +#endif /* PPPOE_TODO */ + + len = 2 + 2 + 2 + 2 + sizeof(sc); /* service name, host unique */ +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { /* service name tag maybe empty */ + l1 = strlen(sc->sc_service_name); + len += l1; + } +#endif /* PPPOE_TODO */ + if (sc->sc_ac_cookie_len > 0) { + len += 2 + 2 + sc->sc_ac_cookie_len; /* AC cookie */ + } + LWIP_ASSERT("sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff", + sizeof(struct eth_hdr) + PPPOE_HEADERLEN + len <= 0xffff); + pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + p = (u8_t*)pb->payload; + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADR, 0, len); + PPPOE_ADD_16(p, PPPOE_TAG_SNAME); +#ifdef PPPOE_TODO + if (sc->sc_service_name != NULL) { + PPPOE_ADD_16(p, l1); + MEMCPY(p, sc->sc_service_name, l1); + p += l1; + } else +#endif /* PPPOE_TODO */ + { + PPPOE_ADD_16(p, 0); + } + if (sc->sc_ac_cookie_len > 0) { + PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE); + PPPOE_ADD_16(p, sc->sc_ac_cookie_len); + MEMCPY(p, sc->sc_ac_cookie, sc->sc_ac_cookie_len); + p += sc->sc_ac_cookie_len; + } + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sizeof(sc)); + MEMCPY(p, &sc, sizeof sc); + + return pppoe_output(sc, pb); +} + +/* send a PADT packet */ +static err_t +pppoe_send_padt(struct netif *outgoing_if, u_int session, const u8_t *dest) +{ + struct pbuf *pb; + struct eth_hdr *ethhdr; + err_t res; + u8_t *p; + + pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN), PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + if (pbuf_add_header(pb, sizeof(struct eth_hdr))) { + PPPDEBUG(LOG_ERR, ("pppoe: pppoe_send_padt: could not allocate room for PPPoE header\n")); + LINK_STATS_INC(link.lenerr); + pbuf_free(pb); + return ERR_BUF; + } + ethhdr = (struct eth_hdr *)pb->payload; + ethhdr->type = PP_HTONS(ETHTYPE_PPPOEDISC); + MEMCPY(ðhdr->dest.addr, dest, sizeof(ethhdr->dest.addr)); + MEMCPY(ðhdr->src.addr, &outgoing_if->hwaddr, sizeof(ethhdr->src.addr)); + + p = (u8_t*)(ethhdr + 1); + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADT, session, 0); + + res = outgoing_if->linkoutput(outgoing_if, pb); + + pbuf_free(pb); + + return res; +} + +#ifdef PPPOE_SERVER +static err_t +pppoe_send_pado(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + size_t len; + + /* calc length */ + len = 0; + /* include ac_cookie */ + len += 2 + 2 + sizeof(sc); + /* include hunique */ + len += 2 + 2 + sc->sc_hunique_len; + pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + p = (u8_t*)pb->payload; + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADO, 0, len); + PPPOE_ADD_16(p, PPPOE_TAG_ACCOOKIE); + PPPOE_ADD_16(p, sizeof(sc)); + MEMCPY(p, &sc, sizeof(sc)); + p += sizeof(sc); + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sc->sc_hunique_len); + MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len); + return pppoe_output(sc, pb); +} + +static err_t +pppoe_send_pads(struct pppoe_softc *sc) +{ + struct pbuf *pb; + u8_t *p; + size_t len, l1 = 0; /* XXX: gcc */ + + sc->sc_session = mono_time.tv_sec % 0xff + 1; + /* calc length */ + len = 0; + /* include hunique */ + len += 2 + 2 + 2 + 2 + sc->sc_hunique_len; /* service name, host unique*/ + if (sc->sc_service_name != NULL) { /* service name tag maybe empty */ + l1 = strlen(sc->sc_service_name); + len += l1; + } + pb = pbuf_alloc(PBUF_LINK, (u16_t)(PPPOE_HEADERLEN + len), PBUF_RAM); + if (!pb) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + p = (u8_t*)pb->payload; + PPPOE_ADD_HEADER(p, PPPOE_CODE_PADS, sc->sc_session, len); + PPPOE_ADD_16(p, PPPOE_TAG_SNAME); + if (sc->sc_service_name != NULL) { + PPPOE_ADD_16(p, l1); + MEMCPY(p, sc->sc_service_name, l1); + p += l1; + } else { + PPPOE_ADD_16(p, 0); + } + PPPOE_ADD_16(p, PPPOE_TAG_HUNIQUE); + PPPOE_ADD_16(p, sc->sc_hunique_len); + MEMCPY(p, sc->sc_hunique, sc->sc_hunique_len); + return pppoe_output(sc, pb); +} +#endif + +static err_t +pppoe_xmit(struct pppoe_softc *sc, struct pbuf *pb) +{ + u8_t *p; + size_t len; + + len = pb->tot_len; + + /* make room for PPPoE header - should not fail */ + if (pbuf_add_header(pb, PPPOE_HEADERLEN) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppoe: %c%c%"U16_F": pppoe_xmit: could not allocate room for PPPoE header\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + LINK_STATS_INC(link.lenerr); + pbuf_free(pb); + return ERR_BUF; + } + + p = (u8_t*)pb->payload; + PPPOE_ADD_HEADER(p, 0, sc->sc_session, len); + + return pppoe_output(sc, pb); +} + +#if 0 /*def PFIL_HOOKS*/ +static int +pppoe_ifattach_hook(void *arg, struct pbuf **mp, struct netif *ifp, int dir) +{ + struct pppoe_softc *sc; + int s; + + if (mp != (struct pbuf **)PFIL_IFNET_DETACH) { + return 0; + } + + LIST_FOREACH(sc, &pppoe_softc_list, sc_list) { + if (sc->sc_ethif != ifp) { + continue; + } + if (sc->sc_sppp.pp_if.if_flags & IFF_UP) { + sc->sc_sppp.pp_if.if_flags &= ~(IFF_UP|IFF_RUNNING); + PPPDEBUG(LOG_DEBUG, ("%c%c%"U16_F": ethernet interface detached, going down\n", + sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num)); + } + sc->sc_ethif = NULL; + pppoe_clear_softc(sc, "ethernet interface detached"); + } + + return 0; +} +#endif + +#if 0 /* UNUSED */ +static void +pppoe_clear_softc(struct pppoe_softc *sc, const char *message) +{ + LWIP_UNUSED_ARG(message); + + /* stop timer */ + sys_untimeout(pppoe_timeout, sc); + PPPDEBUG(LOG_DEBUG, ("pppoe: %c%c%"U16_F": session 0x%x terminated, %s\n", sc->sc_ethif->name[0], sc->sc_ethif->name[1], sc->sc_ethif->num, sc->sc_session, message)); + sc->sc_state = PPPOE_STATE_INITIAL; + ppp_link_end(sc->pcb); /* notify upper layers - /!\ dangerous /!\ - see pppoe_disc_input() */ +} +#endif /* UNUSED */ +#endif /* PPP_SUPPORT && PPPOE_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c new file mode 100644 index 0000000..4c4557f --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppol2tp.c @@ -0,0 +1,1159 @@ +/** + * @file + * Network Point to Point Protocol over Layer 2 Tunneling Protocol program file. + * + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +/* + * L2TP Support status: + * + * Supported: + * - L2TPv2 (PPP over L2TP, a.k.a. UDP tunnels) + * - LAC + * + * Not supported: + * - LNS (require PPP server support) + * - L2TPv3 ethernet pseudowires + * - L2TPv3 VLAN pseudowire + * - L2TPv3 PPP pseudowires + * - L2TPv3 IP encapsulation + * - L2TPv3 IP pseudowire + * - L2TP tunnel switching - http://tools.ietf.org/html/draft-ietf-l2tpext-tunnel-switching-08 + * - Multiple tunnels per UDP socket, as well as multiple sessions per tunnel + * - Hidden AVPs + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPPOL2TP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/err.h" +#include "lwip/memp.h" +#include "lwip/netif.h" +#include "lwip/udp.h" +#include "lwip/snmp.h" + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/lcp.h" +#include "netif/ppp/ipcp.h" +#include "netif/ppp/pppol2tp.h" +#include "netif/ppp/pppcrypt.h" +#include "netif/ppp/magic.h" + +/* Memory pool */ +LWIP_MEMPOOL_DECLARE(PPPOL2TP_PCB, MEMP_NUM_PPPOL2TP_INTERFACES, sizeof(pppol2tp_pcb), "PPPOL2TP_PCB") + +/* callbacks called from PPP core */ +static err_t pppol2tp_write(ppp_pcb *ppp, void *ctx, struct pbuf *p); +static err_t pppol2tp_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol); +static err_t pppol2tp_destroy(ppp_pcb *ppp, void *ctx); /* Destroy a L2TP control block */ +static void pppol2tp_connect(ppp_pcb *ppp, void *ctx); /* Be a LAC, connect to a LNS. */ +static void pppol2tp_disconnect(ppp_pcb *ppp, void *ctx); /* Disconnect */ + + /* Prototypes for procedures local to this file. */ +static void pppol2tp_input(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port); +static void pppol2tp_dispatch_control_packet(pppol2tp_pcb *l2tp, u16_t port, struct pbuf *p, u16_t ns, u16_t nr); +static void pppol2tp_timeout(void *arg); +static void pppol2tp_abort_connect(pppol2tp_pcb *l2tp); +static err_t pppol2tp_send_sccrq(pppol2tp_pcb *l2tp); +static err_t pppol2tp_send_scccn(pppol2tp_pcb *l2tp, u16_t ns); +static err_t pppol2tp_send_icrq(pppol2tp_pcb *l2tp, u16_t ns); +static err_t pppol2tp_send_iccn(pppol2tp_pcb *l2tp, u16_t ns); +static err_t pppol2tp_send_zlb(pppol2tp_pcb *l2tp, u16_t ns, u16_t nr); +static err_t pppol2tp_send_stopccn(pppol2tp_pcb *l2tp, u16_t ns); +static err_t pppol2tp_xmit(pppol2tp_pcb *l2tp, struct pbuf *pb); +static err_t pppol2tp_udp_send(pppol2tp_pcb *l2tp, struct pbuf *pb); + +/* Callbacks structure for PPP core */ +static const struct link_callbacks pppol2tp_callbacks = { + pppol2tp_connect, +#if PPP_SERVER + NULL, +#endif /* PPP_SERVER */ + pppol2tp_disconnect, + pppol2tp_destroy, + pppol2tp_write, + pppol2tp_netif_output, + NULL, + NULL +}; + + +/* Create a new L2TP session. */ +ppp_pcb *pppol2tp_create(struct netif *pppif, + struct netif *netif, const ip_addr_t *ipaddr, u16_t port, + const u8_t *secret, u8_t secret_len, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb) { + ppp_pcb *ppp; + pppol2tp_pcb *l2tp; + struct udp_pcb *udp; +#if !PPPOL2TP_AUTH_SUPPORT + LWIP_UNUSED_ARG(secret); + LWIP_UNUSED_ARG(secret_len); +#endif /* !PPPOL2TP_AUTH_SUPPORT */ + + if (ipaddr == NULL) { + goto ipaddr_check_failed; + } + + l2tp = (pppol2tp_pcb *)LWIP_MEMPOOL_ALLOC(PPPOL2TP_PCB); + if (l2tp == NULL) { + goto memp_malloc_l2tp_failed; + } + + udp = udp_new_ip_type(IP_GET_TYPE(ipaddr)); + if (udp == NULL) { + goto udp_new_failed; + } + udp_recv(udp, pppol2tp_input, l2tp); + + ppp = ppp_new(pppif, &pppol2tp_callbacks, l2tp, link_status_cb, ctx_cb); + if (ppp == NULL) { + goto ppp_new_failed; + } + + memset(l2tp, 0, sizeof(pppol2tp_pcb)); + l2tp->phase = PPPOL2TP_STATE_INITIAL; + l2tp->ppp = ppp; + l2tp->udp = udp; + l2tp->netif = netif; + ip_addr_copy(l2tp->remote_ip, *ipaddr); + l2tp->remote_port = port; +#if PPPOL2TP_AUTH_SUPPORT + l2tp->secret = secret; + l2tp->secret_len = secret_len; +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + return ppp; + +ppp_new_failed: + udp_remove(udp); +udp_new_failed: + LWIP_MEMPOOL_FREE(PPPOL2TP_PCB, l2tp); +memp_malloc_l2tp_failed: +ipaddr_check_failed: + return NULL; +} + +/* Called by PPP core */ +static err_t pppol2tp_write(ppp_pcb *ppp, void *ctx, struct pbuf *p) { + pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx; + struct pbuf *ph; /* UDP + L2TP header */ + err_t ret; +#if MIB2_STATS + u16_t tot_len; +#else /* MIB2_STATS */ + LWIP_UNUSED_ARG(ppp); +#endif /* MIB2_STATS */ + + ph = pbuf_alloc(PBUF_TRANSPORT, (u16_t)(PPPOL2TP_OUTPUT_DATA_HEADER_LEN), PBUF_RAM); + if(!ph) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + pbuf_free(p); + return ERR_MEM; + } + + pbuf_remove_header(ph, PPPOL2TP_OUTPUT_DATA_HEADER_LEN); /* hide L2TP header */ + pbuf_cat(ph, p); +#if MIB2_STATS + tot_len = ph->tot_len; +#endif /* MIB2_STATS */ + + ret = pppol2tp_xmit(l2tp, ph); + if (ret != ERR_OK) { + LINK_STATS_INC(link.err); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + return ret; + } + + MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, (u16_t)tot_len); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts); + LINK_STATS_INC(link.xmit); + return ERR_OK; +} + +/* Called by PPP core */ +static err_t pppol2tp_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *p, u_short protocol) { + pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx; + struct pbuf *pb; + u8_t *pl; + err_t err; +#if MIB2_STATS + u16_t tot_len; +#else /* MIB2_STATS */ + LWIP_UNUSED_ARG(ppp); +#endif /* MIB2_STATS */ + + /* @todo: try to use pbuf_header() here! */ + pb = pbuf_alloc(PBUF_TRANSPORT, PPPOL2TP_OUTPUT_DATA_HEADER_LEN + sizeof(protocol), PBUF_RAM); + if(!pb) { + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.proterr); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + return ERR_MEM; + } + + pbuf_remove_header(pb, PPPOL2TP_OUTPUT_DATA_HEADER_LEN); + + pl = (u8_t*)pb->payload; + PUTSHORT(protocol, pl); + + pbuf_chain(pb, p); +#if MIB2_STATS + tot_len = pb->tot_len; +#endif /* MIB2_STATS */ + + if( (err = pppol2tp_xmit(l2tp, pb)) != ERR_OK) { + LINK_STATS_INC(link.err); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + return err; + } + + MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, tot_len); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts); + LINK_STATS_INC(link.xmit); + return ERR_OK; +} + +/* Destroy a L2TP control block */ +static err_t pppol2tp_destroy(ppp_pcb *ppp, void *ctx) { + pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx; + LWIP_UNUSED_ARG(ppp); + + sys_untimeout(pppol2tp_timeout, l2tp); + udp_remove(l2tp->udp); + LWIP_MEMPOOL_FREE(PPPOL2TP_PCB, l2tp); + return ERR_OK; +} + +/* Be a LAC, connect to a LNS. */ +static void pppol2tp_connect(ppp_pcb *ppp, void *ctx) { + err_t err; + pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx; + lcp_options *lcp_wo; + lcp_options *lcp_ao; +#if PPP_IPV4_SUPPORT && VJ_SUPPORT + ipcp_options *ipcp_wo; + ipcp_options *ipcp_ao; +#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */ + + l2tp->tunnel_port = l2tp->remote_port; + l2tp->our_ns = 0; + l2tp->peer_nr = 0; + l2tp->peer_ns = 0; + l2tp->source_tunnel_id = 0; + l2tp->remote_tunnel_id = 0; + l2tp->source_session_id = 0; + l2tp->remote_session_id = 0; + /* l2tp->*_retried are cleared when used */ + + lcp_wo = &ppp->lcp_wantoptions; + lcp_wo->mru = PPPOL2TP_DEFMRU; + lcp_wo->neg_asyncmap = 0; + lcp_wo->neg_pcompression = 0; + lcp_wo->neg_accompression = 0; + lcp_wo->passive = 0; + lcp_wo->silent = 0; + + lcp_ao = &ppp->lcp_allowoptions; + lcp_ao->mru = PPPOL2TP_DEFMRU; + lcp_ao->neg_asyncmap = 0; + lcp_ao->neg_pcompression = 0; + lcp_ao->neg_accompression = 0; + +#if PPP_IPV4_SUPPORT && VJ_SUPPORT + ipcp_wo = &ppp->ipcp_wantoptions; + ipcp_wo->neg_vj = 0; + ipcp_wo->old_vj = 0; + + ipcp_ao = &ppp->ipcp_allowoptions; + ipcp_ao->neg_vj = 0; + ipcp_ao->old_vj = 0; +#endif /* PPP_IPV4_SUPPORT && VJ_SUPPORT */ + + /* Listen to a random source port, we need to do that instead of using udp_connect() + * because the L2TP LNS might answer with its own random source port (!= 1701) + */ +#if LWIP_IPV6 + if (IP_IS_V6_VAL(l2tp->udp->local_ip)) { + udp_bind(l2tp->udp, IP6_ADDR_ANY, 0); + } else +#endif /* LWIP_IPV6 */ + udp_bind(l2tp->udp, IP_ADDR_ANY, 0); + +#if PPPOL2TP_AUTH_SUPPORT + /* Generate random vector */ + if (l2tp->secret != NULL) { + magic_random_bytes(l2tp->secret_rv, sizeof(l2tp->secret_rv)); + } +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + do { + l2tp->remote_tunnel_id = magic(); + } while(l2tp->remote_tunnel_id == 0); + /* save state, in case we fail to send SCCRQ */ + l2tp->sccrq_retried = 0; + l2tp->phase = PPPOL2TP_STATE_SCCRQ_SENT; + if ((err = pppol2tp_send_sccrq(l2tp)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCRQ, error=%d\n", err)); + } + sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp); +} + +/* Disconnect */ +static void pppol2tp_disconnect(ppp_pcb *ppp, void *ctx) { + pppol2tp_pcb *l2tp = (pppol2tp_pcb *)ctx; + + l2tp->our_ns++; + pppol2tp_send_stopccn(l2tp, l2tp->our_ns); + + /* stop any timer, disconnect can be called while initiating is in progress */ + sys_untimeout(pppol2tp_timeout, l2tp); + l2tp->phase = PPPOL2TP_STATE_INITIAL; + ppp_link_end(ppp); /* notify upper layers */ +} + +/* UDP Callback for incoming IPv4 L2TP frames */ +static void pppol2tp_input(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, u16_t port) { + pppol2tp_pcb *l2tp = (pppol2tp_pcb*)arg; + u16_t hflags, hlen, len=0, tunnel_id=0, session_id=0, ns=0, nr=0, offset=0; + u8_t *inp; + LWIP_UNUSED_ARG(pcb); + + /* we can't unbound a UDP pcb, thus we can still receive UDP frames after the link is closed */ + if (l2tp->phase < PPPOL2TP_STATE_SCCRQ_SENT) { + goto free_and_return; + } + + if (!ip_addr_cmp(&l2tp->remote_ip, addr)) { + goto free_and_return; + } + + /* discard packet if port mismatch, but only if we received a SCCRP */ + if (l2tp->phase > PPPOL2TP_STATE_SCCRQ_SENT && l2tp->tunnel_port != port) { + goto free_and_return; + } + + /* printf("-----------\nL2TP INPUT, %d\n", p->len); */ + + /* L2TP header */ + if (p->len < sizeof(hflags) + sizeof(tunnel_id) + sizeof(session_id) ) { + goto packet_too_short; + } + + inp = (u8_t*)p->payload; + GETSHORT(hflags, inp); + + if (hflags & PPPOL2TP_HEADERFLAG_CONTROL) { + /* check mandatory flags for a control packet */ + if ( (hflags & PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY) != PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY ) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: mandatory header flags for control packet not set\n")); + goto free_and_return; + } + /* check forbidden flags for a control packet */ + if (hflags & PPPOL2TP_HEADERFLAG_CONTROL_FORBIDDEN) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: forbidden header flags for control packet found\n")); + goto free_and_return; + } + } else { + /* check mandatory flags for a data packet */ + if ( (hflags & PPPOL2TP_HEADERFLAG_DATA_MANDATORY) != PPPOL2TP_HEADERFLAG_DATA_MANDATORY) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: mandatory header flags for data packet not set\n")); + goto free_and_return; + } + } + + /* Expected header size */ + hlen = sizeof(hflags) + sizeof(tunnel_id) + sizeof(session_id); + if (hflags & PPPOL2TP_HEADERFLAG_LENGTH) { + hlen += sizeof(len); + } + if (hflags & PPPOL2TP_HEADERFLAG_SEQUENCE) { + hlen += sizeof(ns) + sizeof(nr); + } + if (hflags & PPPOL2TP_HEADERFLAG_OFFSET) { + hlen += sizeof(offset); + } + if (p->len < hlen) { + goto packet_too_short; + } + + if (hflags & PPPOL2TP_HEADERFLAG_LENGTH) { + GETSHORT(len, inp); + if (p->len < len || len < hlen) { + goto packet_too_short; + } + } + GETSHORT(tunnel_id, inp); + GETSHORT(session_id, inp); + if (hflags & PPPOL2TP_HEADERFLAG_SEQUENCE) { + GETSHORT(ns, inp); + GETSHORT(nr, inp); + } + if (hflags & PPPOL2TP_HEADERFLAG_OFFSET) { + GETSHORT(offset, inp) + if (offset > 4096) { /* don't be fooled with large offset which might overflow hlen */ + PPPDEBUG(LOG_DEBUG, ("pppol2tp: strange packet received, offset=%d\n", offset)); + goto free_and_return; + } + hlen += offset; + if (p->len < hlen) { + goto packet_too_short; + } + INCPTR(offset, inp); + } + + /* printf("HLEN = %d\n", hlen); */ + + /* skip L2TP header */ + if (pbuf_remove_header(p, hlen) != 0) { + goto free_and_return; + } + + /* printf("LEN=%d, TUNNEL_ID=%d, SESSION_ID=%d, NS=%d, NR=%d, OFFSET=%d\n", len, tunnel_id, session_id, ns, nr, offset); */ + PPPDEBUG(LOG_DEBUG, ("pppol2tp: input packet, len=%"U16_F", tunnel=%"U16_F", session=%"U16_F", ns=%"U16_F", nr=%"U16_F"\n", + len, tunnel_id, session_id, ns, nr)); + + /* Control packet */ + if (hflags & PPPOL2TP_HEADERFLAG_CONTROL) { + pppol2tp_dispatch_control_packet(l2tp, port, p, ns, nr); + goto free_and_return; + } + + /* Data packet */ + if(l2tp->phase != PPPOL2TP_STATE_DATA) { + goto free_and_return; + } + if(tunnel_id != l2tp->remote_tunnel_id) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: tunnel ID mismatch, assigned=%d, received=%d\n", l2tp->remote_tunnel_id, tunnel_id)); + goto free_and_return; + } + if(session_id != l2tp->remote_session_id) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: session ID mismatch, assigned=%d, received=%d\n", l2tp->remote_session_id, session_id)); + goto free_and_return; + } + /* + * skip address & flags if necessary + * + * RFC 2661 does not specify whether the PPP frame in the L2TP payload should + * have a HDLC header or not. We handle both cases for compatibility. + */ + if (p->len >= 2) { + GETSHORT(hflags, inp); + if (hflags == 0xff03) { + pbuf_remove_header(p, 2); + } + } + /* Dispatch the packet thereby consuming it. */ + ppp_input(l2tp->ppp, p); + return; + +packet_too_short: + PPPDEBUG(LOG_DEBUG, ("pppol2tp: packet too short: %d\n", p->len)); +free_and_return: + pbuf_free(p); +} + +/* L2TP Control packet entry point */ +static void pppol2tp_dispatch_control_packet(pppol2tp_pcb *l2tp, u16_t port, struct pbuf *p, u16_t ns, u16_t nr) { + u8_t *inp; + u16_t avplen, avpflags, vendorid, attributetype, messagetype=0; + err_t err; +#if PPPOL2TP_AUTH_SUPPORT + lwip_md5_context md5_ctx; + u8_t md5_hash[16]; + u8_t challenge_id = 0; +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + /* printf("L2TP CTRL INPUT, ns=%d, nr=%d, len=%d\n", ns, nr, p->len); */ + + /* Drop unexpected packet */ + if (ns != l2tp->peer_ns) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: drop unexpected packet: received NS=%d, expected NS=%d\n", ns, l2tp->peer_ns)); + /* + * In order to ensure that all messages are acknowledged properly + * (particularly in the case of a lost ZLB ACK message), receipt + * of duplicate messages MUST be acknowledged. + * + * In this very special case we Ack a packet we previously received. + * Therefore our NS is the NR we just received. And our NR is the + * NS we just received plus one. + */ + if ((s16_t)(ns - l2tp->peer_ns) < 0) { + pppol2tp_send_zlb(l2tp, nr, ns+1); + } + return; + } + + l2tp->peer_nr = nr; + + /* Handle the special case of the ICCN acknowledge */ + if (l2tp->phase == PPPOL2TP_STATE_ICCN_SENT && (s16_t)(l2tp->peer_nr - l2tp->our_ns) > 0) { + l2tp->phase = PPPOL2TP_STATE_DATA; + sys_untimeout(pppol2tp_timeout, l2tp); + ppp_start(l2tp->ppp); /* notify upper layers */ + } + + /* ZLB packets */ + if (p->tot_len == 0) { + return; + } + /* A ZLB packet does not consume a NS slot thus we don't record the NS value for ZLB packets */ + l2tp->peer_ns = ns+1; + + p = pbuf_coalesce(p, PBUF_RAW); + inp = (u8_t*)p->payload; + /* Decode AVPs */ + while (p->len > 0) { + if (p->len < sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype) ) { + goto packet_too_short; + } + GETSHORT(avpflags, inp); + avplen = avpflags & PPPOL2TP_AVPHEADERFLAG_LENGTHMASK; + /* printf("AVPLEN = %d\n", avplen); */ + if (p->len < avplen || avplen < sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype)) { + goto packet_too_short; + } + GETSHORT(vendorid, inp); + GETSHORT(attributetype, inp); + avplen -= sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype); + + /* Message type must be the first AVP */ + if (messagetype == 0) { + if (attributetype != 0 || vendorid != 0 || avplen != sizeof(messagetype) ) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: message type must be the first AVP\n")); + return; + } + GETSHORT(messagetype, inp); + /* printf("Message type = %d\n", messagetype); */ + switch(messagetype) { + /* Start Control Connection Reply */ + case PPPOL2TP_MESSAGETYPE_SCCRP: + /* Only accept SCCRP packet if we sent a SCCRQ */ + if (l2tp->phase != PPPOL2TP_STATE_SCCRQ_SENT) { + goto send_zlb; + } + break; + /* Incoming Call Reply */ + case PPPOL2TP_MESSAGETYPE_ICRP: + /* Only accept ICRP packet if we sent a IRCQ */ + if (l2tp->phase != PPPOL2TP_STATE_ICRQ_SENT) { + goto send_zlb; + } + break; + /* Stop Control Connection Notification */ + case PPPOL2TP_MESSAGETYPE_STOPCCN: + pppol2tp_send_zlb(l2tp, l2tp->our_ns+1, l2tp->peer_ns); /* Ack the StopCCN before we switch to down state */ + if (l2tp->phase < PPPOL2TP_STATE_DATA) { + pppol2tp_abort_connect(l2tp); + } else if (l2tp->phase == PPPOL2TP_STATE_DATA) { + /* Don't disconnect here, we let the LCP Echo/Reply find the fact + * that PPP session is down. Asking the PPP stack to end the session + * require strict checking about the PPP phase to prevent endless + * disconnection loops. + */ + } + return; + default: + break; + } + goto nextavp; + } + + /* Skip proprietary L2TP extensions */ + if (vendorid != 0) { + goto skipavp; + } + + switch (messagetype) { + /* Start Control Connection Reply */ + case PPPOL2TP_MESSAGETYPE_SCCRP: + switch (attributetype) { + case PPPOL2TP_AVPTYPE_TUNNELID: + if (avplen != sizeof(l2tp->source_tunnel_id) ) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: AVP Assign tunnel ID length check failed\n")); + return; + } + GETSHORT(l2tp->source_tunnel_id, inp); + PPPDEBUG(LOG_DEBUG, ("pppol2tp: Assigned tunnel ID %"U16_F"\n", l2tp->source_tunnel_id)); + goto nextavp; +#if PPPOL2TP_AUTH_SUPPORT + case PPPOL2TP_AVPTYPE_CHALLENGE: + if (avplen == 0) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: Challenge length check failed\n")); + return; + } + if (l2tp->secret == NULL) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: Received challenge from peer and no secret key available\n")); + pppol2tp_abort_connect(l2tp); + return; + } + /* Generate hash of ID, secret, challenge */ + lwip_md5_init(&md5_ctx); + lwip_md5_starts(&md5_ctx); + challenge_id = PPPOL2TP_MESSAGETYPE_SCCCN; + lwip_md5_update(&md5_ctx, &challenge_id, 1); + lwip_md5_update(&md5_ctx, l2tp->secret, l2tp->secret_len); + lwip_md5_update(&md5_ctx, inp, avplen); + lwip_md5_finish(&md5_ctx, l2tp->challenge_hash); + lwip_md5_free(&md5_ctx); + l2tp->send_challenge = 1; + goto skipavp; + case PPPOL2TP_AVPTYPE_CHALLENGERESPONSE: + if (avplen != PPPOL2TP_AVPTYPE_CHALLENGERESPONSE_SIZE) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: AVP Challenge Response length check failed\n")); + return; + } + /* Generate hash of ID, secret, challenge */ + lwip_md5_init(&md5_ctx); + lwip_md5_starts(&md5_ctx); + challenge_id = PPPOL2TP_MESSAGETYPE_SCCRP; + lwip_md5_update(&md5_ctx, &challenge_id, 1); + lwip_md5_update(&md5_ctx, l2tp->secret, l2tp->secret_len); + lwip_md5_update(&md5_ctx, l2tp->secret_rv, sizeof(l2tp->secret_rv)); + lwip_md5_finish(&md5_ctx, md5_hash); + lwip_md5_free(&md5_ctx); + if ( memcmp(inp, md5_hash, sizeof(md5_hash)) ) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: Received challenge response from peer and secret key do not match\n")); + pppol2tp_abort_connect(l2tp); + return; + } + goto skipavp; +#endif /* PPPOL2TP_AUTH_SUPPORT */ + default: + break; + } + break; + /* Incoming Call Reply */ + case PPPOL2TP_MESSAGETYPE_ICRP: + switch (attributetype) { + case PPPOL2TP_AVPTYPE_SESSIONID: + if (avplen != sizeof(l2tp->source_session_id) ) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: AVP Assign session ID length check failed\n")); + return; + } + GETSHORT(l2tp->source_session_id, inp); + PPPDEBUG(LOG_DEBUG, ("pppol2tp: Assigned session ID %"U16_F"\n", l2tp->source_session_id)); + goto nextavp; + default: + break; + } + break; + default: + break; + } + +skipavp: + INCPTR(avplen, inp); +nextavp: + /* printf("AVP Found, vendor=%d, attribute=%d, len=%d\n", vendorid, attributetype, avplen); */ + /* next AVP */ + if (pbuf_remove_header(p, avplen + sizeof(avpflags) + sizeof(vendorid) + sizeof(attributetype)) != 0) { + return; + } + } + + switch(messagetype) { + /* Start Control Connection Reply */ + case PPPOL2TP_MESSAGETYPE_SCCRP: + do { + l2tp->remote_session_id = magic(); + } while(l2tp->remote_session_id == 0); + l2tp->tunnel_port = port; /* LNS server might have chosen its own local port */ + l2tp->icrq_retried = 0; + l2tp->phase = PPPOL2TP_STATE_ICRQ_SENT; + l2tp->our_ns++; + if ((err = pppol2tp_send_scccn(l2tp, l2tp->our_ns)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCCN, error=%d\n", err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + l2tp->our_ns++; + if ((err = pppol2tp_send_icrq(l2tp, l2tp->our_ns)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICRQ, error=%d\n", err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_untimeout(pppol2tp_timeout, l2tp); + sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp); + break; + /* Incoming Call Reply */ + case PPPOL2TP_MESSAGETYPE_ICRP: + l2tp->iccn_retried = 0; + l2tp->phase = PPPOL2TP_STATE_ICCN_SENT; + l2tp->our_ns++; + if ((err = pppol2tp_send_iccn(l2tp, l2tp->our_ns)) != 0) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICCN, error=%d\n", err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_untimeout(pppol2tp_timeout, l2tp); + sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp); + break; + /* Unhandled packet, send ZLB ACK */ + default: + goto send_zlb; + } + return; + +send_zlb: + pppol2tp_send_zlb(l2tp, l2tp->our_ns+1, l2tp->peer_ns); + return; +packet_too_short: + PPPDEBUG(LOG_DEBUG, ("pppol2tp: packet too short: %d\n", p->len)); +} + +/* L2TP Timeout handler */ +static void pppol2tp_timeout(void *arg) { + pppol2tp_pcb *l2tp = (pppol2tp_pcb*)arg; + err_t err; + u32_t retry_wait; + + PPPDEBUG(LOG_DEBUG, ("pppol2tp: timeout\n")); + + switch (l2tp->phase) { + case PPPOL2TP_STATE_SCCRQ_SENT: + /* backoff wait */ + if (l2tp->sccrq_retried < 0xff) { + l2tp->sccrq_retried++; + } + if (!l2tp->ppp->settings.persist && l2tp->sccrq_retried >= PPPOL2TP_MAXSCCRQ) { + pppol2tp_abort_connect(l2tp); + return; + } + retry_wait = LWIP_MIN(PPPOL2TP_CONTROL_TIMEOUT * l2tp->sccrq_retried, PPPOL2TP_SLOW_RETRY); + PPPDEBUG(LOG_DEBUG, ("pppol2tp: sccrq_retried=%d\n", l2tp->sccrq_retried)); + if ((err = pppol2tp_send_sccrq(l2tp)) != 0) { + l2tp->sccrq_retried--; + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCRQ, error=%d\n", err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_timeout(retry_wait, pppol2tp_timeout, l2tp); + break; + + case PPPOL2TP_STATE_ICRQ_SENT: + l2tp->icrq_retried++; + if (l2tp->icrq_retried >= PPPOL2TP_MAXICRQ) { + pppol2tp_abort_connect(l2tp); + return; + } + PPPDEBUG(LOG_DEBUG, ("pppol2tp: icrq_retried=%d\n", l2tp->icrq_retried)); + if ((s16_t)(l2tp->peer_nr - l2tp->our_ns) < 0) { /* the SCCCN was not acknowledged */ + if ((err = pppol2tp_send_scccn(l2tp, l2tp->our_ns -1)) != 0) { + l2tp->icrq_retried--; + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send SCCCN, error=%d\n", err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp); + break; + } + } + if ((err = pppol2tp_send_icrq(l2tp, l2tp->our_ns)) != 0) { + l2tp->icrq_retried--; + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICRQ, error=%d\n", err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp); + break; + + case PPPOL2TP_STATE_ICCN_SENT: + l2tp->iccn_retried++; + if (l2tp->iccn_retried >= PPPOL2TP_MAXICCN) { + pppol2tp_abort_connect(l2tp); + return; + } + PPPDEBUG(LOG_DEBUG, ("pppol2tp: iccn_retried=%d\n", l2tp->iccn_retried)); + if ((err = pppol2tp_send_iccn(l2tp, l2tp->our_ns)) != 0) { + l2tp->iccn_retried--; + PPPDEBUG(LOG_DEBUG, ("pppol2tp: failed to send ICCN, error=%d\n", err)); + LWIP_UNUSED_ARG(err); /* if PPPDEBUG is disabled */ + } + sys_timeout(PPPOL2TP_CONTROL_TIMEOUT, pppol2tp_timeout, l2tp); + break; + + default: + return; /* all done, work in peace */ + } +} + +/* Connection attempt aborted */ +static void pppol2tp_abort_connect(pppol2tp_pcb *l2tp) { + PPPDEBUG(LOG_DEBUG, ("pppol2tp: could not establish connection\n")); + l2tp->phase = PPPOL2TP_STATE_INITIAL; + ppp_link_failed(l2tp->ppp); /* notify upper layers */ +} + +/* Initiate a new tunnel */ +static err_t pppol2tp_send_sccrq(pppol2tp_pcb *l2tp) { + struct pbuf *pb; + u8_t *p; + u16_t len; + + /* calculate UDP packet length */ + len = 12 +8 +8 +10 +10 +6+sizeof(PPPOL2TP_HOSTNAME)-1 +6+sizeof(PPPOL2TP_VENDORNAME)-1 +8 +8; +#if PPPOL2TP_AUTH_SUPPORT + if (l2tp->secret != NULL) { + len += 6 + sizeof(l2tp->secret_rv); + } +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + if (pb == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload; + /* fill in pkt */ + /* L2TP control header */ + PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p); + PUTSHORT(len, p); /* Length */ + PUTSHORT(0, p); /* Tunnel Id */ + PUTSHORT(0, p); /* Session Id */ + PUTSHORT(0, p); /* NS Sequence number - to peer */ + PUTSHORT(0, p); /* NR Sequence number - expected for peer */ + + /* AVP - Message type */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */ + PUTSHORT(PPPOL2TP_MESSAGETYPE_SCCRQ, p); /* Attribute value: Message type: SCCRQ */ + + /* AVP - L2TP Version */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_VERSION, p); /* Attribute type: Version */ + PUTSHORT(PPPOL2TP_VERSION, p); /* Attribute value: L2TP Version */ + + /* AVP - Framing capabilities */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_FRAMINGCAPABILITIES, p); /* Attribute type: Framing capabilities */ + PUTLONG(PPPOL2TP_FRAMINGCAPABILITIES, p); /* Attribute value: Framing capabilities */ + + /* AVP - Bearer capabilities */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_BEARERCAPABILITIES, p); /* Attribute type: Bearer capabilities */ + PUTLONG(PPPOL2TP_BEARERCAPABILITIES, p); /* Attribute value: Bearer capabilities */ + + /* AVP - Host name */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 6+sizeof(PPPOL2TP_HOSTNAME)-1, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_HOSTNAME, p); /* Attribute type: Hostname */ + MEMCPY(p, PPPOL2TP_HOSTNAME, sizeof(PPPOL2TP_HOSTNAME)-1); /* Attribute value: Hostname */ + INCPTR(sizeof(PPPOL2TP_HOSTNAME)-1, p); + + /* AVP - Vendor name */ + PUTSHORT(6+sizeof(PPPOL2TP_VENDORNAME)-1, p); /* len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_VENDORNAME, p); /* Attribute type: Vendor name */ + MEMCPY(p, PPPOL2TP_VENDORNAME, sizeof(PPPOL2TP_VENDORNAME)-1); /* Attribute value: Vendor name */ + INCPTR(sizeof(PPPOL2TP_VENDORNAME)-1, p); + + /* AVP - Assign tunnel ID */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_TUNNELID, p); /* Attribute type: Tunnel ID */ + PUTSHORT(l2tp->remote_tunnel_id, p); /* Attribute value: Tunnel ID */ + + /* AVP - Receive window size */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_RECEIVEWINDOWSIZE, p); /* Attribute type: Receive window size */ + PUTSHORT(PPPOL2TP_RECEIVEWINDOWSIZE, p); /* Attribute value: Receive window size */ + +#if PPPOL2TP_AUTH_SUPPORT + /* AVP - Challenge */ + if (l2tp->secret != NULL) { + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 6 + sizeof(l2tp->secret_rv), p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_CHALLENGE, p); /* Attribute type: Challenge */ + MEMCPY(p, l2tp->secret_rv, sizeof(l2tp->secret_rv)); /* Attribute value: Random vector */ + INCPTR(sizeof(l2tp->secret_rv), p); + } +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + return pppol2tp_udp_send(l2tp, pb); +} + +/* Complete tunnel establishment */ +static err_t pppol2tp_send_scccn(pppol2tp_pcb *l2tp, u16_t ns) { + struct pbuf *pb; + u8_t *p; + u16_t len; + + /* calculate UDP packet length */ + len = 12 +8; +#if PPPOL2TP_AUTH_SUPPORT + if (l2tp->send_challenge) { + len += 6 + sizeof(l2tp->challenge_hash); + } +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + if (pb == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload; + /* fill in pkt */ + /* L2TP control header */ + PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p); + PUTSHORT(len, p); /* Length */ + PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */ + PUTSHORT(0, p); /* Session Id */ + PUTSHORT(ns, p); /* NS Sequence number - to peer */ + PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */ + + /* AVP - Message type */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */ + PUTSHORT(PPPOL2TP_MESSAGETYPE_SCCCN, p); /* Attribute value: Message type: SCCCN */ + +#if PPPOL2TP_AUTH_SUPPORT + /* AVP - Challenge response */ + if (l2tp->send_challenge) { + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 6 + sizeof(l2tp->challenge_hash), p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_CHALLENGERESPONSE, p); /* Attribute type: Challenge response */ + MEMCPY(p, l2tp->challenge_hash, sizeof(l2tp->challenge_hash)); /* Attribute value: Computed challenge */ + INCPTR(sizeof(l2tp->challenge_hash), p); + } +#endif /* PPPOL2TP_AUTH_SUPPORT */ + + return pppol2tp_udp_send(l2tp, pb); +} + +/* Initiate a new session */ +static err_t pppol2tp_send_icrq(pppol2tp_pcb *l2tp, u16_t ns) { + struct pbuf *pb; + u8_t *p; + u16_t len; + u32_t serialnumber; + + /* calculate UDP packet length */ + len = 12 +8 +8 +10; + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + if (pb == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload; + /* fill in pkt */ + /* L2TP control header */ + PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p); + PUTSHORT(len, p); /* Length */ + PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */ + PUTSHORT(0, p); /* Session Id */ + PUTSHORT(ns, p); /* NS Sequence number - to peer */ + PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */ + + /* AVP - Message type */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */ + PUTSHORT(PPPOL2TP_MESSAGETYPE_ICRQ, p); /* Attribute value: Message type: ICRQ */ + + /* AVP - Assign session ID */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_SESSIONID, p); /* Attribute type: Session ID */ + PUTSHORT(l2tp->remote_session_id, p); /* Attribute value: Session ID */ + + /* AVP - Call Serial Number */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_CALLSERIALNUMBER, p); /* Attribute type: Serial number */ + serialnumber = magic(); + PUTLONG(serialnumber, p); /* Attribute value: Serial number */ + + return pppol2tp_udp_send(l2tp, pb); +} + +/* Complete tunnel establishment */ +static err_t pppol2tp_send_iccn(pppol2tp_pcb *l2tp, u16_t ns) { + struct pbuf *pb; + u8_t *p; + u16_t len; + + /* calculate UDP packet length */ + len = 12 +8 +10 +10; + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + if (pb == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload; + /* fill in pkt */ + /* L2TP control header */ + PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p); + PUTSHORT(len, p); /* Length */ + PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */ + PUTSHORT(l2tp->source_session_id, p); /* Session Id */ + PUTSHORT(ns, p); /* NS Sequence number - to peer */ + PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */ + + /* AVP - Message type */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */ + PUTSHORT(PPPOL2TP_MESSAGETYPE_ICCN, p); /* Attribute value: Message type: ICCN */ + + /* AVP - Framing type */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_FRAMINGTYPE, p); /* Attribute type: Framing type */ + PUTLONG(PPPOL2TP_FRAMINGTYPE, p); /* Attribute value: Framing type */ + + /* AVP - TX Connect speed */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 10, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_TXCONNECTSPEED, p); /* Attribute type: TX Connect speed */ + PUTLONG(PPPOL2TP_TXCONNECTSPEED, p); /* Attribute value: TX Connect speed */ + + return pppol2tp_udp_send(l2tp, pb); +} + +/* Send a ZLB ACK packet */ +static err_t pppol2tp_send_zlb(pppol2tp_pcb *l2tp, u16_t ns, u16_t nr) { + struct pbuf *pb; + u8_t *p; + u16_t len; + + /* calculate UDP packet length */ + len = 12; + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + if (pb == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload; + /* fill in pkt */ + /* L2TP control header */ + PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p); + PUTSHORT(len, p); /* Length */ + PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */ + PUTSHORT(0, p); /* Session Id */ + PUTSHORT(ns, p); /* NS Sequence number - to peer */ + PUTSHORT(nr, p); /* NR Sequence number - expected for peer */ + + return pppol2tp_udp_send(l2tp, pb); +} + +/* Send a StopCCN packet */ +static err_t pppol2tp_send_stopccn(pppol2tp_pcb *l2tp, u16_t ns) { + struct pbuf *pb; + u8_t *p; + u16_t len; + + /* calculate UDP packet length */ + len = 12 +8 +8 +8; + + /* allocate a buffer */ + pb = pbuf_alloc(PBUF_TRANSPORT, len, PBUF_RAM); + if (pb == NULL) { + return ERR_MEM; + } + LWIP_ASSERT("pb->tot_len == pb->len", pb->tot_len == pb->len); + + p = (u8_t*)pb->payload; + /* fill in pkt */ + /* L2TP control header */ + PUTSHORT(PPPOL2TP_HEADERFLAG_CONTROL_MANDATORY, p); + PUTSHORT(len, p); /* Length */ + PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */ + PUTSHORT(0, p); /* Session Id */ + PUTSHORT(ns, p); /* NS Sequence number - to peer */ + PUTSHORT(l2tp->peer_ns, p); /* NR Sequence number - expected for peer */ + + /* AVP - Message type */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_MESSAGE, p); /* Attribute type: Message Type */ + PUTSHORT(PPPOL2TP_MESSAGETYPE_STOPCCN, p); /* Attribute value: Message type: StopCCN */ + + /* AVP - Assign tunnel ID */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_TUNNELID, p); /* Attribute type: Tunnel ID */ + PUTSHORT(l2tp->remote_tunnel_id, p); /* Attribute value: Tunnel ID */ + + /* AVP - Result code */ + PUTSHORT(PPPOL2TP_AVPHEADERFLAG_MANDATORY + 8, p); /* Mandatory flag + len field */ + PUTSHORT(0, p); /* Vendor ID */ + PUTSHORT(PPPOL2TP_AVPTYPE_RESULTCODE, p); /* Attribute type: Result code */ + PUTSHORT(PPPOL2TP_RESULTCODE, p); /* Attribute value: Result code */ + + return pppol2tp_udp_send(l2tp, pb); +} + +static err_t pppol2tp_xmit(pppol2tp_pcb *l2tp, struct pbuf *pb) { + u8_t *p; + + /* make room for L2TP header - should not fail */ + if (pbuf_add_header(pb, PPPOL2TP_OUTPUT_DATA_HEADER_LEN) != 0) { + /* bail out */ + PPPDEBUG(LOG_ERR, ("pppol2tp: pppol2tp_pcb: could not allocate room for L2TP header\n")); + LINK_STATS_INC(link.lenerr); + pbuf_free(pb); + return ERR_BUF; + } + + p = (u8_t*)pb->payload; + PUTSHORT(PPPOL2TP_HEADERFLAG_DATA_MANDATORY, p); + PUTSHORT(l2tp->source_tunnel_id, p); /* Tunnel Id */ + PUTSHORT(l2tp->source_session_id, p); /* Session Id */ + + return pppol2tp_udp_send(l2tp, pb); +} + +static err_t pppol2tp_udp_send(pppol2tp_pcb *l2tp, struct pbuf *pb) { + err_t err; + if (l2tp->netif) { + err = udp_sendto_if(l2tp->udp, pb, &l2tp->remote_ip, l2tp->tunnel_port, l2tp->netif); + } else { + err = udp_sendto(l2tp->udp, pb, &l2tp->remote_ip, l2tp->tunnel_port); + } + pbuf_free(pb); + return err; +} + +#endif /* PPP_SUPPORT && PPPOL2TP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c new file mode 100644 index 0000000..dff0255 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/pppos.c @@ -0,0 +1,895 @@ +/** + * @file + * Network Point to Point Protocol over Serial file. + * + */ + +/* + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PPPOS_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include + +#include "lwip/arch.h" +#include "lwip/err.h" +#include "lwip/pbuf.h" +#include "lwip/sys.h" +#include "lwip/memp.h" +#include "lwip/netif.h" +#include "lwip/snmp.h" +#include "lwip/priv/tcpip_priv.h" +#include "lwip/api.h" +#include "lwip/ip4.h" /* for ip4_input() */ + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/pppos.h" +#include "netif/ppp/vj.h" + +/* Memory pool */ +LWIP_MEMPOOL_DECLARE(PPPOS_PCB, MEMP_NUM_PPPOS_INTERFACES, sizeof(pppos_pcb), "PPPOS_PCB") + +/* callbacks called from PPP core */ +static err_t pppos_write(ppp_pcb *ppp, void *ctx, struct pbuf *p); +static err_t pppos_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *pb, u16_t protocol); +static void pppos_connect(ppp_pcb *ppp, void *ctx); +#if PPP_SERVER +static void pppos_listen(ppp_pcb *ppp, void *ctx); +#endif /* PPP_SERVER */ +static void pppos_disconnect(ppp_pcb *ppp, void *ctx); +static err_t pppos_destroy(ppp_pcb *ppp, void *ctx); +static void pppos_send_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp); +static void pppos_recv_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp); + +/* Prototypes for procedures local to this file. */ +#if PPP_INPROC_IRQ_SAFE +static void pppos_input_callback(void *arg); +#endif /* PPP_INPROC_IRQ_SAFE */ +static void pppos_input_free_current_packet(pppos_pcb *pppos); +static void pppos_input_drop(pppos_pcb *pppos); +static err_t pppos_output_append(pppos_pcb *pppos, err_t err, struct pbuf *nb, u8_t c, u8_t accm, u16_t *fcs); +static err_t pppos_output_last(pppos_pcb *pppos, err_t err, struct pbuf *nb, u16_t *fcs); + +/* Callbacks structure for PPP core */ +static const struct link_callbacks pppos_callbacks = { + pppos_connect, +#if PPP_SERVER + pppos_listen, +#endif /* PPP_SERVER */ + pppos_disconnect, + pppos_destroy, + pppos_write, + pppos_netif_output, + pppos_send_config, + pppos_recv_config +}; + +/* PPP's Asynchronous-Control-Character-Map. The mask array is used + * to select the specific bit for a character. */ +#define ESCAPE_P(accm, c) ((accm)[(c) >> 3] & 1 << (c & 0x07)) + +#if PPP_FCS_TABLE +/* + * FCS lookup table as calculated by genfcstab. + */ +static const u16_t fcstab[256] = { + 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, + 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, + 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, + 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, + 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd, + 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5, + 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c, + 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974, + 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb, + 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, + 0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, + 0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72, + 0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9, + 0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1, + 0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738, + 0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70, + 0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7, + 0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff, + 0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036, + 0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e, + 0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5, + 0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd, + 0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134, + 0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c, + 0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3, + 0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb, + 0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232, + 0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a, + 0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1, + 0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9, + 0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330, + 0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78 +}; +#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ fcstab[((fcs) ^ (c)) & 0xff]) +#else /* PPP_FCS_TABLE */ +/* The HDLC polynomial: X**0 + X**5 + X**12 + X**16 (0x8408) */ +#define PPP_FCS_POLYNOMIAL 0x8408 +static u16_t +ppp_get_fcs(u8_t byte) +{ + unsigned int octet; + int bit; + octet = byte; + for (bit = 8; bit-- > 0; ) { + octet = (octet & 0x01) ? ((octet >> 1) ^ PPP_FCS_POLYNOMIAL) : (octet >> 1); + } + return octet & 0xffff; +} +#define PPP_FCS(fcs, c) (((fcs) >> 8) ^ ppp_get_fcs(((fcs) ^ (c)) & 0xff)) +#endif /* PPP_FCS_TABLE */ + +/* + * Values for FCS calculations. + */ +#define PPP_INITFCS 0xffff /* Initial FCS value */ +#define PPP_GOODFCS 0xf0b8 /* Good final FCS value */ + +#if PPP_INPROC_IRQ_SAFE +#define PPPOS_DECL_PROTECT(lev) SYS_ARCH_DECL_PROTECT(lev) +#define PPPOS_PROTECT(lev) SYS_ARCH_PROTECT(lev) +#define PPPOS_UNPROTECT(lev) SYS_ARCH_UNPROTECT(lev) +#else +#define PPPOS_DECL_PROTECT(lev) +#define PPPOS_PROTECT(lev) +#define PPPOS_UNPROTECT(lev) +#endif /* PPP_INPROC_IRQ_SAFE */ + + +/* + * Create a new PPP connection using the given serial I/O device. + * + * Return 0 on success, an error code on failure. + */ +ppp_pcb *pppos_create(struct netif *pppif, pppos_output_cb_fn output_cb, + ppp_link_status_cb_fn link_status_cb, void *ctx_cb) +{ + pppos_pcb *pppos; + ppp_pcb *ppp; + LWIP_ASSERT_CORE_LOCKED(); + + pppos = (pppos_pcb *)LWIP_MEMPOOL_ALLOC(PPPOS_PCB); + if (pppos == NULL) { + return NULL; + } + + ppp = ppp_new(pppif, &pppos_callbacks, pppos, link_status_cb, ctx_cb); + if (ppp == NULL) { + LWIP_MEMPOOL_FREE(PPPOS_PCB, pppos); + return NULL; + } + + memset(pppos, 0, sizeof(pppos_pcb)); + pppos->ppp = ppp; + pppos->output_cb = output_cb; + return ppp; +} + +/* Called by PPP core */ +static err_t +pppos_write(ppp_pcb *ppp, void *ctx, struct pbuf *p) +{ + pppos_pcb *pppos = (pppos_pcb *)ctx; + u8_t *s; + struct pbuf *nb; + u16_t n; + u16_t fcs_out; + err_t err; + LWIP_UNUSED_ARG(ppp); + + /* Grab an output buffer. Using PBUF_POOL here for tx is ok since the pbuf + gets freed by 'pppos_output_last' before this function returns and thus + cannot starve rx. */ + nb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (nb == NULL) { + PPPDEBUG(LOG_WARNING, ("pppos_write[%d]: alloc fail\n", ppp->netif->num)); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + pbuf_free(p); + return ERR_MEM; + } + + /* Set nb->tot_len to actual payload length */ + nb->tot_len = p->len; + + /* If the link has been idle, we'll send a fresh flag character to + * flush any noise. */ + err = ERR_OK; + if ((sys_now() - pppos->last_xmit) >= PPP_MAXIDLEFLAG) { + err = pppos_output_append(pppos, err, nb, PPP_FLAG, 0, NULL); + } + + /* Load output buffer. */ + fcs_out = PPP_INITFCS; + s = (u8_t*)p->payload; + n = p->len; + while (n-- > 0) { + err = pppos_output_append(pppos, err, nb, *s++, 1, &fcs_out); + } + + err = pppos_output_last(pppos, err, nb, &fcs_out); + if (err == ERR_OK) { + PPPDEBUG(LOG_INFO, ("pppos_write[%d]: len=%d\n", ppp->netif->num, p->len)); + } else { + PPPDEBUG(LOG_WARNING, ("pppos_write[%d]: output failed len=%d\n", ppp->netif->num, p->len)); + } + pbuf_free(p); + return err; +} + +/* Called by PPP core */ +static err_t +pppos_netif_output(ppp_pcb *ppp, void *ctx, struct pbuf *pb, u16_t protocol) +{ + pppos_pcb *pppos = (pppos_pcb *)ctx; + struct pbuf *nb, *p; + u16_t fcs_out; + err_t err; + LWIP_UNUSED_ARG(ppp); + + /* Grab an output buffer. Using PBUF_POOL here for tx is ok since the pbuf + gets freed by 'pppos_output_last' before this function returns and thus + cannot starve rx. */ + nb = pbuf_alloc(PBUF_RAW, 0, PBUF_POOL); + if (nb == NULL) { + PPPDEBUG(LOG_WARNING, ("pppos_netif_output[%d]: alloc fail\n", ppp->netif->num)); + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + return ERR_MEM; + } + + /* Set nb->tot_len to actual payload length */ + nb->tot_len = pb->tot_len; + + /* If the link has been idle, we'll send a fresh flag character to + * flush any noise. */ + err = ERR_OK; + if ((sys_now() - pppos->last_xmit) >= PPP_MAXIDLEFLAG) { + err = pppos_output_append(pppos, err, nb, PPP_FLAG, 0, NULL); + } + + fcs_out = PPP_INITFCS; + if (!pppos->accomp) { + err = pppos_output_append(pppos, err, nb, PPP_ALLSTATIONS, 1, &fcs_out); + err = pppos_output_append(pppos, err, nb, PPP_UI, 1, &fcs_out); + } + if (!pppos->pcomp || protocol > 0xFF) { + err = pppos_output_append(pppos, err, nb, (protocol >> 8) & 0xFF, 1, &fcs_out); + } + err = pppos_output_append(pppos, err, nb, protocol & 0xFF, 1, &fcs_out); + + /* Load packet. */ + for(p = pb; p; p = p->next) { + u16_t n = p->len; + u8_t *s = (u8_t*)p->payload; + + while (n-- > 0) { + err = pppos_output_append(pppos, err, nb, *s++, 1, &fcs_out); + } + } + + err = pppos_output_last(pppos, err, nb, &fcs_out); + if (err == ERR_OK) { + PPPDEBUG(LOG_INFO, ("pppos_netif_output[%d]: proto=0x%"X16_F", len = %d\n", ppp->netif->num, protocol, pb->tot_len)); + } else { + PPPDEBUG(LOG_WARNING, ("pppos_netif_output[%d]: output failed proto=0x%"X16_F", len = %d\n", ppp->netif->num, protocol, pb->tot_len)); + } + return err; +} + +static void +pppos_connect(ppp_pcb *ppp, void *ctx) +{ + pppos_pcb *pppos = (pppos_pcb *)ctx; + PPPOS_DECL_PROTECT(lev); + +#if PPP_INPROC_IRQ_SAFE + /* input pbuf left over from last session? */ + pppos_input_free_current_packet(pppos); +#endif /* PPP_INPROC_IRQ_SAFE */ + + /* reset PPPoS control block to its initial state */ + memset(&pppos->last_xmit, 0, sizeof(pppos_pcb) - offsetof(pppos_pcb, last_xmit)); + + /* + * Default the in and out accm so that escape and flag characters + * are always escaped. + */ + pppos->in_accm[15] = 0x60; /* no need to protect since RX is not running */ + pppos->out_accm[15] = 0x60; + PPPOS_PROTECT(lev); + pppos->open = 1; + PPPOS_UNPROTECT(lev); + + /* + * Start the connection and handle incoming events (packet or timeout). + */ + PPPDEBUG(LOG_INFO, ("pppos_connect: unit %d: connecting\n", ppp->netif->num)); + ppp_start(ppp); /* notify upper layers */ +} + +#if PPP_SERVER +static void +pppos_listen(ppp_pcb *ppp, void *ctx) +{ + pppos_pcb *pppos = (pppos_pcb *)ctx; + PPPOS_DECL_PROTECT(lev); + +#if PPP_INPROC_IRQ_SAFE + /* input pbuf left over from last session? */ + pppos_input_free_current_packet(pppos); +#endif /* PPP_INPROC_IRQ_SAFE */ + + /* reset PPPoS control block to its initial state */ + memset(&pppos->last_xmit, 0, sizeof(pppos_pcb) - offsetof(pppos_pcb, last_xmit)); + + /* + * Default the in and out accm so that escape and flag characters + * are always escaped. + */ + pppos->in_accm[15] = 0x60; /* no need to protect since RX is not running */ + pppos->out_accm[15] = 0x60; + PPPOS_PROTECT(lev); + pppos->open = 1; + PPPOS_UNPROTECT(lev); + + /* + * Wait for something to happen. + */ + PPPDEBUG(LOG_INFO, ("pppos_listen: unit %d: listening\n", ppp->netif->num)); + ppp_start(ppp); /* notify upper layers */ +} +#endif /* PPP_SERVER */ + +static void +pppos_disconnect(ppp_pcb *ppp, void *ctx) +{ + pppos_pcb *pppos = (pppos_pcb *)ctx; + PPPOS_DECL_PROTECT(lev); + + PPPOS_PROTECT(lev); + pppos->open = 0; + PPPOS_UNPROTECT(lev); + + /* If PPP_INPROC_IRQ_SAFE is used we cannot call + * pppos_input_free_current_packet() here because + * rx IRQ might still call pppos_input(). + */ +#if !PPP_INPROC_IRQ_SAFE + /* input pbuf left ? */ + pppos_input_free_current_packet(pppos); +#endif /* !PPP_INPROC_IRQ_SAFE */ + + ppp_link_end(ppp); /* notify upper layers */ +} + +static err_t +pppos_destroy(ppp_pcb *ppp, void *ctx) +{ + pppos_pcb *pppos = (pppos_pcb *)ctx; + LWIP_UNUSED_ARG(ppp); + +#if PPP_INPROC_IRQ_SAFE + /* input pbuf left ? */ + pppos_input_free_current_packet(pppos); +#endif /* PPP_INPROC_IRQ_SAFE */ + + LWIP_MEMPOOL_FREE(PPPOS_PCB, pppos); + return ERR_OK; +} + +#if !NO_SYS && !PPP_INPROC_IRQ_SAFE +/** Pass received raw characters to PPPoS to be decoded through lwIP TCPIP thread. + * + * This is one of the only functions that may be called outside of the TCPIP thread! + * + * @param ppp PPP descriptor index, returned by pppos_create() + * @param s received data + * @param l length of received data + */ +err_t +pppos_input_tcpip(ppp_pcb *ppp, u8_t *s, int l) +{ + struct pbuf *p; + err_t err; + + p = pbuf_alloc(PBUF_RAW, l, PBUF_POOL); + if (!p) { + return ERR_MEM; + } + pbuf_take(p, s, l); + + err = tcpip_inpkt(p, ppp_netif(ppp), pppos_input_sys); + if (err != ERR_OK) { + pbuf_free(p); + } + return err; +} + +/* called from TCPIP thread */ +err_t pppos_input_sys(struct pbuf *p, struct netif *inp) { + ppp_pcb *ppp = (ppp_pcb*)inp->state; + struct pbuf *n; + LWIP_ASSERT_CORE_LOCKED(); + + for (n = p; n; n = n->next) { + pppos_input(ppp, (u8_t*)n->payload, n->len); + } + pbuf_free(p); + return ERR_OK; +} +#endif /* !NO_SYS && !PPP_INPROC_IRQ_SAFE */ + +/** PPPoS input helper struct, must be packed since it is stored + * to pbuf->payload, which might be unaligned. */ +#if PPP_INPROC_IRQ_SAFE +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct pppos_input_header { + PACK_STRUCT_FIELD(ppp_pcb *ppp); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif +#endif /* PPP_INPROC_IRQ_SAFE */ + +/** Pass received raw characters to PPPoS to be decoded. + * + * @param ppp PPP descriptor index, returned by pppos_create() + * @param s received data + * @param l length of received data + */ +void +pppos_input(ppp_pcb *ppp, u8_t *s, int l) +{ + pppos_pcb *pppos = (pppos_pcb *)ppp->link_ctx_cb; + struct pbuf *next_pbuf; + u8_t cur_char; + u8_t escaped; + PPPOS_DECL_PROTECT(lev); +#if !PPP_INPROC_IRQ_SAFE + LWIP_ASSERT_CORE_LOCKED(); +#endif + + PPPDEBUG(LOG_DEBUG, ("pppos_input[%d]: got %d bytes\n", ppp->netif->num, l)); + while (l-- > 0) { + cur_char = *s++; + + PPPOS_PROTECT(lev); + /* ppp_input can disconnect the interface, we need to abort to prevent a memory + * leak if there are remaining bytes because pppos_connect and pppos_listen + * functions expect input buffer to be free. Furthermore there are no real + * reason to continue reading bytes if we are disconnected. + */ + if (!pppos->open) { + PPPOS_UNPROTECT(lev); + return; + } + escaped = ESCAPE_P(pppos->in_accm, cur_char); + PPPOS_UNPROTECT(lev); + /* Handle special characters. */ + if (escaped) { + /* Check for escape sequences. */ + /* XXX Note that this does not handle an escaped 0x5d character which + * would appear as an escape character. Since this is an ASCII ']' + * and there is no reason that I know of to escape it, I won't complicate + * the code to handle this case. GLL */ + if (cur_char == PPP_ESCAPE) { + pppos->in_escaped = 1; + /* Check for the flag character. */ + } else if (cur_char == PPP_FLAG) { + /* If this is just an extra flag character, ignore it. */ + if (pppos->in_state <= PDADDRESS) { + /* ignore it */; + /* If we haven't received the packet header, drop what has come in. */ + } else if (pppos->in_state < PDDATA) { + PPPDEBUG(LOG_WARNING, + ("pppos_input[%d]: Dropping incomplete packet %d\n", + ppp->netif->num, pppos->in_state)); + LINK_STATS_INC(link.lenerr); + pppos_input_drop(pppos); + /* If the fcs is invalid, drop the packet. */ + } else if (pppos->in_fcs != PPP_GOODFCS) { + PPPDEBUG(LOG_INFO, + ("pppos_input[%d]: Dropping bad fcs 0x%"X16_F" proto=0x%"X16_F"\n", + ppp->netif->num, pppos->in_fcs, pppos->in_protocol)); + /* Note: If you get lots of these, check for UART frame errors or try different baud rate */ + LINK_STATS_INC(link.chkerr); + pppos_input_drop(pppos); + /* Otherwise it's a good packet so pass it on. */ + } else { + struct pbuf *inp; + /* Trim off the checksum. */ + if(pppos->in_tail->len > 2) { + pppos->in_tail->len -= 2; + + pppos->in_tail->tot_len = pppos->in_tail->len; + if (pppos->in_tail != pppos->in_head) { + pbuf_cat(pppos->in_head, pppos->in_tail); + } + } else { + pppos->in_tail->tot_len = pppos->in_tail->len; + if (pppos->in_tail != pppos->in_head) { + pbuf_cat(pppos->in_head, pppos->in_tail); + } + + pbuf_realloc(pppos->in_head, pppos->in_head->tot_len - 2); + } + + /* Dispatch the packet thereby consuming it. */ + inp = pppos->in_head; + /* Packet consumed, release our references. */ + pppos->in_head = NULL; + pppos->in_tail = NULL; +#if IP_FORWARD || LWIP_IPV6_FORWARD + /* hide the room for Ethernet forwarding header */ + pbuf_remove_header(inp, PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN); +#endif /* IP_FORWARD || LWIP_IPV6_FORWARD */ +#if PPP_INPROC_IRQ_SAFE + if(tcpip_try_callback(pppos_input_callback, inp) != ERR_OK) { + PPPDEBUG(LOG_ERR, ("pppos_input[%d]: tcpip_callback() failed, dropping packet\n", ppp->netif->num)); + pbuf_free(inp); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(ppp->netif, ifindiscards); + } +#else /* PPP_INPROC_IRQ_SAFE */ + ppp_input(ppp, inp); +#endif /* PPP_INPROC_IRQ_SAFE */ + } + + /* Prepare for a new packet. */ + pppos->in_fcs = PPP_INITFCS; + pppos->in_state = PDADDRESS; + pppos->in_escaped = 0; + /* Other characters are usually control characters that may have + * been inserted by the physical layer so here we just drop them. */ + } else { + PPPDEBUG(LOG_WARNING, + ("pppos_input[%d]: Dropping ACCM char <%d>\n", ppp->netif->num, cur_char)); + } + /* Process other characters. */ + } else { + /* Unencode escaped characters. */ + if (pppos->in_escaped) { + pppos->in_escaped = 0; + cur_char ^= PPP_TRANS; + } + + /* Process character relative to current state. */ + switch(pppos->in_state) { + case PDIDLE: /* Idle state - waiting. */ + /* Drop the character if it's not 0xff + * we would have processed a flag character above. */ + if (cur_char != PPP_ALLSTATIONS) { + break; + } + /* no break */ + /* Fall through */ + + case PDSTART: /* Process start flag. */ + /* Prepare for a new packet. */ + pppos->in_fcs = PPP_INITFCS; + /* no break */ + /* Fall through */ + + case PDADDRESS: /* Process address field. */ + if (cur_char == PPP_ALLSTATIONS) { + pppos->in_state = PDCONTROL; + break; + } + /* no break */ + + /* Else assume compressed address and control fields so + * fall through to get the protocol... */ + /* Fall through */ + case PDCONTROL: /* Process control field. */ + /* If we don't get a valid control code, restart. */ + if (cur_char == PPP_UI) { + pppos->in_state = PDPROTOCOL1; + break; + } + /* no break */ + +#if 0 + else { + PPPDEBUG(LOG_WARNING, + ("pppos_input[%d]: Invalid control <%d>\n", ppp->netif->num, cur_char)); + pppos->in_state = PDSTART; + } +#endif + /* Fall through */ + + case PDPROTOCOL1: /* Process protocol field 1. */ + /* If the lower bit is set, this is the end of the protocol + * field. */ + if (cur_char & 1) { + pppos->in_protocol = cur_char; + pppos->in_state = PDDATA; + } else { + pppos->in_protocol = (u16_t)cur_char << 8; + pppos->in_state = PDPROTOCOL2; + } + break; + case PDPROTOCOL2: /* Process protocol field 2. */ + pppos->in_protocol |= cur_char; + pppos->in_state = PDDATA; + break; + case PDDATA: /* Process data byte. */ + /* Make space to receive processed data. */ + if (pppos->in_tail == NULL || pppos->in_tail->len == PBUF_POOL_BUFSIZE) { + u16_t pbuf_alloc_len; + if (pppos->in_tail != NULL) { + pppos->in_tail->tot_len = pppos->in_tail->len; + if (pppos->in_tail != pppos->in_head) { + pbuf_cat(pppos->in_head, pppos->in_tail); + /* give up the in_tail reference now */ + pppos->in_tail = NULL; + } + } + /* If we haven't started a packet, we need a packet header. */ + pbuf_alloc_len = 0; +#if IP_FORWARD || LWIP_IPV6_FORWARD + /* If IP forwarding is enabled we are reserving PBUF_LINK_ENCAPSULATION_HLEN + * + PBUF_LINK_HLEN bytes so the packet is being allocated with enough header + * space to be forwarded (to Ethernet for example). + */ + if (pppos->in_head == NULL) { + pbuf_alloc_len = PBUF_LINK_ENCAPSULATION_HLEN + PBUF_LINK_HLEN; + } +#endif /* IP_FORWARD || LWIP_IPV6_FORWARD */ + next_pbuf = pbuf_alloc(PBUF_RAW, pbuf_alloc_len, PBUF_POOL); + if (next_pbuf == NULL) { + /* No free buffers. Drop the input packet and let the + * higher layers deal with it. Continue processing + * the received pbuf chain in case a new packet starts. */ + PPPDEBUG(LOG_ERR, ("pppos_input[%d]: NO FREE PBUFS!\n", ppp->netif->num)); + LINK_STATS_INC(link.memerr); + pppos_input_drop(pppos); + pppos->in_state = PDSTART; /* Wait for flag sequence. */ + break; + } + if (pppos->in_head == NULL) { + u8_t *payload = ((u8_t*)next_pbuf->payload) + pbuf_alloc_len; +#if PPP_INPROC_IRQ_SAFE + ((struct pppos_input_header*)payload)->ppp = ppp; + payload += sizeof(struct pppos_input_header); + next_pbuf->len += sizeof(struct pppos_input_header); +#endif /* PPP_INPROC_IRQ_SAFE */ + next_pbuf->len += sizeof(pppos->in_protocol); + *(payload++) = pppos->in_protocol >> 8; + *(payload) = pppos->in_protocol & 0xFF; + pppos->in_head = next_pbuf; + } + pppos->in_tail = next_pbuf; + } + /* Load character into buffer. */ + ((u8_t*)pppos->in_tail->payload)[pppos->in_tail->len++] = cur_char; + break; + default: + break; + } + + /* update the frame check sequence number. */ + pppos->in_fcs = PPP_FCS(pppos->in_fcs, cur_char); + } + } /* while (l-- > 0), all bytes processed */ +} + +#if PPP_INPROC_IRQ_SAFE +/* PPPoS input callback using one input pointer + */ +static void pppos_input_callback(void *arg) { + struct pbuf *pb = (struct pbuf*)arg; + ppp_pcb *ppp; + + ppp = ((struct pppos_input_header*)pb->payload)->ppp; + if(pbuf_remove_header(pb, sizeof(struct pppos_input_header))) { + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + goto drop; + } + + /* Dispatch the packet thereby consuming it. */ + ppp_input(ppp, pb); + return; + +drop: + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(ppp->netif, ifindiscards); + pbuf_free(pb); +} +#endif /* PPP_INPROC_IRQ_SAFE */ + +static void +pppos_send_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp) +{ + int i; + pppos_pcb *pppos = (pppos_pcb *)ctx; + LWIP_UNUSED_ARG(ppp); + + pppos->pcomp = pcomp; + pppos->accomp = accomp; + + /* Load the ACCM bits for the 32 control codes. */ + for (i = 0; i < 32/8; i++) { + pppos->out_accm[i] = (u8_t)((accm >> (8 * i)) & 0xFF); + } + + PPPDEBUG(LOG_INFO, ("pppos_send_config[%d]: out_accm=%X %X %X %X\n", + pppos->ppp->netif->num, + pppos->out_accm[0], pppos->out_accm[1], pppos->out_accm[2], pppos->out_accm[3])); +} + +static void +pppos_recv_config(ppp_pcb *ppp, void *ctx, u32_t accm, int pcomp, int accomp) +{ + int i; + pppos_pcb *pppos = (pppos_pcb *)ctx; + PPPOS_DECL_PROTECT(lev); + LWIP_UNUSED_ARG(ppp); + LWIP_UNUSED_ARG(pcomp); + LWIP_UNUSED_ARG(accomp); + + /* Load the ACCM bits for the 32 control codes. */ + PPPOS_PROTECT(lev); + for (i = 0; i < 32 / 8; i++) { + pppos->in_accm[i] = (u8_t)(accm >> (i * 8)); + } + PPPOS_UNPROTECT(lev); + + PPPDEBUG(LOG_INFO, ("pppos_recv_config[%d]: in_accm=%X %X %X %X\n", + pppos->ppp->netif->num, + pppos->in_accm[0], pppos->in_accm[1], pppos->in_accm[2], pppos->in_accm[3])); +} + +/* + * Drop the input packet. + */ +static void +pppos_input_free_current_packet(pppos_pcb *pppos) +{ + if (pppos->in_head != NULL) { + if (pppos->in_tail && (pppos->in_tail != pppos->in_head)) { + pbuf_free(pppos->in_tail); + } + pbuf_free(pppos->in_head); + pppos->in_head = NULL; + } + pppos->in_tail = NULL; +} + +/* + * Drop the input packet and increase error counters. + */ +static void +pppos_input_drop(pppos_pcb *pppos) +{ + if (pppos->in_head != NULL) { +#if 0 + PPPDEBUG(LOG_INFO, ("pppos_input_drop: %d:%.*H\n", pppos->in_head->len, min(60, pppos->in_head->len * 2), pppos->in_head->payload)); +#endif + PPPDEBUG(LOG_INFO, ("pppos_input_drop: pbuf len=%d, addr %p\n", pppos->in_head->len, (void*)pppos->in_head)); + } + pppos_input_free_current_packet(pppos); +#if VJ_SUPPORT + vj_uncompress_err(&pppos->ppp->vj_comp); +#endif /* VJ_SUPPORT */ + + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(pppos->ppp->netif, ifindiscards); +} + +/* + * pppos_output_append - append given character to end of given pbuf. + * If out_accm is not 0 and the character needs to be escaped, do so. + * If pbuf is full, send the pbuf and reuse it. + * Return the current pbuf. + */ +static err_t +pppos_output_append(pppos_pcb *pppos, err_t err, struct pbuf *nb, u8_t c, u8_t accm, u16_t *fcs) +{ + if (err != ERR_OK) { + return err; + } + + /* Make sure there is room for the character and an escape code. + * Sure we don't quite fill the buffer if the character doesn't + * get escaped but is one character worth complicating this? */ + if ((PBUF_POOL_BUFSIZE - nb->len) < 2) { + u32_t l = pppos->output_cb(pppos->ppp, (u8_t*)nb->payload, nb->len, pppos->ppp->ctx_cb); + if (l != nb->len) { + return ERR_IF; + } + nb->len = 0; + } + + /* Update FCS before checking for special characters. */ + if (fcs) { + *fcs = PPP_FCS(*fcs, c); + } + + /* Copy to output buffer escaping special characters. */ + if (accm && ESCAPE_P(pppos->out_accm, c)) { + *((u8_t*)nb->payload + nb->len++) = PPP_ESCAPE; + *((u8_t*)nb->payload + nb->len++) = c ^ PPP_TRANS; + } else { + *((u8_t*)nb->payload + nb->len++) = c; + } + + return ERR_OK; +} + +static err_t +pppos_output_last(pppos_pcb *pppos, err_t err, struct pbuf *nb, u16_t *fcs) +{ + ppp_pcb *ppp = pppos->ppp; + + /* Add FCS and trailing flag. */ + err = pppos_output_append(pppos, err, nb, ~(*fcs) & 0xFF, 1, NULL); + err = pppos_output_append(pppos, err, nb, (~(*fcs) >> 8) & 0xFF, 1, NULL); + err = pppos_output_append(pppos, err, nb, PPP_FLAG, 0, NULL); + + if (err != ERR_OK) { + goto failed; + } + + /* Send remaining buffer if not empty */ + if (nb->len > 0) { + u32_t l = pppos->output_cb(ppp, (u8_t*)nb->payload, nb->len, ppp->ctx_cb); + if (l != nb->len) { + err = ERR_IF; + goto failed; + } + } + + pppos->last_xmit = sys_now(); + MIB2_STATS_NETIF_ADD(ppp->netif, ifoutoctets, nb->tot_len); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutucastpkts); + LINK_STATS_INC(link.xmit); + pbuf_free(nb); + return ERR_OK; + +failed: + pppos->last_xmit = 0; /* prepend PPP_FLAG to next packet */ + LINK_STATS_INC(link.err); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(ppp->netif, ifoutdiscards); + pbuf_free(nb); + return err; +} + +#endif /* PPP_SUPPORT && PPPOS_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c new file mode 100644 index 0000000..3b2399d --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/upap.c @@ -0,0 +1,677 @@ +/* + * upap.c - User/Password Authentication Protocol. + * + * Copyright (c) 1984-2000 Carnegie Mellon University. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * 3. The name "Carnegie Mellon University" must not be used to + * endorse or promote products derived from this software without + * prior written permission. For permission or any legal + * details, please contact + * Office of Technology Transfer + * Carnegie Mellon University + * 5000 Forbes Avenue + * Pittsburgh, PA 15213-3890 + * (412) 268-4387, fax: (412) 268-7395 + * tech-transfer@andrew.cmu.edu + * + * 4. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Computing Services + * at Carnegie Mellon University (http://www.cmu.edu/computing/)." + * + * CARNEGIE MELLON UNIVERSITY DISCLAIMS ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY BE LIABLE + * FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && PAP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +/* + * @todo: + */ + +#if 0 /* UNUSED */ +#include +#include +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/upap.h" + +#if PPP_OPTIONS +/* + * Command-line options. + */ +static option_t pap_option_list[] = { + { "hide-password", o_bool, &hide_password, + "Don't output passwords to log", OPT_PRIO | 1 }, + { "show-password", o_bool, &hide_password, + "Show password string in debug log messages", OPT_PRIOSUB | 0 }, + + { "pap-restart", o_int, &upap[0].us_timeouttime, + "Set retransmit timeout for PAP", OPT_PRIO }, + { "pap-max-authreq", o_int, &upap[0].us_maxtransmits, + "Set max number of transmissions for auth-reqs", OPT_PRIO }, + { "pap-timeout", o_int, &upap[0].us_reqtimeout, + "Set time limit for peer PAP authentication", OPT_PRIO }, + + { NULL } +}; +#endif /* PPP_OPTIONS */ + +/* + * Protocol entry points. + */ +static void upap_init(ppp_pcb *pcb); +static void upap_lowerup(ppp_pcb *pcb); +static void upap_lowerdown(ppp_pcb *pcb); +static void upap_input(ppp_pcb *pcb, u_char *inpacket, int l); +static void upap_protrej(ppp_pcb *pcb); +#if PRINTPKT_SUPPORT +static int upap_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg); +#endif /* PRINTPKT_SUPPORT */ + +const struct protent pap_protent = { + PPP_PAP, + upap_init, + upap_input, + upap_protrej, + upap_lowerup, + upap_lowerdown, + NULL, + NULL, +#if PRINTPKT_SUPPORT + upap_printpkt, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_DATAINPUT + NULL, +#endif /* PPP_DATAINPUT */ +#if PRINTPKT_SUPPORT + "PAP", + NULL, +#endif /* PRINTPKT_SUPPORT */ +#if PPP_OPTIONS + pap_option_list, + NULL, +#endif /* PPP_OPTIONS */ +#if DEMAND_SUPPORT + NULL, + NULL +#endif /* DEMAND_SUPPORT */ +}; + +static void upap_timeout(void *arg); +#if PPP_SERVER +static void upap_reqtimeout(void *arg); +static void upap_rauthreq(ppp_pcb *pcb, u_char *inp, int id, int len); +#endif /* PPP_SERVER */ +static void upap_rauthack(ppp_pcb *pcb, u_char *inp, int id, int len); +static void upap_rauthnak(ppp_pcb *pcb, u_char *inp, int id, int len); +static void upap_sauthreq(ppp_pcb *pcb); +#if PPP_SERVER +static void upap_sresp(ppp_pcb *pcb, u_char code, u_char id, const char *msg, int msglen); +#endif /* PPP_SERVER */ + + +/* + * upap_init - Initialize a UPAP unit. + */ +static void upap_init(ppp_pcb *pcb) { + pcb->upap.us_user = NULL; + pcb->upap.us_userlen = 0; + pcb->upap.us_passwd = NULL; + pcb->upap.us_passwdlen = 0; + pcb->upap.us_clientstate = UPAPCS_INITIAL; +#if PPP_SERVER + pcb->upap.us_serverstate = UPAPSS_INITIAL; +#endif /* PPP_SERVER */ + pcb->upap.us_id = 0; +} + + +/* + * upap_authwithpeer - Authenticate us with our peer (start client). + * + * Set new state and send authenticate's. + */ +void upap_authwithpeer(ppp_pcb *pcb, const char *user, const char *password) { + + if(!user || !password) + return; + + /* Save the username and password we're given */ + pcb->upap.us_user = user; + pcb->upap.us_userlen = (u8_t)LWIP_MIN(strlen(user), 0xff); + pcb->upap.us_passwd = password; + pcb->upap.us_passwdlen = (u8_t)LWIP_MIN(strlen(password), 0xff); + pcb->upap.us_transmits = 0; + + /* Lower layer up yet? */ + if (pcb->upap.us_clientstate == UPAPCS_INITIAL || + pcb->upap.us_clientstate == UPAPCS_PENDING) { + pcb->upap.us_clientstate = UPAPCS_PENDING; + return; + } + + upap_sauthreq(pcb); /* Start protocol */ +} + +#if PPP_SERVER +/* + * upap_authpeer - Authenticate our peer (start server). + * + * Set new state. + */ +void upap_authpeer(ppp_pcb *pcb) { + + /* Lower layer up yet? */ + if (pcb->upap.us_serverstate == UPAPSS_INITIAL || + pcb->upap.us_serverstate == UPAPSS_PENDING) { + pcb->upap.us_serverstate = UPAPSS_PENDING; + return; + } + + pcb->upap.us_serverstate = UPAPSS_LISTEN; + if (pcb->settings.pap_req_timeout > 0) + TIMEOUT(upap_reqtimeout, pcb, pcb->settings.pap_req_timeout); +} +#endif /* PPP_SERVER */ + +/* + * upap_timeout - Retransmission timer for sending auth-reqs expired. + */ +static void upap_timeout(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + + if (pcb->upap.us_clientstate != UPAPCS_AUTHREQ) + return; + + if (pcb->upap.us_transmits >= pcb->settings.pap_max_transmits) { + /* give up in disgust */ + ppp_error("No response to PAP authenticate-requests"); + pcb->upap.us_clientstate = UPAPCS_BADAUTH; + auth_withpeer_fail(pcb, PPP_PAP); + return; + } + + upap_sauthreq(pcb); /* Send Authenticate-Request */ +} + + +#if PPP_SERVER +/* + * upap_reqtimeout - Give up waiting for the peer to send an auth-req. + */ +static void upap_reqtimeout(void *arg) { + ppp_pcb *pcb = (ppp_pcb*)arg; + + if (pcb->upap.us_serverstate != UPAPSS_LISTEN) + return; /* huh?? */ + + auth_peer_fail(pcb, PPP_PAP); + pcb->upap.us_serverstate = UPAPSS_BADAUTH; +} +#endif /* PPP_SERVER */ + + +/* + * upap_lowerup - The lower layer is up. + * + * Start authenticating if pending. + */ +static void upap_lowerup(ppp_pcb *pcb) { + + if (pcb->upap.us_clientstate == UPAPCS_INITIAL) + pcb->upap.us_clientstate = UPAPCS_CLOSED; + else if (pcb->upap.us_clientstate == UPAPCS_PENDING) { + upap_sauthreq(pcb); /* send an auth-request */ + } + +#if PPP_SERVER + if (pcb->upap.us_serverstate == UPAPSS_INITIAL) + pcb->upap.us_serverstate = UPAPSS_CLOSED; + else if (pcb->upap.us_serverstate == UPAPSS_PENDING) { + pcb->upap.us_serverstate = UPAPSS_LISTEN; + if (pcb->settings.pap_req_timeout > 0) + TIMEOUT(upap_reqtimeout, pcb, pcb->settings.pap_req_timeout); + } +#endif /* PPP_SERVER */ +} + + +/* + * upap_lowerdown - The lower layer is down. + * + * Cancel all timeouts. + */ +static void upap_lowerdown(ppp_pcb *pcb) { + + if (pcb->upap.us_clientstate == UPAPCS_AUTHREQ) /* Timeout pending? */ + UNTIMEOUT(upap_timeout, pcb); /* Cancel timeout */ +#if PPP_SERVER + if (pcb->upap.us_serverstate == UPAPSS_LISTEN && pcb->settings.pap_req_timeout > 0) + UNTIMEOUT(upap_reqtimeout, pcb); +#endif /* PPP_SERVER */ + + pcb->upap.us_clientstate = UPAPCS_INITIAL; +#if PPP_SERVER + pcb->upap.us_serverstate = UPAPSS_INITIAL; +#endif /* PPP_SERVER */ +} + + +/* + * upap_protrej - Peer doesn't speak this protocol. + * + * This shouldn't happen. In any case, pretend lower layer went down. + */ +static void upap_protrej(ppp_pcb *pcb) { + + if (pcb->upap.us_clientstate == UPAPCS_AUTHREQ) { + ppp_error("PAP authentication failed due to protocol-reject"); + auth_withpeer_fail(pcb, PPP_PAP); + } +#if PPP_SERVER + if (pcb->upap.us_serverstate == UPAPSS_LISTEN) { + ppp_error("PAP authentication of peer failed (protocol-reject)"); + auth_peer_fail(pcb, PPP_PAP); + } +#endif /* PPP_SERVER */ + upap_lowerdown(pcb); +} + + +/* + * upap_input - Input UPAP packet. + */ +static void upap_input(ppp_pcb *pcb, u_char *inpacket, int l) { + u_char *inp; + u_char code, id; + int len; + + /* + * Parse header (code, id and length). + * If packet too short, drop it. + */ + inp = inpacket; + if (l < UPAP_HEADERLEN) { + UPAPDEBUG(("pap_input: rcvd short header.")); + return; + } + GETCHAR(code, inp); + GETCHAR(id, inp); + GETSHORT(len, inp); + if (len < UPAP_HEADERLEN) { + UPAPDEBUG(("pap_input: rcvd illegal length.")); + return; + } + if (len > l) { + UPAPDEBUG(("pap_input: rcvd short packet.")); + return; + } + len -= UPAP_HEADERLEN; + + /* + * Action depends on code. + */ + switch (code) { + case UPAP_AUTHREQ: +#if PPP_SERVER + upap_rauthreq(pcb, inp, id, len); +#endif /* PPP_SERVER */ + break; + + case UPAP_AUTHACK: + upap_rauthack(pcb, inp, id, len); + break; + + case UPAP_AUTHNAK: + upap_rauthnak(pcb, inp, id, len); + break; + + default: /* XXX Need code reject */ + break; + } +} + +#if PPP_SERVER +/* + * upap_rauth - Receive Authenticate. + */ +static void upap_rauthreq(ppp_pcb *pcb, u_char *inp, int id, int len) { + u_char ruserlen, rpasswdlen; + char *ruser; + char *rpasswd; + char rhostname[256]; + int retcode; + const char *msg; + int msglen; + + if (pcb->upap.us_serverstate < UPAPSS_LISTEN) + return; + + /* + * If we receive a duplicate authenticate-request, we are + * supposed to return the same status as for the first request. + */ + if (pcb->upap.us_serverstate == UPAPSS_OPEN) { + upap_sresp(pcb, UPAP_AUTHACK, id, "", 0); /* return auth-ack */ + return; + } + if (pcb->upap.us_serverstate == UPAPSS_BADAUTH) { + upap_sresp(pcb, UPAP_AUTHNAK, id, "", 0); /* return auth-nak */ + return; + } + + /* + * Parse user/passwd. + */ + if (len < 1) { + UPAPDEBUG(("pap_rauth: rcvd short packet.")); + return; + } + GETCHAR(ruserlen, inp); + len -= sizeof (u_char) + ruserlen + sizeof (u_char); + if (len < 0) { + UPAPDEBUG(("pap_rauth: rcvd short packet.")); + return; + } + ruser = (char *) inp; + INCPTR(ruserlen, inp); + GETCHAR(rpasswdlen, inp); + if (len < rpasswdlen) { + UPAPDEBUG(("pap_rauth: rcvd short packet.")); + return; + } + + rpasswd = (char *) inp; + + /* + * Check the username and password given. + */ + retcode = UPAP_AUTHNAK; + if (auth_check_passwd(pcb, ruser, ruserlen, rpasswd, rpasswdlen, &msg, &msglen)) { + retcode = UPAP_AUTHACK; + } + BZERO(rpasswd, rpasswdlen); + +#if 0 /* UNUSED */ + /* + * Check remote number authorization. A plugin may have filled in + * the remote number or added an allowed number, and rather than + * return an authenticate failure, is leaving it for us to verify. + */ + if (retcode == UPAP_AUTHACK) { + if (!auth_number()) { + /* We do not want to leak info about the pap result. */ + retcode = UPAP_AUTHNAK; /* XXX exit value will be "wrong" */ + warn("calling number %q is not authorized", remote_number); + } + } + + msglen = strlen(msg); + if (msglen > 255) + msglen = 255; +#endif /* UNUSED */ + + upap_sresp(pcb, retcode, id, msg, msglen); + + /* Null terminate and clean remote name. */ + ppp_slprintf(rhostname, sizeof(rhostname), "%.*v", ruserlen, ruser); + + if (retcode == UPAP_AUTHACK) { + pcb->upap.us_serverstate = UPAPSS_OPEN; + ppp_notice("PAP peer authentication succeeded for %q", rhostname); + auth_peer_success(pcb, PPP_PAP, 0, ruser, ruserlen); + } else { + pcb->upap.us_serverstate = UPAPSS_BADAUTH; + ppp_warn("PAP peer authentication failed for %q", rhostname); + auth_peer_fail(pcb, PPP_PAP); + } + + if (pcb->settings.pap_req_timeout > 0) + UNTIMEOUT(upap_reqtimeout, pcb); +} +#endif /* PPP_SERVER */ + +/* + * upap_rauthack - Receive Authenticate-Ack. + */ +static void upap_rauthack(ppp_pcb *pcb, u_char *inp, int id, int len) { + u_char msglen; + char *msg; + LWIP_UNUSED_ARG(id); + + if (pcb->upap.us_clientstate != UPAPCS_AUTHREQ) /* XXX */ + return; + + /* + * Parse message. + */ + if (len < 1) { + UPAPDEBUG(("pap_rauthack: ignoring missing msg-length.")); + } else { + GETCHAR(msglen, inp); + if (msglen > 0) { + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG(("pap_rauthack: rcvd short packet.")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + } + } + + pcb->upap.us_clientstate = UPAPCS_OPEN; + + auth_withpeer_success(pcb, PPP_PAP, 0); +} + + +/* + * upap_rauthnak - Receive Authenticate-Nak. + */ +static void upap_rauthnak(ppp_pcb *pcb, u_char *inp, int id, int len) { + u_char msglen; + char *msg; + LWIP_UNUSED_ARG(id); + + if (pcb->upap.us_clientstate != UPAPCS_AUTHREQ) /* XXX */ + return; + + /* + * Parse message. + */ + if (len < 1) { + UPAPDEBUG(("pap_rauthnak: ignoring missing msg-length.")); + } else { + GETCHAR(msglen, inp); + if (msglen > 0) { + len -= sizeof (u_char); + if (len < msglen) { + UPAPDEBUG(("pap_rauthnak: rcvd short packet.")); + return; + } + msg = (char *) inp; + PRINTMSG(msg, msglen); + } + } + + pcb->upap.us_clientstate = UPAPCS_BADAUTH; + + ppp_error("PAP authentication failed"); + auth_withpeer_fail(pcb, PPP_PAP); +} + + +/* + * upap_sauthreq - Send an Authenticate-Request. + */ +static void upap_sauthreq(ppp_pcb *pcb) { + struct pbuf *p; + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) + + pcb->upap.us_userlen + pcb->upap.us_passwdlen; + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN +outlen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(UPAP_AUTHREQ, outp); + PUTCHAR(++pcb->upap.us_id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(pcb->upap.us_userlen, outp); + MEMCPY(outp, pcb->upap.us_user, pcb->upap.us_userlen); + INCPTR(pcb->upap.us_userlen, outp); + PUTCHAR(pcb->upap.us_passwdlen, outp); + MEMCPY(outp, pcb->upap.us_passwd, pcb->upap.us_passwdlen); + + ppp_write(pcb, p); + + TIMEOUT(upap_timeout, pcb, pcb->settings.pap_timeout_time); + ++pcb->upap.us_transmits; + pcb->upap.us_clientstate = UPAPCS_AUTHREQ; +} + +#if PPP_SERVER +/* + * upap_sresp - Send a response (ack or nak). + */ +static void upap_sresp(ppp_pcb *pcb, u_char code, u_char id, const char *msg, int msglen) { + struct pbuf *p; + u_char *outp; + int outlen; + + outlen = UPAP_HEADERLEN + sizeof (u_char) + msglen; + p = pbuf_alloc(PBUF_RAW, (u16_t)(PPP_HDRLEN +outlen), PPP_CTRL_PBUF_TYPE); + if(NULL == p) + return; + if(p->tot_len != p->len) { + pbuf_free(p); + return; + } + + outp = (u_char*)p->payload; + MAKEHEADER(outp, PPP_PAP); + + PUTCHAR(code, outp); + PUTCHAR(id, outp); + PUTSHORT(outlen, outp); + PUTCHAR(msglen, outp); + MEMCPY(outp, msg, msglen); + + ppp_write(pcb, p); +} +#endif /* PPP_SERVER */ + +#if PRINTPKT_SUPPORT +/* + * upap_printpkt - print the contents of a PAP packet. + */ +static const char* const upap_codenames[] = { + "AuthReq", "AuthAck", "AuthNak" +}; + +static int upap_printpkt(const u_char *p, int plen, void (*printer) (void *, const char *, ...), void *arg) { + int code, id, len; + int mlen, ulen, wlen; + const u_char *user, *pwd, *msg; + const u_char *pstart; + + if (plen < UPAP_HEADERLEN) + return 0; + pstart = p; + GETCHAR(code, p); + GETCHAR(id, p); + GETSHORT(len, p); + if (len < UPAP_HEADERLEN || len > plen) + return 0; + + if (code >= 1 && code <= (int)LWIP_ARRAYSIZE(upap_codenames)) + printer(arg, " %s", upap_codenames[code-1]); + else + printer(arg, " code=0x%x", code); + printer(arg, " id=0x%x", id); + len -= UPAP_HEADERLEN; + switch (code) { + case UPAP_AUTHREQ: + if (len < 1) + break; + ulen = p[0]; + if (len < ulen + 2) + break; + wlen = p[ulen + 1]; + if (len < ulen + wlen + 2) + break; + user = (const u_char *) (p + 1); + pwd = (const u_char *) (p + ulen + 2); + p += ulen + wlen + 2; + len -= ulen + wlen + 2; + printer(arg, " user="); + ppp_print_string(user, ulen, printer, arg); + printer(arg, " password="); +/* FIXME: require ppp_pcb struct as printpkt() argument */ +#if 0 + if (!pcb->settings.hide_password) +#endif + ppp_print_string(pwd, wlen, printer, arg); +#if 0 + else + printer(arg, ""); +#endif + break; + case UPAP_AUTHACK: + case UPAP_AUTHNAK: + if (len < 1) + break; + mlen = p[0]; + if (len < mlen + 1) + break; + msg = (const u_char *) (p + 1); + p += mlen + 1; + len -= mlen + 1; + printer(arg, " "); + ppp_print_string(msg, mlen, printer, arg); + break; + default: + break; + } + + /* print the rest of the bytes in the packet */ + for (; len > 0; --len) { + GETCHAR(code, p); + printer(arg, " %.2x", code); + } + + return p - pstart; +} +#endif /* PRINTPKT_SUPPORT */ + +#endif /* PPP_SUPPORT && PAP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c new file mode 100644 index 0000000..f1366da --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/utils.c @@ -0,0 +1,957 @@ +/* + * utils.c - various utility functions used in pppd. + * + * Copyright (c) 1999-2002 Paul Mackerras. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. The name(s) of the authors of this software must not be used to + * endorse or promote products derived from this software without + * prior written permission. + * + * 3. Redistributions of any form whatsoever must retain the following + * acknowledgment: + * "This product includes software developed by Paul Mackerras + * ". + * + * THE AUTHORS OF THIS SOFTWARE DISCLAIM ALL WARRANTIES WITH REGARD TO + * THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY + * SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN + * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#if 0 /* UNUSED */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef SVR4 +#include +#endif +#endif /* UNUSED */ + +#include "netif/ppp/ppp_impl.h" + +#include "netif/ppp/fsm.h" +#include "netif/ppp/lcp.h" + +#if defined(SUNOS4) +extern char *strerror(); +#endif + +static void ppp_logit(int level, const char *fmt, va_list args); +static void ppp_log_write(int level, char *buf); +#if PRINTPKT_SUPPORT +static void ppp_vslp_printer(void *arg, const char *fmt, ...); +static void ppp_format_packet(const u_char *p, int len, + void (*printer) (void *, const char *, ...), void *arg); + +struct buffer_info { + char *ptr; + int len; +}; +#endif /* PRINTPKT_SUPPORT */ + +/* + * ppp_strlcpy - like strcpy/strncpy, doesn't overflow destination buffer, + * always leaves destination null-terminated (for len > 0). + */ +size_t ppp_strlcpy(char *dest, const char *src, size_t len) { + size_t ret = strlen(src); + + if (len != 0) { + if (ret < len) + strcpy(dest, src); + else { + strncpy(dest, src, len - 1); + dest[len-1] = 0; + } + } + return ret; +} + +/* + * ppp_strlcat - like strcat/strncat, doesn't overflow destination buffer, + * always leaves destination null-terminated (for len > 0). + */ +size_t ppp_strlcat(char *dest, const char *src, size_t len) { + size_t dlen = strlen(dest); + + return dlen + ppp_strlcpy(dest + dlen, src, (len > dlen? len - dlen: 0)); +} + + +/* + * ppp_slprintf - format a message into a buffer. Like sprintf except we + * also specify the length of the output buffer, and we handle + * %m (error message), %v (visible string), + * %q (quoted string), %t (current time) and %I (IP address) formats. + * Doesn't do floating-point formats. + * Returns the number of chars put into buf. + */ +int ppp_slprintf(char *buf, int buflen, const char *fmt, ...) { + va_list args; + int n; + + va_start(args, fmt); + n = ppp_vslprintf(buf, buflen, fmt, args); + va_end(args); + return n; +} + +/* + * ppp_vslprintf - like ppp_slprintf, takes a va_list instead of a list of args. + */ +#define OUTCHAR(c) (buflen > 0? (--buflen, *buf++ = (c)): 0) + +int ppp_vslprintf(char *buf, int buflen, const char *fmt, va_list args) { + int c, i, n; + int width, prec, fillch; + int base, len, neg, quoted; + unsigned long val = 0; + const char *f; + char *str, *buf0; + const unsigned char *p; + char num[32]; +#if 0 /* need port */ + time_t t; +#endif /* need port */ + u32_t ip; + static char hexchars[] = "0123456789abcdef"; +#if PRINTPKT_SUPPORT + struct buffer_info bufinfo; +#endif /* PRINTPKT_SUPPORT */ + + buf0 = buf; + --buflen; + while (buflen > 0) { + for (f = fmt; *f != '%' && *f != 0; ++f) + ; + if (f > fmt) { + len = f - fmt; + if (len > buflen) + len = buflen; + memcpy(buf, fmt, len); + buf += len; + buflen -= len; + fmt = f; + } + if (*fmt == 0) + break; + c = *++fmt; + width = 0; + prec = -1; + fillch = ' '; + if (c == '0') { + fillch = '0'; + c = *++fmt; + } + if (c == '*') { + width = va_arg(args, int); + c = *++fmt; + } else { + while (lwip_isdigit(c)) { + width = width * 10 + c - '0'; + c = *++fmt; + } + } + if (c == '.') { + c = *++fmt; + if (c == '*') { + prec = va_arg(args, int); + c = *++fmt; + } else { + prec = 0; + while (lwip_isdigit(c)) { + prec = prec * 10 + c - '0'; + c = *++fmt; + } + } + } + str = 0; + base = 0; + neg = 0; + ++fmt; + switch (c) { + case 'l': + c = *fmt++; + switch (c) { + case 'd': + val = va_arg(args, long); + if ((long)val < 0) { + neg = 1; + val = (unsigned long)-(long)val; + } + base = 10; + break; + case 'u': + val = va_arg(args, unsigned long); + base = 10; + break; + default: + OUTCHAR('%'); + OUTCHAR('l'); + --fmt; /* so %lz outputs %lz etc. */ + continue; + } + break; + case 'd': + i = va_arg(args, int); + if (i < 0) { + neg = 1; + val = -i; + } else + val = i; + base = 10; + break; + case 'u': + val = va_arg(args, unsigned int); + base = 10; + break; + case 'o': + val = va_arg(args, unsigned int); + base = 8; + break; + case 'x': + case 'X': + val = va_arg(args, unsigned int); + base = 16; + break; +#if 0 /* unused (and wrong on LLP64 systems) */ + case 'p': + val = (unsigned long) va_arg(args, void *); + base = 16; + neg = 2; + break; +#endif /* unused (and wrong on LLP64 systems) */ + case 's': + str = va_arg(args, char *); + break; + case 'c': + num[0] = va_arg(args, int); + num[1] = 0; + str = num; + break; +#if 0 /* do we always have strerror() in embedded ? */ + case 'm': + str = strerror(errno); + break; +#endif /* do we always have strerror() in embedded ? */ + case 'I': + ip = va_arg(args, u32_t); + ip = lwip_ntohl(ip); + ppp_slprintf(num, sizeof(num), "%d.%d.%d.%d", (ip >> 24) & 0xff, + (ip >> 16) & 0xff, (ip >> 8) & 0xff, ip & 0xff); + str = num; + break; +#if 0 /* need port */ + case 't': + time(&t); + str = ctime(&t); + str += 4; /* chop off the day name */ + str[15] = 0; /* chop off year and newline */ + break; +#endif /* need port */ + case 'v': /* "visible" string */ + case 'q': /* quoted string */ + quoted = c == 'q'; + p = va_arg(args, unsigned char *); + if (p == NULL) + p = (const unsigned char *)""; + if (fillch == '0' && prec >= 0) { + n = prec; + } else { + n = strlen((const char *)p); + if (prec >= 0 && n > prec) + n = prec; + } + while (n > 0 && buflen > 0) { + c = *p++; + --n; + if (!quoted && c >= 0x80) { + OUTCHAR('M'); + OUTCHAR('-'); + c -= 0x80; + } + if (quoted && (c == '"' || c == '\\')) + OUTCHAR('\\'); + if (c < 0x20 || (0x7f <= c && c < 0xa0)) { + if (quoted) { + OUTCHAR('\\'); + switch (c) { + case '\t': OUTCHAR('t'); break; + case '\n': OUTCHAR('n'); break; + case '\b': OUTCHAR('b'); break; + case '\f': OUTCHAR('f'); break; + default: + OUTCHAR('x'); + OUTCHAR(hexchars[c >> 4]); + OUTCHAR(hexchars[c & 0xf]); + } + } else { + if (c == '\t') + OUTCHAR(c); + else { + OUTCHAR('^'); + OUTCHAR(c ^ 0x40); + } + } + } else + OUTCHAR(c); + } + continue; +#if PRINTPKT_SUPPORT + case 'P': /* print PPP packet */ + bufinfo.ptr = buf; + bufinfo.len = buflen + 1; + p = va_arg(args, unsigned char *); + n = va_arg(args, int); + ppp_format_packet(p, n, ppp_vslp_printer, &bufinfo); + buf = bufinfo.ptr; + buflen = bufinfo.len - 1; + continue; +#endif /* PRINTPKT_SUPPORT */ + case 'B': + p = va_arg(args, unsigned char *); + for (n = prec; n > 0; --n) { + c = *p++; + if (fillch == ' ') + OUTCHAR(' '); + OUTCHAR(hexchars[(c >> 4) & 0xf]); + OUTCHAR(hexchars[c & 0xf]); + } + continue; + default: + *buf++ = '%'; + if (c != '%') + --fmt; /* so %z outputs %z etc. */ + --buflen; + continue; + } + if (base != 0) { + str = num + sizeof(num); + *--str = 0; + while (str > num + neg) { + *--str = hexchars[val % base]; + val = val / base; + if (--prec <= 0 && val == 0) + break; + } + switch (neg) { + case 1: + *--str = '-'; + break; + case 2: + *--str = 'x'; + *--str = '0'; + break; + default: + break; + } + len = num + sizeof(num) - 1 - str; + } else { + len = strlen(str); + if (prec >= 0 && len > prec) + len = prec; + } + if (width > 0) { + if (width > buflen) + width = buflen; + if ((n = width - len) > 0) { + buflen -= n; + for (; n > 0; --n) + *buf++ = fillch; + } + } + if (len > buflen) + len = buflen; + memcpy(buf, str, len); + buf += len; + buflen -= len; + } + *buf = 0; + return buf - buf0; +} + +#if PRINTPKT_SUPPORT +/* + * vslp_printer - used in processing a %P format + */ +static void ppp_vslp_printer(void *arg, const char *fmt, ...) { + int n; + va_list pvar; + struct buffer_info *bi; + + va_start(pvar, fmt); + bi = (struct buffer_info *) arg; + n = ppp_vslprintf(bi->ptr, bi->len, fmt, pvar); + va_end(pvar); + + bi->ptr += n; + bi->len -= n; +} +#endif /* PRINTPKT_SUPPORT */ + +#if 0 /* UNUSED */ +/* + * log_packet - format a packet and log it. + */ + +void +log_packet(p, len, prefix, level) + u_char *p; + int len; + char *prefix; + int level; +{ + init_pr_log(prefix, level); + ppp_format_packet(p, len, pr_log, &level); + end_pr_log(); +} +#endif /* UNUSED */ + +#if PRINTPKT_SUPPORT +/* + * ppp_format_packet - make a readable representation of a packet, + * calling `printer(arg, format, ...)' to output it. + */ +static void ppp_format_packet(const u_char *p, int len, + void (*printer) (void *, const char *, ...), void *arg) { + int i, n; + u_short proto; + const struct protent *protp; + + if (len >= 2) { + GETSHORT(proto, p); + len -= 2; + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (proto == protp->protocol) + break; + if (protp != NULL) { + printer(arg, "[%s", protp->name); + n = (*protp->printpkt)(p, len, printer, arg); + printer(arg, "]"); + p += n; + len -= n; + } else { + for (i = 0; (protp = protocols[i]) != NULL; ++i) + if (proto == (protp->protocol & ~0x8000)) + break; + if (protp != 0 && protp->data_name != 0) { + printer(arg, "[%s data]", protp->data_name); + if (len > 8) + printer(arg, "%.8B ...", p); + else + printer(arg, "%.*B", len, p); + len = 0; + } else + printer(arg, "[proto=0x%x]", proto); + } + } + + if (len > 32) + printer(arg, "%.32B ...", p); + else + printer(arg, "%.*B", len, p); +} +#endif /* PRINTPKT_SUPPORT */ + +#if 0 /* UNUSED */ +/* + * init_pr_log, end_pr_log - initialize and finish use of pr_log. + */ + +static char line[256]; /* line to be logged accumulated here */ +static char *linep; /* current pointer within line */ +static int llevel; /* level for logging */ + +void +init_pr_log(prefix, level) + const char *prefix; + int level; +{ + linep = line; + if (prefix != NULL) { + ppp_strlcpy(line, prefix, sizeof(line)); + linep = line + strlen(line); + } + llevel = level; +} + +void +end_pr_log() +{ + if (linep != line) { + *linep = 0; + ppp_log_write(llevel, line); + } +} + +/* + * pr_log - printer routine for outputting to log + */ +void +pr_log (void *arg, const char *fmt, ...) +{ + int l, n; + va_list pvar; + char *p, *eol; + char buf[256]; + + va_start(pvar, fmt); + n = ppp_vslprintf(buf, sizeof(buf), fmt, pvar); + va_end(pvar); + + p = buf; + eol = strchr(buf, '\n'); + if (linep != line) { + l = (eol == NULL)? n: eol - buf; + if (linep + l < line + sizeof(line)) { + if (l > 0) { + memcpy(linep, buf, l); + linep += l; + } + if (eol == NULL) + return; + p = eol + 1; + eol = strchr(p, '\n'); + } + *linep = 0; + ppp_log_write(llevel, line); + linep = line; + } + + while (eol != NULL) { + *eol = 0; + ppp_log_write(llevel, p); + p = eol + 1; + eol = strchr(p, '\n'); + } + + /* assumes sizeof(buf) <= sizeof(line) */ + l = buf + n - p; + if (l > 0) { + memcpy(line, p, n); + linep = line + l; + } +} +#endif /* UNUSED */ + +/* + * ppp_print_string - print a readable representation of a string using + * printer. + */ +void ppp_print_string(const u_char *p, int len, void (*printer) (void *, const char *, ...), void *arg) { + int c; + + printer(arg, "\""); + for (; len > 0; --len) { + c = *p++; + if (' ' <= c && c <= '~') { + if (c == '\\' || c == '"') + printer(arg, "\\"); + printer(arg, "%c", c); + } else { + switch (c) { + case '\n': + printer(arg, "\\n"); + break; + case '\r': + printer(arg, "\\r"); + break; + case '\t': + printer(arg, "\\t"); + break; + default: + printer(arg, "\\%.3o", (u8_t)c); + /* no break */ + } + } + } + printer(arg, "\""); +} + +/* + * ppp_logit - does the hard work for fatal et al. + */ +static void ppp_logit(int level, const char *fmt, va_list args) { + char buf[1024]; + + ppp_vslprintf(buf, sizeof(buf), fmt, args); + ppp_log_write(level, buf); +} + +static void ppp_log_write(int level, char *buf) { + LWIP_UNUSED_ARG(level); /* necessary if PPPDEBUG is defined to an empty function */ + LWIP_UNUSED_ARG(buf); + PPPDEBUG(level, ("%s\n", buf) ); +#if 0 + if (log_to_fd >= 0 && (level != LOG_DEBUG || debug)) { + int n = strlen(buf); + + if (n > 0 && buf[n-1] == '\n') + --n; + if (write(log_to_fd, buf, n) != n + || write(log_to_fd, "\n", 1) != 1) + log_to_fd = -1; + } +#endif +} + +/* + * ppp_fatal - log an error message and die horribly. + */ +void ppp_fatal(const char *fmt, ...) { + va_list pvar; + + va_start(pvar, fmt); + ppp_logit(LOG_ERR, fmt, pvar); + va_end(pvar); + + LWIP_ASSERT("ppp_fatal", 0); /* as promised */ +} + +/* + * ppp_error - log an error message. + */ +void ppp_error(const char *fmt, ...) { + va_list pvar; + + va_start(pvar, fmt); + ppp_logit(LOG_ERR, fmt, pvar); + va_end(pvar); +#if 0 /* UNUSED */ + ++error_count; +#endif /* UNUSED */ +} + +/* + * ppp_warn - log a warning message. + */ +void ppp_warn(const char *fmt, ...) { + va_list pvar; + + va_start(pvar, fmt); + ppp_logit(LOG_WARNING, fmt, pvar); + va_end(pvar); +} + +/* + * ppp_notice - log a notice-level message. + */ +void ppp_notice(const char *fmt, ...) { + va_list pvar; + + va_start(pvar, fmt); + ppp_logit(LOG_NOTICE, fmt, pvar); + va_end(pvar); +} + +/* + * ppp_info - log an informational message. + */ +void ppp_info(const char *fmt, ...) { + va_list pvar; + + va_start(pvar, fmt); + ppp_logit(LOG_INFO, fmt, pvar); + va_end(pvar); +} + +/* + * ppp_dbglog - log a debug message. + */ +void ppp_dbglog(const char *fmt, ...) { + va_list pvar; + + va_start(pvar, fmt); + ppp_logit(LOG_DEBUG, fmt, pvar); + va_end(pvar); +} + +#if PRINTPKT_SUPPORT +/* + * ppp_dump_packet - print out a packet in readable form if it is interesting. + * Assumes len >= PPP_HDRLEN. + */ +void ppp_dump_packet(ppp_pcb *pcb, const char *tag, unsigned char *p, int len) { + int proto; + + /* + * don't print data packets, i.e. IPv4, IPv6, VJ, and compressed packets. + */ + proto = (p[0] << 8) + p[1]; + if (proto < 0xC000 && (proto & ~0x8000) == proto) + return; + + /* + * don't print valid LCP echo request/reply packets if the link is up. + */ + if (proto == PPP_LCP && pcb->phase == PPP_PHASE_RUNNING && len >= 2 + HEADERLEN) { + unsigned char *lcp = p + 2; + int l = (lcp[2] << 8) + lcp[3]; + + if ((lcp[0] == ECHOREQ || lcp[0] == ECHOREP) + && l >= HEADERLEN && l <= len - 2) + return; + } + + ppp_dbglog("%s %P", tag, p, len); +} +#endif /* PRINTPKT_SUPPORT */ + +#if 0 /* Unused */ + +/* + * complete_read - read a full `count' bytes from fd, + * unless end-of-file or an error other than EINTR is encountered. + */ +ssize_t +complete_read(int fd, void *buf, size_t count) +{ + size_t done; + ssize_t nb; + char *ptr = buf; + + for (done = 0; done < count; ) { + nb = read(fd, ptr, count - done); + if (nb < 0) { + if (errno == EINTR) + continue; + return -1; + } + if (nb == 0) + break; + done += nb; + ptr += nb; + } + return done; +} + +/* Procedures for locking the serial device using a lock file. */ +#ifndef LOCK_DIR +#ifdef __linux__ +#define LOCK_DIR "/var/lock" +#else +#ifdef SVR4 +#define LOCK_DIR "/var/spool/locks" +#else +#define LOCK_DIR "/var/spool/lock" +#endif +#endif +#endif /* LOCK_DIR */ + +static char lock_file[MAXPATHLEN]; + +/* + * lock - create a lock file for the named device + */ +int +lock(dev) + char *dev; +{ +#ifdef LOCKLIB + int result; + + result = mklock (dev, (void *) 0); + if (result == 0) { + ppp_strlcpy(lock_file, dev, sizeof(lock_file)); + return 0; + } + + if (result > 0) + ppp_notice("Device %s is locked by pid %d", dev, result); + else + ppp_error("Can't create lock file %s", lock_file); + return -1; + +#else /* LOCKLIB */ + + char lock_buffer[12]; + int fd, pid, n; + +#ifdef SVR4 + struct stat sbuf; + + if (stat(dev, &sbuf) < 0) { + ppp_error("Can't get device number for %s: %m", dev); + return -1; + } + if ((sbuf.st_mode & S_IFMT) != S_IFCHR) { + ppp_error("Can't lock %s: not a character device", dev); + return -1; + } + ppp_slprintf(lock_file, sizeof(lock_file), "%s/LK.%03d.%03d.%03d", + LOCK_DIR, major(sbuf.st_dev), + major(sbuf.st_rdev), minor(sbuf.st_rdev)); +#else + char *p; + char lockdev[MAXPATHLEN]; + + if ((p = strstr(dev, "dev/")) != NULL) { + dev = p + 4; + strncpy(lockdev, dev, MAXPATHLEN-1); + lockdev[MAXPATHLEN-1] = 0; + while ((p = strrchr(lockdev, '/')) != NULL) { + *p = '_'; + } + dev = lockdev; + } else + if ((p = strrchr(dev, '/')) != NULL) + dev = p + 1; + + ppp_slprintf(lock_file, sizeof(lock_file), "%s/LCK..%s", LOCK_DIR, dev); +#endif + + while ((fd = open(lock_file, O_EXCL | O_CREAT | O_RDWR, 0644)) < 0) { + if (errno != EEXIST) { + ppp_error("Can't create lock file %s: %m", lock_file); + break; + } + + /* Read the lock file to find out who has the device locked. */ + fd = open(lock_file, O_RDONLY, 0); + if (fd < 0) { + if (errno == ENOENT) /* This is just a timing problem. */ + continue; + ppp_error("Can't open existing lock file %s: %m", lock_file); + break; + } +#ifndef LOCK_BINARY + n = read(fd, lock_buffer, 11); +#else + n = read(fd, &pid, sizeof(pid)); +#endif /* LOCK_BINARY */ + close(fd); + fd = -1; + if (n <= 0) { + ppp_error("Can't read pid from lock file %s", lock_file); + break; + } + + /* See if the process still exists. */ +#ifndef LOCK_BINARY + lock_buffer[n] = 0; + pid = atoi(lock_buffer); +#endif /* LOCK_BINARY */ + if (pid == getpid()) + return 1; /* somebody else locked it for us */ + if (pid == 0 + || (kill(pid, 0) == -1 && errno == ESRCH)) { + if (unlink (lock_file) == 0) { + ppp_notice("Removed stale lock on %s (pid %d)", dev, pid); + continue; + } + ppp_warn("Couldn't remove stale lock on %s", dev); + } else + ppp_notice("Device %s is locked by pid %d", dev, pid); + break; + } + + if (fd < 0) { + lock_file[0] = 0; + return -1; + } + + pid = getpid(); +#ifndef LOCK_BINARY + ppp_slprintf(lock_buffer, sizeof(lock_buffer), "%10d\n", pid); + write (fd, lock_buffer, 11); +#else + write(fd, &pid, sizeof (pid)); +#endif + close(fd); + return 0; + +#endif +} + +/* + * relock - called to update our lockfile when we are about to detach, + * thus changing our pid (we fork, the child carries on, and the parent dies). + * Note that this is called by the parent, with pid equal to the pid + * of the child. This avoids a potential race which would exist if + * we had the child rewrite the lockfile (the parent might die first, + * and another process could think the lock was stale if it checked + * between when the parent died and the child rewrote the lockfile). + */ +int +relock(pid) + int pid; +{ +#ifdef LOCKLIB + /* XXX is there a way to do this? */ + return -1; +#else /* LOCKLIB */ + + int fd; + char lock_buffer[12]; + + if (lock_file[0] == 0) + return -1; + fd = open(lock_file, O_WRONLY, 0); + if (fd < 0) { + ppp_error("Couldn't reopen lock file %s: %m", lock_file); + lock_file[0] = 0; + return -1; + } + +#ifndef LOCK_BINARY + ppp_slprintf(lock_buffer, sizeof(lock_buffer), "%10d\n", pid); + write (fd, lock_buffer, 11); +#else + write(fd, &pid, sizeof(pid)); +#endif /* LOCK_BINARY */ + close(fd); + return 0; + +#endif /* LOCKLIB */ +} + +/* + * unlock - remove our lockfile + */ +void +unlock() +{ + if (lock_file[0]) { +#ifdef LOCKLIB + (void) rmlock(lock_file, (void *) 0); +#else + unlink(lock_file); +#endif + lock_file[0] = 0; + } +} + +#endif /* Unused */ + +#endif /* PPP_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c b/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c new file mode 100644 index 0000000..3fecba6 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/ppp/vj.c @@ -0,0 +1,685 @@ +/* + * Routines to compress and uncompess tcp packets (for transmission + * over low speed serial lines. + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the above copyright notice and this paragraph are + * duplicated in all such forms and that any documentation, + * advertising materials, and other materials related to such + * distribution and use acknowledge that the software was developed + * by the University of California, Berkeley. The name of the + * University may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + * + * Van Jacobson (van@helios.ee.lbl.gov), Dec 31, 1989: + * Initial distribution. + * + * Modified June 1993 by Paul Mackerras, paulus@cs.anu.edu.au, + * so that the entire packet being decompressed doesn't have + * to be in contiguous memory (just the compressed header). + * + * Modified March 1998 by Guy Lancaster, glanca@gesn.com, + * for a 16 bit processor. + */ + +#include "netif/ppp/ppp_opts.h" +#if PPP_SUPPORT && VJ_SUPPORT /* don't build if not configured for use in lwipopts.h */ + +#include "netif/ppp/ppp_impl.h" +#include "netif/ppp/pppdebug.h" + +#include "netif/ppp/vj.h" + +#include + +#if LINK_STATS +#define INCR(counter) ++comp->stats.counter +#else +#define INCR(counter) +#endif + +void +vj_compress_init(struct vjcompress *comp) +{ + u8_t i; + struct cstate *tstate = comp->tstate; + +#if MAX_SLOTS == 0 + memset((char *)comp, 0, sizeof(*comp)); +#endif + comp->maxSlotIndex = MAX_SLOTS - 1; + comp->compressSlot = 0; /* Disable slot ID compression by default. */ + for (i = MAX_SLOTS - 1; i > 0; --i) { + tstate[i].cs_id = i; + tstate[i].cs_next = &tstate[i - 1]; + } + tstate[0].cs_next = &tstate[MAX_SLOTS - 1]; + tstate[0].cs_id = 0; + comp->last_cs = &tstate[0]; + comp->last_recv = 255; + comp->last_xmit = 255; + comp->flags = VJF_TOSS; +} + + +/* ENCODE encodes a number that is known to be non-zero. ENCODEZ + * checks for zero (since zero has to be encoded in the long, 3 byte + * form). + */ +#define ENCODE(n) { \ + if ((u16_t)(n) >= 256) { \ + *cp++ = 0; \ + cp[1] = (u8_t)(n); \ + cp[0] = (u8_t)((n) >> 8); \ + cp += 2; \ + } else { \ + *cp++ = (u8_t)(n); \ + } \ +} +#define ENCODEZ(n) { \ + if ((u16_t)(n) >= 256 || (u16_t)(n) == 0) { \ + *cp++ = 0; \ + cp[1] = (u8_t)(n); \ + cp[0] = (u8_t)((n) >> 8); \ + cp += 2; \ + } else { \ + *cp++ = (u8_t)(n); \ + } \ +} + +#define DECODEL(f) { \ + if (*cp == 0) {\ + u32_t tmp_ = lwip_ntohl(f) + ((cp[1] << 8) | cp[2]); \ + (f) = lwip_htonl(tmp_); \ + cp += 3; \ + } else { \ + u32_t tmp_ = lwip_ntohl(f) + (u32_t)*cp++; \ + (f) = lwip_htonl(tmp_); \ + } \ +} + +#define DECODES(f) { \ + if (*cp == 0) {\ + u16_t tmp_ = lwip_ntohs(f) + (((u16_t)cp[1] << 8) | cp[2]); \ + (f) = lwip_htons(tmp_); \ + cp += 3; \ + } else { \ + u16_t tmp_ = lwip_ntohs(f) + (u16_t)*cp++; \ + (f) = lwip_htons(tmp_); \ + } \ +} + +#define DECODEU(f) { \ + if (*cp == 0) {\ + (f) = lwip_htons(((u16_t)cp[1] << 8) | cp[2]); \ + cp += 3; \ + } else { \ + (f) = lwip_htons((u16_t)*cp++); \ + } \ +} + +/* Helper structures for unaligned *u32_t and *u16_t accesses */ +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct vj_u32_t { + PACK_STRUCT_FIELD(u32_t v); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct vj_u16_t { + PACK_STRUCT_FIELD(u16_t v); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +/* + * vj_compress_tcp - Attempt to do Van Jacobson header compression on a + * packet. This assumes that nb and comp are not null and that the first + * buffer of the chain contains a valid IP header. + * Return the VJ type code indicating whether or not the packet was + * compressed. + */ +u8_t +vj_compress_tcp(struct vjcompress *comp, struct pbuf **pb) +{ + struct pbuf *np = *pb; + struct ip_hdr *ip = (struct ip_hdr *)np->payload; + struct cstate *cs = comp->last_cs->cs_next; + u16_t ilen = IPH_HL(ip); + u16_t hlen; + struct tcp_hdr *oth; + struct tcp_hdr *th; + u16_t deltaS, deltaA = 0; + u32_t deltaL; + u32_t changes = 0; + u8_t new_seq[16]; + u8_t *cp = new_seq; + + /* + * Check that the packet is IP proto TCP. + */ + if (IPH_PROTO(ip) != IP_PROTO_TCP) { + return (TYPE_IP); + } + + /* + * Bail if this is an IP fragment or if the TCP packet isn't + * `compressible' (i.e., ACK isn't set or some other control bit is + * set). + */ + if ((IPH_OFFSET(ip) & PP_HTONS(0x3fff)) || np->tot_len < 40) { + return (TYPE_IP); + } + th = (struct tcp_hdr *)&((struct vj_u32_t*)ip)[ilen]; + if ((TCPH_FLAGS(th) & (TCP_SYN|TCP_FIN|TCP_RST|TCP_ACK)) != TCP_ACK) { + return (TYPE_IP); + } + + /* Check that the TCP/IP headers are contained in the first buffer. */ + hlen = ilen + TCPH_HDRLEN(th); + hlen <<= 2; + if (np->len < hlen) { + PPPDEBUG(LOG_INFO, ("vj_compress_tcp: header len %d spans buffers\n", hlen)); + return (TYPE_IP); + } + + /* TCP stack requires that we don't change the packet payload, therefore we copy + * the whole packet before compression. */ + np = pbuf_clone(PBUF_RAW, PBUF_RAM, *pb); + if (!np) { + return (TYPE_IP); + } + + *pb = np; + ip = (struct ip_hdr *)np->payload; + + /* + * Packet is compressible -- we're going to send either a + * COMPRESSED_TCP or UNCOMPRESSED_TCP packet. Either way we need + * to locate (or create) the connection state. Special case the + * most recently used connection since it's most likely to be used + * again & we don't have to do any reordering if it's used. + */ + INCR(vjs_packets); + if (!ip4_addr_cmp(&ip->src, &cs->cs_ip.src) + || !ip4_addr_cmp(&ip->dest, &cs->cs_ip.dest) + || (*(struct vj_u32_t*)th).v != (((struct vj_u32_t*)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]).v) { + /* + * Wasn't the first -- search for it. + * + * States are kept in a circularly linked list with + * last_cs pointing to the end of the list. The + * list is kept in lru order by moving a state to the + * head of the list whenever it is referenced. Since + * the list is short and, empirically, the connection + * we want is almost always near the front, we locate + * states via linear search. If we don't find a state + * for the datagram, the oldest state is (re-)used. + */ + struct cstate *lcs; + struct cstate *lastcs = comp->last_cs; + + do { + lcs = cs; cs = cs->cs_next; + INCR(vjs_searches); + if (ip4_addr_cmp(&ip->src, &cs->cs_ip.src) + && ip4_addr_cmp(&ip->dest, &cs->cs_ip.dest) + && (*(struct vj_u32_t*)th).v == (((struct vj_u32_t*)&cs->cs_ip)[IPH_HL(&cs->cs_ip)]).v) { + goto found; + } + } while (cs != lastcs); + + /* + * Didn't find it -- re-use oldest cstate. Send an + * uncompressed packet that tells the other side what + * connection number we're using for this conversation. + * Note that since the state list is circular, the oldest + * state points to the newest and we only need to set + * last_cs to update the lru linkage. + */ + INCR(vjs_misses); + comp->last_cs = lcs; + goto uncompressed; + + found: + /* + * Found it -- move to the front on the connection list. + */ + if (cs == lastcs) { + comp->last_cs = lcs; + } else { + lcs->cs_next = cs->cs_next; + cs->cs_next = lastcs->cs_next; + lastcs->cs_next = cs; + } + } + + oth = (struct tcp_hdr *)&((struct vj_u32_t*)&cs->cs_ip)[ilen]; + deltaS = ilen; + + /* + * Make sure that only what we expect to change changed. The first + * line of the `if' checks the IP protocol version, header length & + * type of service. The 2nd line checks the "Don't fragment" bit. + * The 3rd line checks the time-to-live and protocol (the protocol + * check is unnecessary but costless). The 4th line checks the TCP + * header length. The 5th line checks IP options, if any. The 6th + * line checks TCP options, if any. If any of these things are + * different between the previous & current datagram, we send the + * current datagram `uncompressed'. + */ + if ((((struct vj_u16_t*)ip)[0]).v != (((struct vj_u16_t*)&cs->cs_ip)[0]).v + || (((struct vj_u16_t*)ip)[3]).v != (((struct vj_u16_t*)&cs->cs_ip)[3]).v + || (((struct vj_u16_t*)ip)[4]).v != (((struct vj_u16_t*)&cs->cs_ip)[4]).v + || TCPH_HDRLEN(th) != TCPH_HDRLEN(oth) + || (deltaS > 5 && BCMP(ip + 1, &cs->cs_ip + 1, (deltaS - 5) << 2)) + || (TCPH_HDRLEN(th) > 5 && BCMP(th + 1, oth + 1, (TCPH_HDRLEN(th) - 5) << 2))) { + goto uncompressed; + } + + /* + * Figure out which of the changing fields changed. The + * receiver expects changes in the order: urgent, window, + * ack, seq (the order minimizes the number of temporaries + * needed in this section of code). + */ + if (TCPH_FLAGS(th) & TCP_URG) { + deltaS = lwip_ntohs(th->urgp); + ENCODEZ(deltaS); + changes |= NEW_U; + } else if (th->urgp != oth->urgp) { + /* argh! URG not set but urp changed -- a sensible + * implementation should never do this but RFC793 + * doesn't prohibit the change so we have to deal + * with it. */ + goto uncompressed; + } + + if ((deltaS = (u16_t)(lwip_ntohs(th->wnd) - lwip_ntohs(oth->wnd))) != 0) { + ENCODE(deltaS); + changes |= NEW_W; + } + + if ((deltaL = lwip_ntohl(th->ackno) - lwip_ntohl(oth->ackno)) != 0) { + if (deltaL > 0xffff) { + goto uncompressed; + } + deltaA = (u16_t)deltaL; + ENCODE(deltaA); + changes |= NEW_A; + } + + if ((deltaL = lwip_ntohl(th->seqno) - lwip_ntohl(oth->seqno)) != 0) { + if (deltaL > 0xffff) { + goto uncompressed; + } + deltaS = (u16_t)deltaL; + ENCODE(deltaS); + changes |= NEW_S; + } + + switch(changes) { + case 0: + /* + * Nothing changed. If this packet contains data and the + * last one didn't, this is probably a data packet following + * an ack (normal on an interactive connection) and we send + * it compressed. Otherwise it's probably a retransmit, + * retransmitted ack or window probe. Send it uncompressed + * in case the other side missed the compressed version. + */ + if (IPH_LEN(ip) != IPH_LEN(&cs->cs_ip) && + lwip_ntohs(IPH_LEN(&cs->cs_ip)) == hlen) { + break; + } + /* no break */ + /* fall through */ + + case SPECIAL_I: + case SPECIAL_D: + /* + * actual changes match one of our special case encodings -- + * send packet uncompressed. + */ + goto uncompressed; + + case NEW_S|NEW_A: + if (deltaS == deltaA && deltaS == lwip_ntohs(IPH_LEN(&cs->cs_ip)) - hlen) { + /* special case for echoed terminal traffic */ + changes = SPECIAL_I; + cp = new_seq; + } + break; + + case NEW_S: + if (deltaS == lwip_ntohs(IPH_LEN(&cs->cs_ip)) - hlen) { + /* special case for data xfer */ + changes = SPECIAL_D; + cp = new_seq; + } + break; + default: + break; + } + + deltaS = (u16_t)(lwip_ntohs(IPH_ID(ip)) - lwip_ntohs(IPH_ID(&cs->cs_ip))); + if (deltaS != 1) { + ENCODEZ(deltaS); + changes |= NEW_I; + } + if (TCPH_FLAGS(th) & TCP_PSH) { + changes |= TCP_PUSH_BIT; + } + /* + * Grab the cksum before we overwrite it below. Then update our + * state with this packet's header. + */ + deltaA = lwip_ntohs(th->chksum); + MEMCPY(&cs->cs_ip, ip, hlen); + + /* + * We want to use the original packet as our compressed packet. + * (cp - new_seq) is the number of bytes we need for compressed + * sequence numbers. In addition we need one byte for the change + * mask, one for the connection id and two for the tcp checksum. + * So, (cp - new_seq) + 4 bytes of header are needed. hlen is how + * many bytes of the original packet to toss so subtract the two to + * get the new packet size. + */ + deltaS = (u16_t)(cp - new_seq); + if (!comp->compressSlot || comp->last_xmit != cs->cs_id) { + comp->last_xmit = cs->cs_id; + hlen -= deltaS + 4; + if (pbuf_remove_header(np, hlen)){ + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + } + cp = (u8_t*)np->payload; + *cp++ = (u8_t)(changes | NEW_C); + *cp++ = cs->cs_id; + } else { + hlen -= deltaS + 3; + if (pbuf_remove_header(np, hlen)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + } + cp = (u8_t*)np->payload; + *cp++ = (u8_t)changes; + } + *cp++ = (u8_t)(deltaA >> 8); + *cp++ = (u8_t)deltaA; + MEMCPY(cp, new_seq, deltaS); + INCR(vjs_compressed); + return (TYPE_COMPRESSED_TCP); + + /* + * Update connection state cs & send uncompressed packet (that is, + * a regular ip/tcp packet but with the 'conversation id' we hope + * to use on future compressed packets in the protocol field). + */ +uncompressed: + MEMCPY(&cs->cs_ip, ip, hlen); + IPH_PROTO_SET(ip, cs->cs_id); + comp->last_xmit = cs->cs_id; + return (TYPE_UNCOMPRESSED_TCP); +} + +/* + * Called when we may have missed a packet. + */ +void +vj_uncompress_err(struct vjcompress *comp) +{ + comp->flags |= VJF_TOSS; + INCR(vjs_errorin); +} + +/* + * "Uncompress" a packet of type TYPE_UNCOMPRESSED_TCP. + * Return 0 on success, -1 on failure. + */ +int +vj_uncompress_uncomp(struct pbuf *nb, struct vjcompress *comp) +{ + u32_t hlen; + struct cstate *cs; + struct ip_hdr *ip; + + ip = (struct ip_hdr *)nb->payload; + hlen = IPH_HL(ip) << 2; + if (IPH_PROTO(ip) >= MAX_SLOTS + || hlen + sizeof(struct tcp_hdr) > nb->len + || (hlen += TCPH_HDRLEN_BYTES((struct tcp_hdr *)&((char *)ip)[hlen])) + > nb->len + || hlen > MAX_HDR) { + PPPDEBUG(LOG_INFO, ("vj_uncompress_uncomp: bad cid=%d, hlen=%d buflen=%d\n", + IPH_PROTO(ip), hlen, nb->len)); + vj_uncompress_err(comp); + return -1; + } + cs = &comp->rstate[comp->last_recv = IPH_PROTO(ip)]; + comp->flags &=~ VJF_TOSS; + IPH_PROTO_SET(ip, IP_PROTO_TCP); + /* copy from/to bigger buffers checked above instead of cs->cs_ip and ip + just to help static code analysis to see this is correct ;-) */ + MEMCPY(&cs->cs_hdr, nb->payload, hlen); + cs->cs_hlen = (u16_t)hlen; + INCR(vjs_uncompressedin); + return 0; +} + +/* + * Uncompress a packet of type TYPE_COMPRESSED_TCP. + * The packet is composed of a buffer chain and the first buffer + * must contain an accurate chain length. + * The first buffer must include the entire compressed TCP/IP header. + * This procedure replaces the compressed header with the uncompressed + * header and returns the length of the VJ header. + */ +int +vj_uncompress_tcp(struct pbuf **nb, struct vjcompress *comp) +{ + u8_t *cp; + struct tcp_hdr *th; + struct cstate *cs; + struct vj_u16_t *bp; + struct pbuf *n0 = *nb; + u32_t tmp; + u32_t vjlen, hlen, changes; + + INCR(vjs_compressedin); + cp = (u8_t*)n0->payload; + changes = *cp++; + if (changes & NEW_C) { + /* + * Make sure the state index is in range, then grab the state. + * If we have a good state index, clear the 'discard' flag. + */ + if (*cp >= MAX_SLOTS) { + PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: bad cid=%d\n", *cp)); + goto bad; + } + + comp->flags &=~ VJF_TOSS; + comp->last_recv = *cp++; + } else { + /* + * this packet has an implicit state index. If we've + * had a line error since the last time we got an + * explicit state index, we have to toss the packet. + */ + if (comp->flags & VJF_TOSS) { + PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: tossing\n")); + INCR(vjs_tossed); + return (-1); + } + } + cs = &comp->rstate[comp->last_recv]; + hlen = IPH_HL(&cs->cs_ip) << 2; + th = (struct tcp_hdr *)&((u8_t*)&cs->cs_ip)[hlen]; + th->chksum = lwip_htons((*cp << 8) | cp[1]); + cp += 2; + if (changes & TCP_PUSH_BIT) { + TCPH_SET_FLAG(th, TCP_PSH); + } else { + TCPH_UNSET_FLAG(th, TCP_PSH); + } + + switch (changes & SPECIALS_MASK) { + case SPECIAL_I: + { + u32_t i = lwip_ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen; + /* some compilers can't nest inline assembler.. */ + tmp = lwip_ntohl(th->ackno) + i; + th->ackno = lwip_htonl(tmp); + tmp = lwip_ntohl(th->seqno) + i; + th->seqno = lwip_htonl(tmp); + } + break; + + case SPECIAL_D: + /* some compilers can't nest inline assembler.. */ + tmp = lwip_ntohl(th->seqno) + lwip_ntohs(IPH_LEN(&cs->cs_ip)) - cs->cs_hlen; + th->seqno = lwip_htonl(tmp); + break; + + default: + if (changes & NEW_U) { + TCPH_SET_FLAG(th, TCP_URG); + DECODEU(th->urgp); + } else { + TCPH_UNSET_FLAG(th, TCP_URG); + } + if (changes & NEW_W) { + DECODES(th->wnd); + } + if (changes & NEW_A) { + DECODEL(th->ackno); + } + if (changes & NEW_S) { + DECODEL(th->seqno); + } + break; + } + if (changes & NEW_I) { + DECODES(cs->cs_ip._id); + } else { + IPH_ID_SET(&cs->cs_ip, lwip_ntohs(IPH_ID(&cs->cs_ip)) + 1); + IPH_ID_SET(&cs->cs_ip, lwip_htons(IPH_ID(&cs->cs_ip))); + } + + /* + * At this point, cp points to the first byte of data in the + * packet. Fill in the IP total length and update the IP + * header checksum. + */ + vjlen = (u16_t)(cp - (u8_t*)n0->payload); + if (n0->len < vjlen) { + /* + * We must have dropped some characters (crc should detect + * this but the old slip framing won't) + */ + PPPDEBUG(LOG_INFO, ("vj_uncompress_tcp: head buffer %d too short %d\n", + n0->len, vjlen)); + goto bad; + } + +#if BYTE_ORDER == LITTLE_ENDIAN + tmp = n0->tot_len - vjlen + cs->cs_hlen; + IPH_LEN_SET(&cs->cs_ip, lwip_htons((u16_t)tmp)); +#else + IPH_LEN_SET(&cs->cs_ip, lwip_htons(n0->tot_len - vjlen + cs->cs_hlen)); +#endif + + /* recompute the ip header checksum */ + bp = (struct vj_u16_t*) &cs->cs_ip; + IPH_CHKSUM_SET(&cs->cs_ip, 0); + for (tmp = 0; hlen > 0; hlen -= 2) { + tmp += (*bp++).v; + } + tmp = (tmp & 0xffff) + (tmp >> 16); + tmp = (tmp & 0xffff) + (tmp >> 16); + IPH_CHKSUM_SET(&cs->cs_ip, (u16_t)(~tmp)); + + /* Remove the compressed header and prepend the uncompressed header. */ + if (pbuf_remove_header(n0, vjlen)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + goto bad; + } + + if(LWIP_MEM_ALIGN(n0->payload) != n0->payload) { + struct pbuf *np; + +#if IP_FORWARD + /* If IP forwarding is enabled we are using a PBUF_LINK packet type so + * the packet is being allocated with enough header space to be + * forwarded (to Ethernet for example). + */ + np = pbuf_alloc(PBUF_LINK, n0->len + cs->cs_hlen, PBUF_POOL); +#else /* IP_FORWARD */ + np = pbuf_alloc(PBUF_RAW, n0->len + cs->cs_hlen, PBUF_POOL); +#endif /* IP_FORWARD */ + if(!np) { + PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: realign failed\n")); + goto bad; + } + + if (pbuf_remove_header(np, cs->cs_hlen)) { + /* Can we cope with this failing? Just assert for now */ + LWIP_ASSERT("pbuf_remove_header failed\n", 0); + goto bad; + } + + pbuf_take(np, n0->payload, n0->len); + + if(n0->next) { + pbuf_chain(np, n0->next); + pbuf_dechain(n0); + } + pbuf_free(n0); + n0 = np; + } + + if (pbuf_add_header(n0, cs->cs_hlen)) { + struct pbuf *np; + + LWIP_ASSERT("vj_uncompress_tcp: cs->cs_hlen <= PBUF_POOL_BUFSIZE", cs->cs_hlen <= PBUF_POOL_BUFSIZE); + np = pbuf_alloc(PBUF_RAW, cs->cs_hlen, PBUF_POOL); + if(!np) { + PPPDEBUG(LOG_WARNING, ("vj_uncompress_tcp: prepend failed\n")); + goto bad; + } + pbuf_cat(np, n0); + n0 = np; + } + LWIP_ASSERT("n0->len >= cs->cs_hlen", n0->len >= cs->cs_hlen); + MEMCPY(n0->payload, &cs->cs_ip, cs->cs_hlen); + + *nb = n0; + + return vjlen; + +bad: + vj_uncompress_err(comp); + return (-1); +} + +#endif /* PPP_SUPPORT && VJ_SUPPORT */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/slipif.c b/Middlewares/Third_Party/LwIP/src/netif/slipif.c new file mode 100644 index 0000000..9b175dc --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/slipif.c @@ -0,0 +1,558 @@ +/** + * @file + * SLIP Interface + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * This file is built upon the file: src/arch/rtxc/netif/sioslip.c + * + * Author: Magnus Ivarsson + * Simon Goldschmidt + */ + + +/** + * @defgroup slipif SLIP + * @ingroup netifs + * + * This is an arch independent SLIP netif. The specific serial hooks must be + * provided by another file. They are sio_open, sio_read/sio_tryread and sio_send + * + * Usage: This netif can be used in three ways:\n + * 1) For NO_SYS==0, an RX thread can be used which blocks on sio_read() + * until data is received.\n + * 2) In your main loop, call slipif_poll() to check for new RX bytes, + * completed packets are fed into netif->input().\n + * 3) Call slipif_received_byte[s]() from your serial RX ISR and + * slipif_process_rxqueue() from your main loop. ISR level decodes + * packets and puts completed packets on a queue which is fed into + * the stack from the main loop (needs SYS_LIGHTWEIGHT_PROT for + * pbuf_alloc to work on ISR level!). + * + */ + +#include "netif/slipif.h" +#include "lwip/opt.h" + +#include "lwip/def.h" +#include "lwip/pbuf.h" +#include "lwip/stats.h" +#include "lwip/snmp.h" +#include "lwip/sys.h" +#include "lwip/sio.h" + +#define SLIP_END 0xC0 /* 0300: start and end of every packet */ +#define SLIP_ESC 0xDB /* 0333: escape start (one byte escaped data follows) */ +#define SLIP_ESC_END 0xDC /* 0334: following escape: original byte is 0xC0 (END) */ +#define SLIP_ESC_ESC 0xDD /* 0335: following escape: original byte is 0xDB (ESC) */ + +/** Maximum packet size that is received by this netif */ +#ifndef SLIP_MAX_SIZE +#define SLIP_MAX_SIZE 1500 +#endif + +/** Define this to the interface speed for SNMP + * (sio_fd is the sio_fd_t returned by sio_open). + * The default value of zero means 'unknown'. + */ +#ifndef SLIP_SIO_SPEED +#define SLIP_SIO_SPEED(sio_fd) 0 +#endif + +enum slipif_recv_state { + SLIP_RECV_NORMAL, + SLIP_RECV_ESCAPE +}; + +struct slipif_priv { + sio_fd_t sd; + /* q is the whole pbuf chain for a packet, p is the current pbuf in the chain */ + struct pbuf *p, *q; + u8_t state; + u16_t i, recved; +#if SLIP_RX_FROM_ISR + struct pbuf *rxpackets; +#endif +}; + +/** + * Send a pbuf doing the necessary SLIP encapsulation + * + * Uses the serial layer's sio_send() + * + * @param netif the lwip network interface structure for this slipif + * @param p the pbuf chain packet to send + * @return always returns ERR_OK since the serial layer does not provide return values + */ +static err_t +slipif_output(struct netif *netif, struct pbuf *p) +{ + struct slipif_priv *priv; + struct pbuf *q; + u16_t i; + u8_t c; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + LWIP_ASSERT("p != NULL", (p != NULL)); + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_output: sending %"U16_F" bytes\n", p->tot_len)); + priv = (struct slipif_priv *)netif->state; + + /* Send pbuf out on the serial I/O device. */ + /* Start with packet delimiter. */ + sio_send(SLIP_END, priv->sd); + + for (q = p; q != NULL; q = q->next) { + for (i = 0; i < q->len; i++) { + c = ((u8_t *)q->payload)[i]; + switch (c) { + case SLIP_END: + /* need to escape this byte (0xC0 -> 0xDB, 0xDC) */ + sio_send(SLIP_ESC, priv->sd); + sio_send(SLIP_ESC_END, priv->sd); + break; + case SLIP_ESC: + /* need to escape this byte (0xDB -> 0xDB, 0xDD) */ + sio_send(SLIP_ESC, priv->sd); + sio_send(SLIP_ESC_ESC, priv->sd); + break; + default: + /* normal byte - no need for escaping */ + sio_send(c, priv->sd); + break; + } + } + } + /* End with packet delimiter. */ + sio_send(SLIP_END, priv->sd); + return ERR_OK; +} + +#if LWIP_IPV4 +/** + * Send a pbuf doing the necessary SLIP encapsulation + * + * Uses the serial layer's sio_send() + * + * @param netif the lwip network interface structure for this slipif + * @param p the pbuf chain packet to send + * @param ipaddr the ip address to send the packet to (not used for slipif) + * @return always returns ERR_OK since the serial layer does not provide return values + */ +static err_t +slipif_output_v4(struct netif *netif, struct pbuf *p, const ip4_addr_t *ipaddr) +{ + LWIP_UNUSED_ARG(ipaddr); + return slipif_output(netif, p); +} +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +/** + * Send a pbuf doing the necessary SLIP encapsulation + * + * Uses the serial layer's sio_send() + * + * @param netif the lwip network interface structure for this slipif + * @param p the pbuf chain packet to send + * @param ipaddr the ip address to send the packet to (not used for slipif) + * @return always returns ERR_OK since the serial layer does not provide return values + */ +static err_t +slipif_output_v6(struct netif *netif, struct pbuf *p, const ip6_addr_t *ipaddr) +{ + LWIP_UNUSED_ARG(ipaddr); + return slipif_output(netif, p); +} +#endif /* LWIP_IPV6 */ + +/** + * Handle the incoming SLIP stream character by character + * + * @param netif the lwip network interface structure for this slipif + * @param c received character (multiple calls to this function will + * return a complete packet, NULL is returned before - used for polling) + * @return The IP packet when SLIP_END is received + */ +static struct pbuf * +slipif_rxbyte(struct netif *netif, u8_t c) +{ + struct slipif_priv *priv; + struct pbuf *t; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + + priv = (struct slipif_priv *)netif->state; + + switch (priv->state) { + case SLIP_RECV_NORMAL: + switch (c) { + case SLIP_END: + if (priv->recved > 0) { + /* Received whole packet. */ + /* Trim the pbuf to the size of the received packet. */ + pbuf_realloc(priv->q, priv->recved); + + LINK_STATS_INC(link.recv); + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif: Got packet (%"U16_F" bytes)\n", priv->recved)); + t = priv->q; + priv->p = priv->q = NULL; + priv->i = priv->recved = 0; + return t; + } + return NULL; + case SLIP_ESC: + priv->state = SLIP_RECV_ESCAPE; + return NULL; + default: + break; + } /* end switch (c) */ + break; + case SLIP_RECV_ESCAPE: + /* un-escape END or ESC bytes, leave other bytes + (although that would be a protocol error) */ + switch (c) { + case SLIP_ESC_END: + c = SLIP_END; + break; + case SLIP_ESC_ESC: + c = SLIP_ESC; + break; + default: + break; + } + priv->state = SLIP_RECV_NORMAL; + break; + default: + break; + } /* end switch (priv->state) */ + + /* byte received, packet not yet completely received */ + if (priv->p == NULL) { + /* allocate a new pbuf */ + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: alloc\n")); + priv->p = pbuf_alloc(PBUF_LINK, (PBUF_POOL_BUFSIZE - PBUF_LINK_HLEN - PBUF_LINK_ENCAPSULATION_HLEN), PBUF_POOL); + + if (priv->p == NULL) { + LINK_STATS_INC(link.drop); + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_input: no new pbuf! (DROP)\n")); + /* don't process any further since we got no pbuf to receive to */ + return NULL; + } + + if (priv->q != NULL) { + /* 'chain' the pbuf to the existing chain */ + pbuf_cat(priv->q, priv->p); + } else { + /* p is the first pbuf in the chain */ + priv->q = priv->p; + } + } + + /* this automatically drops bytes if > SLIP_MAX_SIZE */ + if ((priv->p != NULL) && (priv->recved <= SLIP_MAX_SIZE)) { + ((u8_t *)priv->p->payload)[priv->i] = c; + priv->recved++; + priv->i++; + if (priv->i >= priv->p->len) { + /* on to the next pbuf */ + priv->i = 0; + if (priv->p->next != NULL && priv->p->next->len > 0) { + /* p is a chain, on to the next in the chain */ + priv->p = priv->p->next; + } else { + /* p is a single pbuf, set it to NULL so next time a new + * pbuf is allocated */ + priv->p = NULL; + } + } + } + return NULL; +} + +/** Like slipif_rxbyte, but passes completed packets to netif->input + * + * @param netif The lwip network interface structure for this slipif + * @param c received character + */ +static void +slipif_rxbyte_input(struct netif *netif, u8_t c) +{ + struct pbuf *p; + p = slipif_rxbyte(netif, c); + if (p != NULL) { + if (netif->input(p, netif) != ERR_OK) { + pbuf_free(p); + } + } +} + +#if SLIP_USE_RX_THREAD +/** + * The SLIP input thread. + * + * Feed the IP layer with incoming packets + * + * @param nf the lwip network interface structure for this slipif + */ +static void +slipif_loop_thread(void *nf) +{ + u8_t c; + struct netif *netif = (struct netif *)nf; + struct slipif_priv *priv = (struct slipif_priv *)netif->state; + + while (1) { + if (sio_read(priv->sd, &c, 1) > 0) { + slipif_rxbyte_input(netif, c); + } + } +} +#endif /* SLIP_USE_RX_THREAD */ + +/** + * @ingroup slipif + * SLIP netif initialization + * + * Call the arch specific sio_open and remember + * the opened device in the state field of the netif. + * + * @param netif the lwip network interface structure for this slipif + * @return ERR_OK if serial line could be opened, + * ERR_MEM if no memory could be allocated, + * ERR_IF is serial line couldn't be opened + * + * @note If netif->state is interpreted as an u8_t serial port number. + * + */ +err_t +slipif_init(struct netif *netif) +{ + struct slipif_priv *priv; + u8_t sio_num; + + LWIP_ASSERT("slipif needs an input callback", netif->input != NULL); + + /* netif->state contains serial port number */ + sio_num = LWIP_PTR_NUMERIC_CAST(u8_t, netif->state); + + LWIP_DEBUGF(SLIP_DEBUG, ("slipif_init: netif->num=%"U16_F"\n", (u16_t)sio_num)); + + /* Allocate private data */ + priv = (struct slipif_priv *)mem_malloc(sizeof(struct slipif_priv)); + if (!priv) { + return ERR_MEM; + } + + netif->name[0] = 's'; + netif->name[1] = 'l'; +#if LWIP_IPV4 + netif->output = slipif_output_v4; +#endif /* LWIP_IPV4 */ +#if LWIP_IPV6 + netif->output_ip6 = slipif_output_v6; +#endif /* LWIP_IPV6 */ + netif->mtu = SLIP_MAX_SIZE; + + /* Try to open the serial port. */ + priv->sd = sio_open(sio_num); + if (!priv->sd) { + /* Opening the serial port failed. */ + mem_free(priv); + return ERR_IF; + } + + /* Initialize private data */ + priv->p = NULL; + priv->q = NULL; + priv->state = SLIP_RECV_NORMAL; + priv->i = 0; + priv->recved = 0; +#if SLIP_RX_FROM_ISR + priv->rxpackets = NULL; +#endif + + netif->state = priv; + + /* initialize the snmp variables and counters inside the struct netif */ + MIB2_INIT_NETIF(netif, snmp_ifType_slip, SLIP_SIO_SPEED(priv->sd)); + +#if SLIP_USE_RX_THREAD + /* Create a thread to poll the serial line. */ + sys_thread_new(SLIPIF_THREAD_NAME, slipif_loop_thread, netif, + SLIPIF_THREAD_STACKSIZE, SLIPIF_THREAD_PRIO); +#endif /* SLIP_USE_RX_THREAD */ + return ERR_OK; +} + +/** + * @ingroup slipif + * Polls the serial device and feeds the IP layer with incoming packets. + * + * @param netif The lwip network interface structure for this slipif + */ +void +slipif_poll(struct netif *netif) +{ + u8_t c; + struct slipif_priv *priv; + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + + priv = (struct slipif_priv *)netif->state; + + while (sio_tryread(priv->sd, &c, 1) > 0) { + slipif_rxbyte_input(netif, c); + } +} + +#if SLIP_RX_FROM_ISR +/** + * @ingroup slipif + * Feeds the IP layer with incoming packets that were receive + * + * @param netif The lwip network interface structure for this slipif + */ +void +slipif_process_rxqueue(struct netif *netif) +{ + struct slipif_priv *priv; + SYS_ARCH_DECL_PROTECT(old_level); + + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + + priv = (struct slipif_priv *)netif->state; + + SYS_ARCH_PROTECT(old_level); + while (priv->rxpackets != NULL) { + struct pbuf *p = priv->rxpackets; +#if SLIP_RX_QUEUE + /* dequeue packet */ + struct pbuf *q = p; + while ((q->len != q->tot_len) && (q->next != NULL)) { + q = q->next; + } + priv->rxpackets = q->next; + q->next = NULL; +#else /* SLIP_RX_QUEUE */ + priv->rxpackets = NULL; +#endif /* SLIP_RX_QUEUE */ + SYS_ARCH_UNPROTECT(old_level); + if (netif->input(p, netif) != ERR_OK) { + pbuf_free(p); + } + SYS_ARCH_PROTECT(old_level); + } + SYS_ARCH_UNPROTECT(old_level); +} + +/** Like slipif_rxbyte, but queues completed packets. + * + * @param netif The lwip network interface structure for this slipif + * @param data Received serial byte + */ +static void +slipif_rxbyte_enqueue(struct netif *netif, u8_t data) +{ + struct pbuf *p; + struct slipif_priv *priv = (struct slipif_priv *)netif->state; + SYS_ARCH_DECL_PROTECT(old_level); + + p = slipif_rxbyte(netif, data); + if (p != NULL) { + SYS_ARCH_PROTECT(old_level); + if (priv->rxpackets != NULL) { +#if SLIP_RX_QUEUE + /* queue multiple pbufs */ + struct pbuf *q = p; + while (q->next != NULL) { + q = q->next; + } + q->next = p; + } else { +#else /* SLIP_RX_QUEUE */ + pbuf_free(priv->rxpackets); + } + { +#endif /* SLIP_RX_QUEUE */ + priv->rxpackets = p; + } + SYS_ARCH_UNPROTECT(old_level); + } +} + +/** + * @ingroup slipif + * Process a received byte, completed packets are put on a queue that is + * fed into IP through slipif_process_rxqueue(). + * + * This function can be called from ISR if SYS_LIGHTWEIGHT_PROT is enabled. + * + * @param netif The lwip network interface structure for this slipif + * @param data received character + */ +void +slipif_received_byte(struct netif *netif, u8_t data) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + slipif_rxbyte_enqueue(netif, data); +} + +/** + * @ingroup slipif + * Process multiple received byte, completed packets are put on a queue that is + * fed into IP through slipif_process_rxqueue(). + * + * This function can be called from ISR if SYS_LIGHTWEIGHT_PROT is enabled. + * + * @param netif The lwip network interface structure for this slipif + * @param data received character + * @param len Number of received characters + */ +void +slipif_received_bytes(struct netif *netif, u8_t *data, u8_t len) +{ + u8_t i; + u8_t *rxdata = data; + LWIP_ASSERT("netif != NULL", (netif != NULL)); + LWIP_ASSERT("netif->state != NULL", (netif->state != NULL)); + + for (i = 0; i < len; i++, rxdata++) { + slipif_rxbyte_enqueue(netif, *rxdata); + } +} +#endif /* SLIP_RX_FROM_ISR */ diff --git a/Middlewares/Third_Party/LwIP/src/netif/zepif.c b/Middlewares/Third_Party/LwIP/src/netif/zepif.c new file mode 100644 index 0000000..b403303 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/src/netif/zepif.c @@ -0,0 +1,300 @@ +/** + * @file + * + * @defgroup zepif ZEP - ZigBee Encapsulation Protocol + * @ingroup netifs + * A netif implementing the ZigBee Encapsulation Protocol (ZEP). + * This is used to tunnel 6LowPAN over UDP. + * + * Usage (there must be a default netif before!): + * @code{.c} + * netif_add(&zep_netif, NULL, NULL, NULL, NULL, zepif_init, tcpip_6lowpan_input); + * netif_create_ip6_linklocal_address(&zep_netif, 1); + * netif_set_up(&zep_netif); + * netif_set_link_up(&zep_netif); + * @endcode + */ + +/* + * Copyright (c) 2018 Simon Goldschmidt + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ + +#include "netif/zepif.h" + +#if LWIP_IPV6 && LWIP_UDP + +#include "netif/lowpan6.h" +#include "lwip/udp.h" +#include "lwip/timeouts.h" +#include + +/** Define this to 1 to loop back TX packets for testing */ +#ifndef ZEPIF_LOOPBACK +#define ZEPIF_LOOPBACK 0 +#endif + +#define ZEP_MAX_DATA_LEN 127 + +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/bpstruct.h" +#endif +PACK_STRUCT_BEGIN +struct zep_hdr { + PACK_STRUCT_FLD_8(u8_t prot_id[2]); + PACK_STRUCT_FLD_8(u8_t prot_version); + PACK_STRUCT_FLD_8(u8_t type); + PACK_STRUCT_FLD_8(u8_t channel_id); + PACK_STRUCT_FIELD(u16_t device_id); + PACK_STRUCT_FLD_8(u8_t crc_mode); + PACK_STRUCT_FLD_8(u8_t unknown_1); + PACK_STRUCT_FIELD(u32_t timestamp[2]); + PACK_STRUCT_FIELD(u32_t seq_num); + PACK_STRUCT_FLD_8(u8_t unknown_2[10]); + PACK_STRUCT_FLD_8(u8_t len); +} PACK_STRUCT_STRUCT; +PACK_STRUCT_END +#ifdef PACK_STRUCT_USE_INCLUDES +# include "arch/epstruct.h" +#endif + +struct zepif_state { + struct zepif_init init; + struct udp_pcb *pcb; + u32_t seqno; +}; + +static u8_t zep_lowpan_timer_running; + +/* Helper function that calls the 6LoWPAN timer and reschedules itself */ +static void +zep_lowpan_timer(void *arg) +{ + lowpan6_tmr(); + if (zep_lowpan_timer_running) { + sys_timeout(LOWPAN6_TMR_INTERVAL, zep_lowpan_timer, arg); + } +} + +/* Pass received pbufs into 6LowPAN netif */ +static void +zepif_udp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr, u16_t port) +{ + err_t err; + struct netif *netif_lowpan6 = (struct netif *)arg; + struct zep_hdr *zep; + + LWIP_ASSERT("arg != NULL", arg != NULL); + LWIP_ASSERT("pcb != NULL", pcb != NULL); + LWIP_UNUSED_ARG(pcb); /* for LWIP_NOASSERT */ + LWIP_UNUSED_ARG(addr); + LWIP_UNUSED_ARG(port); + if (p == NULL) { + return; + } + + /* Parse and hide the ZEP header */ + if (p->len < sizeof(struct zep_hdr)) { + /* need the zep_hdr in one piece */ + goto err_return; + } + zep = (struct zep_hdr *)p->payload; + if (zep->prot_id[0] != 'E') { + goto err_return; + } + if (zep->prot_id[1] != 'X') { + goto err_return; + } + if (zep->prot_version != 2) { + /* we only support this version for now */ + goto err_return; + } + if (zep->type != 1) { + goto err_return; + } + if (zep->crc_mode != 1) { + goto err_return; + } + if (zep->len != p->tot_len - sizeof(struct zep_hdr)) { + goto err_return; + } + /* everything seems to be OK, hide the ZEP header */ + if (pbuf_remove_header(p, sizeof(struct zep_hdr))) { + goto err_return; + } + /* TODO Check CRC? */ + /* remove CRC trailer */ + pbuf_realloc(p, p->tot_len - 2); + + /* Call into 6LoWPAN code. */ + err = netif_lowpan6->input(p, netif_lowpan6); + if (err == ERR_OK) { + return; + } +err_return: + pbuf_free(p); +} + +/* Send 6LoWPAN TX packets as UDP broadcast */ +static err_t +zepif_linkoutput(struct netif *netif, struct pbuf *p) +{ + err_t err; + struct pbuf *q; + struct zep_hdr *zep; + struct zepif_state *state; + + LWIP_ASSERT("invalid netif", netif != NULL); + LWIP_ASSERT("invalid pbuf", p != NULL); + + if (p->tot_len > ZEP_MAX_DATA_LEN) { + return ERR_VAL; + } + LWIP_ASSERT("TODO: support chained pbufs", p->next == NULL); + + state = (struct zepif_state *)netif->state; + LWIP_ASSERT("state->pcb != NULL", state->pcb != NULL); + + q = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct zep_hdr) + p->tot_len, PBUF_RAM); + if (q == NULL) { + return ERR_MEM; + } + zep = (struct zep_hdr *)q->payload; + memset(zep, 0, sizeof(struct zep_hdr)); + zep->prot_id[0] = 'E'; + zep->prot_id[1] = 'X'; + zep->prot_version = 2; + zep->type = 1; /* Data */ + zep->channel_id = 0; /* whatever */ + zep->device_id = lwip_htons(1); /* whatever */ + zep->crc_mode = 1; + zep->unknown_1 = 0xff; + zep->seq_num = lwip_htonl(state->seqno); + state->seqno++; + zep->len = (u8_t)p->tot_len; + + err = pbuf_take_at(q, p->payload, p->tot_len, sizeof(struct zep_hdr)); + if (err == ERR_OK) { +#if ZEPIF_LOOPBACK + zepif_udp_recv(netif, state->pcb, pbuf_clone(PBUF_RAW, PBUF_RAM, q), NULL, 0); +#endif + err = udp_sendto(state->pcb, q, state->init.zep_dst_ip_addr, state->init.zep_dst_udp_port); + } + pbuf_free(q); + + return err; +} + +/** + * @ingroup zepif + * Set up a raw 6LowPAN netif and surround it with input- and output + * functions for ZEP + */ +err_t +zepif_init(struct netif *netif) +{ + err_t err; + struct zepif_init *init_state = (struct zepif_init *)netif->state; + struct zepif_state *state = (struct zepif_state *)mem_malloc(sizeof(struct zepif_state)); + + LWIP_ASSERT("zepif needs an input callback", netif->input != NULL); + + if (state == NULL) { + return ERR_MEM; + } + memset(state, 0, sizeof(struct zepif_state)); + if (init_state != NULL) { + memcpy(&state->init, init_state, sizeof(struct zepif_init)); + } + if (state->init.zep_src_udp_port == 0) { + state->init.zep_src_udp_port = ZEPIF_DEFAULT_UDP_PORT; + } + if (state->init.zep_dst_udp_port == 0) { + state->init.zep_dst_udp_port = ZEPIF_DEFAULT_UDP_PORT; + } +#if LWIP_IPV4 + if (state->init.zep_dst_ip_addr == NULL) { + /* With IPv4 enabled, default to broadcasting packets if no address is set */ + state->init.zep_dst_ip_addr = IP_ADDR_BROADCAST; + } +#endif /* LWIP_IPV4 */ + + netif->state = NULL; + + state->pcb = udp_new_ip_type(IPADDR_TYPE_ANY); + if (state->pcb == NULL) { + err = ERR_MEM; + goto err_ret; + } + err = udp_bind(state->pcb, state->init.zep_src_ip_addr, state->init.zep_src_udp_port); + if (err != ERR_OK) { + goto err_ret; + } + if (state->init.zep_netif != NULL) { + udp_bind_netif(state->pcb, state->init.zep_netif); + } + LWIP_ASSERT("udp_bind(lowpan6_broadcast_pcb) failed", err == ERR_OK); + ip_set_option(state->pcb, SOF_BROADCAST); + udp_recv(state->pcb, zepif_udp_recv, netif); + + err = lowpan6_if_init(netif); + LWIP_ASSERT("lowpan6_if_init set a state", netif->state == NULL); + if (err == ERR_OK) { + netif->state = state; + netif->hwaddr_len = 6; + if (init_state != NULL) { + memcpy(netif->hwaddr, init_state->addr, 6); + } else { + u8_t i; + for (i = 0; i < 6; i++) { + netif->hwaddr[i] = i; + } + netif->hwaddr[0] &= 0xfc; + } + netif->linkoutput = zepif_linkoutput; + + if (!zep_lowpan_timer_running) { + sys_timeout(LOWPAN6_TMR_INTERVAL, zep_lowpan_timer, NULL); + zep_lowpan_timer_running = 1; + } + + return ERR_OK; + } + +err_ret: + if (state->pcb != NULL) { + udp_remove(state->pcb); + } + mem_free(state); + return err; +} + +#endif /* LWIP_IPV6 && LWIP_UDP */ diff --git a/Middlewares/Third_Party/LwIP/system/arch/bpstruct.h b/Middlewares/Third_Party/LwIP/system/arch/bpstruct.h new file mode 100644 index 0000000..177758c --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/bpstruct.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma pack(1) +#endif + diff --git a/Middlewares/Third_Party/LwIP/system/arch/cc.h b/Middlewares/Third_Party/LwIP/system/arch/cc.h new file mode 100644 index 0000000..3065318 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/cc.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __CC_H__ +#define __CC_H__ + +#include "cpu.h" +#include +#include + +typedef int sys_prot_t; + +#define LWIP_PROVIDE_ERRNO + +#if defined (__GNUC__) & !defined (__CC_ARM) + +#define LWIP_TIMEVAL_PRIVATE 0 +#include + +#endif + +/* define compiler specific symbols */ +#if defined (__ICCARM__) + +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x +#define PACK_STRUCT_USE_INCLUDES + +#elif defined (__GNUC__) + +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_STRUCT __attribute__ ((__packed__)) +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x + +#elif defined (__CC_ARM) + +#define PACK_STRUCT_BEGIN __packed +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x + +#elif defined (__TASKING__) + +#define PACK_STRUCT_BEGIN +#define PACK_STRUCT_STRUCT +#define PACK_STRUCT_END +#define PACK_STRUCT_FIELD(x) x + +#endif + +#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \ + x, __LINE__, __FILE__); } while(0) + +/* Define random number generator function */ +#define LWIP_RAND() ((u32_t)rand()) + +#endif /* __CC_H__ */ diff --git a/Middlewares/Third_Party/LwIP/system/arch/cpu.h b/Middlewares/Third_Party/LwIP/system/arch/cpu.h new file mode 100644 index 0000000..bfdf881 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/cpu.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __CPU_H__ +#define __CPU_H__ + +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +#endif /* __CPU_H__ */ diff --git a/Middlewares/Third_Party/LwIP/system/arch/epstruct.h b/Middlewares/Third_Party/LwIP/system/arch/epstruct.h new file mode 100644 index 0000000..1e1a049 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/epstruct.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#if defined(__IAR_SYSTEMS_ICC__) +#pragma pack() +#endif + diff --git a/Middlewares/Third_Party/LwIP/system/arch/init.h b/Middlewares/Third_Party/LwIP/system/arch/init.h new file mode 100644 index 0000000..e622c73 --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/init.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __ARCH_INIT_H__ +#define __ARCH_INIT_H__ + +#define TCPIP_INIT_DONE(arg) tcpip_init_done(arg) + +void tcpip_init_done(void *); +int wait_for_tcpip_init(void); + +#endif /* __ARCH_INIT_H__ */ + + + + diff --git a/Middlewares/Third_Party/LwIP/system/arch/lib.h b/Middlewares/Third_Party/LwIP/system/arch/lib.h new file mode 100644 index 0000000..378f25b --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/lib.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LIB_H__ +#define __LIB_H__ + +#include + + +#endif /* __LIB_H__ */ diff --git a/Middlewares/Third_Party/LwIP/system/arch/perf.h b/Middlewares/Third_Party/LwIP/system/arch/perf.h new file mode 100644 index 0000000..334d42a --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/perf.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START /* null definition */ +#define PERF_STOP(x) /* null definition */ + +#endif /* __PERF_H__ */ diff --git a/Middlewares/Third_Party/LwIP/system/arch/sys_arch.h b/Middlewares/Third_Party/LwIP/system/arch/sys_arch.h new file mode 100644 index 0000000..49bfd4e --- /dev/null +++ b/Middlewares/Third_Party/LwIP/system/arch/sys_arch.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __SYS_ARCH_H__ +#define __SYS_ARCH_H__ + +#include "lwip/opt.h" + +#if (NO_SYS != 0) +#error "NO_SYS need to be set to 0 to use threaded API" +#endif + +#include "cmsis_os.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if (osCMSIS < 0x20000U) + +#define SYS_MBOX_NULL (osMessageQId)0 +#define SYS_SEM_NULL (osSemaphoreId)0 + +typedef osSemaphoreId sys_sem_t; +typedef osSemaphoreId sys_mutex_t; +typedef osMessageQId sys_mbox_t; +typedef osThreadId sys_thread_t; +#else + +#define SYS_MBOX_NULL (osMessageQueueId_t)0 +#define SYS_SEM_NULL (osSemaphoreId_t)0 + +typedef osSemaphoreId_t sys_sem_t; +typedef osSemaphoreId_t sys_mutex_t; +typedef osMessageQueueId_t sys_mbox_t; +typedef osThreadId_t sys_thread_t; +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_ARCH_H__ */ + diff --git a/STM32H723VGHX_FLASH.ld b/STM32H723VGHX_FLASH.ld new file mode 100644 index 0000000..362840c --- /dev/null +++ b/STM32H723VGHX_FLASH.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7 series +** 1024Kbytes FLASH and 560Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 320K + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 32K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM_D1 AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM_D1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM_D1 + + /* Modification start */ + .lwip_sec (NOLOAD) : + { + . = ABSOLUTE(0x30000000); + *(.RxDecripSection) + + . = ABSOLUTE(0x30000100); + *(.TxDecripSection) + } >RAM_D2 + /* Modification end */ + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/STM32H723VGHX_RAM.ld b/STM32H723VGHX_RAM.ld new file mode 100644 index 0000000..b00b194 --- /dev/null +++ b/STM32H723VGHX_RAM.ld @@ -0,0 +1,173 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld (debug in RAM dedicated) +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7 series +** 320Kbytes RAM_EXEC and 240Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2023 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + RAM_EXEC (xrw) : ORIGIN = 0x24000000, LENGTH = 320K + DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 32K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 16K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into RAM_EXEC */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM_EXEC + + /* The program code and other data goes into RAM_EXEC */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM_EXEC + + /* Constant data goes into RAM_EXEC */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM_EXEC + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >RAM_EXEC + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >RAM_EXEC + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >RAM_EXEC + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >RAM_EXEC + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >RAM_EXEC + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >DTCMRAM AT> RAM_EXEC + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >DTCMRAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >DTCMRAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/lwip_test Debug.launch b/lwip_test Debug.launch new file mode 100644 index 0000000..b15ee9b --- /dev/null +++ b/lwip_test Debug.launch @@ -0,0 +1,93 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lwip_test.ioc b/lwip_test.ioc new file mode 100644 index 0000000..a09c8a3 --- /dev/null +++ b/lwip_test.ioc @@ -0,0 +1,250 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_FULL_ACCESS +CORTEX_M7.AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_FULL_ACCESS +CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=0x30000000 +CORTEX_M7.BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=0x30000000 +CORTEX_M7.CPU_DCache=Enabled +CORTEX_M7.CPU_ICache=Enabled +CORTEX_M7.DisableExec_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_INSTRUCTION_ACCESS_DISABLE +CORTEX_M7.DisableExec_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_INSTRUCTION_ACCESS_DISABLE +CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_ENABLE +CORTEX_M7.Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_ENABLE +CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,Enable_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,TypeExtField_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,DisableExec_S-Cortex_Memory_Protection_Unit_Region1_Settings_S,Enable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,BaseAddress_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,AccessPermission_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,DisableExec_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsShareable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S,IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S +CORTEX_M7.IsBufferable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_BUFFERABLE +CORTEX_M7.IsShareable_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_ACCESS_SHAREABLE +CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_REGION_SIZE_32KB +CORTEX_M7.Size_S-Cortex_Memory_Protection_Unit_Region2_Settings_S=MPU_REGION_SIZE_512B +CORTEX_M7.TypeExtField_S-Cortex_Memory_Protection_Unit_Region1_Settings_S=MPU_TEX_LEVEL1 +ETH.IPParameters=MediaInterface,TxDescAddress +ETH.MediaInterface=HAL_ETH_RMII_MODE +ETH.TxDescAddress=0x30000100 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +LWIP.BSP.number=1 +LWIP.IPParameters=MEM_SIZE,LWIP_RAM_HEAP_POINTER,LWIP_DHCP,IP_ADDRESS,NETMASK_ADDRESS +LWIP.IP_ADDRESS=192.168.000.120 +LWIP.LWIP_DHCP=0 +LWIP.LWIP_RAM_HEAP_POINTER=0x30000200 +LWIP.MEM_SIZE=32232 +LWIP.NETMASK_ADDRESS=255.255.255.000 +LWIP.Version=v2.1.2_Cube +LWIP0.BSP.STBoard=false +LWIP0.BSP.api=BSP_COMPONENT_DRIVER +LWIP0.BSP.component=LAN8742 +LWIP0.BSP.condition= +LWIP0.BSP.instance=LAN8742 +LWIP0.BSP.ip= +LWIP0.BSP.mode= +LWIP0.BSP.name=Driver_PHY +LWIP0.BSP.semaphore=S_LAN8742 +LWIP0.BSP.solution=LAN8742 +Mcu.CPN=STM32H723VGH6 +Mcu.Family=STM32H7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=DEBUG +Mcu.IP2=ETH +Mcu.IP3=LWIP +Mcu.IP4=NVIC +Mcu.IP5=RCC +Mcu.IP6=SYS +Mcu.IPNb=7 +Mcu.Name=STM32H723VGHx +Mcu.Package=TFBGA100 +Mcu.Pin0=PB3(JTDO/TRACESWO) +Mcu.Pin1=PA14(JTCK/SWCLK) +Mcu.Pin10=PB13 +Mcu.Pin11=PA7 +Mcu.Pin12=PB11 +Mcu.Pin13=PB12 +Mcu.Pin14=VP_LWIP_VS_Enabled +Mcu.Pin15=VP_SYS_VS_Systick +Mcu.Pin2=PA13(JTMS/SWDIO) +Mcu.Pin3=PH0-OSC_IN +Mcu.Pin4=PH1-OSC_OUT +Mcu.Pin5=PC1 +Mcu.Pin6=PC4 +Mcu.Pin7=PA1 +Mcu.Pin8=PC5 +Mcu.Pin9=PA2 +Mcu.PinsNb=16 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32H723VGHx +MxCube.Version=6.10.0 +MxDb.Version=DB.6.0.100 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ETH_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA1.GPIOParameters=GPIO_Speed +PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA13(JTMS/SWDIO).Mode=Trace_Asynchronous_SW +PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO +PA14(JTCK/SWCLK).Mode=Trace_Asynchronous_SW +PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK +PA2.GPIOParameters=GPIO_Speed +PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA7.GPIOParameters=GPIO_Speed +PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PB11.GPIOParameters=GPIO_Speed +PB11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB11.Mode=RMII +PB11.Signal=ETH_TX_EN +PB12.GPIOParameters=GPIO_Speed +PB12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB12.Mode=RMII +PB12.Signal=ETH_TXD0 +PB13.GPIOParameters=GPIO_Speed +PB13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PB3(JTDO/TRACESWO).Mode=Trace_Asynchronous_SW +PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO +PC1.GPIOParameters=GPIO_Speed +PC1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC4.GPIOParameters=GPIO_Speed +PC4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.GPIOParameters=GPIO_Speed +PC5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PH0-OSC_IN.Mode=HSE-External-Oscillator +PH0-OSC_IN.Signal=RCC_OSC_IN +PH1-OSC_OUT.Mode=HSE-External-Oscillator +PH1-OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.CurrentBGAView=Top +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32H723VGHx +ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.1 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=lwip_test.ioc +ProjectManager.ProjectName=lwip_test +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=STM32CubeIDE +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.ADCFreq_Value=50390625 +RCC.AHB12Freq_Value=240000000 +RCC.AHB4Freq_Value=240000000 +RCC.APB1Freq_Value=120000000 +RCC.APB2Freq_Value=120000000 +RCC.APB3Freq_Value=120000000 +RCC.APB4Freq_Value=120000000 +RCC.AXIClockFreq_Value=240000000 +RCC.CECFreq_Value=32000 +RCC.CKPERFreq_Value=64000000 +RCC.CortexFreq_Value=480000000 +RCC.CpuClockFreq_Value=480000000 +RCC.D1CPREFreq_Value=480000000 +RCC.D1PPRE=RCC_APB3_DIV2 +RCC.D2PPRE1=RCC_APB1_DIV2 +RCC.D2PPRE2=RCC_APB2_DIV2 +RCC.D3PPRE=RCC_APB4_DIV2 +RCC.DFSDMACLkFreq_Value=240000000 +RCC.DFSDMFreq_Value=120000000 +RCC.DIVM1=5 +RCC.DIVN1=96 +RCC.DIVP1=1 +RCC.DIVP1Freq_Value=480000000 +RCC.DIVP2Freq_Value=50390625 +RCC.DIVP3Freq_Value=50390625 +RCC.DIVQ1Freq_Value=240000000 +RCC.DIVQ2Freq_Value=50390625 +RCC.DIVQ3Freq_Value=50390625 +RCC.DIVR1Freq_Value=240000000 +RCC.DIVR2Freq_Value=50390625 +RCC.DIVR3Freq_Value=50390625 +RCC.FDCANFreq_Value=240000000 +RCC.FMCFreq_Value=240000000 +RCC.FamilyName=M +RCC.HCLK3ClockFreq_Value=240000000 +RCC.HCLKFreq_Value=240000000 +RCC.HPRE=RCC_HCLK_DIV2 +RCC.I2C123Freq_Value=120000000 +RCC.I2C4Freq_Value=120000000 +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.LPTIM1Freq_Value=120000000 +RCC.LPTIM2Freq_Value=120000000 +RCC.LPTIM345Freq_Value=120000000 +RCC.LPUART1Freq_Value=120000000 +RCC.LTDCFreq_Value=50390625 +RCC.MCO1PinFreq_Value=64000000 +RCC.MCO2PinFreq_Value=480000000 +RCC.PLLFRACN=0 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.QSPIFreq_Value=240000000 +RCC.RNGFreq_Value=48000000 +RCC.RTCFreq_Value=32000 +RCC.SAI1Freq_Value=240000000 +RCC.SAI4AFreq_Value=240000000 +RCC.SAI4BFreq_Value=240000000 +RCC.SDMMCFreq_Value=240000000 +RCC.SPDIFRXFreq_Value=240000000 +RCC.SPI123Freq_Value=240000000 +RCC.SPI45Freq_Value=120000000 +RCC.SPI6Freq_Value=120000000 +RCC.SWPMI1Freq_Value=120000000 +RCC.SYSCLKFreq_VALUE=480000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.Tim1OutputFreq_Value=240000000 +RCC.Tim2OutputFreq_Value=240000000 +RCC.TraceFreq_Value=240000000 +RCC.USART16Freq_Value=120000000 +RCC.USART234578Freq_Value=120000000 +RCC.USBFreq_Value=240000000 +RCC.VCO1OutputFreq_Value=480000000 +RCC.VCO2OutputFreq_Value=100781250 +RCC.VCO3OutputFreq_Value=100781250 +RCC.VCOInput1Freq_Value=5000000 +RCC.VCOInput2Freq_Value=781250 +RCC.VCOInput3Freq_Value=781250 +VP_LWIP_VS_Enabled.Mode=Enabled +VP_LWIP_VS_Enabled.Signal=LWIP_VS_Enabled +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom +isbadioc=false